; -------------------------------------------------------------------------------- ; @Title: IMX8X On-Chip Peripherals ; @Props: Released ; @Author: KMW, KOF, BUM, DOR, BAN, CEZ, KRZ, PAM, MIC, DPR, MRO, JUS, DAS ; @Changelog: 2019-01-07 KMW ; 2019-10-31 DOR ; 2019-11-28 MRO ; 2020-02-21 DAS ; @Manufacturer: NXP - NXP Semiconductors ; @Doc: IMX8DQXPRM_Rev_A.pdf (Rev. A, 2017-06) ; IMX8DQXP_RM_Rev_D.pdf (Rev. D, 2018-11) ; PCI_Express_Base_Specification_Revision_3.0.pdf (Rev. 3.0, 2010-11-10) ; IMX8DQXPRM.pdf (Rev. E, 2019-06) ; @Core: Cortex-A35, Cortex-M4F ; @Chip: IMX8DX, IMX8DXP, IMX8QXP, IMX8QXP-CM4, IMX8DX-CM4, IMX8QXP-SCU, ; IMX8DX-SCU, IMX8DXP-SCU, IMX8DXP-CM4 ; @Copyright: (C) 1989-2020 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perimx8x.per 17736 2024-04-08 09:26:07Z kwisniewski $ ; Known problems: ; MODULE REGISTER DESCRIPTION ; IOMUX All Base address is missing ; LMEM All Base address is missing ; OCOTP_CTRL All Base address is missing ; BCH All Base address is missing ; GPMI All Base address is missing ; USBDCD All Base address is missing ; USB2 All Base address is missing ; USB2 HWGENERAL PHYM bit is able to accept 8 states, but ; bit description contains 12 states ; USB2 PERIODICLISTBASE the same offset as in DEVICEADDR register ; USB2 ASYNCLISTADDR the same offset as in ENDPTLISTADDR register ; USB2-PHY All Base address is missing ; USB3 NC All Base address is missing ; ISI All Base address is missing ; JPEGENCWRP All Base address is missing ; JPEGDECWRP All Base address is missing ; Common Control All Base address is missing ; Command Sequencer All Base address is missing ; Pixel Engine Configuration All Base address is missing ; FETCHDECODE9 All Base address is missing ; FETCHDECODE0 All Base address is missing ; FETCHDECODE1 All Base address is missing ; FETCHWARP9 All Base address is missing ; FETCHECO9 All Base address is missing ; ROP9 All Base address is missing ; CLUT9 All Base address is missing ; MATRIX9 All Base address is missing ; HSCALER9 All Base address is missing ; VSCALER9 All Base address is missing ; FILTER9 All Base address is missing ; STORE9 All Base address is missing ; CONSTFRAME0 All Base address is missing ; EXTDST0 All Base address is missing ; CONSTFRAME4 All Base address is missing ; EXTDST4 All Base address is missing ; CONSTFRAME1 All Base address is missing ; EXTDST1 All Base address is missing ; CONSTFRAME5 All Base address is missing ; EXTDST5 All Base address is missing ; FETCHWARP2 All Base address is missing ; FETCHECO2 All Base address is missing ; FETCHECO0 All Base address is missing ; FETCHECO1 All Base address is missing ; FETCHLAYER0 All Base address is missing ; MATRIX4 All Base address is missing ; HSCALER4 All Base address is missing ; VSCALER4 All Base address is missing ; MATRIX5 All Base address is missing ; HSCALER5 All Base address is missing ; VSCALER5 All Base address is missing ; LAYERBLEND0 All Base address is missing ; LAYERBLEND1 All Base address is missing ; LAYERBLEND2 All Base address is missing ; LAYERBLEND3 All Base address is missing ; DISENGCFG All Base address is missing ; FRAMEGEN0 All Base address is missing ; MATRIX0 All Base address is missing ; GAMMACOR0 All Base address is missing ; DITHER0 All Base address is missing ; TCON0 All Base address is missing ; SIG0 All Base address is missing ; FRAMEGEN1 All Base address is missing ; MATRIX1 All Base address is missing ; GAMMACOR1 All Base address is missing ; DITHER1 All Base address is missing ; TCON1 All Base address is missing ; SIG1 All Base address is missing ; Parallel Capture All Misleading base address ; PCIe All Based on the PCI Express Base Specification 3.0 ; PCIe All Lack of PCI Express Base Specification 3.1 ; MLB MLBPC2 Two registers partially occupy the same address range (First register 0x0C, second register 0x0D) ; LPI2C MIER,SIER MIER.FEIE and SIER.AM0IE bits descriptions suggest "Enabled" state ; on assertion, possible mistakes in documentation sif (CORENAME()=="CORTEXA35") tree "Core Registers (Cortex-A35)" AUTOINDENT.ON center tree tree.open "AArch64" tree "ID Registers" rgroup.quad spr:0x30000++0x0 line.quad 0x00 "MIDR_EL1,Main ID Register" hexmask.quad.byte 0x00 24.--31. 0x01 "IMPLEMENTER,Implementer code" bitfld.quad 0x00 20.--23. "VARIANT,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 16.--19. "ARCHITECTURE,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CPUID scheme" newline hexmask.quad.word 0x00 4.--15. 0x10 "PARTNUM,Primary Part Number" bitfld.quad 0x00 0.--3. "REVISION,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.quad spr:0x30040++0x00 line.quad 0x00 "ID_AA64PFR0_EL1,AArch64 Processor Feature Register 0" bitfld.quad 0x00 24.--27. "GIC,GIC CPU interface" "Disabled,Enabled,?..." bitfld.quad 0x00 20.--23. "ADVSIMD,Advanced SIMD" "Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented" bitfld.quad 0x00 16.--19. "FP,Floating-point" "Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented" newline bitfld.quad 0x00 12.--15. "EL3H,EL3 exception handling" "Reserved,Reserved,AArch32/AArch64,?..." bitfld.quad 0x00 8.--11. "EL2H,EL2 exception handling" "Reserved,Reserved,AArch32/AArch64,?..." bitfld.quad 0x00 4.--7. "EL1H,EL1 exception handling" "Reserved,Reserved,AArch32/AArch64,?..." newline bitfld.quad 0x00 0.--3. "EL0H,EL0 exception handling" "Reserved,Reserved,AArch32/AArch64,?..." rgroup.quad spr:0x30050++0x00 line.quad 0x00 "ID_AA64DFR0_EL1,AArch64 Debug Feature Register 0" bitfld.quad 0x00 28.--31. "CTX_CMPS,Number of breakpoints that are context-aware minus 1" "Reserved,1,?..." bitfld.quad 0x00 20.--23. "WRPS,The number of watchpoints minus 1" "Reserved,Reserved,Reserved,3,?..." bitfld.quad 0x00 12.--15. "BRPS,The number of breakpoints minus 1" "Reserved,Reserved,Reserved,Reserved,Reserved,5,?..." newline bitfld.quad 0x00 8.--11. "PMUVER,Performance Monitors extension version" "Reserved,Implemented,?..." bitfld.quad 0x00 4.--7. "TRACEVER,Trace extension" "Not implemented,?..." bitfld.quad 0x00 0.--3. "DEBUGGER,Debug architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implemented,?..." rgroup.quad spr:0x30060++0x00 line.quad 0x00 "ID_AA64ISAR0_EL1,AArch64 Instruction Set Attribute Register 0" bitfld.quad 0x00 16.--19. "CRC32,CRC32" "Reserved,Implemented,?..." bitfld.quad 0x00 12.--15. "SHA2,SHA2 instructions are implemented" "Not implemented,Implemented,?..." bitfld.quad 0x00 8.--11. "SHA1,SHA1 instructions are implemented" "Not implemented,Implemented,?..." newline bitfld.quad 0x00 4.--7. "AES,AES instructions are implemented" "Not implemented,Reserved,Implemented,?..." rgroup.quad spr:0x30070++0x00 line.quad 0x00 "ID_AA64MMFR0_EL1,AArch64 Memory Model Feature Register 0" bitfld.quad 0x00 28.--31. "4KB,4KB granule supported" "Supported,?..." bitfld.quad 0x00 24.--27. "64KB,64KB granule supported" "Supported,?..." bitfld.quad 0x00 20.--23. "16KB,16KB granule supported" "Reserved,Supported,?..." newline bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..." newline bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,40 bits/1 TB,?..." rgroup.quad spr:0x30054++0x00 line.quad 0x00 "ID_AA64AFR0_EL1,AArch64 Auxiliary Feature Register 0" rgroup.quad spr:0x30055++0x00 line.quad 0x00 "ID_AA64AFR1_EL1,AArch64 Auxiliary Feature Register 1" rgroup.quad spr:0x30041++0x00 line.quad 0x00 "ID_AA64PFR1_EL1,AArch64 Processor Feature Register 1" rgroup.quad spr:0x30051++0x00 line.quad 0x00 "ID_AA64DFR1_EL1,AArch64 Debug Feature Register 1" rgroup.quad spr:0x30061++0x00 line.quad 0x00 "ID_AA64ISAR1_EL1,AArch64 Instruction Set Attribute Register 1" rgroup.quad spr:0x30071++0x00 line.quad 0x00 "ID_AA64MMFR1_EL1,AArch64 Memory Model Feature Register 1" rgroup.quad spr:0x30010++0x00 line.quad 0x00 "ID_PFR0_EL1,AArch32 Processor Feature Register 0" bitfld.quad 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..." bitfld.quad 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." newline bitfld.quad 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.quad spr:0x30011++0x00 line.quad 0x00 "ID_PFR1_EL1,AArch32 Processor Feature Register 1" bitfld.quad 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..." newline bitfld.quad 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..." newline bitfld.quad 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." rgroup.quad spr:0x30012++0x00 line.quad 0x00 "ID_DFR0_EL1,AArch32 Debug Feature Register 0" bitfld.quad 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.quad 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Not supported,Supported,?..." newline bitfld.quad 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.quad 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." rgroup.quad spr:0x30013++0x00 line.quad 0x00 "ID_AFR0_EL1,AArch32 Auxiliary Feature Register 0 EL1" rgroup.quad spr:0x30014++0x00 line.quad 0x00 "ID_MMFR0_EL1,AArch32 Memory Model Feature Register 0" bitfld.quad 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..." bitfld.quad 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..." bitfld.quad 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..." bitfld.quad 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..." bitfld.quad 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,Implemented,?..." newline bitfld.quad 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.quad 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,VMSAv7,?..." rgroup.quad spr:0x30015++0x00 line.quad 0x00 "ID_MMFR1_EL1,AArch32 Memory Model Feature Register 1" bitfld.quad 0x00 28.--31. "BTB,Indicates branch predictor management requirements" "Reserved,Reserved,Reserved,Reserved,Not required,?..." bitfld.quad 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.quad 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." newline bitfld.quad 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.quad 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.quad 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." newline bitfld.quad 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.quad 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." rgroup.quad spr:0x30016++0x00 line.quad 0x00 "ID_MMFR2_EL1,AArch32 Memory Model Feature Register 2" bitfld.quad 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..." bitfld.quad 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.quad 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." newline bitfld.quad 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.quad 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.quad spr:0x30017++0x00 line.quad 0x00 "ID_MMFR3_EL1,AArch32 Memory Model Feature Register 3" bitfld.quad 0x00 28.--31. "SS,Supersection support" "Supported,?..." bitfld.quad 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..." bitfld.quad 0x00 20.--23. "CW,Coherent walk" "Reserved,Supported,?..." newline bitfld.quad 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "HCMOSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 0.--3. "HCMOMVA,Invalidate Cache MVA Support" "Reserved,Supported,?..." rgroup.quad spr:0x30020++0x00 line.quad 0x00 "ID_ISAR0_EL1,AArch32 Instruction Set Attribute Register 0" bitfld.quad 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..." newline bitfld.quad 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..." rgroup.quad spr:0x30021++0x00 line.quad 0x00 "ID_ISAR1_EL1,AArch32 Instruction Set Attribute Register 1" bitfld.quad 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..." rgroup.quad spr:0x30022++0x00 line.quad 0x00 "ID_ISAR2_EL1,AArch32 Instruction Set Attribute Register 2" bitfld.quad 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 24.--27. "PSRI,PSR Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..." newline bitfld.quad 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.quad spr:0x30023++0x00 line.quad 0x00 "ID_ISAR3_EL1,AArch32 Instruction Set Attribute Register 3" bitfld.quad 0x00 28.--31. "TEEEI,Thumb-EE Extensions Support" "Not supported,?..." bitfld.quad 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.quad spr:0x30024++0x00 line.quad 0x00 "ID_ISAR4_EL1,AArch32 Instruction Set Attribute Register 4" bitfld.quad 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..." bitfld.quad 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..." bitfld.quad 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..." newline bitfld.quad 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.quad spr:0x30025++0x00 line.quad 0x00 "ID_ISAR5_EL1,AArch32 Instruction Set Attribute Register 5" bitfld.quad 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..." bitfld.quad 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..." newline bitfld.quad 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "SEVL,SEVL Instructions Support" "Reserved,Supported,?..." rgroup.quad spr:0x33001++0x0 line.quad 0x00 "CTR_EL0,Cache Type Register" bitfld.quad 0x00 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.quad 0x00 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.quad 0x00 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.quad 0x00 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..." bitfld.quad 0x00 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." rgroup.quad spr:0x30005++0x00 line.quad 0x00 "MPIDR_EL1,Multiprocessor Affinity Register" hexmask.quad.byte 0x00 32.--39. 1. "AFF3,Highest level affinity field" bitfld.quad 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor" bitfld.quad 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largely independent,?..." newline hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field" hexmask.quad.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Lowest level affinity field" rgroup.quad spr:0x30006++0x0 line.quad 0x00 "REVIDR_EL1,Revision ID Register" rgroup.quad spr:0x33007++0x00 line.quad 0x00 "DCZID_EL0,Data Cache Zero ID Register" bitfld.quad 0x00 4. "DZP,Prohibit the DC ZVA instruction" "Not prohibited,Prohibited" bitfld.quad 0x00 0.--3. "BS,Block Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." rgroup.quad spr:0x31007++0x00 line.quad 0x00 "AIDR_EL1,Auxiliary ID Register" group.quad spr:0x34000++0x0 line.quad 0x00 "VPIDR_EL2,Virtualization Processor ID Register" hexmask.quad.byte 0x00 24.--31. 0x01 "IMPLEMENTER,Implementer code" bitfld.quad 0x00 20.--23. "VARIANT,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 16.--19. "ARCHITECTURE,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CPUID scheme" newline hexmask.quad.word 0x00 4.--15. 0x10 "PARTNUM,Primary Part Number" bitfld.quad 0x00 0.--3. "REVISION,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.quad spr:0x34005++0x00 line.quad 0x00 "VMPIDR_EL2,Virtualization Multiprocessor ID Register" hexmask.quad.byte 0x00 32.--39. 1. "AFF3,Highest level affinity field" bitfld.quad 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor" bitfld.quad 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largely independent,?..." newline hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field" hexmask.quad.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Lowest level affinity field" tree.end tree "System Control and Configuration" group.quad spr:0x36111++0x00 line.quad 0x00 "SDER32_EL3,Secure Debug Enable Register" bitfld.quad 0x00 1. "SUNIDEN,Enable non-invasive debug features in Secure User mode" "Disabled,Enabled" bitfld.quad 0x00 0. "SUIDEN,Enable debug exceptions in Secure User mode" "Disabled,Enabled" group.quad spr:0x30100++0x0 line.quad 0x00 "SCTLR_EL1,System Control Register (EL1)" bitfld.quad 0x00 26. "UCI,EL0 access enable (DC CVAU|DC CIVAC|DC CVAC|IC IVAU)" "Disabled,Enabled" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.quad 0x00 24. "E0E,Endianness of explicit data access at EL0" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 18. "NTWE,Not trap WFE" "No,Yes" bitfld.quad 0x00 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.quad 0x00 15. "UCT,EL0 access enable (CTR_EL0)" "Disabled,Enabled" bitfld.quad 0x00 14. "DZE,EL0 access enable (DC ZVA)" "Disabled,Enabled" newline bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x00 9. "UMA,User Mask Access" "Disabled,Enabled" newline bitfld.quad 0x00 8. "SED,SETEND Disable" "No,Yes" bitfld.quad 0x00 7. "ITD,IT instruction disable" "No,Yes" newline bitfld.quad 0x00 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" bitfld.quad 0x00 4. "SA0,EL0 stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" newline bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x34100++0x0 line.quad 0x00 "SCTLR_EL2,System Control Register (EL2)" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x36100++0x0 line.quad 0x00 "SCTLR_EL3,System Control Register (EL3)" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x31F20++0x00 line.quad 0x00 "CPUACTLR_EL1,CPU Auxiliary Control Register" bitfld.quad 0x00 44. "ENDCCASCI,Enable Data Cache Clean As data cache Clean/Invalidate" "Disabled,Enabled" bitfld.quad 0x00 30. "CDIDIS,Disable Cryptographic Dual Issue" "No,Yes" newline bitfld.quad 0x00 29. "DIDIS,Disable Dual Issue" "No,Yes" bitfld.quad 0x00 27.--28. "RADIS,Write streaming no-allocate threshold" "16th,128th,512th,Disabled" newline bitfld.quad 0x00 25.--26. "L1RADIS,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled" bitfld.quad 0x00 24. "DTAH,Disable Transient allocation hint" "No,Yes" newline bitfld.quad 0x00 23. "STBPFRS,Disable ReadUnique request for prefetch streams initiated by STB accesses" "No,Yes" bitfld.quad 0x00 22. "STBPFDIS,Disable prefetch streams initiated from STB accesses" "No,Yes" newline bitfld.quad 0x00 19.--20. "NPFSTRM,Number of independent data prefetch streams" "1 stream,2 streams,3 streams,4 streams" bitfld.quad 0x00 18. "DSTDIS,Enable device split throttle" "Disabled,Enabled" newline bitfld.quad 0x00 17. "STRIDE,Configure the sequence length that triggers data prefetch streams" "2 linefills,3 linefills" bitfld.quad 0x00 13.--15. "L1PCTL,L1 Data prefetch control" "Disabled,1,2,3,4,5,6,8" newline bitfld.quad 0x00 10. "DODMBS,Disable optimized Data Memory Barrier behavior" "No,Yes" bitfld.quad 0x00 6. "L1DEIEN,L1 D-cache Data RAM Error Injection Enable" "Disabled,Enabled" group.quad spr:0x31F21++0x00 line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register" bitfld.quad 0x00 6. "SMPEN,Enable hardware management ofdata coherency with other processors in the multiprocessor" "Disabled,Enabled" bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" newline bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.quad spr:0x30101++0x0 line.quad 0x00 "ACTLR_EL1,Auxiliary Control Register (EL1)" group.quad spr:0x34101++0x0 line.quad 0x00 "ACTLR_EL2,Auxiliary Control Register (EL2)" bitfld.quad 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled" bitfld.quad 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled" newline bitfld.quad 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled" bitfld.quad 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled" newline bitfld.quad 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled" group.quad spr:0x36101++0x0 line.quad 0x00 "ACTLR_EL3,Auxiliary Control Register (EL3)" bitfld.quad 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled" bitfld.quad 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled" newline bitfld.quad 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled" bitfld.quad 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled" newline bitfld.quad 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled" group.quad spr:0x30102++0x00 line.quad 0x00 "CPACR_EL1,Architectural Feature Access Control Register" bitfld.quad 0x00 20.--21. "FPEN,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution to trap to EL1 when executed from EL0 or EL1" "EL0/EL1,EL0,EL0/EL1,Not trapped" group.quad spr:0x36110++0x0 line.quad 0x00 "SCR_EL3,Secure Configuration Register" bitfld.quad 0x00 13. "TWE,Trap WFE Instructions" "Not trapped,Trapped" bitfld.quad 0x00 12. "TWI,Trap WFI Instructions" "Not trapped,Trapped" newline bitfld.quad 0x00 11. "ST,Enable secure EL1 access" "Disabled,Enabled" bitfld.quad 0x00 10. "RW,Register width control for lower exception levels" "AArch32,AArch64" newline bitfld.quad 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted" bitfld.quad 0x00 8. "HCE,Hypervisor Call enable" "No,Yes" newline bitfld.quad 0x00 7. "SMD,Secure Monitor Call disable" "No,Yes" bitfld.quad 0x00 3. "EA,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor" newline bitfld.quad 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor" bitfld.quad 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor" newline bitfld.quad 0x00 0. "NS,Secure mode " "Secure,Non-secure" group.quad spr:0x34110++0x00 line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register" bitfld.quad 0x00 33. "ID,Stage 2 Instruction cache disable" "No,Yes" bitfld.quad 0x00 32. "CD,Stage 2 Data cache disable" "No,Yes" newline bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit" bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" newline bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled" bitfld.quad 0x00 27. "TGE,Trap General Exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled" newline bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Disabled,Enabled" bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unificiation to EL2" "Disabled,Enabled" bitfld.quad 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency tp EL2" "Disabled,Enabled" newline bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Disabled,Enabled" bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Register" "Disabled,Enabled" newline bitfld.quad 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "Disabled,Enabled" bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" newline bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" newline bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" newline bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" newline bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System" newline bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced" bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort" "Not pending,Pending" newline bitfld.quad 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending" bitfld.quad 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending" newline bitfld.quad 0x00 5. "AMO,Asynchronous abort and error interrupt routing" "Disabled,Enabled" bitfld.quad 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled" newline bitfld.quad 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled" bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" newline bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled" bitfld.quad 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled" group.quad spr:0x30510++0x00 line.quad 0x00 "AFSR0_EL1,Auxiliary Fault Status Registers 0 (EL1)" group.quad spr:0x30511++0x00 line.quad 0x00 "AFSR1_EL1,Auxiliary Fault Status Registers 1 (EL1)" group.quad spr:0x34510++0x00 line.quad 0x00 "AFSR0_EL2,Auxiliary Fault Status Registers 0 (EL2)" group.quad spr:0x34511++0x00 line.quad 0x00 "AFSR1_EL2,Auxiliary Fault Status Registers 1 (EL2)" group.quad spr:0x36510++0x00 line.quad 0x00 "AFSR0_EL3,Auxiliary Fault Status Registers 0 (EL3)" group.quad spr:0x36511++0x00 line.quad 0x00 "AFSR1_EL3,Auxiliary Fault Status Registers 1 (EL3)" tree.open "Exception Syndrome Registers" if (((per.q(spr:0x30520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((per.q(spr:0x30520))&0xFC000000)==0x04000000) if (((per.q(spr:0x30520))&0x1000000)==0x1000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" endif elif (((per.q(spr:0x30520))&0xFC000000)==(0x0C000000||0x14000000)) if (((per.q(spr:0x30520))&0x1000000)==0x1000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" endif elif (((per.q(spr:0x30520))&0xFC000000)==(0x10000000||0x30000000)) if (((per.q(spr:0x30520))&0x1000000)==0x1000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" endif elif (((per.q(spr:0x30520))&0xFC000000)==0x18000000) if (((per.q(spr:0x30520))&0x1000000)==0x1000000) if (((per.q(spr:0x30520))&0x08)==0x08) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..." newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.quad 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..." newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" endif else if (((per.q(spr:0x30520))&0x08)==0x08) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..." newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.quad 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..." newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" endif endif elif (((per.q(spr:0x30520))&0xFC000000)==0x1C000000) if (((per.q(spr:0x30520))&0x1000000)==0x1000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" endif elif (((per.q(spr:0x30520))&0xFC000000)==(0x44000000||0x54000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((per.q(spr:0x30520))&0xFC000000)==0x60000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 20.--21. "OP0,Op0 value from the issued instruction" "0,1,2,3" bitfld.quad 0x00 17.--19. "OP2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 14.--16. "OP1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x30520))&0xFC000000)==(0x80000000||0x84000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,UEO,UC,CE" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/L0/base register,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." elif (((per.q(spr:0x30520))&0xFD000000)==(0x91000000||0x95000000)) if (((per.q(spr:0x30520))&0x3F)==0x10) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,?..." else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline newline bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,?..." endif elif (((per.q(spr:0x30520))&0xFD000000)==(0x90000000||0x94000000)) if (((per.q(spr:0x30520))&0x3F)==0x10) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" newline newline newline newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,?..." else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" newline newline newline newline bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,?..." endif elif (((per.q(spr:0x30520))&0xFC800000)==(0xA0800000||0xB0800000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((per.q(spr:0x30520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((per.q(spr:0x30520))&0xFD000000)==0xBD000000) if (((per.q(spr:0x30520))&0x3F)==0x11) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 13. "IESB,Implicit Error Synchronization Barrier" "Not synchronized,Synchronized" newline bitfld.quad 0x00 10.--12. "AET,Asynchronous Error Type" "UC,UEU,UEO,UER,CE,?..." bitfld.quad 0x00 9. "EA,External abort type" "No,Yes" newline bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..." else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 9. "EA,External abort type" "No,Yes" newline newline bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..." endif elif (((per.q(spr:0x30520))&0xFD000000)==0xBC000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((per.q(spr:0x30520))&0xFC000000)==(0xC0000000||0xC4000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.q(spr:0x30520))&0xFC000000)==(0xC8000000||0xCC000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.q(spr:0x30520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.q(spr:0x30520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value" else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." endif if (((per.q(spr:0x34520))&0xFC000000)==(0x00000000||0x24000000||0x38000000||0x88000000||0x98000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((per.q(spr:0x34520))&0xFC000000)==0x04000000) if (((per.q(spr:0x34520))&0x1000000)==0x1000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" endif elif (((per.q(spr:0x34520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000)) if (((per.q(spr:0x34520))&0x1000000)==0x1000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" endif elif (((per.q(spr:0x34520))&0xFC000000)==(0x10000000||0x30000000)) if (((per.q(spr:0x34520))&0x1000000)==0x1000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" endif elif (((per.q(spr:0x34520))&0xFC000000)==0x18000000) if (((per.q(spr:0x34520))&0x1000000)==0x1000000) if (((per.q(spr:0x34520))&0x08)==0x08) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..." newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..." newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" endif else if (((per.q(spr:0x34520))&0x08)==0x08) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..." newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..." newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" endif endif elif (((per.q(spr:0x34520))&0xFC000000)==0x1C000000) if (((per.q(spr:0x34520))&0x1000000)==0x1000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" endif elif (((per.q(spr:0x34520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000||0x5C000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((per.q(spr:0x34520))&0xFC000000)==0x4C000000) if ((((per.q(spr:0x34520))&0x1000000)==0x1000000)&&(((per.q(spr:0x34520))&0xF0000)==0x80000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional" elif (((per.q(spr:0x34520))&0xF0000)==0x80000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional" else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline newline bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional" endif elif (((per.q(spr:0x34520))&0xFC000000)==0x60000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 20.--21. "OP0,Op0 value from the issued instruction" "0,1,2,3" bitfld.quad 0x00 17.--19. "OP2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 14.--16. "OP1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x34520))&0xFC000000)==0x68000000) if (((per.q(spr:0x34520))&0x02)==0x02) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 1. "ERET,Indicates whether an ERET or ERETA* instruction was trapped to EL2" "ERET,ERETA*" bitfld.quad 0x00 0. "ERETA,Indicates whether an ERETAA or ERETAB instruction was trapped to EL2" "ERETAA,ERETAB" else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 1. "ERET,Indicates whether an ERET or ERETA* instruction was trapped to EL2" "ERET,ERETA*" endif elif (((per.q(spr:0x34520))&0xFC000000)==(0x80000000||0x84000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,UEO,UC,CE" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/L0/base register,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." elif (((per.q(spr:0x34520))&0xFD000000)==(0x91000000||0x95000000)) if (((per.q(spr:0x34520))&0x3F)==0x10) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,?..." else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline newline bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,?..." endif elif (((per.q(spr:0x34520))&0xFD000000)==(0x90000000||0x94000000)) if (((per.q(spr:0x34520))&0x3F)==0x10) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" newline newline newline newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,?..." else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" newline newline newline newline bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,?..." endif elif (((per.q(spr:0x34520))&0xFC800000)==(0xA0800000||0xB0800000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((per.q(spr:0x34520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((per.q(spr:0x34520))&0xFD000000)==0xBD000000) if (((per.q(spr:0x34520))&0x3F)==0x11) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 13. "IESB,Implicit Error Synchronization Barrier" "Not synchronized,Synchronized" newline bitfld.quad 0x00 10.--12. "AET,Asynchronous Error Type" "UC,UEU,UEO,UER,CE,?..." newline bitfld.quad 0x00 9. "EA,External abort type" "No,Yes" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..." else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" newline newline bitfld.quad 0x00 9. "EA,External abort type" "No,Yes" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..." endif elif (((per.q(spr:0x34520))&0xFD000000)==0xBC000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((per.q(spr:0x34520))&0xFC000000)==(0xC0000000||0xC4000000||0xE8000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.q(spr:0x34520))&0xFC000000)==(0xC8000000||0xCC000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.q(spr:0x34520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.q(spr:0x34520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value" else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..." endif if (((per.q(spr:0x36520))&0xFC000000)==(0x00000000||0x24000000||0x38000000||0x88000000||0x98000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((per.q(spr:0x36520))&0xFC000000)==0x04000000) if (((per.q(spr:0x36520))&0x1000000)==0x1000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" endif elif (((per.q(spr:0x36520))&0xFC000000)==(0x0C000000||0x14000000)) if (((per.q(spr:0x36520))&0x1000000)==0x1000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" endif elif (((per.q(spr:0x36520))&0xFC000000)==(0x10000000||0x30000000)) if (((per.q(spr:0x36520))&0x1000000)==0x1000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" endif elif (((per.q(spr:0x36520))&0xFC000000)==0x18000000) if (((per.q(spr:0x36520))&0x1000000)==0x1000000) if (((per.q(spr:0x36520))&0x08)==0x08) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..." newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..." newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" endif else if (((per.q(spr:0x36520))&0x08)==0x08) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..." newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..." newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" endif endif elif (((per.q(spr:0x36520))&0xFC000000)==0x1C000000) if (((per.q(spr:0x36520))&0x1000000)==0x1000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" endif elif (((per.q(spr:0x36520))&0xFC000000)==0x4C000000) if ((((per.q(spr:0x36520))&0x1000000)==0x1000000)&&(((per.q(spr:0x36520))&0xF0000)==0x80000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional" elif (((per.q(spr:0x36520))&0xF0000)==0x80000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional" else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline newline bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional" endif elif (((per.q(spr:0x36520))&0xFC000000)==(0x54000000||0x58000000||0x5C000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((per.q(spr:0x36520))&0xFC000000)==0x60000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 20.--21. "OP0,Op0 value from the issued instruction" "0,1,2,3" bitfld.quad 0x00 17.--19. "OP2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 14.--16. "OP1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x36520))&0xFC000000)==0x7C000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.long 0x00 0.--24. 1. "IMPL_DEF,Implementation defined" elif (((per.q(spr:0x36520))&0xFC000000)==(0x80000000||0x84000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,UEO,UC,CE" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/L0/base register,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." elif (((per.q(spr:0x36520))&0xFD000000)==(0x91000000||0x95000000)) if (((per.q(spr:0x36520))&0x3F)==0x10) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,?..." else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline newline bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,?..." endif elif (((per.q(spr:0x36520))&0xFD000000)==(0x90000000||0x94000000)) if (((per.q(spr:0x36520))&0x3F)==0x10) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" newline newline newline newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,?..." else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" newline newline newline newline bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,?..." endif elif (((per.q(spr:0x36520))&0xFC800000)==0xB0800000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((per.q(spr:0x36520))&0xFC800000)==0xB0000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((per.q(spr:0x36520))&0xFD000000)==0xBD000000) if (((per.q(spr:0x36520))&0x3F)==0x11) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 13. "IESB,Implicit Error Synchronization Barrier" "Not synchronized,Synchronized" newline bitfld.quad 0x00 10.--12. "AET,Asynchronous Error Type" "UC,UEU,UEO,UER,CE,?..." newline bitfld.quad 0x00 9. "EA,External abort type" "No,Yes" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..." else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" newline newline bitfld.quad 0x00 9. "EA,External abort type" "No,Yes" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..." endif elif (((per.q(spr:0x36520))&0xFD000000)==0xBC000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((per.q(spr:0x36520))&0xFC000000)==0xF0000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value" else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." endif tree.end newline if (((per.q(spr:0x34501))&0x200)==0x200) group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/L1,Sync. external/on TTW/L2,Sync. external/on TTW/L3,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/L1,Sync. parity/on memory access/on TTW/L2,Sync. parity/on memory access/on TTW/L3,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." else group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/L1,Permission/section,Sync. external/on TTW/L2,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/L1,Reserved,Sync. parity/on TTW/L2,?..." endif group.quad spr:0x30600++0x00 line.quad 0x00 "FAR_EL1,Fault Address Register (EL1)" group.quad spr:0x34600++0x00 line.quad 0x00 "FAR_EL2,Fault Address Register (EL2)" group.quad spr:0x36600++0x00 line.quad 0x00 "FAR_EL3,Fault Address Register (EL3)" group.quad spr:0x34604++0x00 line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register" hexmask.quad 0x00 4.--39. 0x10 "FIPA[47:12],Bits [47:12] of the faulting intermediate physical address" group.quad spr:0x30C00++0x00 line.quad 0x00 "VBAR_EL1,Vector Base Address Register (EL1)" hexmask.quad 0x00 11.--63. 0x8 "VBA,Base address of the exception vectors for exceptions taken in this exception level" group.quad spr:0x34C00++0x00 line.quad 0x00 "VBAR_EL2,Vector Base Address Register (EL2)" hexmask.quad 0x00 11.--63. 0x8 "VBA,Base address of the exception vectors for exceptions taken in this exception level" group.quad spr:0x36C00++0x00 line.quad 0x00 "VBAR_EL3,Vector Base Address Register (EL3)" hexmask.quad 0x00 11.--63. 0x8 "VBA,Base address of the exception vectors for exceptions taken in this exception level" rgroup.quad spr:0x36C01++0x00 line.quad 0x00 "RVBAR_EL3,Reset Vector Base Address Register" group.quad spr:0x36C02++0x00 line.quad 0x00 "RMR_EL3,Reset Management Register" bitfld.quad 0x00 1. "RR,Reset Request" "Not requested,Requested" bitfld.quad 0x00 0. "AA64,Determines which execution state the processor boots into after a warmreset" "AArch32,AArch64" rgroup.quad spr:0x30C10++0x00 line.quad 0x00 "ISR_EL1,Interrupt Status Register" bitfld.quad 0x00 8. "A,External abort pending flag" "Not pending,Pending" bitfld.quad 0x00 7. "I,Interrupt pending flag" "Not pending,Pending" bitfld.quad 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending" rgroup.quad spr:0x31F30++0x00 line.quad 0x00 "CBAR_EL1,Configuration Base Address Register" hexmask.quad.tbyte 0x00 18.--39. 0x4 "PERIPHBASE[39:18],Holds the physical base address of the memory-mapped GIC CPU interface registers" group.quad spr:0x30D01++0x00 line.quad 0x00 "CONTEXTIDR_EL1,Context ID Register" group.quad spr:0x33D02++0x00 line.quad 0x00 "TPIDR_EL0,Software Thread ID Register (EL0)" group.quad spr:0x33D03++0x00 line.quad 0x00 "TPIDRRO_EL0,Read-Only Software Thread ID Register (EL0)" group.quad spr:0x30D04++0x00 line.quad 0x00 "TPIDR_EL1,Software Thread ID Register (EL1)" group.quad spr:0x34D02++0x00 line.quad 0x00 "TPIDR_EL2,Software Thread ID Register (EL2)" group.quad spr:0x36D02++0x00 line.quad 0x00 "TPIDR_EL3,Software Thread ID Register (EL3)" tree.end tree "System Instructions" wgroup.quad spr:0x10710++0x00 line.quad 0x00 "IC_IALLUIS,IC_IALLUIS" wgroup.quad spr:0x10750++0x00 line.quad 0x00 "IC_IALLU,IC_IALLU" wgroup.quad spr:0x13751++0x00 line.quad 0x00 "IC_IVAU,IC_IVAU" wgroup.quad spr:0x13741++0x00 line.quad 0x00 "DC_ZVA,DC_ZVA" wgroup.quad spr:0x10761++0x00 line.quad 0x00 "DC_IVAC,DC_IVAC" wgroup.quad spr:0x10762++0x00 line.quad 0x00 "DC_ISW,DC_ISW" wgroup.quad spr:0x137A1++0x00 line.quad 0x00 "DC_CVAC,DC_CVAC" wgroup.quad spr:0x107A2++0x00 line.quad 0x00 "DC_CSW,DC_CSW" wgroup.quad spr:0x137B1++0x00 line.quad 0x00 "DC_CVAU,DC_CVAU" wgroup.quad spr:0x137E1++0x00 line.quad 0x00 "DC_CIVAC,DC_CIVAC" wgroup.quad spr:0x107E2++0x00 line.quad 0x00 "DC_CISW,DC_CISW" wgroup.quad spr:0x10780++0x00 line.quad 0x00 "AT_S1E1R,AT_S1E1R" wgroup.quad spr:0x10781++0x00 line.quad 0x00 "AT_S1E1W,AT_S1E1W" wgroup.quad spr:0x10782++0x00 line.quad 0x00 "AT_S1E0R,AT_S1E0R" wgroup.quad spr:0x10783++0x00 line.quad 0x00 "AT_S1E0W,AT_S1E0W" wgroup.quad spr:0x14784++0x00 line.quad 0x00 "AT_S12E1R,AT_S12E1R" wgroup.quad spr:0x14785++0x00 line.quad 0x00 "AT_S12E1W,AT_S12E1W" wgroup.quad spr:0x14786++0x00 line.quad 0x00 "AT_S12E0R,AT_S12E0R" wgroup.quad spr:0x14787++0x00 line.quad 0x00 "AT_S12E0W,AT_S12E0W" wgroup.quad spr:0x14780++0x00 line.quad 0x00 "AT_S1E2R,AT_S1E2R" wgroup.quad spr:0x14781++0x00 line.quad 0x00 "AT_S1E2W,AT_S1E2W" wgroup.quad spr:0x16780++0x00 line.quad 0x00 "AT_S1E3R,AT_S1E3R" wgroup.quad spr:0x16781++0x00 line.quad 0x00 "AT_S1E3W,AT_S1E3W" wgroup.quad spr:0x10870++0x00 line.quad 0x00 "TLBI_VMALLE1,TLBI_VMALLE1" wgroup.quad spr:0x10871++0x00 line.quad 0x00 "TLBI_VAE1,TLBI_VAE1" wgroup.quad spr:0x10872++0x00 line.quad 0x00 "TLBI_ASIDE1,TLBI_ASIDE1" wgroup.quad spr:0x10873++0x00 line.quad 0x00 "TLBI_VAAE1,TLBI_VAAE1" wgroup.quad spr:0x10875++0x00 line.quad 0x00 "TLBI_VALE1,TLBI_VALE1" wgroup.quad spr:0x10877++0x00 line.quad 0x00 "TLBI_VAALE1,TLBI_VAALE1" wgroup.quad spr:0x10830++0x00 line.quad 0x00 "TLBI_VMALLE1IS,TLBI_VMALLE1IS" wgroup.quad spr:0x10831++0x00 line.quad 0x00 "TLBI_VAE1IS,TLBI_VAE1IS" wgroup.quad spr:0x10832++0x00 line.quad 0x00 "TLBI_ASIDE1IS,TLBI_ASIDE1IS" wgroup.quad spr:0x10833++0x00 line.quad 0x00 "TLBI_VAAE1IS,TLBI_VAAE1IS" wgroup.quad spr:0x10835++0x00 line.quad 0x00 "TLBI_VALE1IS,TLBI_VALE1IS" wgroup.quad spr:0x10837++0x00 line.quad 0x00 "TLBI_VAALE1IS,TLBI_VAALE1IS" wgroup.quad spr:0x14801++0x00 line.quad 0x00 "TLBI_IPAS2E1IS,TLBI_IPAS2E1IS" wgroup.quad spr:0x14805++0x00 line.quad 0x00 "TLBI_IPAS2LE1IS,TLBI_IPAS2LE1IS" wgroup.quad spr:0x14841++0x00 line.quad 0x00 "TLBI_IPAS2E1,TLBI_IPAS2E1" wgroup.quad spr:0x14845++0x00 line.quad 0x00 "TLBI_IPAS2LE1,TLBI_IPAS2LE1" wgroup.quad spr:0x14871++0x00 line.quad 0x00 "TLBI_VAE2,TLBI_VAE2" wgroup.quad spr:0x14875++0x00 line.quad 0x00 "TLBI_VALE2,TLBI_VALE2" wgroup.quad spr:0x14876++0x00 line.quad 0x00 "TLBI_VMALLS12E1,TLBI_VMALLS12E1" wgroup.quad spr:0x14831++0x00 line.quad 0x00 "TLBI_VAE2IS,TLBI_VAE2IS" wgroup.quad spr:0x14835++0x00 line.quad 0x00 "TLBI_VALE2IS,TLBI_VALE2IS" wgroup.quad spr:0x14836++0x00 line.quad 0x00 "TLBI_VMALLS12E1IS,TLBI_VMALLS12E1IS" wgroup.quad spr:0x16871++0x00 line.quad 0x00 "TLBI_VAE3,TLBI_VAE3" wgroup.quad spr:0x16875++0x00 line.quad 0x00 "TLBI_VALE3,TLBI_VALE3" wgroup.quad spr:0x16831++0x00 line.quad 0x00 "TLBI_VAE3IS,TLBI_VAE3IS" wgroup.quad spr:0x16835++0x00 line.quad 0x00 "TLBI_VALE3IS,TLBI_VALE3IS" wgroup.quad spr:0x14870++0x00 line.quad 0x00 "TLBI_ALLE2,TLBI_ALLE2" wgroup.quad spr:0x14830++0x00 line.quad 0x00 "TLBI_ALLE2IS,TLBI_ALLE2IS" wgroup.quad spr:0x14874++0x00 line.quad 0x00 "TLBI_ALLE1,TLBI_ALLE1" wgroup.quad spr:0x14834++0x00 line.quad 0x00 "TLBI_ALLE1IS,TLBI_ALLE1IS" wgroup.quad spr:0x16870++0x00 line.quad 0x00 "TLBI_ALLE3,TLBI_ALLE3" wgroup.quad spr:0x16830++0x00 line.quad 0x00 "TLBI_ALLE3IS,TLBI_ALLE3IS" tree.end tree "Memory Management Unit" group.quad spr:0x30100++0x0 line.quad 0x00 "SCTLR_EL1,System Control Register (EL1)" bitfld.quad 0x00 26. "UCI,EL0 access enable (DC CVAU|DC CIVAC|DC CVAC|IC IVAU)" "Disabled,Enabled" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.quad 0x00 24. "E0E,Endianness of explicit data access at EL0" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 18. "NTWE,Not trap WFE" "No,Yes" bitfld.quad 0x00 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.quad 0x00 15. "UCT,EL0 access enable (CTR_EL0)" "Disabled,Enabled" bitfld.quad 0x00 14. "DZE,EL0 access enable (DC ZVA)" "Disabled,Enabled" newline bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x00 9. "UMA,User Mask Access" "Disabled,Enabled" newline bitfld.quad 0x00 8. "SED,SETEND Disable" "No,Yes" bitfld.quad 0x00 7. "ITD,IT instruction disable" "No,Yes" newline bitfld.quad 0x00 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" bitfld.quad 0x00 4. "SA0,EL0 stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" newline bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x34100++0x0 line.quad 0x00 "SCTLR_EL2,System Control Register (EL2)" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x36100++0x0 line.quad 0x00 "SCTLR_EL3,System Control Register (EL3)" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x30200++0x00 line.quad 0x00 "TTBR0_EL1,Translation Table Base Register 0 (EL1)" hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 0x01 "BADDR,Translation table base address" group.quad spr:0x30201++0x00 line.quad 0x00 "TTBR1_EL1,Translation Table Base Register 1 (EL1)" hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 0x01 "BADDR,Translation table base address" group.quad spr:0x34200++0x00 line.quad 0x00 "TTBR0_EL2,Translation Table Base Register 0 (EL2)" hexmask.quad 0x00 1.--47. 0x02 "BADDR,Translation table base address" group.quad spr:0x36200++0x00 line.quad 0x00 "TTBR0_EL3,Translation Table Base Register 0 (EL3)" hexmask.quad 0x00 0.--47. 0x01 "BADDR,Translation table base address" group.quad spr:0x30202++0x00 line.quad 0x00 "TCR_EL1,Translation Control Register (EL1)" bitfld.quad 0x00 38. "TBI1,Top Byte Ignored 1" "Not ignored,Ignored" bitfld.quad 0x00 37. "TBI0,Top Byte Ignored 0" "Not ignored,Ignored" newline bitfld.quad 0x00 36. "AS,ASID size" "8-bit,16-bit" bitfld.quad 0x00 32.--34. "IPS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..." newline bitfld.quad 0x00 30.--31. "TG1,TTBR1_EL1 granule size" "Reserved,16 KB,4 KB,64 KB" bitfld.quad 0x00 28.--29. "SH1,Shareability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 26.--27. "ORGN1,Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 24.--25. "IRGN1,Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 23. "EPD1,Translation table walk disable for translations using TTBR1_EL1" "Enabled,Disabled" bitfld.quad 0x00 22. "A1,Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID" "TTBR0_EL1,TTBR1_EL1" newline bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region addressed by TTBR1_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL1 granule size" "4 KB,64 KB,16 KB,?..." newline bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 7. "EPD0,Translation table walk disable for translations using TTBR0" "Enabled,Disabled" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.quad spr:0x34202++0x00 line.quad 0x00 "TCR_EL2,Translation Control Register (EL2)" bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored" bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..." newline bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL2 granule size" "4 KB,64 KB,16 KB,?..." bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.quad spr:0x36202++0x00 line.quad 0x00 "TCR_EL3,Translation Control Register (EL3)" bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored" bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..." newline bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL3 granule size" "4 KB,64 KB,16 KB,?..." bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.quad spr:0x34300++0x00 line.quad 0x00 "DACR32_EL2,Domain Access Control Register" bitfld.quad 0x00 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager" bitfld.quad 0x00 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x00 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager" bitfld.quad 0x00 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x00 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager" bitfld.quad 0x00 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x00 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager" bitfld.quad 0x00 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x00 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager" bitfld.quad 0x00 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x00 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager" bitfld.quad 0x00 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x00 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager" bitfld.quad 0x00 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x00 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager" bitfld.quad 0x00 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager" if (((per.q(spr:0x30740))&0xF000000000000001)==0x0000000000000000) group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read" bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Device-nGnRnE,Reserved,Reserved,Reserved,Device-not nGnRnE,?..." newline hexmask.quad 0x00 12.--47. 0x10 "PA[47:12],Physical Address" bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes" newline bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" elif (((per.q(spr:0x30740))&0x01)==0x00) group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read" bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Reserved,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read" newline hexmask.quad 0x00 12.--47. 0x10 "PA[47:12],Physical Address" bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes" newline bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" else group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" newline bitfld.quad 0x00 9. "S,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2" bitfld.quad 0x00 8. "PTW,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes" newline bitfld.quad 0x00 1.--6. "FST,Fault status field" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Reserved,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,?..." newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" endif tree.open "Memory Attribute Indirection Registers" group.quad spr:0x30A20++0x00 line.quad 0x00 "MAIR_EL1,Memory Attribute Indirection Register" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate" group.quad spr:0x34A20++0x00 line.quad 0x00 "MAIR_EL2,Memory Attribute Indirection Register" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate" group.quad spr:0x36A20++0x00 line.quad 0x00 "MAIR_EL3,Memory Attribute Indirection Register" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate" group.quad spr:0x30A30++0x00 line.quad 0x00 "AMAIR_EL1,Memory Attribute Indirection Register (EL1)" group.quad spr:0x34A30++0x00 line.quad 0x00 "AMAIR_EL2,Memory Attribute Indirection Register (EL2)" group.quad spr:0x36A30++0x00 line.quad 0x00 "AMAIR_EL3,Memory Attribute Indirection Register (EL3)" tree.end newline group.quad spr:0x30D01++0x00 line.quad 0x00 "CONTEXTIDR_EL1,Context ID Register" tree.end tree "Virtualization Extensions" group.quad spr:0x34100++0x0 line.quad 0x00 "SCTLR_EL2,System Control Register (EL2)" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x34110++0x00 line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register" bitfld.quad 0x00 33. "ID,Stage 2 instruction cache disable" "No,Yes" bitfld.quad 0x00 32. "CD,Stage 2 data cache disable" "No,Yes" bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,AArch64" newline bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" bitfld.quad 0x00 28. "TDZ,Traps DC ZVA instruction" "Disabled,Enabled" bitfld.quad 0x00 27. "TGE,Trap General Exceptions" "Disabled,Enabled" newline bitfld.quad 0x00 26. "TVM,Trap Virtual Memory Controls" "Disabled,Enabled" bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions" "Disabled,Enabled" bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled" newline bitfld.quad 0x00 23. "TPC,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled" bitfld.quad 0x00 22. "TSW,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled" bitfld.quad 0x00 21. "TAC,Trap Auxiliary Control Register Accesses" "Disabled,Enabled" newline bitfld.quad 0x00 20. "TIDCP,Trap Lockdown" "Disabled,Enabled" bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" newline bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" newline bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" newline bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability Upgrade" "No effect,Inner Shareable,Outer Shareable,Full system" bitfld.quad 0x00 9. "FB,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled" bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort" "Not aborted,Aborted" newline bitfld.quad 0x00 7. "VI,Virtual IRQ interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 6. "VF,Virtual FIQ interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 5. "AMO,A-bit Mask Override" "Not routed,Routed" newline bitfld.quad 0x00 4. "IMO,I-bit Mask Override" "Not routed,Routed" bitfld.quad 0x00 3. "FMO,F-bit Mask Override" "Not routed,Routed" bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" newline bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override" bitfld.quad 0x00 0. "VM,Second Stage of Translation Enable" "Disabled,Enabled" group.quad spr:0x34111++0x00 line.quad 0x00 "MDCR_EL2,Hypervisor Debug Control Register (EL2)" bitfld.quad 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid" bitfld.quad 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid" bitfld.quad 0x00 9. "TDA,Trap Debug Access" "No effect,Valid" newline bitfld.quad 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid" bitfld.quad 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled" bitfld.quad 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid" newline bitfld.quad 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid" bitfld.quad 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6" group.quad spr:0x34112++0x00 line.quad 0x00 "CPTR_EL2,Architectural Feature Trap Register (EL2)" bitfld.quad 0x00 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped" bitfld.quad 0x00 10. "TFP,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2" "Not trapped,Trapped" group.quad spr:0x36131++0x00 line.quad 0x00 "MDCR_EL3,Hypervisor Debug Control Register (EL3)" bitfld.quad 0x00 21. "EPMAD,External debugger access to Performance Monitors registers disabled" "No,Yes" bitfld.quad 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint registers disabled" "No,Yes" bitfld.quad 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled" newline bitfld.quad 0x00 16. "SDD,AArch64 secure debug disable" "No,Yes" bitfld.quad 0x00 14.--15. "SPD32,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled" bitfld.quad 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid" newline bitfld.quad 0x00 9. "TDA,Trap Debug Access" "No effect,Valid" bitfld.quad 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid" group.quad spr:0x36112++0x00 line.quad 0x00 "CPTR_EL3,Architectural Feature Trap Register (EL3)" bitfld.quad 0x00 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped" bitfld.quad 0x00 10. "TFP,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2" "Not trapped,Trapped" group.quad spr:0x34113++0x00 line.quad 0x00 "HSTR_EL2,Hypervisor System Trap Register" bitfld.quad 0x00 16. "TTEE,Trap ThumbEE" "Not supported,?..." bitfld.quad 0x00 15. "T15,Trap coprocessor primary register CRn = 15" "No effect,Trapped" bitfld.quad 0x00 13. "T13,Trap coprocessor primary register CRn = 13" "No effect,Trapped" newline bitfld.quad 0x00 12. "T12,Trap coprocessor primary register CRn = 12" "No effect,Trapped" bitfld.quad 0x00 11. "T11,Trap coprocessor primary register CRn = 11" "No effect,Trapped" bitfld.quad 0x00 10. "T10,Trap coprocessor primary register CRn = 10" "No effect,Trapped" newline bitfld.quad 0x00 9. "T9,Trap coprocessor primary register CRn = 9" "No effect,Trapped" bitfld.quad 0x00 8. "T8,Trap coprocessor primary register CRn = 8" "No effect,Trapped" bitfld.quad 0x00 7. "T7,Trap coprocessor primary register CRn = 7" "No effect,Trapped" newline bitfld.quad 0x00 6. "T6,Trap coprocessor primary register CRn = 6" "No effect,Trapped" bitfld.quad 0x00 5. "T5,Trap coprocessor primary register CRn = 5" "No effect,Trapped" bitfld.quad 0x00 3. "T3,Trap coprocessor primary register CRn = 3" "No effect,Trapped" newline bitfld.quad 0x00 2. "T2,Trap coprocessor primary register CRn = 2" "No effect,Trapped" bitfld.quad 0x00 1. "T1,Trap coprocessor primary register CRn = 1" "No effect,Trapped" bitfld.quad 0x00 0. "T0,Trap coprocessor primary register CRn = 0" "No effect,Trapped" group.quad spr:0x34117++0x00 line.quad 0x00 "HACR_EL2,Hypervisor Auxiliary Configuration Register" group.quad spr:0x34210++0x00 line.quad 0x00 "VTTBR_EL2,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,VMID for the translation table" hexmask.quad 0x00 1.--47. 1. "BADDR,Translation table base address" group.quad spr:0x34212++0x00 line.quad 0x00 "VTCR_EL2,Virtualization Translation Control Register" bitfld.quad 0x00 16.--18. "PS,Physical Address Size" "32 bits/4GB,36 bits/64GB,40 bits/1TB,?..." bitfld.quad 0x00 14.--15. "TG0,Granule size for the corresponding translation table base address register" "4 KB,64 KB,16 KB,?..." bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable" bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable" bitfld.quad 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "0,1,2,3" newline bitfld.quad 0x00 0.--5. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.quad spr:0x34604++0x00 line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register" hexmask.quad 0x00 4.--39. 0x10 "FIPA,Faulting IPA bits" tree.end tree "Cache Control and Configuration" rgroup.quad spr:0x33001++0x0 line.quad 0x00 "CTR_EL0,Cache Type Register" bitfld.quad 0x00 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.quad 0x00 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.quad 0x00 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.quad 0x00 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..." bitfld.quad 0x00 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." group.quad spr:0x32000++0x0 line.quad 0x00 "CSSELR_EL1,Cache Size Selection Register" bitfld.quad 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,?..." bitfld.quad 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction" rgroup.quad spr:0x31000++0x0 line.quad 0x00 "CCSIDR_EL1,Current Cache Size ID Register" bitfld.quad 0x00 31. "WT,Write-Through" "Not Supported,?..." bitfld.quad 0x00 30. "WB,Write-Back" "Not Supported,Supported" bitfld.quad 0x00 29. "RA,Read-Allocate" "Not Supported,Supported" newline bitfld.quad 0x00 28. "WA,Write-Allocate" "Not Supported,Supported" hexmask.quad.word 0x00 13.--27. 1. 1. "SETS,Number of Sets" hexmask.quad.word 0x00 3.--12. 1. 1. "ASSOC,Associativity" newline bitfld.quad 0x00 0.--2. "LSIZE,Line Size" "Reserved,Reserved,16 words,?..." rgroup.quad spr:0x31001++0x0 line.quad 0x00 "CLIDR_EL1,Cache Level ID Register" bitfld.quad 0x00 30.--31. "ICB,Inner cache boundary" "Not disclosed,?..." bitfld.quad 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,L1 cache,?..." bitfld.quad 0x00 24.--26. "LOC,Level of Coherency" "Reserved,No L2 cache,L2 cache,?..." newline bitfld.quad 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Reserved,L2 cache,?..." bitfld.quad 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..." bitfld.quad 0x00 3.--5. "CTYPE2,Cache type for levels 2" "No cache,Reserved,Reserved,Reserved,Unified,?..." newline bitfld.quad 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate,?..." tree "Level 1 memory system" rgroup.quad spr:0x33F00++0x00 line.quad 0x00 "CDBGDR0_EL3,Cache Debug Data Register 0" rgroup.quad spr:0x33F01++0x00 line.quad 0x00 "CDBGDR1_EL3,Cache Debug Data Register 1" rgroup.quad spr:0x33F02++0x00 line.quad 0x00 "CDBGDR2_EL3,Cache Debug Data Register 2" rgroup.quad spr:0x33F03++0x00 line.quad 0x00 "CDBGDR3_EL3,Cache Debug Data Register 3" wgroup.quad spr:0x33F20++0x00 line.quad 0x00 "CDBGDCT_EL3,Data Cache Tag Read Operation Register" wgroup.quad spr:0x33F21++0x00 line.quad 0x00 "CDBGICT_EL3,Instruction Cache Tag Read Operation Register" wgroup.quad spr:0x33F40++0x00 line.quad 0x00 "CDBGDCD_EL3,Data Cache Data Read Operation Register" wgroup.quad spr:0x33F41++0x00 line.quad 0x00 "CDBGICD_EL3,Instruction Cache Data Read Operation Register" wgroup.quad spr:0x33F42++0x00 line.quad 0x00 "CDBGTD_EL3,TLB Data Read Operation Register" if (((per.q(spr:0x31F22))&0x7F000000)==0x000000000) group.quad spr:0x31F22++0x00 line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register EL1" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "Way 0,Way 1,?..." newline hexmask.quad.word 0x00 0.--11. 0x01 "RAD,RAM address" elif (((per.q(spr:0x31F22))&0x7F000000)==0x01000000) group.quad spr:0x31F22++0x00 line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register EL1" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "Bank 0,Bank 1,?..." newline hexmask.quad.word 0x00 0.--11. 0x01 "RAD,RAM address" elif (((per.q(spr:0x31F22))&0x7F000000)==0x08000000) group.quad spr:0x31F22++0x00 line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register EL1" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "Way 0,Way 1,Way 2,Way 3,?..." newline hexmask.quad.word 0x00 0.--11. 0x01 "RAD,RAM address" elif (((per.q(spr:0x31F22))&0x7F000000)==0x09000000) group.quad spr:0x31F22++0x00 line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register EL1" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "Bank 0,Bank 1,Bank 2,Bank 3,Bank 4,Bank 5,Bank 6,Bank 7" newline hexmask.quad.word 0x00 0.--11. 0x01 "RAD,RAM address" elif (((per.q(spr:0x31F22))&0x7F000000)==0x0A000000) group.quad spr:0x31F22++0x00 line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register EL1" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "Dirty RAM,?..." newline hexmask.quad.word 0x00 0.--11. 0x01 "RAD,RAM address" elif (((per.q(spr:0x31F22))&0x7F000000)==0x18000000) group.quad spr:0x31F22++0x00 line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register EL1" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "Way 0,Way 1,?..." newline hexmask.quad.word 0x00 0.--11. 0x01 "RAD,RAM address" else group.quad spr:0x31F22++0x00 line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register EL1" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" hexmask.quad.word 0x00 0.--11. 0x01 "RAD,RAM address" endif tree.end tree "Level 2 memory system" group.quad spr:0x31B02++0x0 line.quad 0x00 "L2CTLR_EL1,L2 Control Register" bitfld.quad 0x00 24.--25. "NCPU,Number of CPU" "1,2,3,4" bitfld.quad 0x00 22. "CPUCP,CPU Cache Protection" "Not implemented,ECC implemented" bitfld.quad 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Not implemented,ECC implemented" newline bitfld.quad 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycles" bitfld.quad 0x00 0. "DRAMOL,L2 data RAM output latency" "2 cycles,3 cycles" group.quad spr:0x31B03++0x0 line.quad 0x00 "L2ECTLR_EL1,L2 Extended Control Register" bitfld.quad 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error" bitfld.quad 0x00 29. "AACASYNCERR,AXI/ACE/CHI asynchronous error" "No error,Error" bitfld.quad 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.quad spr:0x31F00++0x00 line.quad 0x00 "L2ACTLR_EL1,L2 Auxiliary Control Register" bitfld.quad 0x00 30.--31. "L2VC,L2 victim Control" "0,1,2,3" bitfld.quad 0x00 29. "L2DEIEN,L2 cache data RAM error injection enable" "Disabled,Enabled" bitfld.quad 0x00 24. "L2TEIEN,L2 cache tag RAM error injection enable" "Disabled,Enabled" newline bitfld.quad 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled" bitfld.quad 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes" if (((per.q(spr:0x31F23))&0x7F000000)==0x10000000) group.quad spr:0x31F23++0x00 line.quad 0x00 "L2MERRSR_EL1,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--21. "C/W,Indicates the RAM where the first memory error occurred" "Way 0,Way 1,Way 2,Way 3,Way 4,Way 5,Way 6,Way 7,?..." newline hexmask.quad.word 0x00 3.--16. 1. "IND,Index" elif (((per.q(spr:0x31F23))&0x7F000000)==0x11000000) group.quad spr:0x31F23++0x00 line.quad 0x00 "L2MERRSR_EL1,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--21. "C/W,Indicates the RAM where the first memory error occurred" "Bank 0,Bank 1,Bank 2,Bank 3,Bank 4,Bank 5,Bank 6,Bank 7,?..." newline hexmask.quad.word 0x00 3.--16. 1. "IND,Index" elif (((per.q(spr:0x31F23))&0x7F000000)==0x12000000) group.quad spr:0x31F23++0x00 line.quad 0x00 "L2MERRSR_EL1,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--21. "C/W,Indicates the RAM where the first memory error occurred" "CPU0/Way 0,CPU0/Way 1,CPU0/Way 2,CPU0/Way 3,CPU1/Way 0,CPU1/Way 1,CPU1/Way 2,CPU1/Way 3,CPU2/Way 0,CPU2/Way 1,CPU2/Way 2,CPU2/Way 3,CPU3/Way 0,CPU3/Way 1,CPU3/Way 2,CPU3/Way 3" newline hexmask.quad.word 0x00 3.--16. 1. "IND,Index" else group.quad spr:0x31F23++0x00 line.quad 0x00 "L2MERRSR_EL1,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" hexmask.quad.word 0x00 3.--16. 1. "IND,Index" endif tree.end tree.end tree "System Performance Monitor" group.quad spr:0x339C0++0x00 line.quad 0x00 "PMCR_EL0,Performance Monitor Control Register" rhexmask.quad.byte 0x00 24.--31. 1. "IMP,Implementer code" rhexmask.quad.byte 0x00 16.--23. 1. "IDCODE,Identification code" rbitfld.quad 0x00 11.--15. "N,Number of counters implemented" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,6,?..." bitfld.quad 0x00 6. "LC,Long cycle count enable" "Disabled,Enabled" newline bitfld.quad 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes" bitfld.quad 0x00 4. "X,Export Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "D,Clock Divider" "Every cycle,64th cycle" eventfld.quad 0x00 2. "C,Clock Counter Reset" "No reset,Reset" newline eventfld.quad 0x00 1. "P,Performance Counter Reset" "No reset,Reset" bitfld.quad 0x00 0. "E,All Counters enable" "Disabled,Enabled" group.quad spr:0x339C1++0x00 line.quad 0x00 "PMCNTENSET_EL0,Count Enable Set Register " bitfld.quad 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" bitfld.quad 0x00 5. "P5,Event Counter 5 enable bit" "Disabled,Enabled" bitfld.quad 0x00 4. "P4,Event Counter 4 enable bit" "Disabled,Enabled" bitfld.quad 0x00 3. "P3,Event Counter 3 enable bit" "Disabled,Enabled" newline bitfld.quad 0x00 2. "P2,Event Counter 2 enable bit" "Disabled,Enabled" bitfld.quad 0x00 1. "P1,Event Counter 1 enable bit" "Disabled,Enabled" bitfld.quad 0x00 0. "P0,Event Counter 0 enable bit" "Disabled,Enabled" group.quad spr:0x339C2++0x00 line.quad 0x00 "PMCNTENCLR_EL0,Count Enable Clear Register" bitfld.quad 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" bitfld.quad 0x00 5. "P5,Event Counter 5 clear bit" "Disabled,Enabled" bitfld.quad 0x00 4. "P4,Event Counter 4 clear bit" "Disabled,Enabled" bitfld.quad 0x00 3. "P3,Event Counter 3 clear bit" "Disabled,Enabled" newline bitfld.quad 0x00 2. "P2,Event Counter 2 clear bit" "Disabled,Enabled" bitfld.quad 0x00 1. "P1,Event Counter 1 clear bit" "Disabled,Enabled" bitfld.quad 0x00 0. "P0,Event Counter 0 clear bit" "Disabled,Enabled" group.quad spr:0x339C3++0x00 line.quad 0x00 "PMOVSCLR_EL0,Performance Monitors Overflow Flag Status Clear Register" eventfld.quad 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow" eventfld.quad 0x00 5. "P5,Event Counter 5 overflow clear bit" "Disabled,Enabled" eventfld.quad 0x00 4. "P4,Event Counter 4 overflow clear bit" "Disabled,Enabled" eventfld.quad 0x00 3. "P3,Event Counter 3 overflow clear bit" "Disabled,Enabled" newline eventfld.quad 0x00 2. "P2,Event Counter 2 overflow clear bit" "Disabled,Enabled" eventfld.quad 0x00 1. "P1,Event Counter 1 overflow clear bit" "Disabled,Enabled" eventfld.quad 0x00 0. "P0,Event Counter 0 overflow clear bit" "Disabled,Enabled" wgroup.quad spr:0x339C4++0x00 line.quad 0x00 "PMSWINC_EL0,Performance Monitor Software Increment" bitfld.quad 0x00 5. "P5,Increment PMN5" "No action,Increment" bitfld.quad 0x00 4. "P4,Increment PMN4" "No action,Increment" bitfld.quad 0x00 3. "P3,Increment PMN3" "No action,Increment" bitfld.quad 0x00 2. "P2,Increment PMN2" "No action,Increment" newline bitfld.quad 0x00 1. "P1,Increment PMN1" "No action,Increment" bitfld.quad 0x00 0. "P0,Increment PMN0" "No action,Increment" group.quad spr:0x339C5++0x00 line.quad 0x00 "PMSELR_EL0,Performance Monitor Select Register" bitfld.quad 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.open "Common Event Identification Registers" rgroup.quad spr:0x339C6++0x00 line.quad 0x00 "PMCEID0_EL0,Common Event Identification Register" bitfld.quad 0x00 31. "L1D_CACHE_ALLOCATE,Level 1 data cache allocate" "Not implemented,?..." bitfld.quad 0x00 30. "CHAIN,Chain" "Reserved,Implemented" bitfld.quad 0x00 29. "BUS_CYCLES,Bus cycle" "Reserved,Implemented" newline bitfld.quad 0x00 28. "TTBR_WRITE_RETIRED,TTBR write retired" "Not implemented,?..." bitfld.quad 0x00 27. "INST_SPEC,Instruction speculatively executed" "Reserved,Implemented" bitfld.quad 0x00 26. "MEMORY_ERROR,Local memory error" "Reserved,Implemented" newline bitfld.quad 0x00 25. "BUS_ACCESS,Bus access" "Reserved,Implemented" bitfld.quad 0x00 24. "L2D_CACHE_WB,Level 2 data cache write-back" "Not implemented,Implemented" bitfld.quad 0x00 23. "L2D_CACHE_REFILL,Level 2 data cache refill" "Not implemented,Implemented" newline bitfld.quad 0x00 22. "L2D_CACHE,Level 2 data cache access" "Not implemented,Implemented" bitfld.quad 0x00 21. "L1D_CACHE_WB,Level 1 data cache write-back" "Reserved,Implemented" bitfld.quad 0x00 20. "L1I_CACHE,Level 1 instruction cache access" "Reserved,Implemented" newline bitfld.quad 0x00 19. "MEM_ACCESS,Data memory access" "Reserved,Implemented" bitfld.quad 0x00 18. "BR_PRED,Predictable branch speculatively executed" "Reserved,Implemented" bitfld.quad 0x00 17. "CPU_CYCLES,CPU Cycle" "Reserved,Implemented" newline bitfld.quad 0x00 16. "BR_MIS_PRED,Mispredicted or not predicted branch speculatively executed" "Reserved,Implemented" bitfld.quad 0x00 15. "UNALIGNED_LDST_RETIRED,UNALIGNED_LDST_RETIRED" "Reserved,Implemented" bitfld.quad 0x00 14. "BR_RETURN_RETIRED,Instruction architecturally executed condition check pass procedure return" "Not implemented,?..." newline bitfld.quad 0x00 13. "BR_IMMED_RETIRED,Instruction architecturally executed immediate branch" "Reserved,Implemented" bitfld.quad 0x00 12. "PC_WRITE_RETIRED,Instruction architecturally executed condition check pass software change of the PC" "Reserved,Implemented" bitfld.quad 0x00 11. "CID_WRITE_RETIRED,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Reserved,Implemented" newline bitfld.quad 0x00 10. "EXC_RETURN,Instruction architecturally executed condition check pass exception return" "Reserved,Implemented" bitfld.quad 0x00 9. "EXC_TAKEN,Exception taken" "Reserved,Implemented" bitfld.quad 0x00 8. "INST_RETIRED,Instruction architecturally executed" "Reserved,Implemented" newline bitfld.quad 0x00 7. "ST_RETIRED,Instruction architecturally executed condition check pass store" "Reserved,Implemented" bitfld.quad 0x00 6. "LD_RETIRED,Instruction architecturally executed condition check pass load" "Reserved,Implemented" bitfld.quad 0x00 5. "L1D_TLB_REFILL,Level 1 data TLB refill" "Reserved,Implemented" newline bitfld.quad 0x00 4. "L1D_CACHE,Level 1 data cache access" "Reserved,Implemented" bitfld.quad 0x00 3. "L1D_CACHE_REFILL,Level 1 data cache refill" "Reserved,Implemented" bitfld.quad 0x00 2. "L1I_TLB_REFILL,Level 1 instruction TLB refill" "Reserved,Implemented" newline bitfld.quad 0x00 1. "L1I_CACHE_REFILL,Level 1 instruction cache refill" "Reserved,Implemented" bitfld.quad 0x00 0. "SW_INCR,Instruction architecturally executed condition check pass software increment" "Reserved,Implemented" rgroup.quad spr:0x339C7++0x00 line.quad 0x00 "PMCEID1_EL0,Common Event Identification Register" bitfld.quad 0x00 16. "L2I_TLB,Attributable Level 2 instruction TLB access" "Not implemented,?..." bitfld.quad 0x00 15. "L2D_TLB,Attributable Level 2 data or unified TLB access" "Not implemented,?..." bitfld.quad 0x00 14. "L2I_TLB_REFILL,Attributable Level 2 instruction TLB refill" "Not implemented,?..." newline bitfld.quad 0x00 13. "L2D_TLB_REFIL,Attributable Level 2 data or unified TLB refill" "Not implemented,?..." bitfld.quad 0x00 12. "L3D_CACHE_WB,Attributable Level 3 data or unified cache write-back" "Not implemented,?..." bitfld.quad 0x00 11. "L3D_CACHE,Attributable Level 3 data or unified cache access" "Not implemented,?..." newline bitfld.quad 0x00 10. "L3D_CACHE_REFILL,Attributable Level 3 data or unified cache refill" "Not implemented,?..." bitfld.quad 0x00 9. "L3D_CACHE_ALLOCATE,Attributable Level 3 data or unified cache allocation without refill" "Not implemented,?..." bitfld.quad 0x00 8. "L2I_CACHE_REFILL,Attributable Level 2 instruction cache refill" "Not implemented,?..." newline bitfld.quad 0x00 7. "L2I_CACHE,Attributable Level 2 instruction cache access" "Not implemented,?..." bitfld.quad 0x00 6. "L1I_TLB,Level 1 instruction TLB access" "Not implemented,?..." bitfld.quad 0x00 5. "L1D_TLB,Level 1 data or unified TLB access" "Not implemented,?..." newline bitfld.quad 0x00 4. "STALL_BACKEND,No operation issued due to backend" "Not implemented,?..." bitfld.quad 0x00 3. "STALL_FRONTEND,No operation issued due to the frontend" "Not implemented,?..." bitfld.quad 0x00 2. "BR_MIS_PRED_RETIRED,Instruction architecturally executed mispredicted branch" "Not implemented,?..." newline bitfld.quad 0x00 1. "BR_RETIRED,Instruction architecturally executed branch" "Not implemented,?..." bitfld.quad 0x00 0. "L2D_CACHE_ALLOCATE,Level 2 data cache allocation without refill" "Not implemented,?..." tree.end newline group.quad spr:0x339D0++0x00 line.quad 0x00 "PMCCNTR_EL0,Performance Monitor Cycle Count Register" if (((per.q(spr:0x339C5))&0x1F)==0x1F) group.quad spr:0x339D1++0x00 line.quad 0x00 "PMXEVTYPER_EL0,Performance Monitor Event Type Register" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" else group.quad spr:0x339D1++0x00 line.quad 0x00 "PMXEVTYPER_EL0,Performance Monitor Event Type Register" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" endif group.quad spr:0x339D2++0x00 line.quad 0x00 "PMXEVCNTR_EL0,Performance Monitor Event Count Register" group.quad spr:0x339E0++0x00 line.quad 0x00 "PMUSERENR_EL0,Performance Monitor User Enable Register" bitfld.quad 0x00 3. "ER,Event counter read enable" "Disabled,Enabled" bitfld.quad 0x00 2. "EC,Cycle counter read enable" "Disabled,Enabled" bitfld.quad 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled" bitfld.quad 0x00 0. "EN,User mode access enable" "Disabled,Enabled" group.quad spr:0x309E1++0x00 line.quad 0x00 "PMINTENSET_EL1,Performance Monitor Interrupt Enable Set" bitfld.quad 0x00 31. "C,Cycle counter Overflow Interrupt clear" "Disabled,Enabled" bitfld.quad 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.quad spr:0x309E2++0x00 line.quad 0x00 "PMINTENCLR_EL1,Performance Monitor Interrupt Enable Clear" eventfld.quad 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" eventfld.quad 0x00 5. "P5,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.quad 0x00 4. "P4,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.quad 0x00 3. "P3,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.quad 0x00 2. "P2,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.quad 0x00 1. "P1,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.quad 0x00 0. "P0,Overflow Interrupt Clear" "Disabled,Enabled" group.quad spr:0x339E3++0x00 line.quad 0x00 "PMOVSSET_EL0,Performance Monitor Overflow Flag Status Set Register" bitfld.quad 0x00 31. "C,Cycle counter Overflow Interrupt clear" "Disabled,Enabled" bitfld.quad 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.quad spr:0x33E80++0x00 line.quad 0x00 "PMEVCNTR0_EL0,Performance Monitors Event Count Register 0" group.quad spr:(0x33E80+0x40)++0x00 line.quad 0x00 "PMEVTYPER0_EL0,Performance Monitors Selected Event Type Register 0" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad spr:0x33E81++0x00 line.quad 0x00 "PMEVCNTR1_EL0,Performance Monitors Event Count Register 1" group.quad spr:(0x33E81+0x40)++0x00 line.quad 0x00 "PMEVTYPER1_EL0,Performance Monitors Selected Event Type Register 1" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad spr:0x33E82++0x00 line.quad 0x00 "PMEVCNTR2_EL0,Performance Monitors Event Count Register 2" group.quad spr:(0x33E82+0x40)++0x00 line.quad 0x00 "PMEVTYPER2_EL0,Performance Monitors Selected Event Type Register 2" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad spr:0x33E83++0x00 line.quad 0x00 "PMEVCNTR3_EL0,Performance Monitors Event Count Register 3" group.quad spr:(0x33E83+0x40)++0x00 line.quad 0x00 "PMEVTYPER3_EL0,Performance Monitors Selected Event Type Register 3" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad spr:0x33E84++0x00 line.quad 0x00 "PMEVCNTR4_EL0,Performance Monitors Event Count Register 4" group.quad spr:(0x33E84+0x40)++0x00 line.quad 0x00 "PMEVTYPER4_EL0,Performance Monitors Selected Event Type Register 4" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad spr:0x33E85++0x00 line.quad 0x00 "PMEVCNTR5_EL0,Performance Monitors Event Count Register 5" group.quad spr:(0x33E85+0x40)++0x00 line.quad 0x00 "PMEVTYPER5_EL0,Performance Monitors Selected Event Type Register 5" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad spr:0x33EF7++0x00 line.quad 0x00 "PMCCFILTR_EL0,Performance Monitors Cycle Count Filter Register" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" tree.end tree "System Timer Registers" group.quad spr:0x33E00++0x00 line.quad 0x00 "CNTFRQ_EL0,Counter-timer Frequency Register" hexmask.quad.long 0x00 0.--31. 1. "CF,Clock frequency" rgroup.quad spr:0x33E01++0x00 line.quad 0x00 "CNTPCT_EL0,Counter-timer Physical Count Register" rgroup.quad spr:0x33E02++0x00 line.quad 0x00 "CNTVCT_EL0,Counter-timer Virtual Count Register" group.quad spr:0x34E03++0x00 line.quad 0x00 "CNTVOFF_EL2,Counter-timer Virtual Offset Register" group.quad spr:0x30E10++0x00 line.quad 0x00 "CNTKCTL_EL1,Counter-timer Kernel Control Register" bitfld.quad 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 mode" "Disabled,Enabled" bitfld.quad 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 mode" "Disabled,Enabled" bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from that counter when that stream is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit defined by EVNTI generates an event when the event stream is enabled" "0 to 1,1 to 0" newline bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the corresponding counter" "Disabled,Enabled" bitfld.quad 0x00 1. "EL0VCTEN,Controls whether the virtual counter CNTVCT and the frequency Register CNTFRQ are accessible from EL0 mode" "Disabled,Enabled" bitfld.quad 0x00 0. "EL0PCTEN,Controls whether the physical counter CNTPCT and the frequency Register CNTFRQ are accessible from EL0 mode" "Disabled,Enabled" group.quad spr:0x34E10++0x00 line.quad 0x00 "CNTHCTL_EL2,Counter-timer Hypervisor Control Register" bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTPCT is the trigger for the event stream generated from the physical counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit defined by EVNTI generates an event when the event stream is enabled" "0 to 1,1 to 0" bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the physical counter" "Disabled,Enabled" bitfld.quad 0x00 1. "EL1PCEN,Controls whether the physical timer registers are accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible" newline bitfld.quad 0x00 0. "EL1PCTEN,Controls whether the physical counter CNTPCT is accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible" group.quad spr:0x33E20++0x00 line.quad 0x00 "CNTP_TVAL_EL0,Counter-timer Physical Timer TimerValue Register" hexmask.quad.long 0x00 0.--31. 1. "TV,TimerValue view of the EL1 physical timer" group.quad spr:0x33E21++0x00 line.quad 0x00 "CNTP_CTL_EL0,Counter-timer Physical Timer Control Register" rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x33E22++0x00 line.quad 0x00 "CNTP_CVAL_EL0,Counter-timer Physical Timer CompareValue Register" group.quad spr:0x33E30++0x00 line.quad 0x00 "CNTV_TVAL_EL0,Counter-timer Virtual Timer TimerValue Register" hexmask.quad.long 0x00 0.--31. 1. "TV,TimerValue view of the EL1 virtual timer" group.quad spr:0x33E31++0x00 line.quad 0x00 "CNTV_CTL_EL0,Counter-timer Virtual Timer Control Register" rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x33E32++0x00 line.quad 0x00 "CNTV_CVAL_EL0,Counter-timer Virtual Timer CompareValue Register" group.quad spr:0x34E20++0x00 line.quad 0x00 "CNTHP_TVAL_EL2,Counter-timer Hypervisor Physical Timer TimerValue Register" hexmask.quad.long 0x00 0.--31. 1. "TV,TimerValue view of the EL2 physical timer" group.quad spr:0x34E21++0x00 line.quad 0x00 "CNTHP_CTL_EL2,Counter-timer Hypervisor Physical Timer Control Register" rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x34E22++0x00 line.quad 0x00 "CNTHP_CVAL_EL2,Counter-timer Hypervisor Physical Timer CompareValue Register" group.quad spr:0x37E20++0x00 line.quad 0x00 "CNTPS_TVAL_EL1,Counter-timer Physical Secure Timer TimerValue Register" hexmask.quad.long 0x00 0.--31. 1. "TV,TimerValue view of the secure physical timer" group.quad spr:0x37E21++0x00 line.quad 0x00 "CNTPS_CTL_EL1,Counter-timer Physical Secure Timer Control Register" rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" newline bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x37E22++0x00 line.quad 0x00 "CNTPS_CVAL_EL1,Counter-timer Physical Secure Timer CompareValue Register" tree.end tree "Generic Interrupt Controller System Registers" tree "AArch64 GIC Physical CPU Interface System Registers" tree.open "Interrupt Controller Active Priorities Registers" group.quad spr:0x30C84++0x00 line.quad 0x00 "ICC_AP0R0_EL1,Interrupt Controller Active Priorities Group 0 Register 0 (EL1)" bitfld.quad 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.quad 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.quad 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" newline bitfld.quad 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.quad 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.quad 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.quad 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" newline bitfld.quad 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" bitfld.quad 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.quad 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.quad 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.quad 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.quad 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.quad 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" bitfld.quad 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" newline bitfld.quad 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.quad 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.quad 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.quad 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.quad spr:0x30C90++0x00 line.quad 0x00 "ICC_AP1R0_EL1,Interrupt Controller Active Priorities Group 1 Register 0 (EL1)" bitfld.quad 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.quad 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.quad 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" newline bitfld.quad 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.quad 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.quad 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.quad 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" newline bitfld.quad 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" bitfld.quad 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.quad 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.quad 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.quad 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.quad 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.quad 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" bitfld.quad 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" newline bitfld.quad 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.quad 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.quad 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.quad 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline if (((per.q(spr:0x30CB6))&0x10000000000)==0x00) wgroup.quad spr:0x30CB6++0x00 line.quad 0x00 "ICC_ASGI1R_EL1,Interrupt Controller Alias Software Generated Interrupt Group 1 Register" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated" else wgroup.quad spr:0x30CB6++0x00 line.quad 0x00 "ICC_ASGI1R_EL1,Interrupt Controller Alias Software Generated Interrupt Group 1 Register" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif group.quad spr:0x30C83++0x00 line.quad 0x00 "ICC_BPR0_EL1,Interrupt Controller Binary Point Register 0" bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control and Interrupt Preemption Control" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" group.quad spr:0x30CC3++0x00 line.quad 0x00 "ICC_BPR1_EL1,Interrupt Controller Binary Point Register 1" bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control and Interrupt Preemption Control" "Reserved,[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" group.quad spr:0x30CC4++0x00 line.quad 0x00 "ICC_CTLR_EL1,Interrupt Controller Control Register (EL1)" rbitfld.quad 0x00 19. "EXTRANGE,Extended INTID range" "Reserved,Supported" rbitfld.quad 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255" newline rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Zero,Non-zero" rbitfld.quad 0x00 14. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported" rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline rbitfld.quad 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 6. "PMHE,Controls whether the priority mask Register is used as a hint for interrupt distribution" "Disabled,Enabled" bitfld.quad 0x00 1. "EOIMODE,Controls whether a write to an End of Interrupt Register also deactivates the interrupt" "Disabled,Enabled" newline bitfld.quad 0x00 0. "CBPR,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 interrupts" "Separate registers,Same Register" group.quad spr:0x36CC4++0x00 line.quad 0x00 "ICC_CTLR_EL3,Interrupt Controller Control Register (EL3)" rbitfld.quad 0x00 19. "ExtRange,Extended INTID range" "Not supported,Supported" rbitfld.quad 0x00 18. "RSS,Range Selector Support" "0 - 15,0 - 255" newline rbitfld.quad 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported" rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported" rbitfld.quad 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,Supported" newline rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." rbitfld.quad 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" newline bitfld.quad 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (Non-secure EL1 and EL2)" "Priority drop/Deactivation,Priority drop" bitfld.quad 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (Secure EL1)" "Priority drop/Deactivation,Priority drop" bitfld.quad 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (EL3)" "Enabled,Disabled" newline bitfld.quad 0x00 1. "CBPR_EL1NS,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate registers,Same Register" bitfld.quad 0x00 0. "CBPR_EL1S,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate registers,Same Register" if (((per.q(spr:0x30CC4))&0x3800)==0x00) wgroup.quad spr:0x30CB1++0x00 line.quad 0x00 "ICC_DIR_EL1,Interrupt Controller Deactivate Interrupt Register" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.quad spr:0x30C81++0x00 line.quad 0x00 "ICC_EOIR0_EL1,Interrupt Controller End Of Interrupt Register 0" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0 access" wgroup.quad spr:0x30CC1++0x00 line.quad 0x00 "ICC_EOIR1_EL1,Interrupt Controller End Of Interrupt Register 1" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1 access" rgroup.quad spr:0x30C82++0x00 line.quad 0x00 "ICC_HPPIR0_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 0" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level" rgroup.quad spr:0x30CC2++0x00 line.quad 0x00 "ICC_HPPIR1_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 1" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level" elif (((per.q(spr:0x30CC4))&0x3800)==0x800) wgroup.quad spr:0x30CB1++0x00 line.quad 0x00 "ICC_DIR_EL1,Interrupt Controller Deactivate Interrupt Register" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.quad spr:0x30C81++0x00 line.quad 0x00 "ICC_EOIR0_EL1,Interrupt Controller End Of Interrupt Register 0" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR0 access" wgroup.quad spr:0x30CC1++0x00 line.quad 0x00 "ICC_EOIR1_EL1,Interrupt Controller End Of Interrupt Register 1" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR1 access" rgroup.quad spr:0x30C82++0x00 line.quad 0x00 "ICC_HPPIR0_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 0" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level" rgroup.quad spr:0x30CC2++0x00 line.quad 0x00 "ICC_HPPIR1_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 1" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level" endif hgroup.quad spr:0x30C80++0x00 hide.long 0x00 "ICC_IAR0_EL1,Interrupt Acknowledge Register 0" in hgroup.quad spr:0x30CC0++0x00 hide.long 0x00 "ICC_IAR1_EL1,Interrupt Acknowledge Register 1" in newline group.quad spr:0x30CC6++0x00 line.quad 0x00 "ICC_IGRPEN0_EL1,Interrupt Controller Interrupt Group 0 Enable Register" bitfld.quad 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled" group.quad spr:0x30CC7++0x00 line.quad 0x00 "ICC_IGRPEN1_EL1,Interrupt Controller Interrupt Group 1 Enable Register (EL1)" bitfld.quad 0x00 0. "ENABLE,Enables Group 1 interrupts" "Disabled,Enabled" group.quad spr:0x36CC7++0x00 line.quad 0x00 "ICC_IGRPEN1_EL3,Interrupt Controller Interrupt Group 1 Enable Register (EL3)" bitfld.quad 0x00 1. "ENABLEGRP1S,Enables Group 1 interrupts for the Secure state" "Disabled,Enabled" bitfld.quad 0x00 0. "ENABLEGRP1NS,Enables Group 1 interrupts for the Non-secure state" "Disabled,Enabled" group.quad spr:0x30460++0x00 line.quad 0x00 "ICC_PMR_EL1,Interrupt Controller Interrupt Priority Mask Register" hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,The priority mask level for the CPU interface" rgroup.quad spr:0x30CB3++0x00 line.quad 0x00 "ICC_RPR_EL1,Interrupt Controller Running Priority Register" hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,The current running priority on the CPU interface" if (((per.q(spr:0x30CB7))&0x10000000000)==0x00) wgroup.quad spr:0x30CB7++0x00 line.quad 0x00 "ICC_SGI0R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated." else wgroup.quad spr:0x30CB7++0x00 line.quad 0x00 "ICC_SGI0R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif if (((per.q(spr:0x30CB5))&0x10000000000)==0x00) wgroup.quad spr:0x30CB5++0x00 line.quad 0x00 "ICC_SGI1R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated" else wgroup.quad spr:0x30CB5++0x00 line.quad 0x00 "ICC_SGI1R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif group.quad spr:0x30CC5++0x00 line.quad 0x00 "ICC_SRE_EL1,Interrupt Controller System Register Enable Register (EL1)" bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" bitfld.quad 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" group.quad spr:0x34C95++0x00 line.quad 0x00 "ICC_SRE_EL2,Interrupt Controller System Register Enable Register (EL2)" bitfld.quad 0x00 3. "ENABLE,Enables lower Exception level access to ICC_SRE_EL1" "Trapped,Not trapped" bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.quad 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" group.quad spr:0x36CC5++0x00 line.quad 0x00 "ICC_SRE_EL3,Interrupt Controller System Register Enable Register (EL3)" bitfld.quad 0x00 3. "ENABLE,Enables lower Exception level access to ICC_SRE_EL1/ICC_SRE_EL2" "Trapped,Not trapped" bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.quad 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" tree.end tree "AArch64 Virtual Interface Control System Registers" tree.open "Hypervisor Active Priorities Registers" group.quad spr:0x34C80++0x00 line.quad 0x00 "ICH_AP0R0_EL2,Interrupt Controller Hypervisor Active Priorities Group 0 Register 0" bitfld.quad 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.quad 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.quad 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" newline bitfld.quad 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.quad 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.quad 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.quad 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" newline bitfld.quad 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" bitfld.quad 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.quad 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.quad 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.quad 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.quad 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.quad 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" bitfld.quad 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" newline bitfld.quad 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.quad 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.quad 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.quad 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.quad spr:0x34C90++0x00 line.quad 0x00 "ICH_AP1R0_EL2,Interrupt Controller Hypervisor Active Priorities Group 1 Register 0" bitfld.quad 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.quad 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.quad 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" newline bitfld.quad 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.quad 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.quad 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.quad 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" newline bitfld.quad 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" bitfld.quad 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.quad 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.quad 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.quad 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.quad 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.quad 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" bitfld.quad 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" newline bitfld.quad 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.quad 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.quad 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.quad 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline rgroup.quad spr:0x34CB3++0x00 line.quad 0x00 "ICH_EISR_EL2,Interrupt Controller End of Interrupt Status Register" bitfld.quad 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register 2" "No interrupt,Interrupt" bitfld.quad 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register 1" "No interrupt,Interrupt" newline bitfld.quad 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register 0" "No interrupt,Interrupt" rgroup.quad spr:0x34CB5++0x00 line.quad 0x00 "ICH_ELRSR_EL2,Interrupt Controller Empty List Register Status Register" bitfld.quad 0x00 3. "STATUS3,Status bit for List register 3" "Interrupt,No interrupt" bitfld.quad 0x00 2. "STATUS2,Status bit for List register 2" "Interrupt,No interrupt" bitfld.quad 0x00 1. "STATUS1,Status bit for List register 1" "Interrupt,No interrupt" newline bitfld.quad 0x00 0. "STATUS0,Status bit for List register 0" "Interrupt,No interrupt" if (((per.q(spr:0x34CB1))&0x400000)==0x400000) group.quad spr:0x34CB0++0x00 line.quad 0x00 "ICH_HCR_EL2,Interrupt Controller Hypervisor Control Register" bitfld.quad 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped" bitfld.quad 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped" newline bitfld.quad 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped" bitfld.quad 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped" bitfld.quad 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped" newline bitfld.quad 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled" newline bitfld.quad 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" newline bitfld.quad 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled" else group.quad spr:0x34CB0++0x00 line.quad 0x00 "ICH_HCR_EL2,Interrupt Controller Hypervisor Control Register" bitfld.quad 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped" newline bitfld.quad 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped" bitfld.quad 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped" bitfld.quad 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped" newline bitfld.quad 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled" newline bitfld.quad 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" newline bitfld.quad 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled" endif if (((per.q(spr:0x34CC0+0x0))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x0)++0x00 line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x0)++0x00 line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif if (((per.q(spr:0x34CC0+0x1))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x1)++0x00 line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x1)++0x00 line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif if (((per.q(spr:0x34CC0+0x2))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x2)++0x00 line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x2)++0x00 line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif if (((per.q(spr:0x34CC0+0x3))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x3)++0x00 line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x3)++0x00 line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif rgroup.quad spr:0x34CB2++0x00 line.quad 0x00 "ICH_MISR_EL2,Interrupt Controller Maintenance Interrupt State Register" bitfld.quad 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted" bitfld.quad 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted" bitfld.quad 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted" newline bitfld.quad 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted" bitfld.quad 0x00 3. "NP,No Pending" "Not asserted,Asserted" bitfld.quad 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted" newline bitfld.quad 0x00 1. "U,Underflow" "Not asserted,Asserted" bitfld.quad 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted" group.quad spr:0x34CB7++0x00 line.quad 0x00 "ICH_VMCR_EL2,Interrupt Controller Virtual Machine Control Register" hexmask.quad.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface" bitfld.quad 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" bitfld.quad 0x00 18.--20. "VBPR1,Virtual Binary Point Register Group 1" "Reserved,[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" newline bitfld.quad 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled" bitfld.quad 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate registers,Same register" bitfld.quad 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs" newline bitfld.quad 0x00 2. "VACKCTL,Virtual FIQ enable" "1022,Corresponding interrupt" bitfld.quad 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled" bitfld.quad 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled" rgroup.quad spr:0x34CB1++0x00 line.quad 0x00 "ICH_VTR_EL2,Interrupt Controller VGIC Type Register" bitfld.quad 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline bitfld.quad 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported" bitfld.quad 0x00 21. "A3V,Affinity 3 Valid" "Only zero values supported,Non-zero values supported" bitfld.quad 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,Not supported" newline bitfld.quad 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Not supported,Supported" bitfld.quad 0x00 0.--4. "LISTREGS,The number of implemented List registers minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree.end tree "Debug Registers" rgroup.quad spr:0x23010++0x00 line.quad 0x00 "MDCCSR_EL0,Debug Comms Channel Status Register" bitfld.quad 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.quad 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" group.quad spr:0x20020++0x00 line.quad 0x00 "MDCCINT_EL1,Debug Comms Channel Interrupt Enable register" bitfld.quad 0x00 30. "RX,DCC interrupt enable controls" "Disabled,Enabled" bitfld.quad 0x00 29. "TX,DCC interrupt enable controls" "Disabled,Enabled" group.quad spr:0x23040++0x00 line.quad 0x00 "DBGDTR_EL0,Half Duplex Data Transfer Register" hexmask.quad.long 0x00 32.--63. 1. "HIGHWORD,Writes to this register set DTRRX to the value in this field and do not change RXfull" hexmask.quad.long 0x00 0.--31. 1. "LOWWORD,Writes to this register set DTRTX to the value in this field and set TXfull to 1" rgroup.quad spr:0x23050++0x00 line.quad 0x00 "DBGDTRRX_EL0,Full Duplex Receive Data Transfer Register" wgroup.quad spr:0x23050++0x00 line.quad 0x00 "DBGDTRTX_EL0,Full Duplex Transmit Data Transfer Register" group.quad spr:0x24070++0x00 line.quad 0x00 "DBGVCR32_EL2,Vector Catch Register" bitfld.quad 0x00 31. "NSF,FIQ vector catch enable in Non-secure state" "Low,High" bitfld.quad 0x00 30. "NSI,IRQ vector catch enable in Non-secure state" "Low,High" bitfld.quad 0x00 28. "NSD,Data Abort vector catch enable in Non-secure state" "Low,High" bitfld.quad 0x00 27. "NSP,Prefetch Abort vector catch enable in Non-secure state" "Low,High" newline bitfld.quad 0x00 26. "NSS,Supervisor Call (SVC) vector catch enable in Non-secure state" "Low,High" bitfld.quad 0x00 25. "NSU,Undefined Instruction vector catch enable in Non-secure state" "Low,High" bitfld.quad 0x00 7. "SF,FIQ vector catch enable in Secure state" "Low,High" bitfld.quad 0x00 6. "SI,IRQ vector catch enable in Secure state" "Low,High" newline bitfld.quad 0x00 4. "SD,Data Abort vector catch enable in Secure state" "Low,High" bitfld.quad 0x00 3. "SP,Prefetch Abort vector catch enable in Secure state" "Low,High" bitfld.quad 0x00 2. "SS,Supervisor Call (SVC) vector catch enable in Secure state" "Low,High" bitfld.quad 0x00 1. "SU,Undefined Instruction vector catch enable in Secure state" "Low,High" group.quad spr:0x20002++0x00 line.quad 0x00 "OSDTRRX_EL1,OS Lock Data Transfer Register" if (((per.q(spr:0x20114))&0x02)==0x02) group.quad spr:0x20022++0x00 line.quad 0x00 "MDSCR_EL1,Monitor Debug System Control Register" bitfld.quad 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.quad 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" bitfld.quad 0x00 27. "RXO,Save/restore bit" "Low,High" bitfld.quad 0x00 26. "TXU,Save/restore bit" "Low,High" newline bitfld.quad 0x00 22.--23. "INTDIS,Save/restore bits" "0,1,2,3" bitfld.quad 0x00 21. "TDA,Save/restore bit" "Low,High" bitfld.quad 0x00 15. "MDE,Monitor debug events" "Disabled,Enabled" bitfld.quad 0x00 14. "HDE,Save/restore bit" "Low,High" newline bitfld.quad 0x00 13. "KDE,Local (kernel) debug enable" "Disabled,Enabled" bitfld.quad 0x00 12. "TDCC,Trap accesses to the debug comms channel in EL0" "Disabled,Enabled" bitfld.quad 0x00 6. "ERR,Save/restore bit" "Low,High" bitfld.quad 0x00 0. "SS,Software step control" "Disabled,Enabled" else group.quad spr:0x20022++0x00 line.quad 0x00 "MDSCR_EL1,Monitor Debug System Control Register" rbitfld.quad 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" rbitfld.quad 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" rbitfld.quad 0x00 27. "RXO,Save/restore bit" "Low,High" rbitfld.quad 0x00 26. "TXU,Save/restore bit" "Low,High" newline rbitfld.quad 0x00 22.--23. "INTDIS,Save/restore bits" "0,1,2,3" rbitfld.quad 0x00 21. "TDA,Save/restore bit" "Low,High" bitfld.quad 0x00 15. "MDE,Monitor debug events" "Disabled,Enabled" bitfld.quad 0x00 14. "HDE,Save/restore bit" "Low,High" newline bitfld.quad 0x00 13. "KDE,Local (kernel) debug enable" "Disabled,Enabled" bitfld.quad 0x00 12. "TDCC,Trap accesses to the debug comms channel in EL0" "Disabled,Enabled" rbitfld.quad 0x00 6. "ERR,Save/restore bit" "Low,High" bitfld.quad 0x00 0. "SS,Software step control" "Disabled,Enabled" endif group.quad spr:0x20032++0x00 line.quad 0x00 "OSDTRTX_EL1,OS Lock Data Transfer Register" group.quad spr:0x20062++0x00 line.quad 0x00 "OSECCR_EL1,OS Lock Exception Catch Control Register" rgroup.quad spr:0x20100++0x00 line.quad 0x00 "MDRAR_EL1,Debug ROM Address Register" hexmask.quad 0x00 12.--47. 0x10 "ROMADDR,ROM base physical address" bitfld.quad 0x00 0.--1. "VALID,ROM address valid" "Invalid,Reserved,Reserved,Valid" wgroup.quad spr:0x20104++0x00 line.quad 0x00 "OSLAR_EL1,OS Lock Access Register" bitfld.quad 0x00 0. "OSLK,OS lock" "Unlock,Lock" rgroup.quad spr:0x20114++0x00 line.quad 0x00 "OSLSR_EL1,OS Lock Status Register" bitfld.quad 0x00 2. "NTT,Not 32-bit access" "Low,?..." bitfld.quad 0x00 1. "OSLK,OS lock status" "Not locked,Locked" bitfld.quad 0x00 0. 3. "OSLM,OS lock model implemented field" "Reserved,Reserved,Impelemented,?..." group.quad spr:0x20134++0x00 line.quad 0x00 "OSDLR_EL1,OS Double-lock Register" bitfld.quad 0x00 0. "DLK,OS double-lock control" "Not locked,Locked" group.quad spr:0x20144++0x00 line.quad 0x00 "DBGPRCR_EL1,Debug Power/Reset Control Register" bitfld.quad 0x00 0. "CORENPDRQ,Core no powerdown request" "No,Yes" group.quad spr:0x20786++0x00 line.quad 0x00 "DBGCLAIMSET_EL1,Claim Tag register Set" bitfld.quad 0x00 7. "CT7,Claim Tag 7 Set" "Reserved,Set" bitfld.quad 0x00 6. "CT6,Claim Tag 6 Set" "Reserved,Set" bitfld.quad 0x00 5. "CT5,Claim Tag 5 Set" "Reserved,Set" bitfld.quad 0x00 4. "CT4,Claim Tag 4 Set" "Reserved,Set" newline bitfld.quad 0x00 3. "CT3,Claim Tag 3 Set" "Reserved,Set" bitfld.quad 0x00 2. "CT2,Claim Tag 2 Set" "Reserved,Set" bitfld.quad 0x00 1. "CT1,Claim Tag 1 Set" "Reserved,Set" bitfld.quad 0x00 0. "CT0,Claim Tag 0 Set" "Reserved,Set" group.quad spr:0x20796++0x00 line.quad 0x00 "DBGCLAIMCLR_EL1,Claim Tag register Clear" bitfld.quad 0x00 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared" bitfld.quad 0x00 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared" bitfld.quad 0x00 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared" bitfld.quad 0x00 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared" newline bitfld.quad 0x00 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared" bitfld.quad 0x00 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared" bitfld.quad 0x00 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared" bitfld.quad 0x00 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared" rgroup.quad spr:0x207E6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status Register" bitfld.quad 0x00 6.--7. "SNID,Secure non-invasive debug" "Not implemented,Reserved,Disabled,Enabled" bitfld.quad 0x00 4.--5. "SID,Secure invasive debug" "Not implemented,Reserved,Disabled,Enabled" bitfld.quad 0x00 2.--3. "NSNID,Non-secure non-invasive debug" "Not implemented,Reserved,Reserved,Enabled" bitfld.quad 0x00 0.--1. "NSID,Non-secure invasive debug" "Not implemented,Reserved,Disabled,Enabled" tree.end tree "Breakpoint Registers" tree "Breakpoint 0" if (((per.q(spr:0x20005+0x0))&0xF00000)<=0x100000) group.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x04 "VA,Bits[48:2] of the address value for comparison" elif (((((per.q(spr:0x20005+0x0))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x0))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0x700000))) group.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif ((((per.q(spr:0x20005+0x0))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x00)) group.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif ((((per.q(spr:0x20005+0x0))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x80000)) group.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison" elif ((((per.q(spr:0x20005+0x0))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x00)) group.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif ((((per.q(spr:0x20005+0x0))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x80000)) group.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif ((((per.q(spr:0x20005+0x0))&0xF00000)>=0xC00000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0xD00000)) group.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2" elif ((((per.q(spr:0x20005+0x0))&0xF00000)>=0xE00000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0xF00000)) group.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison against CONTEXTIDR_EL1" else rgroup.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" endif if (((per.q(spr:0x20005+0x0))&0x2000)==0x2000) if (((per.q(spr:0x20005+0x0))&0xC000)==0x0000) group.quad spr:(0x20005+0x0)++0x00 line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x0))&0xC000)==0x4000) group.quad spr:(0x20005+0x0)++0x00 line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x0))&0xC000)==0x8000) group.quad spr:(0x20005+0x0)++0x00 line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x0)++0x00 line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif else if (((per.q(spr:0x20005+0x0))&0xC000)==0xC000) group.quad spr:(0x20005+0x0)++0x00 line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x0)++0x00 line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,User,User/System" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif endif tree.end tree "Breakpoint 1" if (((per.q(spr:0x20005+0x10))&0xF00000)<=0x100000) group.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x04 "VA,Bits[48:2] of the address value for comparison" elif (((((per.q(spr:0x20005+0x10))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x10))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0x700000))) group.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif ((((per.q(spr:0x20005+0x10))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x00)) group.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif ((((per.q(spr:0x20005+0x10))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x80000)) group.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison" elif ((((per.q(spr:0x20005+0x10))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x00)) group.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif ((((per.q(spr:0x20005+0x10))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x80000)) group.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif ((((per.q(spr:0x20005+0x10))&0xF00000)>=0xC00000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0xD00000)) group.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2" elif ((((per.q(spr:0x20005+0x10))&0xF00000)>=0xE00000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0xF00000)) group.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison against CONTEXTIDR_EL1" else rgroup.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" endif if (((per.q(spr:0x20005+0x10))&0x2000)==0x2000) if (((per.q(spr:0x20005+0x10))&0xC000)==0x0000) group.quad spr:(0x20005+0x10)++0x00 line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x10))&0xC000)==0x4000) group.quad spr:(0x20005+0x10)++0x00 line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x10))&0xC000)==0x8000) group.quad spr:(0x20005+0x10)++0x00 line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x10)++0x00 line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif else if (((per.q(spr:0x20005+0x10))&0xC000)==0xC000) group.quad spr:(0x20005+0x10)++0x00 line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x10)++0x00 line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,User,User/System" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif endif tree.end tree "Breakpoint 2" if (((per.q(spr:0x20005+0x20))&0xF00000)<=0x100000) group.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x04 "VA,Bits[48:2] of the address value for comparison" elif (((((per.q(spr:0x20005+0x20))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x20))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0x700000))) group.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif ((((per.q(spr:0x20005+0x20))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x00)) group.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif ((((per.q(spr:0x20005+0x20))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x80000)) group.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison" elif ((((per.q(spr:0x20005+0x20))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x00)) group.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif ((((per.q(spr:0x20005+0x20))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x80000)) group.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif ((((per.q(spr:0x20005+0x20))&0xF00000)>=0xC00000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0xD00000)) group.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2" elif ((((per.q(spr:0x20005+0x20))&0xF00000)>=0xE00000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0xF00000)) group.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison against CONTEXTIDR_EL1" else rgroup.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" endif if (((per.q(spr:0x20005+0x20))&0x2000)==0x2000) if (((per.q(spr:0x20005+0x20))&0xC000)==0x0000) group.quad spr:(0x20005+0x20)++0x00 line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x20))&0xC000)==0x4000) group.quad spr:(0x20005+0x20)++0x00 line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x20))&0xC000)==0x8000) group.quad spr:(0x20005+0x20)++0x00 line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x20)++0x00 line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif else if (((per.q(spr:0x20005+0x20))&0xC000)==0xC000) group.quad spr:(0x20005+0x20)++0x00 line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x20)++0x00 line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,User,User/System" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif endif tree.end tree "Breakpoint 3" if (((per.q(spr:0x20005+0x30))&0xF00000)<=0x100000) group.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x04 "VA,Bits[48:2] of the address value for comparison" elif (((((per.q(spr:0x20005+0x30))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x30))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0x700000))) group.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif ((((per.q(spr:0x20005+0x30))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x00)) group.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif ((((per.q(spr:0x20005+0x30))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x80000)) group.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison" elif ((((per.q(spr:0x20005+0x30))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x00)) group.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif ((((per.q(spr:0x20005+0x30))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x80000)) group.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif ((((per.q(spr:0x20005+0x30))&0xF00000)>=0xC00000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0xD00000)) group.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2" elif ((((per.q(spr:0x20005+0x30))&0xF00000)>=0xE00000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0xF00000)) group.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison against CONTEXTIDR_EL1" else rgroup.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" endif if (((per.q(spr:0x20005+0x30))&0x2000)==0x2000) if (((per.q(spr:0x20005+0x30))&0xC000)==0x0000) group.quad spr:(0x20005+0x30)++0x00 line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x30))&0xC000)==0x4000) group.quad spr:(0x20005+0x30)++0x00 line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x30))&0xC000)==0x8000) group.quad spr:(0x20005+0x30)++0x00 line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x30)++0x00 line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif else if (((per.q(spr:0x20005+0x30))&0xC000)==0xC000) group.quad spr:(0x20005+0x30)++0x00 line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x30)++0x00 line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,User,User/System" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif endif tree.end tree "Breakpoint 4" if (((per.q(spr:0x20005+0x40))&0xF00000)<=0x100000) group.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x04 "VA,Bits[48:2] of the address value for comparison" elif (((((per.q(spr:0x20005+0x40))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x40))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0x700000))) group.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif ((((per.q(spr:0x20005+0x40))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x00)) group.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif ((((per.q(spr:0x20005+0x40))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x80000)) group.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison" elif ((((per.q(spr:0x20005+0x40))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x00)) group.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif ((((per.q(spr:0x20005+0x40))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x80000)) group.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif ((((per.q(spr:0x20005+0x40))&0xF00000)>=0xC00000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0xD00000)) group.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2" elif ((((per.q(spr:0x20005+0x40))&0xF00000)>=0xE00000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0xF00000)) group.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison against CONTEXTIDR_EL1" else rgroup.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" endif if (((per.q(spr:0x20005+0x40))&0x2000)==0x2000) if (((per.q(spr:0x20005+0x40))&0xC000)==0x0000) group.quad spr:(0x20005+0x40)++0x00 line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x40))&0xC000)==0x4000) group.quad spr:(0x20005+0x40)++0x00 line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x40))&0xC000)==0x8000) group.quad spr:(0x20005+0x40)++0x00 line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x40)++0x00 line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif else if (((per.q(spr:0x20005+0x40))&0xC000)==0xC000) group.quad spr:(0x20005+0x40)++0x00 line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x40)++0x00 line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,User,User/System" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif endif tree.end tree "Breakpoint 5" if (((per.q(spr:0x20005+0x50))&0xF00000)<=0x100000) group.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x04 "VA,Bits[48:2] of the address value for comparison" elif (((((per.q(spr:0x20005+0x50))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x50))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0x700000))) group.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif ((((per.q(spr:0x20005+0x50))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x00)) group.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif ((((per.q(spr:0x20005+0x50))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x80000)) group.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison" elif ((((per.q(spr:0x20005+0x50))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x00)) group.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif ((((per.q(spr:0x20005+0x50))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x80000)) group.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif ((((per.q(spr:0x20005+0x50))&0xF00000)>=0xC00000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0xD00000)) group.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2" elif ((((per.q(spr:0x20005+0x50))&0xF00000)>=0xE00000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0xF00000)) group.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison against CONTEXTIDR_EL1" else rgroup.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" endif if (((per.q(spr:0x20005+0x50))&0x2000)==0x2000) if (((per.q(spr:0x20005+0x50))&0xC000)==0x0000) group.quad spr:(0x20005+0x50)++0x00 line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x50))&0xC000)==0x4000) group.quad spr:(0x20005+0x50)++0x00 line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x50))&0xC000)==0x8000) group.quad spr:(0x20005+0x50)++0x00 line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x50)++0x00 line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif else if (((per.q(spr:0x20005+0x50))&0xC000)==0xC000) group.quad spr:(0x20005+0x50)++0x00 line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x50)++0x00 line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,User,User/System" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif endif tree.end tree.end tree "Watchpoint Control Registers" tree "Watchpoint 0" group.quad spr:(0x20006+0x0)++0x00 line.quad 0x00 "DBGWVR0_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x04 "ADDRESS,Data address" if (((per.q(spr:0x20007+0x0))&0x2000)==0x0000) if (((per.q(spr:0x20007+0x0))&0xC000)==0xC000) group.quad spr:(0x20007+0x0)++0x00 line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" else group.quad spr:(0x20007+0x0)++0x00 line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" endif else if (((per.q(spr:0x20007+0x0))&0xC000)==0x0000) group.quad spr:(0x20007+0x0)++0x00 line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" elif (((per.q(spr:0x20007+0x0))&0xC000)==0x8000) group.quad spr:(0x20007+0x0)++0x00 line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" else group.quad spr:(0x20007+0x0)++0x00 line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Superisor,System/Supervisor,Reserved,User/System/Supervisor" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" endif endif tree.end tree "Watchpoint 1" group.quad spr:(0x20006+0x10)++0x00 line.quad 0x00 "DBGWVR1_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x04 "ADDRESS,Data address" if (((per.q(spr:0x20007+0x10))&0x2000)==0x0000) if (((per.q(spr:0x20007+0x10))&0xC000)==0xC000) group.quad spr:(0x20007+0x10)++0x00 line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" else group.quad spr:(0x20007+0x10)++0x00 line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" endif else if (((per.q(spr:0x20007+0x10))&0xC000)==0x0000) group.quad spr:(0x20007+0x10)++0x00 line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" elif (((per.q(spr:0x20007+0x10))&0xC000)==0x8000) group.quad spr:(0x20007+0x10)++0x00 line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" else group.quad spr:(0x20007+0x10)++0x00 line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Superisor,System/Supervisor,Reserved,User/System/Supervisor" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" endif endif tree.end tree "Watchpoint 2" group.quad spr:(0x20006+0x20)++0x00 line.quad 0x00 "DBGWVR2_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x04 "ADDRESS,Data address" if (((per.q(spr:0x20007+0x20))&0x2000)==0x0000) if (((per.q(spr:0x20007+0x20))&0xC000)==0xC000) group.quad spr:(0x20007+0x20)++0x00 line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" else group.quad spr:(0x20007+0x20)++0x00 line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" endif else if (((per.q(spr:0x20007+0x20))&0xC000)==0x0000) group.quad spr:(0x20007+0x20)++0x00 line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" elif (((per.q(spr:0x20007+0x20))&0xC000)==0x8000) group.quad spr:(0x20007+0x20)++0x00 line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" else group.quad spr:(0x20007+0x20)++0x00 line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Superisor,System/Supervisor,Reserved,User/System/Supervisor" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" endif endif tree.end tree "Watchpoint 3" group.quad spr:(0x20006+0x30)++0x00 line.quad 0x00 "DBGWVR3_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x04 "ADDRESS,Data address" if (((per.q(spr:0x20007+0x30))&0x2000)==0x0000) if (((per.q(spr:0x20007+0x30))&0xC000)==0xC000) group.quad spr:(0x20007+0x30)++0x00 line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" else group.quad spr:(0x20007+0x30)++0x00 line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" endif else if (((per.q(spr:0x20007+0x30))&0xC000)==0x0000) group.quad spr:(0x20007+0x30)++0x00 line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" elif (((per.q(spr:0x20007+0x30))&0xC000)==0x8000) group.quad spr:(0x20007+0x30)++0x00 line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" else group.quad spr:(0x20007+0x30)++0x00 line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Superisor,System/Supervisor,Reserved,User/System/Supervisor" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" endif endif tree.end tree.end tree.end tree.open "AArch32" tree "ID Registers" rgroup.long c15:0x0000++0x0 line.long 0x0 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 "IMPL,Implementer code" bitfld.long 0x0 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. "ARCH,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8" newline hexmask.long.word 0x0 4.--15. 0x10 "PART,Primary Part Number" bitfld.long 0x0 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c15:0x0100++0x0 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..." bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." rgroup.long c15:0x0200++0x0 line.long 0x0 "TCMTR,TCM Type Register" rgroup.long c15:0x0300++0x0 line.long 0x0 "TLBTR,TLB Type Register" rgroup.long c15:0x0500++0x0 line.long 0x0 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor" bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largely independent,?..." hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" newline hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field" hexmask.long.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Lowest level affinity field" rgroup.long c15:0x0600++0x0 line.long 0x0 "REVIDR,Revision ID Register" rgroup.long c15:0x0410++0x00 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..." bitfld.long 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..." bitfld.long 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..." bitfld.long 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..." bitfld.long 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,Implemented,?..." newline bitfld.long 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,VMSAv7,?..." rgroup.long c15:0x0510++0x00 line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Reserved,Reserved,No flushing,?..." bitfld.long 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." newline bitfld.long 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." rgroup.long c15:0x0610++0x00 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.long c15:0x0710++0x00 line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. "SS,Supersection support" "Supported,?..." bitfld.long 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..." bitfld.long 0x00 20.--23. "CW,Coherent walk" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. "HCMOSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "HCMOMVA,Invalidate Cache MVA Support" "Reserved,Supported,?..." rgroup.long c15:0x0020++0x00 line.long 0x00 "ID_ISAR0,Instruction Set Attribute Register 0" bitfld.long 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..." newline bitfld.long 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..." rgroup.long c15:0x0120++0x00 line.long 0x00 "ID_ISAR1,Instruction Set Attribute Register 1" bitfld.long 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0220++0x00 line.long 0x00 "ID_ISAR2,Instruction Set Attribute Register 2" bitfld.long 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. "PSRI,PSR Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0320++0x00 line.long 0x00 "ID_ISAR3,Instruction Set Attribute Register 3" bitfld.long 0x00 28.--31. "TEEEI,Thumb-EE Extensions Support" "Not supported,?..." bitfld.long 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0420++0x00 line.long 0x00 "ID_ISAR4,Instruction Set Attribute Register 4" bitfld.long 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..." bitfld.long 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..." newline bitfld.long 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0520++0x00 line.long 0x00 "ID_ISAR5,Instruction Set Attribute Register 5" bitfld.long 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..." newline bitfld.long 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "SEVL,SEVL Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0010++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..." bitfld.long 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.long c15:0x0110++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..." bitfld.long 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..." bitfld.long 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." rgroup.long c15:0x0210++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Not implemented,Supported,?..." newline bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." rgroup.long c15:0x0310++0x00 line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" tree.end tree "System Control and Configuration" group.long c15:0x0001++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled" newline bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" newline bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad c15:0x100F0++0x01 line.quad 0x00 "CPUACTLR,CPU Auxiliary Control Register" bitfld.quad 0x00 44. "ENDCCASCI,Enable Data Cache Clean As data cache Clean/Invalidate" "Disabled,Enabled" bitfld.quad 0x00 30. "CDIDIS,Disable Cryptographic Dual Issue" "No,Yes" newline bitfld.quad 0x00 29. "DIDIS,Disable Dual Issue" "No,Yes" bitfld.quad 0x00 27.--28. "RADIS,Write streaming no-allocate threshold" "16th,128th,512th,Disabled" newline bitfld.quad 0x00 25.--26. "L1RADIS,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled" bitfld.quad 0x00 24. "DTAH,Disable Transient allocation hint" "No,Yes" newline bitfld.quad 0x00 23. "STBPFRS,Disable ReadUnique request for prefetch streams initiated by STB accesses" "No,Yes" bitfld.quad 0x00 22. "STBPFDIS,Disable prefetch streams initiated from STB accesses" "No,Yes" newline bitfld.quad 0x00 19.--20. "NPFSTRM,Number of independent data prefetch streams" "1 stream,2 streams,3 streams,4 streams" bitfld.quad 0x00 18. "DSTDIS,Enable device split throttle" "Disabled,Enabled" newline bitfld.quad 0x00 17. "STRIDE,Enable stride detection" "2 linefills,3 linefills" bitfld.quad 0x00 13.--15. "L1PCTL,L1 Data prefetch control" "Disabled,1,2,3,4,5,6,8" newline bitfld.quad 0x00 11. "DYNSDIS,Disable dynamic stride adjustment for prefetch streams" "No,Yes" bitfld.quad 0x00 10. "DODMBS,Disable optimized Data Memory Barrier behavior" "No,Yes" newline bitfld.quad 0x00 6. "L1DEIEN,L1 D-cache Data RAM Error Injection Enable" "Disabled,Enabled" group.quad c15:0x110F0++0x01 line.quad 0x00 "CPUECTLR,CPU Extended Control Register" bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled" bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" newline bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" if (((per.q(c15:0x120F0))&0x7F000000)==0x000000000) group.quad c15:0x120F0++0x01 line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "Way 0,Way 1,?..." newline hexmask.quad.word 0x00 0.--11. 1. "RAD,RAM address" elif (((per.q(c15:0x120F0))&0x7F000000)==0x01000000) group.quad c15:0x120F0++0x01 line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "Bank 0,Bank 1,?..." newline hexmask.quad.word 0x00 0.--11. 1. "RAD,RAM address" elif (((per.q(c15:0x120F0))&0x7F000000)==0x08000000) group.quad c15:0x120F0++0x01 line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "Way 0,Way 1,Way 2,Way 3,?..." newline hexmask.quad.word 0x00 0.--11. 1. "RAD,RAM address" elif (((per.q(c15:0x120F0))&0x7F000000)==0x09000000) group.quad c15:0x120F0++0x01 line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "Bank 0,Bank 1,Bank 2,Bank 3,Bank 4,Bank 5,Bank 6,Bank 7" newline hexmask.quad.word 0x00 0.--11. 0x01 "RAD,RAM address" elif (((per.q(c15:0x120F0))&0x7F000000)==0x0A000000) group.quad c15:0x120F0++0x01 line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "Dirty RAM,?..." newline hexmask.quad.word 0x00 0.--11. 0x01 "RAD,RAM address" elif (((per.q(c15:0x120F0))&0x7F000000)==0x18000000) group.quad c15:0x120F0++0x01 line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "Way 0,Way 1,?..." newline hexmask.quad.word 0x00 0.--11. 0x01 "RAD,RAM address" else group.quad c15:0x120F0++0x01 line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" hexmask.quad.word 0x00 0.--11. 0x01 "RAD,RAM address" endif group.long c15:0x0101++0x0 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled" bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled" bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled" group.long c15:0x0201++0x00 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 31. "ASEDIS,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x0 22.--23. "CP11,Coprocesor access control" "Denied,EL1 only,Reserved,Full" newline bitfld.long 0x0 20.--21. "CP10,Coprocesor access control" "Denied,EL1 only,Reserved,Full" group.long c15:0x0011++0x0 line.long 0x0 "SCR,Secure Configuration Register" bitfld.long 0x00 13. "TWE,Trap WFE Instructions" "Not trapped,Trapped" bitfld.long 0x00 12. "TWI,Trap WFI Instructions" "Not trapped,Trapped" newline bitfld.long 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted" bitfld.long 0x00 8. "HCE,Hypervisor Call enable" "No,Yes" newline bitfld.long 0x00 7. "SCD,Secure Monitor Call disable" "No,Yes" bitfld.long 0x00 5. "AW,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed" newline bitfld.long 0x00 4. "FW,Controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed" bitfld.long 0x00 3. "EA,External Abort exceptions handled in Abort mode or Monitor mode" "Not taken,Taken" newline bitfld.long 0x00 2. "FIQ,FIQ exceptions handled in FIQ mode or Monitor mode" "Not taken,Taken" bitfld.long 0x00 1. "IRQ,IRQ exceptions handled in IRQ mode or Monitor mode" "Not taken,Taken" newline bitfld.long 0x00 0. "NS,Secure mode" "Secure,Non-secure" group.long c15:0x0111++0x00 line.long 0x00 "SDER,Secure Debug Enable Register" bitfld.long 0x00 1. "SUNIDEN,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted" bitfld.long 0x00 0. "SUIDEN,Invasive Secure User Debug Enable bit" "Denied,Permitted" group.long c15:0x0131++0x00 line.long 0x00 "SDCR,Secure Debug Control Register" bitfld.long 0x00 21. "EPMAD,External debugger access to Performance Monitors registers disabled" "No,Yes" bitfld.long 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint registers disabled" "No,Yes" newline bitfld.long 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. "SPD,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled" group.long c15:0x0211++0x00 line.long 0x00 "NSACR,Non-Secure Access Control Register" bitfld.long 0x00 15. "NSASEDIS,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x00 11. "CP11,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted" newline bitfld.long 0x00 10. "CP10,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted" group.long c15:0x000C++0x00 line.long 0x00 "VBAR,Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address" group.long c15:0x010C++0x00 line.long 0x00 "MVBAR,Monitor Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address" rgroup.long c15:0x001C++0x00 line.long 0x00 "ISR,Interrupt Status Register" bitfld.long 0x00 8. "A,External abort pending flag" "Not pending,Pending" bitfld.long 0x00 7. "I,Interrupt pending flag" "Not pending,Pending" newline bitfld.long 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending" group.long c15:0x020C++0x00 line.long 0x00 "RMR,Reset Management Register" bitfld.long 0x00 1. "RR,Reset Request" "Not requested,Requested" bitfld.long 0x00 0. "AA64,Determines which execution state the processor boots into after a warm reset" "AArch32,AArch64" rgroup.long c15:0x0015++0x00 line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" rgroup.long c15:0x0115++0x00 line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR" newline bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write" bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external,Async. external,Reserved,Reserved,Reserved,Sync. external/on TTW/L1,Sync. external/on TTW/L2,Sync. external/on TTW/L3,Sync. parity/on memory access,Async. parity/on memory access,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/L1,Sync. parity/on memory access/on TTW/L2,Sync. parity/on memory access/on TTW/L3,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Reserved,LDREX or STREX,?..." group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/L1,Sync. external/on TTW/L2,Sync. external/on TTW/L3,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/L1,Sync. parity/on memory access/on TTW/L2,Sync. parity/on memory access/on TTW/L3,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." else group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR" newline bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write" bitfld.long 0x00 4.--7. "DOMAIN,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" newline bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/section,Instruction cache maintenance,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/L1,Permission/section,Sync. external/L2,Permission/L2,TLB conflict,Reserved,Reserved,Reserved,Reserved,LDREX or STREX,Async. external,Reserved,Async. parity,Sync. parity,Reserved,Reserved,Sync. parity/L1,Reserved,Sync. parity/L2,?..." group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/L1,Permission/section,Sync. external/on TTW/L2,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/L1,Reserved,Sync. parity/on TTW/L2,?..." endif group.long c15:0x0006++0x00 line.long 0x00 "DFAR,Data Fault Address Register" group.long c15:0x0206++0x00 line.long 0x00 "IFAR,Instruction Fault Address Register" rgroup.long c15:0x103F++0x00 line.long 0x00 "CBAR,Configuration Base Address Register" hexmask.long.word 0x00 18.--31. 0x04 "PERIPHBASE[31:18],Periphbase[31:18]" hexmask.long.byte 0x00 0.--7. 0x01 "PERIPHBASE[39:32],Periphbase[39:32]" rgroup.long c15:0x000D++0x00 line.long 0x00 "FCSEIDR,FCSE Process ID register" group.long c15:0x020D++0x00 line.long 0x00 "TPIDRURW,User Read/Write Thread ID Register" rgroup.long c15:0x030D++0x00 line.long 0x00 "TPIDRURO,User Read-Only Thread ID Register" group.long c15:0x040D++0x00 line.long 0x00 "TPIDRPRW,EL1 only Thread ID Register" tree "System Instructions" wgroup.long c15:0x0017++0x00 line.long 0x00 "ICIALLUIS,ICIALLUIS" wgroup.long c15:0x0617++0x00 line.long 0x00 "BPIALLIS,BPIALLIS" wgroup.long c15:0x0057++0x00 line.long 0x00 "ICIALLU,ICIALLU" wgroup.long c15:0x0157++0x00 line.long 0x00 "ICIMVAU,ICIMVAU" wgroup.long c15:0x0457++0x00 line.long 0x00 "CP15ISB,CP15ISB" wgroup.long c15:0x0657++0x00 line.long 0x00 "BPIALL,BPIALL" wgroup.long c15:0x0757++0x00 line.long 0x00 "BPIMVA,BPIMVA" wgroup.long c15:0x0167++0x00 line.long 0x00 "DCIMVAC,DCIMVAC" wgroup.long c15:0x0267++0x00 line.long 0x00 "DCISW,DCISW" wgroup.long c15:0x0087++0x00 line.long 0x00 "ATS1CPR,ATS1CPR" wgroup.long c15:0x0187++0x00 line.long 0x00 "ATS1CPW,ATS1CPW" wgroup.long c15:0x0287++0x00 line.long 0x00 "ATS1CUR,ATS1CUR" wgroup.long c15:0x0387++0x00 line.long 0x00 "ATS1CUW,ATS1CUW" wgroup.long c15:0x0487++0x00 line.long 0x00 "ATS12NSOPR,ATS12NSOPR" wgroup.long c15:0x0587++0x00 line.long 0x00 "ATS12NSOPW,ATS12NSOPW" wgroup.long c15:0x0687++0x00 line.long 0x00 "ATS12NSOUR,ATS12NSOUR" wgroup.long c15:0x0787++0x00 line.long 0x00 "ATS12NSOUW,ATS12NSOUW" wgroup.long c15:0x01A7++0x00 line.long 0x00 "DCCMVAC,DCCMVAC" wgroup.long c15:0x02A7++0x00 line.long 0x00 "DCCSW,DCCSW" wgroup.long c15:0x04A7++0x00 line.long 0x00 "CP15DSB,CP15DSB" wgroup.long c15:0x05A7++0x00 line.long 0x00 "CP15DMB,CP15DMB" wgroup.long c15:0x01B7++0x00 line.long 0x00 "DCCMVAU,DCCMVAU" wgroup.long c15:0x01E7++0x00 line.long 0x00 "DCCIMVAC,DCCIMVAC" wgroup.long c15:0x02E7++0x00 line.long 0x00 "DCCISW,DCCISW" wgroup.long c15:0x4087++0x00 line.long 0x00 "ATS1HR,ATS1HR" wgroup.long c15:0x4187++0x00 line.long 0x00 "ATS1HW,ATS1HW" wgroup.long c15:0x0038++0x00 line.long 0x00 "TLBIALLIS,TLBIALLIS" wgroup.long c15:0x0138++0x00 line.long 0x00 "TLBIMVAIS,TLBIMVAIS" wgroup.long c15:0x0238++0x00 line.long 0x00 "TLBIASIDIS,TLBIASIDIS" wgroup.long c15:0x0338++0x00 line.long 0x00 "TLBIMVAAIS,TLBIMVAAIS" wgroup.long c15:0x0538++0x00 line.long 0x00 "TLBIMVALIS,TLBIMVALIS" wgroup.long c15:0x0738++0x00 line.long 0x00 "TLBIMVAALIS,TLBIMVAALIS" wgroup.long c15:0x0058++0x00 line.long 0x00 "ITLBIALL,ITLBIALL" wgroup.long c15:0x0158++0x00 line.long 0x00 "ITLBIMVA,ITLBIMVA" wgroup.long c15:0x0258++0x00 line.long 0x00 "ITLBIASID,ITLBIASID" wgroup.long c15:0x0068++0x00 line.long 0x00 "DTLBIALL,DTLBIALL" wgroup.long c15:0x0168++0x00 line.long 0x00 "DTLBIMVA,DTLBIMVA" wgroup.long c15:0x0268++0x00 line.long 0x00 "DTLBIASID,DTLBIASID" wgroup.long c15:0x0078++0x00 line.long 0x00 "TLBIALL,TLBIALL" wgroup.long c15:0x0178++0x00 line.long 0x00 "TLBIMVA,TLBIMVA" wgroup.long c15:0x0278++0x00 line.long 0x00 "TLBIASID,TLBIASID" wgroup.long c15:0x0378++0x00 line.long 0x00 "TLBIMVAA,TLBIMVAA" wgroup.long c15:0x0578++0x00 line.long 0x00 "TLBIMVAL,TLBIMVAL" wgroup.long c15:0x0778++0x00 line.long 0x00 "TLBIMVAAL,TLBIMVAAL" wgroup.long c15:0x4108++0x00 line.long 0x00 "TLBIIPAS2IS,TLBIIPAS2IS" wgroup.long c15:0x4508++0x00 line.long 0x00 "TLBIIPAS2LIS,TLBIIPAS2LIS" wgroup.long c15:0x4038++0x00 line.long 0x00 "TLBIALLHIS,TLBIALLHIS" wgroup.long c15:0x4138++0x00 line.long 0x00 "TLBIMVAHIS,TLBIMVAHIS" wgroup.long c15:0x4438++0x00 line.long 0x00 "TLBIALLNSNHIS,TLBIALLNSNHIS" wgroup.long c15:0x4538++0x00 line.long 0x00 "TLBIMVALHIS,TLBIMVALHIS" wgroup.long c15:0x4148++0x00 line.long 0x00 "TLBIIPAS2,TLBIIPAS2" wgroup.long c15:0x4548++0x00 line.long 0x00 "TLBIIPAS2L,TLBIIPAS2L" wgroup.long c15:0x4078++0x00 line.long 0x00 "TLBIALLH,TLBIALLH" wgroup.long c15:0x4178++0x00 line.long 0x00 "TLBIMVAH,TLBIMVAH" wgroup.long c15:0x4478++0x00 line.long 0x00 "TLBIALLNSNH,TLBIALLNSNH" wgroup.long c15:0x4578++0x00 line.long 0x00 "TLBIMVALH,TLBIMVALH" tree.end tree.end tree "Memory Management Unit" group.long c15:0x0001++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled" newline bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" newline bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.long c15:0x4001++0x0 line.long 0x00 "HSCTLR,System Control Register" bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced" bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x0 5. "CP15BEN,C15 barrier enable" "Disabled,Enabled" bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" newline bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" bitfld.long 0x0 0. "M,MMU enable" "Disabled,Enabled" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.quad c15:0x10020++0x01 line.quad 0x00 "TTBR0,Translation Table Base Register 0" hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" newline newline group.quad c15:0x11020++0x01 line.quad 0x00 "TTBR1,Translation Table Base Register 1" hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" newline newline group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 28.--29. "SH1,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.long 0x00 26.--27. "ORGN1,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 24.--25. "IRGN1,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 23. "EPD1,Translation Walk Disable for TTBR1" "No,Yes" bitfld.long 0x00 22. "A1,Selects TTBR0 or TTBR1 to defines the ASID" "TTBR0,TTBR1" newline bitfld.long 0x00 16.--18. "T1SZ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 7. "EPD0,Translation Walk Disable for TTBR0 region" "No,Yes" bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7" else group.long c15:0x0002++0x00 line.long 0x00 "TTBR0,Translation Table Base Register 0" hexmask.long 0x00 7.--31. 0x80 "TTB0,Translation table base 0 address" bitfld.long 0x00 6. 0. "IRGN,Inner region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 5. "NOS,Not Outer Shareable bit" "Outer,Inner" bitfld.long 0x00 3.--4. "RGN,RGN" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 1. "S,Shareable bit" "Non-shareable,Shareable" group.long c15:0x0102++0x00 line.long 0x00 "TTBR1,Translation Table Base Register 1" hexmask.long 0x00 7.--31. 0x80 "TTB1,Translation table base 1 address" bitfld.long 0x00 6. 0. "IRGN,Inner region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 5. "NOS,Not Outer Shareable bit" "Outer,Inner" bitfld.long 0x00 3.--4. "RGN,RGN" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 1. "S,Shareable bit" "Non-shareable,Shareable" group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 5. "PD1,Translation table walk disable for translations using TTBR1" "No,Yes" newline bitfld.long 0x00 4. "PD0,Translation table walk disable for translations using TTBR0" "No,Yes" bitfld.long 0x00 0.--2. "N,Width of the base address held in TTBR0" "0,1,2,3,4,5,6,7" newline newline newline newline endif group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 1.--47. 0x02 "BADDR,Translation table base address" group.long c15:0x4202++0x00 line.long 0x00 "HTCR,Hypervisor Translation Control Register" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7" group.long c15:0x0003++0x00 line.long 0x00 "DACR,Domain Access Control Register" bitfld.long 0x0 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager" bitfld.long 0x0 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager" bitfld.long 0x0 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager" bitfld.long 0x0 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager" bitfld.long 0x0 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager" bitfld.long 0x0 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager" bitfld.long 0x0 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager" bitfld.long 0x0 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager" bitfld.long 0x0 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager" if ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0047))&0x01)==0x00)) group.long c15:0x0047++0x00 line.long 0x00 "PAR,Physical Address Register" hexmask.long.tbyte 0x00 12.--31. 0x10 "PA,Physical Address" bitfld.long 0x00 11. "LPAE,Descriptor translation table format" "Short,Long" newline bitfld.long 0x00 10. "NOS,Not Outer Shareable attribute for the region" "No,Yes" bitfld.long 0x00 9. "NS,Non-secure" "No,Yes" newline bitfld.long 0x00 7. "SH,Shareable attribute for the region" "No,Yes" bitfld.long 0x00 4.--6. "INNER,Inner memory attributes for the region" "Non-cacheable,Device-nGnRnE,Reserved,Device-nGnRE,Reserved,Write-Back/Write-Allocate,Write-Through,Write-Back/No Write-Allocate" newline bitfld.long 0x00 2.--3. "OUTER,Outer memory attributes for the region" "Non-cacheable,Write-Back/Write-Allocate,Write-Through/No Write-Allocate,Write-Back/No Write-Allocate" bitfld.long 0x00 1. "SS,Supersection" "Disabled,Enabled" newline bitfld.long 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" elif ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0047))&0x01)==0x01)) group.long c15:0x0047++0x00 line.long 0x00 "PAR,Physical Address Register" newline bitfld.long 0x00 11. "LPAE,Descriptor translation table format" "Short,Long" newline bitfld.long 0x00 6. "FS[5],Fault status bit [5] - External abort type" "Internal,External" newline bitfld.long 0x00 1.--5. "FS[4:0],Fault status bit [4:0] - Abort source" "Reserved,Alignment,Debug,Access flag/L1,Instruction,Translation/L1,Access flag/L2,Translation/L2,Sync. external,Domain/L1,Reserved,Domain/L2,Sync. external/on TTW/L1,Permission/L1,Sync. external/on TTW/L2,Permission/L2,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupp. exclusive access,SError,Reserved,Reserved,Sync. parity/ECC on memory access,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Reserved,Sync. parity/ECC on TTW/L2,?..." newline bitfld.long 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" elif ((((per.l(c15:0x0202))&0x80000000)==0x80000000)&&(((per.l(c15:0x10070))&0x01)==0x00)) group.quad c15:0x10070++0x01 line.quad 0x00 "PAR,Physical Address Register" hexmask.quad.byte 0x00 56.--63. 1. "ATTR,Memory attributes for the returned PA" hexmask.quad.long 0x00 12.--39. 0x10 "PA,Physical Address" newline bitfld.quad 0x00 11. "LPAE,Descriptor translation table format" "Short,Long" bitfld.quad 0x00 9. "NS,Non-secure" "No,Yes" newline bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" else group.quad c15:0x10070++0x01 line.quad 0x00 "PAR,Physical Address Register" newline bitfld.quad 0x00 11. "LPAE,Descriptor translation table format" "Short,Long" bitfld.quad 0x00 9. "FSTAGE,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2" newline bitfld.quad 0x00 8. "S2WLK,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes" newline bitfld.quad 0x00 1.--6. "FST,Fault Status Field" "Address size/TTBR,Address size/L1,Address size/L2,Address size/L3,Reserved,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/L1,Sync. external/on TTW/L2,Sync. external/on TTW/L3,Sync. parity/ECC on memory access,Sync. parity/ECC on memory access,Reserved,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Sync. parity/ECC on TTW/L2,Sync. parity/ECC/on TTW/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" endif tree.open "Memory Attribute Indirection Registers" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x010D++0x00 line.long 0x0 "CONTEXTIDR,Context ID Register" else group.long c15:0x002A++0x0 line.long 0x00 "PRRR,Primary Region Remap Register" bitfld.long 0x00 31. "NOS7,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 30. "NOS6,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 29. "NOS5,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 28. "NOS4,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 27. "NOS3,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 26. "NOS2,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 25. "NOS1,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 24. "NOS0,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 19. "NS1,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped" bitfld.long 0x00 18. "NS0,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped" newline bitfld.long 0x00 17. "DS1,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped" bitfld.long 0x00 16. "DS0,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped" newline bitfld.long 0x00 14.--15. "TR7,{TEX[0] C B} = b111 Remap" "Strongly ordered,Device,Normal,?..." bitfld.long 0x00 12.--13. "TR6,{TEX[0] C B} = b110 Remap" "Strongly ordered,Device,Normal,?..." newline bitfld.long 0x00 10.--11. "TR5,{TEX[0] C B} = b101 Remap" "Strongly ordered,Device,Normal,?..." bitfld.long 0x00 8.--9. "TR4,{TEX[0] C B} = b100 Remap" "Strongly ordered,Device,Normal,?..." newline bitfld.long 0x00 6.--7. "TR3,{TEX[0] C B} = b011 Remap" "Strongly ordered,Device,Normal,?..." bitfld.long 0x00 4.--5. "TR2,{TEX[0] C B} = b010 Remap" "Strongly ordered,Device,Normal,?..." newline bitfld.long 0x00 2.--3. "TR1,{TEX[0] C B} = b001 Remap" "Strongly ordered,Device,Normal,?..." bitfld.long 0x00 0.--1. "TR0,{TEX[0] C B} = b000 Remap" "Strongly ordered,Device,Normal,?..." group.long c15:0x012A++0x0 line.long 0x00 "NMRR,Normal Memory Remap Register" bitfld.long 0x00 30.--31. "OR7,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 28.--29. "OR6,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 26.--27. "OR5,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 24.--25. "OR4,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 22.--23. "OR3,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 20.--21. "OR2,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 18.--19. "OR1,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 16.--17. "OR0,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 14.--15. "IR7,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 12.--13. "IR6,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 10.--11. "IR5,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 8.--9. "IR4,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 6.--7. "IR3,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 4.--5. "IR2,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 2.--3. "IR1,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 0.--1. "IR0,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" group.long c15:0x010D++0x00 line.long 0x0 "CONTEXTIDR,Context ID Register" hexmask.long.tbyte 0x00 8.--31. 1. "PROCID,Process identifier" hexmask.long.byte 0x00 0.--7. 1. "ASID,Address space identifier" endif rgroup.long c15:0x003A++0x00 line.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0" rgroup.long c15:0x013A++0x00 line.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1" rgroup.long c15:0x403A++0x00 line.long 0x00 "HAMAIR0,Hypervisor Auxiliary Memory Attribute Indirection Register 0" rgroup.long c15:0x413A++0x00 line.long 0x00 "HAMAIR1,Hypervisor Auxiliary Memory Attribute Indirection Register 1" tree.end tree.end tree "Virtualization Extensions" group.long c15:0x4000++0x0 line.long 0x00 "VPIDR,Virtualization Processor ID Register" hexmask.long.byte 0x0 24.--31. 0x1 "IMPL,Implementer code" bitfld.long 0x0 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0 16.--19. "ARCH,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8" hexmask.long.word 0x0 4.--15. 0x10 "PART,Primary Part Number" newline bitfld.long 0x0 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long c15:0x4500++0x00 line.long 0x00 "VMPIDR,Virtualization Multiprocessor ID Register" bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor" bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largely independent,?..." newline hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field" newline hexmask.long.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Lowest level affinity field" group.long c15:0x420D++0x00 line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register" group.long c15:0x4001++0x0 line.long 0x00 "HSCTLR,System Control Register" bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced" bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x0 5. "CP15BEN,C15 barrier enable" "Disabled,Enabled" bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" newline bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" bitfld.long 0x0 0. "M,MMU enable" "Disabled,Enabled" group.long c15:0x4101++0x00 line.long 0x00 "HACTLR,Hypervisor Auxiliary Control Register" bitfld.long 0x00 6. "L2ACTLR,L2ACTLR write access control" "Disabled,Enabled" bitfld.long 0x00 5. "L2ECTLR,L2ECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 4. "L2CTLR,L2CTLR write access control" "Disabled,Enabled" bitfld.long 0x00 1. "CPUECTLR,CPUECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 0. "CPUACTLR,CPUACTLR write access control" "Disabled,Enabled" rgroup.long c15:0x4711++0x00 line.long 0x00 "HACR,Hypervisor Auxiliary Configuration Register" group.long c15:0x4011++0x00 line.long 0x00 "HCR,Hypervisor Configuration Register" bitfld.long 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" bitfld.long 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes" newline bitfld.long 0x00 27. "TGE,Trap General Exceptions" "Disabled,Enabled" bitfld.long 0x00 26. "TVM,Trap Virtual Memory Controls" "Disabled,Enabled" newline bitfld.long 0x00 25. "TTLB,Trap TLB maintenance instructions" "Disabled,Enabled" bitfld.long 0x00 24. "TPU,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled" newline bitfld.long 0x00 23. "TPC,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled" bitfld.long 0x00 22. "TSW,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled" newline bitfld.long 0x00 21. "TAC,Trap Auxiliary Control Register Accesses" "Disabled,Enabled" bitfld.long 0x00 20. "TIDCP,Trap Lockdown" "Disabled,Enabled" newline bitfld.long 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" bitfld.long 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" newline bitfld.long 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" bitfld.long 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" newline bitfld.long 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" bitfld.long 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" newline bitfld.long 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" bitfld.long 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" newline bitfld.long 0x00 10.--11. "BSU,Barrier Shareability Upgrade" "No effect,Inner Shareable,Outer Shareable,Full system" bitfld.long 0x00 9. "FB,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled" newline bitfld.long 0x00 8. "VA,Virtual External Asynchronous Abort" "No aborted,Aborted" bitfld.long 0x00 7. "VI,Virtual IRQ interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 6. "VF,Virtual FIQ interrupt" "No interrupt,Interrupt" bitfld.long 0x00 5. "AMO,A-bit Mask Override" "No override,Override" newline bitfld.long 0x00 4. "IMO,I-bit Mask Override" "No override,Override" bitfld.long 0x00 3. "FMO,F-bit Mask Override" "No override,Override" newline bitfld.long 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" bitfld.long 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override" newline bitfld.long 0x00 0. "VM,Second Stage of Translation Enable" "Disabled,Enabled" group.long c15:0x4411++0x00 line.long 0x00 "HCR2,Hypervisor Configuration Register 2" bitfld.long 0x00 1. "ID,Stage 2 Instruction cache disable" "No,Yes" bitfld.long 0x00 0. "CD,Stage 2 Data cache disable" "No,Yes" group.long c15:0x4111++0x00 line.long 0x00 "HDCR,Hypervisor Debug Control Register" bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid" bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid" newline bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid" bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid" newline bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled" bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid" newline bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid" bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long c15:0x4211++0x00 line.long 0x00 "HCPTR,Hypervisor Architectural Feature Trap Register" bitfld.long 0x0 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped" bitfld.long 0x0 15. "TASE,Trap Advanced SIMD extensions" "Not trapped,Trapped" newline bitfld.long 0x0 11. "TCP11,Trap coprocessor 11" "Not trapped,Trapped" bitfld.long 0x0 10. "TCP10,Trap coprocessor 10" "Not trapped,Trapped" group.long c15:0x4311++0x00 line.long 0x00 "HSTR,Hypervisor System Trap Register" bitfld.long 0x00 16. "TTEE,Trap ThumbEE" "Not supported,?..." bitfld.long 0x00 15. "T15,Trap coprocessor primary register CRn = 15" "No effect,Trapped" newline bitfld.long 0x00 13. "T13,Trap coprocessor primary register CRn = 13" "No effect,Trapped" bitfld.long 0x00 12. "T12,Trap coprocessor primary register CRn = 12" "No effect,Trapped" newline bitfld.long 0x00 11. "T11,Trap coprocessor primary register CRn = 11" "No effect,Trapped" bitfld.long 0x00 10. "T10,Trap coprocessor primary register CRn = 10" "No effect,Trapped" newline bitfld.long 0x00 9. "T9,Trap coprocessor primary register CRn = 9" "No effect,Trapped" bitfld.long 0x00 8. "T8,Trap coprocessor primary register CRn = 8" "No effect,Trapped" newline bitfld.long 0x00 7. "T7,Trap coprocessor primary register CRn = 7" "No effect,Trapped" bitfld.long 0x00 6. "T6,Trap coprocessor primary register CRn = 6" "No effect,Trapped" newline bitfld.long 0x00 5. "T5,Trap coprocessor primary register CRn = 5" "No effect,Trapped" bitfld.long 0x00 3. "T3,Trap coprocessor primary register CRn = 3" "No effect,Trapped" newline bitfld.long 0x00 2. "T2,Trap coprocessor primary register CRn = 2" "No effect,Trapped" bitfld.long 0x00 1. "T1,Trap coprocessor primary register CRn = 1" "No effect,Trapped" newline bitfld.long 0x00 0. "T0,Trap coprocessor primary register CRn = 0" "No effect,Trapped" group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.long c15:0x4202++0x00 line.long 0x00 "HTCR,Hypervisor Translation Control Register" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7" group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad 0x00 1.--47. 1. "BADDR,Translation table base address" group.long c15:0x4212++0x00 line.long 0x00 "VTCR,Virtualization Translation Control Register" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "Second,First,?..." newline bitfld.long 0x00 4. "S,Sign-extension of the T0SZ field" "Low,High" bitfld.long 0x00 0.--3. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long c15:0x4006++0x00 line.long 0x00 "HDFAR,Hypervisor Data Fault Address Register" rgroup.long c15:0x4015++0x00 line.long 0x00 "HADFSR,Hypervisor Auxiliary Data Fault Status Syndrome Register" rgroup.long c15:0x4115++0x00 line.long 0x00 "HAIFSR,Hypervisor Auxiliary Instruction Fault Status Register" if ((per.l(c15:0x04025)&0xFC000000)==(0x00000000||0x38000000||0x88000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" elif (((per.l(c15:0x4025))&0xFC000000)==0x4000000) if (((per.l(c15:0x4025))&0x1000000)==0x1000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid" bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid" bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" endif elif (((per.l(c15:0x4025))&0xFC000000)==(0xC000000||0x20000000||0x14000000)) if (((per.l(c15:0x4025))&0x1000000)==0x1000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid" bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 17.--19. "OPC2,The Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "OPC1,The Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRN,The CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--8. "RT,The Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1.--4. "CRM,The CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "MCR,MRC/VMRS" else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid" bitfld.long 0x00 17.--19. "OPC2,The Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14.--16. "OPC1,The Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--13. "CRN,The CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5.--8. "RT,The Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. "CRM,The CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "MCR,MRC/VMRS" endif elif (((per.l(c15:0x4025))&0xFC000000)==(0x10000000||0x30000000)) if (((per.l(c15:0x4025))&0x1000000)==0x1000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid" bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "OPC1,The Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--13. "RT2,The Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5.--8. "RT,The Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. "CRM,The CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "MCRR,MRRC" else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid" bitfld.long 0x00 16.--19. "OPC1,The Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--13. "RT2,The Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--8. "RT,The Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1.--4. "CRM,The CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "MCRR,MRRC" endif elif (((per.l(c15:0x4025))&0xFC000000)==0x18000000) if (((per.l(c15:0x4025))&0x1000000)==0x1000000) if (((per.l(c15:0x4025))&0x08)==0x08) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid" bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" newline bitfld.long 0x00 1.--3. "AM,Addressing mode" "Imm unindexed,Imm post-indexed,Imm offset,Imm pre-indexed,Literal unindexed (A32),Reserved,Literal offset (A32),?..." bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "STC,LDC" else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid" bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--8. "RN,The Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Imm unindexed,Imm post-indexed,Imm offset,Imm pre-indexed,Literal unindexed (A32),Reserved,Literal offset (A32),?..." newline bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "STC,LDC" endif else if (((per.l(c15:0x4025))&0x08)==0x08) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid" hexmask.long.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Imm unindexed,Imm post-indexed,Imm offset,Imm pre-indexed,Literal unindexed (A32),Reserved,Literal offset (A32),?..." newline bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "STC,LDC" else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid" hexmask.long.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" newline bitfld.long 0x00 5.--8. "RN,The Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" newline bitfld.long 0x00 1.--3. "AM,Addressing mode" "Imm unindexed,Imm post-indexed,Imm offset,Imm pre-indexed,Literal unindexed (A32),Reserved,Literal offset (A32),?..." bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "STC,LDC" endif endif elif (((per.l(c15:0x4025))&0xFC000000)==0x1C000000) if (((per.l(c15:0x4025))&0x1000000)==0x1000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid" bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5. "TA,Indicates trapped use of Advanced SIMD functionality" "Not occurred,Occurred" bitfld.long 0x00 0.--3. "COPROC,The number of the coprocessor accessed by the trapped operation" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CP10,?..." else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid" bitfld.long 0x00 5. "TA,Indicates trapped use of Advanced SIMD functionality" "Not occurred,Occurred" newline bitfld.long 0x00 0.--3. "COPROC,The number of the coprocessor accessed by the trapped operation" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CP10,?..." endif elif (((per.l(c15:0x4025))&0xFC000000)==(0x44000000||0x48000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif ((((per.l(c15:0x4025))&0xFC000000)==(0x80000000||0x84000000))&&(((per.l(c15:0x4025))&0x3F)==0x10)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 10. "FNV,FAR not Valid" "HIFAR valid,HIFAR invalid" newline bitfld.long 0x00 9. "EA,External abort type" "Internal,External" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not ECC/Not on TTBW,Reserved,Reserved,Reserved,Reserved,SEA/Not ECC/On TTBW lvl1,SEA/Not ECC/On TTBW lvl2,SEA/Not ECC/On TTBW lvl3,SPE on mem access/Not on TTBW,Reserved,Reserved,Reserved,Reserved,SPE on mem access/On TTBW lvl1,SPE on mem access/On TTBW lvl2,SPE on mem access/On TTBW lvl3,Reserved,Reserved,Debug (only from Hypervisor mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,?..." elif ((((per.l(c15:0x4025))&0xFC000000)==(0x80000000||0x84000000))&&(((per.l(c15:0x4025))&0x3F)!=0x10)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 9. "EA,External abort type" "Internal,External" newline bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred" bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not ECC/Not on TTBW,Reserved,Reserved,Reserved,Reserved,SEA/Not ECC/On TTBW lvl1,SEA/Not ECC/On TTBW lvl2,SEA/Not ECC/On TTBW lvl3,SPE on mem access/Not on TTBW,Reserved,Reserved,Reserved,Reserved,SPE on mem access/On TTBW lvl1,SPE on mem access/On TTBW lvl2,SPE on mem access/On TTBW lvl3,Reserved,Reserved,Debug (only from Hypervisor mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,?..." elif (((per.l(c15:0x4025))&0xFD000000)==(0x91000000||0x95000000)) if (((per.l(c15:0x4025))&0x3F)==(0x11)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Invalid,Valid" bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.long 0x00 16.--19. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14. "AR,Acquire/Release semantics present" "Absent,Present" bitfld.long 0x00 10.--11. "AET,Asynchronous Error Type" "UC,UEU,UEO/CE,UER" newline bitfld.long 0x00 9. "EA,External abort type" "Internal,External" bitfld.long 0x00 8. "CM,Cache maintenance" "Not generated,Generated" newline bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred" bitfld.long 0x00 6. "WNR,Write not Read as abort cause" "Read,Write" newline bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not ECC/Not on TTBW,SError int,Reserved,Reserved,Reserved,SEA/Not ECC/On TTBW lvl1,SEA/Not ECC/On TTBW lvl2,SEA/Not ECC/On TTBW lvl3,SPE on mem access/Not on TTBW,SError int from parity/ECC err on mem access,Reserved,Reserved,Reserved,SPE on mem access/On TTBW lvl1,SPE on mem access/On TTBW lvl2,SPE on mem access/On TTBW lvl3,Reserved,Alignment fault,Debug (only from Hypervisor mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Lockdown fault,Unsupp Exclusive acc fault,?..." else if (((per.l(c15:0x4025))&0x3F)==(0x10)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Invalid,Valid" bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.long 0x00 16.--19. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14. "AR,Acquire/Release semantics present" "Absent,Present" bitfld.long 0x00 10. "FNV,FAR not Valid" "Valid,Invalid" newline bitfld.long 0x00 9. "EA,External abort type" "Internal,External" bitfld.long 0x00 8. "CM,Cache maintenance" "Not generated,Generated" newline bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred" bitfld.long 0x00 6. "WNR,Write not Read as abort cause" "Read,Write" newline bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not ECC/Not on TTBW,SError int,Reserved,Reserved,Reserved,SEA/Not ECC/On TTBW lvl1,SEA/Not ECC/On TTBW lvl2,SEA/Not ECC/On TTBW lvl3,SPE on mem access/Not on TTBW,SError int from parity/ECC err on mem access,Reserved,Reserved,Reserved,SPE on mem access/On TTBW lvl1,SPE on mem access/On TTBW lvl2,SPE on mem access/On TTBW lvl3,Reserved,Alignment fault,Debug (only from Hypervisor mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Lockdown fault,Unsupp Exclusive acc fault,?..." else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Invalid,Valid" bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.long 0x00 16.--19. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14. "AR,Acquire/Release semantics present" "Absent,Present" bitfld.long 0x00 9. "EA,External abort type" "Internal,External" newline bitfld.long 0x00 8. "CM,Cache maintenance" "Not generated,Generated" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred" newline bitfld.long 0x00 6. "WNR,Write not Read as abort cause" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not ECC/Not on TTBW,SError int,Reserved,Reserved,Reserved,SEA/Not ECC/On TTBW lvl1,SEA/Not ECC/On TTBW lvl2,SEA/Not ECC/On TTBW lvl3,SPE on mem access/Not on TTBW,SError int from parity/ECC err on mem access,Reserved,Reserved,Reserved,SPE on mem access/On TTBW lvl1,SPE on mem access/On TTBW lvl2,SPE on mem access/On TTBW lvl3,Reserved,Alignment fault,Debug (only from Hypervisor mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Lockdown fault,Unsupp Exclusive acc fault,?..." endif endif elif (((per.l(c15:0x4025))&0xFD000000)==(0x90000000||0x94000000)) if (((per.l(c15:0x4025))&0x3F)==(0x11)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Invalid,Valid" bitfld.long 0x00 10.--11. "AET,Asynchronous Error Type" "UC,UEU,UEO/CE,UER" newline bitfld.long 0x00 9. "EA,External abort type" "Internal,External" bitfld.long 0x00 8. "CM,Cache maintenance" "Not generated,Generated" newline bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred" bitfld.long 0x00 6. "WNR,Write not Read as abort cause" "Read,Write" newline bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not ECC/Not on TTBW,SError int,Reserved,Reserved,Reserved,SEA/Not ECC/On TTBW lvl1,SEA/Not ECC/On TTBW lvl2,SEA/Not ECC/On TTBW lvl3,SPE on mem access/Not on TTBW,SError int from parity/ECC err on mem access,Reserved,Reserved,Reserved,SPE on mem access/On TTBW lvl1,SPE on mem access/On TTBW lvl2,SPE on mem access/On TTBW lvl3,Reserved,Alignment fault,Debug (only from Hypervisor mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Lockdown fault,Unsupp Exclusive acc fault,?..." else if (((per.l(c15:0x4025))&0x3F)==(0x10)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Invalid,Valid" bitfld.long 0x00 10. "FNV,FAR not Valid" "Valid,Invalid" newline bitfld.long 0x00 9. "EA,External abort type" "Internal,External" bitfld.long 0x00 8. "CM,Cache maintenance" "Not generated,Generated" newline bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred" bitfld.long 0x00 6. "WNR,Write not Read as abort cause" "Read,Write" newline bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not ECC/Not on TTBW,SError int,Reserved,Reserved,Reserved,SEA/Not ECC/On TTBW lvl1,SEA/Not ECC/On TTBW lvl2,SEA/Not ECC/On TTBW lvl3,SPE on mem access/Not on TTBW,SError int from parity/ECC err on mem access,Reserved,Reserved,Reserved,SPE on mem access/On TTBW lvl1,SPE on mem access/On TTBW lvl2,SPE on mem access/On TTBW lvl3,Reserved,Alignment fault,Debug (only from Hypervisor mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Lockdown fault,Unsupp Exclusive acc fault,?..." else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Invalid,Valid" bitfld.long 0x00 9. "EA,External abort type" "Internal,External" newline bitfld.long 0x00 8. "CM,Cache maintenance" "Not generated,Generated" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred" newline bitfld.long 0x00 6. "WNR,Write not Read as abort cause" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not ECC/Not on TTBW,SError int,Reserved,Reserved,Reserved,SEA/Not ECC/On TTBW lvl1,SEA/Not ECC/On TTBW lvl2,SEA/Not ECC/On TTBW lvl3,SPE on mem access/Not on TTBW,SError int from parity/ECC err on mem access,Reserved,Reserved,Reserved,SPE on mem access/On TTBW lvl1,SPE on mem access/On TTBW lvl2,SPE on mem access/On TTBW lvl3,Reserved,Alignment fault,Debug (only from Hypervisor mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Lockdown fault,Unsupp Exclusive acc fault,?..." endif endif elif (((per.l(c15:0x4025))&0xFD000000)==(0x4C000000||0x4D000000)) if (((per.l(c15:0x4025))&0xF0000)==(0x80000)) if (((per.l(c15:0x4025))&0x1000000)==(0x1000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid" bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 19. "CCKNOWNPASS,Trapped instruction" "Unconditional,Conditional" else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid" bitfld.long 0x00 19. "CCKNOWNPASS,Trapped instruction" "Unconditional,Conditional" endif else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 19. "CCKNOWNPASS,Trapped instruction" "Unconditional,Conditional" endif else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline hexmask.long 0x00 0.--24. 1. "ISS,Instruction specific syndrome" endif group.long c15:0x4206++0x00 line.long 0x00 "HIFAR,Hypervisor Instruction Fault Address Register" group.long c15:0x4406++0x00 line.long 0x00 "HPFAR,Hypervisor IPA Fault Address Register" hexmask.long 0x00 4.--31. 1. "FIPA[39:12],Bits [39:12] of the faulting intermediate physical address" tree.open "Hypervisor Memory Attribute Indirection Registers" group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" tree.end newline group.long c15:0x400C++0x00 line.long 0x00 "HVBAR,Hypervisor Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "HVBADDR,Hypervisor Vector Base Address" tree.end tree "Cache Control and Configuration" rgroup.long c15:0x0100++0x0 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..." bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." rgroup.long c15:0x1100++0x0 line.long 0x0 "CLIDR,Cache Level ID Register" bitfld.long 0x00 30.--31. "ICB,Inner cache boundary" "Not disclosed,?..." bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..." bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,No L2 cache,L1/L2 cleaned,?..." newline bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,L2 cache not implemented,L2 cache implemented,?..." bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..." bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "No cache,Reserved,Reserved,Reserved,Unified,?..." newline bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Separate I/D,?..." rgroup.long c15:0x1000++0x0 line.long 0x0 "CCSIDR,Current Cache Size ID Register" bitfld.long 0x00 31. "WT,Write-Through" "Not Supported,?..." bitfld.long 0x00 30. "WB,Write-Back" "Not Supported,Supported" bitfld.long 0x00 29. "RA,Read-Allocate" "Not Supported,Supported" newline bitfld.long 0x00 28. "WA,Write-Allocate" "Not Supported,Supported" hexmask.long.word 0x00 13.--27. 1. "SETS,Number of Sets" hexmask.long.word 0x00 3.--12. 1. "ASSOC,Associativity" newline bitfld.long 0x00 0.--2. "LSIZE,Line Size" "Reserved,Reserved,16 words,?..." group.long c15:0x2000++0x0 line.long 0x0 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,?..." bitfld.long 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction" tree "Level 1 memory system" rgroup.long c15:0x300F++0x00 line.long 0x00 "DL1DATA0,Data L1 Data 0 Register" rgroup.long c15:0x310F++0x00 line.long 0x00 "DL1DATA1,Data L1 Data 1 Register" rgroup.long c15:0x320F++0x00 line.long 0x00 "DL1DATA2,Data L1 Data 2 Register" rgroup.long c15:0x330F++0x00 line.long 0x00 "DL1DATA3,Data L1 Data 3 Register" wgroup.long c15:0x302F++0x00 line.long 0x00 "DCTROR,Data Cache Tag Read Operation Register" wgroup.long c15:0x312F++0x00 line.long 0x00 "ICTROR,Instruction Cache Tag Read Operation Register" wgroup.long c15:0x304F++0x00 line.long 0x00 "DCDROR,Data Cache Data Read Operation Register" wgroup.long c15:0x314F++0x00 line.long 0x00 "ICDROR,Instruction Cache Data Read Operation Register" wgroup.long c15:0x324F++0x00 line.long 0x00 "TLBDROR,TLB Data Read Operation Register" tree.end tree "Level 2 memory system" rgroup.long c15:0x1209++0x0 line.long 0x00 "L2CTLR,L2 Control Register" bitfld.long 0x00 24.--25. "NCPU,Number of CPU" "1,2,3,4" bitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Not implemented,ECC implemented" bitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Not implemented,ECC implemented" newline bitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycles" bitfld.long 0x00 0. "DRAMOL,L2 data RAM output latency" "2 cycles,3 cycles" group.long c15:0x1309++0x0 line.long 0x00 "L2ECTLR,L2 Extended Control Register" bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error" bitfld.long 0x00 29. "AACASYNCERR,AXI/ACE/CHI asynchronous error" "No error,Error" bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.long c15:0x100F++0x00 line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register" bitfld.long 0x00 30.--31. "L2VC,L2 victim Control" "0,1,2,3" newline bitfld.long 0x00 29. "L2DEIEN,L2 cache data RAM error injection enable" "Disabled,Enabled" bitfld.long 0x00 24. "L2TEIEN,L2 cache tag RAM error injection enable" "Disabled,Enabled" newline bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled" bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes" if (((per.q(c15:0x130F0))&0x7F000000)==0x10000000) group.quad c15:0x130F0++0x01 line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--21. "C/W,Indicates the RAM where the first memory error occurred" "Way 0,Way 1,Way 2,Way 3,Way 4,Way 5,Way 6,Way 7,?..." newline hexmask.quad.tbyte 0x00 3.--16. 0x08 "RAD,RAM address" elif (((per.q(c15:0x130F0))&0x7F000000)==0x11000000) group.quad c15:0x130F0++0x01 line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--21. "C/W,Indicates the RAM where the first memory error occurred" "Bank 0,Bank 1,Bank 2,Bank 3,Bank 4,Bank 5,Bank 6,Bank 7,?..." newline hexmask.quad.tbyte 0x00 3.--16. 0x08 "RAD,RAM address" elif (((per.q(c15:0x130F0))&0x7F000000)==0x12000000) group.quad c15:0x130F0++0x01 line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--21. "C/W,Indicates the RAM where the first memory error occurred" "CPU0/Way 0,CPU0/Way 1,CPU0/Way 2,CPU0/Way 3,CPU1/Way 0,CPU1/Way 1,CPU1/Way 2,CPU1/Way 3,CPU2/Way 0,CPU2/Way 1,CPU2/Way 2,CPU2/Way 3,CPU3/Way 0,CPU3/Way 1,CPU3/Way 2,CPU3/Way 3" newline hexmask.quad.tbyte 0x00 3.--16. 0x08 "RAD,RAM address" else group.quad c15:0x130F0++0x01 line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" newline hexmask.quad.tbyte 0x00 3.--16. 0x08 "RAD,RAM address" endif tree.end tree.end tree "System Performance Monitor" group.long c15:0x00c9++0x00 line.long 0x00 "PMCR,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code" hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code" bitfld.long 0x00 11.--15. "N,Number of counters implemented" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 6. "LC,Long cycle count enable" "Disabled,Enabled" newline bitfld.long 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes" bitfld.long 0x00 4. "X,Export Enable" "Disabled,Enabled" bitfld.long 0x00 3. "D,Clock Divider" "Every cycle,64th cycle" bitfld.long 0x00 2. "C,Clock Counter Reset" "No reset,?..." newline bitfld.long 0x00 1. "P,Performance Counter Reset" "No reset,?..." bitfld.long 0x00 0. "E,All Counters Enable" "Disabled,Enabled" group.long c15:0x01c9++0x00 line.long 0x00 "PMCNTENSET,Count Enable Set Register " bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" bitfld.long 0x00 5. "P5,Event Counter 5 enable bit" "Disabled,Enabled" bitfld.long 0x00 4. "P4,Event Counter 4 enable bit" "Disabled,Enabled" bitfld.long 0x00 3. "P3,Event Counter 3 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 2. "P2,Event Counter 2 enable bit" "Disabled,Enabled" bitfld.long 0x00 1. "P1,Event Counter 1 enable bit" "Disabled,Enabled" bitfld.long 0x00 0. "P0,Event Counter 0 enable bit" "Disabled,Enabled" group.long c15:0x02c9++0x00 line.long 0x00 "PMCNTENCLR,Count Enable Clear Register" eventfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" eventfld.long 0x00 5. "P5,Event Counter 5 clear bit" "Disabled,Enabled" eventfld.long 0x00 4. "P4,Event Counter 4 clear bit" "Disabled,Enabled" eventfld.long 0x00 3. "P3,Event Counter 3 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 2. "P2,Event Counter 2 clear bit" "Disabled,Enabled" eventfld.long 0x00 1. "P1,Event Counter 1 clear bit" "Disabled,Enabled" eventfld.long 0x00 0. "P0,Event Counter 0 clear bit" "Disabled,Enabled" group.long c15:0x03c9++0x00 line.long 0x00 "PMOVSR,Performance Monitor Overflow Status Register" eventfld.long 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow" eventfld.long 0x00 5. "P5,PMN5 overflow" "No overflow,Overflow" eventfld.long 0x00 4. "P4,PMN4 overflow" "No overflow,Overflow" eventfld.long 0x00 3. "P3,PMN3 overflow" "No overflow,Overflow" newline eventfld.long 0x00 2. "P2,PMN2 overflow" "No overflow,Overflow" eventfld.long 0x00 1. "P1,PMN1 overflow" "No overflow,Overflow" eventfld.long 0x00 0. "P0,PMN0 overflow" "No overflow,Overflow" wgroup.long c15:0x04c9++0x00 line.long 0x00 "PMSWINC,Performance Monitor Software Increment" bitfld.long 0x00 5. "P5,Increment PMN5" "No action,Increment" bitfld.long 0x00 4. "P4,Increment PMN4" "No action,Increment" bitfld.long 0x00 3. "P3,Increment PMN3" "No action,Increment" bitfld.long 0x00 2. "P2,Increment PMN2" "No action,Increment" newline bitfld.long 0x00 1. "P1,Increment PMN1" "No action,Increment" bitfld.long 0x00 0. "P0,Increment PMN0" "No action,Increment" group.long c15:0x05c9++0x00 line.long 0x00 "PMSELR,Performance Monitor Select Register" bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.open "Common Event Identification Registers" rgroup.long c15:0x06C9++0x00 line.long 0x00 "PMCEID0,Common Event Identification Register 0" bitfld.long 0x00 31. "EVENT31,L1 Data cache allocate" "Not implemented,?..." bitfld.long 0x00 30. "EVENT30,Chain" "Reserved,Implemented" newline bitfld.long 0x00 29. "EVENT29,Bus cycle" "Reserved,Implemented" bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,?..." bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Reserved,Implemented" newline bitfld.long 0x00 26. "EVENT26,Local memory error" "Reserved,Implemented" bitfld.long 0x00 25. "EVENT25,Bus access" "Reserved,Implemented" bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented" newline bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented" bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Reserved,Implemented" newline bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Reserved,Implemented" bitfld.long 0x00 19. "EVENT19,Data memory access" "Reserved,Implemented" bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Reserved,Implemented" newline bitfld.long 0x00 17. "EVENT17,Cycle" "Reserved,Implemented" bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Reserved,Implemented" bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass unaligned load or store" "Reserved,Implemented" newline bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,?..." bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed immediate branch" "Reserved,Implemented" bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Reserved,Implemented" newline bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Reserved,Implemented" bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Reserved,Implemented" bitfld.long 0x00 9. "EVENT9,Exception taken" "Reserved,Implemented" newline bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Reserved,Implemented" bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass store" "Reserved,Implemented" bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass load" "Reserved,Implemented" newline bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Reserved,Implemented" bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Reserved,Implemented" bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Reserved,Implemented" newline bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Reserved,Implemented" bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Reserved,Implemented" bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Reserved,Implemented" rgroup.long c15:0x07C9++0x0 line.long 0x00 "PMCEID1,Common Event Identification Register 1" bitfld.long 0x00 16. "EVENT48,Attributable Level 2 instruction TLB access" "Not implemented,?..." bitfld.long 0x00 15. "EVENT47,Attributable Level 2 data or unified TLB access" "Not implemented,?..." bitfld.long 0x00 14. "EVENT46,Attributable Level 2 instruction TLB refill" "Not implemented,?..." newline bitfld.long 0x00 13. "EVENT45,Attributable Level 2 data or unified TLB refill" "Not implemented,?..." bitfld.long 0x00 12. "EVENT44,Attributable Level 3 data or unified cache write-back" "Not implemented,?..." bitfld.long 0x00 11. "EVENT43,Attributable Level 3 data or unified cache access" "Not implemented,?..." newline bitfld.long 0x00 10. "EVENT42,Attributable Level 3 data or unified cache refill" "Not implemented,?..." bitfld.long 0x00 9. "EVENT41,Attributable Level 3 data or unified cache allocation without refill" "Not implemented,?..." bitfld.long 0x00 8. "EVENT40,Attributable Level 2 instruction cache refill" "Not implemented,?..." newline bitfld.long 0x00 7. "EVENT39,Attributable Level 2 instruction cache access" "Not implemented,?..." bitfld.long 0x00 6. "EVENT38,Level 1 instruction TLB access" "Not implemented,?..." bitfld.long 0x00 5. "EVENT37,Level 1 data or unified TLB access" "Not implemented,?..." newline bitfld.long 0x00 4. "EVENT36,No operation issued due to backend" "Not implemented,?..." bitfld.long 0x00 3. "EVENT35,No operation issued due to the frontend" "Not implemented,?..." bitfld.long 0x00 2. "EVENT34,Instruction architecturally executed mispredicted branch" "Not implemented,?..." newline bitfld.long 0x00 1. "EVENT33,Instruction architecturally executed branch" "Not implemented,?..." bitfld.long 0x00 0. "EVENT32,Level 2 data cache allocation without refill" "Not implemented,?..." tree.end newline if (((per.q(c15:0x00c9))&0x40)==0x40) group.quad c15:0x10090++0x01 line.quad 0x00 "PMCCNTR,Performance Monitor Cycle Count Register" else group.long c15:0x00d9++0x00 line.long 0x00 "PMCCNTR,Performance Monitor Cycle Count Register" endif if (((per.q(c15:0x05c9))&0x1F)==0x1F) group.long c15:0x01d9++0x00 line.long 0x00 "PMXEVTYPER,Performance Monitor Event Type Register" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" else group.long c15:0x01d9++0x00 line.long 0x00 "PMXEVTYPER,Performance Monitor Event Type Register" endif group.long c15:0x02d9++0x00 line.long 0x00 "PMXEVCNTR,Performance Monitor Event Count Register" group.long c15:0x00e9++0x00 line.long 0x00 "PMUSERENR,Performance Monitor User Enable Register" bitfld.long 0x00 3. "ER,Event counter read enable" "Disabled,Enabled" bitfld.long 0x00 2. "CR,Cycle counter read enable" "Disabled,Enabled" bitfld.long 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,User mode access enable" "Disabled,Enabled" group.long c15:0x01e9++0x00 line.long 0x00 "PMINTENSET,Performance Monitor Interrupt Enable Set" bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.long c15:0x02e9++0x00 line.long 0x00 "PMINTENCLR,Performance Monitor Interrupt Enable Clear" eventfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" eventfld.long 0x00 5. "P5,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 4. "P4,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 3. "P3,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 2. "P2,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 1. "P1,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 0. "P0,Overflow Interrupt Clear" "Disabled,Enabled" group.long c15:0x03e9++0x00 line.long 0x00 "PMOVSSET,Performance Monitor Overflow Flag Status Set Register" bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.long c15:0x8E++0x00 line.long 0x00 "PMEVCNTR0,Performance Monitors Event Count Register 0" group.long c15:(0x8E+0x40)++0x00 line.long 0x00 "PMEVTYPER0,Performance Monitors Selected Event Type Register 0" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x18E++0x00 line.long 0x00 "PMEVCNTR1,Performance Monitors Event Count Register 1" group.long c15:(0x18E+0x40)++0x00 line.long 0x00 "PMEVTYPER1,Performance Monitors Selected Event Type Register 1" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x28E++0x00 line.long 0x00 "PMEVCNTR2,Performance Monitors Event Count Register 2" group.long c15:(0x28E+0x40)++0x00 line.long 0x00 "PMEVTYPER2,Performance Monitors Selected Event Type Register 2" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x38E++0x00 line.long 0x00 "PMEVCNTR3,Performance Monitors Event Count Register 3" group.long c15:(0x38E+0x40)++0x00 line.long 0x00 "PMEVTYPER3,Performance Monitors Selected Event Type Register 3" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x48E++0x00 line.long 0x00 "PMEVCNTR4,Performance Monitors Event Count Register 4" group.long c15:(0x48E+0x40)++0x00 line.long 0x00 "PMEVTYPER4,Performance Monitors Selected Event Type Register 4" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x58E++0x00 line.long 0x00 "PMEVCNTR5,Performance Monitors Event Count Register 5" group.long c15:(0x58E+0x40)++0x00 line.long 0x00 "PMEVTYPER5,Performance Monitors Selected Event Type Register 5" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x07FE++0x00 line.long 0x00 "PMCCFILTR,Performance Monitors Cycle Count Filter Register" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" tree.end tree "System Timer Registers" group.long c15:0x000E++0x00 line.long 0x00 "CNTFRQ,Counter Frequency Register" rgroup.quad c15:0x100E0++0x01 line.quad 0x00 "CNTPCT,Counter Physical Count Register" group.long c15:0x001E++0x00 line.long 0x00 "CNTKCTL,Timer PL1 Control Register" bitfld.long 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" newline bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter CNTVCT and the frequency register CNTFRQ are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter CNTPCT and the frequency register CNTFRQ are accessible from EL0 modes" "Not accessible,Accessible" group.long c15:0x002E++0x00 line.long 0x00 "CNTP_TVAL,Counter PL1 Physical Compare Value Register" if (((per.q(c15:0x012E))&0x01)==0x01) group.long c15:0x012E++0x00 line.long 0x00 "CNTP_CTL,Counter PL1 Physical Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" else group.long c15:0x012E++0x00 line.long 0x00 "CNTP_CTL,Counter PL1 Physical Timer Control Register" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" endif group.long c15:0x003E++0x00 line.long 0x00 "CNTV_TVAL,Counter PL1 Virtual Timer Value Register" if (((per.q(c15:0x013E))&0x01)==0x01) group.long c15:0x013E++0x00 line.long 0x00 "CNTV_CTL,Counter PL1 Virtual Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" else group.long c15:0x013E++0x00 line.long 0x00 "CNTV_CTL,Counter PL1 Virtual Timer Control Register" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" endif group.quad c15:0x110E0++0x01 line.quad 0x00 "CNTVCT,Counter Virtual Count Register" group.quad c15:0x120E0++0x01 line.quad 0x00 "CNTP_CVAL,Counter PL1 Physical Compare Value Register" group.quad c15:0x130E0++0x01 line.quad 0x00 "CNTV_CVAL,Counter PL1 Virtual Compare Value Register" group.quad c15:0x140E0++0x01 line.quad 0x00 "CNTVOFF,Counter Virtual Offset Register" group.long c15:0x401E++0x00 line.long 0x00 "CNTHCTL,Counter Non-secure PL2 Control Register" bitfld.long 0x00 4.--7. "EVNTI,Select trigger for the event stream generated from counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" newline bitfld.long 0x00 1. "EL1VCTEN,Controls whether the Non-secure copies of the physical timer registers are accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 0. "EL1PCTEN,Controls whether the physical counter CNTPCT is accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible" group.long c15:0x402E++0x00 line.long 0x00 "CNTHP_TVAL,Counter Non-secure PL2 Physical Timer Value Register" if (((per.q(c15:0x412E))&0x01)==0x01) group.long c15:0x412E++0x00 line.long 0x00 "CNTHP_CTL,Counter Non-secure PL2 Physical Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" else group.long c15:0x412E++0x00 line.long 0x00 "CNTHP_CTL,Counter Non-secure PL2 Physical Timer Control Register" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" endif group.quad c15:0x160E0++0x01 line.quad 0x00 "CNTHP_CVAL,Counter Non-secure PL2 Physical Compare Value Register" tree.end tree "Generic Interrupt Controller System Registers" tree "AArch32 GIC Physical CPU Interface System Registers" tree.open "Interrupt Controller Active Priorities Registers" group.long c15:0x048C++0x00 line.long 0x00 "ICC_AP0R0,Active Priorities 0 Register 0" bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" newline bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" newline bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" newline bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.long c15:0x009C++0x00 line.long 0x00 "ICC_AP1R0,Active Priorities 1 Register 0" bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" newline bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" newline bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" newline bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline if (((per.q(c15:0x110C0))&0x10000000000)==0x00) wgroup.quad c15:0x110C0++0x01 line.quad 0x00 "ICC_ASGI1R,Alternate SGI Generation Register 1" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Target list,All PEs excluding self" newline hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" bitfld.quad 0x00 24.--27. "INTID,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" else wgroup.quad c15:0x110C0++0x01 line.quad 0x00 "ICC_ASGI1R,Alternate SGI Generation Register 1" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Target list,All PEs excluding self" newline bitfld.quad 0x00 24.--27. "INTID,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif group.long c15:0x038C++0x00 line.long 0x00 "ICC_BPR0,Binary Point Register 0" bitfld.long 0x00 0.--2. "BINARYPOINT,Interrupt priority field control and interrupt preemption control" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" group.long c15:0x03CC++0x00 line.long 0x00 "ICC_BPR1,Binary Point Register 1" bitfld.long 0x00 0.--2. "BINARYPOINT,Interrupt priority field control and interrupt preemption control" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" group.long c15:0x04CC++0x00 line.long 0x00 "ICC_CTLR,Interrupt Control Registers for EL1" rbitfld.long 0x00 19. "EXTRANGE,Extended INTID range" "Reserved,Supported" rbitfld.long 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255" newline rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported" rbitfld.long 0x00 14. "SEIS,SEI Support" "Not supported,Supported" rbitfld.long 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline rbitfld.long 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" bitfld.long 0x00 1. "EOIMODE,Alias of ICC_MCTLR.EOImode_EL1" "0,1" newline bitfld.long 0x00 0. "CBPR,Common Binary Point Register" "0,1" group.long c15:0x64CC++0x00 line.long 0x00 "ICC_MCTLR,Interrupt Control Registers for EL3" rbitfld.long 0x00 19. "EXTRANGE,Extended INTID range" "Reserved,Supported" rbitfld.long 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255" newline rbitfld.long 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported" rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported" rbitfld.long 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,Supported" newline rbitfld.long 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." rbitfld.long 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt register also deactivates the interrupt(Non-secure EL1 and EL2)" "Enabled,Disabled" bitfld.long 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt register also deactivates the interrupt(Secure EL1)" "Enabled,Disabled" bitfld.long 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt register also deactivates the interrupt(EL3)" "Enabled,Disabled" newline bitfld.long 0x00 1. "CBPR_EL1NS,Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate registers,Same register" bitfld.long 0x00 0. "CBPR_EL1S,Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate registers,Same register" if (((per.q(c15:0x04CC))&0x3800)==0x0000) wgroup.long c15:0x01BC++0x00 line.long 0x00 "ICC_DIR,Deactivate Interrupt Register" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.long c15:0x018C++0x00 line.long 0x00 "ICC_EOIR0,End Of Interrupt Register 0" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0 access" wgroup.long c15:0x01CC++0x00 line.long 0x00 "ICC_EOIR1,End Of Interrupt Register 1" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1 access." rgroup.long c15:0x028C++0x00 line.long 0x00 "ICC_HPPIR0,Highest Prioity Pending Interrupt Register 0" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt" rgroup.long c15:0x02CC++0x00 line.long 0x00 "ICC_HPPIR1,Highest Prioity Pending Interrupt Register 1" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt" else wgroup.long c15:0x01BC++0x00 line.long 0x00 "ICC_DIR,Deactivate Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.long c15:0x018C++0x00 line.long 0x00 "ICC_EOIR0,End Of Interrupt Register 0" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR0 access" wgroup.long c15:0x01CC++0x00 line.long 0x00 "ICC_EOIR1,End Of Interrupt Register 1" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR1 access." rgroup.long c15:0x028C++0x00 line.long 0x00 "ICC_HPPIR0,Highest Prioity Pending Interrupt Register 0" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt" rgroup.long c15:0x02CC++0x00 line.long 0x00 "ICC_HPPIR1,Highest Prioity Pending Interrupt Register 1" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt" endif hgroup.long c15:0x008C++0x00 hide.long 0x00 "ICC_IAR0,Interrupt Acknowledge Register 0" in hgroup.long c15:0x00CC++0x00 hide.long 0x00 "ICC_IAR1,Interrupt Acknowledge Register 1" in group.long c15:0x06CC++0x00 line.long 0x00 "ICC_IGRPEN0,Interrupt Group Enable Register 0" bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled" group.long c15:0x07CC++0x00 line.long 0x00 "ICC_IGRPEN1,Interrupt Group Enable Register 1" bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled" group.long c15:0x0064++0x00 line.long 0x00 "ICC_PMR,Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface" rgroup.long c15:0x03BC++0x00 line.long 0x00 "ICC_RPR,Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface" if (((per.q(c15:0x120C0))&0x10000000000)==0x00) wgroup.quad c15:0x120C0++0x01 line.quad 0x00 "ICC_SGI0R,SGI Generation Register 0" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Target list,All PEs excluding self" newline hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" else wgroup.quad c15:0x120C0++0x01 line.quad 0x00 "ICC_SGI0R,SGI Generation Register 0" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Target list,All PEs excluding self" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif if (((per.q(c15:0x100C0))&0x10000000000)==0x00) wgroup.quad c15:0x100C0++0x01 line.quad 0x00 "ICC_SGI1R,SGI Generation Register 1" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Target list,All PEs excluding self" newline hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" else wgroup.quad c15:0x100C0++0x01 line.quad 0x00 "ICC_SGI1R,SGI Generation Register 1" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Target list,All PEs excluding self" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif group.long c15:0x05CC++0x00 line.long 0x00 "ICC_SRE,System Register Enable Register for EL1" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" group.long c15:0x459C++0x00 line.long 0x00 "ICC_HSRE,System Register Enable Register for EL2" bitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1" "Disabled,Enabled" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" group.long c15:0x65CC++0x00 line.long 0x00 "ICC_MSRE,System Register Enable Register for EL3" bitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1 and ICC_SRE_EL2" "Disabled,Enabled" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" group.long c15:0x67CC++0x00 line.long 0x00 "ICC_MGRPEN1,Monitor Group1 Interrupt Group Enable" bitfld.long 0x00 1. "ENABLEGRP1S,Enables Group 1 interrupts for the Secure state" "Disabled,Enabled" bitfld.long 0x00 0. "ENABLEGRP1NS,Enables Group 1 interrupts for the Non-secure state" "Disabled,Enabled" tree.end tree "AArch32 Virtual Interface Control System Registers" tree.open "Hypervisor Active Priorities Registers" group.long c15:0x408C++0x00 line.long 0x00 "ICH_AP0R0,Interrupt Controller Hypervisor Active Priorities Group 0 Register 0" bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" newline bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" newline bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" newline bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.long c15:0x409C++0x00 line.long 0x00 "ICH_AP1R0,Interrupt Controller Hypervisor Active Priorities Group 1 Register 0" bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" newline bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" newline bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" newline bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline rgroup.long c15:0x438C++0x00 line.long 0x00 "ICH_EISR,Interrupt Controller End of Interrupt Status Register" bitfld.long 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register 1" "No interrupt,Interrupt" newline bitfld.long 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register 0" "No interrupt,Interrupt" rgroup.long c15:0x458C++0x00 line.long 0x00 "ICH_ELRSR,Interrupt Controller Empty List Register Status Register" bitfld.long 0x00 3. "STATUS3,Status bit for List register 3" "Interrupt,No interrupt" bitfld.long 0x00 2. "STATUS2,Status bit for List register 2" "Interrupt,No interrupt" bitfld.long 0x00 1. "STATUS1,Status bit for List register 1" "Interrupt,No interrupt" newline bitfld.long 0x00 0. "STATUS0,Status bit for List register 0" "Interrupt,No interrupt" if (((per.q(c15:0x41BC))&0x480000)==0x480000) group.long c15:0x40BC++0x00 line.long 0x00 "ICH_HCR,Interrupt Controller Hypervisor Control Register" bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped" bitfld.long 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped" newline bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped" newline bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled" elif (((per.q(c15:0x41BC))&0x480000)==0x080000) group.long c15:0x40BC++0x00 line.long 0x00 "ICH_HCR,Interrupt Controller Hypervisor Control Register" bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped" newline bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped" newline bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled" elif (((per.q(c15:0x41BC))&0x480000)==0x400000) group.long c15:0x40BC++0x00 line.long 0x00 "ICH_HCR,Interrupt Controller Hypervisor Control Register" bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped" newline bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped" newline bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled" else group.long c15:0x40BC++0x00 line.long 0x00 "ICH_HCR,Interrupt Controller Hypervisor Control Register" bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped" newline bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled" endif group.long c15:(0x40CC+0x0)++0x00 line.long 0x00 "ICH_LR0,Interrupt Controller List Register 0" group.long c15:(0x40CC+0x100)++0x00 line.long 0x00 "ICH_LR1,Interrupt Controller List Register 1" group.long c15:(0x40CC+0x200)++0x00 line.long 0x00 "ICH_LR2,Interrupt Controller List Register 2" group.long c15:(0x40CC+0x300)++0x00 line.long 0x00 "ICH_LR3,Interrupt Controller List Register 3" if (((per.q(c15:0x40EC+0x0))&0x20000000)==0x20000000) group.long c15:(0x40EC+0x0)++0x00 line.long 0x00 "ICH_LRC0,Interrupt Controller List Register Extension 0" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" else group.long c15:(0x40EC+0x0)++0x00 line.long 0x00 "ICH_LRC0,Interrupt Controller List Register Extension 0" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" bitfld.long 0x00 9. "EOI,Asserted EOI maintenance interrupt" "Not asserted,Asserted" endif if (((per.q(c15:0x40EC+0x100))&0x20000000)==0x20000000) group.long c15:(0x40EC+0x100)++0x00 line.long 0x00 "ICH_LRC1,Interrupt Controller List Register Extension 1" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" else group.long c15:(0x40EC+0x100)++0x00 line.long 0x00 "ICH_LRC1,Interrupt Controller List Register Extension 1" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" bitfld.long 0x00 9. "EOI,Asserted EOI maintenance interrupt" "Not asserted,Asserted" endif if (((per.q(c15:0x40EC+0x200))&0x20000000)==0x20000000) group.long c15:(0x40EC+0x200)++0x00 line.long 0x00 "ICH_LRC2,Interrupt Controller List Register Extension 2" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" else group.long c15:(0x40EC+0x200)++0x00 line.long 0x00 "ICH_LRC2,Interrupt Controller List Register Extension 2" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" bitfld.long 0x00 9. "EOI,Asserted EOI maintenance interrupt" "Not asserted,Asserted" endif if (((per.q(c15:0x40EC+0x300))&0x20000000)==0x20000000) group.long c15:(0x40EC+0x300)++0x00 line.long 0x00 "ICH_LRC3,Interrupt Controller List Register Extension 3" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" else group.long c15:(0x40EC+0x300)++0x00 line.long 0x00 "ICH_LRC3,Interrupt Controller List Register Extension 3" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" bitfld.long 0x00 9. "EOI,Asserted EOI maintenance interrupt" "Not asserted,Asserted" endif rgroup.long c15:0x42BC++0x00 line.long 0x00 "ICH_MISR,Interrupt Controller Maintenance Interrupt State Register" bitfld.long 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted" bitfld.long 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted" bitfld.long 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted" newline bitfld.long 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted" bitfld.long 0x00 3. "NP,No Pending" "Not asserted,Asserted" bitfld.long 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted" newline bitfld.long 0x00 1. "U,Underflow" "Not asserted,Asserted" bitfld.long 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted" group.long c15:0x478C++0x00 line.long 0x00 "ICH_VMCR,Interrupt Controller Virtual Machine Control Register" hexmask.long.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface" bitfld.long 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" bitfld.long 0x00 18.--20. "VBPR1,Virtual Binary Point Register Group 1" "Reserved,[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" newline bitfld.long 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled" bitfld.long 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate registers,Same register" bitfld.long 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs" newline bitfld.long 0x00 2. "VACKCTL,Virtual FIQ enable" "1022,Corresponding interrupt" bitfld.long 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled" group.long c15:0x449C++0x00 line.long 0x00 "ICH_VSEIR,Virtual System Error Interrupt Register" group.long c15:0x41BC++0x00 line.long 0x00 "ICH_VTR,Interrupt Controller VGIC Type Register" bitfld.long 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline bitfld.long 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported" bitfld.long 0x00 21. "A3V,Affinity 3 Valid" "Only zero values supported,Non-zero values supported" bitfld.long 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,Not supported" newline bitfld.long 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Not supported,Supported" bitfld.long 0x00 0.--4. "LISTREGS,The number of implemented List registers minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree.end tree "Debug Registers" tree "Coresight Management Registers" rgroup.long c14:0x0000++0x00 line.long 0x00 "DBGDIDR,Debug ID Register" bitfld.long 0x00 28.--31. "WRP,Number of Watchpoint Register Pairs" "Reserved,Reserved,Reserved,4,?..." bitfld.long 0x00 24.--27. "BRP,Number of Breakpoint Register Pairs" "Reserved,Reserved,Reserved,Reserved,Reserved,6,?..." bitfld.long 0x00 20.--23. "CTX_CMP,Number of BRPs with Context ID Comparison Capability" "Reserved,Two context,?..." newline hexmask.long.byte 0x00 16.--19. 1. "VERSION,Debug Architecture Version" bitfld.long 0x00 14. "NSUHD,Secure User halting debug-mode" "Reserved,Not supported" bitfld.long 0x00 12. "SE,Security Extensions implemented" "Reserved,Implemented" rgroup.long c14:0x0060++0x00 line.long 0x00 "DBGWFAR,Watchpoint Fault Address Register" group.long c14:0x0070++0x00 line.long 0x00 "DBGVCR,Debug Vector Catch register" bitfld.long 0x00 31. "FIQVCE_NS,FIQ vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 30. "IRQVCE_NS,IRQ vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 28. "DAVCE_NS,Data Abort vector catch in Non-secure state" "Disabled,Enabled" newline bitfld.long 0x00 27. "PAVCE_NS,Prefetch Abort vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 26. "SVCVCE_NS,SVC vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 25. "UIVCE_NS,Undefined instruction vector catch in Non-secure state" "Disabled,Enabled" newline bitfld.long 0x00 15. "FIQVCE_SM,FIQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 14. "IRQVCE_SM,IRQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 12. "DAVCE_SM,Data Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" newline bitfld.long 0x00 11. "PAVCE_SM,Prefetch Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 10. "SMCVCE_S,SMC vector catch enable in Secure state" "Disabled,Enabled" bitfld.long 0x00 7. "FIQVCE_S,FIQ vector catch in Secure state" "Disabled,Enabled" newline bitfld.long 0x00 6. "IRQVCE_S,IRG vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 4. "DAVCE_S,Data Abort vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 3. "PAVCE_S,Prefetch Abort vector catch in Secure state" "Disabled,Enabled" newline bitfld.long 0x00 2. "SVCVCE_S,SVC vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 1. "UIVCE_S,Undefined instruction vector catch in Secure state" "Disabled,Enabled" group.long c14:0x0020++0x000 line.long 0x00 "DBGDCCINT,DCC Interrupt Enable Register" bitfld.long 0x00 30. "RX,DCC interrupt request enable control for DTRRX" "Disabled,Enabled" bitfld.long 0x00 29. "TX,DCC interrupt request enable control for DTRTX" "Disabled,Enabled" group.long c14:0x0200++0x00 line.long 0x00 "DBGDTRRXEXT,Debug Receive Register (External View)" if (((per.l(c14:0x0411))&0x02)==0x02) group.long c14:0x0220++0x00 line.long 0x00 "DBGDSCREXT,Debug Status and Control Register (External View)" bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. "RXO,Used for save/restore of EDSCR.RXO" "Disabled,Enabled" newline bitfld.long 0x00 26. "TXU,Used for save/restore of EDSCR.TXU" "Disabled,Enabled" bitfld.long 0x00 22.--23. "INTDIS,Used for save/restore of EDSCR.INTdis" "Don't disabled interrupts,Disabled interrupts targeting non-sec EL1,Disabled all interrupts,Disabled all interrupts" bitfld.long 0x00 21. "TDA,Used for save/restore of EDSCR.TDA" "Disabled,Enabled" newline rbitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure" rbitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes" rbitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes" newline bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled" bitfld.long 0x00 14. "HDE,Used for save/restore of EDSCR.HDE" "Disabled,Enabled" bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes" newline bitfld.long 0x00 6. "ERR,Used for save/restore of EDSCR.ERR" "Disabled,Enabled" bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..." else group.long c14:0x0220++0x00 line.long 0x00 "DBGDSCREXT,Debug Status and Control Register (External View)" rbitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" rbitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" rbitfld.long 0x00 27. "RXO,Used for save/restore of EDSCR.RXO" "Disabled,Enabled" newline rbitfld.long 0x00 26. "TXU,Used for save/restore of EDSCR.TXU" "Disabled,Enabled" rbitfld.long 0x00 22.--23. "INTDIS,Used for save/restore of EDSCR.INTdis" "Don't disabled interrupts,Disabled interrupts targeting non-sec EL1,Disabled all interrupts,Disabled all interrupts" rbitfld.long 0x00 21. "TDA,Used for save/restore of EDSCR.TDA" "Disabled,Enabled" newline rbitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure" rbitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes" rbitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes" newline bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled" rbitfld.long 0x00 14. "HDE,Used for save/restore of EDSCR.HDE" "Disabled,Enabled" bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes" newline rbitfld.long 0x00 6. "ERR,Used for save/restore of EDSCR.ERR" "Disabled,Enabled" bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..." endif rgroup.long c14:0x0010++0x00 line.long 0x00 "DBGDSCRINT,Debug Status and Control Register (Internal View)" bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure" newline bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled" newline bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes" bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..." group.long c14:0x0230++0x00 line.long 0x00 "DBGDTRTXEXT,Debug Transmit Register (External View)" rgroup.long c14:0x0050++0x00 line.long 0x00 "DBGDTRTXINT,Debug Transmit Register (Internal View)" wgroup.long c14:0x0050++0x00 line.long 0x00 "DBGDTRRXINT,Debug Receive Register (Internal View)" group.long c14:0x0687++0x00 line.long 0x00 "DBGCLAIMSET,Claim Tag Set Register" bitfld.long 0x00 7. "CT7,Claim Tag 7 Set" "Not set,Set" bitfld.long 0x00 6. "CT6,Claim Tag 6 Set" "Not set,Set" bitfld.long 0x00 5. "CT5,Claim Tag 5 Set" "Not set,Set" newline bitfld.long 0x00 4. "CT4,Claim Tag 4 Set" "Not set,Set" bitfld.long 0x00 3. "CT3,Claim Tag 3 Set" "Not set,Set" bitfld.long 0x00 2. "CT2,Claim Tag 2 Set" "Not set,Set" newline bitfld.long 0x00 1. "CT1,Claim Tag 1 Set" "Not set,Set" bitfld.long 0x00 0. "CT0,Claim Tag 0 Set" "Not set,Set" group.long c14:0x0697++0x00 line.long 0x00 "DBGCLAIMCLR,Claim Tag Clear Register" bitfld.long 0x00 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared" bitfld.long 0x00 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared" bitfld.long 0x00 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared" newline bitfld.long 0x00 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared" bitfld.long 0x00 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared" bitfld.long 0x00 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared" newline bitfld.long 0x00 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared" bitfld.long 0x00 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared" rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Debug Authentication Status Register" bitfld.long 0x00 7. "SNDFI,Secure non-invasive debug features implementation" "No effect,Implemented" bitfld.long 0x00 6. "SNDE,Secure non-invasive debug enable" "Disabled,Enabled" bitfld.long 0x00 5. "SIDFI,Secure invasive debug features implementation" "No effect,Implemented" newline bitfld.long 0x00 4. "SIDE,Secure invasive debug enable" "Disabled,Enabled" bitfld.long 0x00 3. "NSNDFI,Non-secure non-invasive debug features implementation" "Not implemented,Implemented" bitfld.long 0x00 2. "NSNDE,Non-secure non-invasive debug enable" "0,1" newline bitfld.long 0x00 1. "NSIDFI,Non-secure invasive debug features implementation" "Not implemented,Implemented" bitfld.long 0x00 0. "NSIDE,Non-secure invasive debug enable" "0,1" rgroup.long c14:0x0707++0x00 line.long 0x00 "DBGDEVID2,Debug Device ID Register 2" rgroup.long c14:0x0717++0x00 line.long 0x00 "DBGDEVID1,Debug Device ID Register 1" bitfld.long 0x00 0.--3. "PCSROFFSET,This field defines the offset applied to DBGPCSR samples" "0,1,No offset,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c14:0x0727++0x000 line.long 0x00 "DBGDEVID,Debug Device ID Register 0" bitfld.long 0x00 28.--31. "CIDMASK,Specifies the level of support for the Context ID matching breakpoint masking capability" "Not implemented,?..." bitfld.long 0x00 24.--27. "AUXREGS,Specifies support for the Debug External Auxiliary Control Register" "Not implemented,?..." bitfld.long 0x00 20.--23. "DOUBLELOCK,Specifies support for the Debug OS Double Lock Register" "Reserved,Implemented,?..." newline bitfld.long 0x00 16.--19. "VIREXTNS,Specifies whether EL2 is implemented" "Reserved,Implemented,?..." bitfld.long 0x00 12.--15. "VECTORCATCH,Defines the form of the vector catch event implemented" "Implemented,?..." bitfld.long 0x00 8.--11. "BPADDRMASK,Indicates the level of support for the Immediate Virtual Address(IVA) matching breakpoint masking capability" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented" newline bitfld.long 0x00 4.--7. "WPADDRMASK,Indicates the level of support for the DVA matching watchpoint masking capability" "Reserved,Implemented,?..." bitfld.long 0x00 0.--3. "PCSAMPLE,Indicates the level of support for Program Counter sampling using debug registers 40 and 41" "Reserved,Reserved,Reserved,Implemented,?..." tree.end newline rgroup.quad c14:0x10010++0x001 line.quad 0x00 "DBGDRAR,Debug ROM Address Register" hexmask.quad.word 0x00 32.--47. 0x1 "ROMADDR,ROM physical address" hexmask.quad.tbyte 0x00 12.--31. 0x10 "ROMADDR,ROM physical address" bitfld.quad 0x00 1. "VALID1,ROM table address valid" "Not valid,Valid" newline bitfld.quad 0x00 0. "VALID0,ROM table address valid" "Not valid,Valid" rgroup.quad c14:0x10020++0x001 line.quad 0x00 "DBGDSAR,Debug Self Address Offset Register" wgroup.long c14:0x0401++0x000 line.long 0x00 "DBGOSLAR,Operating System Lock Access Register" rgroup.long c14:0x0411++0x000 line.long 0x00 "DBGOSLSR,Operating System Lock Status Register" bitfld.long 0x00 2. "NTT,32-Bit Access" "Not required,?..." bitfld.long 0x00 1. "OSLK,Status of the OS Lock" "Not locked,Locked" bitfld.long 0x00 0. 3. "OSLM,OS Lock Model implemented Bit" "Reserved,Reserved,Implemented,?..." if (((per.l(c14:0x0411))&0x2)==0x02) group.long c14:0x0260++0x000 line.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register" else rgroup.long c14:0x0260++0x000 line.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register" endif group.long c14:0x0431++0x000 line.long 0x00 "DBGOSDLR,Debug OS Double Lock Register" bitfld.long 0x00 0. "DLK,OS Double Lock control bit" "Not locked,Locked" group.long c14:0x0441++0x000 line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register" bitfld.long 0x00 0. "CORENPDRQ,Core No Power down Request" "Low,High" tree.end tree "Breakpoint Registers" if (((per.l(c14:0x500+0x0))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x0)++0x000 "Breakpoint 0" line.long 0x00 "DBGBVR0,Breakpoint Value Register" hexmask.long 0x00 2.--31. 0x04 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:0x500+0x0))&0xF00000)==(0x600000||0x700000||0x800000||0x900000||0xC00000||0xD00000||0xE00000||0xF00000)) rgroup.long c14:(0x0400+0x0)++0x000 "Breakpoint 0" line.long 0x00 "DBGBVR0,Breakpoint Value Register" else group.long c14:(0x0400+0x0)++0x000 "Breakpoint 0" line.long 0x00 "DBGBVR0,Breakpoint Value Register" endif if (((per.l(c14:0x0500+0x0))&0x2000)==0x2000) if (((per.l(c14:0x0500+0x0))&0xC000)==0xC000) group.long c14:(0x0500+0x0)++0x00 line.long 0x00 "DBGBCR0,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 0 is generated" "Supervisor,?..." bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" elif (((per.l(c14:0x0500+0x0))&0xC000)==0x8000) group.long c14:(0x0500+0x0)++0x00 line.long 0x00 "DBGBCR0,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 0 is generated" "Reserved,System,Reserved,User/System" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" else group.long c14:(0x0500+0x0)++0x00 line.long 0x00 "DBGBCR0,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 0 is generated" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" endif else group.long c14:(0x0500+0x0)++0x00 line.long 0x00 "DBGBCR0,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 0 is generated" "User/System,System,User,User/System" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" endif if (((per.l(c14:0x500+0x10))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x10)++0x000 "Breakpoint 1" line.long 0x00 "DBGBVR1,Breakpoint Value Register" hexmask.long 0x00 2.--31. 0x04 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:0x500+0x10))&0xF00000)==(0x600000||0x700000||0x800000||0x900000||0xC00000||0xD00000||0xE00000||0xF00000)) rgroup.long c14:(0x0400+0x10)++0x000 "Breakpoint 1" line.long 0x00 "DBGBVR1,Breakpoint Value Register" else group.long c14:(0x0400+0x10)++0x000 "Breakpoint 1" line.long 0x00 "DBGBVR1,Breakpoint Value Register" endif if (((per.l(c14:0x0500+0x10))&0x2000)==0x2000) if (((per.l(c14:0x0500+0x10))&0xC000)==0xC000) group.long c14:(0x0500+0x10)++0x00 line.long 0x00 "DBGBCR1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 1 is generated" "Supervisor,?..." bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" elif (((per.l(c14:0x0500+0x10))&0xC000)==0x8000) group.long c14:(0x0500+0x10)++0x00 line.long 0x00 "DBGBCR1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 1 is generated" "Reserved,System,Reserved,User/System" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" else group.long c14:(0x0500+0x10)++0x00 line.long 0x00 "DBGBCR1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 1 is generated" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" endif else group.long c14:(0x0500+0x10)++0x00 line.long 0x00 "DBGBCR1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 1 is generated" "User/System,System,User,User/System" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" endif if (((per.l(c14:0x500+0x20))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x20)++0x000 "Breakpoint 2" line.long 0x00 "DBGBVR2,Breakpoint Value Register" hexmask.long 0x00 2.--31. 0x04 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:0x500+0x20))&0xF00000)==(0x600000||0x700000||0x800000||0x900000||0xC00000||0xD00000||0xE00000||0xF00000)) rgroup.long c14:(0x0400+0x20)++0x000 "Breakpoint 2" line.long 0x00 "DBGBVR2,Breakpoint Value Register" else group.long c14:(0x0400+0x20)++0x000 "Breakpoint 2" line.long 0x00 "DBGBVR2,Breakpoint Value Register" endif if (((per.l(c14:0x0500+0x20))&0x2000)==0x2000) if (((per.l(c14:0x0500+0x20))&0xC000)==0xC000) group.long c14:(0x0500+0x20)++0x00 line.long 0x00 "DBGBCR2,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 2 is generated" "Supervisor,?..." bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" elif (((per.l(c14:0x0500+0x20))&0xC000)==0x8000) group.long c14:(0x0500+0x20)++0x00 line.long 0x00 "DBGBCR2,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 2 is generated" "Reserved,System,Reserved,User/System" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" else group.long c14:(0x0500+0x20)++0x00 line.long 0x00 "DBGBCR2,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 2 is generated" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" endif else group.long c14:(0x0500+0x20)++0x00 line.long 0x00 "DBGBCR2,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 2 is generated" "User/System,System,User,User/System" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" endif if (((per.l(c14:0x500+0x30))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x30)++0x000 "Breakpoint 3" line.long 0x00 "DBGBVR3,Breakpoint Value Register" hexmask.long 0x00 2.--31. 0x04 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:0x500+0x30))&0xF00000)==(0x600000||0x700000||0x800000||0x900000||0xC00000||0xD00000||0xE00000||0xF00000)) rgroup.long c14:(0x0400+0x30)++0x000 "Breakpoint 3" line.long 0x00 "DBGBVR3,Breakpoint Value Register" else group.long c14:(0x0400+0x30)++0x000 "Breakpoint 3" line.long 0x00 "DBGBVR3,Breakpoint Value Register" endif if (((per.l(c14:0x0500+0x30))&0x2000)==0x2000) if (((per.l(c14:0x0500+0x30))&0xC000)==0xC000) group.long c14:(0x0500+0x30)++0x00 line.long 0x00 "DBGBCR3,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 3 is generated" "Supervisor,?..." bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" elif (((per.l(c14:0x0500+0x30))&0xC000)==0x8000) group.long c14:(0x0500+0x30)++0x00 line.long 0x00 "DBGBCR3,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 3 is generated" "Reserved,System,Reserved,User/System" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" else group.long c14:(0x0500+0x30)++0x00 line.long 0x00 "DBGBCR3,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 3 is generated" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" endif else group.long c14:(0x0500+0x30)++0x00 line.long 0x00 "DBGBCR3,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 3 is generated" "User/System,System,User,User/System" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" endif if (((per.l(c14:0x500+0x40))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x40)++0x000 "Breakpoint 4" line.long 0x00 "DBGBVR4,Breakpoint Value Register" hexmask.long 0x00 2.--31. 0x04 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:0x500+0x40))&0xF00000)==(0x600000||0x700000||0x800000||0x900000||0xC00000||0xD00000||0xE00000||0xF00000)) rgroup.long c14:(0x0400+0x40)++0x000 "Breakpoint 4" line.long 0x00 "DBGBVR4,Breakpoint Value Register" else group.long c14:(0x0400+0x40)++0x000 "Breakpoint 4" line.long 0x00 "DBGBVR4,Breakpoint Value Register" endif if (((per.l(c14:0x0500+0x40))&0x2000)==0x2000) if (((per.l(c14:0x0500+0x40))&0xC000)==0xC000) group.long c14:(0x0500+0x40)++0x00 line.long 0x00 "DBGBCR4,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 4 is generated" "Supervisor,?..." bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" elif (((per.l(c14:0x0500+0x40))&0xC000)==0x8000) group.long c14:(0x0500+0x40)++0x00 line.long 0x00 "DBGBCR4,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 4 is generated" "Reserved,System,Reserved,User/System" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" else group.long c14:(0x0500+0x40)++0x00 line.long 0x00 "DBGBCR4,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 4 is generated" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" endif else group.long c14:(0x0500+0x40)++0x00 line.long 0x00 "DBGBCR4,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 4 is generated" "User/System,System,User,User/System" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" endif if (((per.l(c14:0x500+0x50))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x50)++0x000 "Breakpoint 5" line.long 0x00 "DBGBVR5,Breakpoint Value Register" hexmask.long 0x00 2.--31. 0x04 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:0x500+0x50))&0xF00000)==(0x600000||0x700000||0x800000||0x900000||0xC00000||0xD00000||0xE00000||0xF00000)) rgroup.long c14:(0x0400+0x50)++0x000 "Breakpoint 5" line.long 0x00 "DBGBVR5,Breakpoint Value Register" else group.long c14:(0x0400+0x50)++0x000 "Breakpoint 5" line.long 0x00 "DBGBVR5,Breakpoint Value Register" endif if (((per.l(c14:0x0500+0x50))&0x2000)==0x2000) if (((per.l(c14:0x0500+0x50))&0xC000)==0xC000) group.long c14:(0x0500+0x50)++0x00 line.long 0x00 "DBGBCR5,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 5 is generated" "Supervisor,?..." bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" elif (((per.l(c14:0x0500+0x50))&0xC000)==0x8000) group.long c14:(0x0500+0x50)++0x00 line.long 0x00 "DBGBCR5,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 5 is generated" "Reserved,System,Reserved,User/System" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" else group.long c14:(0x0500+0x50)++0x00 line.long 0x00 "DBGBCR5,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 5 is generated" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" endif else group.long c14:(0x0500+0x50)++0x00 line.long 0x00 "DBGBCR5,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 5 is generated" "User/System,System,User,User/System" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" endif group.long c14:0x0141++0x00 line.long 0x00 "DBGBXVR4,Debug Breakpoint Extended Value Register 4" hexmask.long.byte 0x00 0.--7. 1. "VMID,VMID value" group.long c14:0x0151++0x00 line.long 0x00 "DBGBXVR5,Debug Breakpoint Extended Value Register 5" hexmask.long.byte 0x00 0.--7. 1. "VMID,VMID value" tree.end tree "Watchpoint Control Registers" group.long c14:(0x0600+0x0)++0x000 "Watchpoint 0" line.long 0x00 "DBGWVR0,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" if (((per.l(c14:0x0700+0x0))&0x2000)==0x2000) if (((per.l(c14:0x0700+0x0))&0xC000)==0xC000) group.long c14:(0x0700+0x0)++0x000 line.long 0x00 "DBGWCR0,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x00 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x00 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x01 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x00 1.--2. "PAC,Determines the Exception level or levels at which a watchpoint debug event for watchpoint 0 is generated" "Supervisor,?..." bitfld.long 0x00 0. "WE,Watchpoint enable" "Disabled,Enabled" elif (((per.l(c14:0x0700+0x0))&0x8000)==0x8000) group.long c14:(0x0700+0x0)++0x000 line.long 0x00 "DBGWCR0,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x00 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x00 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x01 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x00 1.--2. "PAC,Determines the Exception level or levels at which a watchpoint debug event for watchpoint 0 is generated" "Reserved,System,Reserved,User/System" bitfld.long 0x00 0. "WE,Watchpoint enable" "Disabled,Enabled" else group.long c14:(0x0700+0x0)++0x000 line.long 0x00 "DBGWCR0,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x00 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x00 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x01 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x00 1.--2. "PAC,Determines the Exception level or levels at which a watchpoint debug event for watchpoint 0 is generated" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" bitfld.long 0x00 0. "WE,Watchpoint enable" "Disabled,Enabled" endif else group.long c14:(0x0700+0x0)++0x000 line.long 0x00 "DBGWCR0,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x00 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x00 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x01 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x00 1.--2. "PAC,Determines the Exception level or levels at which a watchpoint debug event for watchpoint 0 is generated" "Reserved,System,User,User/System" bitfld.long 0x00 0. "WE,Watchpoint enable" "Disabled,Enabled" endif group.long c14:(0x0600+0x10)++0x000 "Watchpoint 1" line.long 0x00 "DBGWVR1,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" if (((per.l(c14:0x0700+0x10))&0x2000)==0x2000) if (((per.l(c14:0x0700+0x10))&0xC000)==0xC000) group.long c14:(0x0700+0x10)++0x000 line.long 0x00 "DBGWCR1,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x00 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x00 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x01 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x00 1.--2. "PAC,Determines the Exception level or levels at which a watchpoint debug event for watchpoint 1 is generated" "Supervisor,?..." bitfld.long 0x00 0. "WE,Watchpoint enable" "Disabled,Enabled" elif (((per.l(c14:0x0700+0x10))&0x8000)==0x8000) group.long c14:(0x0700+0x10)++0x000 line.long 0x00 "DBGWCR1,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x00 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x00 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x01 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x00 1.--2. "PAC,Determines the Exception level or levels at which a watchpoint debug event for watchpoint 1 is generated" "Reserved,System,Reserved,User/System" bitfld.long 0x00 0. "WE,Watchpoint enable" "Disabled,Enabled" else group.long c14:(0x0700+0x10)++0x000 line.long 0x00 "DBGWCR1,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x00 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x00 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x01 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x00 1.--2. "PAC,Determines the Exception level or levels at which a watchpoint debug event for watchpoint 1 is generated" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" bitfld.long 0x00 0. "WE,Watchpoint enable" "Disabled,Enabled" endif else group.long c14:(0x0700+0x10)++0x000 line.long 0x00 "DBGWCR1,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x00 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x00 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x01 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x00 1.--2. "PAC,Determines the Exception level or levels at which a watchpoint debug event for watchpoint 1 is generated" "Reserved,System,User,User/System" bitfld.long 0x00 0. "WE,Watchpoint enable" "Disabled,Enabled" endif group.long c14:(0x0600+0x20)++0x000 "Watchpoint 2" line.long 0x00 "DBGWVR2,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" if (((per.l(c14:0x0700+0x20))&0x2000)==0x2000) if (((per.l(c14:0x0700+0x20))&0xC000)==0xC000) group.long c14:(0x0700+0x20)++0x000 line.long 0x00 "DBGWCR2,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x00 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x00 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x01 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x00 1.--2. "PAC,Determines the Exception level or levels at which a watchpoint debug event for watchpoint 2 is generated" "Supervisor,?..." bitfld.long 0x00 0. "WE,Watchpoint enable" "Disabled,Enabled" elif (((per.l(c14:0x0700+0x20))&0x8000)==0x8000) group.long c14:(0x0700+0x20)++0x000 line.long 0x00 "DBGWCR2,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x00 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x00 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x01 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x00 1.--2. "PAC,Determines the Exception level or levels at which a watchpoint debug event for watchpoint 2 is generated" "Reserved,System,Reserved,User/System" bitfld.long 0x00 0. "WE,Watchpoint enable" "Disabled,Enabled" else group.long c14:(0x0700+0x20)++0x000 line.long 0x00 "DBGWCR2,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x00 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x00 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x01 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x00 1.--2. "PAC,Determines the Exception level or levels at which a watchpoint debug event for watchpoint 2 is generated" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" bitfld.long 0x00 0. "WE,Watchpoint enable" "Disabled,Enabled" endif else group.long c14:(0x0700+0x20)++0x000 line.long 0x00 "DBGWCR2,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x00 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x00 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x01 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x00 1.--2. "PAC,Determines the Exception level or levels at which a watchpoint debug event for watchpoint 2 is generated" "Reserved,System,User,User/System" bitfld.long 0x00 0. "WE,Watchpoint enable" "Disabled,Enabled" endif group.long c14:(0x0600+0x30)++0x000 "Watchpoint 3" line.long 0x00 "DBGWVR3,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" if (((per.l(c14:0x0700+0x30))&0x2000)==0x2000) if (((per.l(c14:0x0700+0x30))&0xC000)==0xC000) group.long c14:(0x0700+0x30)++0x000 line.long 0x00 "DBGWCR3,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x00 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x00 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x01 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x00 1.--2. "PAC,Determines the Exception level or levels at which a watchpoint debug event for watchpoint 3 is generated" "Supervisor,?..." bitfld.long 0x00 0. "WE,Watchpoint enable" "Disabled,Enabled" elif (((per.l(c14:0x0700+0x30))&0x8000)==0x8000) group.long c14:(0x0700+0x30)++0x000 line.long 0x00 "DBGWCR3,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x00 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x00 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x01 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x00 1.--2. "PAC,Determines the Exception level or levels at which a watchpoint debug event for watchpoint 3 is generated" "Reserved,System,Reserved,User/System" bitfld.long 0x00 0. "WE,Watchpoint enable" "Disabled,Enabled" else group.long c14:(0x0700+0x30)++0x000 line.long 0x00 "DBGWCR3,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x00 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x00 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x01 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x00 1.--2. "PAC,Determines the Exception level or levels at which a watchpoint debug event for watchpoint 3 is generated" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" bitfld.long 0x00 0. "WE,Watchpoint enable" "Disabled,Enabled" endif else group.long c14:(0x0700+0x30)++0x000 line.long 0x00 "DBGWCR3,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x00 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x00 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x01 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x00 1.--2. "PAC,Determines the Exception level or levels at which a watchpoint debug event for watchpoint 3 is generated" "Reserved,System,User,User/System" bitfld.long 0x00 0. "WE,Watchpoint enable" "Disabled,Enabled" endif tree.end tree.end AUTOINDENT.OFF tree.open "Interrupt Controller (GIC-500)" base COMP.BASE("GICD",-1.) width 17. tree "Distributor Interface" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))) group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register (Secure access)" rbitfld.long 0x00 31. " RWP ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending" bitfld.long 0x00 7. " E1NWF ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled" bitfld.long 0x00 6. " DS ,Disable Security" "No,Yes" textline " " bitfld.long 0x00 5. " ARE_NS ,Affinity Routing Enable" "Disabled,Enabled" bitfld.long 0x00 4. " ARE_S ,Affinity Routing Enable" "Disabled,Enabled" bitfld.long 0x00 2. " ENABLEGRP1S ,Enable Secure Group 1 interrupts" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ENABLEGRP1NS ,Enable Secure Group 1 interrupts" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enable Group 0 interrupts" "Disabled,Enabled" elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400) group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register (Non-secure access)" rbitfld.long 0x00 31. " RWP ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending" bitfld.long 0x00 7. " E1NWF ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled" bitfld.long 0x00 4. " ARE_NS ,Affinity Routing Enable" "Reserved,Enabled" textline " " bitfld.long 0x00 1. " ENABLEGRP1A ,Enable Group 1 interrupts" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP1 ,Enable Group 1 interrupts" "Disabled,Enabled" else group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register" rbitfld.long 0x00 31. " RWP ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending" bitfld.long 0x00 7. " E1NWF ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled" rbitfld.long 0x00 6. " DS ,Disable Security" "Reserved,Yes" textline " " bitfld.long 0x00 4. " ARE ,Affinity Routing Enable" "Reserved,Enabled" bitfld.long 0x00 1. " ENABLEGRP1 ,Enable Group 1 interrupts" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enable Group 0 interrupts" "Disabled,Enabled" endif rgroup.long 0x0004++0x03 line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register" bitfld.long 0x00 25. " NO1N ,Indicates whether 1 of N SPI interrupts are supported" "Supported,Not supported" bitfld.long 0x00 24. " A3V ,Indicates whether the Distributor supports nonzero values of Affinity level 3" "Not supported,Supported" bitfld.long 0x00 19.--23. " IDBITS ,The number of interrupt identifier bits supported" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..." textline " " bitfld.long 0x00 17. " LPIS ,Indicates whether the implementation supports LPIs" "Not supported,Supported" bitfld.long 0x00 16. " MBIS ,Indicates whether the implementation supports message-based interrupts by writing to Distributor registers" "Not supported,Supported" bitfld.long 0x00 10. " SECURITYEXTN ,Indicates whether interrupt controller implements the security extensions" "Not implemented,Implemented" textline " " bitfld.long 0x00 5.--7. " CPUNUMBER ,Reports the number of PEs that can be used when affinity routing is not enabled" "1,2,3,4,5,6,7,8" bitfld.long 0x00 0.--4. " ITLN ,Indicates the maximum SPI INTID that the GIC implementation supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Reserved" rgroup.long 0x0008++0x03 line.long 0x00 "GICD_IIDR,Distributor Implementer Identification Register" bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "GIC-500,?..." bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x10000)==0x10000) wgroup.long 0x40++0x03 line.long 0x00 "GICD_SETSPI_NSR,Non-secure SPI Set Register" hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI" wgroup.long 0x48++0x03 line.long 0x00 "GICD_CLRSPI_NSR,Non-secure SPI Clear Register" hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x50)) wgroup.long 0x50++0x03 line.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register (Secure access)" hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI" else hgroup.long 0x50++0x03 hide.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register (Non-secure access)" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x58)) wgroup.long 0x58++0x03 line.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register (Secure access)" hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI" else hgroup.long 0x58++0x03 hide.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register (Non-secure access)" endif else hgroup.long 0x40++0x03 hide.long 0x00 "GICD_SETSPI_NSR,Non-secure SPI Set Register" hgroup.long 0x48++0x03 hide.long 0x00 "GICD_CLRSPI_NSR,Non-secure SPI Clear Register" hgroup.long 0x50++0x03 hide.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register" hgroup.long 0x58++0x03 hide.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register" endif width 17. tree "Group Registers" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0080)) group.long 0x0080++0x03 line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Secure Access)" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Secure,Non-secure Group 1" elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00) group.long 0x0080++0x03 line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0,Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0,Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0,Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0,Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0,Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0,Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0,Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0,Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0,Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0,Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0,Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0,Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0,Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0,Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0,Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0,Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0,Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0,Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0,Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0,Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0,Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0,Group 1" else hgroup.long 0x0080++0x03 hide.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Non-secure access)" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x84))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1)) group.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 (Secure Access)" bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1)) group.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 " bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Group 0,Group 1" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Group 0,Group 1" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Group 0,Group 1" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Group 0,Group 1" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Group 0,Group 1" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Group 0,Group 1" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Group 0,Group 1" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Group 0,Group 1" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Group 0,Group 1" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Group 0,Group 1" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Group 0,Group 1" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Group 0,Group 1" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Group 0,Group 1" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Group 0,Group 1" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Group 0,Group 1" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Group 0,Group 1" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Group 0,Group 1" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Group 0,Group 1" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Group 0,Group 1" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Group 0,Group 1" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Group 0,Group 1" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Group 0,Group 1" else hgroup.long 0x0084++0x03 hide.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x88))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2)) group.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 (Secure Access)" bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2)) group.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 " bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Group 0,Group 1" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Group 0,Group 1" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Group 0,Group 1" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Group 0,Group 1" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Group 0,Group 1" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Group 0,Group 1" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Group 0,Group 1" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Group 0,Group 1" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Group 0,Group 1" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Group 0,Group 1" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Group 0,Group 1" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Group 0,Group 1" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Group 0,Group 1" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Group 0,Group 1" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Group 0,Group 1" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Group 0,Group 1" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Group 0,Group 1" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Group 0,Group 1" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Group 0,Group 1" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Group 0,Group 1" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Group 0,Group 1" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Group 0,Group 1" else hgroup.long 0x0088++0x03 hide.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x8C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3)) group.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 (Secure Access)" bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3)) group.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 " bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0,Group 1" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Group 0,Group 1" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0,Group 1" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Group 0,Group 1" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0,Group 1" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Group 0,Group 1" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0,Group 1" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Group 0,Group 1" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0,Group 1" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Group 0,Group 1" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0,Group 1" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Group 0,Group 1" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0,Group 1" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Group 0,Group 1" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0,Group 1" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Group 0,Group 1" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0,Group 1" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Group 0,Group 1" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0,Group 1" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Group 0,Group 1" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Group 0,Group 1" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Group 0,Group 1" else hgroup.long 0x008C++0x03 hide.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x90))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4)) group.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 (Secure Access)" bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4)) group.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 " bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0,Group 1" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Group 0,Group 1" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0,Group 1" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Group 0,Group 1" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0,Group 1" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Group 0,Group 1" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0,Group 1" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Group 0,Group 1" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0,Group 1" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Group 0,Group 1" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0,Group 1" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Group 0,Group 1" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0,Group 1" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Group 0,Group 1" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0,Group 1" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Group 0,Group 1" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0,Group 1" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Group 0,Group 1" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0,Group 1" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Group 0,Group 1" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0,Group 1" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Group 0,Group 1" else hgroup.long 0x0090++0x03 hide.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x94))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5)) group.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 (Secure Access)" bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5)) group.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 " bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0,Group 1" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Group 0,Group 1" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0,Group 1" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Group 0,Group 1" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0,Group 1" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Group 0,Group 1" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0,Group 1" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Group 0,Group 1" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0,Group 1" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Group 0,Group 1" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0,Group 1" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Group 0,Group 1" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0,Group 1" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Group 0,Group 1" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0,Group 1" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Group 0,Group 1" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0,Group 1" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Group 0,Group 1" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0,Group 1" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Group 0,Group 1" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0,Group 1" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Group 0,Group 1" else hgroup.long 0x0094++0x03 hide.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x98))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6)) group.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 (Secure Access)" bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6)) group.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 " bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0,Group 1" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Group 0,Group 1" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0,Group 1" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Group 0,Group 1" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0,Group 1" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Group 0,Group 1" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0,Group 1" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Group 0,Group 1" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0,Group 1" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Group 0,Group 1" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0,Group 1" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Group 0,Group 1" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0,Group 1" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Group 0,Group 1" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0,Group 1" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Group 0,Group 1" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0,Group 1" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Group 0,Group 1" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0,Group 1" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Group 0,Group 1" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0,Group 1" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Group 0,Group 1" else hgroup.long 0x0098++0x03 hide.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x9C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7)) group.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 (Secure Access)" bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7)) group.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 " bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0,Group 1" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Group 0,Group 1" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0,Group 1" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Group 0,Group 1" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0,Group 1" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Group 0,Group 1" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0,Group 1" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Group 0,Group 1" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0,Group 1" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Group 0,Group 1" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0,Group 1" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Group 0,Group 1" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0,Group 1" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Group 0,Group 1" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0,Group 1" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Group 0,Group 1" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0,Group 1" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Group 0,Group 1" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0,Group 1" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Group 0,Group 1" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0,Group 1" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Group 0,Group 1" else hgroup.long 0x009C++0x03 hide.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8)) group.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 (Secure Access)" bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8)) group.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 " bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Group 0,Group 1" bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Group 0,Group 1" bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Group 0,Group 1" bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Group 0,Group 1" bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Group 0,Group 1" bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Group 0,Group 1" bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Group 0,Group 1" bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Group 0,Group 1" bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Group 0,Group 1" bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Group 0,Group 1" bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Group 0,Group 1" bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Group 0,Group 1" bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Group 0,Group 1" bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Group 0,Group 1" bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Group 0,Group 1" bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Group 0,Group 1" bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Group 0,Group 1" bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Group 0,Group 1" bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Group 0,Group 1" bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Group 0,Group 1" bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Group 0,Group 1" bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Group 0,Group 1" else hgroup.long 0x00A0++0x03 hide.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9)) group.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 (Secure Access)" bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9)) group.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 " bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Group 0,Group 1" bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Group 0,Group 1" bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Group 0,Group 1" bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Group 0,Group 1" bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Group 0,Group 1" bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Group 0,Group 1" bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Group 0,Group 1" bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Group 0,Group 1" bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Group 0,Group 1" bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Group 0,Group 1" bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Group 0,Group 1" bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Group 0,Group 1" bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Group 0,Group 1" bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Group 0,Group 1" bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Group 0,Group 1" bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Group 0,Group 1" bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Group 0,Group 1" bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Group 0,Group 1" bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Group 0,Group 1" bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Group 0,Group 1" bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Group 0,Group 1" bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Group 0,Group 1" else hgroup.long 0x00A4++0x03 hide.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA)) group.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Secure Access)" bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA)) group.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10" bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Group 0,Group 1" bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Group 0,Group 1" bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Group 0,Group 1" bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Group 0,Group 1" bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Group 0,Group 1" bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Group 0,Group 1" bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Group 0,Group 1" bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Group 0,Group 1" bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Group 0,Group 1" bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Group 0,Group 1" bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Group 0,Group 1" bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Group 0,Group 1" bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Group 0,Group 1" bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Group 0,Group 1" bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Group 0,Group 1" bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Group 0,Group 1" bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Group 0,Group 1" bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Group 0,Group 1" bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Group 0,Group 1" bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Group 0,Group 1" bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Group 0,Group 1" bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Group 0,Group 1" else hgroup.long 0x00A8++0x03 hide.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xAC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB)) group.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Secure Access)" bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB)) group.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11" bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Group 0,Group 1" bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Group 0,Group 1" bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Group 0,Group 1" bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Group 0,Group 1" bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Group 0,Group 1" bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Group 0,Group 1" bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Group 0,Group 1" bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Group 0,Group 1" bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Group 0,Group 1" bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Group 0,Group 1" bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Group 0,Group 1" bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Group 0,Group 1" bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Group 0,Group 1" bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Group 0,Group 1" bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Group 0,Group 1" bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Group 0,Group 1" bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Group 0,Group 1" bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Group 0,Group 1" bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Group 0,Group 1" bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Group 0,Group 1" bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Group 0,Group 1" bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Group 0,Group 1" else hgroup.long 0x00AC++0x03 hide.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC)) group.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Secure Access)" bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC)) group.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12" bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Group 0,Group 1" bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Group 0,Group 1" bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Group 0,Group 1" bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Group 0,Group 1" bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Group 0,Group 1" bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Group 0,Group 1" bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Group 0,Group 1" bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Group 0,Group 1" bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Group 0,Group 1" bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Group 0,Group 1" bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Group 0,Group 1" bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Group 0,Group 1" bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Group 0,Group 1" bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Group 0,Group 1" bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Group 0,Group 1" bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Group 0,Group 1" bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Group 0,Group 1" bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Group 0,Group 1" bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Group 0,Group 1" bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Group 0,Group 1" bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Group 0,Group 1" bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Group 0,Group 1" else hgroup.long 0x00B0++0x03 hide.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD)) group.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Secure Access)" bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD)) group.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13" bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Group 0,Group 1" bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Group 0,Group 1" bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Group 0,Group 1" bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Group 0,Group 1" bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Group 0,Group 1" bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Group 0,Group 1" bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Group 0,Group 1" bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Group 0,Group 1" bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Group 0,Group 1" bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Group 0,Group 1" bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Group 0,Group 1" bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Group 0,Group 1" bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Group 0,Group 1" bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Group 0,Group 1" bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Group 0,Group 1" bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Group 0,Group 1" bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Group 0,Group 1" bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Group 0,Group 1" bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Group 0,Group 1" bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Group 0,Group 1" bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Group 0,Group 1" bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Group 0,Group 1" else hgroup.long 0x00B4++0x03 hide.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE)) group.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Secure Access)" bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE)) group.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14" bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Group 0,Group 1" bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Group 0,Group 1" bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Group 0,Group 1" bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Group 0,Group 1" bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Group 0,Group 1" bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Group 0,Group 1" bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Group 0,Group 1" bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Group 0,Group 1" bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Group 0,Group 1" bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Group 0,Group 1" bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Group 0,Group 1" bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Group 0,Group 1" bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Group 0,Group 1" bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Group 0,Group 1" bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Group 0,Group 1" bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Group 0,Group 1" bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Group 0,Group 1" bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Group 0,Group 1" bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Group 0,Group 1" bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Group 0,Group 1" bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Group 0,Group 1" bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Group 0,Group 1" else hgroup.long 0x00B8++0x03 hide.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xBC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF)) group.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Secure Access)" bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF)) group.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15" bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Group 0,Group 1" bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Group 0,Group 1" bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Group 0,Group 1" bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Group 0,Group 1" bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Group 0,Group 1" bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Group 0,Group 1" bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Group 0,Group 1" bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Group 0,Group 1" bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Group 0,Group 1" bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Group 0,Group 1" bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Group 0,Group 1" bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Group 0,Group 1" bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Group 0,Group 1" bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Group 0,Group 1" bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Group 0,Group 1" bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Group 0,Group 1" bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Group 0,Group 1" bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Group 0,Group 1" bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Group 0,Group 1" bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Group 0,Group 1" bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Group 0,Group 1" bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Group 0,Group 1" else hgroup.long 0x00BC++0x03 hide.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)) group.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Secure Access)" bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)) group.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16" bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Group 0,Group 1" bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Group 0,Group 1" bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Group 0,Group 1" bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Group 0,Group 1" bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Group 0,Group 1" bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Group 0,Group 1" bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Group 0,Group 1" bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Group 0,Group 1" bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Group 0,Group 1" bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Group 0,Group 1" bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Group 0,Group 1" bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Group 0,Group 1" bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Group 0,Group 1" bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Group 0,Group 1" bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Group 0,Group 1" bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Group 0,Group 1" bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Group 0,Group 1" bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Group 0,Group 1" bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Group 0,Group 1" bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Group 0,Group 1" bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Group 0,Group 1" bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Group 0,Group 1" else hgroup.long 0x00C0++0x03 hide.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)) group.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Secure Access)" bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)) group.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17" bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Group 0,Group 1" bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Group 0,Group 1" bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Group 0,Group 1" bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Group 0,Group 1" bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Group 0,Group 1" bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Group 0,Group 1" bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Group 0,Group 1" bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Group 0,Group 1" bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Group 0,Group 1" bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Group 0,Group 1" bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Group 0,Group 1" bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Group 0,Group 1" bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Group 0,Group 1" bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Group 0,Group 1" bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Group 0,Group 1" bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Group 0,Group 1" bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Group 0,Group 1" bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Group 0,Group 1" bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Group 0,Group 1" bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Group 0,Group 1" bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Group 0,Group 1" bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Group 0,Group 1" else hgroup.long 0x00C4++0x03 hide.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)) group.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Secure Access)" bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)) group.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18" bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Group 0,Group 1" bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Group 0,Group 1" bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Group 0,Group 1" bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Group 0,Group 1" bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Group 0,Group 1" bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Group 0,Group 1" bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Group 0,Group 1" bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Group 0,Group 1" bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Group 0,Group 1" bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Group 0,Group 1" bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Group 0,Group 1" bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Group 0,Group 1" bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Group 0,Group 1" bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Group 0,Group 1" bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Group 0,Group 1" bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Group 0,Group 1" bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Group 0,Group 1" bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Group 0,Group 1" bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Group 0,Group 1" bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Group 0,Group 1" bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Group 0,Group 1" bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Group 0,Group 1" else hgroup.long 0x00C8++0x03 hide.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xCC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)) group.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Secure Access)" bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)) group.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19" bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Group 0,Group 1" bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Group 0,Group 1" bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Group 0,Group 1" bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Group 0,Group 1" bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Group 0,Group 1" bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Group 0,Group 1" bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Group 0,Group 1" bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Group 0,Group 1" bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Group 0,Group 1" bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Group 0,Group 1" bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Group 0,Group 1" bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Group 0,Group 1" bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Group 0,Group 1" bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Group 0,Group 1" bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Group 0,Group 1" bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Group 0,Group 1" bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Group 0,Group 1" bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Group 0,Group 1" bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Group 0,Group 1" bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Group 0,Group 1" bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Group 0,Group 1" bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Group 0,Group 1" else hgroup.long 0x00CC++0x03 hide.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)) group.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Secure Access)" bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)) group.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20" bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Group 0,Group 1" bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Group 0,Group 1" bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Group 0,Group 1" bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Group 0,Group 1" bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Group 0,Group 1" bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Group 0,Group 1" bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Group 0,Group 1" bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Group 0,Group 1" bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Group 0,Group 1" bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Group 0,Group 1" bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Group 0,Group 1" bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Group 0,Group 1" bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Group 0,Group 1" bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Group 0,Group 1" bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Group 0,Group 1" bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Group 0,Group 1" bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Group 0,Group 1" bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Group 0,Group 1" bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Group 0,Group 1" bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Group 0,Group 1" bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Group 0,Group 1" bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Group 0,Group 1" else hgroup.long 0x00D0++0x03 hide.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)) group.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Secure Access)" bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)) group.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21" bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Group 0,Group 1" bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Group 0,Group 1" bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Group 0,Group 1" bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Group 0,Group 1" bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Group 0,Group 1" bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Group 0,Group 1" bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Group 0,Group 1" bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Group 0,Group 1" bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Group 0,Group 1" bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Group 0,Group 1" bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Group 0,Group 1" bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Group 0,Group 1" bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Group 0,Group 1" bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Group 0,Group 1" bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Group 0,Group 1" bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Group 0,Group 1" bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Group 0,Group 1" bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Group 0,Group 1" bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Group 0,Group 1" bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Group 0,Group 1" bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Group 0,Group 1" bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Group 0,Group 1" else hgroup.long 0x00D4++0x03 hide.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)) group.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Secure Access)" bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)) group.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22" bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Group 0,Group 1" bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Group 0,Group 1" bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Group 0,Group 1" bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Group 0,Group 1" bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Group 0,Group 1" bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Group 0,Group 1" bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Group 0,Group 1" bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Group 0,Group 1" bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Group 0,Group 1" bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Group 0,Group 1" bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Group 0,Group 1" bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Group 0,Group 1" bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Group 0,Group 1" bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Group 0,Group 1" bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Group 0,Group 1" bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Group 0,Group 1" bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Group 0,Group 1" bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Group 0,Group 1" bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Group 0,Group 1" bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Group 0,Group 1" bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Group 0,Group 1" bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Group 0,Group 1" else hgroup.long 0x00D8++0x03 hide.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xDC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)) group.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Secure Access)" bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)) group.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23" bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Group 0,Group 1" bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Group 0,Group 1" bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Group 0,Group 1" bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Group 0,Group 1" bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Group 0,Group 1" bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Group 0,Group 1" bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Group 0,Group 1" bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Group 0,Group 1" bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Group 0,Group 1" bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Group 0,Group 1" bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Group 0,Group 1" bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Group 0,Group 1" bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Group 0,Group 1" bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Group 0,Group 1" bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Group 0,Group 1" bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Group 0,Group 1" bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Group 0,Group 1" bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Group 0,Group 1" bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Group 0,Group 1" bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Group 0,Group 1" bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Group 0,Group 1" bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Group 0,Group 1" else hgroup.long 0x00DC++0x03 hide.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)) group.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Secure Access)" bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)) group.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24" bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Group 0,Group 1" bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Group 0,Group 1" bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Group 0,Group 1" bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Group 0,Group 1" bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Group 0,Group 1" bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Group 0,Group 1" bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Group 0,Group 1" bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Group 0,Group 1" bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Group 0,Group 1" bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Group 0,Group 1" bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Group 0,Group 1" bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Group 0,Group 1" bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Group 0,Group 1" bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Group 0,Group 1" bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Group 0,Group 1" bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Group 0,Group 1" bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Group 0,Group 1" bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Group 0,Group 1" bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Group 0,Group 1" bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Group 0,Group 1" bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Group 0,Group 1" bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Group 0,Group 1" else hgroup.long 0x00E0++0x03 hide.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)) group.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Secure Access)" bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)) group.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25" bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Group 0,Group 1" bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Group 0,Group 1" bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Group 0,Group 1" bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Group 0,Group 1" bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Group 0,Group 1" bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Group 0,Group 1" bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Group 0,Group 1" bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Group 0,Group 1" bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Group 0,Group 1" bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Group 0,Group 1" bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Group 0,Group 1" bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Group 0,Group 1" bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Group 0,Group 1" bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Group 0,Group 1" bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Group 0,Group 1" bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Group 0,Group 1" bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Group 0,Group 1" bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Group 0,Group 1" bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Group 0,Group 1" bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Group 0,Group 1" bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Group 0,Group 1" bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Group 0,Group 1" else hgroup.long 0x00E4++0x03 hide.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)) group.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Secure Access)" bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)) group.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26" bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Group 0,Group 1" bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Group 0,Group 1" bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Group 0,Group 1" bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Group 0,Group 1" bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Group 0,Group 1" bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Group 0,Group 1" bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Group 0,Group 1" bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Group 0,Group 1" bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Group 0,Group 1" bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Group 0,Group 1" bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Group 0,Group 1" bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Group 0,Group 1" bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Group 0,Group 1" bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Group 0,Group 1" bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Group 0,Group 1" bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Group 0,Group 1" bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Group 0,Group 1" bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Group 0,Group 1" bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Group 0,Group 1" bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Group 0,Group 1" bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Group 0,Group 1" bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Group 0,Group 1" else hgroup.long 0x00E8++0x03 hide.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)) group.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Secure Access)" bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)) group.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27" bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Group 0,Group 1" bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Group 0,Group 1" bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Group 0,Group 1" bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Group 0,Group 1" bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Group 0,Group 1" bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Group 0,Group 1" bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Group 0,Group 1" bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Group 0,Group 1" bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Group 0,Group 1" bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Group 0,Group 1" bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Group 0,Group 1" bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Group 0,Group 1" bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Group 0,Group 1" bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Group 0,Group 1" bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Group 0,Group 1" bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Group 0,Group 1" bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Group 0,Group 1" bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Group 0,Group 1" bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Group 0,Group 1" bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Group 0,Group 1" bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Group 0,Group 1" bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Group 0,Group 1" else hgroup.long 0x00EC++0x03 hide.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)) group.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Secure Access)" bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)) group.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28" bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Group 0,Group 1" bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Group 0,Group 1" bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Group 0,Group 1" bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Group 0,Group 1" bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Group 0,Group 1" bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Group 0,Group 1" bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Group 0,Group 1" bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Group 0,Group 1" bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Group 0,Group 1" bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Group 0,Group 1" bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Group 0,Group 1" bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Group 0,Group 1" bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Group 0,Group 1" bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Group 0,Group 1" bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Group 0,Group 1" bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Group 0,Group 1" bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Group 0,Group 1" bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Group 0,Group 1" bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Group 0,Group 1" bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Group 0,Group 1" bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Group 0,Group 1" bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Group 0,Group 1" else hgroup.long 0x00F0++0x03 hide.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)) group.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Secure Access)" bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)) group.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29" bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Group 0,Group 1" bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Group 0,Group 1" bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Group 0,Group 1" bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Group 0,Group 1" bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Group 0,Group 1" bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Group 0,Group 1" bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Group 0,Group 1" bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Group 0,Group 1" bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Group 0,Group 1" bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Group 0,Group 1" bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Group 0,Group 1" bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Group 0,Group 1" bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Group 0,Group 1" bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Group 0,Group 1" bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Group 0,Group 1" bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Group 0,Group 1" bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Group 0,Group 1" bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Group 0,Group 1" bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Group 0,Group 1" bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Group 0,Group 1" bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Group 0,Group 1" bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Group 0,Group 1" else hgroup.long 0x00F4++0x03 hide.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)) group.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Secure Access)" bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)) group.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30" bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Group 0,Group 1" bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Group 0,Group 1" bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Group 0,Group 1" bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Group 0,Group 1" bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Group 0,Group 1" bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Group 0,Group 1" bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Group 0,Group 1" bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Group 0,Group 1" bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Group 0,Group 1" bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Group 0,Group 1" bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Group 0,Group 1" bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Group 0,Group 1" bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Group 0,Group 1" bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Group 0,Group 1" bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Group 0,Group 1" bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Group 0,Group 1" bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Group 0,Group 1" bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Group 0,Group 1" bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Group 0,Group 1" bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Group 0,Group 1" bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Group 0,Group 1" bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Group 0,Group 1" else hgroup.long 0x00F8++0x03 hide.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30" endif tree.end width 24. tree "Set/Clear Enable Registers" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x0100++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0" newline newline newline newline newline newline newline newline newline newline else group.long 0x0100++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31 ,Set/Clear Enable Bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB30 ,Set/Clear Enable Bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB29 ,Set/Clear Enable Bit 29" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28 ,Set/Clear Enable Bit 28" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB27 ,Set/Clear Enable Bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB26 ,Set/Clear Enable Bit 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25 ,Set/Clear Enable Bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB24 ,Set/Clear Enable Bit 24" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB23 ,Set/Clear Enable Bit 23" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22 ,Set/Clear Enable Bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB21 ,Set/Clear Enable Bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB20 ,Set/Clear Enable Bit 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19 ,Set/Clear Enable Bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB18 ,Set/Clear Enable Bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB17 ,Set/Clear Enable Bit 17" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16 ,Set/Clear Enable Bit 16" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB15 ,Set/Clear Enable Bit 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB14 ,Set/Clear Enable Bit 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB13 ,Set/Clear Enable Bit 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB12 ,Set/Clear Enable Bit 12" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB11 ,Set/Clear Enable Bit 11" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB10 ,Set/Clear Enable Bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB9 ,Set/Clear Enable Bit 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB8 ,Set/Clear Enable Bit 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB7 ,Set/Clear Enable Bit 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB6 ,Set/Clear Enable Bit 6" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB5 ,Set/Clear Enable Bit 5" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB4 ,Set/Clear Enable Bit 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB3 ,Set/Clear Enable Bit 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB2 ,Set/Clear Enable Bit 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB1 ,Set/Clear Enable Bit 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB0 ,Set/Clear Enable Bit 0" "Disabled,Enabled" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x0104++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB63 ,Set/Clear Enable Bit 63" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB62 ,Set/Clear Enable Bit 62" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB61 ,Set/Clear Enable Bit 61" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB60 ,Set/Clear Enable Bit 60" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB59 ,Set/Clear Enable Bit 59" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB58 ,Set/Clear Enable Bit 58" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB57 ,Set/Clear Enable Bit 57" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB56 ,Set/Clear Enable Bit 56" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB55 ,Set/Clear Enable Bit 55" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB54 ,Set/Clear Enable Bit 54" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB53 ,Set/Clear Enable Bit 53" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB52 ,Set/Clear Enable Bit 52" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB51 ,Set/Clear Enable Bit 51" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB50 ,Set/Clear Enable Bit 50" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB49 ,Set/Clear Enable Bit 49" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB48 ,Set/Clear Enable Bit 48" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB47 ,Set/Clear Enable Bit 47" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB46 ,Set/Clear Enable Bit 46" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB45 ,Set/Clear Enable Bit 45" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB44 ,Set/Clear Enable Bit 44" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB43 ,Set/Clear Enable Bit 43" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB42 ,Set/Clear Enable Bit 42" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB41 ,Set/Clear Enable Bit 41" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB40 ,Set/Clear Enable Bit 40" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB39 ,Set/Clear Enable Bit 39" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB38 ,Set/Clear Enable Bit 38" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB37 ,Set/Clear Enable Bit 37" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB36 ,Set/Clear Enable Bit 36" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB35 ,Set/Clear Enable Bit 35" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB34 ,Set/Clear Enable Bit 34" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB33 ,Set/Clear Enable Bit 33" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB32 ,Set/Clear Enable Bit 32" "Disabled,Enabled" else hgroup.long 0x0104++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x0108++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB95 ,Set/Clear Enable Bit 95" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB94 ,Set/Clear Enable Bit 94" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB93 ,Set/Clear Enable Bit 93" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB92 ,Set/Clear Enable Bit 92" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB91 ,Set/Clear Enable Bit 91" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB90 ,Set/Clear Enable Bit 90" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB89 ,Set/Clear Enable Bit 89" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB88 ,Set/Clear Enable Bit 88" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB87 ,Set/Clear Enable Bit 87" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB86 ,Set/Clear Enable Bit 86" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB85 ,Set/Clear Enable Bit 85" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB84 ,Set/Clear Enable Bit 84" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB83 ,Set/Clear Enable Bit 83" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB82 ,Set/Clear Enable Bit 82" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB81 ,Set/Clear Enable Bit 81" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB80 ,Set/Clear Enable Bit 80" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB79 ,Set/Clear Enable Bit 79" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB78 ,Set/Clear Enable Bit 78" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB77 ,Set/Clear Enable Bit 77" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB76 ,Set/Clear Enable Bit 76" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB75 ,Set/Clear Enable Bit 75" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB74 ,Set/Clear Enable Bit 74" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB73 ,Set/Clear Enable Bit 73" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB72 ,Set/Clear Enable Bit 72" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB71 ,Set/Clear Enable Bit 71" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB70 ,Set/Clear Enable Bit 70" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB69 ,Set/Clear Enable Bit 69" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB68 ,Set/Clear Enable Bit 68" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB67 ,Set/Clear Enable Bit 67" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB66 ,Set/Clear Enable Bit 66" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB65 ,Set/Clear Enable Bit 65" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB64 ,Set/Clear Enable Bit 64" "Disabled,Enabled" else hgroup.long 0x0108++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x010C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB127 ,Set/Clear Enable Bit 127" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB126 ,Set/Clear Enable Bit 126" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB125 ,Set/Clear Enable Bit 125" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB124 ,Set/Clear Enable Bit 124" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB123 ,Set/Clear Enable Bit 123" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB122 ,Set/Clear Enable Bit 122" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB121 ,Set/Clear Enable Bit 121" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB120 ,Set/Clear Enable Bit 120" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB119 ,Set/Clear Enable Bit 119" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB118 ,Set/Clear Enable Bit 118" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB117 ,Set/Clear Enable Bit 117" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB116 ,Set/Clear Enable Bit 116" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB115 ,Set/Clear Enable Bit 115" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB114 ,Set/Clear Enable Bit 114" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB113 ,Set/Clear Enable Bit 113" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB112 ,Set/Clear Enable Bit 112" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB111 ,Set/Clear Enable Bit 111" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB110 ,Set/Clear Enable Bit 110" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB109 ,Set/Clear Enable Bit 109" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB108 ,Set/Clear Enable Bit 108" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB107 ,Set/Clear Enable Bit 107" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB106 ,Set/Clear Enable Bit 106" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB105 ,Set/Clear Enable Bit 105" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB104 ,Set/Clear Enable Bit 104" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB103 ,Set/Clear Enable Bit 103" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB102 ,Set/Clear Enable Bit 102" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB101 ,Set/Clear Enable Bit 101" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB100 ,Set/Clear Enable Bit 100" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB99 ,Set/Clear Enable Bit 99" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB98 ,Set/Clear Enable Bit 98" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB97 ,Set/Clear Enable Bit 97" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB96 ,Set/Clear Enable Bit 96" "Disabled,Enabled" else hgroup.long 0x010C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x0110++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB159 ,Set/Clear Enable Bit 159" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB158 ,Set/Clear Enable Bit 158" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB157 ,Set/Clear Enable Bit 157" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB156 ,Set/Clear Enable Bit 156" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB155 ,Set/Clear Enable Bit 155" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB154 ,Set/Clear Enable Bit 154" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB153 ,Set/Clear Enable Bit 153" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB152 ,Set/Clear Enable Bit 152" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB151 ,Set/Clear Enable Bit 151" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB150 ,Set/Clear Enable Bit 150" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB149 ,Set/Clear Enable Bit 149" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB148 ,Set/Clear Enable Bit 148" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB147 ,Set/Clear Enable Bit 147" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB146 ,Set/Clear Enable Bit 146" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB145 ,Set/Clear Enable Bit 145" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB144 ,Set/Clear Enable Bit 144" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB143 ,Set/Clear Enable Bit 143" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB142 ,Set/Clear Enable Bit 142" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB141 ,Set/Clear Enable Bit 141" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB140 ,Set/Clear Enable Bit 140" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB139 ,Set/Clear Enable Bit 139" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB138 ,Set/Clear Enable Bit 138" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB137 ,Set/Clear Enable Bit 137" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB136 ,Set/Clear Enable Bit 136" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB135 ,Set/Clear Enable Bit 135" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB134 ,Set/Clear Enable Bit 134" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB133 ,Set/Clear Enable Bit 133" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB132 ,Set/Clear Enable Bit 132" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB131 ,Set/Clear Enable Bit 131" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB130 ,Set/Clear Enable Bit 130" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB129 ,Set/Clear Enable Bit 129" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB128 ,Set/Clear Enable Bit 128" "Disabled,Enabled" else hgroup.long 0x0110++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x0114++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB191 ,Set/Clear Enable Bit 191" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB190 ,Set/Clear Enable Bit 190" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB189 ,Set/Clear Enable Bit 189" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB188 ,Set/Clear Enable Bit 188" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB187 ,Set/Clear Enable Bit 187" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB186 ,Set/Clear Enable Bit 186" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB185 ,Set/Clear Enable Bit 185" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB184 ,Set/Clear Enable Bit 184" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB183 ,Set/Clear Enable Bit 183" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB182 ,Set/Clear Enable Bit 182" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB181 ,Set/Clear Enable Bit 181" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB180 ,Set/Clear Enable Bit 180" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB179 ,Set/Clear Enable Bit 179" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB178 ,Set/Clear Enable Bit 178" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB177 ,Set/Clear Enable Bit 177" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB176 ,Set/Clear Enable Bit 176" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB175 ,Set/Clear Enable Bit 175" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB174 ,Set/Clear Enable Bit 174" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB173 ,Set/Clear Enable Bit 173" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB172 ,Set/Clear Enable Bit 172" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB171 ,Set/Clear Enable Bit 171" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB170 ,Set/Clear Enable Bit 170" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB169 ,Set/Clear Enable Bit 169" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB168 ,Set/Clear Enable Bit 168" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB167 ,Set/Clear Enable Bit 167" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB166 ,Set/Clear Enable Bit 166" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB165 ,Set/Clear Enable Bit 165" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB164 ,Set/Clear Enable Bit 164" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB163 ,Set/Clear Enable Bit 163" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB162 ,Set/Clear Enable Bit 162" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB161 ,Set/Clear Enable Bit 161" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB160 ,Set/Clear Enable Bit 160" "Disabled,Enabled" else hgroup.long 0x0114++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x0118++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB223 ,Set/Clear Enable Bit 223" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB222 ,Set/Clear Enable Bit 222" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB221 ,Set/Clear Enable Bit 221" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB220 ,Set/Clear Enable Bit 220" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB219 ,Set/Clear Enable Bit 219" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB218 ,Set/Clear Enable Bit 218" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB217 ,Set/Clear Enable Bit 217" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB216 ,Set/Clear Enable Bit 216" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB215 ,Set/Clear Enable Bit 215" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB214 ,Set/Clear Enable Bit 214" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB213 ,Set/Clear Enable Bit 213" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB212 ,Set/Clear Enable Bit 212" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB211 ,Set/Clear Enable Bit 211" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB210 ,Set/Clear Enable Bit 210" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB209 ,Set/Clear Enable Bit 209" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB208 ,Set/Clear Enable Bit 208" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB207 ,Set/Clear Enable Bit 207" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB206 ,Set/Clear Enable Bit 206" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB205 ,Set/Clear Enable Bit 205" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB204 ,Set/Clear Enable Bit 204" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB203 ,Set/Clear Enable Bit 203" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB202 ,Set/Clear Enable Bit 202" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB201 ,Set/Clear Enable Bit 201" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB200 ,Set/Clear Enable Bit 200" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB199 ,Set/Clear Enable Bit 199" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB198 ,Set/Clear Enable Bit 198" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB197 ,Set/Clear Enable Bit 197" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB196 ,Set/Clear Enable Bit 196" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB195 ,Set/Clear Enable Bit 195" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB194 ,Set/Clear Enable Bit 194" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB193 ,Set/Clear Enable Bit 193" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB192 ,Set/Clear Enable Bit 192" "Disabled,Enabled" else hgroup.long 0x0118++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x011C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB255 ,Set/Clear Enable Bit 255" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB254 ,Set/Clear Enable Bit 254" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB253 ,Set/Clear Enable Bit 253" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB252 ,Set/Clear Enable Bit 252" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB251 ,Set/Clear Enable Bit 251" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB250 ,Set/Clear Enable Bit 250" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB249 ,Set/Clear Enable Bit 249" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB248 ,Set/Clear Enable Bit 248" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB247 ,Set/Clear Enable Bit 247" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB246 ,Set/Clear Enable Bit 246" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB245 ,Set/Clear Enable Bit 245" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB244 ,Set/Clear Enable Bit 244" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB243 ,Set/Clear Enable Bit 243" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB242 ,Set/Clear Enable Bit 242" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB241 ,Set/Clear Enable Bit 241" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB240 ,Set/Clear Enable Bit 240" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB239 ,Set/Clear Enable Bit 239" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB238 ,Set/Clear Enable Bit 238" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB237 ,Set/Clear Enable Bit 237" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB236 ,Set/Clear Enable Bit 236" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB235 ,Set/Clear Enable Bit 235" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB234 ,Set/Clear Enable Bit 234" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB233 ,Set/Clear Enable Bit 233" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB232 ,Set/Clear Enable Bit 232" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB231 ,Set/Clear Enable Bit 231" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB230 ,Set/Clear Enable Bit 230" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB229 ,Set/Clear Enable Bit 229" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB228 ,Set/Clear Enable Bit 228" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB227 ,Set/Clear Enable Bit 227" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB226 ,Set/Clear Enable Bit 226" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB225 ,Set/Clear Enable Bit 225" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB224 ,Set/Clear Enable Bit 224" "Disabled,Enabled" else hgroup.long 0x011C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x0120++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB287 ,Set/Clear Enable Bit 287" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB286 ,Set/Clear Enable Bit 286" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB285 ,Set/Clear Enable Bit 285" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB284 ,Set/Clear Enable Bit 284" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB283 ,Set/Clear Enable Bit 283" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB282 ,Set/Clear Enable Bit 282" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB281 ,Set/Clear Enable Bit 281" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB280 ,Set/Clear Enable Bit 280" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB279 ,Set/Clear Enable Bit 279" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB278 ,Set/Clear Enable Bit 278" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB277 ,Set/Clear Enable Bit 277" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB276 ,Set/Clear Enable Bit 276" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB275 ,Set/Clear Enable Bit 275" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB274 ,Set/Clear Enable Bit 274" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB273 ,Set/Clear Enable Bit 273" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB272 ,Set/Clear Enable Bit 272" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB271 ,Set/Clear Enable Bit 271" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB270 ,Set/Clear Enable Bit 270" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB269 ,Set/Clear Enable Bit 269" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB268 ,Set/Clear Enable Bit 268" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB267 ,Set/Clear Enable Bit 267" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB266 ,Set/Clear Enable Bit 266" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB265 ,Set/Clear Enable Bit 265" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB264 ,Set/Clear Enable Bit 264" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB263 ,Set/Clear Enable Bit 263" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB262 ,Set/Clear Enable Bit 262" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB261 ,Set/Clear Enable Bit 261" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB260 ,Set/Clear Enable Bit 260" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB259 ,Set/Clear Enable Bit 259" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB258 ,Set/Clear Enable Bit 258" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB257 ,Set/Clear Enable Bit 257" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB256 ,Set/Clear Enable Bit 256" "Disabled,Enabled" else hgroup.long 0x0120++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x0124++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB319 ,Set/Clear Enable Bit 319" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB318 ,Set/Clear Enable Bit 318" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB317 ,Set/Clear Enable Bit 317" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB316 ,Set/Clear Enable Bit 316" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB315 ,Set/Clear Enable Bit 315" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB314 ,Set/Clear Enable Bit 314" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB313 ,Set/Clear Enable Bit 313" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB312 ,Set/Clear Enable Bit 312" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB311 ,Set/Clear Enable Bit 311" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB310 ,Set/Clear Enable Bit 310" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB309 ,Set/Clear Enable Bit 309" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB308 ,Set/Clear Enable Bit 308" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB307 ,Set/Clear Enable Bit 307" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB306 ,Set/Clear Enable Bit 306" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB305 ,Set/Clear Enable Bit 305" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB304 ,Set/Clear Enable Bit 304" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB303 ,Set/Clear Enable Bit 303" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB302 ,Set/Clear Enable Bit 302" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB301 ,Set/Clear Enable Bit 301" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB300 ,Set/Clear Enable Bit 300" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB299 ,Set/Clear Enable Bit 299" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB298 ,Set/Clear Enable Bit 298" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB297 ,Set/Clear Enable Bit 297" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB296 ,Set/Clear Enable Bit 296" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB295 ,Set/Clear Enable Bit 295" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB294 ,Set/Clear Enable Bit 294" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB293 ,Set/Clear Enable Bit 293" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB292 ,Set/Clear Enable Bit 292" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB291 ,Set/Clear Enable Bit 291" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB290 ,Set/Clear Enable Bit 290" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB289 ,Set/Clear Enable Bit 289" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB288 ,Set/Clear Enable Bit 288" "Disabled,Enabled" else hgroup.long 0x0124++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x0128++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB351 ,Set/Clear Enable Bit 351" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB350 ,Set/Clear Enable Bit 350" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB349 ,Set/Clear Enable Bit 349" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB348 ,Set/Clear Enable Bit 348" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB347 ,Set/Clear Enable Bit 347" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB346 ,Set/Clear Enable Bit 346" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB345 ,Set/Clear Enable Bit 345" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB344 ,Set/Clear Enable Bit 344" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB343 ,Set/Clear Enable Bit 343" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB342 ,Set/Clear Enable Bit 342" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB341 ,Set/Clear Enable Bit 341" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB340 ,Set/Clear Enable Bit 340" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB339 ,Set/Clear Enable Bit 339" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB338 ,Set/Clear Enable Bit 338" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB337 ,Set/Clear Enable Bit 337" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB336 ,Set/Clear Enable Bit 336" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB335 ,Set/Clear Enable Bit 335" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB334 ,Set/Clear Enable Bit 334" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB333 ,Set/Clear Enable Bit 333" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB332 ,Set/Clear Enable Bit 332" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB331 ,Set/Clear Enable Bit 331" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB330 ,Set/Clear Enable Bit 330" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB329 ,Set/Clear Enable Bit 329" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB328 ,Set/Clear Enable Bit 328" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB327 ,Set/Clear Enable Bit 327" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB326 ,Set/Clear Enable Bit 326" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB325 ,Set/Clear Enable Bit 325" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB324 ,Set/Clear Enable Bit 324" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB323 ,Set/Clear Enable Bit 323" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB322 ,Set/Clear Enable Bit 322" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB321 ,Set/Clear Enable Bit 321" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB320 ,Set/Clear Enable Bit 320" "Disabled,Enabled" else hgroup.long 0x0128++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x012C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB383 ,Set/Clear Enable Bit 383" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB382 ,Set/Clear Enable Bit 382" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB381 ,Set/Clear Enable Bit 381" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB380 ,Set/Clear Enable Bit 380" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB379 ,Set/Clear Enable Bit 379" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB378 ,Set/Clear Enable Bit 378" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB377 ,Set/Clear Enable Bit 377" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB376 ,Set/Clear Enable Bit 376" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB375 ,Set/Clear Enable Bit 375" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB374 ,Set/Clear Enable Bit 374" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB373 ,Set/Clear Enable Bit 373" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB372 ,Set/Clear Enable Bit 372" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB371 ,Set/Clear Enable Bit 371" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB370 ,Set/Clear Enable Bit 370" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB369 ,Set/Clear Enable Bit 369" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB368 ,Set/Clear Enable Bit 368" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB367 ,Set/Clear Enable Bit 367" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB366 ,Set/Clear Enable Bit 366" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB365 ,Set/Clear Enable Bit 365" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB364 ,Set/Clear Enable Bit 364" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB363 ,Set/Clear Enable Bit 363" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB362 ,Set/Clear Enable Bit 362" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB361 ,Set/Clear Enable Bit 361" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB360 ,Set/Clear Enable Bit 360" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB359 ,Set/Clear Enable Bit 359" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB358 ,Set/Clear Enable Bit 358" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB357 ,Set/Clear Enable Bit 357" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB356 ,Set/Clear Enable Bit 356" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB355 ,Set/Clear Enable Bit 355" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB354 ,Set/Clear Enable Bit 354" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB353 ,Set/Clear Enable Bit 353" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB352 ,Set/Clear Enable Bit 352" "Disabled,Enabled" else hgroup.long 0x012C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x0130++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB415 ,Set/Clear Enable Bit 415" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB414 ,Set/Clear Enable Bit 414" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB413 ,Set/Clear Enable Bit 413" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB412 ,Set/Clear Enable Bit 412" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB411 ,Set/Clear Enable Bit 411" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB410 ,Set/Clear Enable Bit 410" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB409 ,Set/Clear Enable Bit 409" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB408 ,Set/Clear Enable Bit 408" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB407 ,Set/Clear Enable Bit 407" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB406 ,Set/Clear Enable Bit 406" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB405 ,Set/Clear Enable Bit 405" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB404 ,Set/Clear Enable Bit 404" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB403 ,Set/Clear Enable Bit 403" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB402 ,Set/Clear Enable Bit 402" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB401 ,Set/Clear Enable Bit 401" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB400 ,Set/Clear Enable Bit 400" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB399 ,Set/Clear Enable Bit 399" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB398 ,Set/Clear Enable Bit 398" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB397 ,Set/Clear Enable Bit 397" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB396 ,Set/Clear Enable Bit 396" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB395 ,Set/Clear Enable Bit 395" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB394 ,Set/Clear Enable Bit 394" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB393 ,Set/Clear Enable Bit 393" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB392 ,Set/Clear Enable Bit 392" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB391 ,Set/Clear Enable Bit 391" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB390 ,Set/Clear Enable Bit 390" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB389 ,Set/Clear Enable Bit 389" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB388 ,Set/Clear Enable Bit 388" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB387 ,Set/Clear Enable Bit 387" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB386 ,Set/Clear Enable Bit 386" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB385 ,Set/Clear Enable Bit 385" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB384 ,Set/Clear Enable Bit 384" "Disabled,Enabled" else hgroup.long 0x0130++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x0134++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB447 ,Set/Clear Enable Bit 447" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB446 ,Set/Clear Enable Bit 446" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB445 ,Set/Clear Enable Bit 445" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB444 ,Set/Clear Enable Bit 444" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB443 ,Set/Clear Enable Bit 443" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB442 ,Set/Clear Enable Bit 442" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB441 ,Set/Clear Enable Bit 441" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB440 ,Set/Clear Enable Bit 440" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB439 ,Set/Clear Enable Bit 439" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB438 ,Set/Clear Enable Bit 438" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB437 ,Set/Clear Enable Bit 437" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB436 ,Set/Clear Enable Bit 436" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB435 ,Set/Clear Enable Bit 435" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB434 ,Set/Clear Enable Bit 434" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB433 ,Set/Clear Enable Bit 433" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB432 ,Set/Clear Enable Bit 432" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB431 ,Set/Clear Enable Bit 431" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB430 ,Set/Clear Enable Bit 430" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB429 ,Set/Clear Enable Bit 429" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB428 ,Set/Clear Enable Bit 428" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB427 ,Set/Clear Enable Bit 427" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB426 ,Set/Clear Enable Bit 426" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB425 ,Set/Clear Enable Bit 425" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB424 ,Set/Clear Enable Bit 424" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB423 ,Set/Clear Enable Bit 423" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB422 ,Set/Clear Enable Bit 422" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB421 ,Set/Clear Enable Bit 421" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB420 ,Set/Clear Enable Bit 420" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB419 ,Set/Clear Enable Bit 419" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB418 ,Set/Clear Enable Bit 418" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB417 ,Set/Clear Enable Bit 417" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB416 ,Set/Clear Enable Bit 416" "Disabled,Enabled" else hgroup.long 0x0134++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x0138++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB479 ,Set/Clear Enable Bit 479" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB478 ,Set/Clear Enable Bit 478" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB477 ,Set/Clear Enable Bit 477" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB476 ,Set/Clear Enable Bit 476" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB475 ,Set/Clear Enable Bit 475" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB474 ,Set/Clear Enable Bit 474" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB473 ,Set/Clear Enable Bit 473" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB472 ,Set/Clear Enable Bit 472" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB471 ,Set/Clear Enable Bit 471" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB470 ,Set/Clear Enable Bit 470" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB469 ,Set/Clear Enable Bit 469" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB468 ,Set/Clear Enable Bit 468" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB467 ,Set/Clear Enable Bit 467" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB466 ,Set/Clear Enable Bit 466" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB465 ,Set/Clear Enable Bit 465" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB464 ,Set/Clear Enable Bit 464" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB463 ,Set/Clear Enable Bit 463" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB462 ,Set/Clear Enable Bit 462" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB461 ,Set/Clear Enable Bit 461" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB460 ,Set/Clear Enable Bit 460" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB459 ,Set/Clear Enable Bit 459" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB458 ,Set/Clear Enable Bit 458" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB457 ,Set/Clear Enable Bit 457" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB456 ,Set/Clear Enable Bit 456" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB455 ,Set/Clear Enable Bit 455" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB454 ,Set/Clear Enable Bit 454" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB453 ,Set/Clear Enable Bit 453" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB452 ,Set/Clear Enable Bit 452" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB451 ,Set/Clear Enable Bit 451" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB450 ,Set/Clear Enable Bit 450" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB449 ,Set/Clear Enable Bit 449" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB448 ,Set/Clear Enable Bit 448" "Disabled,Enabled" else hgroup.long 0x0138++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x013C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB511 ,Set/Clear Enable Bit 511" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB510 ,Set/Clear Enable Bit 510" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB509 ,Set/Clear Enable Bit 509" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB508 ,Set/Clear Enable Bit 508" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB507 ,Set/Clear Enable Bit 507" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB506 ,Set/Clear Enable Bit 506" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB505 ,Set/Clear Enable Bit 505" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB504 ,Set/Clear Enable Bit 504" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB503 ,Set/Clear Enable Bit 503" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB502 ,Set/Clear Enable Bit 502" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB501 ,Set/Clear Enable Bit 501" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB500 ,Set/Clear Enable Bit 500" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB499 ,Set/Clear Enable Bit 499" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB498 ,Set/Clear Enable Bit 498" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB497 ,Set/Clear Enable Bit 497" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB496 ,Set/Clear Enable Bit 496" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB495 ,Set/Clear Enable Bit 495" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB494 ,Set/Clear Enable Bit 494" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB493 ,Set/Clear Enable Bit 493" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB492 ,Set/Clear Enable Bit 492" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB491 ,Set/Clear Enable Bit 491" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB490 ,Set/Clear Enable Bit 490" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB489 ,Set/Clear Enable Bit 489" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB488 ,Set/Clear Enable Bit 488" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB487 ,Set/Clear Enable Bit 487" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB486 ,Set/Clear Enable Bit 486" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB485 ,Set/Clear Enable Bit 485" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB484 ,Set/Clear Enable Bit 484" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB483 ,Set/Clear Enable Bit 483" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB482 ,Set/Clear Enable Bit 482" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB481 ,Set/Clear Enable Bit 481" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB480 ,Set/Clear Enable Bit 480" "Disabled,Enabled" else hgroup.long 0x013C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x0140++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB543 ,Set/Clear Enable Bit 543" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB542 ,Set/Clear Enable Bit 542" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB541 ,Set/Clear Enable Bit 541" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB540 ,Set/Clear Enable Bit 540" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB539 ,Set/Clear Enable Bit 539" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB538 ,Set/Clear Enable Bit 538" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB537 ,Set/Clear Enable Bit 537" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB536 ,Set/Clear Enable Bit 536" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB535 ,Set/Clear Enable Bit 535" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB534 ,Set/Clear Enable Bit 534" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB533 ,Set/Clear Enable Bit 533" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB532 ,Set/Clear Enable Bit 532" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB531 ,Set/Clear Enable Bit 531" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB530 ,Set/Clear Enable Bit 530" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB529 ,Set/Clear Enable Bit 529" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB528 ,Set/Clear Enable Bit 528" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB527 ,Set/Clear Enable Bit 527" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB526 ,Set/Clear Enable Bit 526" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB525 ,Set/Clear Enable Bit 525" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB524 ,Set/Clear Enable Bit 524" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB523 ,Set/Clear Enable Bit 523" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB522 ,Set/Clear Enable Bit 522" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB521 ,Set/Clear Enable Bit 521" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB520 ,Set/Clear Enable Bit 520" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB519 ,Set/Clear Enable Bit 519" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB518 ,Set/Clear Enable Bit 518" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB517 ,Set/Clear Enable Bit 517" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB516 ,Set/Clear Enable Bit 516" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB515 ,Set/Clear Enable Bit 515" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB514 ,Set/Clear Enable Bit 514" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB513 ,Set/Clear Enable Bit 513" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB512 ,Set/Clear Enable Bit 512" "Disabled,Enabled" else hgroup.long 0x0140++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x0144++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB575 ,Set/Clear Enable Bit 575" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB574 ,Set/Clear Enable Bit 574" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB573 ,Set/Clear Enable Bit 573" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB572 ,Set/Clear Enable Bit 572" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB571 ,Set/Clear Enable Bit 571" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB570 ,Set/Clear Enable Bit 570" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB569 ,Set/Clear Enable Bit 569" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB568 ,Set/Clear Enable Bit 568" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB567 ,Set/Clear Enable Bit 567" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB566 ,Set/Clear Enable Bit 566" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB565 ,Set/Clear Enable Bit 565" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB564 ,Set/Clear Enable Bit 564" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB563 ,Set/Clear Enable Bit 563" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB562 ,Set/Clear Enable Bit 562" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB561 ,Set/Clear Enable Bit 561" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB560 ,Set/Clear Enable Bit 560" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB559 ,Set/Clear Enable Bit 559" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB558 ,Set/Clear Enable Bit 558" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB557 ,Set/Clear Enable Bit 557" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB556 ,Set/Clear Enable Bit 556" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB555 ,Set/Clear Enable Bit 555" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB554 ,Set/Clear Enable Bit 554" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB553 ,Set/Clear Enable Bit 553" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB552 ,Set/Clear Enable Bit 552" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB551 ,Set/Clear Enable Bit 551" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB550 ,Set/Clear Enable Bit 550" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB549 ,Set/Clear Enable Bit 549" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB548 ,Set/Clear Enable Bit 548" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB547 ,Set/Clear Enable Bit 547" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB546 ,Set/Clear Enable Bit 546" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB545 ,Set/Clear Enable Bit 545" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB544 ,Set/Clear Enable Bit 544" "Disabled,Enabled" else hgroup.long 0x0144++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x0148++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB607 ,Set/Clear Enable Bit 607" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB606 ,Set/Clear Enable Bit 606" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB605 ,Set/Clear Enable Bit 605" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB604 ,Set/Clear Enable Bit 604" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB603 ,Set/Clear Enable Bit 603" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB602 ,Set/Clear Enable Bit 602" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB601 ,Set/Clear Enable Bit 601" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB600 ,Set/Clear Enable Bit 600" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB599 ,Set/Clear Enable Bit 599" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB598 ,Set/Clear Enable Bit 598" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB597 ,Set/Clear Enable Bit 597" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB596 ,Set/Clear Enable Bit 596" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB595 ,Set/Clear Enable Bit 595" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB594 ,Set/Clear Enable Bit 594" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB593 ,Set/Clear Enable Bit 593" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB592 ,Set/Clear Enable Bit 592" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB591 ,Set/Clear Enable Bit 591" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB590 ,Set/Clear Enable Bit 590" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB589 ,Set/Clear Enable Bit 589" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB588 ,Set/Clear Enable Bit 588" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB587 ,Set/Clear Enable Bit 587" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB586 ,Set/Clear Enable Bit 586" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB585 ,Set/Clear Enable Bit 585" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB584 ,Set/Clear Enable Bit 584" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB583 ,Set/Clear Enable Bit 583" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB582 ,Set/Clear Enable Bit 582" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB581 ,Set/Clear Enable Bit 581" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB580 ,Set/Clear Enable Bit 580" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB579 ,Set/Clear Enable Bit 579" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB578 ,Set/Clear Enable Bit 578" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB577 ,Set/Clear Enable Bit 577" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB576 ,Set/Clear Enable Bit 576" "Disabled,Enabled" else hgroup.long 0x0148++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x014C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB639 ,Set/Clear Enable Bit 639" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB638 ,Set/Clear Enable Bit 638" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB637 ,Set/Clear Enable Bit 637" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB636 ,Set/Clear Enable Bit 636" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB635 ,Set/Clear Enable Bit 635" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB634 ,Set/Clear Enable Bit 634" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB633 ,Set/Clear Enable Bit 633" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB632 ,Set/Clear Enable Bit 632" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB631 ,Set/Clear Enable Bit 631" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB630 ,Set/Clear Enable Bit 630" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB629 ,Set/Clear Enable Bit 629" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB628 ,Set/Clear Enable Bit 628" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB627 ,Set/Clear Enable Bit 627" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB626 ,Set/Clear Enable Bit 626" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB625 ,Set/Clear Enable Bit 625" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB624 ,Set/Clear Enable Bit 624" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB623 ,Set/Clear Enable Bit 623" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB622 ,Set/Clear Enable Bit 622" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB621 ,Set/Clear Enable Bit 621" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB620 ,Set/Clear Enable Bit 620" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB619 ,Set/Clear Enable Bit 619" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB618 ,Set/Clear Enable Bit 618" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB617 ,Set/Clear Enable Bit 617" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB616 ,Set/Clear Enable Bit 616" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB615 ,Set/Clear Enable Bit 615" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB614 ,Set/Clear Enable Bit 614" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB613 ,Set/Clear Enable Bit 613" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB612 ,Set/Clear Enable Bit 612" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB611 ,Set/Clear Enable Bit 611" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB610 ,Set/Clear Enable Bit 610" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB609 ,Set/Clear Enable Bit 609" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB608 ,Set/Clear Enable Bit 608" "Disabled,Enabled" else hgroup.long 0x014C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x0150++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB671 ,Set/Clear Enable Bit 671" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB670 ,Set/Clear Enable Bit 670" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB669 ,Set/Clear Enable Bit 669" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB668 ,Set/Clear Enable Bit 668" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB667 ,Set/Clear Enable Bit 667" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB666 ,Set/Clear Enable Bit 666" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB665 ,Set/Clear Enable Bit 665" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB664 ,Set/Clear Enable Bit 664" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB663 ,Set/Clear Enable Bit 663" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB662 ,Set/Clear Enable Bit 662" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB661 ,Set/Clear Enable Bit 661" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB660 ,Set/Clear Enable Bit 660" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB659 ,Set/Clear Enable Bit 659" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB658 ,Set/Clear Enable Bit 658" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB657 ,Set/Clear Enable Bit 657" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB656 ,Set/Clear Enable Bit 656" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB655 ,Set/Clear Enable Bit 655" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB654 ,Set/Clear Enable Bit 654" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB653 ,Set/Clear Enable Bit 653" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB652 ,Set/Clear Enable Bit 652" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB651 ,Set/Clear Enable Bit 651" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB650 ,Set/Clear Enable Bit 650" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB649 ,Set/Clear Enable Bit 649" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB648 ,Set/Clear Enable Bit 648" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB647 ,Set/Clear Enable Bit 647" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB646 ,Set/Clear Enable Bit 646" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB645 ,Set/Clear Enable Bit 645" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB644 ,Set/Clear Enable Bit 644" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB643 ,Set/Clear Enable Bit 643" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB642 ,Set/Clear Enable Bit 642" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB641 ,Set/Clear Enable Bit 641" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB640 ,Set/Clear Enable Bit 640" "Disabled,Enabled" else hgroup.long 0x0150++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x0154++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB703 ,Set/Clear Enable Bit 703" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB702 ,Set/Clear Enable Bit 702" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB701 ,Set/Clear Enable Bit 701" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB700 ,Set/Clear Enable Bit 700" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB699 ,Set/Clear Enable Bit 699" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB698 ,Set/Clear Enable Bit 698" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB697 ,Set/Clear Enable Bit 697" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB696 ,Set/Clear Enable Bit 696" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB695 ,Set/Clear Enable Bit 695" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB694 ,Set/Clear Enable Bit 694" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB693 ,Set/Clear Enable Bit 693" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB692 ,Set/Clear Enable Bit 692" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB691 ,Set/Clear Enable Bit 691" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB690 ,Set/Clear Enable Bit 690" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB689 ,Set/Clear Enable Bit 689" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB688 ,Set/Clear Enable Bit 688" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB687 ,Set/Clear Enable Bit 687" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB686 ,Set/Clear Enable Bit 686" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB685 ,Set/Clear Enable Bit 685" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB684 ,Set/Clear Enable Bit 684" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB683 ,Set/Clear Enable Bit 683" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB682 ,Set/Clear Enable Bit 682" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB681 ,Set/Clear Enable Bit 681" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB680 ,Set/Clear Enable Bit 680" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB679 ,Set/Clear Enable Bit 679" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB678 ,Set/Clear Enable Bit 678" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB677 ,Set/Clear Enable Bit 677" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB676 ,Set/Clear Enable Bit 676" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB675 ,Set/Clear Enable Bit 675" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB674 ,Set/Clear Enable Bit 674" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB673 ,Set/Clear Enable Bit 673" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB672 ,Set/Clear Enable Bit 672" "Disabled,Enabled" else hgroup.long 0x0154++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x0158++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB735 ,Set/Clear Enable Bit 735" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB734 ,Set/Clear Enable Bit 734" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB733 ,Set/Clear Enable Bit 733" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB732 ,Set/Clear Enable Bit 732" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB731 ,Set/Clear Enable Bit 731" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB730 ,Set/Clear Enable Bit 730" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB729 ,Set/Clear Enable Bit 729" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB728 ,Set/Clear Enable Bit 728" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB727 ,Set/Clear Enable Bit 727" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB726 ,Set/Clear Enable Bit 726" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB725 ,Set/Clear Enable Bit 725" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB724 ,Set/Clear Enable Bit 724" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB723 ,Set/Clear Enable Bit 723" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB722 ,Set/Clear Enable Bit 722" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB721 ,Set/Clear Enable Bit 721" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB720 ,Set/Clear Enable Bit 720" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB719 ,Set/Clear Enable Bit 719" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB718 ,Set/Clear Enable Bit 718" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB717 ,Set/Clear Enable Bit 717" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB716 ,Set/Clear Enable Bit 716" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB715 ,Set/Clear Enable Bit 715" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB714 ,Set/Clear Enable Bit 714" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB713 ,Set/Clear Enable Bit 713" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB712 ,Set/Clear Enable Bit 712" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB711 ,Set/Clear Enable Bit 711" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB710 ,Set/Clear Enable Bit 710" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB709 ,Set/Clear Enable Bit 709" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB708 ,Set/Clear Enable Bit 708" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB707 ,Set/Clear Enable Bit 707" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB706 ,Set/Clear Enable Bit 706" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB705 ,Set/Clear Enable Bit 705" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB704 ,Set/Clear Enable Bit 704" "Disabled,Enabled" else hgroup.long 0x0158++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x015C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB767 ,Set/Clear Enable Bit 767" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB766 ,Set/Clear Enable Bit 766" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB765 ,Set/Clear Enable Bit 765" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB764 ,Set/Clear Enable Bit 764" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB763 ,Set/Clear Enable Bit 763" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB762 ,Set/Clear Enable Bit 762" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB761 ,Set/Clear Enable Bit 761" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB760 ,Set/Clear Enable Bit 760" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB759 ,Set/Clear Enable Bit 759" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB758 ,Set/Clear Enable Bit 758" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB757 ,Set/Clear Enable Bit 757" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB756 ,Set/Clear Enable Bit 756" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB755 ,Set/Clear Enable Bit 755" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB754 ,Set/Clear Enable Bit 754" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB753 ,Set/Clear Enable Bit 753" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB752 ,Set/Clear Enable Bit 752" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB751 ,Set/Clear Enable Bit 751" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB750 ,Set/Clear Enable Bit 750" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB749 ,Set/Clear Enable Bit 749" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB748 ,Set/Clear Enable Bit 748" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB747 ,Set/Clear Enable Bit 747" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB746 ,Set/Clear Enable Bit 746" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB745 ,Set/Clear Enable Bit 745" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB744 ,Set/Clear Enable Bit 744" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB743 ,Set/Clear Enable Bit 743" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB742 ,Set/Clear Enable Bit 742" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB741 ,Set/Clear Enable Bit 741" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB740 ,Set/Clear Enable Bit 740" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB739 ,Set/Clear Enable Bit 739" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB738 ,Set/Clear Enable Bit 738" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB737 ,Set/Clear Enable Bit 737" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB736 ,Set/Clear Enable Bit 736" "Disabled,Enabled" else hgroup.long 0x015C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x0160++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB799 ,Set/Clear Enable Bit 799" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB798 ,Set/Clear Enable Bit 798" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB797 ,Set/Clear Enable Bit 797" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB796 ,Set/Clear Enable Bit 796" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB795 ,Set/Clear Enable Bit 795" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB794 ,Set/Clear Enable Bit 794" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB793 ,Set/Clear Enable Bit 793" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB792 ,Set/Clear Enable Bit 792" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB791 ,Set/Clear Enable Bit 791" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB790 ,Set/Clear Enable Bit 790" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB789 ,Set/Clear Enable Bit 789" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB788 ,Set/Clear Enable Bit 788" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB787 ,Set/Clear Enable Bit 787" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB786 ,Set/Clear Enable Bit 786" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB785 ,Set/Clear Enable Bit 785" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB784 ,Set/Clear Enable Bit 784" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB783 ,Set/Clear Enable Bit 783" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB782 ,Set/Clear Enable Bit 782" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB781 ,Set/Clear Enable Bit 781" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB780 ,Set/Clear Enable Bit 780" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB779 ,Set/Clear Enable Bit 779" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB778 ,Set/Clear Enable Bit 778" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB777 ,Set/Clear Enable Bit 777" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB776 ,Set/Clear Enable Bit 776" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB775 ,Set/Clear Enable Bit 775" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB774 ,Set/Clear Enable Bit 774" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB773 ,Set/Clear Enable Bit 773" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB772 ,Set/Clear Enable Bit 772" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB771 ,Set/Clear Enable Bit 771" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB770 ,Set/Clear Enable Bit 770" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB769 ,Set/Clear Enable Bit 769" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB768 ,Set/Clear Enable Bit 768" "Disabled,Enabled" else hgroup.long 0x0160++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x0164++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB831 ,Set/Clear Enable Bit 831" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB830 ,Set/Clear Enable Bit 830" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB829 ,Set/Clear Enable Bit 829" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB828 ,Set/Clear Enable Bit 828" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB827 ,Set/Clear Enable Bit 827" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB826 ,Set/Clear Enable Bit 826" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB825 ,Set/Clear Enable Bit 825" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB824 ,Set/Clear Enable Bit 824" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB823 ,Set/Clear Enable Bit 823" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB822 ,Set/Clear Enable Bit 822" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB821 ,Set/Clear Enable Bit 821" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB820 ,Set/Clear Enable Bit 820" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB819 ,Set/Clear Enable Bit 819" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB818 ,Set/Clear Enable Bit 818" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB817 ,Set/Clear Enable Bit 817" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB816 ,Set/Clear Enable Bit 816" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB815 ,Set/Clear Enable Bit 815" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB814 ,Set/Clear Enable Bit 814" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB813 ,Set/Clear Enable Bit 813" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB812 ,Set/Clear Enable Bit 812" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB811 ,Set/Clear Enable Bit 811" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB810 ,Set/Clear Enable Bit 810" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB809 ,Set/Clear Enable Bit 809" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB808 ,Set/Clear Enable Bit 808" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB807 ,Set/Clear Enable Bit 807" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB806 ,Set/Clear Enable Bit 806" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB805 ,Set/Clear Enable Bit 805" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB804 ,Set/Clear Enable Bit 804" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB803 ,Set/Clear Enable Bit 803" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB802 ,Set/Clear Enable Bit 802" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB801 ,Set/Clear Enable Bit 801" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB800 ,Set/Clear Enable Bit 800" "Disabled,Enabled" else hgroup.long 0x0164++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x0168++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB863 ,Set/Clear Enable Bit 863" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB862 ,Set/Clear Enable Bit 862" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB861 ,Set/Clear Enable Bit 861" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB860 ,Set/Clear Enable Bit 860" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB859 ,Set/Clear Enable Bit 859" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB858 ,Set/Clear Enable Bit 858" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB857 ,Set/Clear Enable Bit 857" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB856 ,Set/Clear Enable Bit 856" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB855 ,Set/Clear Enable Bit 855" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB854 ,Set/Clear Enable Bit 854" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB853 ,Set/Clear Enable Bit 853" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB852 ,Set/Clear Enable Bit 852" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB851 ,Set/Clear Enable Bit 851" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB850 ,Set/Clear Enable Bit 850" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB849 ,Set/Clear Enable Bit 849" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB848 ,Set/Clear Enable Bit 848" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB847 ,Set/Clear Enable Bit 847" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB846 ,Set/Clear Enable Bit 846" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB845 ,Set/Clear Enable Bit 845" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB844 ,Set/Clear Enable Bit 844" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB843 ,Set/Clear Enable Bit 843" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB842 ,Set/Clear Enable Bit 842" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB841 ,Set/Clear Enable Bit 841" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB840 ,Set/Clear Enable Bit 840" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB839 ,Set/Clear Enable Bit 839" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB838 ,Set/Clear Enable Bit 838" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB837 ,Set/Clear Enable Bit 837" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB836 ,Set/Clear Enable Bit 836" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB835 ,Set/Clear Enable Bit 835" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB834 ,Set/Clear Enable Bit 834" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB833 ,Set/Clear Enable Bit 833" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB832 ,Set/Clear Enable Bit 832" "Disabled,Enabled" else hgroup.long 0x0168++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x016C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB895 ,Set/Clear Enable Bit 895" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB894 ,Set/Clear Enable Bit 894" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB893 ,Set/Clear Enable Bit 893" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB892 ,Set/Clear Enable Bit 892" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB891 ,Set/Clear Enable Bit 891" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB890 ,Set/Clear Enable Bit 890" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB889 ,Set/Clear Enable Bit 889" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB888 ,Set/Clear Enable Bit 888" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB887 ,Set/Clear Enable Bit 887" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB886 ,Set/Clear Enable Bit 886" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB885 ,Set/Clear Enable Bit 885" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB884 ,Set/Clear Enable Bit 884" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB883 ,Set/Clear Enable Bit 883" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB882 ,Set/Clear Enable Bit 882" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB881 ,Set/Clear Enable Bit 881" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB880 ,Set/Clear Enable Bit 880" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB879 ,Set/Clear Enable Bit 879" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB878 ,Set/Clear Enable Bit 878" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB877 ,Set/Clear Enable Bit 877" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB876 ,Set/Clear Enable Bit 876" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB875 ,Set/Clear Enable Bit 875" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB874 ,Set/Clear Enable Bit 874" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB873 ,Set/Clear Enable Bit 873" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB872 ,Set/Clear Enable Bit 872" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB871 ,Set/Clear Enable Bit 871" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB870 ,Set/Clear Enable Bit 870" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB869 ,Set/Clear Enable Bit 869" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB868 ,Set/Clear Enable Bit 868" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB867 ,Set/Clear Enable Bit 867" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB866 ,Set/Clear Enable Bit 866" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB865 ,Set/Clear Enable Bit 865" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB864 ,Set/Clear Enable Bit 864" "Disabled,Enabled" else hgroup.long 0x016C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x0170++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB927 ,Set/Clear Enable Bit 927" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB926 ,Set/Clear Enable Bit 926" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB925 ,Set/Clear Enable Bit 925" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB924 ,Set/Clear Enable Bit 924" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB923 ,Set/Clear Enable Bit 923" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB922 ,Set/Clear Enable Bit 922" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB921 ,Set/Clear Enable Bit 921" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB920 ,Set/Clear Enable Bit 920" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB919 ,Set/Clear Enable Bit 919" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB918 ,Set/Clear Enable Bit 918" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB917 ,Set/Clear Enable Bit 917" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB916 ,Set/Clear Enable Bit 916" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB915 ,Set/Clear Enable Bit 915" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB914 ,Set/Clear Enable Bit 914" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB913 ,Set/Clear Enable Bit 913" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB912 ,Set/Clear Enable Bit 912" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB911 ,Set/Clear Enable Bit 911" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB910 ,Set/Clear Enable Bit 910" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB909 ,Set/Clear Enable Bit 909" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB908 ,Set/Clear Enable Bit 908" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB907 ,Set/Clear Enable Bit 907" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB906 ,Set/Clear Enable Bit 906" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB905 ,Set/Clear Enable Bit 905" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB904 ,Set/Clear Enable Bit 904" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB903 ,Set/Clear Enable Bit 903" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB902 ,Set/Clear Enable Bit 902" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB901 ,Set/Clear Enable Bit 901" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB900 ,Set/Clear Enable Bit 900" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB899 ,Set/Clear Enable Bit 899" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB898 ,Set/Clear Enable Bit 898" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB897 ,Set/Clear Enable Bit 897" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB896 ,Set/Clear Enable Bit 896" "Disabled,Enabled" else hgroup.long 0x0170++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x0174++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB959 ,Set/Clear Enable Bit 959" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB958 ,Set/Clear Enable Bit 958" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB957 ,Set/Clear Enable Bit 957" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB956 ,Set/Clear Enable Bit 956" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB955 ,Set/Clear Enable Bit 955" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB954 ,Set/Clear Enable Bit 954" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB953 ,Set/Clear Enable Bit 953" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB952 ,Set/Clear Enable Bit 952" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB951 ,Set/Clear Enable Bit 951" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB950 ,Set/Clear Enable Bit 950" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB949 ,Set/Clear Enable Bit 949" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB948 ,Set/Clear Enable Bit 948" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB947 ,Set/Clear Enable Bit 947" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB946 ,Set/Clear Enable Bit 946" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB945 ,Set/Clear Enable Bit 945" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB944 ,Set/Clear Enable Bit 944" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB943 ,Set/Clear Enable Bit 943" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB942 ,Set/Clear Enable Bit 942" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB941 ,Set/Clear Enable Bit 941" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB940 ,Set/Clear Enable Bit 940" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB939 ,Set/Clear Enable Bit 939" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB938 ,Set/Clear Enable Bit 938" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB937 ,Set/Clear Enable Bit 937" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB936 ,Set/Clear Enable Bit 936" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB935 ,Set/Clear Enable Bit 935" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB934 ,Set/Clear Enable Bit 934" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB933 ,Set/Clear Enable Bit 933" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB932 ,Set/Clear Enable Bit 932" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB931 ,Set/Clear Enable Bit 931" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB930 ,Set/Clear Enable Bit 930" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB929 ,Set/Clear Enable Bit 929" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB928 ,Set/Clear Enable Bit 928" "Disabled,Enabled" else hgroup.long 0x0174++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x0178++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB991 ,Set/Clear Enable Bit 991" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB990 ,Set/Clear Enable Bit 990" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB989 ,Set/Clear Enable Bit 989" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB988 ,Set/Clear Enable Bit 988" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB987 ,Set/Clear Enable Bit 987" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB986 ,Set/Clear Enable Bit 986" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB985 ,Set/Clear Enable Bit 985" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB984 ,Set/Clear Enable Bit 984" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB983 ,Set/Clear Enable Bit 983" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB982 ,Set/Clear Enable Bit 982" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB981 ,Set/Clear Enable Bit 981" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB980 ,Set/Clear Enable Bit 980" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB979 ,Set/Clear Enable Bit 979" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB978 ,Set/Clear Enable Bit 978" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB977 ,Set/Clear Enable Bit 977" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB976 ,Set/Clear Enable Bit 976" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB975 ,Set/Clear Enable Bit 975" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB974 ,Set/Clear Enable Bit 974" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB973 ,Set/Clear Enable Bit 973" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB972 ,Set/Clear Enable Bit 972" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB971 ,Set/Clear Enable Bit 971" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB970 ,Set/Clear Enable Bit 970" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB969 ,Set/Clear Enable Bit 969" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB968 ,Set/Clear Enable Bit 968" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB967 ,Set/Clear Enable Bit 967" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB966 ,Set/Clear Enable Bit 966" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB965 ,Set/Clear Enable Bit 965" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB964 ,Set/Clear Enable Bit 964" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB963 ,Set/Clear Enable Bit 963" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB962 ,Set/Clear Enable Bit 962" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB961 ,Set/Clear Enable Bit 961" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB960 ,Set/Clear Enable Bit 960" "Disabled,Enabled" else hgroup.long 0x0178++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" endif tree.end width 22. tree "Set/Clear Pending Registers" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x0200++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0" newline newline newline newline newline newline newline newline newline newline else group.long 0x0200++0x03 line.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31 ,Set/Clear Pending Bit 31" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND30 ,Set/Clear Pending Bit 30" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND29 ,Set/Clear Pending Bit 29" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28 ,Set/Clear Pending Bit 28" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND27 ,Set/Clear Pending Bit 27" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND26 ,Set/Clear Pending Bit 26" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25 ,Set/Clear Pending Bit 25" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND24 ,Set/Clear Pending Bit 24" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND23 ,Set/Clear Pending Bit 23" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22 ,Set/Clear Pending Bit 22" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND21 ,Set/Clear Pending Bit 21" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND20 ,Set/Clear Pending Bit 20" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19 ,Set/Clear Pending Bit 19" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND18 ,Set/Clear Pending Bit 18" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND17 ,Set/Clear Pending Bit 17" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16 ,Set/Clear Pending Bit 16" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND15 ,Set/Clear Pending Bit 15" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND14 ,Set/Clear Pending Bit 14" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13 ,Set/Clear Pending Bit 13" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND12 ,Set/Clear Pending Bit 12" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND11 ,Set/Clear Pending Bit 11" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10 ,Set/Clear Pending Bit 10" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND9 ,Set/Clear Pending Bit 9" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND8 ,Set/Clear Pending Bit 8" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7 ,Set/Clear Pending Bit 7" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND6 ,Set/Clear Pending Bit 6" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND5 ,Set/Clear Pending Bit 5" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4 ,Set/Clear Pending Bit 4" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND3 ,Set/Clear Pending Bit 3" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND2 ,Set/Clear Pending Bit 2" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1 ,Set/Clear Pending Bit 1" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND0 ,Set/Clear Pending Bit 0" "Not pending,Pending" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x0204++0x03 line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND63 ,Set/Clear Pending Bit 63" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND62 ,Set/Clear Pending Bit 62" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND61 ,Set/Clear Pending Bit 61" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND60 ,Set/Clear Pending Bit 60" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND59 ,Set/Clear Pending Bit 59" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND58 ,Set/Clear Pending Bit 58" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND57 ,Set/Clear Pending Bit 57" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND56 ,Set/Clear Pending Bit 56" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND55 ,Set/Clear Pending Bit 55" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND54 ,Set/Clear Pending Bit 54" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND53 ,Set/Clear Pending Bit 53" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND52 ,Set/Clear Pending Bit 52" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND51 ,Set/Clear Pending Bit 51" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND50 ,Set/Clear Pending Bit 50" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND49 ,Set/Clear Pending Bit 49" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND48 ,Set/Clear Pending Bit 48" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND47 ,Set/Clear Pending Bit 47" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND46 ,Set/Clear Pending Bit 46" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND45 ,Set/Clear Pending Bit 45" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND44 ,Set/Clear Pending Bit 44" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND43 ,Set/Clear Pending Bit 43" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND42 ,Set/Clear Pending Bit 42" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND41 ,Set/Clear Pending Bit 41" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND40 ,Set/Clear Pending Bit 40" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND39 ,Set/Clear Pending Bit 39" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND38 ,Set/Clear Pending Bit 38" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND37 ,Set/Clear Pending Bit 37" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND36 ,Set/Clear Pending Bit 36" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND35 ,Set/Clear Pending Bit 35" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND34 ,Set/Clear Pending Bit 34" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND33 ,Set/Clear Pending Bit 33" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND32 ,Set/Clear Pending Bit 32" "Not pending,Pending" else hgroup.long 0x0204++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x0208++0x03 line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND95 ,Set/Clear Pending Bit 95" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND94 ,Set/Clear Pending Bit 94" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND93 ,Set/Clear Pending Bit 93" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND92 ,Set/Clear Pending Bit 92" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND91 ,Set/Clear Pending Bit 91" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND90 ,Set/Clear Pending Bit 90" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND89 ,Set/Clear Pending Bit 89" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND88 ,Set/Clear Pending Bit 88" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND87 ,Set/Clear Pending Bit 87" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND86 ,Set/Clear Pending Bit 86" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND85 ,Set/Clear Pending Bit 85" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND84 ,Set/Clear Pending Bit 84" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND83 ,Set/Clear Pending Bit 83" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND82 ,Set/Clear Pending Bit 82" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND81 ,Set/Clear Pending Bit 81" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND80 ,Set/Clear Pending Bit 80" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND79 ,Set/Clear Pending Bit 79" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND78 ,Set/Clear Pending Bit 78" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND77 ,Set/Clear Pending Bit 77" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND76 ,Set/Clear Pending Bit 76" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND75 ,Set/Clear Pending Bit 75" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND74 ,Set/Clear Pending Bit 74" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND73 ,Set/Clear Pending Bit 73" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND72 ,Set/Clear Pending Bit 72" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND71 ,Set/Clear Pending Bit 71" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND70 ,Set/Clear Pending Bit 70" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND69 ,Set/Clear Pending Bit 69" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND68 ,Set/Clear Pending Bit 68" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND67 ,Set/Clear Pending Bit 67" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND66 ,Set/Clear Pending Bit 66" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND65 ,Set/Clear Pending Bit 65" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND64 ,Set/Clear Pending Bit 64" "Not pending,Pending" else hgroup.long 0x0208++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x020C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND127 ,Set/Clear Pending Bit 127" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND126 ,Set/Clear Pending Bit 126" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND125 ,Set/Clear Pending Bit 125" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND124 ,Set/Clear Pending Bit 124" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND123 ,Set/Clear Pending Bit 123" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND122 ,Set/Clear Pending Bit 122" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND121 ,Set/Clear Pending Bit 121" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND120 ,Set/Clear Pending Bit 120" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND119 ,Set/Clear Pending Bit 119" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND118 ,Set/Clear Pending Bit 118" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND117 ,Set/Clear Pending Bit 117" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND116 ,Set/Clear Pending Bit 116" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND115 ,Set/Clear Pending Bit 115" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND114 ,Set/Clear Pending Bit 114" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND113 ,Set/Clear Pending Bit 113" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND112 ,Set/Clear Pending Bit 112" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND111 ,Set/Clear Pending Bit 111" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND110 ,Set/Clear Pending Bit 110" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND109 ,Set/Clear Pending Bit 109" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND108 ,Set/Clear Pending Bit 108" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND107 ,Set/Clear Pending Bit 107" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND106 ,Set/Clear Pending Bit 106" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND105 ,Set/Clear Pending Bit 105" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND104 ,Set/Clear Pending Bit 104" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND103 ,Set/Clear Pending Bit 103" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND102 ,Set/Clear Pending Bit 102" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND101 ,Set/Clear Pending Bit 101" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND100 ,Set/Clear Pending Bit 100" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND99 ,Set/Clear Pending Bit 99" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND98 ,Set/Clear Pending Bit 98" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND97 ,Set/Clear Pending Bit 97" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND96 ,Set/Clear Pending Bit 96" "Not pending,Pending" else hgroup.long 0x020C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x0210++0x03 line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND159 ,Set/Clear Pending Bit 159" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND158 ,Set/Clear Pending Bit 158" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND157 ,Set/Clear Pending Bit 157" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND156 ,Set/Clear Pending Bit 156" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND155 ,Set/Clear Pending Bit 155" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND154 ,Set/Clear Pending Bit 154" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND153 ,Set/Clear Pending Bit 153" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND152 ,Set/Clear Pending Bit 152" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND151 ,Set/Clear Pending Bit 151" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND150 ,Set/Clear Pending Bit 150" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND149 ,Set/Clear Pending Bit 149" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND148 ,Set/Clear Pending Bit 148" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND147 ,Set/Clear Pending Bit 147" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND146 ,Set/Clear Pending Bit 146" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND145 ,Set/Clear Pending Bit 145" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND144 ,Set/Clear Pending Bit 144" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND143 ,Set/Clear Pending Bit 143" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND142 ,Set/Clear Pending Bit 142" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND141 ,Set/Clear Pending Bit 141" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND140 ,Set/Clear Pending Bit 140" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND139 ,Set/Clear Pending Bit 139" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND138 ,Set/Clear Pending Bit 138" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND137 ,Set/Clear Pending Bit 137" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND136 ,Set/Clear Pending Bit 136" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND135 ,Set/Clear Pending Bit 135" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND134 ,Set/Clear Pending Bit 134" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND133 ,Set/Clear Pending Bit 133" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND132 ,Set/Clear Pending Bit 132" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND131 ,Set/Clear Pending Bit 131" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND130 ,Set/Clear Pending Bit 130" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND129 ,Set/Clear Pending Bit 129" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND128 ,Set/Clear Pending Bit 128" "Not pending,Pending" else hgroup.long 0x0210++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x0214++0x03 line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND191 ,Set/Clear Pending Bit 191" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND190 ,Set/Clear Pending Bit 190" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND189 ,Set/Clear Pending Bit 189" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND188 ,Set/Clear Pending Bit 188" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND187 ,Set/Clear Pending Bit 187" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND186 ,Set/Clear Pending Bit 186" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND185 ,Set/Clear Pending Bit 185" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND184 ,Set/Clear Pending Bit 184" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND183 ,Set/Clear Pending Bit 183" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND182 ,Set/Clear Pending Bit 182" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND181 ,Set/Clear Pending Bit 181" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND180 ,Set/Clear Pending Bit 180" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND179 ,Set/Clear Pending Bit 179" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND178 ,Set/Clear Pending Bit 178" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND177 ,Set/Clear Pending Bit 177" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND176 ,Set/Clear Pending Bit 176" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND175 ,Set/Clear Pending Bit 175" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND174 ,Set/Clear Pending Bit 174" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND173 ,Set/Clear Pending Bit 173" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND172 ,Set/Clear Pending Bit 172" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND171 ,Set/Clear Pending Bit 171" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND170 ,Set/Clear Pending Bit 170" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND169 ,Set/Clear Pending Bit 169" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND168 ,Set/Clear Pending Bit 168" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND167 ,Set/Clear Pending Bit 167" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND166 ,Set/Clear Pending Bit 166" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND165 ,Set/Clear Pending Bit 165" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND164 ,Set/Clear Pending Bit 164" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND163 ,Set/Clear Pending Bit 163" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND162 ,Set/Clear Pending Bit 162" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND161 ,Set/Clear Pending Bit 161" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND160 ,Set/Clear Pending Bit 160" "Not pending,Pending" else hgroup.long 0x0214++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x0218++0x03 line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND223 ,Set/Clear Pending Bit 223" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND222 ,Set/Clear Pending Bit 222" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND221 ,Set/Clear Pending Bit 221" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND220 ,Set/Clear Pending Bit 220" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND219 ,Set/Clear Pending Bit 219" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND218 ,Set/Clear Pending Bit 218" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND217 ,Set/Clear Pending Bit 217" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND216 ,Set/Clear Pending Bit 216" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND215 ,Set/Clear Pending Bit 215" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND214 ,Set/Clear Pending Bit 214" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND213 ,Set/Clear Pending Bit 213" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND212 ,Set/Clear Pending Bit 212" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND211 ,Set/Clear Pending Bit 211" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND210 ,Set/Clear Pending Bit 210" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND209 ,Set/Clear Pending Bit 209" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND208 ,Set/Clear Pending Bit 208" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND207 ,Set/Clear Pending Bit 207" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND206 ,Set/Clear Pending Bit 206" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND205 ,Set/Clear Pending Bit 205" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND204 ,Set/Clear Pending Bit 204" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND203 ,Set/Clear Pending Bit 203" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND202 ,Set/Clear Pending Bit 202" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND201 ,Set/Clear Pending Bit 201" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND200 ,Set/Clear Pending Bit 200" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND199 ,Set/Clear Pending Bit 199" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND198 ,Set/Clear Pending Bit 198" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND197 ,Set/Clear Pending Bit 197" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND196 ,Set/Clear Pending Bit 196" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND195 ,Set/Clear Pending Bit 195" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND194 ,Set/Clear Pending Bit 194" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND193 ,Set/Clear Pending Bit 193" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND192 ,Set/Clear Pending Bit 192" "Not pending,Pending" else hgroup.long 0x0218++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x021C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND255 ,Set/Clear Pending Bit 255" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND254 ,Set/Clear Pending Bit 254" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND253 ,Set/Clear Pending Bit 253" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND252 ,Set/Clear Pending Bit 252" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND251 ,Set/Clear Pending Bit 251" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND250 ,Set/Clear Pending Bit 250" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND249 ,Set/Clear Pending Bit 249" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND248 ,Set/Clear Pending Bit 248" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND247 ,Set/Clear Pending Bit 247" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND246 ,Set/Clear Pending Bit 246" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND245 ,Set/Clear Pending Bit 245" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND244 ,Set/Clear Pending Bit 244" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND243 ,Set/Clear Pending Bit 243" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND242 ,Set/Clear Pending Bit 242" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND241 ,Set/Clear Pending Bit 241" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND240 ,Set/Clear Pending Bit 240" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND239 ,Set/Clear Pending Bit 239" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND238 ,Set/Clear Pending Bit 238" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND237 ,Set/Clear Pending Bit 237" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND236 ,Set/Clear Pending Bit 236" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND235 ,Set/Clear Pending Bit 235" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND234 ,Set/Clear Pending Bit 234" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND233 ,Set/Clear Pending Bit 233" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND232 ,Set/Clear Pending Bit 232" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND231 ,Set/Clear Pending Bit 231" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND230 ,Set/Clear Pending Bit 230" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND229 ,Set/Clear Pending Bit 229" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND228 ,Set/Clear Pending Bit 228" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND227 ,Set/Clear Pending Bit 227" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND226 ,Set/Clear Pending Bit 226" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND225 ,Set/Clear Pending Bit 225" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND224 ,Set/Clear Pending Bit 224" "Not pending,Pending" else hgroup.long 0x021C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x0220++0x03 line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND287 ,Set/Clear Pending Bit 287" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND286 ,Set/Clear Pending Bit 286" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND285 ,Set/Clear Pending Bit 285" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND284 ,Set/Clear Pending Bit 284" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND283 ,Set/Clear Pending Bit 283" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND282 ,Set/Clear Pending Bit 282" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND281 ,Set/Clear Pending Bit 281" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND280 ,Set/Clear Pending Bit 280" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND279 ,Set/Clear Pending Bit 279" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND278 ,Set/Clear Pending Bit 278" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND277 ,Set/Clear Pending Bit 277" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND276 ,Set/Clear Pending Bit 276" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND275 ,Set/Clear Pending Bit 275" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND274 ,Set/Clear Pending Bit 274" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND273 ,Set/Clear Pending Bit 273" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND272 ,Set/Clear Pending Bit 272" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND271 ,Set/Clear Pending Bit 271" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND270 ,Set/Clear Pending Bit 270" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND269 ,Set/Clear Pending Bit 269" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND268 ,Set/Clear Pending Bit 268" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND267 ,Set/Clear Pending Bit 267" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND266 ,Set/Clear Pending Bit 266" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND265 ,Set/Clear Pending Bit 265" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND264 ,Set/Clear Pending Bit 264" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND263 ,Set/Clear Pending Bit 263" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND262 ,Set/Clear Pending Bit 262" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND261 ,Set/Clear Pending Bit 261" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND260 ,Set/Clear Pending Bit 260" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND259 ,Set/Clear Pending Bit 259" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND258 ,Set/Clear Pending Bit 258" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND257 ,Set/Clear Pending Bit 257" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND256 ,Set/Clear Pending Bit 256" "Not pending,Pending" else hgroup.long 0x0220++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x0224++0x03 line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND319 ,Set/Clear Pending Bit 319" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND318 ,Set/Clear Pending Bit 318" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND317 ,Set/Clear Pending Bit 317" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND316 ,Set/Clear Pending Bit 316" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND315 ,Set/Clear Pending Bit 315" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND314 ,Set/Clear Pending Bit 314" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND313 ,Set/Clear Pending Bit 313" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND312 ,Set/Clear Pending Bit 312" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND311 ,Set/Clear Pending Bit 311" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND310 ,Set/Clear Pending Bit 310" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND309 ,Set/Clear Pending Bit 309" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND308 ,Set/Clear Pending Bit 308" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND307 ,Set/Clear Pending Bit 307" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND306 ,Set/Clear Pending Bit 306" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND305 ,Set/Clear Pending Bit 305" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND304 ,Set/Clear Pending Bit 304" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND303 ,Set/Clear Pending Bit 303" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND302 ,Set/Clear Pending Bit 302" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND301 ,Set/Clear Pending Bit 301" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND300 ,Set/Clear Pending Bit 300" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND299 ,Set/Clear Pending Bit 299" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND298 ,Set/Clear Pending Bit 298" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND297 ,Set/Clear Pending Bit 297" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND296 ,Set/Clear Pending Bit 296" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND295 ,Set/Clear Pending Bit 295" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND294 ,Set/Clear Pending Bit 294" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND293 ,Set/Clear Pending Bit 293" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND292 ,Set/Clear Pending Bit 292" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND291 ,Set/Clear Pending Bit 291" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND290 ,Set/Clear Pending Bit 290" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND289 ,Set/Clear Pending Bit 289" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND288 ,Set/Clear Pending Bit 288" "Not pending,Pending" else hgroup.long 0x0224++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x0228++0x03 line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND351 ,Set/Clear Pending Bit 351" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND350 ,Set/Clear Pending Bit 350" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND349 ,Set/Clear Pending Bit 349" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND348 ,Set/Clear Pending Bit 348" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND347 ,Set/Clear Pending Bit 347" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND346 ,Set/Clear Pending Bit 346" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND345 ,Set/Clear Pending Bit 345" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND344 ,Set/Clear Pending Bit 344" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND343 ,Set/Clear Pending Bit 343" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND342 ,Set/Clear Pending Bit 342" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND341 ,Set/Clear Pending Bit 341" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND340 ,Set/Clear Pending Bit 340" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND339 ,Set/Clear Pending Bit 339" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND338 ,Set/Clear Pending Bit 338" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND337 ,Set/Clear Pending Bit 337" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND336 ,Set/Clear Pending Bit 336" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND335 ,Set/Clear Pending Bit 335" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND334 ,Set/Clear Pending Bit 334" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND333 ,Set/Clear Pending Bit 333" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND332 ,Set/Clear Pending Bit 332" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND331 ,Set/Clear Pending Bit 331" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND330 ,Set/Clear Pending Bit 330" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND329 ,Set/Clear Pending Bit 329" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND328 ,Set/Clear Pending Bit 328" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND327 ,Set/Clear Pending Bit 327" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND326 ,Set/Clear Pending Bit 326" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND325 ,Set/Clear Pending Bit 325" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND324 ,Set/Clear Pending Bit 324" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND323 ,Set/Clear Pending Bit 323" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND322 ,Set/Clear Pending Bit 322" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND321 ,Set/Clear Pending Bit 321" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND320 ,Set/Clear Pending Bit 320" "Not pending,Pending" else hgroup.long 0x0228++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x022C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND383 ,Set/Clear Pending Bit 383" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND382 ,Set/Clear Pending Bit 382" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND381 ,Set/Clear Pending Bit 381" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND380 ,Set/Clear Pending Bit 380" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND379 ,Set/Clear Pending Bit 379" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND378 ,Set/Clear Pending Bit 378" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND377 ,Set/Clear Pending Bit 377" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND376 ,Set/Clear Pending Bit 376" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND375 ,Set/Clear Pending Bit 375" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND374 ,Set/Clear Pending Bit 374" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND373 ,Set/Clear Pending Bit 373" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND372 ,Set/Clear Pending Bit 372" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND371 ,Set/Clear Pending Bit 371" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND370 ,Set/Clear Pending Bit 370" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND369 ,Set/Clear Pending Bit 369" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND368 ,Set/Clear Pending Bit 368" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND367 ,Set/Clear Pending Bit 367" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND366 ,Set/Clear Pending Bit 366" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND365 ,Set/Clear Pending Bit 365" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND364 ,Set/Clear Pending Bit 364" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND363 ,Set/Clear Pending Bit 363" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND362 ,Set/Clear Pending Bit 362" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND361 ,Set/Clear Pending Bit 361" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND360 ,Set/Clear Pending Bit 360" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND359 ,Set/Clear Pending Bit 359" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND358 ,Set/Clear Pending Bit 358" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND357 ,Set/Clear Pending Bit 357" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND356 ,Set/Clear Pending Bit 356" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND355 ,Set/Clear Pending Bit 355" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND354 ,Set/Clear Pending Bit 354" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND353 ,Set/Clear Pending Bit 353" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND352 ,Set/Clear Pending Bit 352" "Not pending,Pending" else hgroup.long 0x022C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x0230++0x03 line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND415 ,Set/Clear Pending Bit 415" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND414 ,Set/Clear Pending Bit 414" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND413 ,Set/Clear Pending Bit 413" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND412 ,Set/Clear Pending Bit 412" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND411 ,Set/Clear Pending Bit 411" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND410 ,Set/Clear Pending Bit 410" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND409 ,Set/Clear Pending Bit 409" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND408 ,Set/Clear Pending Bit 408" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND407 ,Set/Clear Pending Bit 407" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND406 ,Set/Clear Pending Bit 406" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND405 ,Set/Clear Pending Bit 405" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND404 ,Set/Clear Pending Bit 404" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND403 ,Set/Clear Pending Bit 403" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND402 ,Set/Clear Pending Bit 402" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND401 ,Set/Clear Pending Bit 401" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND400 ,Set/Clear Pending Bit 400" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND399 ,Set/Clear Pending Bit 399" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND398 ,Set/Clear Pending Bit 398" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND397 ,Set/Clear Pending Bit 397" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND396 ,Set/Clear Pending Bit 396" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND395 ,Set/Clear Pending Bit 395" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND394 ,Set/Clear Pending Bit 394" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND393 ,Set/Clear Pending Bit 393" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND392 ,Set/Clear Pending Bit 392" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND391 ,Set/Clear Pending Bit 391" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND390 ,Set/Clear Pending Bit 390" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND389 ,Set/Clear Pending Bit 389" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND388 ,Set/Clear Pending Bit 388" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND387 ,Set/Clear Pending Bit 387" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND386 ,Set/Clear Pending Bit 386" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND385 ,Set/Clear Pending Bit 385" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND384 ,Set/Clear Pending Bit 384" "Not pending,Pending" else hgroup.long 0x0230++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x0234++0x03 line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND447 ,Set/Clear Pending Bit 447" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND446 ,Set/Clear Pending Bit 446" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND445 ,Set/Clear Pending Bit 445" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND444 ,Set/Clear Pending Bit 444" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND443 ,Set/Clear Pending Bit 443" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND442 ,Set/Clear Pending Bit 442" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND441 ,Set/Clear Pending Bit 441" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND440 ,Set/Clear Pending Bit 440" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND439 ,Set/Clear Pending Bit 439" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND438 ,Set/Clear Pending Bit 438" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND437 ,Set/Clear Pending Bit 437" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND436 ,Set/Clear Pending Bit 436" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND435 ,Set/Clear Pending Bit 435" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND434 ,Set/Clear Pending Bit 434" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND433 ,Set/Clear Pending Bit 433" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND432 ,Set/Clear Pending Bit 432" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND431 ,Set/Clear Pending Bit 431" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND430 ,Set/Clear Pending Bit 430" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND429 ,Set/Clear Pending Bit 429" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND428 ,Set/Clear Pending Bit 428" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND427 ,Set/Clear Pending Bit 427" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND426 ,Set/Clear Pending Bit 426" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND425 ,Set/Clear Pending Bit 425" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND424 ,Set/Clear Pending Bit 424" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND423 ,Set/Clear Pending Bit 423" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND422 ,Set/Clear Pending Bit 422" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND421 ,Set/Clear Pending Bit 421" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND420 ,Set/Clear Pending Bit 420" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND419 ,Set/Clear Pending Bit 419" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND418 ,Set/Clear Pending Bit 418" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND417 ,Set/Clear Pending Bit 417" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND416 ,Set/Clear Pending Bit 416" "Not pending,Pending" else hgroup.long 0x0234++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x0238++0x03 line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND479 ,Set/Clear Pending Bit 479" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND478 ,Set/Clear Pending Bit 478" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND477 ,Set/Clear Pending Bit 477" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND476 ,Set/Clear Pending Bit 476" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND475 ,Set/Clear Pending Bit 475" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND474 ,Set/Clear Pending Bit 474" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND473 ,Set/Clear Pending Bit 473" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND472 ,Set/Clear Pending Bit 472" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND471 ,Set/Clear Pending Bit 471" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND470 ,Set/Clear Pending Bit 470" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND469 ,Set/Clear Pending Bit 469" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND468 ,Set/Clear Pending Bit 468" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND467 ,Set/Clear Pending Bit 467" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND466 ,Set/Clear Pending Bit 466" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND465 ,Set/Clear Pending Bit 465" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND464 ,Set/Clear Pending Bit 464" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND463 ,Set/Clear Pending Bit 463" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND462 ,Set/Clear Pending Bit 462" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND461 ,Set/Clear Pending Bit 461" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND460 ,Set/Clear Pending Bit 460" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND459 ,Set/Clear Pending Bit 459" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND458 ,Set/Clear Pending Bit 458" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND457 ,Set/Clear Pending Bit 457" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND456 ,Set/Clear Pending Bit 456" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND455 ,Set/Clear Pending Bit 455" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND454 ,Set/Clear Pending Bit 454" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND453 ,Set/Clear Pending Bit 453" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND452 ,Set/Clear Pending Bit 452" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND451 ,Set/Clear Pending Bit 451" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND450 ,Set/Clear Pending Bit 450" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND449 ,Set/Clear Pending Bit 449" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND448 ,Set/Clear Pending Bit 448" "Not pending,Pending" else hgroup.long 0x0238++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x023C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND511 ,Set/Clear Pending Bit 511" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND510 ,Set/Clear Pending Bit 510" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND509 ,Set/Clear Pending Bit 509" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND508 ,Set/Clear Pending Bit 508" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND507 ,Set/Clear Pending Bit 507" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND506 ,Set/Clear Pending Bit 506" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND505 ,Set/Clear Pending Bit 505" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND504 ,Set/Clear Pending Bit 504" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND503 ,Set/Clear Pending Bit 503" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND502 ,Set/Clear Pending Bit 502" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND501 ,Set/Clear Pending Bit 501" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND500 ,Set/Clear Pending Bit 500" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND499 ,Set/Clear Pending Bit 499" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND498 ,Set/Clear Pending Bit 498" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND497 ,Set/Clear Pending Bit 497" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND496 ,Set/Clear Pending Bit 496" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND495 ,Set/Clear Pending Bit 495" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND494 ,Set/Clear Pending Bit 494" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND493 ,Set/Clear Pending Bit 493" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND492 ,Set/Clear Pending Bit 492" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND491 ,Set/Clear Pending Bit 491" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND490 ,Set/Clear Pending Bit 490" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND489 ,Set/Clear Pending Bit 489" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND488 ,Set/Clear Pending Bit 488" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND487 ,Set/Clear Pending Bit 487" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND486 ,Set/Clear Pending Bit 486" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND485 ,Set/Clear Pending Bit 485" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND484 ,Set/Clear Pending Bit 484" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND483 ,Set/Clear Pending Bit 483" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND482 ,Set/Clear Pending Bit 482" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND481 ,Set/Clear Pending Bit 481" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND480 ,Set/Clear Pending Bit 480" "Not pending,Pending" else hgroup.long 0x023C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x0240++0x03 line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND543 ,Set/Clear Pending Bit 543" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND542 ,Set/Clear Pending Bit 542" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND541 ,Set/Clear Pending Bit 541" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND540 ,Set/Clear Pending Bit 540" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND539 ,Set/Clear Pending Bit 539" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND538 ,Set/Clear Pending Bit 538" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND537 ,Set/Clear Pending Bit 537" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND536 ,Set/Clear Pending Bit 536" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND535 ,Set/Clear Pending Bit 535" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND534 ,Set/Clear Pending Bit 534" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND533 ,Set/Clear Pending Bit 533" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND532 ,Set/Clear Pending Bit 532" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND531 ,Set/Clear Pending Bit 531" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND530 ,Set/Clear Pending Bit 530" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND529 ,Set/Clear Pending Bit 529" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND528 ,Set/Clear Pending Bit 528" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND527 ,Set/Clear Pending Bit 527" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND526 ,Set/Clear Pending Bit 526" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND525 ,Set/Clear Pending Bit 525" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND524 ,Set/Clear Pending Bit 524" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND523 ,Set/Clear Pending Bit 523" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND522 ,Set/Clear Pending Bit 522" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND521 ,Set/Clear Pending Bit 521" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND520 ,Set/Clear Pending Bit 520" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND519 ,Set/Clear Pending Bit 519" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND518 ,Set/Clear Pending Bit 518" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND517 ,Set/Clear Pending Bit 517" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND516 ,Set/Clear Pending Bit 516" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND515 ,Set/Clear Pending Bit 515" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND514 ,Set/Clear Pending Bit 514" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND513 ,Set/Clear Pending Bit 513" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND512 ,Set/Clear Pending Bit 512" "Not pending,Pending" else hgroup.long 0x0240++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x0244++0x03 line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND575 ,Set/Clear Pending Bit 575" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND574 ,Set/Clear Pending Bit 574" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND573 ,Set/Clear Pending Bit 573" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND572 ,Set/Clear Pending Bit 572" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND571 ,Set/Clear Pending Bit 571" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND570 ,Set/Clear Pending Bit 570" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND569 ,Set/Clear Pending Bit 569" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND568 ,Set/Clear Pending Bit 568" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND567 ,Set/Clear Pending Bit 567" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND566 ,Set/Clear Pending Bit 566" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND565 ,Set/Clear Pending Bit 565" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND564 ,Set/Clear Pending Bit 564" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND563 ,Set/Clear Pending Bit 563" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND562 ,Set/Clear Pending Bit 562" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND561 ,Set/Clear Pending Bit 561" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND560 ,Set/Clear Pending Bit 560" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND559 ,Set/Clear Pending Bit 559" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND558 ,Set/Clear Pending Bit 558" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND557 ,Set/Clear Pending Bit 557" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND556 ,Set/Clear Pending Bit 556" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND555 ,Set/Clear Pending Bit 555" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND554 ,Set/Clear Pending Bit 554" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND553 ,Set/Clear Pending Bit 553" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND552 ,Set/Clear Pending Bit 552" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND551 ,Set/Clear Pending Bit 551" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND550 ,Set/Clear Pending Bit 550" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND549 ,Set/Clear Pending Bit 549" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND548 ,Set/Clear Pending Bit 548" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND547 ,Set/Clear Pending Bit 547" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND546 ,Set/Clear Pending Bit 546" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND545 ,Set/Clear Pending Bit 545" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND544 ,Set/Clear Pending Bit 544" "Not pending,Pending" else hgroup.long 0x0244++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x0248++0x03 line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND607 ,Set/Clear Pending Bit 607" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND606 ,Set/Clear Pending Bit 606" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND605 ,Set/Clear Pending Bit 605" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND604 ,Set/Clear Pending Bit 604" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND603 ,Set/Clear Pending Bit 603" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND602 ,Set/Clear Pending Bit 602" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND601 ,Set/Clear Pending Bit 601" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND600 ,Set/Clear Pending Bit 600" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND599 ,Set/Clear Pending Bit 599" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND598 ,Set/Clear Pending Bit 598" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND597 ,Set/Clear Pending Bit 597" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND596 ,Set/Clear Pending Bit 596" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND595 ,Set/Clear Pending Bit 595" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND594 ,Set/Clear Pending Bit 594" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND593 ,Set/Clear Pending Bit 593" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND592 ,Set/Clear Pending Bit 592" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND591 ,Set/Clear Pending Bit 591" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND590 ,Set/Clear Pending Bit 590" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND589 ,Set/Clear Pending Bit 589" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND588 ,Set/Clear Pending Bit 588" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND587 ,Set/Clear Pending Bit 587" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND586 ,Set/Clear Pending Bit 586" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND585 ,Set/Clear Pending Bit 585" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND584 ,Set/Clear Pending Bit 584" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND583 ,Set/Clear Pending Bit 583" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND582 ,Set/Clear Pending Bit 582" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND581 ,Set/Clear Pending Bit 581" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND580 ,Set/Clear Pending Bit 580" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND579 ,Set/Clear Pending Bit 579" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND578 ,Set/Clear Pending Bit 578" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND577 ,Set/Clear Pending Bit 577" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND576 ,Set/Clear Pending Bit 576" "Not pending,Pending" else hgroup.long 0x0248++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x024C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND639 ,Set/Clear Pending Bit 639" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND638 ,Set/Clear Pending Bit 638" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND637 ,Set/Clear Pending Bit 637" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND636 ,Set/Clear Pending Bit 636" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND635 ,Set/Clear Pending Bit 635" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND634 ,Set/Clear Pending Bit 634" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND633 ,Set/Clear Pending Bit 633" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND632 ,Set/Clear Pending Bit 632" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND631 ,Set/Clear Pending Bit 631" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND630 ,Set/Clear Pending Bit 630" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND629 ,Set/Clear Pending Bit 629" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND628 ,Set/Clear Pending Bit 628" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND627 ,Set/Clear Pending Bit 627" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND626 ,Set/Clear Pending Bit 626" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND625 ,Set/Clear Pending Bit 625" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND624 ,Set/Clear Pending Bit 624" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND623 ,Set/Clear Pending Bit 623" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND622 ,Set/Clear Pending Bit 622" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND621 ,Set/Clear Pending Bit 621" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND620 ,Set/Clear Pending Bit 620" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND619 ,Set/Clear Pending Bit 619" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND618 ,Set/Clear Pending Bit 618" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND617 ,Set/Clear Pending Bit 617" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND616 ,Set/Clear Pending Bit 616" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND615 ,Set/Clear Pending Bit 615" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND614 ,Set/Clear Pending Bit 614" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND613 ,Set/Clear Pending Bit 613" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND612 ,Set/Clear Pending Bit 612" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND611 ,Set/Clear Pending Bit 611" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND610 ,Set/Clear Pending Bit 610" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND609 ,Set/Clear Pending Bit 609" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND608 ,Set/Clear Pending Bit 608" "Not pending,Pending" else hgroup.long 0x024C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x0250++0x03 line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND671 ,Set/Clear Pending Bit 671" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND670 ,Set/Clear Pending Bit 670" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND669 ,Set/Clear Pending Bit 669" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND668 ,Set/Clear Pending Bit 668" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND667 ,Set/Clear Pending Bit 667" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND666 ,Set/Clear Pending Bit 666" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND665 ,Set/Clear Pending Bit 665" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND664 ,Set/Clear Pending Bit 664" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND663 ,Set/Clear Pending Bit 663" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND662 ,Set/Clear Pending Bit 662" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND661 ,Set/Clear Pending Bit 661" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND660 ,Set/Clear Pending Bit 660" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND659 ,Set/Clear Pending Bit 659" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND658 ,Set/Clear Pending Bit 658" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND657 ,Set/Clear Pending Bit 657" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND656 ,Set/Clear Pending Bit 656" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND655 ,Set/Clear Pending Bit 655" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND654 ,Set/Clear Pending Bit 654" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND653 ,Set/Clear Pending Bit 653" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND652 ,Set/Clear Pending Bit 652" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND651 ,Set/Clear Pending Bit 651" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND650 ,Set/Clear Pending Bit 650" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND649 ,Set/Clear Pending Bit 649" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND648 ,Set/Clear Pending Bit 648" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND647 ,Set/Clear Pending Bit 647" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND646 ,Set/Clear Pending Bit 646" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND645 ,Set/Clear Pending Bit 645" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND644 ,Set/Clear Pending Bit 644" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND643 ,Set/Clear Pending Bit 643" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND642 ,Set/Clear Pending Bit 642" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND641 ,Set/Clear Pending Bit 641" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND640 ,Set/Clear Pending Bit 640" "Not pending,Pending" else hgroup.long 0x0250++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x0254++0x03 line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND703 ,Set/Clear Pending Bit 703" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND702 ,Set/Clear Pending Bit 702" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND701 ,Set/Clear Pending Bit 701" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND700 ,Set/Clear Pending Bit 700" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND699 ,Set/Clear Pending Bit 699" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND698 ,Set/Clear Pending Bit 698" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND697 ,Set/Clear Pending Bit 697" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND696 ,Set/Clear Pending Bit 696" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND695 ,Set/Clear Pending Bit 695" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND694 ,Set/Clear Pending Bit 694" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND693 ,Set/Clear Pending Bit 693" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND692 ,Set/Clear Pending Bit 692" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND691 ,Set/Clear Pending Bit 691" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND690 ,Set/Clear Pending Bit 690" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND689 ,Set/Clear Pending Bit 689" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND688 ,Set/Clear Pending Bit 688" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND687 ,Set/Clear Pending Bit 687" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND686 ,Set/Clear Pending Bit 686" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND685 ,Set/Clear Pending Bit 685" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND684 ,Set/Clear Pending Bit 684" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND683 ,Set/Clear Pending Bit 683" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND682 ,Set/Clear Pending Bit 682" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND681 ,Set/Clear Pending Bit 681" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND680 ,Set/Clear Pending Bit 680" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND679 ,Set/Clear Pending Bit 679" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND678 ,Set/Clear Pending Bit 678" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND677 ,Set/Clear Pending Bit 677" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND676 ,Set/Clear Pending Bit 676" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND675 ,Set/Clear Pending Bit 675" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND674 ,Set/Clear Pending Bit 674" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND673 ,Set/Clear Pending Bit 673" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND672 ,Set/Clear Pending Bit 672" "Not pending,Pending" else hgroup.long 0x0254++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x0258++0x03 line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND735 ,Set/Clear Pending Bit 735" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND734 ,Set/Clear Pending Bit 734" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND733 ,Set/Clear Pending Bit 733" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND732 ,Set/Clear Pending Bit 732" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND731 ,Set/Clear Pending Bit 731" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND730 ,Set/Clear Pending Bit 730" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND729 ,Set/Clear Pending Bit 729" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND728 ,Set/Clear Pending Bit 728" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND727 ,Set/Clear Pending Bit 727" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND726 ,Set/Clear Pending Bit 726" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND725 ,Set/Clear Pending Bit 725" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND724 ,Set/Clear Pending Bit 724" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND723 ,Set/Clear Pending Bit 723" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND722 ,Set/Clear Pending Bit 722" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND721 ,Set/Clear Pending Bit 721" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND720 ,Set/Clear Pending Bit 720" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND719 ,Set/Clear Pending Bit 719" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND718 ,Set/Clear Pending Bit 718" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND717 ,Set/Clear Pending Bit 717" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND716 ,Set/Clear Pending Bit 716" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND715 ,Set/Clear Pending Bit 715" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND714 ,Set/Clear Pending Bit 714" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND713 ,Set/Clear Pending Bit 713" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND712 ,Set/Clear Pending Bit 712" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND711 ,Set/Clear Pending Bit 711" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND710 ,Set/Clear Pending Bit 710" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND709 ,Set/Clear Pending Bit 709" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND708 ,Set/Clear Pending Bit 708" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND707 ,Set/Clear Pending Bit 707" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND706 ,Set/Clear Pending Bit 706" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND705 ,Set/Clear Pending Bit 705" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND704 ,Set/Clear Pending Bit 704" "Not pending,Pending" else hgroup.long 0x0258++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x025C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND767 ,Set/Clear Pending Bit 767" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND766 ,Set/Clear Pending Bit 766" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND765 ,Set/Clear Pending Bit 765" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND764 ,Set/Clear Pending Bit 764" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND763 ,Set/Clear Pending Bit 763" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND762 ,Set/Clear Pending Bit 762" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND761 ,Set/Clear Pending Bit 761" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND760 ,Set/Clear Pending Bit 760" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND759 ,Set/Clear Pending Bit 759" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND758 ,Set/Clear Pending Bit 758" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND757 ,Set/Clear Pending Bit 757" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND756 ,Set/Clear Pending Bit 756" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND755 ,Set/Clear Pending Bit 755" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND754 ,Set/Clear Pending Bit 754" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND753 ,Set/Clear Pending Bit 753" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND752 ,Set/Clear Pending Bit 752" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND751 ,Set/Clear Pending Bit 751" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND750 ,Set/Clear Pending Bit 750" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND749 ,Set/Clear Pending Bit 749" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND748 ,Set/Clear Pending Bit 748" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND747 ,Set/Clear Pending Bit 747" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND746 ,Set/Clear Pending Bit 746" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND745 ,Set/Clear Pending Bit 745" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND744 ,Set/Clear Pending Bit 744" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND743 ,Set/Clear Pending Bit 743" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND742 ,Set/Clear Pending Bit 742" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND741 ,Set/Clear Pending Bit 741" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND740 ,Set/Clear Pending Bit 740" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND739 ,Set/Clear Pending Bit 739" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND738 ,Set/Clear Pending Bit 738" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND737 ,Set/Clear Pending Bit 737" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND736 ,Set/Clear Pending Bit 736" "Not pending,Pending" else hgroup.long 0x025C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x0260++0x03 line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND799 ,Set/Clear Pending Bit 799" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND798 ,Set/Clear Pending Bit 798" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND797 ,Set/Clear Pending Bit 797" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND796 ,Set/Clear Pending Bit 796" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND795 ,Set/Clear Pending Bit 795" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND794 ,Set/Clear Pending Bit 794" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND793 ,Set/Clear Pending Bit 793" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND792 ,Set/Clear Pending Bit 792" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND791 ,Set/Clear Pending Bit 791" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND790 ,Set/Clear Pending Bit 790" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND789 ,Set/Clear Pending Bit 789" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND788 ,Set/Clear Pending Bit 788" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND787 ,Set/Clear Pending Bit 787" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND786 ,Set/Clear Pending Bit 786" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND785 ,Set/Clear Pending Bit 785" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND784 ,Set/Clear Pending Bit 784" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND783 ,Set/Clear Pending Bit 783" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND782 ,Set/Clear Pending Bit 782" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND781 ,Set/Clear Pending Bit 781" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND780 ,Set/Clear Pending Bit 780" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND779 ,Set/Clear Pending Bit 779" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND778 ,Set/Clear Pending Bit 778" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND777 ,Set/Clear Pending Bit 777" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND776 ,Set/Clear Pending Bit 776" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND775 ,Set/Clear Pending Bit 775" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND774 ,Set/Clear Pending Bit 774" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND773 ,Set/Clear Pending Bit 773" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND772 ,Set/Clear Pending Bit 772" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND771 ,Set/Clear Pending Bit 771" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND770 ,Set/Clear Pending Bit 770" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND769 ,Set/Clear Pending Bit 769" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND768 ,Set/Clear Pending Bit 768" "Not pending,Pending" else hgroup.long 0x0260++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x0264++0x03 line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND831 ,Set/Clear Pending Bit 831" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND830 ,Set/Clear Pending Bit 830" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND829 ,Set/Clear Pending Bit 829" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND828 ,Set/Clear Pending Bit 828" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND827 ,Set/Clear Pending Bit 827" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND826 ,Set/Clear Pending Bit 826" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND825 ,Set/Clear Pending Bit 825" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND824 ,Set/Clear Pending Bit 824" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND823 ,Set/Clear Pending Bit 823" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND822 ,Set/Clear Pending Bit 822" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND821 ,Set/Clear Pending Bit 821" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND820 ,Set/Clear Pending Bit 820" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND819 ,Set/Clear Pending Bit 819" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND818 ,Set/Clear Pending Bit 818" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND817 ,Set/Clear Pending Bit 817" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND816 ,Set/Clear Pending Bit 816" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND815 ,Set/Clear Pending Bit 815" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND814 ,Set/Clear Pending Bit 814" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND813 ,Set/Clear Pending Bit 813" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND812 ,Set/Clear Pending Bit 812" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND811 ,Set/Clear Pending Bit 811" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND810 ,Set/Clear Pending Bit 810" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND809 ,Set/Clear Pending Bit 809" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND808 ,Set/Clear Pending Bit 808" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND807 ,Set/Clear Pending Bit 807" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND806 ,Set/Clear Pending Bit 806" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND805 ,Set/Clear Pending Bit 805" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND804 ,Set/Clear Pending Bit 804" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND803 ,Set/Clear Pending Bit 803" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND802 ,Set/Clear Pending Bit 802" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND801 ,Set/Clear Pending Bit 801" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND800 ,Set/Clear Pending Bit 800" "Not pending,Pending" else hgroup.long 0x0264++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x0268++0x03 line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND863 ,Set/Clear Pending Bit 863" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND862 ,Set/Clear Pending Bit 862" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND861 ,Set/Clear Pending Bit 861" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND860 ,Set/Clear Pending Bit 860" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND859 ,Set/Clear Pending Bit 859" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND858 ,Set/Clear Pending Bit 858" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND857 ,Set/Clear Pending Bit 857" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND856 ,Set/Clear Pending Bit 856" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND855 ,Set/Clear Pending Bit 855" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND854 ,Set/Clear Pending Bit 854" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND853 ,Set/Clear Pending Bit 853" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND852 ,Set/Clear Pending Bit 852" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND851 ,Set/Clear Pending Bit 851" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND850 ,Set/Clear Pending Bit 850" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND849 ,Set/Clear Pending Bit 849" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND848 ,Set/Clear Pending Bit 848" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND847 ,Set/Clear Pending Bit 847" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND846 ,Set/Clear Pending Bit 846" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND845 ,Set/Clear Pending Bit 845" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND844 ,Set/Clear Pending Bit 844" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND843 ,Set/Clear Pending Bit 843" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND842 ,Set/Clear Pending Bit 842" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND841 ,Set/Clear Pending Bit 841" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND840 ,Set/Clear Pending Bit 840" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND839 ,Set/Clear Pending Bit 839" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND838 ,Set/Clear Pending Bit 838" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND837 ,Set/Clear Pending Bit 837" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND836 ,Set/Clear Pending Bit 836" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND835 ,Set/Clear Pending Bit 835" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND834 ,Set/Clear Pending Bit 834" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND833 ,Set/Clear Pending Bit 833" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND832 ,Set/Clear Pending Bit 832" "Not pending,Pending" else hgroup.long 0x0268++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x026C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND895 ,Set/Clear Pending Bit 895" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND894 ,Set/Clear Pending Bit 894" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND893 ,Set/Clear Pending Bit 893" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND892 ,Set/Clear Pending Bit 892" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND891 ,Set/Clear Pending Bit 891" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND890 ,Set/Clear Pending Bit 890" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND889 ,Set/Clear Pending Bit 889" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND888 ,Set/Clear Pending Bit 888" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND887 ,Set/Clear Pending Bit 887" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND886 ,Set/Clear Pending Bit 886" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND885 ,Set/Clear Pending Bit 885" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND884 ,Set/Clear Pending Bit 884" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND883 ,Set/Clear Pending Bit 883" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND882 ,Set/Clear Pending Bit 882" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND881 ,Set/Clear Pending Bit 881" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND880 ,Set/Clear Pending Bit 880" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND879 ,Set/Clear Pending Bit 879" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND878 ,Set/Clear Pending Bit 878" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND877 ,Set/Clear Pending Bit 877" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND876 ,Set/Clear Pending Bit 876" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND875 ,Set/Clear Pending Bit 875" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND874 ,Set/Clear Pending Bit 874" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND873 ,Set/Clear Pending Bit 873" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND872 ,Set/Clear Pending Bit 872" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND871 ,Set/Clear Pending Bit 871" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND870 ,Set/Clear Pending Bit 870" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND869 ,Set/Clear Pending Bit 869" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND868 ,Set/Clear Pending Bit 868" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND867 ,Set/Clear Pending Bit 867" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND866 ,Set/Clear Pending Bit 866" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND865 ,Set/Clear Pending Bit 865" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND864 ,Set/Clear Pending Bit 864" "Not pending,Pending" else hgroup.long 0x026C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x0270++0x03 line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND927 ,Set/Clear Pending Bit 927" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND926 ,Set/Clear Pending Bit 926" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND925 ,Set/Clear Pending Bit 925" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND924 ,Set/Clear Pending Bit 924" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND923 ,Set/Clear Pending Bit 923" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND922 ,Set/Clear Pending Bit 922" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND921 ,Set/Clear Pending Bit 921" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND920 ,Set/Clear Pending Bit 920" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND919 ,Set/Clear Pending Bit 919" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND918 ,Set/Clear Pending Bit 918" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND917 ,Set/Clear Pending Bit 917" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND916 ,Set/Clear Pending Bit 916" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND915 ,Set/Clear Pending Bit 915" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND914 ,Set/Clear Pending Bit 914" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND913 ,Set/Clear Pending Bit 913" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND912 ,Set/Clear Pending Bit 912" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND911 ,Set/Clear Pending Bit 911" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND910 ,Set/Clear Pending Bit 910" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND909 ,Set/Clear Pending Bit 909" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND908 ,Set/Clear Pending Bit 908" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND907 ,Set/Clear Pending Bit 907" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND906 ,Set/Clear Pending Bit 906" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND905 ,Set/Clear Pending Bit 905" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND904 ,Set/Clear Pending Bit 904" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND903 ,Set/Clear Pending Bit 903" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND902 ,Set/Clear Pending Bit 902" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND901 ,Set/Clear Pending Bit 901" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND900 ,Set/Clear Pending Bit 900" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND899 ,Set/Clear Pending Bit 899" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND898 ,Set/Clear Pending Bit 898" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND897 ,Set/Clear Pending Bit 897" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND896 ,Set/Clear Pending Bit 896" "Not pending,Pending" else hgroup.long 0x0270++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x0274++0x03 line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND959 ,Set/Clear Pending Bit 959" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND958 ,Set/Clear Pending Bit 958" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND957 ,Set/Clear Pending Bit 957" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND956 ,Set/Clear Pending Bit 956" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND955 ,Set/Clear Pending Bit 955" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND954 ,Set/Clear Pending Bit 954" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND953 ,Set/Clear Pending Bit 953" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND952 ,Set/Clear Pending Bit 952" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND951 ,Set/Clear Pending Bit 951" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND950 ,Set/Clear Pending Bit 950" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND949 ,Set/Clear Pending Bit 949" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND948 ,Set/Clear Pending Bit 948" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND947 ,Set/Clear Pending Bit 947" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND946 ,Set/Clear Pending Bit 946" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND945 ,Set/Clear Pending Bit 945" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND944 ,Set/Clear Pending Bit 944" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND943 ,Set/Clear Pending Bit 943" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND942 ,Set/Clear Pending Bit 942" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND941 ,Set/Clear Pending Bit 941" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND940 ,Set/Clear Pending Bit 940" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND939 ,Set/Clear Pending Bit 939" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND938 ,Set/Clear Pending Bit 938" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND937 ,Set/Clear Pending Bit 937" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND936 ,Set/Clear Pending Bit 936" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND935 ,Set/Clear Pending Bit 935" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND934 ,Set/Clear Pending Bit 934" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND933 ,Set/Clear Pending Bit 933" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND932 ,Set/Clear Pending Bit 932" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND931 ,Set/Clear Pending Bit 931" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND930 ,Set/Clear Pending Bit 930" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND929 ,Set/Clear Pending Bit 929" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND928 ,Set/Clear Pending Bit 928" "Not pending,Pending" else hgroup.long 0x0274++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x0278++0x03 line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND991 ,Set/Clear Pending Bit 991" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND990 ,Set/Clear Pending Bit 990" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND989 ,Set/Clear Pending Bit 989" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND988 ,Set/Clear Pending Bit 988" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND987 ,Set/Clear Pending Bit 987" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND986 ,Set/Clear Pending Bit 986" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND985 ,Set/Clear Pending Bit 985" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND984 ,Set/Clear Pending Bit 984" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND983 ,Set/Clear Pending Bit 983" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND982 ,Set/Clear Pending Bit 982" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND981 ,Set/Clear Pending Bit 981" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND980 ,Set/Clear Pending Bit 980" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND979 ,Set/Clear Pending Bit 979" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND978 ,Set/Clear Pending Bit 978" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND977 ,Set/Clear Pending Bit 977" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND976 ,Set/Clear Pending Bit 976" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND975 ,Set/Clear Pending Bit 975" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND974 ,Set/Clear Pending Bit 974" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND973 ,Set/Clear Pending Bit 973" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND972 ,Set/Clear Pending Bit 972" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND971 ,Set/Clear Pending Bit 971" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND970 ,Set/Clear Pending Bit 970" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND969 ,Set/Clear Pending Bit 969" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND968 ,Set/Clear Pending Bit 968" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND967 ,Set/Clear Pending Bit 967" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND966 ,Set/Clear Pending Bit 966" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND965 ,Set/Clear Pending Bit 965" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND964 ,Set/Clear Pending Bit 964" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND963 ,Set/Clear Pending Bit 963" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND962 ,Set/Clear Pending Bit 962" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND961 ,Set/Clear Pending Bit 961" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND960 ,Set/Clear Pending Bit 960" "Not pending,Pending" else hgroup.long 0x0278++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" endif tree.end width 24. tree "Set/Clear Active Registers" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x0300++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0" newline newline newline newline newline newline newline newline newline newline else group.long 0x0300++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE31 ,Set/Clear Active Bit 31" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE30 ,Set/Clear Active Bit 30" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE29 ,Set/Clear Active Bit 29" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE28 ,Set/Clear Active Bit 28" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE27 ,Set/Clear Active Bit 27" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE26 ,Set/Clear Active Bit 26" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE25 ,Set/Clear Active Bit 25" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE24 ,Set/Clear Active Bit 24" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE23 ,Set/Clear Active Bit 23" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE22 ,Set/Clear Active Bit 22" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE21 ,Set/Clear Active Bit 21" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE20 ,Set/Clear Active Bit 20" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE19 ,Set/Clear Active Bit 19" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE18 ,Set/Clear Active Bit 18" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE17 ,Set/Clear Active Bit 17" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE16 ,Set/Clear Active Bit 16" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE15 ,Set/Clear Active Bit 15" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE14 ,Set/Clear Active Bit 14" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE13 ,Set/Clear Active Bit 13" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE12 ,Set/Clear Active Bit 12" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE11 ,Set/Clear Active Bit 11" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE10 ,Set/Clear Active Bit 10" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE9 ,Set/Clear Active Bit 9" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE8 ,Set/Clear Active Bit 8" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE7 ,Set/Clear Active Bit 7" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE6 ,Set/Clear Active Bit 6" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE5 ,Set/Clear Active Bit 5" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE4 ,Set/Clear Active Bit 4" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE3 ,Set/Clear Active Bit 3" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE2 ,Set/Clear Active Bit 2" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE1 ,Set/Clear Active Bit 1" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE0 ,Set/Clear Active Bit 0" "Not active,Active" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x0304++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE63 ,Set/Clear Active Bit 63" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE62 ,Set/Clear Active Bit 62" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE61 ,Set/Clear Active Bit 61" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE60 ,Set/Clear Active Bit 60" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE59 ,Set/Clear Active Bit 59" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE58 ,Set/Clear Active Bit 58" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE57 ,Set/Clear Active Bit 57" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE56 ,Set/Clear Active Bit 56" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE55 ,Set/Clear Active Bit 55" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE54 ,Set/Clear Active Bit 54" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE53 ,Set/Clear Active Bit 53" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE52 ,Set/Clear Active Bit 52" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE51 ,Set/Clear Active Bit 51" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE50 ,Set/Clear Active Bit 50" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE49 ,Set/Clear Active Bit 49" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE48 ,Set/Clear Active Bit 48" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE47 ,Set/Clear Active Bit 47" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE46 ,Set/Clear Active Bit 46" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE45 ,Set/Clear Active Bit 45" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE44 ,Set/Clear Active Bit 44" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE43 ,Set/Clear Active Bit 43" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE42 ,Set/Clear Active Bit 42" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE41 ,Set/Clear Active Bit 41" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE40 ,Set/Clear Active Bit 40" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE39 ,Set/Clear Active Bit 39" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE38 ,Set/Clear Active Bit 38" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE37 ,Set/Clear Active Bit 37" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE36 ,Set/Clear Active Bit 36" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE35 ,Set/Clear Active Bit 35" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE34 ,Set/Clear Active Bit 34" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE33 ,Set/Clear Active Bit 33" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE32 ,Set/Clear Active Bit 32" "Not active,Active" else hgroup.long 0x0304++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x0308++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE95 ,Set/Clear Active Bit 95" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE94 ,Set/Clear Active Bit 94" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE93 ,Set/Clear Active Bit 93" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE92 ,Set/Clear Active Bit 92" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE91 ,Set/Clear Active Bit 91" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE90 ,Set/Clear Active Bit 90" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE89 ,Set/Clear Active Bit 89" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE88 ,Set/Clear Active Bit 88" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE87 ,Set/Clear Active Bit 87" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE86 ,Set/Clear Active Bit 86" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE85 ,Set/Clear Active Bit 85" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE84 ,Set/Clear Active Bit 84" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE83 ,Set/Clear Active Bit 83" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE82 ,Set/Clear Active Bit 82" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE81 ,Set/Clear Active Bit 81" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE80 ,Set/Clear Active Bit 80" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE79 ,Set/Clear Active Bit 79" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE78 ,Set/Clear Active Bit 78" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE77 ,Set/Clear Active Bit 77" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE76 ,Set/Clear Active Bit 76" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE75 ,Set/Clear Active Bit 75" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE74 ,Set/Clear Active Bit 74" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE73 ,Set/Clear Active Bit 73" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE72 ,Set/Clear Active Bit 72" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE71 ,Set/Clear Active Bit 71" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE70 ,Set/Clear Active Bit 70" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE69 ,Set/Clear Active Bit 69" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE68 ,Set/Clear Active Bit 68" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE67 ,Set/Clear Active Bit 67" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE66 ,Set/Clear Active Bit 66" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE65 ,Set/Clear Active Bit 65" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE64 ,Set/Clear Active Bit 64" "Not active,Active" else hgroup.long 0x0308++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x030C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE127 ,Set/Clear Active Bit 127" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE126 ,Set/Clear Active Bit 126" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE125 ,Set/Clear Active Bit 125" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE124 ,Set/Clear Active Bit 124" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE123 ,Set/Clear Active Bit 123" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE122 ,Set/Clear Active Bit 122" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE121 ,Set/Clear Active Bit 121" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE120 ,Set/Clear Active Bit 120" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE119 ,Set/Clear Active Bit 119" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE118 ,Set/Clear Active Bit 118" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE117 ,Set/Clear Active Bit 117" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE116 ,Set/Clear Active Bit 116" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE115 ,Set/Clear Active Bit 115" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE114 ,Set/Clear Active Bit 114" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE113 ,Set/Clear Active Bit 113" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE112 ,Set/Clear Active Bit 112" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE111 ,Set/Clear Active Bit 111" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE110 ,Set/Clear Active Bit 110" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE109 ,Set/Clear Active Bit 109" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE108 ,Set/Clear Active Bit 108" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE107 ,Set/Clear Active Bit 107" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE106 ,Set/Clear Active Bit 106" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE105 ,Set/Clear Active Bit 105" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE104 ,Set/Clear Active Bit 104" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE103 ,Set/Clear Active Bit 103" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE102 ,Set/Clear Active Bit 102" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE101 ,Set/Clear Active Bit 101" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE100 ,Set/Clear Active Bit 100" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE99 ,Set/Clear Active Bit 99" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE98 ,Set/Clear Active Bit 98" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE97 ,Set/Clear Active Bit 97" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE96 ,Set/Clear Active Bit 96" "Not active,Active" else hgroup.long 0x030C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x0310++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE159 ,Set/Clear Active Bit 159" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE158 ,Set/Clear Active Bit 158" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE157 ,Set/Clear Active Bit 157" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE156 ,Set/Clear Active Bit 156" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE155 ,Set/Clear Active Bit 155" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE154 ,Set/Clear Active Bit 154" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE153 ,Set/Clear Active Bit 153" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE152 ,Set/Clear Active Bit 152" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE151 ,Set/Clear Active Bit 151" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE150 ,Set/Clear Active Bit 150" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE149 ,Set/Clear Active Bit 149" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE148 ,Set/Clear Active Bit 148" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE147 ,Set/Clear Active Bit 147" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE146 ,Set/Clear Active Bit 146" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE145 ,Set/Clear Active Bit 145" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE144 ,Set/Clear Active Bit 144" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE143 ,Set/Clear Active Bit 143" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE142 ,Set/Clear Active Bit 142" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE141 ,Set/Clear Active Bit 141" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE140 ,Set/Clear Active Bit 140" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE139 ,Set/Clear Active Bit 139" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE138 ,Set/Clear Active Bit 138" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE137 ,Set/Clear Active Bit 137" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE136 ,Set/Clear Active Bit 136" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE135 ,Set/Clear Active Bit 135" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE134 ,Set/Clear Active Bit 134" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE133 ,Set/Clear Active Bit 133" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE132 ,Set/Clear Active Bit 132" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE131 ,Set/Clear Active Bit 131" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE130 ,Set/Clear Active Bit 130" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE129 ,Set/Clear Active Bit 129" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE128 ,Set/Clear Active Bit 128" "Not active,Active" else hgroup.long 0x0310++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x0314++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE191 ,Set/Clear Active Bit 191" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE190 ,Set/Clear Active Bit 190" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE189 ,Set/Clear Active Bit 189" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE188 ,Set/Clear Active Bit 188" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE187 ,Set/Clear Active Bit 187" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE186 ,Set/Clear Active Bit 186" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE185 ,Set/Clear Active Bit 185" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE184 ,Set/Clear Active Bit 184" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE183 ,Set/Clear Active Bit 183" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE182 ,Set/Clear Active Bit 182" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE181 ,Set/Clear Active Bit 181" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE180 ,Set/Clear Active Bit 180" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE179 ,Set/Clear Active Bit 179" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE178 ,Set/Clear Active Bit 178" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE177 ,Set/Clear Active Bit 177" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE176 ,Set/Clear Active Bit 176" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE175 ,Set/Clear Active Bit 175" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE174 ,Set/Clear Active Bit 174" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE173 ,Set/Clear Active Bit 173" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE172 ,Set/Clear Active Bit 172" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE171 ,Set/Clear Active Bit 171" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE170 ,Set/Clear Active Bit 170" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE169 ,Set/Clear Active Bit 169" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE168 ,Set/Clear Active Bit 168" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE167 ,Set/Clear Active Bit 167" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE166 ,Set/Clear Active Bit 166" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE165 ,Set/Clear Active Bit 165" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE164 ,Set/Clear Active Bit 164" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE163 ,Set/Clear Active Bit 163" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE162 ,Set/Clear Active Bit 162" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE161 ,Set/Clear Active Bit 161" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE160 ,Set/Clear Active Bit 160" "Not active,Active" else hgroup.long 0x0314++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x0318++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE223 ,Set/Clear Active Bit 223" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE222 ,Set/Clear Active Bit 222" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE221 ,Set/Clear Active Bit 221" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE220 ,Set/Clear Active Bit 220" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE219 ,Set/Clear Active Bit 219" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE218 ,Set/Clear Active Bit 218" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE217 ,Set/Clear Active Bit 217" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE216 ,Set/Clear Active Bit 216" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE215 ,Set/Clear Active Bit 215" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE214 ,Set/Clear Active Bit 214" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE213 ,Set/Clear Active Bit 213" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE212 ,Set/Clear Active Bit 212" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE211 ,Set/Clear Active Bit 211" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE210 ,Set/Clear Active Bit 210" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE209 ,Set/Clear Active Bit 209" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE208 ,Set/Clear Active Bit 208" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE207 ,Set/Clear Active Bit 207" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE206 ,Set/Clear Active Bit 206" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE205 ,Set/Clear Active Bit 205" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE204 ,Set/Clear Active Bit 204" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE203 ,Set/Clear Active Bit 203" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE202 ,Set/Clear Active Bit 202" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE201 ,Set/Clear Active Bit 201" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE200 ,Set/Clear Active Bit 200" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE199 ,Set/Clear Active Bit 199" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE198 ,Set/Clear Active Bit 198" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE197 ,Set/Clear Active Bit 197" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE196 ,Set/Clear Active Bit 196" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE195 ,Set/Clear Active Bit 195" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE194 ,Set/Clear Active Bit 194" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE193 ,Set/Clear Active Bit 193" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE192 ,Set/Clear Active Bit 192" "Not active,Active" else hgroup.long 0x0318++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x031C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE255 ,Set/Clear Active Bit 255" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE254 ,Set/Clear Active Bit 254" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE253 ,Set/Clear Active Bit 253" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE252 ,Set/Clear Active Bit 252" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE251 ,Set/Clear Active Bit 251" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE250 ,Set/Clear Active Bit 250" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE249 ,Set/Clear Active Bit 249" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE248 ,Set/Clear Active Bit 248" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE247 ,Set/Clear Active Bit 247" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE246 ,Set/Clear Active Bit 246" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE245 ,Set/Clear Active Bit 245" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE244 ,Set/Clear Active Bit 244" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE243 ,Set/Clear Active Bit 243" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE242 ,Set/Clear Active Bit 242" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE241 ,Set/Clear Active Bit 241" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE240 ,Set/Clear Active Bit 240" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE239 ,Set/Clear Active Bit 239" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE238 ,Set/Clear Active Bit 238" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE237 ,Set/Clear Active Bit 237" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE236 ,Set/Clear Active Bit 236" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE235 ,Set/Clear Active Bit 235" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE234 ,Set/Clear Active Bit 234" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE233 ,Set/Clear Active Bit 233" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE232 ,Set/Clear Active Bit 232" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE231 ,Set/Clear Active Bit 231" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE230 ,Set/Clear Active Bit 230" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE229 ,Set/Clear Active Bit 229" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE228 ,Set/Clear Active Bit 228" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE227 ,Set/Clear Active Bit 227" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE226 ,Set/Clear Active Bit 226" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE225 ,Set/Clear Active Bit 225" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE224 ,Set/Clear Active Bit 224" "Not active,Active" else hgroup.long 0x031C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x0320++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE287 ,Set/Clear Active Bit 287" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE286 ,Set/Clear Active Bit 286" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE285 ,Set/Clear Active Bit 285" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE284 ,Set/Clear Active Bit 284" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE283 ,Set/Clear Active Bit 283" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE282 ,Set/Clear Active Bit 282" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE281 ,Set/Clear Active Bit 281" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE280 ,Set/Clear Active Bit 280" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE279 ,Set/Clear Active Bit 279" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE278 ,Set/Clear Active Bit 278" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE277 ,Set/Clear Active Bit 277" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE276 ,Set/Clear Active Bit 276" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE275 ,Set/Clear Active Bit 275" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE274 ,Set/Clear Active Bit 274" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE273 ,Set/Clear Active Bit 273" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE272 ,Set/Clear Active Bit 272" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE271 ,Set/Clear Active Bit 271" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE270 ,Set/Clear Active Bit 270" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE269 ,Set/Clear Active Bit 269" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE268 ,Set/Clear Active Bit 268" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE267 ,Set/Clear Active Bit 267" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE266 ,Set/Clear Active Bit 266" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE265 ,Set/Clear Active Bit 265" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE264 ,Set/Clear Active Bit 264" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE263 ,Set/Clear Active Bit 263" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE262 ,Set/Clear Active Bit 262" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE261 ,Set/Clear Active Bit 261" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE260 ,Set/Clear Active Bit 260" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE259 ,Set/Clear Active Bit 259" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE258 ,Set/Clear Active Bit 258" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE257 ,Set/Clear Active Bit 257" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE256 ,Set/Clear Active Bit 256" "Not active,Active" else hgroup.long 0x0320++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x0324++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE319 ,Set/Clear Active Bit 319" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE318 ,Set/Clear Active Bit 318" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE317 ,Set/Clear Active Bit 317" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE316 ,Set/Clear Active Bit 316" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE315 ,Set/Clear Active Bit 315" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE314 ,Set/Clear Active Bit 314" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE313 ,Set/Clear Active Bit 313" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE312 ,Set/Clear Active Bit 312" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE311 ,Set/Clear Active Bit 311" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE310 ,Set/Clear Active Bit 310" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE309 ,Set/Clear Active Bit 309" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE308 ,Set/Clear Active Bit 308" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE307 ,Set/Clear Active Bit 307" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE306 ,Set/Clear Active Bit 306" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE305 ,Set/Clear Active Bit 305" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE304 ,Set/Clear Active Bit 304" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE303 ,Set/Clear Active Bit 303" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE302 ,Set/Clear Active Bit 302" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE301 ,Set/Clear Active Bit 301" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE300 ,Set/Clear Active Bit 300" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE299 ,Set/Clear Active Bit 299" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE298 ,Set/Clear Active Bit 298" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE297 ,Set/Clear Active Bit 297" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE296 ,Set/Clear Active Bit 296" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE295 ,Set/Clear Active Bit 295" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE294 ,Set/Clear Active Bit 294" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE293 ,Set/Clear Active Bit 293" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE292 ,Set/Clear Active Bit 292" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE291 ,Set/Clear Active Bit 291" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE290 ,Set/Clear Active Bit 290" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE289 ,Set/Clear Active Bit 289" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE288 ,Set/Clear Active Bit 288" "Not active,Active" else hgroup.long 0x0324++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x0328++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE351 ,Set/Clear Active Bit 351" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE350 ,Set/Clear Active Bit 350" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE349 ,Set/Clear Active Bit 349" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE348 ,Set/Clear Active Bit 348" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE347 ,Set/Clear Active Bit 347" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE346 ,Set/Clear Active Bit 346" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE345 ,Set/Clear Active Bit 345" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE344 ,Set/Clear Active Bit 344" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE343 ,Set/Clear Active Bit 343" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE342 ,Set/Clear Active Bit 342" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE341 ,Set/Clear Active Bit 341" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE340 ,Set/Clear Active Bit 340" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE339 ,Set/Clear Active Bit 339" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE338 ,Set/Clear Active Bit 338" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE337 ,Set/Clear Active Bit 337" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE336 ,Set/Clear Active Bit 336" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE335 ,Set/Clear Active Bit 335" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE334 ,Set/Clear Active Bit 334" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE333 ,Set/Clear Active Bit 333" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE332 ,Set/Clear Active Bit 332" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE331 ,Set/Clear Active Bit 331" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE330 ,Set/Clear Active Bit 330" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE329 ,Set/Clear Active Bit 329" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE328 ,Set/Clear Active Bit 328" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE327 ,Set/Clear Active Bit 327" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE326 ,Set/Clear Active Bit 326" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE325 ,Set/Clear Active Bit 325" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE324 ,Set/Clear Active Bit 324" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE323 ,Set/Clear Active Bit 323" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE322 ,Set/Clear Active Bit 322" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE321 ,Set/Clear Active Bit 321" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE320 ,Set/Clear Active Bit 320" "Not active,Active" else hgroup.long 0x0328++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x032C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE383 ,Set/Clear Active Bit 383" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE382 ,Set/Clear Active Bit 382" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE381 ,Set/Clear Active Bit 381" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE380 ,Set/Clear Active Bit 380" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE379 ,Set/Clear Active Bit 379" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE378 ,Set/Clear Active Bit 378" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE377 ,Set/Clear Active Bit 377" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE376 ,Set/Clear Active Bit 376" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE375 ,Set/Clear Active Bit 375" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE374 ,Set/Clear Active Bit 374" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE373 ,Set/Clear Active Bit 373" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE372 ,Set/Clear Active Bit 372" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE371 ,Set/Clear Active Bit 371" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE370 ,Set/Clear Active Bit 370" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE369 ,Set/Clear Active Bit 369" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE368 ,Set/Clear Active Bit 368" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE367 ,Set/Clear Active Bit 367" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE366 ,Set/Clear Active Bit 366" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE365 ,Set/Clear Active Bit 365" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE364 ,Set/Clear Active Bit 364" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE363 ,Set/Clear Active Bit 363" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE362 ,Set/Clear Active Bit 362" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE361 ,Set/Clear Active Bit 361" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE360 ,Set/Clear Active Bit 360" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE359 ,Set/Clear Active Bit 359" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE358 ,Set/Clear Active Bit 358" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE357 ,Set/Clear Active Bit 357" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE356 ,Set/Clear Active Bit 356" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE355 ,Set/Clear Active Bit 355" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE354 ,Set/Clear Active Bit 354" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE353 ,Set/Clear Active Bit 353" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE352 ,Set/Clear Active Bit 352" "Not active,Active" else hgroup.long 0x032C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x0330++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE415 ,Set/Clear Active Bit 415" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE414 ,Set/Clear Active Bit 414" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE413 ,Set/Clear Active Bit 413" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE412 ,Set/Clear Active Bit 412" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE411 ,Set/Clear Active Bit 411" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE410 ,Set/Clear Active Bit 410" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE409 ,Set/Clear Active Bit 409" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE408 ,Set/Clear Active Bit 408" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE407 ,Set/Clear Active Bit 407" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE406 ,Set/Clear Active Bit 406" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE405 ,Set/Clear Active Bit 405" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE404 ,Set/Clear Active Bit 404" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE403 ,Set/Clear Active Bit 403" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE402 ,Set/Clear Active Bit 402" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE401 ,Set/Clear Active Bit 401" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE400 ,Set/Clear Active Bit 400" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE399 ,Set/Clear Active Bit 399" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE398 ,Set/Clear Active Bit 398" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE397 ,Set/Clear Active Bit 397" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE396 ,Set/Clear Active Bit 396" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE395 ,Set/Clear Active Bit 395" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE394 ,Set/Clear Active Bit 394" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE393 ,Set/Clear Active Bit 393" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE392 ,Set/Clear Active Bit 392" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE391 ,Set/Clear Active Bit 391" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE390 ,Set/Clear Active Bit 390" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE389 ,Set/Clear Active Bit 389" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE388 ,Set/Clear Active Bit 388" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE387 ,Set/Clear Active Bit 387" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE386 ,Set/Clear Active Bit 386" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE385 ,Set/Clear Active Bit 385" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE384 ,Set/Clear Active Bit 384" "Not active,Active" else hgroup.long 0x0330++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x0334++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE447 ,Set/Clear Active Bit 447" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE446 ,Set/Clear Active Bit 446" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE445 ,Set/Clear Active Bit 445" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE444 ,Set/Clear Active Bit 444" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE443 ,Set/Clear Active Bit 443" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE442 ,Set/Clear Active Bit 442" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE441 ,Set/Clear Active Bit 441" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE440 ,Set/Clear Active Bit 440" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE439 ,Set/Clear Active Bit 439" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE438 ,Set/Clear Active Bit 438" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE437 ,Set/Clear Active Bit 437" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE436 ,Set/Clear Active Bit 436" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE435 ,Set/Clear Active Bit 435" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE434 ,Set/Clear Active Bit 434" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE433 ,Set/Clear Active Bit 433" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE432 ,Set/Clear Active Bit 432" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE431 ,Set/Clear Active Bit 431" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE430 ,Set/Clear Active Bit 430" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE429 ,Set/Clear Active Bit 429" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE428 ,Set/Clear Active Bit 428" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE427 ,Set/Clear Active Bit 427" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE426 ,Set/Clear Active Bit 426" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE425 ,Set/Clear Active Bit 425" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE424 ,Set/Clear Active Bit 424" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE423 ,Set/Clear Active Bit 423" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE422 ,Set/Clear Active Bit 422" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE421 ,Set/Clear Active Bit 421" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE420 ,Set/Clear Active Bit 420" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE419 ,Set/Clear Active Bit 419" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE418 ,Set/Clear Active Bit 418" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE417 ,Set/Clear Active Bit 417" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE416 ,Set/Clear Active Bit 416" "Not active,Active" else hgroup.long 0x0334++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x0338++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE479 ,Set/Clear Active Bit 479" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE478 ,Set/Clear Active Bit 478" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE477 ,Set/Clear Active Bit 477" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE476 ,Set/Clear Active Bit 476" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE475 ,Set/Clear Active Bit 475" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE474 ,Set/Clear Active Bit 474" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE473 ,Set/Clear Active Bit 473" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE472 ,Set/Clear Active Bit 472" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE471 ,Set/Clear Active Bit 471" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE470 ,Set/Clear Active Bit 470" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE469 ,Set/Clear Active Bit 469" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE468 ,Set/Clear Active Bit 468" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE467 ,Set/Clear Active Bit 467" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE466 ,Set/Clear Active Bit 466" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE465 ,Set/Clear Active Bit 465" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE464 ,Set/Clear Active Bit 464" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE463 ,Set/Clear Active Bit 463" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE462 ,Set/Clear Active Bit 462" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE461 ,Set/Clear Active Bit 461" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE460 ,Set/Clear Active Bit 460" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE459 ,Set/Clear Active Bit 459" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE458 ,Set/Clear Active Bit 458" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE457 ,Set/Clear Active Bit 457" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE456 ,Set/Clear Active Bit 456" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE455 ,Set/Clear Active Bit 455" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE454 ,Set/Clear Active Bit 454" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE453 ,Set/Clear Active Bit 453" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE452 ,Set/Clear Active Bit 452" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE451 ,Set/Clear Active Bit 451" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE450 ,Set/Clear Active Bit 450" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE449 ,Set/Clear Active Bit 449" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE448 ,Set/Clear Active Bit 448" "Not active,Active" else hgroup.long 0x0338++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x033C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE511 ,Set/Clear Active Bit 511" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE510 ,Set/Clear Active Bit 510" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE509 ,Set/Clear Active Bit 509" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE508 ,Set/Clear Active Bit 508" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE507 ,Set/Clear Active Bit 507" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE506 ,Set/Clear Active Bit 506" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE505 ,Set/Clear Active Bit 505" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE504 ,Set/Clear Active Bit 504" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE503 ,Set/Clear Active Bit 503" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE502 ,Set/Clear Active Bit 502" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE501 ,Set/Clear Active Bit 501" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE500 ,Set/Clear Active Bit 500" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE499 ,Set/Clear Active Bit 499" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE498 ,Set/Clear Active Bit 498" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE497 ,Set/Clear Active Bit 497" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE496 ,Set/Clear Active Bit 496" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE495 ,Set/Clear Active Bit 495" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE494 ,Set/Clear Active Bit 494" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE493 ,Set/Clear Active Bit 493" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE492 ,Set/Clear Active Bit 492" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE491 ,Set/Clear Active Bit 491" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE490 ,Set/Clear Active Bit 490" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE489 ,Set/Clear Active Bit 489" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE488 ,Set/Clear Active Bit 488" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE487 ,Set/Clear Active Bit 487" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE486 ,Set/Clear Active Bit 486" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE485 ,Set/Clear Active Bit 485" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE484 ,Set/Clear Active Bit 484" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE483 ,Set/Clear Active Bit 483" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE482 ,Set/Clear Active Bit 482" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE481 ,Set/Clear Active Bit 481" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE480 ,Set/Clear Active Bit 480" "Not active,Active" else hgroup.long 0x033C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x0340++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE543 ,Set/Clear Active Bit 543" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE542 ,Set/Clear Active Bit 542" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE541 ,Set/Clear Active Bit 541" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE540 ,Set/Clear Active Bit 540" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE539 ,Set/Clear Active Bit 539" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE538 ,Set/Clear Active Bit 538" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE537 ,Set/Clear Active Bit 537" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE536 ,Set/Clear Active Bit 536" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE535 ,Set/Clear Active Bit 535" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE534 ,Set/Clear Active Bit 534" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE533 ,Set/Clear Active Bit 533" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE532 ,Set/Clear Active Bit 532" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE531 ,Set/Clear Active Bit 531" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE530 ,Set/Clear Active Bit 530" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE529 ,Set/Clear Active Bit 529" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE528 ,Set/Clear Active Bit 528" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE527 ,Set/Clear Active Bit 527" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE526 ,Set/Clear Active Bit 526" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE525 ,Set/Clear Active Bit 525" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE524 ,Set/Clear Active Bit 524" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE523 ,Set/Clear Active Bit 523" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE522 ,Set/Clear Active Bit 522" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE521 ,Set/Clear Active Bit 521" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE520 ,Set/Clear Active Bit 520" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE519 ,Set/Clear Active Bit 519" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE518 ,Set/Clear Active Bit 518" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE517 ,Set/Clear Active Bit 517" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE516 ,Set/Clear Active Bit 516" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE515 ,Set/Clear Active Bit 515" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE514 ,Set/Clear Active Bit 514" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE513 ,Set/Clear Active Bit 513" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE512 ,Set/Clear Active Bit 512" "Not active,Active" else hgroup.long 0x0340++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x0344++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE575 ,Set/Clear Active Bit 575" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE574 ,Set/Clear Active Bit 574" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE573 ,Set/Clear Active Bit 573" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE572 ,Set/Clear Active Bit 572" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE571 ,Set/Clear Active Bit 571" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE570 ,Set/Clear Active Bit 570" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE569 ,Set/Clear Active Bit 569" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE568 ,Set/Clear Active Bit 568" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE567 ,Set/Clear Active Bit 567" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE566 ,Set/Clear Active Bit 566" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE565 ,Set/Clear Active Bit 565" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE564 ,Set/Clear Active Bit 564" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE563 ,Set/Clear Active Bit 563" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE562 ,Set/Clear Active Bit 562" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE561 ,Set/Clear Active Bit 561" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE560 ,Set/Clear Active Bit 560" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE559 ,Set/Clear Active Bit 559" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE558 ,Set/Clear Active Bit 558" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE557 ,Set/Clear Active Bit 557" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE556 ,Set/Clear Active Bit 556" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE555 ,Set/Clear Active Bit 555" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE554 ,Set/Clear Active Bit 554" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE553 ,Set/Clear Active Bit 553" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE552 ,Set/Clear Active Bit 552" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE551 ,Set/Clear Active Bit 551" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE550 ,Set/Clear Active Bit 550" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE549 ,Set/Clear Active Bit 549" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE548 ,Set/Clear Active Bit 548" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE547 ,Set/Clear Active Bit 547" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE546 ,Set/Clear Active Bit 546" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE545 ,Set/Clear Active Bit 545" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE544 ,Set/Clear Active Bit 544" "Not active,Active" else hgroup.long 0x0344++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x0348++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE607 ,Set/Clear Active Bit 607" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE606 ,Set/Clear Active Bit 606" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE605 ,Set/Clear Active Bit 605" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE604 ,Set/Clear Active Bit 604" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE603 ,Set/Clear Active Bit 603" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE602 ,Set/Clear Active Bit 602" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE601 ,Set/Clear Active Bit 601" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE600 ,Set/Clear Active Bit 600" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE599 ,Set/Clear Active Bit 599" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE598 ,Set/Clear Active Bit 598" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE597 ,Set/Clear Active Bit 597" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE596 ,Set/Clear Active Bit 596" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE595 ,Set/Clear Active Bit 595" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE594 ,Set/Clear Active Bit 594" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE593 ,Set/Clear Active Bit 593" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE592 ,Set/Clear Active Bit 592" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE591 ,Set/Clear Active Bit 591" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE590 ,Set/Clear Active Bit 590" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE589 ,Set/Clear Active Bit 589" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE588 ,Set/Clear Active Bit 588" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE587 ,Set/Clear Active Bit 587" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE586 ,Set/Clear Active Bit 586" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE585 ,Set/Clear Active Bit 585" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE584 ,Set/Clear Active Bit 584" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE583 ,Set/Clear Active Bit 583" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE582 ,Set/Clear Active Bit 582" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE581 ,Set/Clear Active Bit 581" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE580 ,Set/Clear Active Bit 580" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE579 ,Set/Clear Active Bit 579" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE578 ,Set/Clear Active Bit 578" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE577 ,Set/Clear Active Bit 577" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE576 ,Set/Clear Active Bit 576" "Not active,Active" else hgroup.long 0x0348++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x034C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE639 ,Set/Clear Active Bit 639" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE638 ,Set/Clear Active Bit 638" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE637 ,Set/Clear Active Bit 637" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE636 ,Set/Clear Active Bit 636" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE635 ,Set/Clear Active Bit 635" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE634 ,Set/Clear Active Bit 634" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE633 ,Set/Clear Active Bit 633" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE632 ,Set/Clear Active Bit 632" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE631 ,Set/Clear Active Bit 631" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE630 ,Set/Clear Active Bit 630" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE629 ,Set/Clear Active Bit 629" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE628 ,Set/Clear Active Bit 628" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE627 ,Set/Clear Active Bit 627" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE626 ,Set/Clear Active Bit 626" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE625 ,Set/Clear Active Bit 625" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE624 ,Set/Clear Active Bit 624" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE623 ,Set/Clear Active Bit 623" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE622 ,Set/Clear Active Bit 622" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE621 ,Set/Clear Active Bit 621" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE620 ,Set/Clear Active Bit 620" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE619 ,Set/Clear Active Bit 619" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE618 ,Set/Clear Active Bit 618" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE617 ,Set/Clear Active Bit 617" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE616 ,Set/Clear Active Bit 616" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE615 ,Set/Clear Active Bit 615" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE614 ,Set/Clear Active Bit 614" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE613 ,Set/Clear Active Bit 613" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE612 ,Set/Clear Active Bit 612" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE611 ,Set/Clear Active Bit 611" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE610 ,Set/Clear Active Bit 610" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE609 ,Set/Clear Active Bit 609" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE608 ,Set/Clear Active Bit 608" "Not active,Active" else hgroup.long 0x034C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x0350++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE671 ,Set/Clear Active Bit 671" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE670 ,Set/Clear Active Bit 670" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE669 ,Set/Clear Active Bit 669" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE668 ,Set/Clear Active Bit 668" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE667 ,Set/Clear Active Bit 667" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE666 ,Set/Clear Active Bit 666" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE665 ,Set/Clear Active Bit 665" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE664 ,Set/Clear Active Bit 664" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE663 ,Set/Clear Active Bit 663" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE662 ,Set/Clear Active Bit 662" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE661 ,Set/Clear Active Bit 661" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE660 ,Set/Clear Active Bit 660" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE659 ,Set/Clear Active Bit 659" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE658 ,Set/Clear Active Bit 658" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE657 ,Set/Clear Active Bit 657" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE656 ,Set/Clear Active Bit 656" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE655 ,Set/Clear Active Bit 655" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE654 ,Set/Clear Active Bit 654" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE653 ,Set/Clear Active Bit 653" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE652 ,Set/Clear Active Bit 652" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE651 ,Set/Clear Active Bit 651" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE650 ,Set/Clear Active Bit 650" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE649 ,Set/Clear Active Bit 649" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE648 ,Set/Clear Active Bit 648" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE647 ,Set/Clear Active Bit 647" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE646 ,Set/Clear Active Bit 646" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE645 ,Set/Clear Active Bit 645" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE644 ,Set/Clear Active Bit 644" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE643 ,Set/Clear Active Bit 643" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE642 ,Set/Clear Active Bit 642" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE641 ,Set/Clear Active Bit 641" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE640 ,Set/Clear Active Bit 640" "Not active,Active" else hgroup.long 0x0350++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x0354++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE703 ,Set/Clear Active Bit 703" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE702 ,Set/Clear Active Bit 702" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE701 ,Set/Clear Active Bit 701" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE700 ,Set/Clear Active Bit 700" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE699 ,Set/Clear Active Bit 699" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE698 ,Set/Clear Active Bit 698" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE697 ,Set/Clear Active Bit 697" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE696 ,Set/Clear Active Bit 696" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE695 ,Set/Clear Active Bit 695" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE694 ,Set/Clear Active Bit 694" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE693 ,Set/Clear Active Bit 693" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE692 ,Set/Clear Active Bit 692" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE691 ,Set/Clear Active Bit 691" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE690 ,Set/Clear Active Bit 690" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE689 ,Set/Clear Active Bit 689" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE688 ,Set/Clear Active Bit 688" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE687 ,Set/Clear Active Bit 687" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE686 ,Set/Clear Active Bit 686" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE685 ,Set/Clear Active Bit 685" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE684 ,Set/Clear Active Bit 684" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE683 ,Set/Clear Active Bit 683" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE682 ,Set/Clear Active Bit 682" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE681 ,Set/Clear Active Bit 681" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE680 ,Set/Clear Active Bit 680" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE679 ,Set/Clear Active Bit 679" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE678 ,Set/Clear Active Bit 678" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE677 ,Set/Clear Active Bit 677" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE676 ,Set/Clear Active Bit 676" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE675 ,Set/Clear Active Bit 675" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE674 ,Set/Clear Active Bit 674" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE673 ,Set/Clear Active Bit 673" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE672 ,Set/Clear Active Bit 672" "Not active,Active" else hgroup.long 0x0354++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x0358++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE735 ,Set/Clear Active Bit 735" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE734 ,Set/Clear Active Bit 734" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE733 ,Set/Clear Active Bit 733" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE732 ,Set/Clear Active Bit 732" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE731 ,Set/Clear Active Bit 731" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE730 ,Set/Clear Active Bit 730" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE729 ,Set/Clear Active Bit 729" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE728 ,Set/Clear Active Bit 728" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE727 ,Set/Clear Active Bit 727" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE726 ,Set/Clear Active Bit 726" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE725 ,Set/Clear Active Bit 725" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE724 ,Set/Clear Active Bit 724" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE723 ,Set/Clear Active Bit 723" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE722 ,Set/Clear Active Bit 722" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE721 ,Set/Clear Active Bit 721" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE720 ,Set/Clear Active Bit 720" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE719 ,Set/Clear Active Bit 719" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE718 ,Set/Clear Active Bit 718" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE717 ,Set/Clear Active Bit 717" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE716 ,Set/Clear Active Bit 716" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE715 ,Set/Clear Active Bit 715" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE714 ,Set/Clear Active Bit 714" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE713 ,Set/Clear Active Bit 713" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE712 ,Set/Clear Active Bit 712" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE711 ,Set/Clear Active Bit 711" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE710 ,Set/Clear Active Bit 710" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE709 ,Set/Clear Active Bit 709" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE708 ,Set/Clear Active Bit 708" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE707 ,Set/Clear Active Bit 707" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE706 ,Set/Clear Active Bit 706" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE705 ,Set/Clear Active Bit 705" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE704 ,Set/Clear Active Bit 704" "Not active,Active" else hgroup.long 0x0358++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x035C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE767 ,Set/Clear Active Bit 767" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE766 ,Set/Clear Active Bit 766" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE765 ,Set/Clear Active Bit 765" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE764 ,Set/Clear Active Bit 764" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE763 ,Set/Clear Active Bit 763" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE762 ,Set/Clear Active Bit 762" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE761 ,Set/Clear Active Bit 761" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE760 ,Set/Clear Active Bit 760" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE759 ,Set/Clear Active Bit 759" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE758 ,Set/Clear Active Bit 758" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE757 ,Set/Clear Active Bit 757" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE756 ,Set/Clear Active Bit 756" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE755 ,Set/Clear Active Bit 755" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE754 ,Set/Clear Active Bit 754" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE753 ,Set/Clear Active Bit 753" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE752 ,Set/Clear Active Bit 752" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE751 ,Set/Clear Active Bit 751" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE750 ,Set/Clear Active Bit 750" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE749 ,Set/Clear Active Bit 749" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE748 ,Set/Clear Active Bit 748" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE747 ,Set/Clear Active Bit 747" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE746 ,Set/Clear Active Bit 746" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE745 ,Set/Clear Active Bit 745" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE744 ,Set/Clear Active Bit 744" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE743 ,Set/Clear Active Bit 743" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE742 ,Set/Clear Active Bit 742" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE741 ,Set/Clear Active Bit 741" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE740 ,Set/Clear Active Bit 740" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE739 ,Set/Clear Active Bit 739" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE738 ,Set/Clear Active Bit 738" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE737 ,Set/Clear Active Bit 737" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE736 ,Set/Clear Active Bit 736" "Not active,Active" else hgroup.long 0x035C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x0360++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE799 ,Set/Clear Active Bit 799" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE798 ,Set/Clear Active Bit 798" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE797 ,Set/Clear Active Bit 797" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE796 ,Set/Clear Active Bit 796" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE795 ,Set/Clear Active Bit 795" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE794 ,Set/Clear Active Bit 794" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE793 ,Set/Clear Active Bit 793" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE792 ,Set/Clear Active Bit 792" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE791 ,Set/Clear Active Bit 791" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE790 ,Set/Clear Active Bit 790" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE789 ,Set/Clear Active Bit 789" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE788 ,Set/Clear Active Bit 788" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE787 ,Set/Clear Active Bit 787" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE786 ,Set/Clear Active Bit 786" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE785 ,Set/Clear Active Bit 785" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE784 ,Set/Clear Active Bit 784" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE783 ,Set/Clear Active Bit 783" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE782 ,Set/Clear Active Bit 782" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE781 ,Set/Clear Active Bit 781" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE780 ,Set/Clear Active Bit 780" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE779 ,Set/Clear Active Bit 779" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE778 ,Set/Clear Active Bit 778" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE777 ,Set/Clear Active Bit 777" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE776 ,Set/Clear Active Bit 776" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE775 ,Set/Clear Active Bit 775" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE774 ,Set/Clear Active Bit 774" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE773 ,Set/Clear Active Bit 773" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE772 ,Set/Clear Active Bit 772" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE771 ,Set/Clear Active Bit 771" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE770 ,Set/Clear Active Bit 770" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE769 ,Set/Clear Active Bit 769" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE768 ,Set/Clear Active Bit 768" "Not active,Active" else hgroup.long 0x0360++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x0364++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE831 ,Set/Clear Active Bit 831" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE830 ,Set/Clear Active Bit 830" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE829 ,Set/Clear Active Bit 829" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE828 ,Set/Clear Active Bit 828" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE827 ,Set/Clear Active Bit 827" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE826 ,Set/Clear Active Bit 826" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE825 ,Set/Clear Active Bit 825" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE824 ,Set/Clear Active Bit 824" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE823 ,Set/Clear Active Bit 823" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE822 ,Set/Clear Active Bit 822" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE821 ,Set/Clear Active Bit 821" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE820 ,Set/Clear Active Bit 820" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE819 ,Set/Clear Active Bit 819" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE818 ,Set/Clear Active Bit 818" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE817 ,Set/Clear Active Bit 817" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE816 ,Set/Clear Active Bit 816" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE815 ,Set/Clear Active Bit 815" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE814 ,Set/Clear Active Bit 814" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE813 ,Set/Clear Active Bit 813" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE812 ,Set/Clear Active Bit 812" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE811 ,Set/Clear Active Bit 811" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE810 ,Set/Clear Active Bit 810" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE809 ,Set/Clear Active Bit 809" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE808 ,Set/Clear Active Bit 808" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE807 ,Set/Clear Active Bit 807" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE806 ,Set/Clear Active Bit 806" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE805 ,Set/Clear Active Bit 805" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE804 ,Set/Clear Active Bit 804" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE803 ,Set/Clear Active Bit 803" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE802 ,Set/Clear Active Bit 802" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE801 ,Set/Clear Active Bit 801" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE800 ,Set/Clear Active Bit 800" "Not active,Active" else hgroup.long 0x0364++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x0368++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE863 ,Set/Clear Active Bit 863" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE862 ,Set/Clear Active Bit 862" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE861 ,Set/Clear Active Bit 861" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE860 ,Set/Clear Active Bit 860" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE859 ,Set/Clear Active Bit 859" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE858 ,Set/Clear Active Bit 858" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE857 ,Set/Clear Active Bit 857" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE856 ,Set/Clear Active Bit 856" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE855 ,Set/Clear Active Bit 855" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE854 ,Set/Clear Active Bit 854" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE853 ,Set/Clear Active Bit 853" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE852 ,Set/Clear Active Bit 852" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE851 ,Set/Clear Active Bit 851" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE850 ,Set/Clear Active Bit 850" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE849 ,Set/Clear Active Bit 849" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE848 ,Set/Clear Active Bit 848" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE847 ,Set/Clear Active Bit 847" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE846 ,Set/Clear Active Bit 846" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE845 ,Set/Clear Active Bit 845" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE844 ,Set/Clear Active Bit 844" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE843 ,Set/Clear Active Bit 843" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE842 ,Set/Clear Active Bit 842" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE841 ,Set/Clear Active Bit 841" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE840 ,Set/Clear Active Bit 840" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE839 ,Set/Clear Active Bit 839" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE838 ,Set/Clear Active Bit 838" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE837 ,Set/Clear Active Bit 837" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE836 ,Set/Clear Active Bit 836" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE835 ,Set/Clear Active Bit 835" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE834 ,Set/Clear Active Bit 834" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE833 ,Set/Clear Active Bit 833" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE832 ,Set/Clear Active Bit 832" "Not active,Active" else hgroup.long 0x0368++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x036C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE895 ,Set/Clear Active Bit 895" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE894 ,Set/Clear Active Bit 894" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE893 ,Set/Clear Active Bit 893" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE892 ,Set/Clear Active Bit 892" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE891 ,Set/Clear Active Bit 891" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE890 ,Set/Clear Active Bit 890" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE889 ,Set/Clear Active Bit 889" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE888 ,Set/Clear Active Bit 888" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE887 ,Set/Clear Active Bit 887" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE886 ,Set/Clear Active Bit 886" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE885 ,Set/Clear Active Bit 885" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE884 ,Set/Clear Active Bit 884" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE883 ,Set/Clear Active Bit 883" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE882 ,Set/Clear Active Bit 882" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE881 ,Set/Clear Active Bit 881" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE880 ,Set/Clear Active Bit 880" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE879 ,Set/Clear Active Bit 879" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE878 ,Set/Clear Active Bit 878" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE877 ,Set/Clear Active Bit 877" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE876 ,Set/Clear Active Bit 876" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE875 ,Set/Clear Active Bit 875" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE874 ,Set/Clear Active Bit 874" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE873 ,Set/Clear Active Bit 873" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE872 ,Set/Clear Active Bit 872" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE871 ,Set/Clear Active Bit 871" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE870 ,Set/Clear Active Bit 870" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE869 ,Set/Clear Active Bit 869" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE868 ,Set/Clear Active Bit 868" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE867 ,Set/Clear Active Bit 867" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE866 ,Set/Clear Active Bit 866" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE865 ,Set/Clear Active Bit 865" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE864 ,Set/Clear Active Bit 864" "Not active,Active" else hgroup.long 0x036C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x0370++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE927 ,Set/Clear Active Bit 927" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE926 ,Set/Clear Active Bit 926" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE925 ,Set/Clear Active Bit 925" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE924 ,Set/Clear Active Bit 924" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE923 ,Set/Clear Active Bit 923" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE922 ,Set/Clear Active Bit 922" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE921 ,Set/Clear Active Bit 921" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE920 ,Set/Clear Active Bit 920" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE919 ,Set/Clear Active Bit 919" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE918 ,Set/Clear Active Bit 918" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE917 ,Set/Clear Active Bit 917" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE916 ,Set/Clear Active Bit 916" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE915 ,Set/Clear Active Bit 915" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE914 ,Set/Clear Active Bit 914" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE913 ,Set/Clear Active Bit 913" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE912 ,Set/Clear Active Bit 912" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE911 ,Set/Clear Active Bit 911" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE910 ,Set/Clear Active Bit 910" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE909 ,Set/Clear Active Bit 909" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE908 ,Set/Clear Active Bit 908" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE907 ,Set/Clear Active Bit 907" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE906 ,Set/Clear Active Bit 906" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE905 ,Set/Clear Active Bit 905" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE904 ,Set/Clear Active Bit 904" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE903 ,Set/Clear Active Bit 903" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE902 ,Set/Clear Active Bit 902" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE901 ,Set/Clear Active Bit 901" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE900 ,Set/Clear Active Bit 900" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE899 ,Set/Clear Active Bit 899" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE898 ,Set/Clear Active Bit 898" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE897 ,Set/Clear Active Bit 897" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE896 ,Set/Clear Active Bit 896" "Not active,Active" else hgroup.long 0x0370++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x0374++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE959 ,Set/Clear Active Bit 959" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE958 ,Set/Clear Active Bit 958" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE957 ,Set/Clear Active Bit 957" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE956 ,Set/Clear Active Bit 956" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE955 ,Set/Clear Active Bit 955" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE954 ,Set/Clear Active Bit 954" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE953 ,Set/Clear Active Bit 953" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE952 ,Set/Clear Active Bit 952" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE951 ,Set/Clear Active Bit 951" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE950 ,Set/Clear Active Bit 950" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE949 ,Set/Clear Active Bit 949" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE948 ,Set/Clear Active Bit 948" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE947 ,Set/Clear Active Bit 947" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE946 ,Set/Clear Active Bit 946" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE945 ,Set/Clear Active Bit 945" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE944 ,Set/Clear Active Bit 944" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE943 ,Set/Clear Active Bit 943" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE942 ,Set/Clear Active Bit 942" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE941 ,Set/Clear Active Bit 941" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE940 ,Set/Clear Active Bit 940" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE939 ,Set/Clear Active Bit 939" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE938 ,Set/Clear Active Bit 938" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE937 ,Set/Clear Active Bit 937" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE936 ,Set/Clear Active Bit 936" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE935 ,Set/Clear Active Bit 935" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE934 ,Set/Clear Active Bit 934" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE933 ,Set/Clear Active Bit 933" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE932 ,Set/Clear Active Bit 932" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE931 ,Set/Clear Active Bit 931" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE930 ,Set/Clear Active Bit 930" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE929 ,Set/Clear Active Bit 929" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE928 ,Set/Clear Active Bit 928" "Not active,Active" else hgroup.long 0x0374++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x0378++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE991 ,Set/Clear Active Bit 991" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE990 ,Set/Clear Active Bit 990" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE989 ,Set/Clear Active Bit 989" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE988 ,Set/Clear Active Bit 988" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE987 ,Set/Clear Active Bit 987" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE986 ,Set/Clear Active Bit 986" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE985 ,Set/Clear Active Bit 985" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE984 ,Set/Clear Active Bit 984" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE983 ,Set/Clear Active Bit 983" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE982 ,Set/Clear Active Bit 982" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE981 ,Set/Clear Active Bit 981" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE980 ,Set/Clear Active Bit 980" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE979 ,Set/Clear Active Bit 979" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE978 ,Set/Clear Active Bit 978" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE977 ,Set/Clear Active Bit 977" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE976 ,Set/Clear Active Bit 976" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE975 ,Set/Clear Active Bit 975" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE974 ,Set/Clear Active Bit 974" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE973 ,Set/Clear Active Bit 973" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE972 ,Set/Clear Active Bit 972" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE971 ,Set/Clear Active Bit 971" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE970 ,Set/Clear Active Bit 970" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE969 ,Set/Clear Active Bit 969" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE968 ,Set/Clear Active Bit 968" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE967 ,Set/Clear Active Bit 967" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE966 ,Set/Clear Active Bit 966" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE965 ,Set/Clear Active Bit 965" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE964 ,Set/Clear Active Bit 964" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE963 ,Set/Clear Active Bit 963" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE962 ,Set/Clear Active Bit 962" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE961 ,Set/Clear Active Bit 961" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE960 ,Set/Clear Active Bit 960" "Not active,Active" else hgroup.long 0x0378++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30" endif tree.end width 20. tree "Priority Registers" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x400++0x03 hide.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0" hgroup.long 0x404++0x03 hide.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1" hgroup.long 0x408++0x03 hide.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2" hgroup.long 0x40C++0x03 hide.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3" hgroup.long 0x410++0x03 hide.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4" hgroup.long 0x414++0x03 hide.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5" hgroup.long 0x418++0x03 hide.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6" hgroup.long 0x41C++0x03 hide.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7" else group.long 0x400++0x03 line.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0" hexmask.long.byte 0x00 24.--31. 1. " INTID3 ,Interrupt ID3 Priority/Priority Byte Offset 3 " hexmask.long.byte 0x00 16.--23. 1. " INTID2 ,Interrupt ID2 Priority/Priority Byte Offset 2 " hexmask.long.byte 0x00 8.--15. 1. " INTID1 ,Interrupt ID1 Priority/Priority Byte Offset 1 " hexmask.long.byte 0x00 0.--7. 1. " INTID0 ,Interrupt ID0 Priority/Priority Byte Offset 0 " group.long 0x404++0x03 line.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1" hexmask.long.byte 0x00 24.--31. 1. " INTID7 ,Interrupt ID7 Priority/Priority Byte Offset 7 " hexmask.long.byte 0x00 16.--23. 1. " INTID6 ,Interrupt ID6 Priority/Priority Byte Offset 6 " hexmask.long.byte 0x00 8.--15. 1. " INTID5 ,Interrupt ID5 Priority/Priority Byte Offset 5 " hexmask.long.byte 0x00 0.--7. 1. " INTID4 ,Interrupt ID4 Priority/Priority Byte Offset 4 " group.long 0x408++0x03 line.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2" hexmask.long.byte 0x00 24.--31. 1. " INTID11 ,Interrupt ID11 Priority/Priority Byte Offset 11 " hexmask.long.byte 0x00 16.--23. 1. " INTID10 ,Interrupt ID10 Priority/Priority Byte Offset 10 " hexmask.long.byte 0x00 8.--15. 1. " INTID9 ,Interrupt ID9 Priority/Priority Byte Offset 9 " hexmask.long.byte 0x00 0.--7. 1. " INTID8 ,Interrupt ID8 Priority/Priority Byte Offset 8 " group.long 0x40C++0x03 line.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3" hexmask.long.byte 0x00 24.--31. 1. " INTID15 ,Interrupt ID15 Priority/Priority Byte Offset 15 " hexmask.long.byte 0x00 16.--23. 1. " INTID14 ,Interrupt ID14 Priority/Priority Byte Offset 14 " hexmask.long.byte 0x00 8.--15. 1. " INTID13 ,Interrupt ID13 Priority/Priority Byte Offset 13 " hexmask.long.byte 0x00 0.--7. 1. " INTID12 ,Interrupt ID12 Priority/Priority Byte Offset 12 " group.long 0x410++0x03 line.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4" hexmask.long.byte 0x00 24.--31. 1. " INTID19 ,Interrupt ID19 Priority/Priority Byte Offset 19 " hexmask.long.byte 0x00 16.--23. 1. " INTID18 ,Interrupt ID18 Priority/Priority Byte Offset 18 " hexmask.long.byte 0x00 8.--15. 1. " INTID17 ,Interrupt ID17 Priority/Priority Byte Offset 17 " hexmask.long.byte 0x00 0.--7. 1. " INTID16 ,Interrupt ID16 Priority/Priority Byte Offset 16 " group.long 0x414++0x03 line.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5" hexmask.long.byte 0x00 24.--31. 1. " INTID23 ,Interrupt ID23 Priority/Priority Byte Offset 23 " hexmask.long.byte 0x00 16.--23. 1. " INTID22 ,Interrupt ID22 Priority/Priority Byte Offset 22 " hexmask.long.byte 0x00 8.--15. 1. " INTID21 ,Interrupt ID21 Priority/Priority Byte Offset 21 " hexmask.long.byte 0x00 0.--7. 1. " INTID20 ,Interrupt ID20 Priority/Priority Byte Offset 20 " group.long 0x418++0x03 line.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6" hexmask.long.byte 0x00 24.--31. 1. " INTID27 ,Interrupt ID27 Priority/Priority Byte Offset 27 " hexmask.long.byte 0x00 16.--23. 1. " INTID26 ,Interrupt ID26 Priority/Priority Byte Offset 26 " hexmask.long.byte 0x00 8.--15. 1. " INTID25 ,Interrupt ID25 Priority/Priority Byte Offset 25 " hexmask.long.byte 0x00 0.--7. 1. " INTID24 ,Interrupt ID24 Priority/Priority Byte Offset 24 " group.long 0x41C++0x03 line.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7" hexmask.long.byte 0x00 24.--31. 1. " INTID31 ,Interrupt ID31 Priority/Priority Byte Offset 31 " hexmask.long.byte 0x00 16.--23. 1. " INTID30 ,Interrupt ID30 Priority/Priority Byte Offset 30 " hexmask.long.byte 0x00 8.--15. 1. " INTID29 ,Interrupt ID29 Priority/Priority Byte Offset 29 " hexmask.long.byte 0x00 0.--7. 1. " INTID28 ,Interrupt ID28 Priority/Priority Byte Offset 28 " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x420++0x03 line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" hexmask.long.byte 0x00 24.--31. 1. " INTID35 ,Interrupt ID35 Priority/Priority Byte Offset 35 " hexmask.long.byte 0x00 16.--23. 1. " INTID34 ,Interrupt ID34 Priority/Priority Byte Offset 34 " hexmask.long.byte 0x00 8.--15. 1. " INTID33 ,Interrupt ID33 Priority/Priority Byte Offset 33 " hexmask.long.byte 0x00 0.--7. 1. " INTID32 ,Interrupt ID32 Priority/Priority Byte Offset 32 " group.long 0x424++0x03 line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" hexmask.long.byte 0x00 24.--31. 1. " INTID39 ,Interrupt ID39 Priority/Priority Byte Offset 39 " hexmask.long.byte 0x00 16.--23. 1. " INTID38 ,Interrupt ID38 Priority/Priority Byte Offset 38 " hexmask.long.byte 0x00 8.--15. 1. " INTID37 ,Interrupt ID37 Priority/Priority Byte Offset 37 " hexmask.long.byte 0x00 0.--7. 1. " INTID36 ,Interrupt ID36 Priority/Priority Byte Offset 36 " group.long 0x428++0x03 line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" hexmask.long.byte 0x00 24.--31. 1. " INTID43 ,Interrupt ID43 Priority/Priority Byte Offset 43 " hexmask.long.byte 0x00 16.--23. 1. " INTID42 ,Interrupt ID42 Priority/Priority Byte Offset 42 " hexmask.long.byte 0x00 8.--15. 1. " INTID41 ,Interrupt ID41 Priority/Priority Byte Offset 41 " hexmask.long.byte 0x00 0.--7. 1. " INTID40 ,Interrupt ID40 Priority/Priority Byte Offset 40 " group.long 0x42C++0x03 line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" hexmask.long.byte 0x00 24.--31. 1. " INTID47 ,Interrupt ID47 Priority/Priority Byte Offset 47 " hexmask.long.byte 0x00 16.--23. 1. " INTID46 ,Interrupt ID46 Priority/Priority Byte Offset 46 " hexmask.long.byte 0x00 8.--15. 1. " INTID45 ,Interrupt ID45 Priority/Priority Byte Offset 45 " hexmask.long.byte 0x00 0.--7. 1. " INTID44 ,Interrupt ID44 Priority/Priority Byte Offset 44 " group.long 0x430++0x03 line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" hexmask.long.byte 0x00 24.--31. 1. " INTID51 ,Interrupt ID51 Priority/Priority Byte Offset 51 " hexmask.long.byte 0x00 16.--23. 1. " INTID50 ,Interrupt ID50 Priority/Priority Byte Offset 50 " hexmask.long.byte 0x00 8.--15. 1. " INTID49 ,Interrupt ID49 Priority/Priority Byte Offset 49 " hexmask.long.byte 0x00 0.--7. 1. " INTID48 ,Interrupt ID48 Priority/Priority Byte Offset 48 " group.long 0x434++0x03 line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" hexmask.long.byte 0x00 24.--31. 1. " INTID55 ,Interrupt ID55 Priority/Priority Byte Offset 55 " hexmask.long.byte 0x00 16.--23. 1. " INTID54 ,Interrupt ID54 Priority/Priority Byte Offset 54 " hexmask.long.byte 0x00 8.--15. 1. " INTID53 ,Interrupt ID53 Priority/Priority Byte Offset 53 " hexmask.long.byte 0x00 0.--7. 1. " INTID52 ,Interrupt ID52 Priority/Priority Byte Offset 52 " group.long 0x438++0x03 line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" hexmask.long.byte 0x00 24.--31. 1. " INTID59 ,Interrupt ID59 Priority/Priority Byte Offset 59 " hexmask.long.byte 0x00 16.--23. 1. " INTID58 ,Interrupt ID58 Priority/Priority Byte Offset 58 " hexmask.long.byte 0x00 8.--15. 1. " INTID57 ,Interrupt ID57 Priority/Priority Byte Offset 57 " hexmask.long.byte 0x00 0.--7. 1. " INTID56 ,Interrupt ID56 Priority/Priority Byte Offset 56 " group.long 0x43C++0x03 line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" hexmask.long.byte 0x00 24.--31. 1. " INTID63 ,Interrupt ID63 Priority/Priority Byte Offset 63 " hexmask.long.byte 0x00 16.--23. 1. " INTID62 ,Interrupt ID62 Priority/Priority Byte Offset 62 " hexmask.long.byte 0x00 8.--15. 1. " INTID61 ,Interrupt ID61 Priority/Priority Byte Offset 61 " hexmask.long.byte 0x00 0.--7. 1. " INTID60 ,Interrupt ID60 Priority/Priority Byte Offset 60 " else hgroup.long 0x420++0x03 hide.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" hgroup.long 0x424++0x03 hide.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" hgroup.long 0x428++0x03 hide.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" hgroup.long 0x42C++0x03 hide.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" hgroup.long 0x430++0x03 hide.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" hgroup.long 0x434++0x03 hide.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" hgroup.long 0x438++0x03 hide.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" hgroup.long 0x43C++0x03 hide.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x440++0x03 line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" hexmask.long.byte 0x00 24.--31. 1. " INTID67 ,Interrupt ID67 Priority/Priority Byte Offset 67 " hexmask.long.byte 0x00 16.--23. 1. " INTID66 ,Interrupt ID66 Priority/Priority Byte Offset 66 " hexmask.long.byte 0x00 8.--15. 1. " INTID65 ,Interrupt ID65 Priority/Priority Byte Offset 65 " hexmask.long.byte 0x00 0.--7. 1. " INTID64 ,Interrupt ID64 Priority/Priority Byte Offset 64 " group.long 0x444++0x03 line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" hexmask.long.byte 0x00 24.--31. 1. " INTID71 ,Interrupt ID71 Priority/Priority Byte Offset 71 " hexmask.long.byte 0x00 16.--23. 1. " INTID70 ,Interrupt ID70 Priority/Priority Byte Offset 70 " hexmask.long.byte 0x00 8.--15. 1. " INTID69 ,Interrupt ID69 Priority/Priority Byte Offset 69 " hexmask.long.byte 0x00 0.--7. 1. " INTID68 ,Interrupt ID68 Priority/Priority Byte Offset 68 " group.long 0x448++0x03 line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" hexmask.long.byte 0x00 24.--31. 1. " INTID75 ,Interrupt ID75 Priority/Priority Byte Offset 75 " hexmask.long.byte 0x00 16.--23. 1. " INTID74 ,Interrupt ID74 Priority/Priority Byte Offset 74 " hexmask.long.byte 0x00 8.--15. 1. " INTID73 ,Interrupt ID73 Priority/Priority Byte Offset 73 " hexmask.long.byte 0x00 0.--7. 1. " INTID72 ,Interrupt ID72 Priority/Priority Byte Offset 72 " group.long 0x44C++0x03 line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" hexmask.long.byte 0x00 24.--31. 1. " INTID79 ,Interrupt ID79 Priority/Priority Byte Offset 79 " hexmask.long.byte 0x00 16.--23. 1. " INTID78 ,Interrupt ID78 Priority/Priority Byte Offset 78 " hexmask.long.byte 0x00 8.--15. 1. " INTID77 ,Interrupt ID77 Priority/Priority Byte Offset 77 " hexmask.long.byte 0x00 0.--7. 1. " INTID76 ,Interrupt ID76 Priority/Priority Byte Offset 76 " group.long 0x450++0x03 line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" hexmask.long.byte 0x00 24.--31. 1. " INTID83 ,Interrupt ID83 Priority/Priority Byte Offset 83 " hexmask.long.byte 0x00 16.--23. 1. " INTID82 ,Interrupt ID82 Priority/Priority Byte Offset 82 " hexmask.long.byte 0x00 8.--15. 1. " INTID81 ,Interrupt ID81 Priority/Priority Byte Offset 81 " hexmask.long.byte 0x00 0.--7. 1. " INTID80 ,Interrupt ID80 Priority/Priority Byte Offset 80 " group.long 0x454++0x03 line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" hexmask.long.byte 0x00 24.--31. 1. " INTID87 ,Interrupt ID87 Priority/Priority Byte Offset 87 " hexmask.long.byte 0x00 16.--23. 1. " INTID86 ,Interrupt ID86 Priority/Priority Byte Offset 86 " hexmask.long.byte 0x00 8.--15. 1. " INTID85 ,Interrupt ID85 Priority/Priority Byte Offset 85 " hexmask.long.byte 0x00 0.--7. 1. " INTID84 ,Interrupt ID84 Priority/Priority Byte Offset 84 " group.long 0x458++0x03 line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" hexmask.long.byte 0x00 24.--31. 1. " INTID91 ,Interrupt ID91 Priority/Priority Byte Offset 91 " hexmask.long.byte 0x00 16.--23. 1. " INTID90 ,Interrupt ID90 Priority/Priority Byte Offset 90 " hexmask.long.byte 0x00 8.--15. 1. " INTID89 ,Interrupt ID89 Priority/Priority Byte Offset 89 " hexmask.long.byte 0x00 0.--7. 1. " INTID88 ,Interrupt ID88 Priority/Priority Byte Offset 88 " group.long 0x45C++0x03 line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" hexmask.long.byte 0x00 24.--31. 1. " INTID95 ,Interrupt ID95 Priority/Priority Byte Offset 95 " hexmask.long.byte 0x00 16.--23. 1. " INTID94 ,Interrupt ID94 Priority/Priority Byte Offset 94 " hexmask.long.byte 0x00 8.--15. 1. " INTID93 ,Interrupt ID93 Priority/Priority Byte Offset 93 " hexmask.long.byte 0x00 0.--7. 1. " INTID92 ,Interrupt ID92 Priority/Priority Byte Offset 92 " else hgroup.long 0x440++0x03 hide.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" hgroup.long 0x444++0x03 hide.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" hgroup.long 0x448++0x03 hide.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" hgroup.long 0x44C++0x03 hide.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" hgroup.long 0x450++0x03 hide.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" hgroup.long 0x454++0x03 hide.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" hgroup.long 0x458++0x03 hide.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" hgroup.long 0x45C++0x03 hide.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x460++0x03 line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" hexmask.long.byte 0x00 24.--31. 1. " INTID99 ,Interrupt ID99 Priority/Priority Byte Offset 99 " hexmask.long.byte 0x00 16.--23. 1. " INTID98 ,Interrupt ID98 Priority/Priority Byte Offset 98 " hexmask.long.byte 0x00 8.--15. 1. " INTID97 ,Interrupt ID97 Priority/Priority Byte Offset 97 " hexmask.long.byte 0x00 0.--7. 1. " INTID96 ,Interrupt ID96 Priority/Priority Byte Offset 96 " group.long 0x464++0x03 line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" hexmask.long.byte 0x00 24.--31. 1. " INTID103 ,Interrupt ID103 Priority/Priority Byte Offset 103 " hexmask.long.byte 0x00 16.--23. 1. " INTID102 ,Interrupt ID102 Priority/Priority Byte Offset 102 " hexmask.long.byte 0x00 8.--15. 1. " INTID101 ,Interrupt ID101 Priority/Priority Byte Offset 101 " hexmask.long.byte 0x00 0.--7. 1. " INTID100 ,Interrupt ID100 Priority/Priority Byte Offset 100 " group.long 0x468++0x03 line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" hexmask.long.byte 0x00 24.--31. 1. " INTID107 ,Interrupt ID107 Priority/Priority Byte Offset 107 " hexmask.long.byte 0x00 16.--23. 1. " INTID106 ,Interrupt ID106 Priority/Priority Byte Offset 106 " hexmask.long.byte 0x00 8.--15. 1. " INTID105 ,Interrupt ID105 Priority/Priority Byte Offset 105 " hexmask.long.byte 0x00 0.--7. 1. " INTID104 ,Interrupt ID104 Priority/Priority Byte Offset 104 " group.long 0x46C++0x03 line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" hexmask.long.byte 0x00 24.--31. 1. " INTID111 ,Interrupt ID111 Priority/Priority Byte Offset 111 " hexmask.long.byte 0x00 16.--23. 1. " INTID110 ,Interrupt ID110 Priority/Priority Byte Offset 110 " hexmask.long.byte 0x00 8.--15. 1. " INTID109 ,Interrupt ID109 Priority/Priority Byte Offset 109 " hexmask.long.byte 0x00 0.--7. 1. " INTID108 ,Interrupt ID108 Priority/Priority Byte Offset 108 " group.long 0x470++0x03 line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" hexmask.long.byte 0x00 24.--31. 1. " INTID115 ,Interrupt ID115 Priority/Priority Byte Offset 115 " hexmask.long.byte 0x00 16.--23. 1. " INTID114 ,Interrupt ID114 Priority/Priority Byte Offset 114 " hexmask.long.byte 0x00 8.--15. 1. " INTID113 ,Interrupt ID113 Priority/Priority Byte Offset 113 " hexmask.long.byte 0x00 0.--7. 1. " INTID112 ,Interrupt ID112 Priority/Priority Byte Offset 112 " group.long 0x474++0x03 line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" hexmask.long.byte 0x00 24.--31. 1. " INTID119 ,Interrupt ID119 Priority/Priority Byte Offset 119 " hexmask.long.byte 0x00 16.--23. 1. " INTID118 ,Interrupt ID118 Priority/Priority Byte Offset 118 " hexmask.long.byte 0x00 8.--15. 1. " INTID117 ,Interrupt ID117 Priority/Priority Byte Offset 117 " hexmask.long.byte 0x00 0.--7. 1. " INTID116 ,Interrupt ID116 Priority/Priority Byte Offset 116 " group.long 0x478++0x03 line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" hexmask.long.byte 0x00 24.--31. 1. " INTID123 ,Interrupt ID123 Priority/Priority Byte Offset 123 " hexmask.long.byte 0x00 16.--23. 1. " INTID122 ,Interrupt ID122 Priority/Priority Byte Offset 122 " hexmask.long.byte 0x00 8.--15. 1. " INTID121 ,Interrupt ID121 Priority/Priority Byte Offset 121 " hexmask.long.byte 0x00 0.--7. 1. " INTID120 ,Interrupt ID120 Priority/Priority Byte Offset 120 " group.long 0x47C++0x03 line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" hexmask.long.byte 0x00 24.--31. 1. " INTID127 ,Interrupt ID127 Priority/Priority Byte Offset 127 " hexmask.long.byte 0x00 16.--23. 1. " INTID126 ,Interrupt ID126 Priority/Priority Byte Offset 126 " hexmask.long.byte 0x00 8.--15. 1. " INTID125 ,Interrupt ID125 Priority/Priority Byte Offset 125 " hexmask.long.byte 0x00 0.--7. 1. " INTID124 ,Interrupt ID124 Priority/Priority Byte Offset 124 " else hgroup.long 0x460++0x03 hide.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" hgroup.long 0x464++0x03 hide.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" hgroup.long 0x468++0x03 hide.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" hgroup.long 0x46C++0x03 hide.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" hgroup.long 0x470++0x03 hide.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" hgroup.long 0x474++0x03 hide.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" hgroup.long 0x478++0x03 hide.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" hgroup.long 0x47C++0x03 hide.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x480++0x03 line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" hexmask.long.byte 0x00 24.--31. 1. " INTID131 ,Interrupt ID131 Priority/Priority Byte Offset 131 " hexmask.long.byte 0x00 16.--23. 1. " INTID130 ,Interrupt ID130 Priority/Priority Byte Offset 130 " hexmask.long.byte 0x00 8.--15. 1. " INTID129 ,Interrupt ID129 Priority/Priority Byte Offset 129 " hexmask.long.byte 0x00 0.--7. 1. " INTID128 ,Interrupt ID128 Priority/Priority Byte Offset 128 " group.long 0x484++0x03 line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" hexmask.long.byte 0x00 24.--31. 1. " INTID135 ,Interrupt ID135 Priority/Priority Byte Offset 135 " hexmask.long.byte 0x00 16.--23. 1. " INTID134 ,Interrupt ID134 Priority/Priority Byte Offset 134 " hexmask.long.byte 0x00 8.--15. 1. " INTID133 ,Interrupt ID133 Priority/Priority Byte Offset 133 " hexmask.long.byte 0x00 0.--7. 1. " INTID132 ,Interrupt ID132 Priority/Priority Byte Offset 132 " group.long 0x488++0x03 line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" hexmask.long.byte 0x00 24.--31. 1. " INTID139 ,Interrupt ID139 Priority/Priority Byte Offset 139 " hexmask.long.byte 0x00 16.--23. 1. " INTID138 ,Interrupt ID138 Priority/Priority Byte Offset 138 " hexmask.long.byte 0x00 8.--15. 1. " INTID137 ,Interrupt ID137 Priority/Priority Byte Offset 137 " hexmask.long.byte 0x00 0.--7. 1. " INTID136 ,Interrupt ID136 Priority/Priority Byte Offset 136 " group.long 0x48C++0x03 line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" hexmask.long.byte 0x00 24.--31. 1. " INTID143 ,Interrupt ID143 Priority/Priority Byte Offset 143 " hexmask.long.byte 0x00 16.--23. 1. " INTID142 ,Interrupt ID142 Priority/Priority Byte Offset 142 " hexmask.long.byte 0x00 8.--15. 1. " INTID141 ,Interrupt ID141 Priority/Priority Byte Offset 141 " hexmask.long.byte 0x00 0.--7. 1. " INTID140 ,Interrupt ID140 Priority/Priority Byte Offset 140 " group.long 0x490++0x03 line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" hexmask.long.byte 0x00 24.--31. 1. " INTID147 ,Interrupt ID147 Priority/Priority Byte Offset 147 " hexmask.long.byte 0x00 16.--23. 1. " INTID146 ,Interrupt ID146 Priority/Priority Byte Offset 146 " hexmask.long.byte 0x00 8.--15. 1. " INTID145 ,Interrupt ID145 Priority/Priority Byte Offset 145 " hexmask.long.byte 0x00 0.--7. 1. " INTID144 ,Interrupt ID144 Priority/Priority Byte Offset 144 " group.long 0x494++0x03 line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" hexmask.long.byte 0x00 24.--31. 1. " INTID151 ,Interrupt ID151 Priority/Priority Byte Offset 151 " hexmask.long.byte 0x00 16.--23. 1. " INTID150 ,Interrupt ID150 Priority/Priority Byte Offset 150 " hexmask.long.byte 0x00 8.--15. 1. " INTID149 ,Interrupt ID149 Priority/Priority Byte Offset 149 " hexmask.long.byte 0x00 0.--7. 1. " INTID148 ,Interrupt ID148 Priority/Priority Byte Offset 148 " group.long 0x498++0x03 line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" hexmask.long.byte 0x00 24.--31. 1. " INTID155 ,Interrupt ID155 Priority/Priority Byte Offset 155 " hexmask.long.byte 0x00 16.--23. 1. " INTID154 ,Interrupt ID154 Priority/Priority Byte Offset 154 " hexmask.long.byte 0x00 8.--15. 1. " INTID153 ,Interrupt ID153 Priority/Priority Byte Offset 153 " hexmask.long.byte 0x00 0.--7. 1. " INTID152 ,Interrupt ID152 Priority/Priority Byte Offset 152 " group.long 0x49C++0x03 line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" hexmask.long.byte 0x00 24.--31. 1. " INTID159 ,Interrupt ID159 Priority/Priority Byte Offset 159 " hexmask.long.byte 0x00 16.--23. 1. " INTID158 ,Interrupt ID158 Priority/Priority Byte Offset 158 " hexmask.long.byte 0x00 8.--15. 1. " INTID157 ,Interrupt ID157 Priority/Priority Byte Offset 157 " hexmask.long.byte 0x00 0.--7. 1. " INTID156 ,Interrupt ID156 Priority/Priority Byte Offset 156 " else hgroup.long 0x480++0x03 hide.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" hgroup.long 0x484++0x03 hide.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" hgroup.long 0x488++0x03 hide.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" hgroup.long 0x48C++0x03 hide.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" hgroup.long 0x490++0x03 hide.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" hgroup.long 0x494++0x03 hide.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" hgroup.long 0x498++0x03 hide.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" hgroup.long 0x49C++0x03 hide.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x4A0++0x03 line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" hexmask.long.byte 0x00 24.--31. 1. " INTID163 ,Interrupt ID163 Priority/Priority Byte Offset 163 " hexmask.long.byte 0x00 16.--23. 1. " INTID162 ,Interrupt ID162 Priority/Priority Byte Offset 162 " hexmask.long.byte 0x00 8.--15. 1. " INTID161 ,Interrupt ID161 Priority/Priority Byte Offset 161 " hexmask.long.byte 0x00 0.--7. 1. " INTID160 ,Interrupt ID160 Priority/Priority Byte Offset 160 " group.long 0x4A4++0x03 line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" hexmask.long.byte 0x00 24.--31. 1. " INTID167 ,Interrupt ID167 Priority/Priority Byte Offset 167 " hexmask.long.byte 0x00 16.--23. 1. " INTID166 ,Interrupt ID166 Priority/Priority Byte Offset 166 " hexmask.long.byte 0x00 8.--15. 1. " INTID165 ,Interrupt ID165 Priority/Priority Byte Offset 165 " hexmask.long.byte 0x00 0.--7. 1. " INTID164 ,Interrupt ID164 Priority/Priority Byte Offset 164 " group.long 0x4A8++0x03 line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" hexmask.long.byte 0x00 24.--31. 1. " INTID171 ,Interrupt ID171 Priority/Priority Byte Offset 171 " hexmask.long.byte 0x00 16.--23. 1. " INTID170 ,Interrupt ID170 Priority/Priority Byte Offset 170 " hexmask.long.byte 0x00 8.--15. 1. " INTID169 ,Interrupt ID169 Priority/Priority Byte Offset 169 " hexmask.long.byte 0x00 0.--7. 1. " INTID168 ,Interrupt ID168 Priority/Priority Byte Offset 168 " group.long 0x4AC++0x03 line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" hexmask.long.byte 0x00 24.--31. 1. " INTID175 ,Interrupt ID175 Priority/Priority Byte Offset 175 " hexmask.long.byte 0x00 16.--23. 1. " INTID174 ,Interrupt ID174 Priority/Priority Byte Offset 174 " hexmask.long.byte 0x00 8.--15. 1. " INTID173 ,Interrupt ID173 Priority/Priority Byte Offset 173 " hexmask.long.byte 0x00 0.--7. 1. " INTID172 ,Interrupt ID172 Priority/Priority Byte Offset 172 " group.long 0x4B0++0x03 line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" hexmask.long.byte 0x00 24.--31. 1. " INTID179 ,Interrupt ID179 Priority/Priority Byte Offset 179 " hexmask.long.byte 0x00 16.--23. 1. " INTID178 ,Interrupt ID178 Priority/Priority Byte Offset 178 " hexmask.long.byte 0x00 8.--15. 1. " INTID177 ,Interrupt ID177 Priority/Priority Byte Offset 177 " hexmask.long.byte 0x00 0.--7. 1. " INTID176 ,Interrupt ID176 Priority/Priority Byte Offset 176 " group.long 0x4B4++0x03 line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" hexmask.long.byte 0x00 24.--31. 1. " INTID183 ,Interrupt ID183 Priority/Priority Byte Offset 183 " hexmask.long.byte 0x00 16.--23. 1. " INTID182 ,Interrupt ID182 Priority/Priority Byte Offset 182 " hexmask.long.byte 0x00 8.--15. 1. " INTID181 ,Interrupt ID181 Priority/Priority Byte Offset 181 " hexmask.long.byte 0x00 0.--7. 1. " INTID180 ,Interrupt ID180 Priority/Priority Byte Offset 180 " group.long 0x4B8++0x03 line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" hexmask.long.byte 0x00 24.--31. 1. " INTID187 ,Interrupt ID187 Priority/Priority Byte Offset 187 " hexmask.long.byte 0x00 16.--23. 1. " INTID186 ,Interrupt ID186 Priority/Priority Byte Offset 186 " hexmask.long.byte 0x00 8.--15. 1. " INTID185 ,Interrupt ID185 Priority/Priority Byte Offset 185 " hexmask.long.byte 0x00 0.--7. 1. " INTID184 ,Interrupt ID184 Priority/Priority Byte Offset 184 " group.long 0x4BC++0x03 line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" hexmask.long.byte 0x00 24.--31. 1. " INTID191 ,Interrupt ID191 Priority/Priority Byte Offset 191 " hexmask.long.byte 0x00 16.--23. 1. " INTID190 ,Interrupt ID190 Priority/Priority Byte Offset 190 " hexmask.long.byte 0x00 8.--15. 1. " INTID189 ,Interrupt ID189 Priority/Priority Byte Offset 189 " hexmask.long.byte 0x00 0.--7. 1. " INTID188 ,Interrupt ID188 Priority/Priority Byte Offset 188 " else hgroup.long 0x4A0++0x03 hide.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" hgroup.long 0x4A4++0x03 hide.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" hgroup.long 0x4A8++0x03 hide.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" hgroup.long 0x4AC++0x03 hide.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" hgroup.long 0x4B0++0x03 hide.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" hgroup.long 0x4B4++0x03 hide.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" hgroup.long 0x4B8++0x03 hide.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" hgroup.long 0x4BC++0x03 hide.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x4C0++0x03 line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" hexmask.long.byte 0x00 24.--31. 1. " INTID195 ,Interrupt ID195 Priority/Priority Byte Offset 195 " hexmask.long.byte 0x00 16.--23. 1. " INTID194 ,Interrupt ID194 Priority/Priority Byte Offset 194 " hexmask.long.byte 0x00 8.--15. 1. " INTID193 ,Interrupt ID193 Priority/Priority Byte Offset 193 " hexmask.long.byte 0x00 0.--7. 1. " INTID192 ,Interrupt ID192 Priority/Priority Byte Offset 192 " group.long 0x4C4++0x03 line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" hexmask.long.byte 0x00 24.--31. 1. " INTID199 ,Interrupt ID199 Priority/Priority Byte Offset 199 " hexmask.long.byte 0x00 16.--23. 1. " INTID198 ,Interrupt ID198 Priority/Priority Byte Offset 198 " hexmask.long.byte 0x00 8.--15. 1. " INTID197 ,Interrupt ID197 Priority/Priority Byte Offset 197 " hexmask.long.byte 0x00 0.--7. 1. " INTID196 ,Interrupt ID196 Priority/Priority Byte Offset 196 " group.long 0x4C8++0x03 line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" hexmask.long.byte 0x00 24.--31. 1. " INTID203 ,Interrupt ID203 Priority/Priority Byte Offset 203 " hexmask.long.byte 0x00 16.--23. 1. " INTID202 ,Interrupt ID202 Priority/Priority Byte Offset 202 " hexmask.long.byte 0x00 8.--15. 1. " INTID201 ,Interrupt ID201 Priority/Priority Byte Offset 201 " hexmask.long.byte 0x00 0.--7. 1. " INTID200 ,Interrupt ID200 Priority/Priority Byte Offset 200 " group.long 0x4CC++0x03 line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" hexmask.long.byte 0x00 24.--31. 1. " INTID207 ,Interrupt ID207 Priority/Priority Byte Offset 207 " hexmask.long.byte 0x00 16.--23. 1. " INTID206 ,Interrupt ID206 Priority/Priority Byte Offset 206 " hexmask.long.byte 0x00 8.--15. 1. " INTID205 ,Interrupt ID205 Priority/Priority Byte Offset 205 " hexmask.long.byte 0x00 0.--7. 1. " INTID204 ,Interrupt ID204 Priority/Priority Byte Offset 204 " group.long 0x4D0++0x03 line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" hexmask.long.byte 0x00 24.--31. 1. " INTID211 ,Interrupt ID211 Priority/Priority Byte Offset 211 " hexmask.long.byte 0x00 16.--23. 1. " INTID210 ,Interrupt ID210 Priority/Priority Byte Offset 210 " hexmask.long.byte 0x00 8.--15. 1. " INTID209 ,Interrupt ID209 Priority/Priority Byte Offset 209 " hexmask.long.byte 0x00 0.--7. 1. " INTID208 ,Interrupt ID208 Priority/Priority Byte Offset 208 " group.long 0x4D4++0x03 line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" hexmask.long.byte 0x00 24.--31. 1. " INTID215 ,Interrupt ID215 Priority/Priority Byte Offset 215 " hexmask.long.byte 0x00 16.--23. 1. " INTID214 ,Interrupt ID214 Priority/Priority Byte Offset 214 " hexmask.long.byte 0x00 8.--15. 1. " INTID213 ,Interrupt ID213 Priority/Priority Byte Offset 213 " hexmask.long.byte 0x00 0.--7. 1. " INTID212 ,Interrupt ID212 Priority/Priority Byte Offset 212 " group.long 0x4D8++0x03 line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" hexmask.long.byte 0x00 24.--31. 1. " INTID219 ,Interrupt ID219 Priority/Priority Byte Offset 219 " hexmask.long.byte 0x00 16.--23. 1. " INTID218 ,Interrupt ID218 Priority/Priority Byte Offset 218 " hexmask.long.byte 0x00 8.--15. 1. " INTID217 ,Interrupt ID217 Priority/Priority Byte Offset 217 " hexmask.long.byte 0x00 0.--7. 1. " INTID216 ,Interrupt ID216 Priority/Priority Byte Offset 216 " group.long 0x4DC++0x03 line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" hexmask.long.byte 0x00 24.--31. 1. " INTID223 ,Interrupt ID223 Priority/Priority Byte Offset 223 " hexmask.long.byte 0x00 16.--23. 1. " INTID222 ,Interrupt ID222 Priority/Priority Byte Offset 222 " hexmask.long.byte 0x00 8.--15. 1. " INTID221 ,Interrupt ID221 Priority/Priority Byte Offset 221 " hexmask.long.byte 0x00 0.--7. 1. " INTID220 ,Interrupt ID220 Priority/Priority Byte Offset 220 " else hgroup.long 0x4C0++0x03 hide.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" hgroup.long 0x4C4++0x03 hide.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" hgroup.long 0x4C8++0x03 hide.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" hgroup.long 0x4CC++0x03 hide.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" hgroup.long 0x4D0++0x03 hide.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" hgroup.long 0x4D4++0x03 hide.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" hgroup.long 0x4D8++0x03 hide.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" hgroup.long 0x4DC++0x03 hide.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x4E0++0x03 line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" hexmask.long.byte 0x00 24.--31. 1. " INTID227 ,Interrupt ID227 Priority/Priority Byte Offset 227 " hexmask.long.byte 0x00 16.--23. 1. " INTID226 ,Interrupt ID226 Priority/Priority Byte Offset 226 " hexmask.long.byte 0x00 8.--15. 1. " INTID225 ,Interrupt ID225 Priority/Priority Byte Offset 225 " hexmask.long.byte 0x00 0.--7. 1. " INTID224 ,Interrupt ID224 Priority/Priority Byte Offset 224 " group.long 0x4E4++0x03 line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" hexmask.long.byte 0x00 24.--31. 1. " INTID231 ,Interrupt ID231 Priority/Priority Byte Offset 231 " hexmask.long.byte 0x00 16.--23. 1. " INTID230 ,Interrupt ID230 Priority/Priority Byte Offset 230 " hexmask.long.byte 0x00 8.--15. 1. " INTID229 ,Interrupt ID229 Priority/Priority Byte Offset 229 " hexmask.long.byte 0x00 0.--7. 1. " INTID228 ,Interrupt ID228 Priority/Priority Byte Offset 228 " group.long 0x4E8++0x03 line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" hexmask.long.byte 0x00 24.--31. 1. " INTID235 ,Interrupt ID235 Priority/Priority Byte Offset 235 " hexmask.long.byte 0x00 16.--23. 1. " INTID234 ,Interrupt ID234 Priority/Priority Byte Offset 234 " hexmask.long.byte 0x00 8.--15. 1. " INTID233 ,Interrupt ID233 Priority/Priority Byte Offset 233 " hexmask.long.byte 0x00 0.--7. 1. " INTID232 ,Interrupt ID232 Priority/Priority Byte Offset 232 " group.long 0x4EC++0x03 line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" hexmask.long.byte 0x00 24.--31. 1. " INTID239 ,Interrupt ID239 Priority/Priority Byte Offset 239 " hexmask.long.byte 0x00 16.--23. 1. " INTID238 ,Interrupt ID238 Priority/Priority Byte Offset 238 " hexmask.long.byte 0x00 8.--15. 1. " INTID237 ,Interrupt ID237 Priority/Priority Byte Offset 237 " hexmask.long.byte 0x00 0.--7. 1. " INTID236 ,Interrupt ID236 Priority/Priority Byte Offset 236 " group.long 0x4F0++0x03 line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" hexmask.long.byte 0x00 24.--31. 1. " INTID243 ,Interrupt ID243 Priority/Priority Byte Offset 243 " hexmask.long.byte 0x00 16.--23. 1. " INTID242 ,Interrupt ID242 Priority/Priority Byte Offset 242 " hexmask.long.byte 0x00 8.--15. 1. " INTID241 ,Interrupt ID241 Priority/Priority Byte Offset 241 " hexmask.long.byte 0x00 0.--7. 1. " INTID240 ,Interrupt ID240 Priority/Priority Byte Offset 240 " group.long 0x4F4++0x03 line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" hexmask.long.byte 0x00 24.--31. 1. " INTID247 ,Interrupt ID247 Priority/Priority Byte Offset 247 " hexmask.long.byte 0x00 16.--23. 1. " INTID246 ,Interrupt ID246 Priority/Priority Byte Offset 246 " hexmask.long.byte 0x00 8.--15. 1. " INTID245 ,Interrupt ID245 Priority/Priority Byte Offset 245 " hexmask.long.byte 0x00 0.--7. 1. " INTID244 ,Interrupt ID244 Priority/Priority Byte Offset 244 " group.long 0x4F8++0x03 line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" hexmask.long.byte 0x00 24.--31. 1. " INTID251 ,Interrupt ID251 Priority/Priority Byte Offset 251 " hexmask.long.byte 0x00 16.--23. 1. " INTID250 ,Interrupt ID250 Priority/Priority Byte Offset 250 " hexmask.long.byte 0x00 8.--15. 1. " INTID249 ,Interrupt ID249 Priority/Priority Byte Offset 249 " hexmask.long.byte 0x00 0.--7. 1. " INTID248 ,Interrupt ID248 Priority/Priority Byte Offset 248 " group.long 0x4FC++0x03 line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" hexmask.long.byte 0x00 24.--31. 1. " INTID255 ,Interrupt ID255 Priority/Priority Byte Offset 255 " hexmask.long.byte 0x00 16.--23. 1. " INTID254 ,Interrupt ID254 Priority/Priority Byte Offset 254 " hexmask.long.byte 0x00 8.--15. 1. " INTID253 ,Interrupt ID253 Priority/Priority Byte Offset 253 " hexmask.long.byte 0x00 0.--7. 1. " INTID252 ,Interrupt ID252 Priority/Priority Byte Offset 252 " else hgroup.long 0x4E0++0x03 hide.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" hgroup.long 0x4E4++0x03 hide.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" hgroup.long 0x4E8++0x03 hide.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" hgroup.long 0x4EC++0x03 hide.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" hgroup.long 0x4F0++0x03 hide.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" hgroup.long 0x4F4++0x03 hide.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" hgroup.long 0x4F8++0x03 hide.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" hgroup.long 0x4FC++0x03 hide.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x500++0x03 line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" hexmask.long.byte 0x00 24.--31. 1. " INTID259 ,Interrupt ID259 Priority/Priority Byte Offset 259 " hexmask.long.byte 0x00 16.--23. 1. " INTID258 ,Interrupt ID258 Priority/Priority Byte Offset 258 " hexmask.long.byte 0x00 8.--15. 1. " INTID257 ,Interrupt ID257 Priority/Priority Byte Offset 257 " hexmask.long.byte 0x00 0.--7. 1. " INTID256 ,Interrupt ID256 Priority/Priority Byte Offset 256 " group.long 0x504++0x03 line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" hexmask.long.byte 0x00 24.--31. 1. " INTID263 ,Interrupt ID263 Priority/Priority Byte Offset 263 " hexmask.long.byte 0x00 16.--23. 1. " INTID262 ,Interrupt ID262 Priority/Priority Byte Offset 262 " hexmask.long.byte 0x00 8.--15. 1. " INTID261 ,Interrupt ID261 Priority/Priority Byte Offset 261 " hexmask.long.byte 0x00 0.--7. 1. " INTID260 ,Interrupt ID260 Priority/Priority Byte Offset 260 " group.long 0x508++0x03 line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" hexmask.long.byte 0x00 24.--31. 1. " INTID267 ,Interrupt ID267 Priority/Priority Byte Offset 267 " hexmask.long.byte 0x00 16.--23. 1. " INTID266 ,Interrupt ID266 Priority/Priority Byte Offset 266 " hexmask.long.byte 0x00 8.--15. 1. " INTID265 ,Interrupt ID265 Priority/Priority Byte Offset 265 " hexmask.long.byte 0x00 0.--7. 1. " INTID264 ,Interrupt ID264 Priority/Priority Byte Offset 264 " group.long 0x50C++0x03 line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" hexmask.long.byte 0x00 24.--31. 1. " INTID271 ,Interrupt ID271 Priority/Priority Byte Offset 271 " hexmask.long.byte 0x00 16.--23. 1. " INTID270 ,Interrupt ID270 Priority/Priority Byte Offset 270 " hexmask.long.byte 0x00 8.--15. 1. " INTID269 ,Interrupt ID269 Priority/Priority Byte Offset 269 " hexmask.long.byte 0x00 0.--7. 1. " INTID268 ,Interrupt ID268 Priority/Priority Byte Offset 268 " group.long 0x510++0x03 line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" hexmask.long.byte 0x00 24.--31. 1. " INTID275 ,Interrupt ID275 Priority/Priority Byte Offset 275 " hexmask.long.byte 0x00 16.--23. 1. " INTID274 ,Interrupt ID274 Priority/Priority Byte Offset 274 " hexmask.long.byte 0x00 8.--15. 1. " INTID273 ,Interrupt ID273 Priority/Priority Byte Offset 273 " hexmask.long.byte 0x00 0.--7. 1. " INTID272 ,Interrupt ID272 Priority/Priority Byte Offset 272 " group.long 0x514++0x03 line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" hexmask.long.byte 0x00 24.--31. 1. " INTID279 ,Interrupt ID279 Priority/Priority Byte Offset 279 " hexmask.long.byte 0x00 16.--23. 1. " INTID278 ,Interrupt ID278 Priority/Priority Byte Offset 278 " hexmask.long.byte 0x00 8.--15. 1. " INTID277 ,Interrupt ID277 Priority/Priority Byte Offset 277 " hexmask.long.byte 0x00 0.--7. 1. " INTID276 ,Interrupt ID276 Priority/Priority Byte Offset 276 " group.long 0x518++0x03 line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" hexmask.long.byte 0x00 24.--31. 1. " INTID283 ,Interrupt ID283 Priority/Priority Byte Offset 283 " hexmask.long.byte 0x00 16.--23. 1. " INTID282 ,Interrupt ID282 Priority/Priority Byte Offset 282 " hexmask.long.byte 0x00 8.--15. 1. " INTID281 ,Interrupt ID281 Priority/Priority Byte Offset 281 " hexmask.long.byte 0x00 0.--7. 1. " INTID280 ,Interrupt ID280 Priority/Priority Byte Offset 280 " group.long 0x51C++0x03 line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" hexmask.long.byte 0x00 24.--31. 1. " INTID287 ,Interrupt ID287 Priority/Priority Byte Offset 287 " hexmask.long.byte 0x00 16.--23. 1. " INTID286 ,Interrupt ID286 Priority/Priority Byte Offset 286 " hexmask.long.byte 0x00 8.--15. 1. " INTID285 ,Interrupt ID285 Priority/Priority Byte Offset 285 " hexmask.long.byte 0x00 0.--7. 1. " INTID284 ,Interrupt ID284 Priority/Priority Byte Offset 284 " else hgroup.long 0x500++0x03 hide.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" hgroup.long 0x504++0x03 hide.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" hgroup.long 0x508++0x03 hide.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" hgroup.long 0x50C++0x03 hide.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" hgroup.long 0x510++0x03 hide.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" hgroup.long 0x514++0x03 hide.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" hgroup.long 0x518++0x03 hide.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" hgroup.long 0x51C++0x03 hide.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x520++0x03 line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" hexmask.long.byte 0x00 24.--31. 1. " INTID291 ,Interrupt ID291 Priority/Priority Byte Offset 291 " hexmask.long.byte 0x00 16.--23. 1. " INTID290 ,Interrupt ID290 Priority/Priority Byte Offset 290 " hexmask.long.byte 0x00 8.--15. 1. " INTID289 ,Interrupt ID289 Priority/Priority Byte Offset 289 " hexmask.long.byte 0x00 0.--7. 1. " INTID288 ,Interrupt ID288 Priority/Priority Byte Offset 288 " group.long 0x524++0x03 line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" hexmask.long.byte 0x00 24.--31. 1. " INTID295 ,Interrupt ID295 Priority/Priority Byte Offset 295 " hexmask.long.byte 0x00 16.--23. 1. " INTID294 ,Interrupt ID294 Priority/Priority Byte Offset 294 " hexmask.long.byte 0x00 8.--15. 1. " INTID293 ,Interrupt ID293 Priority/Priority Byte Offset 293 " hexmask.long.byte 0x00 0.--7. 1. " INTID292 ,Interrupt ID292 Priority/Priority Byte Offset 292 " group.long 0x528++0x03 line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" hexmask.long.byte 0x00 24.--31. 1. " INTID299 ,Interrupt ID299 Priority/Priority Byte Offset 299 " hexmask.long.byte 0x00 16.--23. 1. " INTID298 ,Interrupt ID298 Priority/Priority Byte Offset 298 " hexmask.long.byte 0x00 8.--15. 1. " INTID297 ,Interrupt ID297 Priority/Priority Byte Offset 297 " hexmask.long.byte 0x00 0.--7. 1. " INTID296 ,Interrupt ID296 Priority/Priority Byte Offset 296 " group.long 0x52C++0x03 line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" hexmask.long.byte 0x00 24.--31. 1. " INTID303 ,Interrupt ID303 Priority/Priority Byte Offset 303 " hexmask.long.byte 0x00 16.--23. 1. " INTID302 ,Interrupt ID302 Priority/Priority Byte Offset 302 " hexmask.long.byte 0x00 8.--15. 1. " INTID301 ,Interrupt ID301 Priority/Priority Byte Offset 301 " hexmask.long.byte 0x00 0.--7. 1. " INTID300 ,Interrupt ID300 Priority/Priority Byte Offset 300 " group.long 0x530++0x03 line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" hexmask.long.byte 0x00 24.--31. 1. " INTID307 ,Interrupt ID307 Priority/Priority Byte Offset 307 " hexmask.long.byte 0x00 16.--23. 1. " INTID306 ,Interrupt ID306 Priority/Priority Byte Offset 306 " hexmask.long.byte 0x00 8.--15. 1. " INTID305 ,Interrupt ID305 Priority/Priority Byte Offset 305 " hexmask.long.byte 0x00 0.--7. 1. " INTID304 ,Interrupt ID304 Priority/Priority Byte Offset 304 " group.long 0x534++0x03 line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" hexmask.long.byte 0x00 24.--31. 1. " INTID311 ,Interrupt ID311 Priority/Priority Byte Offset 311 " hexmask.long.byte 0x00 16.--23. 1. " INTID310 ,Interrupt ID310 Priority/Priority Byte Offset 310 " hexmask.long.byte 0x00 8.--15. 1. " INTID309 ,Interrupt ID309 Priority/Priority Byte Offset 309 " hexmask.long.byte 0x00 0.--7. 1. " INTID308 ,Interrupt ID308 Priority/Priority Byte Offset 308 " group.long 0x538++0x03 line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" hexmask.long.byte 0x00 24.--31. 1. " INTID315 ,Interrupt ID315 Priority/Priority Byte Offset 315 " hexmask.long.byte 0x00 16.--23. 1. " INTID314 ,Interrupt ID314 Priority/Priority Byte Offset 314 " hexmask.long.byte 0x00 8.--15. 1. " INTID313 ,Interrupt ID313 Priority/Priority Byte Offset 313 " hexmask.long.byte 0x00 0.--7. 1. " INTID312 ,Interrupt ID312 Priority/Priority Byte Offset 312 " group.long 0x53C++0x03 line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" hexmask.long.byte 0x00 24.--31. 1. " INTID319 ,Interrupt ID319 Priority/Priority Byte Offset 319 " hexmask.long.byte 0x00 16.--23. 1. " INTID318 ,Interrupt ID318 Priority/Priority Byte Offset 318 " hexmask.long.byte 0x00 8.--15. 1. " INTID317 ,Interrupt ID317 Priority/Priority Byte Offset 317 " hexmask.long.byte 0x00 0.--7. 1. " INTID316 ,Interrupt ID316 Priority/Priority Byte Offset 316 " else hgroup.long 0x520++0x03 hide.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" hgroup.long 0x524++0x03 hide.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" hgroup.long 0x528++0x03 hide.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" hgroup.long 0x52C++0x03 hide.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" hgroup.long 0x530++0x03 hide.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" hgroup.long 0x534++0x03 hide.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" hgroup.long 0x538++0x03 hide.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" hgroup.long 0x53C++0x03 hide.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x540++0x03 line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" hexmask.long.byte 0x00 24.--31. 1. " INTID323 ,Interrupt ID323 Priority/Priority Byte Offset 323 " hexmask.long.byte 0x00 16.--23. 1. " INTID322 ,Interrupt ID322 Priority/Priority Byte Offset 322 " hexmask.long.byte 0x00 8.--15. 1. " INTID321 ,Interrupt ID321 Priority/Priority Byte Offset 321 " hexmask.long.byte 0x00 0.--7. 1. " INTID320 ,Interrupt ID320 Priority/Priority Byte Offset 320 " group.long 0x544++0x03 line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" hexmask.long.byte 0x00 24.--31. 1. " INTID327 ,Interrupt ID327 Priority/Priority Byte Offset 327 " hexmask.long.byte 0x00 16.--23. 1. " INTID326 ,Interrupt ID326 Priority/Priority Byte Offset 326 " hexmask.long.byte 0x00 8.--15. 1. " INTID325 ,Interrupt ID325 Priority/Priority Byte Offset 325 " hexmask.long.byte 0x00 0.--7. 1. " INTID324 ,Interrupt ID324 Priority/Priority Byte Offset 324 " group.long 0x548++0x03 line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" hexmask.long.byte 0x00 24.--31. 1. " INTID331 ,Interrupt ID331 Priority/Priority Byte Offset 331 " hexmask.long.byte 0x00 16.--23. 1. " INTID330 ,Interrupt ID330 Priority/Priority Byte Offset 330 " hexmask.long.byte 0x00 8.--15. 1. " INTID329 ,Interrupt ID329 Priority/Priority Byte Offset 329 " hexmask.long.byte 0x00 0.--7. 1. " INTID328 ,Interrupt ID328 Priority/Priority Byte Offset 328 " group.long 0x54C++0x03 line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" hexmask.long.byte 0x00 24.--31. 1. " INTID335 ,Interrupt ID335 Priority/Priority Byte Offset 335 " hexmask.long.byte 0x00 16.--23. 1. " INTID334 ,Interrupt ID334 Priority/Priority Byte Offset 334 " hexmask.long.byte 0x00 8.--15. 1. " INTID333 ,Interrupt ID333 Priority/Priority Byte Offset 333 " hexmask.long.byte 0x00 0.--7. 1. " INTID332 ,Interrupt ID332 Priority/Priority Byte Offset 332 " group.long 0x550++0x03 line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" hexmask.long.byte 0x00 24.--31. 1. " INTID339 ,Interrupt ID339 Priority/Priority Byte Offset 339 " hexmask.long.byte 0x00 16.--23. 1. " INTID338 ,Interrupt ID338 Priority/Priority Byte Offset 338 " hexmask.long.byte 0x00 8.--15. 1. " INTID337 ,Interrupt ID337 Priority/Priority Byte Offset 337 " hexmask.long.byte 0x00 0.--7. 1. " INTID336 ,Interrupt ID336 Priority/Priority Byte Offset 336 " group.long 0x554++0x03 line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" hexmask.long.byte 0x00 24.--31. 1. " INTID343 ,Interrupt ID343 Priority/Priority Byte Offset 343 " hexmask.long.byte 0x00 16.--23. 1. " INTID342 ,Interrupt ID342 Priority/Priority Byte Offset 342 " hexmask.long.byte 0x00 8.--15. 1. " INTID341 ,Interrupt ID341 Priority/Priority Byte Offset 341 " hexmask.long.byte 0x00 0.--7. 1. " INTID340 ,Interrupt ID340 Priority/Priority Byte Offset 340 " group.long 0x558++0x03 line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" hexmask.long.byte 0x00 24.--31. 1. " INTID347 ,Interrupt ID347 Priority/Priority Byte Offset 347 " hexmask.long.byte 0x00 16.--23. 1. " INTID346 ,Interrupt ID346 Priority/Priority Byte Offset 346 " hexmask.long.byte 0x00 8.--15. 1. " INTID345 ,Interrupt ID345 Priority/Priority Byte Offset 345 " hexmask.long.byte 0x00 0.--7. 1. " INTID344 ,Interrupt ID344 Priority/Priority Byte Offset 344 " group.long 0x55C++0x03 line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" hexmask.long.byte 0x00 24.--31. 1. " INTID351 ,Interrupt ID351 Priority/Priority Byte Offset 351 " hexmask.long.byte 0x00 16.--23. 1. " INTID350 ,Interrupt ID350 Priority/Priority Byte Offset 350 " hexmask.long.byte 0x00 8.--15. 1. " INTID349 ,Interrupt ID349 Priority/Priority Byte Offset 349 " hexmask.long.byte 0x00 0.--7. 1. " INTID348 ,Interrupt ID348 Priority/Priority Byte Offset 348 " else hgroup.long 0x540++0x03 hide.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" hgroup.long 0x544++0x03 hide.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" hgroup.long 0x548++0x03 hide.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" hgroup.long 0x54C++0x03 hide.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" hgroup.long 0x550++0x03 hide.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" hgroup.long 0x554++0x03 hide.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" hgroup.long 0x558++0x03 hide.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" hgroup.long 0x55C++0x03 hide.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x560++0x03 line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" hexmask.long.byte 0x00 24.--31. 1. " INTID355 ,Interrupt ID355 Priority/Priority Byte Offset 355 " hexmask.long.byte 0x00 16.--23. 1. " INTID354 ,Interrupt ID354 Priority/Priority Byte Offset 354 " hexmask.long.byte 0x00 8.--15. 1. " INTID353 ,Interrupt ID353 Priority/Priority Byte Offset 353 " hexmask.long.byte 0x00 0.--7. 1. " INTID352 ,Interrupt ID352 Priority/Priority Byte Offset 352 " group.long 0x564++0x03 line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" hexmask.long.byte 0x00 24.--31. 1. " INTID359 ,Interrupt ID359 Priority/Priority Byte Offset 359 " hexmask.long.byte 0x00 16.--23. 1. " INTID358 ,Interrupt ID358 Priority/Priority Byte Offset 358 " hexmask.long.byte 0x00 8.--15. 1. " INTID357 ,Interrupt ID357 Priority/Priority Byte Offset 357 " hexmask.long.byte 0x00 0.--7. 1. " INTID356 ,Interrupt ID356 Priority/Priority Byte Offset 356 " group.long 0x568++0x03 line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" hexmask.long.byte 0x00 24.--31. 1. " INTID363 ,Interrupt ID363 Priority/Priority Byte Offset 363 " hexmask.long.byte 0x00 16.--23. 1. " INTID362 ,Interrupt ID362 Priority/Priority Byte Offset 362 " hexmask.long.byte 0x00 8.--15. 1. " INTID361 ,Interrupt ID361 Priority/Priority Byte Offset 361 " hexmask.long.byte 0x00 0.--7. 1. " INTID360 ,Interrupt ID360 Priority/Priority Byte Offset 360 " group.long 0x56C++0x03 line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" hexmask.long.byte 0x00 24.--31. 1. " INTID367 ,Interrupt ID367 Priority/Priority Byte Offset 367 " hexmask.long.byte 0x00 16.--23. 1. " INTID366 ,Interrupt ID366 Priority/Priority Byte Offset 366 " hexmask.long.byte 0x00 8.--15. 1. " INTID365 ,Interrupt ID365 Priority/Priority Byte Offset 365 " hexmask.long.byte 0x00 0.--7. 1. " INTID364 ,Interrupt ID364 Priority/Priority Byte Offset 364 " group.long 0x570++0x03 line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" hexmask.long.byte 0x00 24.--31. 1. " INTID371 ,Interrupt ID371 Priority/Priority Byte Offset 371 " hexmask.long.byte 0x00 16.--23. 1. " INTID370 ,Interrupt ID370 Priority/Priority Byte Offset 370 " hexmask.long.byte 0x00 8.--15. 1. " INTID369 ,Interrupt ID369 Priority/Priority Byte Offset 369 " hexmask.long.byte 0x00 0.--7. 1. " INTID368 ,Interrupt ID368 Priority/Priority Byte Offset 368 " group.long 0x574++0x03 line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" hexmask.long.byte 0x00 24.--31. 1. " INTID375 ,Interrupt ID375 Priority/Priority Byte Offset 375 " hexmask.long.byte 0x00 16.--23. 1. " INTID374 ,Interrupt ID374 Priority/Priority Byte Offset 374 " hexmask.long.byte 0x00 8.--15. 1. " INTID373 ,Interrupt ID373 Priority/Priority Byte Offset 373 " hexmask.long.byte 0x00 0.--7. 1. " INTID372 ,Interrupt ID372 Priority/Priority Byte Offset 372 " group.long 0x578++0x03 line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" hexmask.long.byte 0x00 24.--31. 1. " INTID379 ,Interrupt ID379 Priority/Priority Byte Offset 379 " hexmask.long.byte 0x00 16.--23. 1. " INTID378 ,Interrupt ID378 Priority/Priority Byte Offset 378 " hexmask.long.byte 0x00 8.--15. 1. " INTID377 ,Interrupt ID377 Priority/Priority Byte Offset 377 " hexmask.long.byte 0x00 0.--7. 1. " INTID376 ,Interrupt ID376 Priority/Priority Byte Offset 376 " group.long 0x57C++0x03 line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" hexmask.long.byte 0x00 24.--31. 1. " INTID383 ,Interrupt ID383 Priority/Priority Byte Offset 383 " hexmask.long.byte 0x00 16.--23. 1. " INTID382 ,Interrupt ID382 Priority/Priority Byte Offset 382 " hexmask.long.byte 0x00 8.--15. 1. " INTID381 ,Interrupt ID381 Priority/Priority Byte Offset 381 " hexmask.long.byte 0x00 0.--7. 1. " INTID380 ,Interrupt ID380 Priority/Priority Byte Offset 380 " else hgroup.long 0x560++0x03 hide.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" hgroup.long 0x564++0x03 hide.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" hgroup.long 0x568++0x03 hide.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" hgroup.long 0x56C++0x03 hide.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" hgroup.long 0x570++0x03 hide.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" hgroup.long 0x574++0x03 hide.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" hgroup.long 0x578++0x03 hide.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" hgroup.long 0x57C++0x03 hide.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x580++0x03 line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" hexmask.long.byte 0x00 24.--31. 1. " INTID387 ,Interrupt ID387 Priority/Priority Byte Offset 387 " hexmask.long.byte 0x00 16.--23. 1. " INTID386 ,Interrupt ID386 Priority/Priority Byte Offset 386 " hexmask.long.byte 0x00 8.--15. 1. " INTID385 ,Interrupt ID385 Priority/Priority Byte Offset 385 " hexmask.long.byte 0x00 0.--7. 1. " INTID384 ,Interrupt ID384 Priority/Priority Byte Offset 384 " group.long 0x584++0x03 line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" hexmask.long.byte 0x00 24.--31. 1. " INTID391 ,Interrupt ID391 Priority/Priority Byte Offset 391 " hexmask.long.byte 0x00 16.--23. 1. " INTID390 ,Interrupt ID390 Priority/Priority Byte Offset 390 " hexmask.long.byte 0x00 8.--15. 1. " INTID389 ,Interrupt ID389 Priority/Priority Byte Offset 389 " hexmask.long.byte 0x00 0.--7. 1. " INTID388 ,Interrupt ID388 Priority/Priority Byte Offset 388 " group.long 0x588++0x03 line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" hexmask.long.byte 0x00 24.--31. 1. " INTID395 ,Interrupt ID395 Priority/Priority Byte Offset 395 " hexmask.long.byte 0x00 16.--23. 1. " INTID394 ,Interrupt ID394 Priority/Priority Byte Offset 394 " hexmask.long.byte 0x00 8.--15. 1. " INTID393 ,Interrupt ID393 Priority/Priority Byte Offset 393 " hexmask.long.byte 0x00 0.--7. 1. " INTID392 ,Interrupt ID392 Priority/Priority Byte Offset 392 " group.long 0x58C++0x03 line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" hexmask.long.byte 0x00 24.--31. 1. " INTID399 ,Interrupt ID399 Priority/Priority Byte Offset 399 " hexmask.long.byte 0x00 16.--23. 1. " INTID398 ,Interrupt ID398 Priority/Priority Byte Offset 398 " hexmask.long.byte 0x00 8.--15. 1. " INTID397 ,Interrupt ID397 Priority/Priority Byte Offset 397 " hexmask.long.byte 0x00 0.--7. 1. " INTID396 ,Interrupt ID396 Priority/Priority Byte Offset 396 " group.long 0x590++0x03 line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" hexmask.long.byte 0x00 24.--31. 1. " INTID403 ,Interrupt ID403 Priority/Priority Byte Offset 403 " hexmask.long.byte 0x00 16.--23. 1. " INTID402 ,Interrupt ID402 Priority/Priority Byte Offset 402 " hexmask.long.byte 0x00 8.--15. 1. " INTID401 ,Interrupt ID401 Priority/Priority Byte Offset 401 " hexmask.long.byte 0x00 0.--7. 1. " INTID400 ,Interrupt ID400 Priority/Priority Byte Offset 400 " group.long 0x594++0x03 line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" hexmask.long.byte 0x00 24.--31. 1. " INTID407 ,Interrupt ID407 Priority/Priority Byte Offset 407 " hexmask.long.byte 0x00 16.--23. 1. " INTID406 ,Interrupt ID406 Priority/Priority Byte Offset 406 " hexmask.long.byte 0x00 8.--15. 1. " INTID405 ,Interrupt ID405 Priority/Priority Byte Offset 405 " hexmask.long.byte 0x00 0.--7. 1. " INTID404 ,Interrupt ID404 Priority/Priority Byte Offset 404 " group.long 0x598++0x03 line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" hexmask.long.byte 0x00 24.--31. 1. " INTID411 ,Interrupt ID411 Priority/Priority Byte Offset 411 " hexmask.long.byte 0x00 16.--23. 1. " INTID410 ,Interrupt ID410 Priority/Priority Byte Offset 410 " hexmask.long.byte 0x00 8.--15. 1. " INTID409 ,Interrupt ID409 Priority/Priority Byte Offset 409 " hexmask.long.byte 0x00 0.--7. 1. " INTID408 ,Interrupt ID408 Priority/Priority Byte Offset 408 " group.long 0x59C++0x03 line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" hexmask.long.byte 0x00 24.--31. 1. " INTID415 ,Interrupt ID415 Priority/Priority Byte Offset 415 " hexmask.long.byte 0x00 16.--23. 1. " INTID414 ,Interrupt ID414 Priority/Priority Byte Offset 414 " hexmask.long.byte 0x00 8.--15. 1. " INTID413 ,Interrupt ID413 Priority/Priority Byte Offset 413 " hexmask.long.byte 0x00 0.--7. 1. " INTID412 ,Interrupt ID412 Priority/Priority Byte Offset 412 " else hgroup.long 0x580++0x03 hide.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" hgroup.long 0x584++0x03 hide.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" hgroup.long 0x588++0x03 hide.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" hgroup.long 0x58C++0x03 hide.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" hgroup.long 0x590++0x03 hide.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" hgroup.long 0x594++0x03 hide.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" hgroup.long 0x598++0x03 hide.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" hgroup.long 0x59C++0x03 hide.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x5A0++0x03 line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" hexmask.long.byte 0x00 24.--31. 1. " INTID419 ,Interrupt ID419 Priority/Priority Byte Offset 419 " hexmask.long.byte 0x00 16.--23. 1. " INTID418 ,Interrupt ID418 Priority/Priority Byte Offset 418 " hexmask.long.byte 0x00 8.--15. 1. " INTID417 ,Interrupt ID417 Priority/Priority Byte Offset 417 " hexmask.long.byte 0x00 0.--7. 1. " INTID416 ,Interrupt ID416 Priority/Priority Byte Offset 416 " group.long 0x5A4++0x03 line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" hexmask.long.byte 0x00 24.--31. 1. " INTID423 ,Interrupt ID423 Priority/Priority Byte Offset 423 " hexmask.long.byte 0x00 16.--23. 1. " INTID422 ,Interrupt ID422 Priority/Priority Byte Offset 422 " hexmask.long.byte 0x00 8.--15. 1. " INTID421 ,Interrupt ID421 Priority/Priority Byte Offset 421 " hexmask.long.byte 0x00 0.--7. 1. " INTID420 ,Interrupt ID420 Priority/Priority Byte Offset 420 " group.long 0x5A8++0x03 line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" hexmask.long.byte 0x00 24.--31. 1. " INTID427 ,Interrupt ID427 Priority/Priority Byte Offset 427 " hexmask.long.byte 0x00 16.--23. 1. " INTID426 ,Interrupt ID426 Priority/Priority Byte Offset 426 " hexmask.long.byte 0x00 8.--15. 1. " INTID425 ,Interrupt ID425 Priority/Priority Byte Offset 425 " hexmask.long.byte 0x00 0.--7. 1. " INTID424 ,Interrupt ID424 Priority/Priority Byte Offset 424 " group.long 0x5AC++0x03 line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" hexmask.long.byte 0x00 24.--31. 1. " INTID431 ,Interrupt ID431 Priority/Priority Byte Offset 431 " hexmask.long.byte 0x00 16.--23. 1. " INTID430 ,Interrupt ID430 Priority/Priority Byte Offset 430 " hexmask.long.byte 0x00 8.--15. 1. " INTID429 ,Interrupt ID429 Priority/Priority Byte Offset 429 " hexmask.long.byte 0x00 0.--7. 1. " INTID428 ,Interrupt ID428 Priority/Priority Byte Offset 428 " group.long 0x5B0++0x03 line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" hexmask.long.byte 0x00 24.--31. 1. " INTID435 ,Interrupt ID435 Priority/Priority Byte Offset 435 " hexmask.long.byte 0x00 16.--23. 1. " INTID434 ,Interrupt ID434 Priority/Priority Byte Offset 434 " hexmask.long.byte 0x00 8.--15. 1. " INTID433 ,Interrupt ID433 Priority/Priority Byte Offset 433 " hexmask.long.byte 0x00 0.--7. 1. " INTID432 ,Interrupt ID432 Priority/Priority Byte Offset 432 " group.long 0x5B4++0x03 line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" hexmask.long.byte 0x00 24.--31. 1. " INTID439 ,Interrupt ID439 Priority/Priority Byte Offset 439 " hexmask.long.byte 0x00 16.--23. 1. " INTID438 ,Interrupt ID438 Priority/Priority Byte Offset 438 " hexmask.long.byte 0x00 8.--15. 1. " INTID437 ,Interrupt ID437 Priority/Priority Byte Offset 437 " hexmask.long.byte 0x00 0.--7. 1. " INTID436 ,Interrupt ID436 Priority/Priority Byte Offset 436 " group.long 0x5B8++0x03 line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" hexmask.long.byte 0x00 24.--31. 1. " INTID443 ,Interrupt ID443 Priority/Priority Byte Offset 443 " hexmask.long.byte 0x00 16.--23. 1. " INTID442 ,Interrupt ID442 Priority/Priority Byte Offset 442 " hexmask.long.byte 0x00 8.--15. 1. " INTID441 ,Interrupt ID441 Priority/Priority Byte Offset 441 " hexmask.long.byte 0x00 0.--7. 1. " INTID440 ,Interrupt ID440 Priority/Priority Byte Offset 440 " group.long 0x5BC++0x03 line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" hexmask.long.byte 0x00 24.--31. 1. " INTID447 ,Interrupt ID447 Priority/Priority Byte Offset 447 " hexmask.long.byte 0x00 16.--23. 1. " INTID446 ,Interrupt ID446 Priority/Priority Byte Offset 446 " hexmask.long.byte 0x00 8.--15. 1. " INTID445 ,Interrupt ID445 Priority/Priority Byte Offset 445 " hexmask.long.byte 0x00 0.--7. 1. " INTID444 ,Interrupt ID444 Priority/Priority Byte Offset 444 " else hgroup.long 0x5A0++0x03 hide.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" hgroup.long 0x5A4++0x03 hide.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" hgroup.long 0x5A8++0x03 hide.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" hgroup.long 0x5AC++0x03 hide.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" hgroup.long 0x5B0++0x03 hide.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" hgroup.long 0x5B4++0x03 hide.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" hgroup.long 0x5B8++0x03 hide.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" hgroup.long 0x5BC++0x03 hide.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x5C0++0x03 line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" hexmask.long.byte 0x00 24.--31. 1. " INTID451 ,Interrupt ID451 Priority/Priority Byte Offset 451 " hexmask.long.byte 0x00 16.--23. 1. " INTID450 ,Interrupt ID450 Priority/Priority Byte Offset 450 " hexmask.long.byte 0x00 8.--15. 1. " INTID449 ,Interrupt ID449 Priority/Priority Byte Offset 449 " hexmask.long.byte 0x00 0.--7. 1. " INTID448 ,Interrupt ID448 Priority/Priority Byte Offset 448 " group.long 0x5C4++0x03 line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" hexmask.long.byte 0x00 24.--31. 1. " INTID455 ,Interrupt ID455 Priority/Priority Byte Offset 455 " hexmask.long.byte 0x00 16.--23. 1. " INTID454 ,Interrupt ID454 Priority/Priority Byte Offset 454 " hexmask.long.byte 0x00 8.--15. 1. " INTID453 ,Interrupt ID453 Priority/Priority Byte Offset 453 " hexmask.long.byte 0x00 0.--7. 1. " INTID452 ,Interrupt ID452 Priority/Priority Byte Offset 452 " group.long 0x5C8++0x03 line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" hexmask.long.byte 0x00 24.--31. 1. " INTID459 ,Interrupt ID459 Priority/Priority Byte Offset 459 " hexmask.long.byte 0x00 16.--23. 1. " INTID458 ,Interrupt ID458 Priority/Priority Byte Offset 458 " hexmask.long.byte 0x00 8.--15. 1. " INTID457 ,Interrupt ID457 Priority/Priority Byte Offset 457 " hexmask.long.byte 0x00 0.--7. 1. " INTID456 ,Interrupt ID456 Priority/Priority Byte Offset 456 " group.long 0x5CC++0x03 line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" hexmask.long.byte 0x00 24.--31. 1. " INTID463 ,Interrupt ID463 Priority/Priority Byte Offset 463 " hexmask.long.byte 0x00 16.--23. 1. " INTID462 ,Interrupt ID462 Priority/Priority Byte Offset 462 " hexmask.long.byte 0x00 8.--15. 1. " INTID461 ,Interrupt ID461 Priority/Priority Byte Offset 461 " hexmask.long.byte 0x00 0.--7. 1. " INTID460 ,Interrupt ID460 Priority/Priority Byte Offset 460 " group.long 0x5D0++0x03 line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" hexmask.long.byte 0x00 24.--31. 1. " INTID467 ,Interrupt ID467 Priority/Priority Byte Offset 467 " hexmask.long.byte 0x00 16.--23. 1. " INTID466 ,Interrupt ID466 Priority/Priority Byte Offset 466 " hexmask.long.byte 0x00 8.--15. 1. " INTID465 ,Interrupt ID465 Priority/Priority Byte Offset 465 " hexmask.long.byte 0x00 0.--7. 1. " INTID464 ,Interrupt ID464 Priority/Priority Byte Offset 464 " group.long 0x5D4++0x03 line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" hexmask.long.byte 0x00 24.--31. 1. " INTID471 ,Interrupt ID471 Priority/Priority Byte Offset 471 " hexmask.long.byte 0x00 16.--23. 1. " INTID470 ,Interrupt ID470 Priority/Priority Byte Offset 470 " hexmask.long.byte 0x00 8.--15. 1. " INTID469 ,Interrupt ID469 Priority/Priority Byte Offset 469 " hexmask.long.byte 0x00 0.--7. 1. " INTID468 ,Interrupt ID468 Priority/Priority Byte Offset 468 " group.long 0x5D8++0x03 line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" hexmask.long.byte 0x00 24.--31. 1. " INTID475 ,Interrupt ID475 Priority/Priority Byte Offset 475 " hexmask.long.byte 0x00 16.--23. 1. " INTID474 ,Interrupt ID474 Priority/Priority Byte Offset 474 " hexmask.long.byte 0x00 8.--15. 1. " INTID473 ,Interrupt ID473 Priority/Priority Byte Offset 473 " hexmask.long.byte 0x00 0.--7. 1. " INTID472 ,Interrupt ID472 Priority/Priority Byte Offset 472 " group.long 0x5DC++0x03 line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" hexmask.long.byte 0x00 24.--31. 1. " INTID479 ,Interrupt ID479 Priority/Priority Byte Offset 479 " hexmask.long.byte 0x00 16.--23. 1. " INTID478 ,Interrupt ID478 Priority/Priority Byte Offset 478 " hexmask.long.byte 0x00 8.--15. 1. " INTID477 ,Interrupt ID477 Priority/Priority Byte Offset 477 " hexmask.long.byte 0x00 0.--7. 1. " INTID476 ,Interrupt ID476 Priority/Priority Byte Offset 476 " else hgroup.long 0x5C0++0x03 hide.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" hgroup.long 0x5C4++0x03 hide.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" hgroup.long 0x5C8++0x03 hide.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" hgroup.long 0x5CC++0x03 hide.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" hgroup.long 0x5D0++0x03 hide.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" hgroup.long 0x5D4++0x03 hide.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" hgroup.long 0x5D8++0x03 hide.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" hgroup.long 0x5DC++0x03 hide.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x5E0++0x03 line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" hexmask.long.byte 0x00 24.--31. 1. " INTID483 ,Interrupt ID483 Priority/Priority Byte Offset 483 " hexmask.long.byte 0x00 16.--23. 1. " INTID482 ,Interrupt ID482 Priority/Priority Byte Offset 482 " hexmask.long.byte 0x00 8.--15. 1. " INTID481 ,Interrupt ID481 Priority/Priority Byte Offset 481 " hexmask.long.byte 0x00 0.--7. 1. " INTID480 ,Interrupt ID480 Priority/Priority Byte Offset 480 " group.long 0x5E4++0x03 line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" hexmask.long.byte 0x00 24.--31. 1. " INTID487 ,Interrupt ID487 Priority/Priority Byte Offset 487 " hexmask.long.byte 0x00 16.--23. 1. " INTID486 ,Interrupt ID486 Priority/Priority Byte Offset 486 " hexmask.long.byte 0x00 8.--15. 1. " INTID485 ,Interrupt ID485 Priority/Priority Byte Offset 485 " hexmask.long.byte 0x00 0.--7. 1. " INTID484 ,Interrupt ID484 Priority/Priority Byte Offset 484 " group.long 0x5E8++0x03 line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" hexmask.long.byte 0x00 24.--31. 1. " INTID491 ,Interrupt ID491 Priority/Priority Byte Offset 491 " hexmask.long.byte 0x00 16.--23. 1. " INTID490 ,Interrupt ID490 Priority/Priority Byte Offset 490 " hexmask.long.byte 0x00 8.--15. 1. " INTID489 ,Interrupt ID489 Priority/Priority Byte Offset 489 " hexmask.long.byte 0x00 0.--7. 1. " INTID488 ,Interrupt ID488 Priority/Priority Byte Offset 488 " group.long 0x5EC++0x03 line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" hexmask.long.byte 0x00 24.--31. 1. " INTID495 ,Interrupt ID495 Priority/Priority Byte Offset 495 " hexmask.long.byte 0x00 16.--23. 1. " INTID494 ,Interrupt ID494 Priority/Priority Byte Offset 494 " hexmask.long.byte 0x00 8.--15. 1. " INTID493 ,Interrupt ID493 Priority/Priority Byte Offset 493 " hexmask.long.byte 0x00 0.--7. 1. " INTID492 ,Interrupt ID492 Priority/Priority Byte Offset 492 " group.long 0x5F0++0x03 line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" hexmask.long.byte 0x00 24.--31. 1. " INTID499 ,Interrupt ID499 Priority/Priority Byte Offset 499 " hexmask.long.byte 0x00 16.--23. 1. " INTID498 ,Interrupt ID498 Priority/Priority Byte Offset 498 " hexmask.long.byte 0x00 8.--15. 1. " INTID497 ,Interrupt ID497 Priority/Priority Byte Offset 497 " hexmask.long.byte 0x00 0.--7. 1. " INTID496 ,Interrupt ID496 Priority/Priority Byte Offset 496 " group.long 0x5F4++0x03 line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" hexmask.long.byte 0x00 24.--31. 1. " INTID503 ,Interrupt ID503 Priority/Priority Byte Offset 503 " hexmask.long.byte 0x00 16.--23. 1. " INTID502 ,Interrupt ID502 Priority/Priority Byte Offset 502 " hexmask.long.byte 0x00 8.--15. 1. " INTID501 ,Interrupt ID501 Priority/Priority Byte Offset 501 " hexmask.long.byte 0x00 0.--7. 1. " INTID500 ,Interrupt ID500 Priority/Priority Byte Offset 500 " group.long 0x5F8++0x03 line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" hexmask.long.byte 0x00 24.--31. 1. " INTID507 ,Interrupt ID507 Priority/Priority Byte Offset 507 " hexmask.long.byte 0x00 16.--23. 1. " INTID506 ,Interrupt ID506 Priority/Priority Byte Offset 506 " hexmask.long.byte 0x00 8.--15. 1. " INTID505 ,Interrupt ID505 Priority/Priority Byte Offset 505 " hexmask.long.byte 0x00 0.--7. 1. " INTID504 ,Interrupt ID504 Priority/Priority Byte Offset 504 " group.long 0x5FC++0x03 line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" hexmask.long.byte 0x00 24.--31. 1. " INTID511 ,Interrupt ID511 Priority/Priority Byte Offset 511 " hexmask.long.byte 0x00 16.--23. 1. " INTID510 ,Interrupt ID510 Priority/Priority Byte Offset 510 " hexmask.long.byte 0x00 8.--15. 1. " INTID509 ,Interrupt ID509 Priority/Priority Byte Offset 509 " hexmask.long.byte 0x00 0.--7. 1. " INTID508 ,Interrupt ID508 Priority/Priority Byte Offset 508 " else hgroup.long 0x5E0++0x03 hide.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" hgroup.long 0x5E4++0x03 hide.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" hgroup.long 0x5E8++0x03 hide.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" hgroup.long 0x5EC++0x03 hide.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" hgroup.long 0x5F0++0x03 hide.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" hgroup.long 0x5F4++0x03 hide.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" hgroup.long 0x5F8++0x03 hide.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" hgroup.long 0x5FC++0x03 hide.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x600++0x03 line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" hexmask.long.byte 0x00 24.--31. 1. " INTID515 ,Interrupt ID515 Priority/Priority Byte Offset 515 " hexmask.long.byte 0x00 16.--23. 1. " INTID514 ,Interrupt ID514 Priority/Priority Byte Offset 514 " hexmask.long.byte 0x00 8.--15. 1. " INTID513 ,Interrupt ID513 Priority/Priority Byte Offset 513 " hexmask.long.byte 0x00 0.--7. 1. " INTID512 ,Interrupt ID512 Priority/Priority Byte Offset 512 " group.long 0x604++0x03 line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" hexmask.long.byte 0x00 24.--31. 1. " INTID519 ,Interrupt ID519 Priority/Priority Byte Offset 519 " hexmask.long.byte 0x00 16.--23. 1. " INTID518 ,Interrupt ID518 Priority/Priority Byte Offset 518 " hexmask.long.byte 0x00 8.--15. 1. " INTID517 ,Interrupt ID517 Priority/Priority Byte Offset 517 " hexmask.long.byte 0x00 0.--7. 1. " INTID516 ,Interrupt ID516 Priority/Priority Byte Offset 516 " group.long 0x608++0x03 line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" hexmask.long.byte 0x00 24.--31. 1. " INTID523 ,Interrupt ID523 Priority/Priority Byte Offset 523 " hexmask.long.byte 0x00 16.--23. 1. " INTID522 ,Interrupt ID522 Priority/Priority Byte Offset 522 " hexmask.long.byte 0x00 8.--15. 1. " INTID521 ,Interrupt ID521 Priority/Priority Byte Offset 521 " hexmask.long.byte 0x00 0.--7. 1. " INTID520 ,Interrupt ID520 Priority/Priority Byte Offset 520 " group.long 0x60C++0x03 line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" hexmask.long.byte 0x00 24.--31. 1. " INTID527 ,Interrupt ID527 Priority/Priority Byte Offset 527 " hexmask.long.byte 0x00 16.--23. 1. " INTID526 ,Interrupt ID526 Priority/Priority Byte Offset 526 " hexmask.long.byte 0x00 8.--15. 1. " INTID525 ,Interrupt ID525 Priority/Priority Byte Offset 525 " hexmask.long.byte 0x00 0.--7. 1. " INTID524 ,Interrupt ID524 Priority/Priority Byte Offset 524 " group.long 0x610++0x03 line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" hexmask.long.byte 0x00 24.--31. 1. " INTID531 ,Interrupt ID531 Priority/Priority Byte Offset 531 " hexmask.long.byte 0x00 16.--23. 1. " INTID530 ,Interrupt ID530 Priority/Priority Byte Offset 530 " hexmask.long.byte 0x00 8.--15. 1. " INTID529 ,Interrupt ID529 Priority/Priority Byte Offset 529 " hexmask.long.byte 0x00 0.--7. 1. " INTID528 ,Interrupt ID528 Priority/Priority Byte Offset 528 " group.long 0x614++0x03 line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" hexmask.long.byte 0x00 24.--31. 1. " INTID535 ,Interrupt ID535 Priority/Priority Byte Offset 535 " hexmask.long.byte 0x00 16.--23. 1. " INTID534 ,Interrupt ID534 Priority/Priority Byte Offset 534 " hexmask.long.byte 0x00 8.--15. 1. " INTID533 ,Interrupt ID533 Priority/Priority Byte Offset 533 " hexmask.long.byte 0x00 0.--7. 1. " INTID532 ,Interrupt ID532 Priority/Priority Byte Offset 532 " group.long 0x618++0x03 line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" hexmask.long.byte 0x00 24.--31. 1. " INTID539 ,Interrupt ID539 Priority/Priority Byte Offset 539 " hexmask.long.byte 0x00 16.--23. 1. " INTID538 ,Interrupt ID538 Priority/Priority Byte Offset 538 " hexmask.long.byte 0x00 8.--15. 1. " INTID537 ,Interrupt ID537 Priority/Priority Byte Offset 537 " hexmask.long.byte 0x00 0.--7. 1. " INTID536 ,Interrupt ID536 Priority/Priority Byte Offset 536 " group.long 0x61C++0x03 line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" hexmask.long.byte 0x00 24.--31. 1. " INTID543 ,Interrupt ID543 Priority/Priority Byte Offset 543 " hexmask.long.byte 0x00 16.--23. 1. " INTID542 ,Interrupt ID542 Priority/Priority Byte Offset 542 " hexmask.long.byte 0x00 8.--15. 1. " INTID541 ,Interrupt ID541 Priority/Priority Byte Offset 541 " hexmask.long.byte 0x00 0.--7. 1. " INTID540 ,Interrupt ID540 Priority/Priority Byte Offset 540 " else hgroup.long 0x600++0x03 hide.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" hgroup.long 0x604++0x03 hide.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" hgroup.long 0x608++0x03 hide.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" hgroup.long 0x60C++0x03 hide.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" hgroup.long 0x610++0x03 hide.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" hgroup.long 0x614++0x03 hide.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" hgroup.long 0x618++0x03 hide.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" hgroup.long 0x61C++0x03 hide.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x620++0x03 line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" hexmask.long.byte 0x00 24.--31. 1. " INTID547 ,Interrupt ID547 Priority/Priority Byte Offset 547 " hexmask.long.byte 0x00 16.--23. 1. " INTID546 ,Interrupt ID546 Priority/Priority Byte Offset 546 " hexmask.long.byte 0x00 8.--15. 1. " INTID545 ,Interrupt ID545 Priority/Priority Byte Offset 545 " hexmask.long.byte 0x00 0.--7. 1. " INTID544 ,Interrupt ID544 Priority/Priority Byte Offset 544 " group.long 0x624++0x03 line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" hexmask.long.byte 0x00 24.--31. 1. " INTID551 ,Interrupt ID551 Priority/Priority Byte Offset 551 " hexmask.long.byte 0x00 16.--23. 1. " INTID550 ,Interrupt ID550 Priority/Priority Byte Offset 550 " hexmask.long.byte 0x00 8.--15. 1. " INTID549 ,Interrupt ID549 Priority/Priority Byte Offset 549 " hexmask.long.byte 0x00 0.--7. 1. " INTID548 ,Interrupt ID548 Priority/Priority Byte Offset 548 " group.long 0x628++0x03 line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" hexmask.long.byte 0x00 24.--31. 1. " INTID555 ,Interrupt ID555 Priority/Priority Byte Offset 555 " hexmask.long.byte 0x00 16.--23. 1. " INTID554 ,Interrupt ID554 Priority/Priority Byte Offset 554 " hexmask.long.byte 0x00 8.--15. 1. " INTID553 ,Interrupt ID553 Priority/Priority Byte Offset 553 " hexmask.long.byte 0x00 0.--7. 1. " INTID552 ,Interrupt ID552 Priority/Priority Byte Offset 552 " group.long 0x62C++0x03 line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" hexmask.long.byte 0x00 24.--31. 1. " INTID559 ,Interrupt ID559 Priority/Priority Byte Offset 559 " hexmask.long.byte 0x00 16.--23. 1. " INTID558 ,Interrupt ID558 Priority/Priority Byte Offset 558 " hexmask.long.byte 0x00 8.--15. 1. " INTID557 ,Interrupt ID557 Priority/Priority Byte Offset 557 " hexmask.long.byte 0x00 0.--7. 1. " INTID556 ,Interrupt ID556 Priority/Priority Byte Offset 556 " group.long 0x630++0x03 line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" hexmask.long.byte 0x00 24.--31. 1. " INTID563 ,Interrupt ID563 Priority/Priority Byte Offset 563 " hexmask.long.byte 0x00 16.--23. 1. " INTID562 ,Interrupt ID562 Priority/Priority Byte Offset 562 " hexmask.long.byte 0x00 8.--15. 1. " INTID561 ,Interrupt ID561 Priority/Priority Byte Offset 561 " hexmask.long.byte 0x00 0.--7. 1. " INTID560 ,Interrupt ID560 Priority/Priority Byte Offset 560 " group.long 0x634++0x03 line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" hexmask.long.byte 0x00 24.--31. 1. " INTID567 ,Interrupt ID567 Priority/Priority Byte Offset 567 " hexmask.long.byte 0x00 16.--23. 1. " INTID566 ,Interrupt ID566 Priority/Priority Byte Offset 566 " hexmask.long.byte 0x00 8.--15. 1. " INTID565 ,Interrupt ID565 Priority/Priority Byte Offset 565 " hexmask.long.byte 0x00 0.--7. 1. " INTID564 ,Interrupt ID564 Priority/Priority Byte Offset 564 " group.long 0x638++0x03 line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" hexmask.long.byte 0x00 24.--31. 1. " INTID571 ,Interrupt ID571 Priority/Priority Byte Offset 571 " hexmask.long.byte 0x00 16.--23. 1. " INTID570 ,Interrupt ID570 Priority/Priority Byte Offset 570 " hexmask.long.byte 0x00 8.--15. 1. " INTID569 ,Interrupt ID569 Priority/Priority Byte Offset 569 " hexmask.long.byte 0x00 0.--7. 1. " INTID568 ,Interrupt ID568 Priority/Priority Byte Offset 568 " group.long 0x63C++0x03 line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" hexmask.long.byte 0x00 24.--31. 1. " INTID575 ,Interrupt ID575 Priority/Priority Byte Offset 575 " hexmask.long.byte 0x00 16.--23. 1. " INTID574 ,Interrupt ID574 Priority/Priority Byte Offset 574 " hexmask.long.byte 0x00 8.--15. 1. " INTID573 ,Interrupt ID573 Priority/Priority Byte Offset 573 " hexmask.long.byte 0x00 0.--7. 1. " INTID572 ,Interrupt ID572 Priority/Priority Byte Offset 572 " else hgroup.long 0x620++0x03 hide.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" hgroup.long 0x624++0x03 hide.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" hgroup.long 0x628++0x03 hide.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" hgroup.long 0x62C++0x03 hide.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" hgroup.long 0x630++0x03 hide.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" hgroup.long 0x634++0x03 hide.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" hgroup.long 0x638++0x03 hide.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" hgroup.long 0x63C++0x03 hide.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x640++0x03 line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" hexmask.long.byte 0x00 24.--31. 1. " INTID579 ,Interrupt ID579 Priority/Priority Byte Offset 579 " hexmask.long.byte 0x00 16.--23. 1. " INTID578 ,Interrupt ID578 Priority/Priority Byte Offset 578 " hexmask.long.byte 0x00 8.--15. 1. " INTID577 ,Interrupt ID577 Priority/Priority Byte Offset 577 " hexmask.long.byte 0x00 0.--7. 1. " INTID576 ,Interrupt ID576 Priority/Priority Byte Offset 576 " group.long 0x644++0x03 line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" hexmask.long.byte 0x00 24.--31. 1. " INTID583 ,Interrupt ID583 Priority/Priority Byte Offset 583 " hexmask.long.byte 0x00 16.--23. 1. " INTID582 ,Interrupt ID582 Priority/Priority Byte Offset 582 " hexmask.long.byte 0x00 8.--15. 1. " INTID581 ,Interrupt ID581 Priority/Priority Byte Offset 581 " hexmask.long.byte 0x00 0.--7. 1. " INTID580 ,Interrupt ID580 Priority/Priority Byte Offset 580 " group.long 0x648++0x03 line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" hexmask.long.byte 0x00 24.--31. 1. " INTID587 ,Interrupt ID587 Priority/Priority Byte Offset 587 " hexmask.long.byte 0x00 16.--23. 1. " INTID586 ,Interrupt ID586 Priority/Priority Byte Offset 586 " hexmask.long.byte 0x00 8.--15. 1. " INTID585 ,Interrupt ID585 Priority/Priority Byte Offset 585 " hexmask.long.byte 0x00 0.--7. 1. " INTID584 ,Interrupt ID584 Priority/Priority Byte Offset 584 " group.long 0x64C++0x03 line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" hexmask.long.byte 0x00 24.--31. 1. " INTID591 ,Interrupt ID591 Priority/Priority Byte Offset 591 " hexmask.long.byte 0x00 16.--23. 1. " INTID590 ,Interrupt ID590 Priority/Priority Byte Offset 590 " hexmask.long.byte 0x00 8.--15. 1. " INTID589 ,Interrupt ID589 Priority/Priority Byte Offset 589 " hexmask.long.byte 0x00 0.--7. 1. " INTID588 ,Interrupt ID588 Priority/Priority Byte Offset 588 " group.long 0x650++0x03 line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" hexmask.long.byte 0x00 24.--31. 1. " INTID595 ,Interrupt ID595 Priority/Priority Byte Offset 595 " hexmask.long.byte 0x00 16.--23. 1. " INTID594 ,Interrupt ID594 Priority/Priority Byte Offset 594 " hexmask.long.byte 0x00 8.--15. 1. " INTID593 ,Interrupt ID593 Priority/Priority Byte Offset 593 " hexmask.long.byte 0x00 0.--7. 1. " INTID592 ,Interrupt ID592 Priority/Priority Byte Offset 592 " group.long 0x654++0x03 line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" hexmask.long.byte 0x00 24.--31. 1. " INTID599 ,Interrupt ID599 Priority/Priority Byte Offset 599 " hexmask.long.byte 0x00 16.--23. 1. " INTID598 ,Interrupt ID598 Priority/Priority Byte Offset 598 " hexmask.long.byte 0x00 8.--15. 1. " INTID597 ,Interrupt ID597 Priority/Priority Byte Offset 597 " hexmask.long.byte 0x00 0.--7. 1. " INTID596 ,Interrupt ID596 Priority/Priority Byte Offset 596 " group.long 0x658++0x03 line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" hexmask.long.byte 0x00 24.--31. 1. " INTID603 ,Interrupt ID603 Priority/Priority Byte Offset 603 " hexmask.long.byte 0x00 16.--23. 1. " INTID602 ,Interrupt ID602 Priority/Priority Byte Offset 602 " hexmask.long.byte 0x00 8.--15. 1. " INTID601 ,Interrupt ID601 Priority/Priority Byte Offset 601 " hexmask.long.byte 0x00 0.--7. 1. " INTID600 ,Interrupt ID600 Priority/Priority Byte Offset 600 " group.long 0x65C++0x03 line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" hexmask.long.byte 0x00 24.--31. 1. " INTID607 ,Interrupt ID607 Priority/Priority Byte Offset 607 " hexmask.long.byte 0x00 16.--23. 1. " INTID606 ,Interrupt ID606 Priority/Priority Byte Offset 606 " hexmask.long.byte 0x00 8.--15. 1. " INTID605 ,Interrupt ID605 Priority/Priority Byte Offset 605 " hexmask.long.byte 0x00 0.--7. 1. " INTID604 ,Interrupt ID604 Priority/Priority Byte Offset 604 " else hgroup.long 0x640++0x03 hide.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" hgroup.long 0x644++0x03 hide.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" hgroup.long 0x648++0x03 hide.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" hgroup.long 0x64C++0x03 hide.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" hgroup.long 0x650++0x03 hide.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" hgroup.long 0x654++0x03 hide.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" hgroup.long 0x658++0x03 hide.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" hgroup.long 0x65C++0x03 hide.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x660++0x03 line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" hexmask.long.byte 0x00 24.--31. 1. " INTID611 ,Interrupt ID611 Priority/Priority Byte Offset 611 " hexmask.long.byte 0x00 16.--23. 1. " INTID610 ,Interrupt ID610 Priority/Priority Byte Offset 610 " hexmask.long.byte 0x00 8.--15. 1. " INTID609 ,Interrupt ID609 Priority/Priority Byte Offset 609 " hexmask.long.byte 0x00 0.--7. 1. " INTID608 ,Interrupt ID608 Priority/Priority Byte Offset 608 " group.long 0x664++0x03 line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" hexmask.long.byte 0x00 24.--31. 1. " INTID615 ,Interrupt ID615 Priority/Priority Byte Offset 615 " hexmask.long.byte 0x00 16.--23. 1. " INTID614 ,Interrupt ID614 Priority/Priority Byte Offset 614 " hexmask.long.byte 0x00 8.--15. 1. " INTID613 ,Interrupt ID613 Priority/Priority Byte Offset 613 " hexmask.long.byte 0x00 0.--7. 1. " INTID612 ,Interrupt ID612 Priority/Priority Byte Offset 612 " group.long 0x668++0x03 line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" hexmask.long.byte 0x00 24.--31. 1. " INTID619 ,Interrupt ID619 Priority/Priority Byte Offset 619 " hexmask.long.byte 0x00 16.--23. 1. " INTID618 ,Interrupt ID618 Priority/Priority Byte Offset 618 " hexmask.long.byte 0x00 8.--15. 1. " INTID617 ,Interrupt ID617 Priority/Priority Byte Offset 617 " hexmask.long.byte 0x00 0.--7. 1. " INTID616 ,Interrupt ID616 Priority/Priority Byte Offset 616 " group.long 0x66C++0x03 line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" hexmask.long.byte 0x00 24.--31. 1. " INTID623 ,Interrupt ID623 Priority/Priority Byte Offset 623 " hexmask.long.byte 0x00 16.--23. 1. " INTID622 ,Interrupt ID622 Priority/Priority Byte Offset 622 " hexmask.long.byte 0x00 8.--15. 1. " INTID621 ,Interrupt ID621 Priority/Priority Byte Offset 621 " hexmask.long.byte 0x00 0.--7. 1. " INTID620 ,Interrupt ID620 Priority/Priority Byte Offset 620 " group.long 0x670++0x03 line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" hexmask.long.byte 0x00 24.--31. 1. " INTID627 ,Interrupt ID627 Priority/Priority Byte Offset 627 " hexmask.long.byte 0x00 16.--23. 1. " INTID626 ,Interrupt ID626 Priority/Priority Byte Offset 626 " hexmask.long.byte 0x00 8.--15. 1. " INTID625 ,Interrupt ID625 Priority/Priority Byte Offset 625 " hexmask.long.byte 0x00 0.--7. 1. " INTID624 ,Interrupt ID624 Priority/Priority Byte Offset 624 " group.long 0x674++0x03 line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" hexmask.long.byte 0x00 24.--31. 1. " INTID631 ,Interrupt ID631 Priority/Priority Byte Offset 631 " hexmask.long.byte 0x00 16.--23. 1. " INTID630 ,Interrupt ID630 Priority/Priority Byte Offset 630 " hexmask.long.byte 0x00 8.--15. 1. " INTID629 ,Interrupt ID629 Priority/Priority Byte Offset 629 " hexmask.long.byte 0x00 0.--7. 1. " INTID628 ,Interrupt ID628 Priority/Priority Byte Offset 628 " group.long 0x678++0x03 line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" hexmask.long.byte 0x00 24.--31. 1. " INTID635 ,Interrupt ID635 Priority/Priority Byte Offset 635 " hexmask.long.byte 0x00 16.--23. 1. " INTID634 ,Interrupt ID634 Priority/Priority Byte Offset 634 " hexmask.long.byte 0x00 8.--15. 1. " INTID633 ,Interrupt ID633 Priority/Priority Byte Offset 633 " hexmask.long.byte 0x00 0.--7. 1. " INTID632 ,Interrupt ID632 Priority/Priority Byte Offset 632 " group.long 0x67C++0x03 line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" hexmask.long.byte 0x00 24.--31. 1. " INTID639 ,Interrupt ID639 Priority/Priority Byte Offset 639 " hexmask.long.byte 0x00 16.--23. 1. " INTID638 ,Interrupt ID638 Priority/Priority Byte Offset 638 " hexmask.long.byte 0x00 8.--15. 1. " INTID637 ,Interrupt ID637 Priority/Priority Byte Offset 637 " hexmask.long.byte 0x00 0.--7. 1. " INTID636 ,Interrupt ID636 Priority/Priority Byte Offset 636 " else hgroup.long 0x660++0x03 hide.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" hgroup.long 0x664++0x03 hide.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" hgroup.long 0x668++0x03 hide.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" hgroup.long 0x66C++0x03 hide.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" hgroup.long 0x670++0x03 hide.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" hgroup.long 0x674++0x03 hide.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" hgroup.long 0x678++0x03 hide.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" hgroup.long 0x67C++0x03 hide.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x680++0x03 line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" hexmask.long.byte 0x00 24.--31. 1. " INTID643 ,Interrupt ID643 Priority/Priority Byte Offset 643 " hexmask.long.byte 0x00 16.--23. 1. " INTID642 ,Interrupt ID642 Priority/Priority Byte Offset 642 " hexmask.long.byte 0x00 8.--15. 1. " INTID641 ,Interrupt ID641 Priority/Priority Byte Offset 641 " hexmask.long.byte 0x00 0.--7. 1. " INTID640 ,Interrupt ID640 Priority/Priority Byte Offset 640 " group.long 0x684++0x03 line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" hexmask.long.byte 0x00 24.--31. 1. " INTID647 ,Interrupt ID647 Priority/Priority Byte Offset 647 " hexmask.long.byte 0x00 16.--23. 1. " INTID646 ,Interrupt ID646 Priority/Priority Byte Offset 646 " hexmask.long.byte 0x00 8.--15. 1. " INTID645 ,Interrupt ID645 Priority/Priority Byte Offset 645 " hexmask.long.byte 0x00 0.--7. 1. " INTID644 ,Interrupt ID644 Priority/Priority Byte Offset 644 " group.long 0x688++0x03 line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" hexmask.long.byte 0x00 24.--31. 1. " INTID651 ,Interrupt ID651 Priority/Priority Byte Offset 651 " hexmask.long.byte 0x00 16.--23. 1. " INTID650 ,Interrupt ID650 Priority/Priority Byte Offset 650 " hexmask.long.byte 0x00 8.--15. 1. " INTID649 ,Interrupt ID649 Priority/Priority Byte Offset 649 " hexmask.long.byte 0x00 0.--7. 1. " INTID648 ,Interrupt ID648 Priority/Priority Byte Offset 648 " group.long 0x68C++0x03 line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" hexmask.long.byte 0x00 24.--31. 1. " INTID655 ,Interrupt ID655 Priority/Priority Byte Offset 655 " hexmask.long.byte 0x00 16.--23. 1. " INTID654 ,Interrupt ID654 Priority/Priority Byte Offset 654 " hexmask.long.byte 0x00 8.--15. 1. " INTID653 ,Interrupt ID653 Priority/Priority Byte Offset 653 " hexmask.long.byte 0x00 0.--7. 1. " INTID652 ,Interrupt ID652 Priority/Priority Byte Offset 652 " group.long 0x690++0x03 line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" hexmask.long.byte 0x00 24.--31. 1. " INTID659 ,Interrupt ID659 Priority/Priority Byte Offset 659 " hexmask.long.byte 0x00 16.--23. 1. " INTID658 ,Interrupt ID658 Priority/Priority Byte Offset 658 " hexmask.long.byte 0x00 8.--15. 1. " INTID657 ,Interrupt ID657 Priority/Priority Byte Offset 657 " hexmask.long.byte 0x00 0.--7. 1. " INTID656 ,Interrupt ID656 Priority/Priority Byte Offset 656 " group.long 0x694++0x03 line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" hexmask.long.byte 0x00 24.--31. 1. " INTID663 ,Interrupt ID663 Priority/Priority Byte Offset 663 " hexmask.long.byte 0x00 16.--23. 1. " INTID662 ,Interrupt ID662 Priority/Priority Byte Offset 662 " hexmask.long.byte 0x00 8.--15. 1. " INTID661 ,Interrupt ID661 Priority/Priority Byte Offset 661 " hexmask.long.byte 0x00 0.--7. 1. " INTID660 ,Interrupt ID660 Priority/Priority Byte Offset 660 " group.long 0x698++0x03 line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" hexmask.long.byte 0x00 24.--31. 1. " INTID667 ,Interrupt ID667 Priority/Priority Byte Offset 667 " hexmask.long.byte 0x00 16.--23. 1. " INTID666 ,Interrupt ID666 Priority/Priority Byte Offset 666 " hexmask.long.byte 0x00 8.--15. 1. " INTID665 ,Interrupt ID665 Priority/Priority Byte Offset 665 " hexmask.long.byte 0x00 0.--7. 1. " INTID664 ,Interrupt ID664 Priority/Priority Byte Offset 664 " group.long 0x69C++0x03 line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" hexmask.long.byte 0x00 24.--31. 1. " INTID671 ,Interrupt ID671 Priority/Priority Byte Offset 671 " hexmask.long.byte 0x00 16.--23. 1. " INTID670 ,Interrupt ID670 Priority/Priority Byte Offset 670 " hexmask.long.byte 0x00 8.--15. 1. " INTID669 ,Interrupt ID669 Priority/Priority Byte Offset 669 " hexmask.long.byte 0x00 0.--7. 1. " INTID668 ,Interrupt ID668 Priority/Priority Byte Offset 668 " else hgroup.long 0x680++0x03 hide.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" hgroup.long 0x684++0x03 hide.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" hgroup.long 0x688++0x03 hide.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" hgroup.long 0x68C++0x03 hide.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" hgroup.long 0x690++0x03 hide.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" hgroup.long 0x694++0x03 hide.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" hgroup.long 0x698++0x03 hide.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" hgroup.long 0x69C++0x03 hide.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x6A0++0x03 line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" hexmask.long.byte 0x00 24.--31. 1. " INTID675 ,Interrupt ID675 Priority/Priority Byte Offset 675 " hexmask.long.byte 0x00 16.--23. 1. " INTID674 ,Interrupt ID674 Priority/Priority Byte Offset 674 " hexmask.long.byte 0x00 8.--15. 1. " INTID673 ,Interrupt ID673 Priority/Priority Byte Offset 673 " hexmask.long.byte 0x00 0.--7. 1. " INTID672 ,Interrupt ID672 Priority/Priority Byte Offset 672 " group.long 0x6A4++0x03 line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" hexmask.long.byte 0x00 24.--31. 1. " INTID679 ,Interrupt ID679 Priority/Priority Byte Offset 679 " hexmask.long.byte 0x00 16.--23. 1. " INTID678 ,Interrupt ID678 Priority/Priority Byte Offset 678 " hexmask.long.byte 0x00 8.--15. 1. " INTID677 ,Interrupt ID677 Priority/Priority Byte Offset 677 " hexmask.long.byte 0x00 0.--7. 1. " INTID676 ,Interrupt ID676 Priority/Priority Byte Offset 676 " group.long 0x6A8++0x03 line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" hexmask.long.byte 0x00 24.--31. 1. " INTID683 ,Interrupt ID683 Priority/Priority Byte Offset 683 " hexmask.long.byte 0x00 16.--23. 1. " INTID682 ,Interrupt ID682 Priority/Priority Byte Offset 682 " hexmask.long.byte 0x00 8.--15. 1. " INTID681 ,Interrupt ID681 Priority/Priority Byte Offset 681 " hexmask.long.byte 0x00 0.--7. 1. " INTID680 ,Interrupt ID680 Priority/Priority Byte Offset 680 " group.long 0x6AC++0x03 line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" hexmask.long.byte 0x00 24.--31. 1. " INTID687 ,Interrupt ID687 Priority/Priority Byte Offset 687 " hexmask.long.byte 0x00 16.--23. 1. " INTID686 ,Interrupt ID686 Priority/Priority Byte Offset 686 " hexmask.long.byte 0x00 8.--15. 1. " INTID685 ,Interrupt ID685 Priority/Priority Byte Offset 685 " hexmask.long.byte 0x00 0.--7. 1. " INTID684 ,Interrupt ID684 Priority/Priority Byte Offset 684 " group.long 0x6B0++0x03 line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" hexmask.long.byte 0x00 24.--31. 1. " INTID691 ,Interrupt ID691 Priority/Priority Byte Offset 691 " hexmask.long.byte 0x00 16.--23. 1. " INTID690 ,Interrupt ID690 Priority/Priority Byte Offset 690 " hexmask.long.byte 0x00 8.--15. 1. " INTID689 ,Interrupt ID689 Priority/Priority Byte Offset 689 " hexmask.long.byte 0x00 0.--7. 1. " INTID688 ,Interrupt ID688 Priority/Priority Byte Offset 688 " group.long 0x6B4++0x03 line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" hexmask.long.byte 0x00 24.--31. 1. " INTID695 ,Interrupt ID695 Priority/Priority Byte Offset 695 " hexmask.long.byte 0x00 16.--23. 1. " INTID694 ,Interrupt ID694 Priority/Priority Byte Offset 694 " hexmask.long.byte 0x00 8.--15. 1. " INTID693 ,Interrupt ID693 Priority/Priority Byte Offset 693 " hexmask.long.byte 0x00 0.--7. 1. " INTID692 ,Interrupt ID692 Priority/Priority Byte Offset 692 " group.long 0x6B8++0x03 line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" hexmask.long.byte 0x00 24.--31. 1. " INTID699 ,Interrupt ID699 Priority/Priority Byte Offset 699 " hexmask.long.byte 0x00 16.--23. 1. " INTID698 ,Interrupt ID698 Priority/Priority Byte Offset 698 " hexmask.long.byte 0x00 8.--15. 1. " INTID697 ,Interrupt ID697 Priority/Priority Byte Offset 697 " hexmask.long.byte 0x00 0.--7. 1. " INTID696 ,Interrupt ID696 Priority/Priority Byte Offset 696 " group.long 0x6BC++0x03 line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" hexmask.long.byte 0x00 24.--31. 1. " INTID703 ,Interrupt ID703 Priority/Priority Byte Offset 703 " hexmask.long.byte 0x00 16.--23. 1. " INTID702 ,Interrupt ID702 Priority/Priority Byte Offset 702 " hexmask.long.byte 0x00 8.--15. 1. " INTID701 ,Interrupt ID701 Priority/Priority Byte Offset 701 " hexmask.long.byte 0x00 0.--7. 1. " INTID700 ,Interrupt ID700 Priority/Priority Byte Offset 700 " else hgroup.long 0x6A0++0x03 hide.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" hgroup.long 0x6A4++0x03 hide.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" hgroup.long 0x6A8++0x03 hide.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" hgroup.long 0x6AC++0x03 hide.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" hgroup.long 0x6B0++0x03 hide.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" hgroup.long 0x6B4++0x03 hide.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" hgroup.long 0x6B8++0x03 hide.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" hgroup.long 0x6BC++0x03 hide.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x6C0++0x03 line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" hexmask.long.byte 0x00 24.--31. 1. " INTID707 ,Interrupt ID707 Priority/Priority Byte Offset 707 " hexmask.long.byte 0x00 16.--23. 1. " INTID706 ,Interrupt ID706 Priority/Priority Byte Offset 706 " hexmask.long.byte 0x00 8.--15. 1. " INTID705 ,Interrupt ID705 Priority/Priority Byte Offset 705 " hexmask.long.byte 0x00 0.--7. 1. " INTID704 ,Interrupt ID704 Priority/Priority Byte Offset 704 " group.long 0x6C4++0x03 line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" hexmask.long.byte 0x00 24.--31. 1. " INTID711 ,Interrupt ID711 Priority/Priority Byte Offset 711 " hexmask.long.byte 0x00 16.--23. 1. " INTID710 ,Interrupt ID710 Priority/Priority Byte Offset 710 " hexmask.long.byte 0x00 8.--15. 1. " INTID709 ,Interrupt ID709 Priority/Priority Byte Offset 709 " hexmask.long.byte 0x00 0.--7. 1. " INTID708 ,Interrupt ID708 Priority/Priority Byte Offset 708 " group.long 0x6C8++0x03 line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" hexmask.long.byte 0x00 24.--31. 1. " INTID715 ,Interrupt ID715 Priority/Priority Byte Offset 715 " hexmask.long.byte 0x00 16.--23. 1. " INTID714 ,Interrupt ID714 Priority/Priority Byte Offset 714 " hexmask.long.byte 0x00 8.--15. 1. " INTID713 ,Interrupt ID713 Priority/Priority Byte Offset 713 " hexmask.long.byte 0x00 0.--7. 1. " INTID712 ,Interrupt ID712 Priority/Priority Byte Offset 712 " group.long 0x6CC++0x03 line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" hexmask.long.byte 0x00 24.--31. 1. " INTID719 ,Interrupt ID719 Priority/Priority Byte Offset 719 " hexmask.long.byte 0x00 16.--23. 1. " INTID718 ,Interrupt ID718 Priority/Priority Byte Offset 718 " hexmask.long.byte 0x00 8.--15. 1. " INTID717 ,Interrupt ID717 Priority/Priority Byte Offset 717 " hexmask.long.byte 0x00 0.--7. 1. " INTID716 ,Interrupt ID716 Priority/Priority Byte Offset 716 " group.long 0x6D0++0x03 line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" hexmask.long.byte 0x00 24.--31. 1. " INTID723 ,Interrupt ID723 Priority/Priority Byte Offset 723 " hexmask.long.byte 0x00 16.--23. 1. " INTID722 ,Interrupt ID722 Priority/Priority Byte Offset 722 " hexmask.long.byte 0x00 8.--15. 1. " INTID721 ,Interrupt ID721 Priority/Priority Byte Offset 721 " hexmask.long.byte 0x00 0.--7. 1. " INTID720 ,Interrupt ID720 Priority/Priority Byte Offset 720 " group.long 0x6D4++0x03 line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" hexmask.long.byte 0x00 24.--31. 1. " INTID727 ,Interrupt ID727 Priority/Priority Byte Offset 727 " hexmask.long.byte 0x00 16.--23. 1. " INTID726 ,Interrupt ID726 Priority/Priority Byte Offset 726 " hexmask.long.byte 0x00 8.--15. 1. " INTID725 ,Interrupt ID725 Priority/Priority Byte Offset 725 " hexmask.long.byte 0x00 0.--7. 1. " INTID724 ,Interrupt ID724 Priority/Priority Byte Offset 724 " group.long 0x6D8++0x03 line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" hexmask.long.byte 0x00 24.--31. 1. " INTID731 ,Interrupt ID731 Priority/Priority Byte Offset 731 " hexmask.long.byte 0x00 16.--23. 1. " INTID730 ,Interrupt ID730 Priority/Priority Byte Offset 730 " hexmask.long.byte 0x00 8.--15. 1. " INTID729 ,Interrupt ID729 Priority/Priority Byte Offset 729 " hexmask.long.byte 0x00 0.--7. 1. " INTID728 ,Interrupt ID728 Priority/Priority Byte Offset 728 " group.long 0x6DC++0x03 line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" hexmask.long.byte 0x00 24.--31. 1. " INTID735 ,Interrupt ID735 Priority/Priority Byte Offset 735 " hexmask.long.byte 0x00 16.--23. 1. " INTID734 ,Interrupt ID734 Priority/Priority Byte Offset 734 " hexmask.long.byte 0x00 8.--15. 1. " INTID733 ,Interrupt ID733 Priority/Priority Byte Offset 733 " hexmask.long.byte 0x00 0.--7. 1. " INTID732 ,Interrupt ID732 Priority/Priority Byte Offset 732 " else hgroup.long 0x6C0++0x03 hide.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" hgroup.long 0x6C4++0x03 hide.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" hgroup.long 0x6C8++0x03 hide.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" hgroup.long 0x6CC++0x03 hide.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" hgroup.long 0x6D0++0x03 hide.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" hgroup.long 0x6D4++0x03 hide.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" hgroup.long 0x6D8++0x03 hide.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" hgroup.long 0x6DC++0x03 hide.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x6E0++0x03 line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" hexmask.long.byte 0x00 24.--31. 1. " INTID739 ,Interrupt ID739 Priority/Priority Byte Offset 739 " hexmask.long.byte 0x00 16.--23. 1. " INTID738 ,Interrupt ID738 Priority/Priority Byte Offset 738 " hexmask.long.byte 0x00 8.--15. 1. " INTID737 ,Interrupt ID737 Priority/Priority Byte Offset 737 " hexmask.long.byte 0x00 0.--7. 1. " INTID736 ,Interrupt ID736 Priority/Priority Byte Offset 736 " group.long 0x6E4++0x03 line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" hexmask.long.byte 0x00 24.--31. 1. " INTID743 ,Interrupt ID743 Priority/Priority Byte Offset 743 " hexmask.long.byte 0x00 16.--23. 1. " INTID742 ,Interrupt ID742 Priority/Priority Byte Offset 742 " hexmask.long.byte 0x00 8.--15. 1. " INTID741 ,Interrupt ID741 Priority/Priority Byte Offset 741 " hexmask.long.byte 0x00 0.--7. 1. " INTID740 ,Interrupt ID740 Priority/Priority Byte Offset 740 " group.long 0x6E8++0x03 line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" hexmask.long.byte 0x00 24.--31. 1. " INTID747 ,Interrupt ID747 Priority/Priority Byte Offset 747 " hexmask.long.byte 0x00 16.--23. 1. " INTID746 ,Interrupt ID746 Priority/Priority Byte Offset 746 " hexmask.long.byte 0x00 8.--15. 1. " INTID745 ,Interrupt ID745 Priority/Priority Byte Offset 745 " hexmask.long.byte 0x00 0.--7. 1. " INTID744 ,Interrupt ID744 Priority/Priority Byte Offset 744 " group.long 0x6EC++0x03 line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" hexmask.long.byte 0x00 24.--31. 1. " INTID751 ,Interrupt ID751 Priority/Priority Byte Offset 751 " hexmask.long.byte 0x00 16.--23. 1. " INTID750 ,Interrupt ID750 Priority/Priority Byte Offset 750 " hexmask.long.byte 0x00 8.--15. 1. " INTID749 ,Interrupt ID749 Priority/Priority Byte Offset 749 " hexmask.long.byte 0x00 0.--7. 1. " INTID748 ,Interrupt ID748 Priority/Priority Byte Offset 748 " group.long 0x6F0++0x03 line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" hexmask.long.byte 0x00 24.--31. 1. " INTID755 ,Interrupt ID755 Priority/Priority Byte Offset 755 " hexmask.long.byte 0x00 16.--23. 1. " INTID754 ,Interrupt ID754 Priority/Priority Byte Offset 754 " hexmask.long.byte 0x00 8.--15. 1. " INTID753 ,Interrupt ID753 Priority/Priority Byte Offset 753 " hexmask.long.byte 0x00 0.--7. 1. " INTID752 ,Interrupt ID752 Priority/Priority Byte Offset 752 " group.long 0x6F4++0x03 line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" hexmask.long.byte 0x00 24.--31. 1. " INTID759 ,Interrupt ID759 Priority/Priority Byte Offset 759 " hexmask.long.byte 0x00 16.--23. 1. " INTID758 ,Interrupt ID758 Priority/Priority Byte Offset 758 " hexmask.long.byte 0x00 8.--15. 1. " INTID757 ,Interrupt ID757 Priority/Priority Byte Offset 757 " hexmask.long.byte 0x00 0.--7. 1. " INTID756 ,Interrupt ID756 Priority/Priority Byte Offset 756 " group.long 0x6F8++0x03 line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" hexmask.long.byte 0x00 24.--31. 1. " INTID763 ,Interrupt ID763 Priority/Priority Byte Offset 763 " hexmask.long.byte 0x00 16.--23. 1. " INTID762 ,Interrupt ID762 Priority/Priority Byte Offset 762 " hexmask.long.byte 0x00 8.--15. 1. " INTID761 ,Interrupt ID761 Priority/Priority Byte Offset 761 " hexmask.long.byte 0x00 0.--7. 1. " INTID760 ,Interrupt ID760 Priority/Priority Byte Offset 760 " group.long 0x6FC++0x03 line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" hexmask.long.byte 0x00 24.--31. 1. " INTID767 ,Interrupt ID767 Priority/Priority Byte Offset 767 " hexmask.long.byte 0x00 16.--23. 1. " INTID766 ,Interrupt ID766 Priority/Priority Byte Offset 766 " hexmask.long.byte 0x00 8.--15. 1. " INTID765 ,Interrupt ID765 Priority/Priority Byte Offset 765 " hexmask.long.byte 0x00 0.--7. 1. " INTID764 ,Interrupt ID764 Priority/Priority Byte Offset 764 " else hgroup.long 0x6E0++0x03 hide.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" hgroup.long 0x6E4++0x03 hide.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" hgroup.long 0x6E8++0x03 hide.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" hgroup.long 0x6EC++0x03 hide.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" hgroup.long 0x6F0++0x03 hide.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" hgroup.long 0x6F4++0x03 hide.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" hgroup.long 0x6F8++0x03 hide.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" hgroup.long 0x6FC++0x03 hide.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x700++0x03 line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" hexmask.long.byte 0x00 24.--31. 1. " INTID771 ,Interrupt ID771 Priority/Priority Byte Offset 771 " hexmask.long.byte 0x00 16.--23. 1. " INTID770 ,Interrupt ID770 Priority/Priority Byte Offset 770 " hexmask.long.byte 0x00 8.--15. 1. " INTID769 ,Interrupt ID769 Priority/Priority Byte Offset 769 " hexmask.long.byte 0x00 0.--7. 1. " INTID768 ,Interrupt ID768 Priority/Priority Byte Offset 768 " group.long 0x704++0x03 line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" hexmask.long.byte 0x00 24.--31. 1. " INTID775 ,Interrupt ID775 Priority/Priority Byte Offset 775 " hexmask.long.byte 0x00 16.--23. 1. " INTID774 ,Interrupt ID774 Priority/Priority Byte Offset 774 " hexmask.long.byte 0x00 8.--15. 1. " INTID773 ,Interrupt ID773 Priority/Priority Byte Offset 773 " hexmask.long.byte 0x00 0.--7. 1. " INTID772 ,Interrupt ID772 Priority/Priority Byte Offset 772 " group.long 0x708++0x03 line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" hexmask.long.byte 0x00 24.--31. 1. " INTID779 ,Interrupt ID779 Priority/Priority Byte Offset 779 " hexmask.long.byte 0x00 16.--23. 1. " INTID778 ,Interrupt ID778 Priority/Priority Byte Offset 778 " hexmask.long.byte 0x00 8.--15. 1. " INTID777 ,Interrupt ID777 Priority/Priority Byte Offset 777 " hexmask.long.byte 0x00 0.--7. 1. " INTID776 ,Interrupt ID776 Priority/Priority Byte Offset 776 " group.long 0x70C++0x03 line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" hexmask.long.byte 0x00 24.--31. 1. " INTID783 ,Interrupt ID783 Priority/Priority Byte Offset 783 " hexmask.long.byte 0x00 16.--23. 1. " INTID782 ,Interrupt ID782 Priority/Priority Byte Offset 782 " hexmask.long.byte 0x00 8.--15. 1. " INTID781 ,Interrupt ID781 Priority/Priority Byte Offset 781 " hexmask.long.byte 0x00 0.--7. 1. " INTID780 ,Interrupt ID780 Priority/Priority Byte Offset 780 " group.long 0x710++0x03 line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" hexmask.long.byte 0x00 24.--31. 1. " INTID787 ,Interrupt ID787 Priority/Priority Byte Offset 787 " hexmask.long.byte 0x00 16.--23. 1. " INTID786 ,Interrupt ID786 Priority/Priority Byte Offset 786 " hexmask.long.byte 0x00 8.--15. 1. " INTID785 ,Interrupt ID785 Priority/Priority Byte Offset 785 " hexmask.long.byte 0x00 0.--7. 1. " INTID784 ,Interrupt ID784 Priority/Priority Byte Offset 784 " group.long 0x714++0x03 line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" hexmask.long.byte 0x00 24.--31. 1. " INTID791 ,Interrupt ID791 Priority/Priority Byte Offset 791 " hexmask.long.byte 0x00 16.--23. 1. " INTID790 ,Interrupt ID790 Priority/Priority Byte Offset 790 " hexmask.long.byte 0x00 8.--15. 1. " INTID789 ,Interrupt ID789 Priority/Priority Byte Offset 789 " hexmask.long.byte 0x00 0.--7. 1. " INTID788 ,Interrupt ID788 Priority/Priority Byte Offset 788 " group.long 0x718++0x03 line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" hexmask.long.byte 0x00 24.--31. 1. " INTID795 ,Interrupt ID795 Priority/Priority Byte Offset 795 " hexmask.long.byte 0x00 16.--23. 1. " INTID794 ,Interrupt ID794 Priority/Priority Byte Offset 794 " hexmask.long.byte 0x00 8.--15. 1. " INTID793 ,Interrupt ID793 Priority/Priority Byte Offset 793 " hexmask.long.byte 0x00 0.--7. 1. " INTID792 ,Interrupt ID792 Priority/Priority Byte Offset 792 " group.long 0x71C++0x03 line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" hexmask.long.byte 0x00 24.--31. 1. " INTID799 ,Interrupt ID799 Priority/Priority Byte Offset 799 " hexmask.long.byte 0x00 16.--23. 1. " INTID798 ,Interrupt ID798 Priority/Priority Byte Offset 798 " hexmask.long.byte 0x00 8.--15. 1. " INTID797 ,Interrupt ID797 Priority/Priority Byte Offset 797 " hexmask.long.byte 0x00 0.--7. 1. " INTID796 ,Interrupt ID796 Priority/Priority Byte Offset 796 " else hgroup.long 0x700++0x03 hide.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" hgroup.long 0x704++0x03 hide.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" hgroup.long 0x708++0x03 hide.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" hgroup.long 0x70C++0x03 hide.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" hgroup.long 0x710++0x03 hide.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" hgroup.long 0x714++0x03 hide.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" hgroup.long 0x718++0x03 hide.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" hgroup.long 0x71C++0x03 hide.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x720++0x03 line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" hexmask.long.byte 0x00 24.--31. 1. " INTID803 ,Interrupt ID803 Priority/Priority Byte Offset 803 " hexmask.long.byte 0x00 16.--23. 1. " INTID802 ,Interrupt ID802 Priority/Priority Byte Offset 802 " hexmask.long.byte 0x00 8.--15. 1. " INTID801 ,Interrupt ID801 Priority/Priority Byte Offset 801 " hexmask.long.byte 0x00 0.--7. 1. " INTID800 ,Interrupt ID800 Priority/Priority Byte Offset 800 " group.long 0x724++0x03 line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" hexmask.long.byte 0x00 24.--31. 1. " INTID807 ,Interrupt ID807 Priority/Priority Byte Offset 807 " hexmask.long.byte 0x00 16.--23. 1. " INTID806 ,Interrupt ID806 Priority/Priority Byte Offset 806 " hexmask.long.byte 0x00 8.--15. 1. " INTID805 ,Interrupt ID805 Priority/Priority Byte Offset 805 " hexmask.long.byte 0x00 0.--7. 1. " INTID804 ,Interrupt ID804 Priority/Priority Byte Offset 804 " group.long 0x728++0x03 line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" hexmask.long.byte 0x00 24.--31. 1. " INTID811 ,Interrupt ID811 Priority/Priority Byte Offset 811 " hexmask.long.byte 0x00 16.--23. 1. " INTID810 ,Interrupt ID810 Priority/Priority Byte Offset 810 " hexmask.long.byte 0x00 8.--15. 1. " INTID809 ,Interrupt ID809 Priority/Priority Byte Offset 809 " hexmask.long.byte 0x00 0.--7. 1. " INTID808 ,Interrupt ID808 Priority/Priority Byte Offset 808 " group.long 0x72C++0x03 line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" hexmask.long.byte 0x00 24.--31. 1. " INTID815 ,Interrupt ID815 Priority/Priority Byte Offset 815 " hexmask.long.byte 0x00 16.--23. 1. " INTID814 ,Interrupt ID814 Priority/Priority Byte Offset 814 " hexmask.long.byte 0x00 8.--15. 1. " INTID813 ,Interrupt ID813 Priority/Priority Byte Offset 813 " hexmask.long.byte 0x00 0.--7. 1. " INTID812 ,Interrupt ID812 Priority/Priority Byte Offset 812 " group.long 0x730++0x03 line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" hexmask.long.byte 0x00 24.--31. 1. " INTID819 ,Interrupt ID819 Priority/Priority Byte Offset 819 " hexmask.long.byte 0x00 16.--23. 1. " INTID818 ,Interrupt ID818 Priority/Priority Byte Offset 818 " hexmask.long.byte 0x00 8.--15. 1. " INTID817 ,Interrupt ID817 Priority/Priority Byte Offset 817 " hexmask.long.byte 0x00 0.--7. 1. " INTID816 ,Interrupt ID816 Priority/Priority Byte Offset 816 " group.long 0x734++0x03 line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" hexmask.long.byte 0x00 24.--31. 1. " INTID823 ,Interrupt ID823 Priority/Priority Byte Offset 823 " hexmask.long.byte 0x00 16.--23. 1. " INTID822 ,Interrupt ID822 Priority/Priority Byte Offset 822 " hexmask.long.byte 0x00 8.--15. 1. " INTID821 ,Interrupt ID821 Priority/Priority Byte Offset 821 " hexmask.long.byte 0x00 0.--7. 1. " INTID820 ,Interrupt ID820 Priority/Priority Byte Offset 820 " group.long 0x738++0x03 line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" hexmask.long.byte 0x00 24.--31. 1. " INTID827 ,Interrupt ID827 Priority/Priority Byte Offset 827 " hexmask.long.byte 0x00 16.--23. 1. " INTID826 ,Interrupt ID826 Priority/Priority Byte Offset 826 " hexmask.long.byte 0x00 8.--15. 1. " INTID825 ,Interrupt ID825 Priority/Priority Byte Offset 825 " hexmask.long.byte 0x00 0.--7. 1. " INTID824 ,Interrupt ID824 Priority/Priority Byte Offset 824 " group.long 0x73C++0x03 line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" hexmask.long.byte 0x00 24.--31. 1. " INTID831 ,Interrupt ID831 Priority/Priority Byte Offset 831 " hexmask.long.byte 0x00 16.--23. 1. " INTID830 ,Interrupt ID830 Priority/Priority Byte Offset 830 " hexmask.long.byte 0x00 8.--15. 1. " INTID829 ,Interrupt ID829 Priority/Priority Byte Offset 829 " hexmask.long.byte 0x00 0.--7. 1. " INTID828 ,Interrupt ID828 Priority/Priority Byte Offset 828 " else hgroup.long 0x720++0x03 hide.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" hgroup.long 0x724++0x03 hide.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" hgroup.long 0x728++0x03 hide.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" hgroup.long 0x72C++0x03 hide.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" hgroup.long 0x730++0x03 hide.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" hgroup.long 0x734++0x03 hide.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" hgroup.long 0x738++0x03 hide.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" hgroup.long 0x73C++0x03 hide.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x740++0x03 line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" hexmask.long.byte 0x00 24.--31. 1. " INTID835 ,Interrupt ID835 Priority/Priority Byte Offset 835 " hexmask.long.byte 0x00 16.--23. 1. " INTID834 ,Interrupt ID834 Priority/Priority Byte Offset 834 " hexmask.long.byte 0x00 8.--15. 1. " INTID833 ,Interrupt ID833 Priority/Priority Byte Offset 833 " hexmask.long.byte 0x00 0.--7. 1. " INTID832 ,Interrupt ID832 Priority/Priority Byte Offset 832 " group.long 0x744++0x03 line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" hexmask.long.byte 0x00 24.--31. 1. " INTID839 ,Interrupt ID839 Priority/Priority Byte Offset 839 " hexmask.long.byte 0x00 16.--23. 1. " INTID838 ,Interrupt ID838 Priority/Priority Byte Offset 838 " hexmask.long.byte 0x00 8.--15. 1. " INTID837 ,Interrupt ID837 Priority/Priority Byte Offset 837 " hexmask.long.byte 0x00 0.--7. 1. " INTID836 ,Interrupt ID836 Priority/Priority Byte Offset 836 " group.long 0x748++0x03 line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" hexmask.long.byte 0x00 24.--31. 1. " INTID843 ,Interrupt ID843 Priority/Priority Byte Offset 843 " hexmask.long.byte 0x00 16.--23. 1. " INTID842 ,Interrupt ID842 Priority/Priority Byte Offset 842 " hexmask.long.byte 0x00 8.--15. 1. " INTID841 ,Interrupt ID841 Priority/Priority Byte Offset 841 " hexmask.long.byte 0x00 0.--7. 1. " INTID840 ,Interrupt ID840 Priority/Priority Byte Offset 840 " group.long 0x74C++0x03 line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" hexmask.long.byte 0x00 24.--31. 1. " INTID847 ,Interrupt ID847 Priority/Priority Byte Offset 847 " hexmask.long.byte 0x00 16.--23. 1. " INTID846 ,Interrupt ID846 Priority/Priority Byte Offset 846 " hexmask.long.byte 0x00 8.--15. 1. " INTID845 ,Interrupt ID845 Priority/Priority Byte Offset 845 " hexmask.long.byte 0x00 0.--7. 1. " INTID844 ,Interrupt ID844 Priority/Priority Byte Offset 844 " group.long 0x750++0x03 line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" hexmask.long.byte 0x00 24.--31. 1. " INTID851 ,Interrupt ID851 Priority/Priority Byte Offset 851 " hexmask.long.byte 0x00 16.--23. 1. " INTID850 ,Interrupt ID850 Priority/Priority Byte Offset 850 " hexmask.long.byte 0x00 8.--15. 1. " INTID849 ,Interrupt ID849 Priority/Priority Byte Offset 849 " hexmask.long.byte 0x00 0.--7. 1. " INTID848 ,Interrupt ID848 Priority/Priority Byte Offset 848 " group.long 0x754++0x03 line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" hexmask.long.byte 0x00 24.--31. 1. " INTID855 ,Interrupt ID855 Priority/Priority Byte Offset 855 " hexmask.long.byte 0x00 16.--23. 1. " INTID854 ,Interrupt ID854 Priority/Priority Byte Offset 854 " hexmask.long.byte 0x00 8.--15. 1. " INTID853 ,Interrupt ID853 Priority/Priority Byte Offset 853 " hexmask.long.byte 0x00 0.--7. 1. " INTID852 ,Interrupt ID852 Priority/Priority Byte Offset 852 " group.long 0x758++0x03 line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" hexmask.long.byte 0x00 24.--31. 1. " INTID859 ,Interrupt ID859 Priority/Priority Byte Offset 859 " hexmask.long.byte 0x00 16.--23. 1. " INTID858 ,Interrupt ID858 Priority/Priority Byte Offset 858 " hexmask.long.byte 0x00 8.--15. 1. " INTID857 ,Interrupt ID857 Priority/Priority Byte Offset 857 " hexmask.long.byte 0x00 0.--7. 1. " INTID856 ,Interrupt ID856 Priority/Priority Byte Offset 856 " group.long 0x75C++0x03 line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" hexmask.long.byte 0x00 24.--31. 1. " INTID863 ,Interrupt ID863 Priority/Priority Byte Offset 863 " hexmask.long.byte 0x00 16.--23. 1. " INTID862 ,Interrupt ID862 Priority/Priority Byte Offset 862 " hexmask.long.byte 0x00 8.--15. 1. " INTID861 ,Interrupt ID861 Priority/Priority Byte Offset 861 " hexmask.long.byte 0x00 0.--7. 1. " INTID860 ,Interrupt ID860 Priority/Priority Byte Offset 860 " else hgroup.long 0x740++0x03 hide.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" hgroup.long 0x744++0x03 hide.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" hgroup.long 0x748++0x03 hide.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" hgroup.long 0x74C++0x03 hide.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" hgroup.long 0x750++0x03 hide.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" hgroup.long 0x754++0x03 hide.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" hgroup.long 0x758++0x03 hide.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" hgroup.long 0x75C++0x03 hide.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x760++0x03 line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" hexmask.long.byte 0x00 24.--31. 1. " INTID867 ,Interrupt ID867 Priority/Priority Byte Offset 867 " hexmask.long.byte 0x00 16.--23. 1. " INTID866 ,Interrupt ID866 Priority/Priority Byte Offset 866 " hexmask.long.byte 0x00 8.--15. 1. " INTID865 ,Interrupt ID865 Priority/Priority Byte Offset 865 " hexmask.long.byte 0x00 0.--7. 1. " INTID864 ,Interrupt ID864 Priority/Priority Byte Offset 864 " group.long 0x764++0x03 line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" hexmask.long.byte 0x00 24.--31. 1. " INTID871 ,Interrupt ID871 Priority/Priority Byte Offset 871 " hexmask.long.byte 0x00 16.--23. 1. " INTID870 ,Interrupt ID870 Priority/Priority Byte Offset 870 " hexmask.long.byte 0x00 8.--15. 1. " INTID869 ,Interrupt ID869 Priority/Priority Byte Offset 869 " hexmask.long.byte 0x00 0.--7. 1. " INTID868 ,Interrupt ID868 Priority/Priority Byte Offset 868 " group.long 0x768++0x03 line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" hexmask.long.byte 0x00 24.--31. 1. " INTID875 ,Interrupt ID875 Priority/Priority Byte Offset 875 " hexmask.long.byte 0x00 16.--23. 1. " INTID874 ,Interrupt ID874 Priority/Priority Byte Offset 874 " hexmask.long.byte 0x00 8.--15. 1. " INTID873 ,Interrupt ID873 Priority/Priority Byte Offset 873 " hexmask.long.byte 0x00 0.--7. 1. " INTID872 ,Interrupt ID872 Priority/Priority Byte Offset 872 " group.long 0x76C++0x03 line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" hexmask.long.byte 0x00 24.--31. 1. " INTID879 ,Interrupt ID879 Priority/Priority Byte Offset 879 " hexmask.long.byte 0x00 16.--23. 1. " INTID878 ,Interrupt ID878 Priority/Priority Byte Offset 878 " hexmask.long.byte 0x00 8.--15. 1. " INTID877 ,Interrupt ID877 Priority/Priority Byte Offset 877 " hexmask.long.byte 0x00 0.--7. 1. " INTID876 ,Interrupt ID876 Priority/Priority Byte Offset 876 " group.long 0x770++0x03 line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" hexmask.long.byte 0x00 24.--31. 1. " INTID883 ,Interrupt ID883 Priority/Priority Byte Offset 883 " hexmask.long.byte 0x00 16.--23. 1. " INTID882 ,Interrupt ID882 Priority/Priority Byte Offset 882 " hexmask.long.byte 0x00 8.--15. 1. " INTID881 ,Interrupt ID881 Priority/Priority Byte Offset 881 " hexmask.long.byte 0x00 0.--7. 1. " INTID880 ,Interrupt ID880 Priority/Priority Byte Offset 880 " group.long 0x774++0x03 line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" hexmask.long.byte 0x00 24.--31. 1. " INTID887 ,Interrupt ID887 Priority/Priority Byte Offset 887 " hexmask.long.byte 0x00 16.--23. 1. " INTID886 ,Interrupt ID886 Priority/Priority Byte Offset 886 " hexmask.long.byte 0x00 8.--15. 1. " INTID885 ,Interrupt ID885 Priority/Priority Byte Offset 885 " hexmask.long.byte 0x00 0.--7. 1. " INTID884 ,Interrupt ID884 Priority/Priority Byte Offset 884 " group.long 0x778++0x03 line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" hexmask.long.byte 0x00 24.--31. 1. " INTID891 ,Interrupt ID891 Priority/Priority Byte Offset 891 " hexmask.long.byte 0x00 16.--23. 1. " INTID890 ,Interrupt ID890 Priority/Priority Byte Offset 890 " hexmask.long.byte 0x00 8.--15. 1. " INTID889 ,Interrupt ID889 Priority/Priority Byte Offset 889 " hexmask.long.byte 0x00 0.--7. 1. " INTID888 ,Interrupt ID888 Priority/Priority Byte Offset 888 " group.long 0x77C++0x03 line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" hexmask.long.byte 0x00 24.--31. 1. " INTID895 ,Interrupt ID895 Priority/Priority Byte Offset 895 " hexmask.long.byte 0x00 16.--23. 1. " INTID894 ,Interrupt ID894 Priority/Priority Byte Offset 894 " hexmask.long.byte 0x00 8.--15. 1. " INTID893 ,Interrupt ID893 Priority/Priority Byte Offset 893 " hexmask.long.byte 0x00 0.--7. 1. " INTID892 ,Interrupt ID892 Priority/Priority Byte Offset 892 " else hgroup.long 0x760++0x03 hide.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" hgroup.long 0x764++0x03 hide.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" hgroup.long 0x768++0x03 hide.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" hgroup.long 0x76C++0x03 hide.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" hgroup.long 0x770++0x03 hide.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" hgroup.long 0x774++0x03 hide.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" hgroup.long 0x778++0x03 hide.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" hgroup.long 0x77C++0x03 hide.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x780++0x03 line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" hexmask.long.byte 0x00 24.--31. 1. " INTID899 ,Interrupt ID899 Priority/Priority Byte Offset 899 " hexmask.long.byte 0x00 16.--23. 1. " INTID898 ,Interrupt ID898 Priority/Priority Byte Offset 898 " hexmask.long.byte 0x00 8.--15. 1. " INTID897 ,Interrupt ID897 Priority/Priority Byte Offset 897 " hexmask.long.byte 0x00 0.--7. 1. " INTID896 ,Interrupt ID896 Priority/Priority Byte Offset 896 " group.long 0x784++0x03 line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" hexmask.long.byte 0x00 24.--31. 1. " INTID903 ,Interrupt ID903 Priority/Priority Byte Offset 903 " hexmask.long.byte 0x00 16.--23. 1. " INTID902 ,Interrupt ID902 Priority/Priority Byte Offset 902 " hexmask.long.byte 0x00 8.--15. 1. " INTID901 ,Interrupt ID901 Priority/Priority Byte Offset 901 " hexmask.long.byte 0x00 0.--7. 1. " INTID900 ,Interrupt ID900 Priority/Priority Byte Offset 900 " group.long 0x788++0x03 line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" hexmask.long.byte 0x00 24.--31. 1. " INTID907 ,Interrupt ID907 Priority/Priority Byte Offset 907 " hexmask.long.byte 0x00 16.--23. 1. " INTID906 ,Interrupt ID906 Priority/Priority Byte Offset 906 " hexmask.long.byte 0x00 8.--15. 1. " INTID905 ,Interrupt ID905 Priority/Priority Byte Offset 905 " hexmask.long.byte 0x00 0.--7. 1. " INTID904 ,Interrupt ID904 Priority/Priority Byte Offset 904 " group.long 0x78C++0x03 line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" hexmask.long.byte 0x00 24.--31. 1. " INTID911 ,Interrupt ID911 Priority/Priority Byte Offset 911 " hexmask.long.byte 0x00 16.--23. 1. " INTID910 ,Interrupt ID910 Priority/Priority Byte Offset 910 " hexmask.long.byte 0x00 8.--15. 1. " INTID909 ,Interrupt ID909 Priority/Priority Byte Offset 909 " hexmask.long.byte 0x00 0.--7. 1. " INTID908 ,Interrupt ID908 Priority/Priority Byte Offset 908 " group.long 0x790++0x03 line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" hexmask.long.byte 0x00 24.--31. 1. " INTID915 ,Interrupt ID915 Priority/Priority Byte Offset 915 " hexmask.long.byte 0x00 16.--23. 1. " INTID914 ,Interrupt ID914 Priority/Priority Byte Offset 914 " hexmask.long.byte 0x00 8.--15. 1. " INTID913 ,Interrupt ID913 Priority/Priority Byte Offset 913 " hexmask.long.byte 0x00 0.--7. 1. " INTID912 ,Interrupt ID912 Priority/Priority Byte Offset 912 " group.long 0x794++0x03 line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" hexmask.long.byte 0x00 24.--31. 1. " INTID919 ,Interrupt ID919 Priority/Priority Byte Offset 919 " hexmask.long.byte 0x00 16.--23. 1. " INTID918 ,Interrupt ID918 Priority/Priority Byte Offset 918 " hexmask.long.byte 0x00 8.--15. 1. " INTID917 ,Interrupt ID917 Priority/Priority Byte Offset 917 " hexmask.long.byte 0x00 0.--7. 1. " INTID916 ,Interrupt ID916 Priority/Priority Byte Offset 916 " group.long 0x798++0x03 line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" hexmask.long.byte 0x00 24.--31. 1. " INTID923 ,Interrupt ID923 Priority/Priority Byte Offset 923 " hexmask.long.byte 0x00 16.--23. 1. " INTID922 ,Interrupt ID922 Priority/Priority Byte Offset 922 " hexmask.long.byte 0x00 8.--15. 1. " INTID921 ,Interrupt ID921 Priority/Priority Byte Offset 921 " hexmask.long.byte 0x00 0.--7. 1. " INTID920 ,Interrupt ID920 Priority/Priority Byte Offset 920 " group.long 0x79C++0x03 line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" hexmask.long.byte 0x00 24.--31. 1. " INTID927 ,Interrupt ID927 Priority/Priority Byte Offset 927 " hexmask.long.byte 0x00 16.--23. 1. " INTID926 ,Interrupt ID926 Priority/Priority Byte Offset 926 " hexmask.long.byte 0x00 8.--15. 1. " INTID925 ,Interrupt ID925 Priority/Priority Byte Offset 925 " hexmask.long.byte 0x00 0.--7. 1. " INTID924 ,Interrupt ID924 Priority/Priority Byte Offset 924 " else hgroup.long 0x780++0x03 hide.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" hgroup.long 0x784++0x03 hide.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" hgroup.long 0x788++0x03 hide.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" hgroup.long 0x78C++0x03 hide.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" hgroup.long 0x790++0x03 hide.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" hgroup.long 0x794++0x03 hide.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" hgroup.long 0x798++0x03 hide.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" hgroup.long 0x79C++0x03 hide.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x7A0++0x03 line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" hexmask.long.byte 0x00 24.--31. 1. " INTID931 ,Interrupt ID931 Priority/Priority Byte Offset 931 " hexmask.long.byte 0x00 16.--23. 1. " INTID930 ,Interrupt ID930 Priority/Priority Byte Offset 930 " hexmask.long.byte 0x00 8.--15. 1. " INTID929 ,Interrupt ID929 Priority/Priority Byte Offset 929 " hexmask.long.byte 0x00 0.--7. 1. " INTID928 ,Interrupt ID928 Priority/Priority Byte Offset 928 " group.long 0x7A4++0x03 line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" hexmask.long.byte 0x00 24.--31. 1. " INTID935 ,Interrupt ID935 Priority/Priority Byte Offset 935 " hexmask.long.byte 0x00 16.--23. 1. " INTID934 ,Interrupt ID934 Priority/Priority Byte Offset 934 " hexmask.long.byte 0x00 8.--15. 1. " INTID933 ,Interrupt ID933 Priority/Priority Byte Offset 933 " hexmask.long.byte 0x00 0.--7. 1. " INTID932 ,Interrupt ID932 Priority/Priority Byte Offset 932 " group.long 0x7A8++0x03 line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" hexmask.long.byte 0x00 24.--31. 1. " INTID939 ,Interrupt ID939 Priority/Priority Byte Offset 939 " hexmask.long.byte 0x00 16.--23. 1. " INTID938 ,Interrupt ID938 Priority/Priority Byte Offset 938 " hexmask.long.byte 0x00 8.--15. 1. " INTID937 ,Interrupt ID937 Priority/Priority Byte Offset 937 " hexmask.long.byte 0x00 0.--7. 1. " INTID936 ,Interrupt ID936 Priority/Priority Byte Offset 936 " group.long 0x7AC++0x03 line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" hexmask.long.byte 0x00 24.--31. 1. " INTID943 ,Interrupt ID943 Priority/Priority Byte Offset 943 " hexmask.long.byte 0x00 16.--23. 1. " INTID942 ,Interrupt ID942 Priority/Priority Byte Offset 942 " hexmask.long.byte 0x00 8.--15. 1. " INTID941 ,Interrupt ID941 Priority/Priority Byte Offset 941 " hexmask.long.byte 0x00 0.--7. 1. " INTID940 ,Interrupt ID940 Priority/Priority Byte Offset 940 " group.long 0x7B0++0x03 line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" hexmask.long.byte 0x00 24.--31. 1. " INTID947 ,Interrupt ID947 Priority/Priority Byte Offset 947 " hexmask.long.byte 0x00 16.--23. 1. " INTID946 ,Interrupt ID946 Priority/Priority Byte Offset 946 " hexmask.long.byte 0x00 8.--15. 1. " INTID945 ,Interrupt ID945 Priority/Priority Byte Offset 945 " hexmask.long.byte 0x00 0.--7. 1. " INTID944 ,Interrupt ID944 Priority/Priority Byte Offset 944 " group.long 0x7B4++0x03 line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" hexmask.long.byte 0x00 24.--31. 1. " INTID951 ,Interrupt ID951 Priority/Priority Byte Offset 951 " hexmask.long.byte 0x00 16.--23. 1. " INTID950 ,Interrupt ID950 Priority/Priority Byte Offset 950 " hexmask.long.byte 0x00 8.--15. 1. " INTID949 ,Interrupt ID949 Priority/Priority Byte Offset 949 " hexmask.long.byte 0x00 0.--7. 1. " INTID948 ,Interrupt ID948 Priority/Priority Byte Offset 948 " group.long 0x7B8++0x03 line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" hexmask.long.byte 0x00 24.--31. 1. " INTID955 ,Interrupt ID955 Priority/Priority Byte Offset 955 " hexmask.long.byte 0x00 16.--23. 1. " INTID954 ,Interrupt ID954 Priority/Priority Byte Offset 954 " hexmask.long.byte 0x00 8.--15. 1. " INTID953 ,Interrupt ID953 Priority/Priority Byte Offset 953 " hexmask.long.byte 0x00 0.--7. 1. " INTID952 ,Interrupt ID952 Priority/Priority Byte Offset 952 " group.long 0x7BC++0x03 line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" hexmask.long.byte 0x00 24.--31. 1. " INTID959 ,Interrupt ID959 Priority/Priority Byte Offset 959 " hexmask.long.byte 0x00 16.--23. 1. " INTID958 ,Interrupt ID958 Priority/Priority Byte Offset 958 " hexmask.long.byte 0x00 8.--15. 1. " INTID957 ,Interrupt ID957 Priority/Priority Byte Offset 957 " hexmask.long.byte 0x00 0.--7. 1. " INTID956 ,Interrupt ID956 Priority/Priority Byte Offset 956 " else hgroup.long 0x7A0++0x03 hide.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" hgroup.long 0x7A4++0x03 hide.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" hgroup.long 0x7A8++0x03 hide.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" hgroup.long 0x7AC++0x03 hide.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" hgroup.long 0x7B0++0x03 hide.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" hgroup.long 0x7B4++0x03 hide.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" hgroup.long 0x7B8++0x03 hide.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" hgroup.long 0x7BC++0x03 hide.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x7C0++0x03 line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" hexmask.long.byte 0x00 24.--31. 1. " INTID963 ,Interrupt ID963 Priority/Priority Byte Offset 963 " hexmask.long.byte 0x00 16.--23. 1. " INTID962 ,Interrupt ID962 Priority/Priority Byte Offset 962 " hexmask.long.byte 0x00 8.--15. 1. " INTID961 ,Interrupt ID961 Priority/Priority Byte Offset 961 " hexmask.long.byte 0x00 0.--7. 1. " INTID960 ,Interrupt ID960 Priority/Priority Byte Offset 960 " group.long 0x7C4++0x03 line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" hexmask.long.byte 0x00 24.--31. 1. " INTID967 ,Interrupt ID967 Priority/Priority Byte Offset 967 " hexmask.long.byte 0x00 16.--23. 1. " INTID966 ,Interrupt ID966 Priority/Priority Byte Offset 966 " hexmask.long.byte 0x00 8.--15. 1. " INTID965 ,Interrupt ID965 Priority/Priority Byte Offset 965 " hexmask.long.byte 0x00 0.--7. 1. " INTID964 ,Interrupt ID964 Priority/Priority Byte Offset 964 " group.long 0x7C8++0x03 line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" hexmask.long.byte 0x00 24.--31. 1. " INTID971 ,Interrupt ID971 Priority/Priority Byte Offset 971 " hexmask.long.byte 0x00 16.--23. 1. " INTID970 ,Interrupt ID970 Priority/Priority Byte Offset 970 " hexmask.long.byte 0x00 8.--15. 1. " INTID969 ,Interrupt ID969 Priority/Priority Byte Offset 969 " hexmask.long.byte 0x00 0.--7. 1. " INTID968 ,Interrupt ID968 Priority/Priority Byte Offset 968 " group.long 0x7CC++0x03 line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" hexmask.long.byte 0x00 24.--31. 1. " INTID975 ,Interrupt ID975 Priority/Priority Byte Offset 975 " hexmask.long.byte 0x00 16.--23. 1. " INTID974 ,Interrupt ID974 Priority/Priority Byte Offset 974 " hexmask.long.byte 0x00 8.--15. 1. " INTID973 ,Interrupt ID973 Priority/Priority Byte Offset 973 " hexmask.long.byte 0x00 0.--7. 1. " INTID972 ,Interrupt ID972 Priority/Priority Byte Offset 972 " group.long 0x7D0++0x03 line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" hexmask.long.byte 0x00 24.--31. 1. " INTID979 ,Interrupt ID979 Priority/Priority Byte Offset 979 " hexmask.long.byte 0x00 16.--23. 1. " INTID978 ,Interrupt ID978 Priority/Priority Byte Offset 978 " hexmask.long.byte 0x00 8.--15. 1. " INTID977 ,Interrupt ID977 Priority/Priority Byte Offset 977 " hexmask.long.byte 0x00 0.--7. 1. " INTID976 ,Interrupt ID976 Priority/Priority Byte Offset 976 " group.long 0x7D4++0x03 line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" hexmask.long.byte 0x00 24.--31. 1. " INTID983 ,Interrupt ID983 Priority/Priority Byte Offset 983 " hexmask.long.byte 0x00 16.--23. 1. " INTID982 ,Interrupt ID982 Priority/Priority Byte Offset 982 " hexmask.long.byte 0x00 8.--15. 1. " INTID981 ,Interrupt ID981 Priority/Priority Byte Offset 981 " hexmask.long.byte 0x00 0.--7. 1. " INTID980 ,Interrupt ID980 Priority/Priority Byte Offset 980 " group.long 0x7D8++0x03 line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" hexmask.long.byte 0x00 24.--31. 1. " INTID987 ,Interrupt ID987 Priority/Priority Byte Offset 987 " hexmask.long.byte 0x00 16.--23. 1. " INTID986 ,Interrupt ID986 Priority/Priority Byte Offset 986 " hexmask.long.byte 0x00 8.--15. 1. " INTID985 ,Interrupt ID985 Priority/Priority Byte Offset 985 " hexmask.long.byte 0x00 0.--7. 1. " INTID984 ,Interrupt ID984 Priority/Priority Byte Offset 984 " group.long 0x7DC++0x03 line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" hexmask.long.byte 0x00 24.--31. 1. " INTID991 ,Interrupt ID991 Priority/Priority Byte Offset 991 " hexmask.long.byte 0x00 16.--23. 1. " INTID990 ,Interrupt ID990 Priority/Priority Byte Offset 990 " hexmask.long.byte 0x00 8.--15. 1. " INTID989 ,Interrupt ID989 Priority/Priority Byte Offset 989 " hexmask.long.byte 0x00 0.--7. 1. " INTID988 ,Interrupt ID988 Priority/Priority Byte Offset 988 " else hgroup.long 0x7C0++0x03 hide.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" hgroup.long 0x7C4++0x03 hide.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" hgroup.long 0x7C8++0x03 hide.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" hgroup.long 0x7CC++0x03 hide.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" hgroup.long 0x7D0++0x03 hide.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" hgroup.long 0x7D4++0x03 hide.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" hgroup.long 0x7D8++0x03 hide.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" hgroup.long 0x7DC++0x03 hide.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" endif tree.end width 19. tree "Interrupt Targets Registers" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x000000E0)>0x1) hgroup.long 0x800++0x03 hide.long 0x00 "GICD_ITARGETSR0,Interrupt Processor Targets Register 0" hgroup.long 0x804++0x03 hide.long 0x00 "GICD_ITARGETSR1,Interrupt Processor Targets Register 1" hgroup.long 0x808++0x03 hide.long 0x00 "GICD_ITARGETSR2,Interrupt Processor Targets Register 2" hgroup.long 0x80C++0x03 hide.long 0x00 "GICD_ITARGETSR3,Interrupt Processor Targets Register 3" hgroup.long 0x810++0x03 hide.long 0x00 "GICD_ITARGETSR4,Interrupt Processor Targets Register 4" hgroup.long 0x814++0x03 hide.long 0x00 "GICD_ITARGETSR5,Interrupt Processor Targets Register 5" hgroup.long 0x818++0x03 hide.long 0x00 "GICD_ITARGETSR6,Interrupt Processor Targets Register 6" hgroup.long 0x81C++0x03 hide.long 0x00 "GICD_ITARGETSR7,Interrupt Processor Targets Register 7" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x820++0x03 line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO35 ,CPU Targets Byte Offset 35 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO34 ,CPU Targets Byte Offset 34 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO33 ,CPU Targets Byte Offset 33 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO32 ,CPU Targets Byte Offset 32 " group.long 0x824++0x03 line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO39 ,CPU Targets Byte Offset 39 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO38 ,CPU Targets Byte Offset 38 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO37 ,CPU Targets Byte Offset 37 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO36 ,CPU Targets Byte Offset 36 " group.long 0x828++0x03 line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO43 ,CPU Targets Byte Offset 43 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO42 ,CPU Targets Byte Offset 42 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO41 ,CPU Targets Byte Offset 41 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO40 ,CPU Targets Byte Offset 40 " group.long 0x82C++0x03 line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO47 ,CPU Targets Byte Offset 47 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO46 ,CPU Targets Byte Offset 46 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO45 ,CPU Targets Byte Offset 45 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO44 ,CPU Targets Byte Offset 44 " group.long 0x830++0x03 line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO51 ,CPU Targets Byte Offset 51 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO50 ,CPU Targets Byte Offset 50 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO49 ,CPU Targets Byte Offset 49 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO48 ,CPU Targets Byte Offset 48 " group.long 0x834++0x03 line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO55 ,CPU Targets Byte Offset 55 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO54 ,CPU Targets Byte Offset 54 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO53 ,CPU Targets Byte Offset 53 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO52 ,CPU Targets Byte Offset 52 " group.long 0x838++0x03 line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO59 ,CPU Targets Byte Offset 59 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO58 ,CPU Targets Byte Offset 58 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO57 ,CPU Targets Byte Offset 57 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO56 ,CPU Targets Byte Offset 56 " group.long 0x83C++0x03 line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO63 ,CPU Targets Byte Offset 63 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO62 ,CPU Targets Byte Offset 62 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO61 ,CPU Targets Byte Offset 61 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO60 ,CPU Targets Byte Offset 60 " else hgroup.long 0x820++0x03 hide.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8" hgroup.long 0x824++0x03 hide.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9" hgroup.long 0x828++0x03 hide.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10" hgroup.long 0x82C++0x03 hide.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11" hgroup.long 0x830++0x03 hide.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12" hgroup.long 0x834++0x03 hide.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13" hgroup.long 0x838++0x03 hide.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14" hgroup.long 0x83C++0x03 hide.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x840++0x03 line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO67 ,CPU Targets Byte Offset 67 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO66 ,CPU Targets Byte Offset 66 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO65 ,CPU Targets Byte Offset 65 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO64 ,CPU Targets Byte Offset 64 " group.long 0x844++0x03 line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO71 ,CPU Targets Byte Offset 71 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO70 ,CPU Targets Byte Offset 70 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO69 ,CPU Targets Byte Offset 69 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO68 ,CPU Targets Byte Offset 68 " group.long 0x848++0x03 line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO75 ,CPU Targets Byte Offset 75 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO74 ,CPU Targets Byte Offset 74 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO73 ,CPU Targets Byte Offset 73 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO72 ,CPU Targets Byte Offset 72 " group.long 0x84C++0x03 line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO79 ,CPU Targets Byte Offset 79 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO78 ,CPU Targets Byte Offset 78 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO77 ,CPU Targets Byte Offset 77 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO76 ,CPU Targets Byte Offset 76 " group.long 0x850++0x03 line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO83 ,CPU Targets Byte Offset 83 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO82 ,CPU Targets Byte Offset 82 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO81 ,CPU Targets Byte Offset 81 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO80 ,CPU Targets Byte Offset 80 " group.long 0x854++0x03 line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO87 ,CPU Targets Byte Offset 87 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO86 ,CPU Targets Byte Offset 86 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO85 ,CPU Targets Byte Offset 85 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO84 ,CPU Targets Byte Offset 84 " group.long 0x858++0x03 line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO91 ,CPU Targets Byte Offset 91 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO90 ,CPU Targets Byte Offset 90 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO89 ,CPU Targets Byte Offset 89 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO88 ,CPU Targets Byte Offset 88 " group.long 0x85C++0x03 line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO95 ,CPU Targets Byte Offset 95 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO94 ,CPU Targets Byte Offset 94 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO93 ,CPU Targets Byte Offset 93 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO92 ,CPU Targets Byte Offset 92 " else hgroup.long 0x840++0x03 hide.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16" hgroup.long 0x844++0x03 hide.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17" hgroup.long 0x848++0x03 hide.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18" hgroup.long 0x84C++0x03 hide.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19" hgroup.long 0x850++0x03 hide.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20" hgroup.long 0x854++0x03 hide.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21" hgroup.long 0x858++0x03 hide.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22" hgroup.long 0x85C++0x03 hide.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x860++0x03 line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO99 ,CPU Targets Byte Offset 99 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO98 ,CPU Targets Byte Offset 98 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO97 ,CPU Targets Byte Offset 97 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO96 ,CPU Targets Byte Offset 96 " group.long 0x864++0x03 line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO103 ,CPU Targets Byte Offset 103 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO102 ,CPU Targets Byte Offset 102 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO101 ,CPU Targets Byte Offset 101 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO100 ,CPU Targets Byte Offset 100 " group.long 0x868++0x03 line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO107 ,CPU Targets Byte Offset 107 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO106 ,CPU Targets Byte Offset 106 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO105 ,CPU Targets Byte Offset 105 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO104 ,CPU Targets Byte Offset 104 " group.long 0x86C++0x03 line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO111 ,CPU Targets Byte Offset 111 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO110 ,CPU Targets Byte Offset 110 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO109 ,CPU Targets Byte Offset 109 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO108 ,CPU Targets Byte Offset 108 " group.long 0x870++0x03 line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO115 ,CPU Targets Byte Offset 115 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO114 ,CPU Targets Byte Offset 114 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO113 ,CPU Targets Byte Offset 113 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO112 ,CPU Targets Byte Offset 112 " group.long 0x874++0x03 line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO119 ,CPU Targets Byte Offset 119 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO118 ,CPU Targets Byte Offset 118 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO117 ,CPU Targets Byte Offset 117 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO116 ,CPU Targets Byte Offset 116 " group.long 0x878++0x03 line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO123 ,CPU Targets Byte Offset 123 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO122 ,CPU Targets Byte Offset 122 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO121 ,CPU Targets Byte Offset 121 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO120 ,CPU Targets Byte Offset 120 " group.long 0x87C++0x03 line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO127 ,CPU Targets Byte Offset 127 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO126 ,CPU Targets Byte Offset 126 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO125 ,CPU Targets Byte Offset 125 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO124 ,CPU Targets Byte Offset 124 " else hgroup.long 0x860++0x03 hide.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24" hgroup.long 0x864++0x03 hide.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25" hgroup.long 0x868++0x03 hide.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26" hgroup.long 0x86C++0x03 hide.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27" hgroup.long 0x870++0x03 hide.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28" hgroup.long 0x874++0x03 hide.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29" hgroup.long 0x878++0x03 hide.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30" hgroup.long 0x87C++0x03 hide.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x880++0x03 line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO131 ,CPU Targets Byte Offset 131 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO130 ,CPU Targets Byte Offset 130 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO129 ,CPU Targets Byte Offset 129 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO128 ,CPU Targets Byte Offset 128 " group.long 0x884++0x03 line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO135 ,CPU Targets Byte Offset 135 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO134 ,CPU Targets Byte Offset 134 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO133 ,CPU Targets Byte Offset 133 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO132 ,CPU Targets Byte Offset 132 " group.long 0x888++0x03 line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO139 ,CPU Targets Byte Offset 139 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO138 ,CPU Targets Byte Offset 138 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO137 ,CPU Targets Byte Offset 137 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO136 ,CPU Targets Byte Offset 136 " group.long 0x88C++0x03 line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO143 ,CPU Targets Byte Offset 143 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO142 ,CPU Targets Byte Offset 142 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO141 ,CPU Targets Byte Offset 141 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO140 ,CPU Targets Byte Offset 140 " group.long 0x890++0x03 line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO147 ,CPU Targets Byte Offset 147 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO146 ,CPU Targets Byte Offset 146 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO145 ,CPU Targets Byte Offset 145 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO144 ,CPU Targets Byte Offset 144 " group.long 0x894++0x03 line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO151 ,CPU Targets Byte Offset 151 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO150 ,CPU Targets Byte Offset 150 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO149 ,CPU Targets Byte Offset 149 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO148 ,CPU Targets Byte Offset 148 " group.long 0x898++0x03 line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO155 ,CPU Targets Byte Offset 155 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO154 ,CPU Targets Byte Offset 154 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO153 ,CPU Targets Byte Offset 153 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO152 ,CPU Targets Byte Offset 152 " group.long 0x89C++0x03 line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO159 ,CPU Targets Byte Offset 159 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO158 ,CPU Targets Byte Offset 158 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO157 ,CPU Targets Byte Offset 157 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO156 ,CPU Targets Byte Offset 156 " else hgroup.long 0x880++0x03 hide.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32" hgroup.long 0x884++0x03 hide.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33" hgroup.long 0x888++0x03 hide.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34" hgroup.long 0x88C++0x03 hide.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35" hgroup.long 0x890++0x03 hide.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36" hgroup.long 0x894++0x03 hide.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37" hgroup.long 0x898++0x03 hide.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38" hgroup.long 0x89C++0x03 hide.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x8A0++0x03 line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO163 ,CPU Targets Byte Offset 163 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO162 ,CPU Targets Byte Offset 162 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO161 ,CPU Targets Byte Offset 161 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO160 ,CPU Targets Byte Offset 160 " group.long 0x8A4++0x03 line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO167 ,CPU Targets Byte Offset 167 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO166 ,CPU Targets Byte Offset 166 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO165 ,CPU Targets Byte Offset 165 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO164 ,CPU Targets Byte Offset 164 " group.long 0x8A8++0x03 line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO171 ,CPU Targets Byte Offset 171 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO170 ,CPU Targets Byte Offset 170 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO169 ,CPU Targets Byte Offset 169 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO168 ,CPU Targets Byte Offset 168 " group.long 0x8AC++0x03 line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO175 ,CPU Targets Byte Offset 175 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO174 ,CPU Targets Byte Offset 174 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO173 ,CPU Targets Byte Offset 173 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO172 ,CPU Targets Byte Offset 172 " group.long 0x8B0++0x03 line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO179 ,CPU Targets Byte Offset 179 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO178 ,CPU Targets Byte Offset 178 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO177 ,CPU Targets Byte Offset 177 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO176 ,CPU Targets Byte Offset 176 " group.long 0x8B4++0x03 line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO183 ,CPU Targets Byte Offset 183 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO182 ,CPU Targets Byte Offset 182 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO181 ,CPU Targets Byte Offset 181 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO180 ,CPU Targets Byte Offset 180 " group.long 0x8B8++0x03 line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO187 ,CPU Targets Byte Offset 187 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO186 ,CPU Targets Byte Offset 186 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO185 ,CPU Targets Byte Offset 185 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO184 ,CPU Targets Byte Offset 184 " group.long 0x8BC++0x03 line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO191 ,CPU Targets Byte Offset 191 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO190 ,CPU Targets Byte Offset 190 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO189 ,CPU Targets Byte Offset 189 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO188 ,CPU Targets Byte Offset 188 " else hgroup.long 0x8A0++0x03 hide.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40" hgroup.long 0x8A4++0x03 hide.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41" hgroup.long 0x8A8++0x03 hide.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42" hgroup.long 0x8AC++0x03 hide.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43" hgroup.long 0x8B0++0x03 hide.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44" hgroup.long 0x8B4++0x03 hide.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45" hgroup.long 0x8B8++0x03 hide.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46" hgroup.long 0x8BC++0x03 hide.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x8C0++0x03 line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO195 ,CPU Targets Byte Offset 195 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO194 ,CPU Targets Byte Offset 194 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO193 ,CPU Targets Byte Offset 193 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO192 ,CPU Targets Byte Offset 192 " group.long 0x8C4++0x03 line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO199 ,CPU Targets Byte Offset 199 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO198 ,CPU Targets Byte Offset 198 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO197 ,CPU Targets Byte Offset 197 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO196 ,CPU Targets Byte Offset 196 " group.long 0x8C8++0x03 line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO203 ,CPU Targets Byte Offset 203 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO202 ,CPU Targets Byte Offset 202 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO201 ,CPU Targets Byte Offset 201 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO200 ,CPU Targets Byte Offset 200 " group.long 0x8CC++0x03 line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO207 ,CPU Targets Byte Offset 207 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO206 ,CPU Targets Byte Offset 206 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO205 ,CPU Targets Byte Offset 205 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO204 ,CPU Targets Byte Offset 204 " group.long 0x8D0++0x03 line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO211 ,CPU Targets Byte Offset 211 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO210 ,CPU Targets Byte Offset 210 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO209 ,CPU Targets Byte Offset 209 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO208 ,CPU Targets Byte Offset 208 " group.long 0x8D4++0x03 line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO215 ,CPU Targets Byte Offset 215 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO214 ,CPU Targets Byte Offset 214 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO213 ,CPU Targets Byte Offset 213 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO212 ,CPU Targets Byte Offset 212 " group.long 0x8D8++0x03 line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO219 ,CPU Targets Byte Offset 219 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO218 ,CPU Targets Byte Offset 218 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO217 ,CPU Targets Byte Offset 217 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO216 ,CPU Targets Byte Offset 216 " group.long 0x8DC++0x03 line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO223 ,CPU Targets Byte Offset 223 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO222 ,CPU Targets Byte Offset 222 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO221 ,CPU Targets Byte Offset 221 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO220 ,CPU Targets Byte Offset 220 " else hgroup.long 0x8C0++0x03 hide.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48" hgroup.long 0x8C4++0x03 hide.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49" hgroup.long 0x8C8++0x03 hide.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50" hgroup.long 0x8CC++0x03 hide.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51" hgroup.long 0x8D0++0x03 hide.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52" hgroup.long 0x8D4++0x03 hide.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53" hgroup.long 0x8D8++0x03 hide.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54" hgroup.long 0x8DC++0x03 hide.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x8E0++0x03 line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO227 ,CPU Targets Byte Offset 227 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO226 ,CPU Targets Byte Offset 226 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO225 ,CPU Targets Byte Offset 225 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO224 ,CPU Targets Byte Offset 224 " group.long 0x8E4++0x03 line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO231 ,CPU Targets Byte Offset 231 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO230 ,CPU Targets Byte Offset 230 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO229 ,CPU Targets Byte Offset 229 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO228 ,CPU Targets Byte Offset 228 " group.long 0x8E8++0x03 line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO235 ,CPU Targets Byte Offset 235 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO234 ,CPU Targets Byte Offset 234 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO233 ,CPU Targets Byte Offset 233 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO232 ,CPU Targets Byte Offset 232 " group.long 0x8EC++0x03 line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO239 ,CPU Targets Byte Offset 239 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO238 ,CPU Targets Byte Offset 238 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO237 ,CPU Targets Byte Offset 237 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO236 ,CPU Targets Byte Offset 236 " group.long 0x8F0++0x03 line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO243 ,CPU Targets Byte Offset 243 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO242 ,CPU Targets Byte Offset 242 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO241 ,CPU Targets Byte Offset 241 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO240 ,CPU Targets Byte Offset 240 " group.long 0x8F4++0x03 line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO247 ,CPU Targets Byte Offset 247 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO246 ,CPU Targets Byte Offset 246 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO245 ,CPU Targets Byte Offset 245 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO244 ,CPU Targets Byte Offset 244 " group.long 0x8F8++0x03 line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO251 ,CPU Targets Byte Offset 251 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO250 ,CPU Targets Byte Offset 250 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO249 ,CPU Targets Byte Offset 249 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO248 ,CPU Targets Byte Offset 248 " group.long 0x8FC++0x03 line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO255 ,CPU Targets Byte Offset 255 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO254 ,CPU Targets Byte Offset 254 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO253 ,CPU Targets Byte Offset 253 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO252 ,CPU Targets Byte Offset 252 " else hgroup.long 0x8E0++0x03 hide.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56" hgroup.long 0x8E4++0x03 hide.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57" hgroup.long 0x8E8++0x03 hide.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58" hgroup.long 0x8EC++0x03 hide.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59" hgroup.long 0x8F0++0x03 hide.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60" hgroup.long 0x8F4++0x03 hide.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61" hgroup.long 0x8F8++0x03 hide.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62" hgroup.long 0x8FC++0x03 hide.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x900++0x03 line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO259 ,CPU Targets Byte Offset 259 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO258 ,CPU Targets Byte Offset 258 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO257 ,CPU Targets Byte Offset 257 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO256 ,CPU Targets Byte Offset 256 " group.long 0x904++0x03 line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO263 ,CPU Targets Byte Offset 263 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO262 ,CPU Targets Byte Offset 262 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO261 ,CPU Targets Byte Offset 261 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO260 ,CPU Targets Byte Offset 260 " group.long 0x908++0x03 line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO267 ,CPU Targets Byte Offset 267 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO266 ,CPU Targets Byte Offset 266 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO265 ,CPU Targets Byte Offset 265 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO264 ,CPU Targets Byte Offset 264 " group.long 0x90C++0x03 line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO271 ,CPU Targets Byte Offset 271 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO270 ,CPU Targets Byte Offset 270 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO269 ,CPU Targets Byte Offset 269 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO268 ,CPU Targets Byte Offset 268 " group.long 0x910++0x03 line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO275 ,CPU Targets Byte Offset 275 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO274 ,CPU Targets Byte Offset 274 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO273 ,CPU Targets Byte Offset 273 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO272 ,CPU Targets Byte Offset 272 " group.long 0x914++0x03 line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO279 ,CPU Targets Byte Offset 279 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO278 ,CPU Targets Byte Offset 278 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO277 ,CPU Targets Byte Offset 277 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO276 ,CPU Targets Byte Offset 276 " group.long 0x918++0x03 line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO283 ,CPU Targets Byte Offset 283 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO282 ,CPU Targets Byte Offset 282 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO281 ,CPU Targets Byte Offset 281 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO280 ,CPU Targets Byte Offset 280 " group.long 0x91C++0x03 line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO287 ,CPU Targets Byte Offset 287 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO286 ,CPU Targets Byte Offset 286 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO285 ,CPU Targets Byte Offset 285 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO284 ,CPU Targets Byte Offset 284 " else hgroup.long 0x900++0x03 hide.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64" hgroup.long 0x904++0x03 hide.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65" hgroup.long 0x908++0x03 hide.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66" hgroup.long 0x90C++0x03 hide.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67" hgroup.long 0x910++0x03 hide.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68" hgroup.long 0x914++0x03 hide.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69" hgroup.long 0x918++0x03 hide.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70" hgroup.long 0x91C++0x03 hide.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x920++0x03 line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO291 ,CPU Targets Byte Offset 291 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO290 ,CPU Targets Byte Offset 290 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO289 ,CPU Targets Byte Offset 289 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO288 ,CPU Targets Byte Offset 288 " group.long 0x924++0x03 line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO295 ,CPU Targets Byte Offset 295 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO294 ,CPU Targets Byte Offset 294 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO293 ,CPU Targets Byte Offset 293 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO292 ,CPU Targets Byte Offset 292 " group.long 0x928++0x03 line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO299 ,CPU Targets Byte Offset 299 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO298 ,CPU Targets Byte Offset 298 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO297 ,CPU Targets Byte Offset 297 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO296 ,CPU Targets Byte Offset 296 " group.long 0x92C++0x03 line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO303 ,CPU Targets Byte Offset 303 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO302 ,CPU Targets Byte Offset 302 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO301 ,CPU Targets Byte Offset 301 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO300 ,CPU Targets Byte Offset 300 " group.long 0x930++0x03 line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO307 ,CPU Targets Byte Offset 307 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO306 ,CPU Targets Byte Offset 306 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO305 ,CPU Targets Byte Offset 305 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO304 ,CPU Targets Byte Offset 304 " group.long 0x934++0x03 line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO311 ,CPU Targets Byte Offset 311 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO310 ,CPU Targets Byte Offset 310 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO309 ,CPU Targets Byte Offset 309 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO308 ,CPU Targets Byte Offset 308 " group.long 0x938++0x03 line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO315 ,CPU Targets Byte Offset 315 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO314 ,CPU Targets Byte Offset 314 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO313 ,CPU Targets Byte Offset 313 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO312 ,CPU Targets Byte Offset 312 " group.long 0x93C++0x03 line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO319 ,CPU Targets Byte Offset 319 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO318 ,CPU Targets Byte Offset 318 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO317 ,CPU Targets Byte Offset 317 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO316 ,CPU Targets Byte Offset 316 " else hgroup.long 0x920++0x03 hide.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72" hgroup.long 0x924++0x03 hide.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73" hgroup.long 0x928++0x03 hide.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74" hgroup.long 0x92C++0x03 hide.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75" hgroup.long 0x930++0x03 hide.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76" hgroup.long 0x934++0x03 hide.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77" hgroup.long 0x938++0x03 hide.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78" hgroup.long 0x93C++0x03 hide.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x940++0x03 line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO323 ,CPU Targets Byte Offset 323 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO322 ,CPU Targets Byte Offset 322 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO321 ,CPU Targets Byte Offset 321 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO320 ,CPU Targets Byte Offset 320 " group.long 0x944++0x03 line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO327 ,CPU Targets Byte Offset 327 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO326 ,CPU Targets Byte Offset 326 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO325 ,CPU Targets Byte Offset 325 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO324 ,CPU Targets Byte Offset 324 " group.long 0x948++0x03 line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO331 ,CPU Targets Byte Offset 331 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO330 ,CPU Targets Byte Offset 330 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO329 ,CPU Targets Byte Offset 329 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO328 ,CPU Targets Byte Offset 328 " group.long 0x94C++0x03 line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO335 ,CPU Targets Byte Offset 335 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO334 ,CPU Targets Byte Offset 334 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO333 ,CPU Targets Byte Offset 333 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO332 ,CPU Targets Byte Offset 332 " group.long 0x950++0x03 line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO339 ,CPU Targets Byte Offset 339 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO338 ,CPU Targets Byte Offset 338 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO337 ,CPU Targets Byte Offset 337 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO336 ,CPU Targets Byte Offset 336 " group.long 0x954++0x03 line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO343 ,CPU Targets Byte Offset 343 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO342 ,CPU Targets Byte Offset 342 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO341 ,CPU Targets Byte Offset 341 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO340 ,CPU Targets Byte Offset 340 " group.long 0x958++0x03 line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO347 ,CPU Targets Byte Offset 347 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO346 ,CPU Targets Byte Offset 346 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO345 ,CPU Targets Byte Offset 345 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO344 ,CPU Targets Byte Offset 344 " group.long 0x95C++0x03 line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO351 ,CPU Targets Byte Offset 351 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO350 ,CPU Targets Byte Offset 350 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO349 ,CPU Targets Byte Offset 349 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO348 ,CPU Targets Byte Offset 348 " else hgroup.long 0x940++0x03 hide.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80" hgroup.long 0x944++0x03 hide.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81" hgroup.long 0x948++0x03 hide.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82" hgroup.long 0x94C++0x03 hide.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83" hgroup.long 0x950++0x03 hide.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84" hgroup.long 0x954++0x03 hide.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85" hgroup.long 0x958++0x03 hide.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86" hgroup.long 0x95C++0x03 hide.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x960++0x03 line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO355 ,CPU Targets Byte Offset 355 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO354 ,CPU Targets Byte Offset 354 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO353 ,CPU Targets Byte Offset 353 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO352 ,CPU Targets Byte Offset 352 " group.long 0x964++0x03 line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO359 ,CPU Targets Byte Offset 359 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO358 ,CPU Targets Byte Offset 358 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO357 ,CPU Targets Byte Offset 357 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO356 ,CPU Targets Byte Offset 356 " group.long 0x968++0x03 line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO363 ,CPU Targets Byte Offset 363 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO362 ,CPU Targets Byte Offset 362 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO361 ,CPU Targets Byte Offset 361 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO360 ,CPU Targets Byte Offset 360 " group.long 0x96C++0x03 line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO367 ,CPU Targets Byte Offset 367 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO366 ,CPU Targets Byte Offset 366 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO365 ,CPU Targets Byte Offset 365 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO364 ,CPU Targets Byte Offset 364 " group.long 0x970++0x03 line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO371 ,CPU Targets Byte Offset 371 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO370 ,CPU Targets Byte Offset 370 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO369 ,CPU Targets Byte Offset 369 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO368 ,CPU Targets Byte Offset 368 " group.long 0x974++0x03 line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO375 ,CPU Targets Byte Offset 375 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO374 ,CPU Targets Byte Offset 374 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO373 ,CPU Targets Byte Offset 373 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO372 ,CPU Targets Byte Offset 372 " group.long 0x978++0x03 line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO379 ,CPU Targets Byte Offset 379 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO378 ,CPU Targets Byte Offset 378 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO377 ,CPU Targets Byte Offset 377 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO376 ,CPU Targets Byte Offset 376 " group.long 0x97C++0x03 line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO383 ,CPU Targets Byte Offset 383 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO382 ,CPU Targets Byte Offset 382 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO381 ,CPU Targets Byte Offset 381 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO380 ,CPU Targets Byte Offset 380 " else hgroup.long 0x960++0x03 hide.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88" hgroup.long 0x964++0x03 hide.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89" hgroup.long 0x968++0x03 hide.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90" hgroup.long 0x96C++0x03 hide.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91" hgroup.long 0x970++0x03 hide.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92" hgroup.long 0x974++0x03 hide.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93" hgroup.long 0x978++0x03 hide.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94" hgroup.long 0x97C++0x03 hide.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x980++0x03 line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO387 ,CPU Targets Byte Offset 387 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO386 ,CPU Targets Byte Offset 386 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO385 ,CPU Targets Byte Offset 385 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO384 ,CPU Targets Byte Offset 384 " group.long 0x984++0x03 line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO391 ,CPU Targets Byte Offset 391 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO390 ,CPU Targets Byte Offset 390 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO389 ,CPU Targets Byte Offset 389 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO388 ,CPU Targets Byte Offset 388 " group.long 0x988++0x03 line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO395 ,CPU Targets Byte Offset 395 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO394 ,CPU Targets Byte Offset 394 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO393 ,CPU Targets Byte Offset 393 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO392 ,CPU Targets Byte Offset 392 " group.long 0x98C++0x03 line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO399 ,CPU Targets Byte Offset 399 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO398 ,CPU Targets Byte Offset 398 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO397 ,CPU Targets Byte Offset 397 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO396 ,CPU Targets Byte Offset 396 " group.long 0x990++0x03 line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO403 ,CPU Targets Byte Offset 403 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO402 ,CPU Targets Byte Offset 402 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO401 ,CPU Targets Byte Offset 401 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO400 ,CPU Targets Byte Offset 400 " group.long 0x994++0x03 line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO407 ,CPU Targets Byte Offset 407 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO406 ,CPU Targets Byte Offset 406 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO405 ,CPU Targets Byte Offset 405 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO404 ,CPU Targets Byte Offset 404 " group.long 0x998++0x03 line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO411 ,CPU Targets Byte Offset 411 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO410 ,CPU Targets Byte Offset 410 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO409 ,CPU Targets Byte Offset 409 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO408 ,CPU Targets Byte Offset 408 " group.long 0x99C++0x03 line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO415 ,CPU Targets Byte Offset 415 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO414 ,CPU Targets Byte Offset 414 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO413 ,CPU Targets Byte Offset 413 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO412 ,CPU Targets Byte Offset 412 " else hgroup.long 0x980++0x03 hide.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96" hgroup.long 0x984++0x03 hide.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97" hgroup.long 0x988++0x03 hide.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98" hgroup.long 0x98C++0x03 hide.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99" hgroup.long 0x990++0x03 hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hgroup.long 0x994++0x03 hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hgroup.long 0x998++0x03 hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hgroup.long 0x99C++0x03 hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x9A0++0x03 line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO419 ,CPU Targets Byte Offset 419 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO418 ,CPU Targets Byte Offset 418 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO417 ,CPU Targets Byte Offset 417 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO416 ,CPU Targets Byte Offset 416 " group.long 0x9A4++0x03 line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO423 ,CPU Targets Byte Offset 423 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO422 ,CPU Targets Byte Offset 422 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO421 ,CPU Targets Byte Offset 421 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO420 ,CPU Targets Byte Offset 420 " group.long 0x9A8++0x03 line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO427 ,CPU Targets Byte Offset 427 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO426 ,CPU Targets Byte Offset 426 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO425 ,CPU Targets Byte Offset 425 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO424 ,CPU Targets Byte Offset 424 " group.long 0x9AC++0x03 line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO431 ,CPU Targets Byte Offset 431 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO430 ,CPU Targets Byte Offset 430 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO429 ,CPU Targets Byte Offset 429 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO428 ,CPU Targets Byte Offset 428 " group.long 0x9B0++0x03 line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO435 ,CPU Targets Byte Offset 435 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO434 ,CPU Targets Byte Offset 434 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO433 ,CPU Targets Byte Offset 433 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO432 ,CPU Targets Byte Offset 432 " group.long 0x9B4++0x03 line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO439 ,CPU Targets Byte Offset 439 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO438 ,CPU Targets Byte Offset 438 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO437 ,CPU Targets Byte Offset 437 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO436 ,CPU Targets Byte Offset 436 " group.long 0x9B8++0x03 line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO443 ,CPU Targets Byte Offset 443 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO442 ,CPU Targets Byte Offset 442 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO441 ,CPU Targets Byte Offset 441 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO440 ,CPU Targets Byte Offset 440 " group.long 0x9BC++0x03 line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO447 ,CPU Targets Byte Offset 447 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO446 ,CPU Targets Byte Offset 446 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO445 ,CPU Targets Byte Offset 445 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO444 ,CPU Targets Byte Offset 444 " else hgroup.long 0x9A0++0x03 hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hgroup.long 0x9A4++0x03 hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hgroup.long 0x9A8++0x03 hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hgroup.long 0x9AC++0x03 hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hgroup.long 0x9B0++0x03 hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hgroup.long 0x9B4++0x03 hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hgroup.long 0x9B8++0x03 hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hgroup.long 0x9BC++0x03 hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x9C0++0x03 line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO451 ,CPU Targets Byte Offset 451 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO450 ,CPU Targets Byte Offset 450 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO449 ,CPU Targets Byte Offset 449 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO448 ,CPU Targets Byte Offset 448 " group.long 0x9C4++0x03 line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO455 ,CPU Targets Byte Offset 455 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO454 ,CPU Targets Byte Offset 454 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO453 ,CPU Targets Byte Offset 453 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO452 ,CPU Targets Byte Offset 452 " group.long 0x9C8++0x03 line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO459 ,CPU Targets Byte Offset 459 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO458 ,CPU Targets Byte Offset 458 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO457 ,CPU Targets Byte Offset 457 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO456 ,CPU Targets Byte Offset 456 " group.long 0x9CC++0x03 line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO463 ,CPU Targets Byte Offset 463 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO462 ,CPU Targets Byte Offset 462 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO461 ,CPU Targets Byte Offset 461 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO460 ,CPU Targets Byte Offset 460 " group.long 0x9D0++0x03 line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO467 ,CPU Targets Byte Offset 467 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO466 ,CPU Targets Byte Offset 466 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO465 ,CPU Targets Byte Offset 465 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO464 ,CPU Targets Byte Offset 464 " group.long 0x9D4++0x03 line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO471 ,CPU Targets Byte Offset 471 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO470 ,CPU Targets Byte Offset 470 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO469 ,CPU Targets Byte Offset 469 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO468 ,CPU Targets Byte Offset 468 " group.long 0x9D8++0x03 line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO475 ,CPU Targets Byte Offset 475 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO474 ,CPU Targets Byte Offset 474 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO473 ,CPU Targets Byte Offset 473 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO472 ,CPU Targets Byte Offset 472 " group.long 0x9DC++0x03 line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO479 ,CPU Targets Byte Offset 479 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO478 ,CPU Targets Byte Offset 478 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO477 ,CPU Targets Byte Offset 477 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO476 ,CPU Targets Byte Offset 476 " else hgroup.long 0x9C0++0x03 hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hgroup.long 0x9C4++0x03 hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hgroup.long 0x9C8++0x03 hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hgroup.long 0x9CC++0x03 hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hgroup.long 0x9D0++0x03 hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hgroup.long 0x9D4++0x03 hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hgroup.long 0x9D8++0x03 hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hgroup.long 0x9DC++0x03 hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x9E0++0x03 line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO483 ,CPU Targets Byte Offset 483 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO482 ,CPU Targets Byte Offset 482 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO481 ,CPU Targets Byte Offset 481 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO480 ,CPU Targets Byte Offset 480 " group.long 0x9E4++0x03 line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO487 ,CPU Targets Byte Offset 487 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO486 ,CPU Targets Byte Offset 486 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO485 ,CPU Targets Byte Offset 485 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO484 ,CPU Targets Byte Offset 484 " group.long 0x9E8++0x03 line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO491 ,CPU Targets Byte Offset 491 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO490 ,CPU Targets Byte Offset 490 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO489 ,CPU Targets Byte Offset 489 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO488 ,CPU Targets Byte Offset 488 " group.long 0x9EC++0x03 line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO495 ,CPU Targets Byte Offset 495 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO494 ,CPU Targets Byte Offset 494 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO493 ,CPU Targets Byte Offset 493 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO492 ,CPU Targets Byte Offset 492 " group.long 0x9F0++0x03 line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO499 ,CPU Targets Byte Offset 499 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO498 ,CPU Targets Byte Offset 498 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO497 ,CPU Targets Byte Offset 497 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO496 ,CPU Targets Byte Offset 496 " group.long 0x9F4++0x03 line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO503 ,CPU Targets Byte Offset 503 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO502 ,CPU Targets Byte Offset 502 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO501 ,CPU Targets Byte Offset 501 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO500 ,CPU Targets Byte Offset 500 " group.long 0x9F8++0x03 line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO507 ,CPU Targets Byte Offset 507 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO506 ,CPU Targets Byte Offset 506 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO505 ,CPU Targets Byte Offset 505 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO504 ,CPU Targets Byte Offset 504 " group.long 0x9FC++0x03 line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO511 ,CPU Targets Byte Offset 511 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO510 ,CPU Targets Byte Offset 510 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO509 ,CPU Targets Byte Offset 509 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO508 ,CPU Targets Byte Offset 508 " else hgroup.long 0x9E0++0x03 hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hgroup.long 0x9E4++0x03 hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hgroup.long 0x9E8++0x03 hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hgroup.long 0x9EC++0x03 hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hgroup.long 0x9F0++0x03 hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hgroup.long 0x9F4++0x03 hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hgroup.long 0x9F8++0x03 hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hgroup.long 0x9FC++0x03 hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0xA00++0x03 line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO515 ,CPU Targets Byte Offset 515 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO514 ,CPU Targets Byte Offset 514 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO513 ,CPU Targets Byte Offset 513 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO512 ,CPU Targets Byte Offset 512 " group.long 0xA04++0x03 line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO519 ,CPU Targets Byte Offset 519 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO518 ,CPU Targets Byte Offset 518 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO517 ,CPU Targets Byte Offset 517 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO516 ,CPU Targets Byte Offset 516 " group.long 0xA08++0x03 line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO523 ,CPU Targets Byte Offset 523 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO522 ,CPU Targets Byte Offset 522 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO521 ,CPU Targets Byte Offset 521 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO520 ,CPU Targets Byte Offset 520 " group.long 0xA0C++0x03 line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO527 ,CPU Targets Byte Offset 527 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO526 ,CPU Targets Byte Offset 526 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO525 ,CPU Targets Byte Offset 525 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO524 ,CPU Targets Byte Offset 524 " group.long 0xA10++0x03 line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO531 ,CPU Targets Byte Offset 531 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO530 ,CPU Targets Byte Offset 530 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO529 ,CPU Targets Byte Offset 529 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO528 ,CPU Targets Byte Offset 528 " group.long 0xA14++0x03 line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO535 ,CPU Targets Byte Offset 535 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO534 ,CPU Targets Byte Offset 534 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO533 ,CPU Targets Byte Offset 533 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO532 ,CPU Targets Byte Offset 532 " group.long 0xA18++0x03 line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO539 ,CPU Targets Byte Offset 539 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO538 ,CPU Targets Byte Offset 538 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO537 ,CPU Targets Byte Offset 537 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO536 ,CPU Targets Byte Offset 536 " group.long 0xA1C++0x03 line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO543 ,CPU Targets Byte Offset 543 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO542 ,CPU Targets Byte Offset 542 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO541 ,CPU Targets Byte Offset 541 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO540 ,CPU Targets Byte Offset 540 " else hgroup.long 0xA00++0x03 hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hgroup.long 0xA04++0x03 hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hgroup.long 0xA08++0x03 hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hgroup.long 0xA0C++0x03 hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hgroup.long 0xA10++0x03 hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hgroup.long 0xA14++0x03 hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hgroup.long 0xA18++0x03 hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hgroup.long 0xA1C++0x03 hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0xA20++0x03 line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO547 ,CPU Targets Byte Offset 547 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO546 ,CPU Targets Byte Offset 546 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO545 ,CPU Targets Byte Offset 545 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO544 ,CPU Targets Byte Offset 544 " group.long 0xA24++0x03 line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO551 ,CPU Targets Byte Offset 551 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO550 ,CPU Targets Byte Offset 550 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO549 ,CPU Targets Byte Offset 549 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO548 ,CPU Targets Byte Offset 548 " group.long 0xA28++0x03 line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO555 ,CPU Targets Byte Offset 555 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO554 ,CPU Targets Byte Offset 554 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO553 ,CPU Targets Byte Offset 553 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO552 ,CPU Targets Byte Offset 552 " group.long 0xA2C++0x03 line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO559 ,CPU Targets Byte Offset 559 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO558 ,CPU Targets Byte Offset 558 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO557 ,CPU Targets Byte Offset 557 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO556 ,CPU Targets Byte Offset 556 " group.long 0xA30++0x03 line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO563 ,CPU Targets Byte Offset 563 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO562 ,CPU Targets Byte Offset 562 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO561 ,CPU Targets Byte Offset 561 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO560 ,CPU Targets Byte Offset 560 " group.long 0xA34++0x03 line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO567 ,CPU Targets Byte Offset 567 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO566 ,CPU Targets Byte Offset 566 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO565 ,CPU Targets Byte Offset 565 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO564 ,CPU Targets Byte Offset 564 " group.long 0xA38++0x03 line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO571 ,CPU Targets Byte Offset 571 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO570 ,CPU Targets Byte Offset 570 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO569 ,CPU Targets Byte Offset 569 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO568 ,CPU Targets Byte Offset 568 " group.long 0xA3C++0x03 line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO575 ,CPU Targets Byte Offset 575 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO574 ,CPU Targets Byte Offset 574 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO573 ,CPU Targets Byte Offset 573 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO572 ,CPU Targets Byte Offset 572 " else hgroup.long 0xA20++0x03 hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hgroup.long 0xA24++0x03 hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hgroup.long 0xA28++0x03 hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hgroup.long 0xA2C++0x03 hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hgroup.long 0xA30++0x03 hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hgroup.long 0xA34++0x03 hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hgroup.long 0xA38++0x03 hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hgroup.long 0xA3C++0x03 hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0xA40++0x03 line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO579 ,CPU Targets Byte Offset 579 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO578 ,CPU Targets Byte Offset 578 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO577 ,CPU Targets Byte Offset 577 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO576 ,CPU Targets Byte Offset 576 " group.long 0xA44++0x03 line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO583 ,CPU Targets Byte Offset 583 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO582 ,CPU Targets Byte Offset 582 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO581 ,CPU Targets Byte Offset 581 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO580 ,CPU Targets Byte Offset 580 " group.long 0xA48++0x03 line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO587 ,CPU Targets Byte Offset 587 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO586 ,CPU Targets Byte Offset 586 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO585 ,CPU Targets Byte Offset 585 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO584 ,CPU Targets Byte Offset 584 " group.long 0xA4C++0x03 line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO591 ,CPU Targets Byte Offset 591 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO590 ,CPU Targets Byte Offset 590 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO589 ,CPU Targets Byte Offset 589 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO588 ,CPU Targets Byte Offset 588 " group.long 0xA50++0x03 line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO595 ,CPU Targets Byte Offset 595 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO594 ,CPU Targets Byte Offset 594 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO593 ,CPU Targets Byte Offset 593 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO592 ,CPU Targets Byte Offset 592 " group.long 0xA54++0x03 line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO599 ,CPU Targets Byte Offset 599 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO598 ,CPU Targets Byte Offset 598 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO597 ,CPU Targets Byte Offset 597 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO596 ,CPU Targets Byte Offset 596 " group.long 0xA58++0x03 line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO603 ,CPU Targets Byte Offset 603 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO602 ,CPU Targets Byte Offset 602 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO601 ,CPU Targets Byte Offset 601 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO600 ,CPU Targets Byte Offset 600 " group.long 0xA5C++0x03 line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO607 ,CPU Targets Byte Offset 607 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO606 ,CPU Targets Byte Offset 606 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO605 ,CPU Targets Byte Offset 605 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO604 ,CPU Targets Byte Offset 604 " else hgroup.long 0xA40++0x03 hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hgroup.long 0xA44++0x03 hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hgroup.long 0xA48++0x03 hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hgroup.long 0xA4C++0x03 hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hgroup.long 0xA50++0x03 hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hgroup.long 0xA54++0x03 hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hgroup.long 0xA58++0x03 hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hgroup.long 0xA5C++0x03 hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0xA60++0x03 line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO611 ,CPU Targets Byte Offset 611 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO610 ,CPU Targets Byte Offset 610 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO609 ,CPU Targets Byte Offset 609 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO608 ,CPU Targets Byte Offset 608 " group.long 0xA64++0x03 line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO615 ,CPU Targets Byte Offset 615 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO614 ,CPU Targets Byte Offset 614 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO613 ,CPU Targets Byte Offset 613 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO612 ,CPU Targets Byte Offset 612 " group.long 0xA68++0x03 line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO619 ,CPU Targets Byte Offset 619 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO618 ,CPU Targets Byte Offset 618 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO617 ,CPU Targets Byte Offset 617 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO616 ,CPU Targets Byte Offset 616 " group.long 0xA6C++0x03 line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO623 ,CPU Targets Byte Offset 623 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO622 ,CPU Targets Byte Offset 622 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO621 ,CPU Targets Byte Offset 621 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO620 ,CPU Targets Byte Offset 620 " group.long 0xA70++0x03 line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO627 ,CPU Targets Byte Offset 627 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO626 ,CPU Targets Byte Offset 626 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO625 ,CPU Targets Byte Offset 625 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO624 ,CPU Targets Byte Offset 624 " group.long 0xA74++0x03 line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO631 ,CPU Targets Byte Offset 631 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO630 ,CPU Targets Byte Offset 630 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO629 ,CPU Targets Byte Offset 629 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO628 ,CPU Targets Byte Offset 628 " group.long 0xA78++0x03 line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO635 ,CPU Targets Byte Offset 635 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO634 ,CPU Targets Byte Offset 634 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO633 ,CPU Targets Byte Offset 633 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO632 ,CPU Targets Byte Offset 632 " group.long 0xA7C++0x03 line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO639 ,CPU Targets Byte Offset 639 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO638 ,CPU Targets Byte Offset 638 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO637 ,CPU Targets Byte Offset 637 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO636 ,CPU Targets Byte Offset 636 " else hgroup.long 0xA60++0x03 hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hgroup.long 0xA64++0x03 hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hgroup.long 0xA68++0x03 hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hgroup.long 0xA6C++0x03 hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hgroup.long 0xA70++0x03 hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hgroup.long 0xA74++0x03 hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hgroup.long 0xA78++0x03 hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hgroup.long 0xA7C++0x03 hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0xA80++0x03 line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO643 ,CPU Targets Byte Offset 643 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO642 ,CPU Targets Byte Offset 642 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO641 ,CPU Targets Byte Offset 641 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO640 ,CPU Targets Byte Offset 640 " group.long 0xA84++0x03 line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO647 ,CPU Targets Byte Offset 647 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO646 ,CPU Targets Byte Offset 646 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO645 ,CPU Targets Byte Offset 645 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO644 ,CPU Targets Byte Offset 644 " group.long 0xA88++0x03 line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO651 ,CPU Targets Byte Offset 651 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO650 ,CPU Targets Byte Offset 650 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO649 ,CPU Targets Byte Offset 649 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO648 ,CPU Targets Byte Offset 648 " group.long 0xA8C++0x03 line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO655 ,CPU Targets Byte Offset 655 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO654 ,CPU Targets Byte Offset 654 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO653 ,CPU Targets Byte Offset 653 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO652 ,CPU Targets Byte Offset 652 " group.long 0xA90++0x03 line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO659 ,CPU Targets Byte Offset 659 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO658 ,CPU Targets Byte Offset 658 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO657 ,CPU Targets Byte Offset 657 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO656 ,CPU Targets Byte Offset 656 " group.long 0xA94++0x03 line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO663 ,CPU Targets Byte Offset 663 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO662 ,CPU Targets Byte Offset 662 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO661 ,CPU Targets Byte Offset 661 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO660 ,CPU Targets Byte Offset 660 " group.long 0xA98++0x03 line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO667 ,CPU Targets Byte Offset 667 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO666 ,CPU Targets Byte Offset 666 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO665 ,CPU Targets Byte Offset 665 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO664 ,CPU Targets Byte Offset 664 " group.long 0xA9C++0x03 line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO671 ,CPU Targets Byte Offset 671 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO670 ,CPU Targets Byte Offset 670 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO669 ,CPU Targets Byte Offset 669 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO668 ,CPU Targets Byte Offset 668 " else hgroup.long 0xA80++0x03 hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hgroup.long 0xA84++0x03 hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hgroup.long 0xA88++0x03 hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hgroup.long 0xA8C++0x03 hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hgroup.long 0xA90++0x03 hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hgroup.long 0xA94++0x03 hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hgroup.long 0xA98++0x03 hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hgroup.long 0xA9C++0x03 hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0xAA0++0x03 line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO675 ,CPU Targets Byte Offset 675 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO674 ,CPU Targets Byte Offset 674 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO673 ,CPU Targets Byte Offset 673 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO672 ,CPU Targets Byte Offset 672 " group.long 0xAA4++0x03 line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO679 ,CPU Targets Byte Offset 679 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO678 ,CPU Targets Byte Offset 678 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO677 ,CPU Targets Byte Offset 677 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO676 ,CPU Targets Byte Offset 676 " group.long 0xAA8++0x03 line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO683 ,CPU Targets Byte Offset 683 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO682 ,CPU Targets Byte Offset 682 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO681 ,CPU Targets Byte Offset 681 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO680 ,CPU Targets Byte Offset 680 " group.long 0xAAC++0x03 line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO687 ,CPU Targets Byte Offset 687 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO686 ,CPU Targets Byte Offset 686 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO685 ,CPU Targets Byte Offset 685 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO684 ,CPU Targets Byte Offset 684 " group.long 0xAB0++0x03 line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO691 ,CPU Targets Byte Offset 691 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO690 ,CPU Targets Byte Offset 690 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO689 ,CPU Targets Byte Offset 689 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO688 ,CPU Targets Byte Offset 688 " group.long 0xAB4++0x03 line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO695 ,CPU Targets Byte Offset 695 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO694 ,CPU Targets Byte Offset 694 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO693 ,CPU Targets Byte Offset 693 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO692 ,CPU Targets Byte Offset 692 " group.long 0xAB8++0x03 line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO699 ,CPU Targets Byte Offset 699 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO698 ,CPU Targets Byte Offset 698 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO697 ,CPU Targets Byte Offset 697 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO696 ,CPU Targets Byte Offset 696 " group.long 0xABC++0x03 line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO703 ,CPU Targets Byte Offset 703 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO702 ,CPU Targets Byte Offset 702 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO701 ,CPU Targets Byte Offset 701 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO700 ,CPU Targets Byte Offset 700 " else hgroup.long 0xAA0++0x03 hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hgroup.long 0xAA4++0x03 hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hgroup.long 0xAA8++0x03 hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hgroup.long 0xAAC++0x03 hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hgroup.long 0xAB0++0x03 hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hgroup.long 0xAB4++0x03 hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hgroup.long 0xAB8++0x03 hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hgroup.long 0xABC++0x03 hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0xAC0++0x03 line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO707 ,CPU Targets Byte Offset 707 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO706 ,CPU Targets Byte Offset 706 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO705 ,CPU Targets Byte Offset 705 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO704 ,CPU Targets Byte Offset 704 " group.long 0xAC4++0x03 line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO711 ,CPU Targets Byte Offset 711 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO710 ,CPU Targets Byte Offset 710 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO709 ,CPU Targets Byte Offset 709 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO708 ,CPU Targets Byte Offset 708 " group.long 0xAC8++0x03 line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO715 ,CPU Targets Byte Offset 715 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO714 ,CPU Targets Byte Offset 714 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO713 ,CPU Targets Byte Offset 713 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO712 ,CPU Targets Byte Offset 712 " group.long 0xACC++0x03 line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO719 ,CPU Targets Byte Offset 719 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO718 ,CPU Targets Byte Offset 718 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO717 ,CPU Targets Byte Offset 717 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO716 ,CPU Targets Byte Offset 716 " group.long 0xAD0++0x03 line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO723 ,CPU Targets Byte Offset 723 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO722 ,CPU Targets Byte Offset 722 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO721 ,CPU Targets Byte Offset 721 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO720 ,CPU Targets Byte Offset 720 " group.long 0xAD4++0x03 line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO727 ,CPU Targets Byte Offset 727 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO726 ,CPU Targets Byte Offset 726 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO725 ,CPU Targets Byte Offset 725 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO724 ,CPU Targets Byte Offset 724 " group.long 0xAD8++0x03 line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO731 ,CPU Targets Byte Offset 731 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO730 ,CPU Targets Byte Offset 730 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO729 ,CPU Targets Byte Offset 729 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO728 ,CPU Targets Byte Offset 728 " group.long 0xADC++0x03 line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO735 ,CPU Targets Byte Offset 735 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO734 ,CPU Targets Byte Offset 734 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO733 ,CPU Targets Byte Offset 733 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO732 ,CPU Targets Byte Offset 732 " else hgroup.long 0xAC0++0x03 hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hgroup.long 0xAC4++0x03 hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hgroup.long 0xAC8++0x03 hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hgroup.long 0xACC++0x03 hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hgroup.long 0xAD0++0x03 hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hgroup.long 0xAD4++0x03 hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hgroup.long 0xAD8++0x03 hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hgroup.long 0xADC++0x03 hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0xAE0++0x03 line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO739 ,CPU Targets Byte Offset 739 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO738 ,CPU Targets Byte Offset 738 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO737 ,CPU Targets Byte Offset 737 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO736 ,CPU Targets Byte Offset 736 " group.long 0xAE4++0x03 line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO743 ,CPU Targets Byte Offset 743 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO742 ,CPU Targets Byte Offset 742 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO741 ,CPU Targets Byte Offset 741 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO740 ,CPU Targets Byte Offset 740 " group.long 0xAE8++0x03 line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO747 ,CPU Targets Byte Offset 747 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO746 ,CPU Targets Byte Offset 746 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO745 ,CPU Targets Byte Offset 745 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO744 ,CPU Targets Byte Offset 744 " group.long 0xAEC++0x03 line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO751 ,CPU Targets Byte Offset 751 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO750 ,CPU Targets Byte Offset 750 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO749 ,CPU Targets Byte Offset 749 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO748 ,CPU Targets Byte Offset 748 " group.long 0xAF0++0x03 line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO755 ,CPU Targets Byte Offset 755 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO754 ,CPU Targets Byte Offset 754 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO753 ,CPU Targets Byte Offset 753 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO752 ,CPU Targets Byte Offset 752 " group.long 0xAF4++0x03 line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO759 ,CPU Targets Byte Offset 759 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO758 ,CPU Targets Byte Offset 758 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO757 ,CPU Targets Byte Offset 757 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO756 ,CPU Targets Byte Offset 756 " group.long 0xAF8++0x03 line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO763 ,CPU Targets Byte Offset 763 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO762 ,CPU Targets Byte Offset 762 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO761 ,CPU Targets Byte Offset 761 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO760 ,CPU Targets Byte Offset 760 " group.long 0xAFC++0x03 line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO767 ,CPU Targets Byte Offset 767 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO766 ,CPU Targets Byte Offset 766 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO765 ,CPU Targets Byte Offset 765 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO764 ,CPU Targets Byte Offset 764 " else hgroup.long 0xAE0++0x03 hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hgroup.long 0xAE4++0x03 hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hgroup.long 0xAE8++0x03 hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hgroup.long 0xAEC++0x03 hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hgroup.long 0xAF0++0x03 hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hgroup.long 0xAF4++0x03 hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hgroup.long 0xAF8++0x03 hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hgroup.long 0xAFC++0x03 hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0xB00++0x03 line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO771 ,CPU Targets Byte Offset 771 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO770 ,CPU Targets Byte Offset 770 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO769 ,CPU Targets Byte Offset 769 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO768 ,CPU Targets Byte Offset 768 " group.long 0xB04++0x03 line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO775 ,CPU Targets Byte Offset 775 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO774 ,CPU Targets Byte Offset 774 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO773 ,CPU Targets Byte Offset 773 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO772 ,CPU Targets Byte Offset 772 " group.long 0xB08++0x03 line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO779 ,CPU Targets Byte Offset 779 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO778 ,CPU Targets Byte Offset 778 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO777 ,CPU Targets Byte Offset 777 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO776 ,CPU Targets Byte Offset 776 " group.long 0xB0C++0x03 line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO783 ,CPU Targets Byte Offset 783 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO782 ,CPU Targets Byte Offset 782 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO781 ,CPU Targets Byte Offset 781 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO780 ,CPU Targets Byte Offset 780 " group.long 0xB10++0x03 line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO787 ,CPU Targets Byte Offset 787 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO786 ,CPU Targets Byte Offset 786 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO785 ,CPU Targets Byte Offset 785 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO784 ,CPU Targets Byte Offset 784 " group.long 0xB14++0x03 line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO791 ,CPU Targets Byte Offset 791 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO790 ,CPU Targets Byte Offset 790 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO789 ,CPU Targets Byte Offset 789 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO788 ,CPU Targets Byte Offset 788 " group.long 0xB18++0x03 line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO795 ,CPU Targets Byte Offset 795 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO794 ,CPU Targets Byte Offset 794 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO793 ,CPU Targets Byte Offset 793 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO792 ,CPU Targets Byte Offset 792 " group.long 0xB1C++0x03 line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO799 ,CPU Targets Byte Offset 799 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO798 ,CPU Targets Byte Offset 798 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO797 ,CPU Targets Byte Offset 797 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO796 ,CPU Targets Byte Offset 796 " else hgroup.long 0xB00++0x03 hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hgroup.long 0xB04++0x03 hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hgroup.long 0xB08++0x03 hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hgroup.long 0xB0C++0x03 hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hgroup.long 0xB10++0x03 hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hgroup.long 0xB14++0x03 hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hgroup.long 0xB18++0x03 hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hgroup.long 0xB1C++0x03 hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0xB20++0x03 line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO803 ,CPU Targets Byte Offset 803 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO802 ,CPU Targets Byte Offset 802 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO801 ,CPU Targets Byte Offset 801 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO800 ,CPU Targets Byte Offset 800 " group.long 0xB24++0x03 line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO807 ,CPU Targets Byte Offset 807 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO806 ,CPU Targets Byte Offset 806 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO805 ,CPU Targets Byte Offset 805 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO804 ,CPU Targets Byte Offset 804 " group.long 0xB28++0x03 line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO811 ,CPU Targets Byte Offset 811 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO810 ,CPU Targets Byte Offset 810 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO809 ,CPU Targets Byte Offset 809 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO808 ,CPU Targets Byte Offset 808 " group.long 0xB2C++0x03 line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO815 ,CPU Targets Byte Offset 815 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO814 ,CPU Targets Byte Offset 814 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO813 ,CPU Targets Byte Offset 813 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO812 ,CPU Targets Byte Offset 812 " group.long 0xB30++0x03 line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO819 ,CPU Targets Byte Offset 819 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO818 ,CPU Targets Byte Offset 818 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO817 ,CPU Targets Byte Offset 817 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO816 ,CPU Targets Byte Offset 816 " group.long 0xB34++0x03 line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO823 ,CPU Targets Byte Offset 823 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO822 ,CPU Targets Byte Offset 822 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO821 ,CPU Targets Byte Offset 821 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO820 ,CPU Targets Byte Offset 820 " group.long 0xB38++0x03 line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO827 ,CPU Targets Byte Offset 827 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO826 ,CPU Targets Byte Offset 826 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO825 ,CPU Targets Byte Offset 825 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO824 ,CPU Targets Byte Offset 824 " group.long 0xB3C++0x03 line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO831 ,CPU Targets Byte Offset 831 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO830 ,CPU Targets Byte Offset 830 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO829 ,CPU Targets Byte Offset 829 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO828 ,CPU Targets Byte Offset 828 " else hgroup.long 0xB20++0x03 hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hgroup.long 0xB24++0x03 hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hgroup.long 0xB28++0x03 hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hgroup.long 0xB2C++0x03 hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hgroup.long 0xB30++0x03 hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hgroup.long 0xB34++0x03 hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hgroup.long 0xB38++0x03 hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hgroup.long 0xB3C++0x03 hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0xB40++0x03 line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO835 ,CPU Targets Byte Offset 835 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO834 ,CPU Targets Byte Offset 834 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO833 ,CPU Targets Byte Offset 833 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO832 ,CPU Targets Byte Offset 832 " group.long 0xB44++0x03 line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO839 ,CPU Targets Byte Offset 839 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO838 ,CPU Targets Byte Offset 838 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO837 ,CPU Targets Byte Offset 837 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO836 ,CPU Targets Byte Offset 836 " group.long 0xB48++0x03 line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO843 ,CPU Targets Byte Offset 843 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO842 ,CPU Targets Byte Offset 842 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO841 ,CPU Targets Byte Offset 841 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO840 ,CPU Targets Byte Offset 840 " group.long 0xB4C++0x03 line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO847 ,CPU Targets Byte Offset 847 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO846 ,CPU Targets Byte Offset 846 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO845 ,CPU Targets Byte Offset 845 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO844 ,CPU Targets Byte Offset 844 " group.long 0xB50++0x03 line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO851 ,CPU Targets Byte Offset 851 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO850 ,CPU Targets Byte Offset 850 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO849 ,CPU Targets Byte Offset 849 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO848 ,CPU Targets Byte Offset 848 " group.long 0xB54++0x03 line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO855 ,CPU Targets Byte Offset 855 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO854 ,CPU Targets Byte Offset 854 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO853 ,CPU Targets Byte Offset 853 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO852 ,CPU Targets Byte Offset 852 " group.long 0xB58++0x03 line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO859 ,CPU Targets Byte Offset 859 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO858 ,CPU Targets Byte Offset 858 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO857 ,CPU Targets Byte Offset 857 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO856 ,CPU Targets Byte Offset 856 " group.long 0xB5C++0x03 line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO863 ,CPU Targets Byte Offset 863 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO862 ,CPU Targets Byte Offset 862 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO861 ,CPU Targets Byte Offset 861 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO860 ,CPU Targets Byte Offset 860 " else hgroup.long 0xB40++0x03 hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hgroup.long 0xB44++0x03 hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hgroup.long 0xB48++0x03 hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hgroup.long 0xB4C++0x03 hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hgroup.long 0xB50++0x03 hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hgroup.long 0xB54++0x03 hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hgroup.long 0xB58++0x03 hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hgroup.long 0xB5C++0x03 hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0xB60++0x03 line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO867 ,CPU Targets Byte Offset 867 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO866 ,CPU Targets Byte Offset 866 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO865 ,CPU Targets Byte Offset 865 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO864 ,CPU Targets Byte Offset 864 " group.long 0xB64++0x03 line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO871 ,CPU Targets Byte Offset 871 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO870 ,CPU Targets Byte Offset 870 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO869 ,CPU Targets Byte Offset 869 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO868 ,CPU Targets Byte Offset 868 " group.long 0xB68++0x03 line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO875 ,CPU Targets Byte Offset 875 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO874 ,CPU Targets Byte Offset 874 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO873 ,CPU Targets Byte Offset 873 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO872 ,CPU Targets Byte Offset 872 " group.long 0xB6C++0x03 line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO879 ,CPU Targets Byte Offset 879 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO878 ,CPU Targets Byte Offset 878 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO877 ,CPU Targets Byte Offset 877 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO876 ,CPU Targets Byte Offset 876 " group.long 0xB70++0x03 line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO883 ,CPU Targets Byte Offset 883 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO882 ,CPU Targets Byte Offset 882 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO881 ,CPU Targets Byte Offset 881 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO880 ,CPU Targets Byte Offset 880 " group.long 0xB74++0x03 line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO887 ,CPU Targets Byte Offset 887 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO886 ,CPU Targets Byte Offset 886 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO885 ,CPU Targets Byte Offset 885 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO884 ,CPU Targets Byte Offset 884 " group.long 0xB78++0x03 line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO891 ,CPU Targets Byte Offset 891 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO890 ,CPU Targets Byte Offset 890 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO889 ,CPU Targets Byte Offset 889 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO888 ,CPU Targets Byte Offset 888 " group.long 0xB7C++0x03 line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO895 ,CPU Targets Byte Offset 895 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO894 ,CPU Targets Byte Offset 894 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO893 ,CPU Targets Byte Offset 893 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO892 ,CPU Targets Byte Offset 892 " else hgroup.long 0xB60++0x03 hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hgroup.long 0xB64++0x03 hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hgroup.long 0xB68++0x03 hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hgroup.long 0xB6C++0x03 hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hgroup.long 0xB70++0x03 hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hgroup.long 0xB74++0x03 hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hgroup.long 0xB78++0x03 hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hgroup.long 0xB7C++0x03 hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0xB80++0x03 line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO899 ,CPU Targets Byte Offset 899 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO898 ,CPU Targets Byte Offset 898 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO897 ,CPU Targets Byte Offset 897 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO896 ,CPU Targets Byte Offset 896 " group.long 0xB84++0x03 line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO903 ,CPU Targets Byte Offset 903 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO902 ,CPU Targets Byte Offset 902 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO901 ,CPU Targets Byte Offset 901 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO900 ,CPU Targets Byte Offset 900 " group.long 0xB88++0x03 line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO907 ,CPU Targets Byte Offset 907 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO906 ,CPU Targets Byte Offset 906 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO905 ,CPU Targets Byte Offset 905 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO904 ,CPU Targets Byte Offset 904 " group.long 0xB8C++0x03 line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO911 ,CPU Targets Byte Offset 911 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO910 ,CPU Targets Byte Offset 910 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO909 ,CPU Targets Byte Offset 909 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO908 ,CPU Targets Byte Offset 908 " group.long 0xB90++0x03 line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO915 ,CPU Targets Byte Offset 915 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO914 ,CPU Targets Byte Offset 914 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO913 ,CPU Targets Byte Offset 913 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO912 ,CPU Targets Byte Offset 912 " group.long 0xB94++0x03 line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO919 ,CPU Targets Byte Offset 919 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO918 ,CPU Targets Byte Offset 918 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO917 ,CPU Targets Byte Offset 917 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO916 ,CPU Targets Byte Offset 916 " group.long 0xB98++0x03 line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO923 ,CPU Targets Byte Offset 923 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO922 ,CPU Targets Byte Offset 922 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO921 ,CPU Targets Byte Offset 921 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO920 ,CPU Targets Byte Offset 920 " group.long 0xB9C++0x03 line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO927 ,CPU Targets Byte Offset 927 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO926 ,CPU Targets Byte Offset 926 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO925 ,CPU Targets Byte Offset 925 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO924 ,CPU Targets Byte Offset 924 " else hgroup.long 0xB80++0x03 hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hgroup.long 0xB84++0x03 hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hgroup.long 0xB88++0x03 hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hgroup.long 0xB8C++0x03 hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hgroup.long 0xB90++0x03 hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hgroup.long 0xB94++0x03 hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hgroup.long 0xB98++0x03 hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hgroup.long 0xB9C++0x03 hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0xBA0++0x03 line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO931 ,CPU Targets Byte Offset 931 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO930 ,CPU Targets Byte Offset 930 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO929 ,CPU Targets Byte Offset 929 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO928 ,CPU Targets Byte Offset 928 " group.long 0xBA4++0x03 line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO935 ,CPU Targets Byte Offset 935 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO934 ,CPU Targets Byte Offset 934 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO933 ,CPU Targets Byte Offset 933 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO932 ,CPU Targets Byte Offset 932 " group.long 0xBA8++0x03 line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO939 ,CPU Targets Byte Offset 939 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO938 ,CPU Targets Byte Offset 938 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO937 ,CPU Targets Byte Offset 937 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO936 ,CPU Targets Byte Offset 936 " group.long 0xBAC++0x03 line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO943 ,CPU Targets Byte Offset 943 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO942 ,CPU Targets Byte Offset 942 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO941 ,CPU Targets Byte Offset 941 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO940 ,CPU Targets Byte Offset 940 " group.long 0xBB0++0x03 line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO947 ,CPU Targets Byte Offset 947 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO946 ,CPU Targets Byte Offset 946 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO945 ,CPU Targets Byte Offset 945 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO944 ,CPU Targets Byte Offset 944 " group.long 0xBB4++0x03 line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO951 ,CPU Targets Byte Offset 951 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO950 ,CPU Targets Byte Offset 950 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO949 ,CPU Targets Byte Offset 949 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO948 ,CPU Targets Byte Offset 948 " group.long 0xBB8++0x03 line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO955 ,CPU Targets Byte Offset 955 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO954 ,CPU Targets Byte Offset 954 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO953 ,CPU Targets Byte Offset 953 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO952 ,CPU Targets Byte Offset 952 " group.long 0xBBC++0x03 line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO959 ,CPU Targets Byte Offset 959 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO958 ,CPU Targets Byte Offset 958 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO957 ,CPU Targets Byte Offset 957 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO956 ,CPU Targets Byte Offset 956 " else hgroup.long 0xBA0++0x03 hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hgroup.long 0xBA4++0x03 hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hgroup.long 0xBA8++0x03 hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hgroup.long 0xBAC++0x03 hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hgroup.long 0xBB0++0x03 hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hgroup.long 0xBB4++0x03 hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hgroup.long 0xBB8++0x03 hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hgroup.long 0xBBC++0x03 hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0xBC0++0x03 line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO963 ,CPU Targets Byte Offset 963 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO962 ,CPU Targets Byte Offset 962 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO961 ,CPU Targets Byte Offset 961 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO960 ,CPU Targets Byte Offset 960 " group.long 0xBC4++0x03 line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO967 ,CPU Targets Byte Offset 967 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO966 ,CPU Targets Byte Offset 966 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO965 ,CPU Targets Byte Offset 965 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO964 ,CPU Targets Byte Offset 964 " group.long 0xBC8++0x03 line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO971 ,CPU Targets Byte Offset 971 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO970 ,CPU Targets Byte Offset 970 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO969 ,CPU Targets Byte Offset 969 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO968 ,CPU Targets Byte Offset 968 " group.long 0xBCC++0x03 line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO975 ,CPU Targets Byte Offset 975 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO974 ,CPU Targets Byte Offset 974 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO973 ,CPU Targets Byte Offset 973 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO972 ,CPU Targets Byte Offset 972 " group.long 0xBD0++0x03 line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO979 ,CPU Targets Byte Offset 979 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO978 ,CPU Targets Byte Offset 978 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO977 ,CPU Targets Byte Offset 977 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO976 ,CPU Targets Byte Offset 976 " group.long 0xBD4++0x03 line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO983 ,CPU Targets Byte Offset 983 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO982 ,CPU Targets Byte Offset 982 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO981 ,CPU Targets Byte Offset 981 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO980 ,CPU Targets Byte Offset 980 " group.long 0xBD8++0x03 line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO987 ,CPU Targets Byte Offset 987 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO986 ,CPU Targets Byte Offset 986 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO985 ,CPU Targets Byte Offset 985 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO984 ,CPU Targets Byte Offset 984 " group.long 0xBDC++0x03 line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO991 ,CPU Targets Byte Offset 991 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO990 ,CPU Targets Byte Offset 990 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO989 ,CPU Targets Byte Offset 989 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO988 ,CPU Targets Byte Offset 988 " else hgroup.long 0xBC0++0x03 hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hgroup.long 0xBC4++0x03 hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hgroup.long 0xBC8++0x03 hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hgroup.long 0xBCC++0x03 hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hgroup.long 0xBD0++0x03 hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hgroup.long 0xBD4++0x03 hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hgroup.long 0xBD8++0x03 hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hgroup.long 0xBDC++0x03 hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" endif else hgroup.long 0x800++0x03 hide.long 0x00 "GICD_ITARGETSR0 ,Interrupt Processor Targets Register 0 " hgroup.long 0x804++0x03 hide.long 0x00 "GICD_ITARGETSR1 ,Interrupt Processor Targets Register 1 " hgroup.long 0x808++0x03 hide.long 0x00 "GICD_ITARGETSR2 ,Interrupt Processor Targets Register 2 " hgroup.long 0x80C++0x03 hide.long 0x00 "GICD_ITARGETSR3 ,Interrupt Processor Targets Register 3 " hgroup.long 0x810++0x03 hide.long 0x00 "GICD_ITARGETSR4 ,Interrupt Processor Targets Register 4 " hgroup.long 0x814++0x03 hide.long 0x00 "GICD_ITARGETSR5 ,Interrupt Processor Targets Register 5 " hgroup.long 0x818++0x03 hide.long 0x00 "GICD_ITARGETSR6 ,Interrupt Processor Targets Register 6 " hgroup.long 0x81C++0x03 hide.long 0x00 "GICD_ITARGETSR7 ,Interrupt Processor Targets Register 7 " hgroup.long 0x820++0x03 hide.long 0x00 "GICD_ITARGETSR8 ,Interrupt Processor Targets Register 8 " hgroup.long 0x824++0x03 hide.long 0x00 "GICD_ITARGETSR9 ,Interrupt Processor Targets Register 9 " hgroup.long 0x828++0x03 hide.long 0x00 "GICD_ITARGETSR10 ,Interrupt Processor Targets Register 10 " hgroup.long 0x82C++0x03 hide.long 0x00 "GICD_ITARGETSR11 ,Interrupt Processor Targets Register 11 " hgroup.long 0x830++0x03 hide.long 0x00 "GICD_ITARGETSR12 ,Interrupt Processor Targets Register 12 " hgroup.long 0x834++0x03 hide.long 0x00 "GICD_ITARGETSR13 ,Interrupt Processor Targets Register 13 " hgroup.long 0x838++0x03 hide.long 0x00 "GICD_ITARGETSR14 ,Interrupt Processor Targets Register 14 " hgroup.long 0x83C++0x03 hide.long 0x00 "GICD_ITARGETSR15 ,Interrupt Processor Targets Register 15 " hgroup.long 0x840++0x03 hide.long 0x00 "GICD_ITARGETSR16 ,Interrupt Processor Targets Register 16 " hgroup.long 0x844++0x03 hide.long 0x00 "GICD_ITARGETSR17 ,Interrupt Processor Targets Register 17 " hgroup.long 0x848++0x03 hide.long 0x00 "GICD_ITARGETSR18 ,Interrupt Processor Targets Register 18 " hgroup.long 0x84C++0x03 hide.long 0x00 "GICD_ITARGETSR19 ,Interrupt Processor Targets Register 19 " hgroup.long 0x850++0x03 hide.long 0x00 "GICD_ITARGETSR20 ,Interrupt Processor Targets Register 20 " hgroup.long 0x854++0x03 hide.long 0x00 "GICD_ITARGETSR21 ,Interrupt Processor Targets Register 21 " hgroup.long 0x858++0x03 hide.long 0x00 "GICD_ITARGETSR22 ,Interrupt Processor Targets Register 22 " hgroup.long 0x85C++0x03 hide.long 0x00 "GICD_ITARGETSR23 ,Interrupt Processor Targets Register 23 " hgroup.long 0x860++0x03 hide.long 0x00 "GICD_ITARGETSR24 ,Interrupt Processor Targets Register 24 " hgroup.long 0x864++0x03 hide.long 0x00 "GICD_ITARGETSR25 ,Interrupt Processor Targets Register 25 " hgroup.long 0x868++0x03 hide.long 0x00 "GICD_ITARGETSR26 ,Interrupt Processor Targets Register 26 " hgroup.long 0x86C++0x03 hide.long 0x00 "GICD_ITARGETSR27 ,Interrupt Processor Targets Register 27 " hgroup.long 0x870++0x03 hide.long 0x00 "GICD_ITARGETSR28 ,Interrupt Processor Targets Register 28 " hgroup.long 0x874++0x03 hide.long 0x00 "GICD_ITARGETSR29 ,Interrupt Processor Targets Register 29 " hgroup.long 0x878++0x03 hide.long 0x00 "GICD_ITARGETSR30 ,Interrupt Processor Targets Register 30 " hgroup.long 0x87C++0x03 hide.long 0x00 "GICD_ITARGETSR31 ,Interrupt Processor Targets Register 31 " hgroup.long 0x880++0x03 hide.long 0x00 "GICD_ITARGETSR32 ,Interrupt Processor Targets Register 32 " hgroup.long 0x884++0x03 hide.long 0x00 "GICD_ITARGETSR33 ,Interrupt Processor Targets Register 33 " hgroup.long 0x888++0x03 hide.long 0x00 "GICD_ITARGETSR34 ,Interrupt Processor Targets Register 34 " hgroup.long 0x88C++0x03 hide.long 0x00 "GICD_ITARGETSR35 ,Interrupt Processor Targets Register 35 " hgroup.long 0x890++0x03 hide.long 0x00 "GICD_ITARGETSR36 ,Interrupt Processor Targets Register 36 " hgroup.long 0x894++0x03 hide.long 0x00 "GICD_ITARGETSR37 ,Interrupt Processor Targets Register 37 " hgroup.long 0x898++0x03 hide.long 0x00 "GICD_ITARGETSR38 ,Interrupt Processor Targets Register 38 " hgroup.long 0x89C++0x03 hide.long 0x00 "GICD_ITARGETSR39 ,Interrupt Processor Targets Register 39 " hgroup.long 0x8A0++0x03 hide.long 0x00 "GICD_ITARGETSR40 ,Interrupt Processor Targets Register 40 " hgroup.long 0x8A4++0x03 hide.long 0x00 "GICD_ITARGETSR41 ,Interrupt Processor Targets Register 41 " hgroup.long 0x8A8++0x03 hide.long 0x00 "GICD_ITARGETSR42 ,Interrupt Processor Targets Register 42 " hgroup.long 0x8AC++0x03 hide.long 0x00 "GICD_ITARGETSR43 ,Interrupt Processor Targets Register 43 " hgroup.long 0x8B0++0x03 hide.long 0x00 "GICD_ITARGETSR44 ,Interrupt Processor Targets Register 44 " hgroup.long 0x8B4++0x03 hide.long 0x00 "GICD_ITARGETSR45 ,Interrupt Processor Targets Register 45 " hgroup.long 0x8B8++0x03 hide.long 0x00 "GICD_ITARGETSR46 ,Interrupt Processor Targets Register 46 " hgroup.long 0x8BC++0x03 hide.long 0x00 "GICD_ITARGETSR47 ,Interrupt Processor Targets Register 47 " hgroup.long 0x8C0++0x03 hide.long 0x00 "GICD_ITARGETSR48 ,Interrupt Processor Targets Register 48 " hgroup.long 0x8C4++0x03 hide.long 0x00 "GICD_ITARGETSR49 ,Interrupt Processor Targets Register 49 " hgroup.long 0x8C8++0x03 hide.long 0x00 "GICD_ITARGETSR50 ,Interrupt Processor Targets Register 50 " hgroup.long 0x8CC++0x03 hide.long 0x00 "GICD_ITARGETSR51 ,Interrupt Processor Targets Register 51 " hgroup.long 0x8D0++0x03 hide.long 0x00 "GICD_ITARGETSR52 ,Interrupt Processor Targets Register 52 " hgroup.long 0x8D4++0x03 hide.long 0x00 "GICD_ITARGETSR53 ,Interrupt Processor Targets Register 53 " hgroup.long 0x8D8++0x03 hide.long 0x00 "GICD_ITARGETSR54 ,Interrupt Processor Targets Register 54 " hgroup.long 0x8DC++0x03 hide.long 0x00 "GICD_ITARGETSR55 ,Interrupt Processor Targets Register 55 " hgroup.long 0x8E0++0x03 hide.long 0x00 "GICD_ITARGETSR56 ,Interrupt Processor Targets Register 56 " hgroup.long 0x8E4++0x03 hide.long 0x00 "GICD_ITARGETSR57 ,Interrupt Processor Targets Register 57 " hgroup.long 0x8E8++0x03 hide.long 0x00 "GICD_ITARGETSR58 ,Interrupt Processor Targets Register 58 " hgroup.long 0x8EC++0x03 hide.long 0x00 "GICD_ITARGETSR59 ,Interrupt Processor Targets Register 59 " hgroup.long 0x8F0++0x03 hide.long 0x00 "GICD_ITARGETSR60 ,Interrupt Processor Targets Register 60 " hgroup.long 0x8F4++0x03 hide.long 0x00 "GICD_ITARGETSR61 ,Interrupt Processor Targets Register 61 " hgroup.long 0x8F8++0x03 hide.long 0x00 "GICD_ITARGETSR62 ,Interrupt Processor Targets Register 62 " hgroup.long 0x8FC++0x03 hide.long 0x00 "GICD_ITARGETSR63 ,Interrupt Processor Targets Register 63 " hgroup.long 0x900++0x03 hide.long 0x00 "GICD_ITARGETSR64 ,Interrupt Processor Targets Register 64 " hgroup.long 0x904++0x03 hide.long 0x00 "GICD_ITARGETSR65 ,Interrupt Processor Targets Register 65 " hgroup.long 0x908++0x03 hide.long 0x00 "GICD_ITARGETSR66 ,Interrupt Processor Targets Register 66 " hgroup.long 0x90C++0x03 hide.long 0x00 "GICD_ITARGETSR67 ,Interrupt Processor Targets Register 67 " hgroup.long 0x910++0x03 hide.long 0x00 "GICD_ITARGETSR68 ,Interrupt Processor Targets Register 68 " hgroup.long 0x914++0x03 hide.long 0x00 "GICD_ITARGETSR69 ,Interrupt Processor Targets Register 69 " hgroup.long 0x918++0x03 hide.long 0x00 "GICD_ITARGETSR70 ,Interrupt Processor Targets Register 70 " hgroup.long 0x91C++0x03 hide.long 0x00 "GICD_ITARGETSR71 ,Interrupt Processor Targets Register 71 " hgroup.long 0x920++0x03 hide.long 0x00 "GICD_ITARGETSR72 ,Interrupt Processor Targets Register 72 " hgroup.long 0x924++0x03 hide.long 0x00 "GICD_ITARGETSR73 ,Interrupt Processor Targets Register 73 " hgroup.long 0x928++0x03 hide.long 0x00 "GICD_ITARGETSR74 ,Interrupt Processor Targets Register 74 " hgroup.long 0x92C++0x03 hide.long 0x00 "GICD_ITARGETSR75 ,Interrupt Processor Targets Register 75 " hgroup.long 0x930++0x03 hide.long 0x00 "GICD_ITARGETSR76 ,Interrupt Processor Targets Register 76 " hgroup.long 0x934++0x03 hide.long 0x00 "GICD_ITARGETSR77 ,Interrupt Processor Targets Register 77 " hgroup.long 0x938++0x03 hide.long 0x00 "GICD_ITARGETSR78 ,Interrupt Processor Targets Register 78 " hgroup.long 0x93C++0x03 hide.long 0x00 "GICD_ITARGETSR79 ,Interrupt Processor Targets Register 79 " hgroup.long 0x940++0x03 hide.long 0x00 "GICD_ITARGETSR80 ,Interrupt Processor Targets Register 80 " hgroup.long 0x944++0x03 hide.long 0x00 "GICD_ITARGETSR81 ,Interrupt Processor Targets Register 81 " hgroup.long 0x948++0x03 hide.long 0x00 "GICD_ITARGETSR82 ,Interrupt Processor Targets Register 82 " hgroup.long 0x94C++0x03 hide.long 0x00 "GICD_ITARGETSR83 ,Interrupt Processor Targets Register 83 " hgroup.long 0x950++0x03 hide.long 0x00 "GICD_ITARGETSR84 ,Interrupt Processor Targets Register 84 " hgroup.long 0x954++0x03 hide.long 0x00 "GICD_ITARGETSR85 ,Interrupt Processor Targets Register 85 " hgroup.long 0x958++0x03 hide.long 0x00 "GICD_ITARGETSR86 ,Interrupt Processor Targets Register 86 " hgroup.long 0x95C++0x03 hide.long 0x00 "GICD_ITARGETSR87 ,Interrupt Processor Targets Register 87 " hgroup.long 0x960++0x03 hide.long 0x00 "GICD_ITARGETSR88 ,Interrupt Processor Targets Register 88 " hgroup.long 0x964++0x03 hide.long 0x00 "GICD_ITARGETSR89 ,Interrupt Processor Targets Register 89 " hgroup.long 0x968++0x03 hide.long 0x00 "GICD_ITARGETSR90 ,Interrupt Processor Targets Register 90 " hgroup.long 0x96C++0x03 hide.long 0x00 "GICD_ITARGETSR91 ,Interrupt Processor Targets Register 91 " hgroup.long 0x970++0x03 hide.long 0x00 "GICD_ITARGETSR92 ,Interrupt Processor Targets Register 92 " hgroup.long 0x974++0x03 hide.long 0x00 "GICD_ITARGETSR93 ,Interrupt Processor Targets Register 93 " hgroup.long 0x978++0x03 hide.long 0x00 "GICD_ITARGETSR94 ,Interrupt Processor Targets Register 94 " hgroup.long 0x97C++0x03 hide.long 0x00 "GICD_ITARGETSR95 ,Interrupt Processor Targets Register 95 " hgroup.long 0x980++0x03 hide.long 0x00 "GICD_ITARGETSR96 ,Interrupt Processor Targets Register 96 " hgroup.long 0x984++0x03 hide.long 0x00 "GICD_ITARGETSR97 ,Interrupt Processor Targets Register 97 " hgroup.long 0x988++0x03 hide.long 0x00 "GICD_ITARGETSR98 ,Interrupt Processor Targets Register 98 " hgroup.long 0x98C++0x03 hide.long 0x00 "GICD_ITARGETSR99 ,Interrupt Processor Targets Register 99 " hgroup.long 0x990++0x03 hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hgroup.long 0x994++0x03 hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hgroup.long 0x998++0x03 hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hgroup.long 0x99C++0x03 hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" hgroup.long 0x9A0++0x03 hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hgroup.long 0x9A4++0x03 hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hgroup.long 0x9A8++0x03 hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hgroup.long 0x9AC++0x03 hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hgroup.long 0x9B0++0x03 hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hgroup.long 0x9B4++0x03 hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hgroup.long 0x9B8++0x03 hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hgroup.long 0x9BC++0x03 hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" hgroup.long 0x9C0++0x03 hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hgroup.long 0x9C4++0x03 hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hgroup.long 0x9C8++0x03 hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hgroup.long 0x9CC++0x03 hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hgroup.long 0x9D0++0x03 hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hgroup.long 0x9D4++0x03 hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hgroup.long 0x9D8++0x03 hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hgroup.long 0x9DC++0x03 hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" hgroup.long 0x9E0++0x03 hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hgroup.long 0x9E4++0x03 hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hgroup.long 0x9E8++0x03 hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hgroup.long 0x9EC++0x03 hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hgroup.long 0x9F0++0x03 hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hgroup.long 0x9F4++0x03 hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hgroup.long 0x9F8++0x03 hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hgroup.long 0x9FC++0x03 hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" hgroup.long 0xA00++0x03 hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hgroup.long 0xA04++0x03 hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hgroup.long 0xA08++0x03 hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hgroup.long 0xA0C++0x03 hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hgroup.long 0xA10++0x03 hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hgroup.long 0xA14++0x03 hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hgroup.long 0xA18++0x03 hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hgroup.long 0xA1C++0x03 hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" hgroup.long 0xA20++0x03 hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hgroup.long 0xA24++0x03 hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hgroup.long 0xA28++0x03 hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hgroup.long 0xA2C++0x03 hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hgroup.long 0xA30++0x03 hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hgroup.long 0xA34++0x03 hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hgroup.long 0xA38++0x03 hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hgroup.long 0xA3C++0x03 hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" hgroup.long 0xA40++0x03 hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hgroup.long 0xA44++0x03 hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hgroup.long 0xA48++0x03 hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hgroup.long 0xA4C++0x03 hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hgroup.long 0xA50++0x03 hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hgroup.long 0xA54++0x03 hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hgroup.long 0xA58++0x03 hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hgroup.long 0xA5C++0x03 hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" hgroup.long 0xA60++0x03 hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hgroup.long 0xA64++0x03 hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hgroup.long 0xA68++0x03 hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hgroup.long 0xA6C++0x03 hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hgroup.long 0xA70++0x03 hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hgroup.long 0xA74++0x03 hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hgroup.long 0xA78++0x03 hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hgroup.long 0xA7C++0x03 hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" hgroup.long 0xA80++0x03 hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hgroup.long 0xA84++0x03 hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hgroup.long 0xA88++0x03 hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hgroup.long 0xA8C++0x03 hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hgroup.long 0xA90++0x03 hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hgroup.long 0xA94++0x03 hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hgroup.long 0xA98++0x03 hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hgroup.long 0xA9C++0x03 hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" hgroup.long 0xAA0++0x03 hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hgroup.long 0xAA4++0x03 hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hgroup.long 0xAA8++0x03 hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hgroup.long 0xAAC++0x03 hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hgroup.long 0xAB0++0x03 hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hgroup.long 0xAB4++0x03 hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hgroup.long 0xAB8++0x03 hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hgroup.long 0xABC++0x03 hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" hgroup.long 0xAC0++0x03 hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hgroup.long 0xAC4++0x03 hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hgroup.long 0xAC8++0x03 hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hgroup.long 0xACC++0x03 hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hgroup.long 0xAD0++0x03 hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hgroup.long 0xAD4++0x03 hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hgroup.long 0xAD8++0x03 hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hgroup.long 0xADC++0x03 hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" hgroup.long 0xAE0++0x03 hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hgroup.long 0xAE4++0x03 hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hgroup.long 0xAE8++0x03 hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hgroup.long 0xAEC++0x03 hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hgroup.long 0xAF0++0x03 hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hgroup.long 0xAF4++0x03 hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hgroup.long 0xAF8++0x03 hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hgroup.long 0xAFC++0x03 hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" hgroup.long 0xB00++0x03 hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hgroup.long 0xB04++0x03 hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hgroup.long 0xB08++0x03 hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hgroup.long 0xB0C++0x03 hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hgroup.long 0xB10++0x03 hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hgroup.long 0xB14++0x03 hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hgroup.long 0xB18++0x03 hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hgroup.long 0xB1C++0x03 hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" hgroup.long 0xB20++0x03 hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hgroup.long 0xB24++0x03 hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hgroup.long 0xB28++0x03 hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hgroup.long 0xB2C++0x03 hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hgroup.long 0xB30++0x03 hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hgroup.long 0xB34++0x03 hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hgroup.long 0xB38++0x03 hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hgroup.long 0xB3C++0x03 hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" hgroup.long 0xB40++0x03 hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hgroup.long 0xB44++0x03 hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hgroup.long 0xB48++0x03 hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hgroup.long 0xB4C++0x03 hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hgroup.long 0xB50++0x03 hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hgroup.long 0xB54++0x03 hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hgroup.long 0xB58++0x03 hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hgroup.long 0xB5C++0x03 hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" hgroup.long 0xB60++0x03 hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hgroup.long 0xB64++0x03 hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hgroup.long 0xB68++0x03 hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hgroup.long 0xB6C++0x03 hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hgroup.long 0xB70++0x03 hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hgroup.long 0xB74++0x03 hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hgroup.long 0xB78++0x03 hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hgroup.long 0xB7C++0x03 hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" hgroup.long 0xB80++0x03 hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hgroup.long 0xB84++0x03 hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hgroup.long 0xB88++0x03 hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hgroup.long 0xB8C++0x03 hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hgroup.long 0xB90++0x03 hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hgroup.long 0xB94++0x03 hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hgroup.long 0xB98++0x03 hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hgroup.long 0xB9C++0x03 hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" hgroup.long 0xBA0++0x03 hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hgroup.long 0xBA4++0x03 hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hgroup.long 0xBA8++0x03 hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hgroup.long 0xBAC++0x03 hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hgroup.long 0xBB0++0x03 hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hgroup.long 0xBB4++0x03 hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hgroup.long 0xBB8++0x03 hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hgroup.long 0xBBC++0x03 hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" hgroup.long 0xBC0++0x03 hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hgroup.long 0xBC4++0x03 hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hgroup.long 0xBC8++0x03 hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hgroup.long 0xBCC++0x03 hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hgroup.long 0xBD0++0x03 hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hgroup.long 0xBD4++0x03 hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hgroup.long 0xBD8++0x03 hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hgroup.long 0xBDC++0x03 hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" endif tree.end width 14. tree "Configuration Registers" rgroup.long 0xC00++0x03 line.long 0x00 "GICD_ICFGR0,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SGI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SGI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SGI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SGI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SGI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SGI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SGI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SGI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SGI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SGI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SGI)" "Level,Edge" group.long 0xC04++0x03 line.long 0x00 "GICD_ICFGR1,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (PPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (PPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (PPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (PPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (PPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (PPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (PPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (PPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (PPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (PPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (PPI)" "Level,Edge" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1) group.long 0xC08++0x03 line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC0C++0x03 line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC08++0x03 hide.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" hgroup.long 0xC0C++0x03 hide.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2) group.long 0xC10++0x03 line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC14++0x03 line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC10++0x03 hide.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" hgroup.long 0xC14++0x03 hide.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3) group.long 0xC18++0x03 line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC1C++0x03 line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC18++0x03 hide.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" hgroup.long 0xC1C++0x03 hide.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4) group.long 0xC20++0x03 line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC24++0x03 line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC20++0x03 hide.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" hgroup.long 0xC24++0x03 hide.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5) group.long 0xC28++0x03 line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC2C++0x03 line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC28++0x03 hide.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" hgroup.long 0xC2C++0x03 hide.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6) group.long 0xC30++0x03 line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC34++0x03 line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC30++0x03 hide.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" hgroup.long 0xC34++0x03 hide.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7) group.long 0xC38++0x03 line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC3C++0x03 line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC38++0x03 hide.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" hgroup.long 0xC3C++0x03 hide.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8) group.long 0xC40++0x03 line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC44++0x03 line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC40++0x03 hide.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" hgroup.long 0xC44++0x03 hide.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9) group.long 0xC48++0x03 line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC4C++0x03 line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC48++0x03 hide.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" hgroup.long 0xC4C++0x03 hide.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA) group.long 0xC50++0x03 line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC54++0x03 line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC50++0x03 hide.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" hgroup.long 0xC54++0x03 hide.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB) group.long 0xC58++0x03 line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC5C++0x03 line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC58++0x03 hide.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" hgroup.long 0xC5C++0x03 hide.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC) group.long 0xC60++0x03 line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC64++0x03 line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC60++0x03 hide.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" hgroup.long 0xC64++0x03 hide.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD) group.long 0xC68++0x03 line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC6C++0x03 line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC68++0x03 hide.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" hgroup.long 0xC6C++0x03 hide.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE) group.long 0xC70++0x03 line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC74++0x03 line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC70++0x03 hide.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" hgroup.long 0xC74++0x03 hide.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF) group.long 0xC78++0x03 line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC7C++0x03 line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC78++0x03 hide.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" hgroup.long 0xC7C++0x03 hide.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0xC80++0x03 line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC84++0x03 line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC80++0x03 hide.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" hgroup.long 0xC84++0x03 hide.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0xC88++0x03 line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC8C++0x03 line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC88++0x03 hide.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" hgroup.long 0xC8C++0x03 hide.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0xC90++0x03 line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC94++0x03 line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC90++0x03 hide.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" hgroup.long 0xC94++0x03 hide.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0xC98++0x03 line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC9C++0x03 line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC98++0x03 hide.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" hgroup.long 0xC9C++0x03 hide.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0xCA0++0x03 line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCA4++0x03 line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCA0++0x03 hide.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" hgroup.long 0xCA4++0x03 hide.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0xCA8++0x03 line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCAC++0x03 line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCA8++0x03 hide.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" hgroup.long 0xCAC++0x03 hide.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0xCB0++0x03 line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCB4++0x03 line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCB0++0x03 hide.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" hgroup.long 0xCB4++0x03 hide.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0xCB8++0x03 line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCBC++0x03 line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCB8++0x03 hide.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" hgroup.long 0xCBC++0x03 hide.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0xCC0++0x03 line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCC4++0x03 line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCC0++0x03 hide.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" hgroup.long 0xCC4++0x03 hide.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0xCC8++0x03 line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCCC++0x03 line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCC8++0x03 hide.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" hgroup.long 0xCCC++0x03 hide.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0xCD0++0x03 line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCD4++0x03 line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCD0++0x03 hide.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" hgroup.long 0xCD4++0x03 hide.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0xCD8++0x03 line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCDC++0x03 line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCD8++0x03 hide.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" hgroup.long 0xCDC++0x03 hide.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0xCE0++0x03 line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCE4++0x03 line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCE0++0x03 hide.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" hgroup.long 0xCE4++0x03 hide.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0xCE8++0x03 line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCEC++0x03 line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCE8++0x03 hide.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" hgroup.long 0xCEC++0x03 hide.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0xCF0++0x03 line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCF4++0x03 line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCF0++0x03 hide.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" hgroup.long 0xCF4++0x03 hide.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" endif tree.end width 17. tree "Interrupt Group Modifier Registers" hgroup.long 0x0D00++0x03 hide.long 0x0 "GICD_IGRPMODR0,Interrupt Group Modifier Register 0" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D00))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)) group.long 0x0D04++0x03 line.long 0x0 "GICD_IGRPMODR1,Interrupt Group Modifier Register 1" bitfld.long 0x00 31. " GMB63 ,Group Modifier Bit 63" "0,1" bitfld.long 0x00 30. " GMB62 ,Group Modifier Bit 62" "0,1" bitfld.long 0x00 29. " GMB61 ,Group Modifier Bit 61" "0,1" textline " " bitfld.long 0x00 28. " GMB60 ,Group Modifier Bit 60" "0,1" bitfld.long 0x00 27. " GMB59 ,Group Modifier Bit 59" "0,1" bitfld.long 0x00 26. " GMB58 ,Group Modifier Bit 58" "0,1" textline " " bitfld.long 0x00 25. " GMB57 ,Group Modifier Bit 57" "0,1" bitfld.long 0x00 24. " GMB56 ,Group Modifier Bit 56" "0,1" bitfld.long 0x00 23. " GMB55 ,Group Modifier Bit 55" "0,1" textline " " bitfld.long 0x00 22. " GMB54 ,Group Modifier Bit 54" "0,1" bitfld.long 0x00 21. " GMB53 ,Group Modifier Bit 53" "0,1" bitfld.long 0x00 20. " GMB52 ,Group Modifier Bit 52" "0,1" textline " " bitfld.long 0x00 19. " GMB51 ,Group Modifier Bit 51" "0,1" bitfld.long 0x00 18. " GMB50 ,Group Modifier Bit 50" "0,1" bitfld.long 0x00 17. " GMB49 ,Group Modifier Bit 49" "0,1" textline " " bitfld.long 0x00 16. " GMB48 ,Group Modifier Bit 48" "0,1" bitfld.long 0x00 15. " GMB47 ,Group Modifier Bit 47" "0,1" bitfld.long 0x00 14. " GMB46 ,Group Modifier Bit 46" "0,1" textline " " bitfld.long 0x00 13. " GMB45 ,Group Modifier Bit 45" "0,1" bitfld.long 0x00 12. " GMB44 ,Group Modifier Bit 44" "0,1" bitfld.long 0x00 11. " GMB43 ,Group Modifier Bit 43" "0,1" textline " " bitfld.long 0x00 10. " GMB42 ,Group Modifier Bit 42" "0,1" bitfld.long 0x00 9. " GMB41 ,Group Modifier Bit 41" "0,1" bitfld.long 0x00 8. " GMB40 ,Group Modifier Bit 40" "0,1" textline " " bitfld.long 0x00 7. " GMB39 ,Group Modifier Bit 39" "0,1" bitfld.long 0x00 6. " GMB38 ,Group Modifier Bit 38" "0,1" bitfld.long 0x00 5. " GMB37 ,Group Modifier Bit 37" "0,1" textline " " bitfld.long 0x00 4. " GMB36 ,Group Modifier Bit 36" "0,1" bitfld.long 0x00 3. " GMB35 ,Group Modifier Bit 35" "0,1" bitfld.long 0x00 2. " GMB34 ,Group Modifier Bit 34" "0,1" textline " " bitfld.long 0x00 1. " GMB33 ,Group Modifier Bit 33" "0,1" bitfld.long 0x00 0. " GMB32 ,Group Modifier Bit 32" "0,1" else hgroup.long 0x0D04++0x03 hide.long 0x0 "GICD_IGRPMODR1,Interrupt Group Modifier Register 1" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D08))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)) group.long 0x0D08++0x03 line.long 0x0 "GICD_IGRPMODR2,Interrupt Group Modifier Register 2" bitfld.long 0x00 31. " GMB95 ,Group Modifier Bit 95" "0,1" bitfld.long 0x00 30. " GMB94 ,Group Modifier Bit 94" "0,1" bitfld.long 0x00 29. " GMB93 ,Group Modifier Bit 93" "0,1" textline " " bitfld.long 0x00 28. " GMB92 ,Group Modifier Bit 92" "0,1" bitfld.long 0x00 27. " GMB91 ,Group Modifier Bit 91" "0,1" bitfld.long 0x00 26. " GMB90 ,Group Modifier Bit 90" "0,1" textline " " bitfld.long 0x00 25. " GMB89 ,Group Modifier Bit 89" "0,1" bitfld.long 0x00 24. " GMB88 ,Group Modifier Bit 88" "0,1" bitfld.long 0x00 23. " GMB87 ,Group Modifier Bit 87" "0,1" textline " " bitfld.long 0x00 22. " GMB86 ,Group Modifier Bit 86" "0,1" bitfld.long 0x00 21. " GMB85 ,Group Modifier Bit 85" "0,1" bitfld.long 0x00 20. " GMB84 ,Group Modifier Bit 84" "0,1" textline " " bitfld.long 0x00 19. " GMB83 ,Group Modifier Bit 83" "0,1" bitfld.long 0x00 18. " GMB82 ,Group Modifier Bit 82" "0,1" bitfld.long 0x00 17. " GMB81 ,Group Modifier Bit 81" "0,1" textline " " bitfld.long 0x00 16. " GMB80 ,Group Modifier Bit 80" "0,1" bitfld.long 0x00 15. " GMB79 ,Group Modifier Bit 79" "0,1" bitfld.long 0x00 14. " GMB78 ,Group Modifier Bit 78" "0,1" textline " " bitfld.long 0x00 13. " GMB77 ,Group Modifier Bit 77" "0,1" bitfld.long 0x00 12. " GMB76 ,Group Modifier Bit 76" "0,1" bitfld.long 0x00 11. " GMB75 ,Group Modifier Bit 75" "0,1" textline " " bitfld.long 0x00 10. " GMB74 ,Group Modifier Bit 74" "0,1" bitfld.long 0x00 9. " GMB73 ,Group Modifier Bit 73" "0,1" bitfld.long 0x00 8. " GMB72 ,Group Modifier Bit 72" "0,1" textline " " bitfld.long 0x00 7. " GMB71 ,Group Modifier Bit 71" "0,1" bitfld.long 0x00 6. " GMB70 ,Group Modifier Bit 70" "0,1" bitfld.long 0x00 5. " GMB69 ,Group Modifier Bit 69" "0,1" textline " " bitfld.long 0x00 4. " GMB68 ,Group Modifier Bit 68" "0,1" bitfld.long 0x00 3. " GMB67 ,Group Modifier Bit 67" "0,1" bitfld.long 0x00 2. " GMB66 ,Group Modifier Bit 66" "0,1" textline " " bitfld.long 0x00 1. " GMB65 ,Group Modifier Bit 65" "0,1" bitfld.long 0x00 0. " GMB64 ,Group Modifier Bit 64" "0,1" else hgroup.long 0x0D08++0x03 hide.long 0x0 "GICD_IGRPMODR2,Interrupt Group Modifier Register 2" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D0C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)) group.long 0x0D0C++0x03 line.long 0x0 "GICD_IGRPMODR3,Interrupt Group Modifier Register 3" bitfld.long 0x00 31. " GMB127 ,Group Modifier Bit 127" "0,1" bitfld.long 0x00 30. " GMB126 ,Group Modifier Bit 126" "0,1" bitfld.long 0x00 29. " GMB125 ,Group Modifier Bit 125" "0,1" textline " " bitfld.long 0x00 28. " GMB124 ,Group Modifier Bit 124" "0,1" bitfld.long 0x00 27. " GMB123 ,Group Modifier Bit 123" "0,1" bitfld.long 0x00 26. " GMB122 ,Group Modifier Bit 122" "0,1" textline " " bitfld.long 0x00 25. " GMB121 ,Group Modifier Bit 121" "0,1" bitfld.long 0x00 24. " GMB120 ,Group Modifier Bit 120" "0,1" bitfld.long 0x00 23. " GMB119 ,Group Modifier Bit 119" "0,1" textline " " bitfld.long 0x00 22. " GMB118 ,Group Modifier Bit 118" "0,1" bitfld.long 0x00 21. " GMB117 ,Group Modifier Bit 117" "0,1" bitfld.long 0x00 20. " GMB116 ,Group Modifier Bit 116" "0,1" textline " " bitfld.long 0x00 19. " GMB115 ,Group Modifier Bit 115" "0,1" bitfld.long 0x00 18. " GMB114 ,Group Modifier Bit 114" "0,1" bitfld.long 0x00 17. " GMB113 ,Group Modifier Bit 113" "0,1" textline " " bitfld.long 0x00 16. " GMB112 ,Group Modifier Bit 112" "0,1" bitfld.long 0x00 15. " GMB111 ,Group Modifier Bit 111" "0,1" bitfld.long 0x00 14. " GMB110 ,Group Modifier Bit 110" "0,1" textline " " bitfld.long 0x00 13. " GMB109 ,Group Modifier Bit 109" "0,1" bitfld.long 0x00 12. " GMB108 ,Group Modifier Bit 108" "0,1" bitfld.long 0x00 11. " GMB107 ,Group Modifier Bit 107" "0,1" textline " " bitfld.long 0x00 10. " GMB106 ,Group Modifier Bit 106" "0,1" bitfld.long 0x00 9. " GMB105 ,Group Modifier Bit 105" "0,1" bitfld.long 0x00 8. " GMB104 ,Group Modifier Bit 104" "0,1" textline " " bitfld.long 0x00 7. " GMB103 ,Group Modifier Bit 103" "0,1" bitfld.long 0x00 6. " GMB102 ,Group Modifier Bit 102" "0,1" bitfld.long 0x00 5. " GMB101 ,Group Modifier Bit 101" "0,1" textline " " bitfld.long 0x00 4. " GMB100 ,Group Modifier Bit 100" "0,1" bitfld.long 0x00 3. " GMB99 ,Group Modifier Bit 99" "0,1" bitfld.long 0x00 2. " GMB98 ,Group Modifier Bit 98" "0,1" textline " " bitfld.long 0x00 1. " GMB97 ,Group Modifier Bit 97" "0,1" bitfld.long 0x00 0. " GMB96 ,Group Modifier Bit 96" "0,1" else hgroup.long 0x0D0C++0x03 hide.long 0x0 "GICD_IGRPMODR3,Interrupt Group Modifier Register 3" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D10))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)) group.long 0x0D10++0x03 line.long 0x0 "GICD_IGRPMODR4,Interrupt Group Modifier Register 4" bitfld.long 0x00 31. " GMB159 ,Group Modifier Bit 159" "0,1" bitfld.long 0x00 30. " GMB158 ,Group Modifier Bit 158" "0,1" bitfld.long 0x00 29. " GMB157 ,Group Modifier Bit 157" "0,1" textline " " bitfld.long 0x00 28. " GMB156 ,Group Modifier Bit 156" "0,1" bitfld.long 0x00 27. " GMB155 ,Group Modifier Bit 155" "0,1" bitfld.long 0x00 26. " GMB154 ,Group Modifier Bit 154" "0,1" textline " " bitfld.long 0x00 25. " GMB153 ,Group Modifier Bit 153" "0,1" bitfld.long 0x00 24. " GMB152 ,Group Modifier Bit 152" "0,1" bitfld.long 0x00 23. " GMB151 ,Group Modifier Bit 151" "0,1" textline " " bitfld.long 0x00 22. " GMB150 ,Group Modifier Bit 150" "0,1" bitfld.long 0x00 21. " GMB149 ,Group Modifier Bit 149" "0,1" bitfld.long 0x00 20. " GMB148 ,Group Modifier Bit 148" "0,1" textline " " bitfld.long 0x00 19. " GMB147 ,Group Modifier Bit 147" "0,1" bitfld.long 0x00 18. " GMB146 ,Group Modifier Bit 146" "0,1" bitfld.long 0x00 17. " GMB145 ,Group Modifier Bit 145" "0,1" textline " " bitfld.long 0x00 16. " GMB144 ,Group Modifier Bit 144" "0,1" bitfld.long 0x00 15. " GMB143 ,Group Modifier Bit 143" "0,1" bitfld.long 0x00 14. " GMB142 ,Group Modifier Bit 142" "0,1" textline " " bitfld.long 0x00 13. " GMB141 ,Group Modifier Bit 141" "0,1" bitfld.long 0x00 12. " GMB140 ,Group Modifier Bit 140" "0,1" bitfld.long 0x00 11. " GMB139 ,Group Modifier Bit 139" "0,1" textline " " bitfld.long 0x00 10. " GMB138 ,Group Modifier Bit 138" "0,1" bitfld.long 0x00 9. " GMB137 ,Group Modifier Bit 137" "0,1" bitfld.long 0x00 8. " GMB136 ,Group Modifier Bit 136" "0,1" textline " " bitfld.long 0x00 7. " GMB135 ,Group Modifier Bit 135" "0,1" bitfld.long 0x00 6. " GMB134 ,Group Modifier Bit 134" "0,1" bitfld.long 0x00 5. " GMB133 ,Group Modifier Bit 133" "0,1" textline " " bitfld.long 0x00 4. " GMB132 ,Group Modifier Bit 132" "0,1" bitfld.long 0x00 3. " GMB131 ,Group Modifier Bit 131" "0,1" bitfld.long 0x00 2. " GMB130 ,Group Modifier Bit 130" "0,1" textline " " bitfld.long 0x00 1. " GMB129 ,Group Modifier Bit 129" "0,1" bitfld.long 0x00 0. " GMB128 ,Group Modifier Bit 128" "0,1" else hgroup.long 0x0D10++0x03 hide.long 0x0 "GICD_IGRPMODR4,Interrupt Group Modifier Register 4" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D14))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)) group.long 0x0D14++0x03 line.long 0x0 "GICD_IGRPMODR5,Interrupt Group Modifier Register 5" bitfld.long 0x00 31. " GMB191 ,Group Modifier Bit 191" "0,1" bitfld.long 0x00 30. " GMB190 ,Group Modifier Bit 190" "0,1" bitfld.long 0x00 29. " GMB189 ,Group Modifier Bit 189" "0,1" textline " " bitfld.long 0x00 28. " GMB188 ,Group Modifier Bit 188" "0,1" bitfld.long 0x00 27. " GMB187 ,Group Modifier Bit 187" "0,1" bitfld.long 0x00 26. " GMB186 ,Group Modifier Bit 186" "0,1" textline " " bitfld.long 0x00 25. " GMB185 ,Group Modifier Bit 185" "0,1" bitfld.long 0x00 24. " GMB184 ,Group Modifier Bit 184" "0,1" bitfld.long 0x00 23. " GMB183 ,Group Modifier Bit 183" "0,1" textline " " bitfld.long 0x00 22. " GMB182 ,Group Modifier Bit 182" "0,1" bitfld.long 0x00 21. " GMB181 ,Group Modifier Bit 181" "0,1" bitfld.long 0x00 20. " GMB180 ,Group Modifier Bit 180" "0,1" textline " " bitfld.long 0x00 19. " GMB179 ,Group Modifier Bit 179" "0,1" bitfld.long 0x00 18. " GMB178 ,Group Modifier Bit 178" "0,1" bitfld.long 0x00 17. " GMB177 ,Group Modifier Bit 177" "0,1" textline " " bitfld.long 0x00 16. " GMB176 ,Group Modifier Bit 176" "0,1" bitfld.long 0x00 15. " GMB175 ,Group Modifier Bit 175" "0,1" bitfld.long 0x00 14. " GMB174 ,Group Modifier Bit 174" "0,1" textline " " bitfld.long 0x00 13. " GMB173 ,Group Modifier Bit 173" "0,1" bitfld.long 0x00 12. " GMB172 ,Group Modifier Bit 172" "0,1" bitfld.long 0x00 11. " GMB171 ,Group Modifier Bit 171" "0,1" textline " " bitfld.long 0x00 10. " GMB170 ,Group Modifier Bit 170" "0,1" bitfld.long 0x00 9. " GMB169 ,Group Modifier Bit 169" "0,1" bitfld.long 0x00 8. " GMB168 ,Group Modifier Bit 168" "0,1" textline " " bitfld.long 0x00 7. " GMB167 ,Group Modifier Bit 167" "0,1" bitfld.long 0x00 6. " GMB166 ,Group Modifier Bit 166" "0,1" bitfld.long 0x00 5. " GMB165 ,Group Modifier Bit 165" "0,1" textline " " bitfld.long 0x00 4. " GMB164 ,Group Modifier Bit 164" "0,1" bitfld.long 0x00 3. " GMB163 ,Group Modifier Bit 163" "0,1" bitfld.long 0x00 2. " GMB162 ,Group Modifier Bit 162" "0,1" textline " " bitfld.long 0x00 1. " GMB161 ,Group Modifier Bit 161" "0,1" bitfld.long 0x00 0. " GMB160 ,Group Modifier Bit 160" "0,1" else hgroup.long 0x0D14++0x03 hide.long 0x0 "GICD_IGRPMODR5,Interrupt Group Modifier Register 5" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D18))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)) group.long 0x0D18++0x03 line.long 0x0 "GICD_IGRPMODR6,Interrupt Group Modifier Register 6" bitfld.long 0x00 31. " GMB223 ,Group Modifier Bit 223" "0,1" bitfld.long 0x00 30. " GMB222 ,Group Modifier Bit 222" "0,1" bitfld.long 0x00 29. " GMB221 ,Group Modifier Bit 221" "0,1" textline " " bitfld.long 0x00 28. " GMB220 ,Group Modifier Bit 220" "0,1" bitfld.long 0x00 27. " GMB219 ,Group Modifier Bit 219" "0,1" bitfld.long 0x00 26. " GMB218 ,Group Modifier Bit 218" "0,1" textline " " bitfld.long 0x00 25. " GMB217 ,Group Modifier Bit 217" "0,1" bitfld.long 0x00 24. " GMB216 ,Group Modifier Bit 216" "0,1" bitfld.long 0x00 23. " GMB215 ,Group Modifier Bit 215" "0,1" textline " " bitfld.long 0x00 22. " GMB214 ,Group Modifier Bit 214" "0,1" bitfld.long 0x00 21. " GMB213 ,Group Modifier Bit 213" "0,1" bitfld.long 0x00 20. " GMB212 ,Group Modifier Bit 212" "0,1" textline " " bitfld.long 0x00 19. " GMB211 ,Group Modifier Bit 211" "0,1" bitfld.long 0x00 18. " GMB210 ,Group Modifier Bit 210" "0,1" bitfld.long 0x00 17. " GMB209 ,Group Modifier Bit 209" "0,1" textline " " bitfld.long 0x00 16. " GMB208 ,Group Modifier Bit 208" "0,1" bitfld.long 0x00 15. " GMB207 ,Group Modifier Bit 207" "0,1" bitfld.long 0x00 14. " GMB206 ,Group Modifier Bit 206" "0,1" textline " " bitfld.long 0x00 13. " GMB205 ,Group Modifier Bit 205" "0,1" bitfld.long 0x00 12. " GMB204 ,Group Modifier Bit 204" "0,1" bitfld.long 0x00 11. " GMB203 ,Group Modifier Bit 203" "0,1" textline " " bitfld.long 0x00 10. " GMB202 ,Group Modifier Bit 202" "0,1" bitfld.long 0x00 9. " GMB201 ,Group Modifier Bit 201" "0,1" bitfld.long 0x00 8. " GMB200 ,Group Modifier Bit 200" "0,1" textline " " bitfld.long 0x00 7. " GMB199 ,Group Modifier Bit 199" "0,1" bitfld.long 0x00 6. " GMB198 ,Group Modifier Bit 198" "0,1" bitfld.long 0x00 5. " GMB197 ,Group Modifier Bit 197" "0,1" textline " " bitfld.long 0x00 4. " GMB196 ,Group Modifier Bit 196" "0,1" bitfld.long 0x00 3. " GMB195 ,Group Modifier Bit 195" "0,1" bitfld.long 0x00 2. " GMB194 ,Group Modifier Bit 194" "0,1" textline " " bitfld.long 0x00 1. " GMB193 ,Group Modifier Bit 193" "0,1" bitfld.long 0x00 0. " GMB192 ,Group Modifier Bit 192" "0,1" else hgroup.long 0x0D18++0x03 hide.long 0x0 "GICD_IGRPMODR6,Interrupt Group Modifier Register 6" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D1C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)) group.long 0x0D1C++0x03 line.long 0x0 "GICD_IGRPMODR7,Interrupt Group Modifier Register 7" bitfld.long 0x00 31. " GMB255 ,Group Modifier Bit 255" "0,1" bitfld.long 0x00 30. " GMB254 ,Group Modifier Bit 254" "0,1" bitfld.long 0x00 29. " GMB253 ,Group Modifier Bit 253" "0,1" textline " " bitfld.long 0x00 28. " GMB252 ,Group Modifier Bit 252" "0,1" bitfld.long 0x00 27. " GMB251 ,Group Modifier Bit 251" "0,1" bitfld.long 0x00 26. " GMB250 ,Group Modifier Bit 250" "0,1" textline " " bitfld.long 0x00 25. " GMB249 ,Group Modifier Bit 249" "0,1" bitfld.long 0x00 24. " GMB248 ,Group Modifier Bit 248" "0,1" bitfld.long 0x00 23. " GMB247 ,Group Modifier Bit 247" "0,1" textline " " bitfld.long 0x00 22. " GMB246 ,Group Modifier Bit 246" "0,1" bitfld.long 0x00 21. " GMB245 ,Group Modifier Bit 245" "0,1" bitfld.long 0x00 20. " GMB244 ,Group Modifier Bit 244" "0,1" textline " " bitfld.long 0x00 19. " GMB243 ,Group Modifier Bit 243" "0,1" bitfld.long 0x00 18. " GMB242 ,Group Modifier Bit 242" "0,1" bitfld.long 0x00 17. " GMB241 ,Group Modifier Bit 241" "0,1" textline " " bitfld.long 0x00 16. " GMB240 ,Group Modifier Bit 240" "0,1" bitfld.long 0x00 15. " GMB239 ,Group Modifier Bit 239" "0,1" bitfld.long 0x00 14. " GMB238 ,Group Modifier Bit 238" "0,1" textline " " bitfld.long 0x00 13. " GMB237 ,Group Modifier Bit 237" "0,1" bitfld.long 0x00 12. " GMB236 ,Group Modifier Bit 236" "0,1" bitfld.long 0x00 11. " GMB235 ,Group Modifier Bit 235" "0,1" textline " " bitfld.long 0x00 10. " GMB234 ,Group Modifier Bit 234" "0,1" bitfld.long 0x00 9. " GMB233 ,Group Modifier Bit 233" "0,1" bitfld.long 0x00 8. " GMB232 ,Group Modifier Bit 232" "0,1" textline " " bitfld.long 0x00 7. " GMB231 ,Group Modifier Bit 231" "0,1" bitfld.long 0x00 6. " GMB230 ,Group Modifier Bit 230" "0,1" bitfld.long 0x00 5. " GMB229 ,Group Modifier Bit 229" "0,1" textline " " bitfld.long 0x00 4. " GMB228 ,Group Modifier Bit 228" "0,1" bitfld.long 0x00 3. " GMB227 ,Group Modifier Bit 227" "0,1" bitfld.long 0x00 2. " GMB226 ,Group Modifier Bit 226" "0,1" textline " " bitfld.long 0x00 1. " GMB225 ,Group Modifier Bit 225" "0,1" bitfld.long 0x00 0. " GMB224 ,Group Modifier Bit 224" "0,1" else hgroup.long 0x0D1C++0x03 hide.long 0x0 "GICD_IGRPMODR7,Interrupt Group Modifier Register 7" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D20))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)) group.long 0x0D20++0x03 line.long 0x0 "GICD_IGRPMODR8,Interrupt Group Modifier Register 8" bitfld.long 0x00 31. " GMB287 ,Group Modifier Bit 287" "0,1" bitfld.long 0x00 30. " GMB286 ,Group Modifier Bit 286" "0,1" bitfld.long 0x00 29. " GMB285 ,Group Modifier Bit 285" "0,1" textline " " bitfld.long 0x00 28. " GMB284 ,Group Modifier Bit 284" "0,1" bitfld.long 0x00 27. " GMB283 ,Group Modifier Bit 283" "0,1" bitfld.long 0x00 26. " GMB282 ,Group Modifier Bit 282" "0,1" textline " " bitfld.long 0x00 25. " GMB281 ,Group Modifier Bit 281" "0,1" bitfld.long 0x00 24. " GMB280 ,Group Modifier Bit 280" "0,1" bitfld.long 0x00 23. " GMB279 ,Group Modifier Bit 279" "0,1" textline " " bitfld.long 0x00 22. " GMB278 ,Group Modifier Bit 278" "0,1" bitfld.long 0x00 21. " GMB277 ,Group Modifier Bit 277" "0,1" bitfld.long 0x00 20. " GMB276 ,Group Modifier Bit 276" "0,1" textline " " bitfld.long 0x00 19. " GMB275 ,Group Modifier Bit 275" "0,1" bitfld.long 0x00 18. " GMB274 ,Group Modifier Bit 274" "0,1" bitfld.long 0x00 17. " GMB273 ,Group Modifier Bit 273" "0,1" textline " " bitfld.long 0x00 16. " GMB272 ,Group Modifier Bit 272" "0,1" bitfld.long 0x00 15. " GMB271 ,Group Modifier Bit 271" "0,1" bitfld.long 0x00 14. " GMB270 ,Group Modifier Bit 270" "0,1" textline " " bitfld.long 0x00 13. " GMB269 ,Group Modifier Bit 269" "0,1" bitfld.long 0x00 12. " GMB268 ,Group Modifier Bit 268" "0,1" bitfld.long 0x00 11. " GMB267 ,Group Modifier Bit 267" "0,1" textline " " bitfld.long 0x00 10. " GMB266 ,Group Modifier Bit 266" "0,1" bitfld.long 0x00 9. " GMB265 ,Group Modifier Bit 265" "0,1" bitfld.long 0x00 8. " GMB264 ,Group Modifier Bit 264" "0,1" textline " " bitfld.long 0x00 7. " GMB263 ,Group Modifier Bit 263" "0,1" bitfld.long 0x00 6. " GMB262 ,Group Modifier Bit 262" "0,1" bitfld.long 0x00 5. " GMB261 ,Group Modifier Bit 261" "0,1" textline " " bitfld.long 0x00 4. " GMB260 ,Group Modifier Bit 260" "0,1" bitfld.long 0x00 3. " GMB259 ,Group Modifier Bit 259" "0,1" bitfld.long 0x00 2. " GMB258 ,Group Modifier Bit 258" "0,1" textline " " bitfld.long 0x00 1. " GMB257 ,Group Modifier Bit 257" "0,1" bitfld.long 0x00 0. " GMB256 ,Group Modifier Bit 256" "0,1" else hgroup.long 0x0D20++0x03 hide.long 0x0 "GICD_IGRPMODR8,Interrupt Group Modifier Register 8" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D24))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)) group.long 0x0D24++0x03 line.long 0x0 "GICD_IGRPMODR9,Interrupt Group Modifier Register 9" bitfld.long 0x00 31. " GMB319 ,Group Modifier Bit 319" "0,1" bitfld.long 0x00 30. " GMB318 ,Group Modifier Bit 318" "0,1" bitfld.long 0x00 29. " GMB317 ,Group Modifier Bit 317" "0,1" textline " " bitfld.long 0x00 28. " GMB316 ,Group Modifier Bit 316" "0,1" bitfld.long 0x00 27. " GMB315 ,Group Modifier Bit 315" "0,1" bitfld.long 0x00 26. " GMB314 ,Group Modifier Bit 314" "0,1" textline " " bitfld.long 0x00 25. " GMB313 ,Group Modifier Bit 313" "0,1" bitfld.long 0x00 24. " GMB312 ,Group Modifier Bit 312" "0,1" bitfld.long 0x00 23. " GMB311 ,Group Modifier Bit 311" "0,1" textline " " bitfld.long 0x00 22. " GMB310 ,Group Modifier Bit 310" "0,1" bitfld.long 0x00 21. " GMB309 ,Group Modifier Bit 309" "0,1" bitfld.long 0x00 20. " GMB308 ,Group Modifier Bit 308" "0,1" textline " " bitfld.long 0x00 19. " GMB307 ,Group Modifier Bit 307" "0,1" bitfld.long 0x00 18. " GMB306 ,Group Modifier Bit 306" "0,1" bitfld.long 0x00 17. " GMB305 ,Group Modifier Bit 305" "0,1" textline " " bitfld.long 0x00 16. " GMB304 ,Group Modifier Bit 304" "0,1" bitfld.long 0x00 15. " GMB303 ,Group Modifier Bit 303" "0,1" bitfld.long 0x00 14. " GMB302 ,Group Modifier Bit 302" "0,1" textline " " bitfld.long 0x00 13. " GMB301 ,Group Modifier Bit 301" "0,1" bitfld.long 0x00 12. " GMB300 ,Group Modifier Bit 300" "0,1" bitfld.long 0x00 11. " GMB299 ,Group Modifier Bit 299" "0,1" textline " " bitfld.long 0x00 10. " GMB298 ,Group Modifier Bit 298" "0,1" bitfld.long 0x00 9. " GMB297 ,Group Modifier Bit 297" "0,1" bitfld.long 0x00 8. " GMB296 ,Group Modifier Bit 296" "0,1" textline " " bitfld.long 0x00 7. " GMB295 ,Group Modifier Bit 295" "0,1" bitfld.long 0x00 6. " GMB294 ,Group Modifier Bit 294" "0,1" bitfld.long 0x00 5. " GMB293 ,Group Modifier Bit 293" "0,1" textline " " bitfld.long 0x00 4. " GMB292 ,Group Modifier Bit 292" "0,1" bitfld.long 0x00 3. " GMB291 ,Group Modifier Bit 291" "0,1" bitfld.long 0x00 2. " GMB290 ,Group Modifier Bit 290" "0,1" textline " " bitfld.long 0x00 1. " GMB289 ,Group Modifier Bit 289" "0,1" bitfld.long 0x00 0. " GMB288 ,Group Modifier Bit 288" "0,1" else hgroup.long 0x0D24++0x03 hide.long 0x0 "GICD_IGRPMODR9,Interrupt Group Modifier Register 9" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D28))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)) group.long 0x0D28++0x03 line.long 0x0 "GICD_IGRPMODR10,Interrupt Group Modifier Register 10" bitfld.long 0x00 31. " GMB351 ,Group Modifier Bit 351" "0,1" bitfld.long 0x00 30. " GMB350 ,Group Modifier Bit 350" "0,1" bitfld.long 0x00 29. " GMB349 ,Group Modifier Bit 349" "0,1" textline " " bitfld.long 0x00 28. " GMB348 ,Group Modifier Bit 348" "0,1" bitfld.long 0x00 27. " GMB347 ,Group Modifier Bit 347" "0,1" bitfld.long 0x00 26. " GMB346 ,Group Modifier Bit 346" "0,1" textline " " bitfld.long 0x00 25. " GMB345 ,Group Modifier Bit 345" "0,1" bitfld.long 0x00 24. " GMB344 ,Group Modifier Bit 344" "0,1" bitfld.long 0x00 23. " GMB343 ,Group Modifier Bit 343" "0,1" textline " " bitfld.long 0x00 22. " GMB342 ,Group Modifier Bit 342" "0,1" bitfld.long 0x00 21. " GMB341 ,Group Modifier Bit 341" "0,1" bitfld.long 0x00 20. " GMB340 ,Group Modifier Bit 340" "0,1" textline " " bitfld.long 0x00 19. " GMB339 ,Group Modifier Bit 339" "0,1" bitfld.long 0x00 18. " GMB338 ,Group Modifier Bit 338" "0,1" bitfld.long 0x00 17. " GMB337 ,Group Modifier Bit 337" "0,1" textline " " bitfld.long 0x00 16. " GMB336 ,Group Modifier Bit 336" "0,1" bitfld.long 0x00 15. " GMB335 ,Group Modifier Bit 335" "0,1" bitfld.long 0x00 14. " GMB334 ,Group Modifier Bit 334" "0,1" textline " " bitfld.long 0x00 13. " GMB333 ,Group Modifier Bit 333" "0,1" bitfld.long 0x00 12. " GMB332 ,Group Modifier Bit 332" "0,1" bitfld.long 0x00 11. " GMB331 ,Group Modifier Bit 331" "0,1" textline " " bitfld.long 0x00 10. " GMB330 ,Group Modifier Bit 330" "0,1" bitfld.long 0x00 9. " GMB329 ,Group Modifier Bit 329" "0,1" bitfld.long 0x00 8. " GMB328 ,Group Modifier Bit 328" "0,1" textline " " bitfld.long 0x00 7. " GMB327 ,Group Modifier Bit 327" "0,1" bitfld.long 0x00 6. " GMB326 ,Group Modifier Bit 326" "0,1" bitfld.long 0x00 5. " GMB325 ,Group Modifier Bit 325" "0,1" textline " " bitfld.long 0x00 4. " GMB324 ,Group Modifier Bit 324" "0,1" bitfld.long 0x00 3. " GMB323 ,Group Modifier Bit 323" "0,1" bitfld.long 0x00 2. " GMB322 ,Group Modifier Bit 322" "0,1" textline " " bitfld.long 0x00 1. " GMB321 ,Group Modifier Bit 321" "0,1" bitfld.long 0x00 0. " GMB320 ,Group Modifier Bit 320" "0,1" else hgroup.long 0x0D28++0x03 hide.long 0x0 "GICD_IGRPMODR10,Interrupt Group Modifier Register 10" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D2C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)) group.long 0x0D2C++0x03 line.long 0x0 "GICD_IGRPMODR11,Interrupt Group Modifier Register 11" bitfld.long 0x00 31. " GMB383 ,Group Modifier Bit 383" "0,1" bitfld.long 0x00 30. " GMB382 ,Group Modifier Bit 382" "0,1" bitfld.long 0x00 29. " GMB381 ,Group Modifier Bit 381" "0,1" textline " " bitfld.long 0x00 28. " GMB380 ,Group Modifier Bit 380" "0,1" bitfld.long 0x00 27. " GMB379 ,Group Modifier Bit 379" "0,1" bitfld.long 0x00 26. " GMB378 ,Group Modifier Bit 378" "0,1" textline " " bitfld.long 0x00 25. " GMB377 ,Group Modifier Bit 377" "0,1" bitfld.long 0x00 24. " GMB376 ,Group Modifier Bit 376" "0,1" bitfld.long 0x00 23. " GMB375 ,Group Modifier Bit 375" "0,1" textline " " bitfld.long 0x00 22. " GMB374 ,Group Modifier Bit 374" "0,1" bitfld.long 0x00 21. " GMB373 ,Group Modifier Bit 373" "0,1" bitfld.long 0x00 20. " GMB372 ,Group Modifier Bit 372" "0,1" textline " " bitfld.long 0x00 19. " GMB371 ,Group Modifier Bit 371" "0,1" bitfld.long 0x00 18. " GMB370 ,Group Modifier Bit 370" "0,1" bitfld.long 0x00 17. " GMB369 ,Group Modifier Bit 369" "0,1" textline " " bitfld.long 0x00 16. " GMB368 ,Group Modifier Bit 368" "0,1" bitfld.long 0x00 15. " GMB367 ,Group Modifier Bit 367" "0,1" bitfld.long 0x00 14. " GMB366 ,Group Modifier Bit 366" "0,1" textline " " bitfld.long 0x00 13. " GMB365 ,Group Modifier Bit 365" "0,1" bitfld.long 0x00 12. " GMB364 ,Group Modifier Bit 364" "0,1" bitfld.long 0x00 11. " GMB363 ,Group Modifier Bit 363" "0,1" textline " " bitfld.long 0x00 10. " GMB362 ,Group Modifier Bit 362" "0,1" bitfld.long 0x00 9. " GMB361 ,Group Modifier Bit 361" "0,1" bitfld.long 0x00 8. " GMB360 ,Group Modifier Bit 360" "0,1" textline " " bitfld.long 0x00 7. " GMB359 ,Group Modifier Bit 359" "0,1" bitfld.long 0x00 6. " GMB358 ,Group Modifier Bit 358" "0,1" bitfld.long 0x00 5. " GMB357 ,Group Modifier Bit 357" "0,1" textline " " bitfld.long 0x00 4. " GMB356 ,Group Modifier Bit 356" "0,1" bitfld.long 0x00 3. " GMB355 ,Group Modifier Bit 355" "0,1" bitfld.long 0x00 2. " GMB354 ,Group Modifier Bit 354" "0,1" textline " " bitfld.long 0x00 1. " GMB353 ,Group Modifier Bit 353" "0,1" bitfld.long 0x00 0. " GMB352 ,Group Modifier Bit 352" "0,1" else hgroup.long 0x0D2C++0x03 hide.long 0x0 "GICD_IGRPMODR11,Interrupt Group Modifier Register 11" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D30))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)) group.long 0x0D30++0x03 line.long 0x0 "GICD_IGRPMODR12,Interrupt Group Modifier Register 12" bitfld.long 0x00 31. " GMB415 ,Group Modifier Bit 415" "0,1" bitfld.long 0x00 30. " GMB414 ,Group Modifier Bit 414" "0,1" bitfld.long 0x00 29. " GMB413 ,Group Modifier Bit 413" "0,1" textline " " bitfld.long 0x00 28. " GMB412 ,Group Modifier Bit 412" "0,1" bitfld.long 0x00 27. " GMB411 ,Group Modifier Bit 411" "0,1" bitfld.long 0x00 26. " GMB410 ,Group Modifier Bit 410" "0,1" textline " " bitfld.long 0x00 25. " GMB409 ,Group Modifier Bit 409" "0,1" bitfld.long 0x00 24. " GMB408 ,Group Modifier Bit 408" "0,1" bitfld.long 0x00 23. " GMB407 ,Group Modifier Bit 407" "0,1" textline " " bitfld.long 0x00 22. " GMB406 ,Group Modifier Bit 406" "0,1" bitfld.long 0x00 21. " GMB405 ,Group Modifier Bit 405" "0,1" bitfld.long 0x00 20. " GMB404 ,Group Modifier Bit 404" "0,1" textline " " bitfld.long 0x00 19. " GMB403 ,Group Modifier Bit 403" "0,1" bitfld.long 0x00 18. " GMB402 ,Group Modifier Bit 402" "0,1" bitfld.long 0x00 17. " GMB401 ,Group Modifier Bit 401" "0,1" textline " " bitfld.long 0x00 16. " GMB400 ,Group Modifier Bit 400" "0,1" bitfld.long 0x00 15. " GMB399 ,Group Modifier Bit 399" "0,1" bitfld.long 0x00 14. " GMB398 ,Group Modifier Bit 398" "0,1" textline " " bitfld.long 0x00 13. " GMB397 ,Group Modifier Bit 397" "0,1" bitfld.long 0x00 12. " GMB396 ,Group Modifier Bit 396" "0,1" bitfld.long 0x00 11. " GMB395 ,Group Modifier Bit 395" "0,1" textline " " bitfld.long 0x00 10. " GMB394 ,Group Modifier Bit 394" "0,1" bitfld.long 0x00 9. " GMB393 ,Group Modifier Bit 393" "0,1" bitfld.long 0x00 8. " GMB392 ,Group Modifier Bit 392" "0,1" textline " " bitfld.long 0x00 7. " GMB391 ,Group Modifier Bit 391" "0,1" bitfld.long 0x00 6. " GMB390 ,Group Modifier Bit 390" "0,1" bitfld.long 0x00 5. " GMB389 ,Group Modifier Bit 389" "0,1" textline " " bitfld.long 0x00 4. " GMB388 ,Group Modifier Bit 388" "0,1" bitfld.long 0x00 3. " GMB387 ,Group Modifier Bit 387" "0,1" bitfld.long 0x00 2. " GMB386 ,Group Modifier Bit 386" "0,1" textline " " bitfld.long 0x00 1. " GMB385 ,Group Modifier Bit 385" "0,1" bitfld.long 0x00 0. " GMB384 ,Group Modifier Bit 384" "0,1" else hgroup.long 0x0D30++0x03 hide.long 0x0 "GICD_IGRPMODR12,Interrupt Group Modifier Register 12" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D34))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)) group.long 0x0D34++0x03 line.long 0x0 "GICD_IGRPMODR13,Interrupt Group Modifier Register 13" bitfld.long 0x00 31. " GMB447 ,Group Modifier Bit 447" "0,1" bitfld.long 0x00 30. " GMB446 ,Group Modifier Bit 446" "0,1" bitfld.long 0x00 29. " GMB445 ,Group Modifier Bit 445" "0,1" textline " " bitfld.long 0x00 28. " GMB444 ,Group Modifier Bit 444" "0,1" bitfld.long 0x00 27. " GMB443 ,Group Modifier Bit 443" "0,1" bitfld.long 0x00 26. " GMB442 ,Group Modifier Bit 442" "0,1" textline " " bitfld.long 0x00 25. " GMB441 ,Group Modifier Bit 441" "0,1" bitfld.long 0x00 24. " GMB440 ,Group Modifier Bit 440" "0,1" bitfld.long 0x00 23. " GMB439 ,Group Modifier Bit 439" "0,1" textline " " bitfld.long 0x00 22. " GMB438 ,Group Modifier Bit 438" "0,1" bitfld.long 0x00 21. " GMB437 ,Group Modifier Bit 437" "0,1" bitfld.long 0x00 20. " GMB436 ,Group Modifier Bit 436" "0,1" textline " " bitfld.long 0x00 19. " GMB435 ,Group Modifier Bit 435" "0,1" bitfld.long 0x00 18. " GMB434 ,Group Modifier Bit 434" "0,1" bitfld.long 0x00 17. " GMB433 ,Group Modifier Bit 433" "0,1" textline " " bitfld.long 0x00 16. " GMB432 ,Group Modifier Bit 432" "0,1" bitfld.long 0x00 15. " GMB431 ,Group Modifier Bit 431" "0,1" bitfld.long 0x00 14. " GMB430 ,Group Modifier Bit 430" "0,1" textline " " bitfld.long 0x00 13. " GMB429 ,Group Modifier Bit 429" "0,1" bitfld.long 0x00 12. " GMB428 ,Group Modifier Bit 428" "0,1" bitfld.long 0x00 11. " GMB427 ,Group Modifier Bit 427" "0,1" textline " " bitfld.long 0x00 10. " GMB426 ,Group Modifier Bit 426" "0,1" bitfld.long 0x00 9. " GMB425 ,Group Modifier Bit 425" "0,1" bitfld.long 0x00 8. " GMB424 ,Group Modifier Bit 424" "0,1" textline " " bitfld.long 0x00 7. " GMB423 ,Group Modifier Bit 423" "0,1" bitfld.long 0x00 6. " GMB422 ,Group Modifier Bit 422" "0,1" bitfld.long 0x00 5. " GMB421 ,Group Modifier Bit 421" "0,1" textline " " bitfld.long 0x00 4. " GMB420 ,Group Modifier Bit 420" "0,1" bitfld.long 0x00 3. " GMB419 ,Group Modifier Bit 419" "0,1" bitfld.long 0x00 2. " GMB418 ,Group Modifier Bit 418" "0,1" textline " " bitfld.long 0x00 1. " GMB417 ,Group Modifier Bit 417" "0,1" bitfld.long 0x00 0. " GMB416 ,Group Modifier Bit 416" "0,1" else hgroup.long 0x0D34++0x03 hide.long 0x0 "GICD_IGRPMODR13,Interrupt Group Modifier Register 13" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D38))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)) group.long 0x0D38++0x03 line.long 0x0 "GICD_IGRPMODR14,Interrupt Group Modifier Register 14" bitfld.long 0x00 31. " GMB479 ,Group Modifier Bit 479" "0,1" bitfld.long 0x00 30. " GMB478 ,Group Modifier Bit 478" "0,1" bitfld.long 0x00 29. " GMB477 ,Group Modifier Bit 477" "0,1" textline " " bitfld.long 0x00 28. " GMB476 ,Group Modifier Bit 476" "0,1" bitfld.long 0x00 27. " GMB475 ,Group Modifier Bit 475" "0,1" bitfld.long 0x00 26. " GMB474 ,Group Modifier Bit 474" "0,1" textline " " bitfld.long 0x00 25. " GMB473 ,Group Modifier Bit 473" "0,1" bitfld.long 0x00 24. " GMB472 ,Group Modifier Bit 472" "0,1" bitfld.long 0x00 23. " GMB471 ,Group Modifier Bit 471" "0,1" textline " " bitfld.long 0x00 22. " GMB470 ,Group Modifier Bit 470" "0,1" bitfld.long 0x00 21. " GMB469 ,Group Modifier Bit 469" "0,1" bitfld.long 0x00 20. " GMB468 ,Group Modifier Bit 468" "0,1" textline " " bitfld.long 0x00 19. " GMB467 ,Group Modifier Bit 467" "0,1" bitfld.long 0x00 18. " GMB466 ,Group Modifier Bit 466" "0,1" bitfld.long 0x00 17. " GMB465 ,Group Modifier Bit 465" "0,1" textline " " bitfld.long 0x00 16. " GMB464 ,Group Modifier Bit 464" "0,1" bitfld.long 0x00 15. " GMB463 ,Group Modifier Bit 463" "0,1" bitfld.long 0x00 14. " GMB462 ,Group Modifier Bit 462" "0,1" textline " " bitfld.long 0x00 13. " GMB461 ,Group Modifier Bit 461" "0,1" bitfld.long 0x00 12. " GMB460 ,Group Modifier Bit 460" "0,1" bitfld.long 0x00 11. " GMB459 ,Group Modifier Bit 459" "0,1" textline " " bitfld.long 0x00 10. " GMB458 ,Group Modifier Bit 458" "0,1" bitfld.long 0x00 9. " GMB457 ,Group Modifier Bit 457" "0,1" bitfld.long 0x00 8. " GMB456 ,Group Modifier Bit 456" "0,1" textline " " bitfld.long 0x00 7. " GMB455 ,Group Modifier Bit 455" "0,1" bitfld.long 0x00 6. " GMB454 ,Group Modifier Bit 454" "0,1" bitfld.long 0x00 5. " GMB453 ,Group Modifier Bit 453" "0,1" textline " " bitfld.long 0x00 4. " GMB452 ,Group Modifier Bit 452" "0,1" bitfld.long 0x00 3. " GMB451 ,Group Modifier Bit 451" "0,1" bitfld.long 0x00 2. " GMB450 ,Group Modifier Bit 450" "0,1" textline " " bitfld.long 0x00 1. " GMB449 ,Group Modifier Bit 449" "0,1" bitfld.long 0x00 0. " GMB448 ,Group Modifier Bit 448" "0,1" else hgroup.long 0x0D38++0x03 hide.long 0x0 "GICD_IGRPMODR14,Interrupt Group Modifier Register 14" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D3C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)) group.long 0x0D3C++0x03 line.long 0x0 "GICD_IGRPMODR15,Interrupt Group Modifier Register 15" bitfld.long 0x00 31. " GMB511 ,Group Modifier Bit 511" "0,1" bitfld.long 0x00 30. " GMB510 ,Group Modifier Bit 510" "0,1" bitfld.long 0x00 29. " GMB509 ,Group Modifier Bit 509" "0,1" textline " " bitfld.long 0x00 28. " GMB508 ,Group Modifier Bit 508" "0,1" bitfld.long 0x00 27. " GMB507 ,Group Modifier Bit 507" "0,1" bitfld.long 0x00 26. " GMB506 ,Group Modifier Bit 506" "0,1" textline " " bitfld.long 0x00 25. " GMB505 ,Group Modifier Bit 505" "0,1" bitfld.long 0x00 24. " GMB504 ,Group Modifier Bit 504" "0,1" bitfld.long 0x00 23. " GMB503 ,Group Modifier Bit 503" "0,1" textline " " bitfld.long 0x00 22. " GMB502 ,Group Modifier Bit 502" "0,1" bitfld.long 0x00 21. " GMB501 ,Group Modifier Bit 501" "0,1" bitfld.long 0x00 20. " GMB500 ,Group Modifier Bit 500" "0,1" textline " " bitfld.long 0x00 19. " GMB499 ,Group Modifier Bit 499" "0,1" bitfld.long 0x00 18. " GMB498 ,Group Modifier Bit 498" "0,1" bitfld.long 0x00 17. " GMB497 ,Group Modifier Bit 497" "0,1" textline " " bitfld.long 0x00 16. " GMB496 ,Group Modifier Bit 496" "0,1" bitfld.long 0x00 15. " GMB495 ,Group Modifier Bit 495" "0,1" bitfld.long 0x00 14. " GMB494 ,Group Modifier Bit 494" "0,1" textline " " bitfld.long 0x00 13. " GMB493 ,Group Modifier Bit 493" "0,1" bitfld.long 0x00 12. " GMB492 ,Group Modifier Bit 492" "0,1" bitfld.long 0x00 11. " GMB491 ,Group Modifier Bit 491" "0,1" textline " " bitfld.long 0x00 10. " GMB490 ,Group Modifier Bit 490" "0,1" bitfld.long 0x00 9. " GMB489 ,Group Modifier Bit 489" "0,1" bitfld.long 0x00 8. " GMB488 ,Group Modifier Bit 488" "0,1" textline " " bitfld.long 0x00 7. " GMB487 ,Group Modifier Bit 487" "0,1" bitfld.long 0x00 6. " GMB486 ,Group Modifier Bit 486" "0,1" bitfld.long 0x00 5. " GMB485 ,Group Modifier Bit 485" "0,1" textline " " bitfld.long 0x00 4. " GMB484 ,Group Modifier Bit 484" "0,1" bitfld.long 0x00 3. " GMB483 ,Group Modifier Bit 483" "0,1" bitfld.long 0x00 2. " GMB482 ,Group Modifier Bit 482" "0,1" textline " " bitfld.long 0x00 1. " GMB481 ,Group Modifier Bit 481" "0,1" bitfld.long 0x00 0. " GMB480 ,Group Modifier Bit 480" "0,1" else hgroup.long 0x0D3C++0x03 hide.long 0x0 "GICD_IGRPMODR15,Interrupt Group Modifier Register 15" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D40))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)) group.long 0x0D40++0x03 line.long 0x0 "GICD_IGRPMODR16,Interrupt Group Modifier Register 16" bitfld.long 0x00 31. " GMB543 ,Group Modifier Bit 543" "0,1" bitfld.long 0x00 30. " GMB542 ,Group Modifier Bit 542" "0,1" bitfld.long 0x00 29. " GMB541 ,Group Modifier Bit 541" "0,1" textline " " bitfld.long 0x00 28. " GMB540 ,Group Modifier Bit 540" "0,1" bitfld.long 0x00 27. " GMB539 ,Group Modifier Bit 539" "0,1" bitfld.long 0x00 26. " GMB538 ,Group Modifier Bit 538" "0,1" textline " " bitfld.long 0x00 25. " GMB537 ,Group Modifier Bit 537" "0,1" bitfld.long 0x00 24. " GMB536 ,Group Modifier Bit 536" "0,1" bitfld.long 0x00 23. " GMB535 ,Group Modifier Bit 535" "0,1" textline " " bitfld.long 0x00 22. " GMB534 ,Group Modifier Bit 534" "0,1" bitfld.long 0x00 21. " GMB533 ,Group Modifier Bit 533" "0,1" bitfld.long 0x00 20. " GMB532 ,Group Modifier Bit 532" "0,1" textline " " bitfld.long 0x00 19. " GMB531 ,Group Modifier Bit 531" "0,1" bitfld.long 0x00 18. " GMB530 ,Group Modifier Bit 530" "0,1" bitfld.long 0x00 17. " GMB529 ,Group Modifier Bit 529" "0,1" textline " " bitfld.long 0x00 16. " GMB528 ,Group Modifier Bit 528" "0,1" bitfld.long 0x00 15. " GMB527 ,Group Modifier Bit 527" "0,1" bitfld.long 0x00 14. " GMB526 ,Group Modifier Bit 526" "0,1" textline " " bitfld.long 0x00 13. " GMB525 ,Group Modifier Bit 525" "0,1" bitfld.long 0x00 12. " GMB524 ,Group Modifier Bit 524" "0,1" bitfld.long 0x00 11. " GMB523 ,Group Modifier Bit 523" "0,1" textline " " bitfld.long 0x00 10. " GMB522 ,Group Modifier Bit 522" "0,1" bitfld.long 0x00 9. " GMB521 ,Group Modifier Bit 521" "0,1" bitfld.long 0x00 8. " GMB520 ,Group Modifier Bit 520" "0,1" textline " " bitfld.long 0x00 7. " GMB519 ,Group Modifier Bit 519" "0,1" bitfld.long 0x00 6. " GMB518 ,Group Modifier Bit 518" "0,1" bitfld.long 0x00 5. " GMB517 ,Group Modifier Bit 517" "0,1" textline " " bitfld.long 0x00 4. " GMB516 ,Group Modifier Bit 516" "0,1" bitfld.long 0x00 3. " GMB515 ,Group Modifier Bit 515" "0,1" bitfld.long 0x00 2. " GMB514 ,Group Modifier Bit 514" "0,1" textline " " bitfld.long 0x00 1. " GMB513 ,Group Modifier Bit 513" "0,1" bitfld.long 0x00 0. " GMB512 ,Group Modifier Bit 512" "0,1" else hgroup.long 0x0D40++0x03 hide.long 0x0 "GICD_IGRPMODR16,Interrupt Group Modifier Register 16" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D44))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)) group.long 0x0D44++0x03 line.long 0x0 "GICD_IGRPMODR17,Interrupt Group Modifier Register 17" bitfld.long 0x00 31. " GMB575 ,Group Modifier Bit 575" "0,1" bitfld.long 0x00 30. " GMB574 ,Group Modifier Bit 574" "0,1" bitfld.long 0x00 29. " GMB573 ,Group Modifier Bit 573" "0,1" textline " " bitfld.long 0x00 28. " GMB572 ,Group Modifier Bit 572" "0,1" bitfld.long 0x00 27. " GMB571 ,Group Modifier Bit 571" "0,1" bitfld.long 0x00 26. " GMB570 ,Group Modifier Bit 570" "0,1" textline " " bitfld.long 0x00 25. " GMB569 ,Group Modifier Bit 569" "0,1" bitfld.long 0x00 24. " GMB568 ,Group Modifier Bit 568" "0,1" bitfld.long 0x00 23. " GMB567 ,Group Modifier Bit 567" "0,1" textline " " bitfld.long 0x00 22. " GMB566 ,Group Modifier Bit 566" "0,1" bitfld.long 0x00 21. " GMB565 ,Group Modifier Bit 565" "0,1" bitfld.long 0x00 20. " GMB564 ,Group Modifier Bit 564" "0,1" textline " " bitfld.long 0x00 19. " GMB563 ,Group Modifier Bit 563" "0,1" bitfld.long 0x00 18. " GMB562 ,Group Modifier Bit 562" "0,1" bitfld.long 0x00 17. " GMB561 ,Group Modifier Bit 561" "0,1" textline " " bitfld.long 0x00 16. " GMB560 ,Group Modifier Bit 560" "0,1" bitfld.long 0x00 15. " GMB559 ,Group Modifier Bit 559" "0,1" bitfld.long 0x00 14. " GMB558 ,Group Modifier Bit 558" "0,1" textline " " bitfld.long 0x00 13. " GMB557 ,Group Modifier Bit 557" "0,1" bitfld.long 0x00 12. " GMB556 ,Group Modifier Bit 556" "0,1" bitfld.long 0x00 11. " GMB555 ,Group Modifier Bit 555" "0,1" textline " " bitfld.long 0x00 10. " GMB554 ,Group Modifier Bit 554" "0,1" bitfld.long 0x00 9. " GMB553 ,Group Modifier Bit 553" "0,1" bitfld.long 0x00 8. " GMB552 ,Group Modifier Bit 552" "0,1" textline " " bitfld.long 0x00 7. " GMB551 ,Group Modifier Bit 551" "0,1" bitfld.long 0x00 6. " GMB550 ,Group Modifier Bit 550" "0,1" bitfld.long 0x00 5. " GMB549 ,Group Modifier Bit 549" "0,1" textline " " bitfld.long 0x00 4. " GMB548 ,Group Modifier Bit 548" "0,1" bitfld.long 0x00 3. " GMB547 ,Group Modifier Bit 547" "0,1" bitfld.long 0x00 2. " GMB546 ,Group Modifier Bit 546" "0,1" textline " " bitfld.long 0x00 1. " GMB545 ,Group Modifier Bit 545" "0,1" bitfld.long 0x00 0. " GMB544 ,Group Modifier Bit 544" "0,1" else hgroup.long 0x0D44++0x03 hide.long 0x0 "GICD_IGRPMODR17,Interrupt Group Modifier Register 17" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D48))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)) group.long 0x0D48++0x03 line.long 0x0 "GICD_IGRPMODR18,Interrupt Group Modifier Register 18" bitfld.long 0x00 31. " GMB607 ,Group Modifier Bit 607" "0,1" bitfld.long 0x00 30. " GMB606 ,Group Modifier Bit 606" "0,1" bitfld.long 0x00 29. " GMB605 ,Group Modifier Bit 605" "0,1" textline " " bitfld.long 0x00 28. " GMB604 ,Group Modifier Bit 604" "0,1" bitfld.long 0x00 27. " GMB603 ,Group Modifier Bit 603" "0,1" bitfld.long 0x00 26. " GMB602 ,Group Modifier Bit 602" "0,1" textline " " bitfld.long 0x00 25. " GMB601 ,Group Modifier Bit 601" "0,1" bitfld.long 0x00 24. " GMB600 ,Group Modifier Bit 600" "0,1" bitfld.long 0x00 23. " GMB599 ,Group Modifier Bit 599" "0,1" textline " " bitfld.long 0x00 22. " GMB598 ,Group Modifier Bit 598" "0,1" bitfld.long 0x00 21. " GMB597 ,Group Modifier Bit 597" "0,1" bitfld.long 0x00 20. " GMB596 ,Group Modifier Bit 596" "0,1" textline " " bitfld.long 0x00 19. " GMB595 ,Group Modifier Bit 595" "0,1" bitfld.long 0x00 18. " GMB594 ,Group Modifier Bit 594" "0,1" bitfld.long 0x00 17. " GMB593 ,Group Modifier Bit 593" "0,1" textline " " bitfld.long 0x00 16. " GMB592 ,Group Modifier Bit 592" "0,1" bitfld.long 0x00 15. " GMB591 ,Group Modifier Bit 591" "0,1" bitfld.long 0x00 14. " GMB590 ,Group Modifier Bit 590" "0,1" textline " " bitfld.long 0x00 13. " GMB589 ,Group Modifier Bit 589" "0,1" bitfld.long 0x00 12. " GMB588 ,Group Modifier Bit 588" "0,1" bitfld.long 0x00 11. " GMB587 ,Group Modifier Bit 587" "0,1" textline " " bitfld.long 0x00 10. " GMB586 ,Group Modifier Bit 586" "0,1" bitfld.long 0x00 9. " GMB585 ,Group Modifier Bit 585" "0,1" bitfld.long 0x00 8. " GMB584 ,Group Modifier Bit 584" "0,1" textline " " bitfld.long 0x00 7. " GMB583 ,Group Modifier Bit 583" "0,1" bitfld.long 0x00 6. " GMB582 ,Group Modifier Bit 582" "0,1" bitfld.long 0x00 5. " GMB581 ,Group Modifier Bit 581" "0,1" textline " " bitfld.long 0x00 4. " GMB580 ,Group Modifier Bit 580" "0,1" bitfld.long 0x00 3. " GMB579 ,Group Modifier Bit 579" "0,1" bitfld.long 0x00 2. " GMB578 ,Group Modifier Bit 578" "0,1" textline " " bitfld.long 0x00 1. " GMB577 ,Group Modifier Bit 577" "0,1" bitfld.long 0x00 0. " GMB576 ,Group Modifier Bit 576" "0,1" else hgroup.long 0x0D48++0x03 hide.long 0x0 "GICD_IGRPMODR18,Interrupt Group Modifier Register 18" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D4C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)) group.long 0x0D4C++0x03 line.long 0x0 "GICD_IGRPMODR19,Interrupt Group Modifier Register 19" bitfld.long 0x00 31. " GMB639 ,Group Modifier Bit 639" "0,1" bitfld.long 0x00 30. " GMB638 ,Group Modifier Bit 638" "0,1" bitfld.long 0x00 29. " GMB637 ,Group Modifier Bit 637" "0,1" textline " " bitfld.long 0x00 28. " GMB636 ,Group Modifier Bit 636" "0,1" bitfld.long 0x00 27. " GMB635 ,Group Modifier Bit 635" "0,1" bitfld.long 0x00 26. " GMB634 ,Group Modifier Bit 634" "0,1" textline " " bitfld.long 0x00 25. " GMB633 ,Group Modifier Bit 633" "0,1" bitfld.long 0x00 24. " GMB632 ,Group Modifier Bit 632" "0,1" bitfld.long 0x00 23. " GMB631 ,Group Modifier Bit 631" "0,1" textline " " bitfld.long 0x00 22. " GMB630 ,Group Modifier Bit 630" "0,1" bitfld.long 0x00 21. " GMB629 ,Group Modifier Bit 629" "0,1" bitfld.long 0x00 20. " GMB628 ,Group Modifier Bit 628" "0,1" textline " " bitfld.long 0x00 19. " GMB627 ,Group Modifier Bit 627" "0,1" bitfld.long 0x00 18. " GMB626 ,Group Modifier Bit 626" "0,1" bitfld.long 0x00 17. " GMB625 ,Group Modifier Bit 625" "0,1" textline " " bitfld.long 0x00 16. " GMB624 ,Group Modifier Bit 624" "0,1" bitfld.long 0x00 15. " GMB623 ,Group Modifier Bit 623" "0,1" bitfld.long 0x00 14. " GMB622 ,Group Modifier Bit 622" "0,1" textline " " bitfld.long 0x00 13. " GMB621 ,Group Modifier Bit 621" "0,1" bitfld.long 0x00 12. " GMB620 ,Group Modifier Bit 620" "0,1" bitfld.long 0x00 11. " GMB619 ,Group Modifier Bit 619" "0,1" textline " " bitfld.long 0x00 10. " GMB618 ,Group Modifier Bit 618" "0,1" bitfld.long 0x00 9. " GMB617 ,Group Modifier Bit 617" "0,1" bitfld.long 0x00 8. " GMB616 ,Group Modifier Bit 616" "0,1" textline " " bitfld.long 0x00 7. " GMB615 ,Group Modifier Bit 615" "0,1" bitfld.long 0x00 6. " GMB614 ,Group Modifier Bit 614" "0,1" bitfld.long 0x00 5. " GMB613 ,Group Modifier Bit 613" "0,1" textline " " bitfld.long 0x00 4. " GMB612 ,Group Modifier Bit 612" "0,1" bitfld.long 0x00 3. " GMB611 ,Group Modifier Bit 611" "0,1" bitfld.long 0x00 2. " GMB610 ,Group Modifier Bit 610" "0,1" textline " " bitfld.long 0x00 1. " GMB609 ,Group Modifier Bit 609" "0,1" bitfld.long 0x00 0. " GMB608 ,Group Modifier Bit 608" "0,1" else hgroup.long 0x0D4C++0x03 hide.long 0x0 "GICD_IGRPMODR19,Interrupt Group Modifier Register 19" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D50))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)) group.long 0x0D50++0x03 line.long 0x0 "GICD_IGRPMODR20,Interrupt Group Modifier Register 20" bitfld.long 0x00 31. " GMB671 ,Group Modifier Bit 671" "0,1" bitfld.long 0x00 30. " GMB670 ,Group Modifier Bit 670" "0,1" bitfld.long 0x00 29. " GMB669 ,Group Modifier Bit 669" "0,1" textline " " bitfld.long 0x00 28. " GMB668 ,Group Modifier Bit 668" "0,1" bitfld.long 0x00 27. " GMB667 ,Group Modifier Bit 667" "0,1" bitfld.long 0x00 26. " GMB666 ,Group Modifier Bit 666" "0,1" textline " " bitfld.long 0x00 25. " GMB665 ,Group Modifier Bit 665" "0,1" bitfld.long 0x00 24. " GMB664 ,Group Modifier Bit 664" "0,1" bitfld.long 0x00 23. " GMB663 ,Group Modifier Bit 663" "0,1" textline " " bitfld.long 0x00 22. " GMB662 ,Group Modifier Bit 662" "0,1" bitfld.long 0x00 21. " GMB661 ,Group Modifier Bit 661" "0,1" bitfld.long 0x00 20. " GMB660 ,Group Modifier Bit 660" "0,1" textline " " bitfld.long 0x00 19. " GMB659 ,Group Modifier Bit 659" "0,1" bitfld.long 0x00 18. " GMB658 ,Group Modifier Bit 658" "0,1" bitfld.long 0x00 17. " GMB657 ,Group Modifier Bit 657" "0,1" textline " " bitfld.long 0x00 16. " GMB656 ,Group Modifier Bit 656" "0,1" bitfld.long 0x00 15. " GMB655 ,Group Modifier Bit 655" "0,1" bitfld.long 0x00 14. " GMB654 ,Group Modifier Bit 654" "0,1" textline " " bitfld.long 0x00 13. " GMB653 ,Group Modifier Bit 653" "0,1" bitfld.long 0x00 12. " GMB652 ,Group Modifier Bit 652" "0,1" bitfld.long 0x00 11. " GMB651 ,Group Modifier Bit 651" "0,1" textline " " bitfld.long 0x00 10. " GMB650 ,Group Modifier Bit 650" "0,1" bitfld.long 0x00 9. " GMB649 ,Group Modifier Bit 649" "0,1" bitfld.long 0x00 8. " GMB648 ,Group Modifier Bit 648" "0,1" textline " " bitfld.long 0x00 7. " GMB647 ,Group Modifier Bit 647" "0,1" bitfld.long 0x00 6. " GMB646 ,Group Modifier Bit 646" "0,1" bitfld.long 0x00 5. " GMB645 ,Group Modifier Bit 645" "0,1" textline " " bitfld.long 0x00 4. " GMB644 ,Group Modifier Bit 644" "0,1" bitfld.long 0x00 3. " GMB643 ,Group Modifier Bit 643" "0,1" bitfld.long 0x00 2. " GMB642 ,Group Modifier Bit 642" "0,1" textline " " bitfld.long 0x00 1. " GMB641 ,Group Modifier Bit 641" "0,1" bitfld.long 0x00 0. " GMB640 ,Group Modifier Bit 640" "0,1" else hgroup.long 0x0D50++0x03 hide.long 0x0 "GICD_IGRPMODR20,Interrupt Group Modifier Register 20" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D54))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)) group.long 0x0D54++0x03 line.long 0x0 "GICD_IGRPMODR21,Interrupt Group Modifier Register 21" bitfld.long 0x00 31. " GMB703 ,Group Modifier Bit 703" "0,1" bitfld.long 0x00 30. " GMB702 ,Group Modifier Bit 702" "0,1" bitfld.long 0x00 29. " GMB701 ,Group Modifier Bit 701" "0,1" textline " " bitfld.long 0x00 28. " GMB700 ,Group Modifier Bit 700" "0,1" bitfld.long 0x00 27. " GMB699 ,Group Modifier Bit 699" "0,1" bitfld.long 0x00 26. " GMB698 ,Group Modifier Bit 698" "0,1" textline " " bitfld.long 0x00 25. " GMB697 ,Group Modifier Bit 697" "0,1" bitfld.long 0x00 24. " GMB696 ,Group Modifier Bit 696" "0,1" bitfld.long 0x00 23. " GMB695 ,Group Modifier Bit 695" "0,1" textline " " bitfld.long 0x00 22. " GMB694 ,Group Modifier Bit 694" "0,1" bitfld.long 0x00 21. " GMB693 ,Group Modifier Bit 693" "0,1" bitfld.long 0x00 20. " GMB692 ,Group Modifier Bit 692" "0,1" textline " " bitfld.long 0x00 19. " GMB691 ,Group Modifier Bit 691" "0,1" bitfld.long 0x00 18. " GMB690 ,Group Modifier Bit 690" "0,1" bitfld.long 0x00 17. " GMB689 ,Group Modifier Bit 689" "0,1" textline " " bitfld.long 0x00 16. " GMB688 ,Group Modifier Bit 688" "0,1" bitfld.long 0x00 15. " GMB687 ,Group Modifier Bit 687" "0,1" bitfld.long 0x00 14. " GMB686 ,Group Modifier Bit 686" "0,1" textline " " bitfld.long 0x00 13. " GMB685 ,Group Modifier Bit 685" "0,1" bitfld.long 0x00 12. " GMB684 ,Group Modifier Bit 684" "0,1" bitfld.long 0x00 11. " GMB683 ,Group Modifier Bit 683" "0,1" textline " " bitfld.long 0x00 10. " GMB682 ,Group Modifier Bit 682" "0,1" bitfld.long 0x00 9. " GMB681 ,Group Modifier Bit 681" "0,1" bitfld.long 0x00 8. " GMB680 ,Group Modifier Bit 680" "0,1" textline " " bitfld.long 0x00 7. " GMB679 ,Group Modifier Bit 679" "0,1" bitfld.long 0x00 6. " GMB678 ,Group Modifier Bit 678" "0,1" bitfld.long 0x00 5. " GMB677 ,Group Modifier Bit 677" "0,1" textline " " bitfld.long 0x00 4. " GMB676 ,Group Modifier Bit 676" "0,1" bitfld.long 0x00 3. " GMB675 ,Group Modifier Bit 675" "0,1" bitfld.long 0x00 2. " GMB674 ,Group Modifier Bit 674" "0,1" textline " " bitfld.long 0x00 1. " GMB673 ,Group Modifier Bit 673" "0,1" bitfld.long 0x00 0. " GMB672 ,Group Modifier Bit 672" "0,1" else hgroup.long 0x0D54++0x03 hide.long 0x0 "GICD_IGRPMODR21,Interrupt Group Modifier Register 21" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D58))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)) group.long 0x0D58++0x03 line.long 0x0 "GICD_IGRPMODR22,Interrupt Group Modifier Register 22" bitfld.long 0x00 31. " GMB735 ,Group Modifier Bit 735" "0,1" bitfld.long 0x00 30. " GMB734 ,Group Modifier Bit 734" "0,1" bitfld.long 0x00 29. " GMB733 ,Group Modifier Bit 733" "0,1" textline " " bitfld.long 0x00 28. " GMB732 ,Group Modifier Bit 732" "0,1" bitfld.long 0x00 27. " GMB731 ,Group Modifier Bit 731" "0,1" bitfld.long 0x00 26. " GMB730 ,Group Modifier Bit 730" "0,1" textline " " bitfld.long 0x00 25. " GMB729 ,Group Modifier Bit 729" "0,1" bitfld.long 0x00 24. " GMB728 ,Group Modifier Bit 728" "0,1" bitfld.long 0x00 23. " GMB727 ,Group Modifier Bit 727" "0,1" textline " " bitfld.long 0x00 22. " GMB726 ,Group Modifier Bit 726" "0,1" bitfld.long 0x00 21. " GMB725 ,Group Modifier Bit 725" "0,1" bitfld.long 0x00 20. " GMB724 ,Group Modifier Bit 724" "0,1" textline " " bitfld.long 0x00 19. " GMB723 ,Group Modifier Bit 723" "0,1" bitfld.long 0x00 18. " GMB722 ,Group Modifier Bit 722" "0,1" bitfld.long 0x00 17. " GMB721 ,Group Modifier Bit 721" "0,1" textline " " bitfld.long 0x00 16. " GMB720 ,Group Modifier Bit 720" "0,1" bitfld.long 0x00 15. " GMB719 ,Group Modifier Bit 719" "0,1" bitfld.long 0x00 14. " GMB718 ,Group Modifier Bit 718" "0,1" textline " " bitfld.long 0x00 13. " GMB717 ,Group Modifier Bit 717" "0,1" bitfld.long 0x00 12. " GMB716 ,Group Modifier Bit 716" "0,1" bitfld.long 0x00 11. " GMB715 ,Group Modifier Bit 715" "0,1" textline " " bitfld.long 0x00 10. " GMB714 ,Group Modifier Bit 714" "0,1" bitfld.long 0x00 9. " GMB713 ,Group Modifier Bit 713" "0,1" bitfld.long 0x00 8. " GMB712 ,Group Modifier Bit 712" "0,1" textline " " bitfld.long 0x00 7. " GMB711 ,Group Modifier Bit 711" "0,1" bitfld.long 0x00 6. " GMB710 ,Group Modifier Bit 710" "0,1" bitfld.long 0x00 5. " GMB709 ,Group Modifier Bit 709" "0,1" textline " " bitfld.long 0x00 4. " GMB708 ,Group Modifier Bit 708" "0,1" bitfld.long 0x00 3. " GMB707 ,Group Modifier Bit 707" "0,1" bitfld.long 0x00 2. " GMB706 ,Group Modifier Bit 706" "0,1" textline " " bitfld.long 0x00 1. " GMB705 ,Group Modifier Bit 705" "0,1" bitfld.long 0x00 0. " GMB704 ,Group Modifier Bit 704" "0,1" else hgroup.long 0x0D58++0x03 hide.long 0x0 "GICD_IGRPMODR22,Interrupt Group Modifier Register 22" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D5C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)) group.long 0x0D5C++0x03 line.long 0x0 "GICD_IGRPMODR23,Interrupt Group Modifier Register 23" bitfld.long 0x00 31. " GMB767 ,Group Modifier Bit 767" "0,1" bitfld.long 0x00 30. " GMB766 ,Group Modifier Bit 766" "0,1" bitfld.long 0x00 29. " GMB765 ,Group Modifier Bit 765" "0,1" textline " " bitfld.long 0x00 28. " GMB764 ,Group Modifier Bit 764" "0,1" bitfld.long 0x00 27. " GMB763 ,Group Modifier Bit 763" "0,1" bitfld.long 0x00 26. " GMB762 ,Group Modifier Bit 762" "0,1" textline " " bitfld.long 0x00 25. " GMB761 ,Group Modifier Bit 761" "0,1" bitfld.long 0x00 24. " GMB760 ,Group Modifier Bit 760" "0,1" bitfld.long 0x00 23. " GMB759 ,Group Modifier Bit 759" "0,1" textline " " bitfld.long 0x00 22. " GMB758 ,Group Modifier Bit 758" "0,1" bitfld.long 0x00 21. " GMB757 ,Group Modifier Bit 757" "0,1" bitfld.long 0x00 20. " GMB756 ,Group Modifier Bit 756" "0,1" textline " " bitfld.long 0x00 19. " GMB755 ,Group Modifier Bit 755" "0,1" bitfld.long 0x00 18. " GMB754 ,Group Modifier Bit 754" "0,1" bitfld.long 0x00 17. " GMB753 ,Group Modifier Bit 753" "0,1" textline " " bitfld.long 0x00 16. " GMB752 ,Group Modifier Bit 752" "0,1" bitfld.long 0x00 15. " GMB751 ,Group Modifier Bit 751" "0,1" bitfld.long 0x00 14. " GMB750 ,Group Modifier Bit 750" "0,1" textline " " bitfld.long 0x00 13. " GMB749 ,Group Modifier Bit 749" "0,1" bitfld.long 0x00 12. " GMB748 ,Group Modifier Bit 748" "0,1" bitfld.long 0x00 11. " GMB747 ,Group Modifier Bit 747" "0,1" textline " " bitfld.long 0x00 10. " GMB746 ,Group Modifier Bit 746" "0,1" bitfld.long 0x00 9. " GMB745 ,Group Modifier Bit 745" "0,1" bitfld.long 0x00 8. " GMB744 ,Group Modifier Bit 744" "0,1" textline " " bitfld.long 0x00 7. " GMB743 ,Group Modifier Bit 743" "0,1" bitfld.long 0x00 6. " GMB742 ,Group Modifier Bit 742" "0,1" bitfld.long 0x00 5. " GMB741 ,Group Modifier Bit 741" "0,1" textline " " bitfld.long 0x00 4. " GMB740 ,Group Modifier Bit 740" "0,1" bitfld.long 0x00 3. " GMB739 ,Group Modifier Bit 739" "0,1" bitfld.long 0x00 2. " GMB738 ,Group Modifier Bit 738" "0,1" textline " " bitfld.long 0x00 1. " GMB737 ,Group Modifier Bit 737" "0,1" bitfld.long 0x00 0. " GMB736 ,Group Modifier Bit 736" "0,1" else hgroup.long 0x0D5C++0x03 hide.long 0x0 "GICD_IGRPMODR23,Interrupt Group Modifier Register 23" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D60))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)) group.long 0x0D60++0x03 line.long 0x0 "GICD_IGRPMODR24,Interrupt Group Modifier Register 24" bitfld.long 0x00 31. " GMB799 ,Group Modifier Bit 799" "0,1" bitfld.long 0x00 30. " GMB798 ,Group Modifier Bit 798" "0,1" bitfld.long 0x00 29. " GMB797 ,Group Modifier Bit 797" "0,1" textline " " bitfld.long 0x00 28. " GMB796 ,Group Modifier Bit 796" "0,1" bitfld.long 0x00 27. " GMB795 ,Group Modifier Bit 795" "0,1" bitfld.long 0x00 26. " GMB794 ,Group Modifier Bit 794" "0,1" textline " " bitfld.long 0x00 25. " GMB793 ,Group Modifier Bit 793" "0,1" bitfld.long 0x00 24. " GMB792 ,Group Modifier Bit 792" "0,1" bitfld.long 0x00 23. " GMB791 ,Group Modifier Bit 791" "0,1" textline " " bitfld.long 0x00 22. " GMB790 ,Group Modifier Bit 790" "0,1" bitfld.long 0x00 21. " GMB789 ,Group Modifier Bit 789" "0,1" bitfld.long 0x00 20. " GMB788 ,Group Modifier Bit 788" "0,1" textline " " bitfld.long 0x00 19. " GMB787 ,Group Modifier Bit 787" "0,1" bitfld.long 0x00 18. " GMB786 ,Group Modifier Bit 786" "0,1" bitfld.long 0x00 17. " GMB785 ,Group Modifier Bit 785" "0,1" textline " " bitfld.long 0x00 16. " GMB784 ,Group Modifier Bit 784" "0,1" bitfld.long 0x00 15. " GMB783 ,Group Modifier Bit 783" "0,1" bitfld.long 0x00 14. " GMB782 ,Group Modifier Bit 782" "0,1" textline " " bitfld.long 0x00 13. " GMB781 ,Group Modifier Bit 781" "0,1" bitfld.long 0x00 12. " GMB780 ,Group Modifier Bit 780" "0,1" bitfld.long 0x00 11. " GMB779 ,Group Modifier Bit 779" "0,1" textline " " bitfld.long 0x00 10. " GMB778 ,Group Modifier Bit 778" "0,1" bitfld.long 0x00 9. " GMB777 ,Group Modifier Bit 777" "0,1" bitfld.long 0x00 8. " GMB776 ,Group Modifier Bit 776" "0,1" textline " " bitfld.long 0x00 7. " GMB775 ,Group Modifier Bit 775" "0,1" bitfld.long 0x00 6. " GMB774 ,Group Modifier Bit 774" "0,1" bitfld.long 0x00 5. " GMB773 ,Group Modifier Bit 773" "0,1" textline " " bitfld.long 0x00 4. " GMB772 ,Group Modifier Bit 772" "0,1" bitfld.long 0x00 3. " GMB771 ,Group Modifier Bit 771" "0,1" bitfld.long 0x00 2. " GMB770 ,Group Modifier Bit 770" "0,1" textline " " bitfld.long 0x00 1. " GMB769 ,Group Modifier Bit 769" "0,1" bitfld.long 0x00 0. " GMB768 ,Group Modifier Bit 768" "0,1" else hgroup.long 0x0D60++0x03 hide.long 0x0 "GICD_IGRPMODR24,Interrupt Group Modifier Register 24" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D64))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)) group.long 0x0D64++0x03 line.long 0x0 "GICD_IGRPMODR25,Interrupt Group Modifier Register 25" bitfld.long 0x00 31. " GMB831 ,Group Modifier Bit 831" "0,1" bitfld.long 0x00 30. " GMB830 ,Group Modifier Bit 830" "0,1" bitfld.long 0x00 29. " GMB829 ,Group Modifier Bit 829" "0,1" textline " " bitfld.long 0x00 28. " GMB828 ,Group Modifier Bit 828" "0,1" bitfld.long 0x00 27. " GMB827 ,Group Modifier Bit 827" "0,1" bitfld.long 0x00 26. " GMB826 ,Group Modifier Bit 826" "0,1" textline " " bitfld.long 0x00 25. " GMB825 ,Group Modifier Bit 825" "0,1" bitfld.long 0x00 24. " GMB824 ,Group Modifier Bit 824" "0,1" bitfld.long 0x00 23. " GMB823 ,Group Modifier Bit 823" "0,1" textline " " bitfld.long 0x00 22. " GMB822 ,Group Modifier Bit 822" "0,1" bitfld.long 0x00 21. " GMB821 ,Group Modifier Bit 821" "0,1" bitfld.long 0x00 20. " GMB820 ,Group Modifier Bit 820" "0,1" textline " " bitfld.long 0x00 19. " GMB819 ,Group Modifier Bit 819" "0,1" bitfld.long 0x00 18. " GMB818 ,Group Modifier Bit 818" "0,1" bitfld.long 0x00 17. " GMB817 ,Group Modifier Bit 817" "0,1" textline " " bitfld.long 0x00 16. " GMB816 ,Group Modifier Bit 816" "0,1" bitfld.long 0x00 15. " GMB815 ,Group Modifier Bit 815" "0,1" bitfld.long 0x00 14. " GMB814 ,Group Modifier Bit 814" "0,1" textline " " bitfld.long 0x00 13. " GMB813 ,Group Modifier Bit 813" "0,1" bitfld.long 0x00 12. " GMB812 ,Group Modifier Bit 812" "0,1" bitfld.long 0x00 11. " GMB811 ,Group Modifier Bit 811" "0,1" textline " " bitfld.long 0x00 10. " GMB810 ,Group Modifier Bit 810" "0,1" bitfld.long 0x00 9. " GMB809 ,Group Modifier Bit 809" "0,1" bitfld.long 0x00 8. " GMB808 ,Group Modifier Bit 808" "0,1" textline " " bitfld.long 0x00 7. " GMB807 ,Group Modifier Bit 807" "0,1" bitfld.long 0x00 6. " GMB806 ,Group Modifier Bit 806" "0,1" bitfld.long 0x00 5. " GMB805 ,Group Modifier Bit 805" "0,1" textline " " bitfld.long 0x00 4. " GMB804 ,Group Modifier Bit 804" "0,1" bitfld.long 0x00 3. " GMB803 ,Group Modifier Bit 803" "0,1" bitfld.long 0x00 2. " GMB802 ,Group Modifier Bit 802" "0,1" textline " " bitfld.long 0x00 1. " GMB801 ,Group Modifier Bit 801" "0,1" bitfld.long 0x00 0. " GMB800 ,Group Modifier Bit 800" "0,1" else hgroup.long 0x0D64++0x03 hide.long 0x0 "GICD_IGRPMODR25,Interrupt Group Modifier Register 25" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D68))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01A)) group.long 0x0D68++0x03 line.long 0x0 "GICD_IGRPMODR26,Interrupt Group Modifier Register 26" bitfld.long 0x00 31. " GMB863 ,Group Modifier Bit 863" "0,1" bitfld.long 0x00 30. " GMB862 ,Group Modifier Bit 862" "0,1" bitfld.long 0x00 29. " GMB861 ,Group Modifier Bit 861" "0,1" textline " " bitfld.long 0x00 28. " GMB860 ,Group Modifier Bit 860" "0,1" bitfld.long 0x00 27. " GMB859 ,Group Modifier Bit 859" "0,1" bitfld.long 0x00 26. " GMB858 ,Group Modifier Bit 858" "0,1" textline " " bitfld.long 0x00 25. " GMB857 ,Group Modifier Bit 857" "0,1" bitfld.long 0x00 24. " GMB856 ,Group Modifier Bit 856" "0,1" bitfld.long 0x00 23. " GMB855 ,Group Modifier Bit 855" "0,1" textline " " bitfld.long 0x00 22. " GMB854 ,Group Modifier Bit 854" "0,1" bitfld.long 0x00 21. " GMB853 ,Group Modifier Bit 853" "0,1" bitfld.long 0x00 20. " GMB852 ,Group Modifier Bit 852" "0,1" textline " " bitfld.long 0x00 19. " GMB851 ,Group Modifier Bit 851" "0,1" bitfld.long 0x00 18. " GMB850 ,Group Modifier Bit 850" "0,1" bitfld.long 0x00 17. " GMB849 ,Group Modifier Bit 849" "0,1" textline " " bitfld.long 0x00 16. " GMB848 ,Group Modifier Bit 848" "0,1" bitfld.long 0x00 15. " GMB847 ,Group Modifier Bit 847" "0,1" bitfld.long 0x00 14. " GMB846 ,Group Modifier Bit 846" "0,1" textline " " bitfld.long 0x00 13. " GMB845 ,Group Modifier Bit 845" "0,1" bitfld.long 0x00 12. " GMB844 ,Group Modifier Bit 844" "0,1" bitfld.long 0x00 11. " GMB843 ,Group Modifier Bit 843" "0,1" textline " " bitfld.long 0x00 10. " GMB842 ,Group Modifier Bit 842" "0,1" bitfld.long 0x00 9. " GMB841 ,Group Modifier Bit 841" "0,1" bitfld.long 0x00 8. " GMB840 ,Group Modifier Bit 840" "0,1" textline " " bitfld.long 0x00 7. " GMB839 ,Group Modifier Bit 839" "0,1" bitfld.long 0x00 6. " GMB838 ,Group Modifier Bit 838" "0,1" bitfld.long 0x00 5. " GMB837 ,Group Modifier Bit 837" "0,1" textline " " bitfld.long 0x00 4. " GMB836 ,Group Modifier Bit 836" "0,1" bitfld.long 0x00 3. " GMB835 ,Group Modifier Bit 835" "0,1" bitfld.long 0x00 2. " GMB834 ,Group Modifier Bit 834" "0,1" textline " " bitfld.long 0x00 1. " GMB833 ,Group Modifier Bit 833" "0,1" bitfld.long 0x00 0. " GMB832 ,Group Modifier Bit 832" "0,1" else hgroup.long 0x0D68++0x03 hide.long 0x0 "GICD_IGRPMODR26,Interrupt Group Modifier Register 26" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D6C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)) group.long 0x0D6C++0x03 line.long 0x0 "GICD_IGRPMODR27,Interrupt Group Modifier Register 27" bitfld.long 0x00 31. " GMB895 ,Group Modifier Bit 895" "0,1" bitfld.long 0x00 30. " GMB894 ,Group Modifier Bit 894" "0,1" bitfld.long 0x00 29. " GMB893 ,Group Modifier Bit 893" "0,1" textline " " bitfld.long 0x00 28. " GMB892 ,Group Modifier Bit 892" "0,1" bitfld.long 0x00 27. " GMB891 ,Group Modifier Bit 891" "0,1" bitfld.long 0x00 26. " GMB890 ,Group Modifier Bit 890" "0,1" textline " " bitfld.long 0x00 25. " GMB889 ,Group Modifier Bit 889" "0,1" bitfld.long 0x00 24. " GMB888 ,Group Modifier Bit 888" "0,1" bitfld.long 0x00 23. " GMB887 ,Group Modifier Bit 887" "0,1" textline " " bitfld.long 0x00 22. " GMB886 ,Group Modifier Bit 886" "0,1" bitfld.long 0x00 21. " GMB885 ,Group Modifier Bit 885" "0,1" bitfld.long 0x00 20. " GMB884 ,Group Modifier Bit 884" "0,1" textline " " bitfld.long 0x00 19. " GMB883 ,Group Modifier Bit 883" "0,1" bitfld.long 0x00 18. " GMB882 ,Group Modifier Bit 882" "0,1" bitfld.long 0x00 17. " GMB881 ,Group Modifier Bit 881" "0,1" textline " " bitfld.long 0x00 16. " GMB880 ,Group Modifier Bit 880" "0,1" bitfld.long 0x00 15. " GMB879 ,Group Modifier Bit 879" "0,1" bitfld.long 0x00 14. " GMB878 ,Group Modifier Bit 878" "0,1" textline " " bitfld.long 0x00 13. " GMB877 ,Group Modifier Bit 877" "0,1" bitfld.long 0x00 12. " GMB876 ,Group Modifier Bit 876" "0,1" bitfld.long 0x00 11. " GMB875 ,Group Modifier Bit 875" "0,1" textline " " bitfld.long 0x00 10. " GMB874 ,Group Modifier Bit 874" "0,1" bitfld.long 0x00 9. " GMB873 ,Group Modifier Bit 873" "0,1" bitfld.long 0x00 8. " GMB872 ,Group Modifier Bit 872" "0,1" textline " " bitfld.long 0x00 7. " GMB871 ,Group Modifier Bit 871" "0,1" bitfld.long 0x00 6. " GMB870 ,Group Modifier Bit 870" "0,1" bitfld.long 0x00 5. " GMB869 ,Group Modifier Bit 869" "0,1" textline " " bitfld.long 0x00 4. " GMB868 ,Group Modifier Bit 868" "0,1" bitfld.long 0x00 3. " GMB867 ,Group Modifier Bit 867" "0,1" bitfld.long 0x00 2. " GMB866 ,Group Modifier Bit 866" "0,1" textline " " bitfld.long 0x00 1. " GMB865 ,Group Modifier Bit 865" "0,1" bitfld.long 0x00 0. " GMB864 ,Group Modifier Bit 864" "0,1" else hgroup.long 0x0D6C++0x03 hide.long 0x0 "GICD_IGRPMODR27,Interrupt Group Modifier Register 27" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D70))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)) group.long 0x0D70++0x03 line.long 0x0 "GICD_IGRPMODR28,Interrupt Group Modifier Register 28" bitfld.long 0x00 31. " GMB927 ,Group Modifier Bit 927" "0,1" bitfld.long 0x00 30. " GMB926 ,Group Modifier Bit 926" "0,1" bitfld.long 0x00 29. " GMB925 ,Group Modifier Bit 925" "0,1" textline " " bitfld.long 0x00 28. " GMB924 ,Group Modifier Bit 924" "0,1" bitfld.long 0x00 27. " GMB923 ,Group Modifier Bit 923" "0,1" bitfld.long 0x00 26. " GMB922 ,Group Modifier Bit 922" "0,1" textline " " bitfld.long 0x00 25. " GMB921 ,Group Modifier Bit 921" "0,1" bitfld.long 0x00 24. " GMB920 ,Group Modifier Bit 920" "0,1" bitfld.long 0x00 23. " GMB919 ,Group Modifier Bit 919" "0,1" textline " " bitfld.long 0x00 22. " GMB918 ,Group Modifier Bit 918" "0,1" bitfld.long 0x00 21. " GMB917 ,Group Modifier Bit 917" "0,1" bitfld.long 0x00 20. " GMB916 ,Group Modifier Bit 916" "0,1" textline " " bitfld.long 0x00 19. " GMB915 ,Group Modifier Bit 915" "0,1" bitfld.long 0x00 18. " GMB914 ,Group Modifier Bit 914" "0,1" bitfld.long 0x00 17. " GMB913 ,Group Modifier Bit 913" "0,1" textline " " bitfld.long 0x00 16. " GMB912 ,Group Modifier Bit 912" "0,1" bitfld.long 0x00 15. " GMB911 ,Group Modifier Bit 911" "0,1" bitfld.long 0x00 14. " GMB910 ,Group Modifier Bit 910" "0,1" textline " " bitfld.long 0x00 13. " GMB909 ,Group Modifier Bit 909" "0,1" bitfld.long 0x00 12. " GMB908 ,Group Modifier Bit 908" "0,1" bitfld.long 0x00 11. " GMB907 ,Group Modifier Bit 907" "0,1" textline " " bitfld.long 0x00 10. " GMB906 ,Group Modifier Bit 906" "0,1" bitfld.long 0x00 9. " GMB905 ,Group Modifier Bit 905" "0,1" bitfld.long 0x00 8. " GMB904 ,Group Modifier Bit 904" "0,1" textline " " bitfld.long 0x00 7. " GMB903 ,Group Modifier Bit 903" "0,1" bitfld.long 0x00 6. " GMB902 ,Group Modifier Bit 902" "0,1" bitfld.long 0x00 5. " GMB901 ,Group Modifier Bit 901" "0,1" textline " " bitfld.long 0x00 4. " GMB900 ,Group Modifier Bit 900" "0,1" bitfld.long 0x00 3. " GMB899 ,Group Modifier Bit 899" "0,1" bitfld.long 0x00 2. " GMB898 ,Group Modifier Bit 898" "0,1" textline " " bitfld.long 0x00 1. " GMB897 ,Group Modifier Bit 897" "0,1" bitfld.long 0x00 0. " GMB896 ,Group Modifier Bit 896" "0,1" else hgroup.long 0x0D70++0x03 hide.long 0x0 "GICD_IGRPMODR28,Interrupt Group Modifier Register 28" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D74))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)) group.long 0x0D74++0x03 line.long 0x0 "GICD_IGRPMODR29,Interrupt Group Modifier Register 29" bitfld.long 0x00 31. " GMB959 ,Group Modifier Bit 959" "0,1" bitfld.long 0x00 30. " GMB958 ,Group Modifier Bit 958" "0,1" bitfld.long 0x00 29. " GMB957 ,Group Modifier Bit 957" "0,1" textline " " bitfld.long 0x00 28. " GMB956 ,Group Modifier Bit 956" "0,1" bitfld.long 0x00 27. " GMB955 ,Group Modifier Bit 955" "0,1" bitfld.long 0x00 26. " GMB954 ,Group Modifier Bit 954" "0,1" textline " " bitfld.long 0x00 25. " GMB953 ,Group Modifier Bit 953" "0,1" bitfld.long 0x00 24. " GMB952 ,Group Modifier Bit 952" "0,1" bitfld.long 0x00 23. " GMB951 ,Group Modifier Bit 951" "0,1" textline " " bitfld.long 0x00 22. " GMB950 ,Group Modifier Bit 950" "0,1" bitfld.long 0x00 21. " GMB949 ,Group Modifier Bit 949" "0,1" bitfld.long 0x00 20. " GMB948 ,Group Modifier Bit 948" "0,1" textline " " bitfld.long 0x00 19. " GMB947 ,Group Modifier Bit 947" "0,1" bitfld.long 0x00 18. " GMB946 ,Group Modifier Bit 946" "0,1" bitfld.long 0x00 17. " GMB945 ,Group Modifier Bit 945" "0,1" textline " " bitfld.long 0x00 16. " GMB944 ,Group Modifier Bit 944" "0,1" bitfld.long 0x00 15. " GMB943 ,Group Modifier Bit 943" "0,1" bitfld.long 0x00 14. " GMB942 ,Group Modifier Bit 942" "0,1" textline " " bitfld.long 0x00 13. " GMB941 ,Group Modifier Bit 941" "0,1" bitfld.long 0x00 12. " GMB940 ,Group Modifier Bit 940" "0,1" bitfld.long 0x00 11. " GMB939 ,Group Modifier Bit 939" "0,1" textline " " bitfld.long 0x00 10. " GMB938 ,Group Modifier Bit 938" "0,1" bitfld.long 0x00 9. " GMB937 ,Group Modifier Bit 937" "0,1" bitfld.long 0x00 8. " GMB936 ,Group Modifier Bit 936" "0,1" textline " " bitfld.long 0x00 7. " GMB935 ,Group Modifier Bit 935" "0,1" bitfld.long 0x00 6. " GMB934 ,Group Modifier Bit 934" "0,1" bitfld.long 0x00 5. " GMB933 ,Group Modifier Bit 933" "0,1" textline " " bitfld.long 0x00 4. " GMB932 ,Group Modifier Bit 932" "0,1" bitfld.long 0x00 3. " GMB931 ,Group Modifier Bit 931" "0,1" bitfld.long 0x00 2. " GMB930 ,Group Modifier Bit 930" "0,1" textline " " bitfld.long 0x00 1. " GMB929 ,Group Modifier Bit 929" "0,1" bitfld.long 0x00 0. " GMB928 ,Group Modifier Bit 928" "0,1" else hgroup.long 0x0D74++0x03 hide.long 0x0 "GICD_IGRPMODR29,Interrupt Group Modifier Register 29" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D78))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)) group.long 0x0D78++0x03 line.long 0x0 "GICD_IGRPMODR30,Interrupt Group Modifier Register 30" bitfld.long 0x00 31. " GMB991 ,Group Modifier Bit 991" "0,1" bitfld.long 0x00 30. " GMB990 ,Group Modifier Bit 990" "0,1" bitfld.long 0x00 29. " GMB989 ,Group Modifier Bit 989" "0,1" textline " " bitfld.long 0x00 28. " GMB988 ,Group Modifier Bit 988" "0,1" bitfld.long 0x00 27. " GMB987 ,Group Modifier Bit 987" "0,1" bitfld.long 0x00 26. " GMB986 ,Group Modifier Bit 986" "0,1" textline " " bitfld.long 0x00 25. " GMB985 ,Group Modifier Bit 985" "0,1" bitfld.long 0x00 24. " GMB984 ,Group Modifier Bit 984" "0,1" bitfld.long 0x00 23. " GMB983 ,Group Modifier Bit 983" "0,1" textline " " bitfld.long 0x00 22. " GMB982 ,Group Modifier Bit 982" "0,1" bitfld.long 0x00 21. " GMB981 ,Group Modifier Bit 981" "0,1" bitfld.long 0x00 20. " GMB980 ,Group Modifier Bit 980" "0,1" textline " " bitfld.long 0x00 19. " GMB979 ,Group Modifier Bit 979" "0,1" bitfld.long 0x00 18. " GMB978 ,Group Modifier Bit 978" "0,1" bitfld.long 0x00 17. " GMB977 ,Group Modifier Bit 977" "0,1" textline " " bitfld.long 0x00 16. " GMB976 ,Group Modifier Bit 976" "0,1" bitfld.long 0x00 15. " GMB975 ,Group Modifier Bit 975" "0,1" bitfld.long 0x00 14. " GMB974 ,Group Modifier Bit 974" "0,1" textline " " bitfld.long 0x00 13. " GMB973 ,Group Modifier Bit 973" "0,1" bitfld.long 0x00 12. " GMB972 ,Group Modifier Bit 972" "0,1" bitfld.long 0x00 11. " GMB971 ,Group Modifier Bit 971" "0,1" textline " " bitfld.long 0x00 10. " GMB970 ,Group Modifier Bit 970" "0,1" bitfld.long 0x00 9. " GMB969 ,Group Modifier Bit 969" "0,1" bitfld.long 0x00 8. " GMB968 ,Group Modifier Bit 968" "0,1" textline " " bitfld.long 0x00 7. " GMB967 ,Group Modifier Bit 967" "0,1" bitfld.long 0x00 6. " GMB966 ,Group Modifier Bit 966" "0,1" bitfld.long 0x00 5. " GMB965 ,Group Modifier Bit 965" "0,1" textline " " bitfld.long 0x00 4. " GMB964 ,Group Modifier Bit 964" "0,1" bitfld.long 0x00 3. " GMB963 ,Group Modifier Bit 963" "0,1" bitfld.long 0x00 2. " GMB962 ,Group Modifier Bit 962" "0,1" textline " " bitfld.long 0x00 1. " GMB961 ,Group Modifier Bit 961" "0,1" bitfld.long 0x00 0. " GMB960 ,Group Modifier Bit 960" "0,1" else hgroup.long 0x0D78++0x03 hide.long 0x0 "GICD_IGRPMODR30,Interrupt Group Modifier Register 30" endif tree.end width 14. tree "Non-secure Access Control Registers" hgroup.long 0x0E00++0x03 hide.long 0x00 "GICD_NSACR0,Non-secure Access Control Register 0" hgroup.long 0xE04++0x03 hide.long 0x00 "GICD_NSACR1,Non-secure Access Control Register 1" if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE08))) group.long 0xE08++0x03 line.long 0x00 "GICD_NSACR2,Non-secure Access Control Register 2" bitfld.long 0x00 30.--31. " NS_ACCESS47 ,Controls Non-secure access of the interrupt with ID47 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS46 ,Controls Non-secure access of the interrupt with ID46 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS45 ,Controls Non-secure access of the interrupt with ID45 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS44 ,Controls Non-secure access of the interrupt with ID44 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS43 ,Controls Non-secure access of the interrupt with ID43 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS42 ,Controls Non-secure access of the interrupt with ID42 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS41 ,Controls Non-secure access of the interrupt with ID41 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS40 ,Controls Non-secure access of the interrupt with ID40 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS39 ,Controls Non-secure access of the interrupt with ID39 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS38 ,Controls Non-secure access of the interrupt with ID38 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS37 ,Controls Non-secure access of the interrupt with ID37 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS36 ,Controls Non-secure access of the interrupt with ID36 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS35 ,Controls Non-secure access of the interrupt with ID35 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS34 ,Controls Non-secure access of the interrupt with ID34 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS33 ,Controls Non-secure access of the interrupt with ID33 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS32 ,Controls Non-secure access of the interrupt with ID32 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE08++0x03 hide.long 0x00 "GICD_NSACR2,Non-secure Access Control Register 2" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE0C))) group.long 0xE0C++0x03 line.long 0x00 "GICD_NSACR3,Non-secure Access Control Register 3" bitfld.long 0x00 30.--31. " NS_ACCESS63 ,Controls Non-secure access of the interrupt with ID63 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS62 ,Controls Non-secure access of the interrupt with ID62 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS61 ,Controls Non-secure access of the interrupt with ID61 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS60 ,Controls Non-secure access of the interrupt with ID60 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS59 ,Controls Non-secure access of the interrupt with ID59 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS58 ,Controls Non-secure access of the interrupt with ID58 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS57 ,Controls Non-secure access of the interrupt with ID57 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS56 ,Controls Non-secure access of the interrupt with ID56 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS55 ,Controls Non-secure access of the interrupt with ID55 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS54 ,Controls Non-secure access of the interrupt with ID54 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS53 ,Controls Non-secure access of the interrupt with ID53 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS52 ,Controls Non-secure access of the interrupt with ID52 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS51 ,Controls Non-secure access of the interrupt with ID51 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS50 ,Controls Non-secure access of the interrupt with ID50 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS49 ,Controls Non-secure access of the interrupt with ID49 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS48 ,Controls Non-secure access of the interrupt with ID48 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE0C++0x03 hide.long 0x00 "GICD_NSACR3,Non-secure Access Control Register 3" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE10))) group.long 0xE10++0x03 line.long 0x00 "GICD_NSACR4,Non-secure Access Control Register 4" bitfld.long 0x00 30.--31. " NS_ACCESS79 ,Controls Non-secure access of the interrupt with ID79 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS78 ,Controls Non-secure access of the interrupt with ID78 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS77 ,Controls Non-secure access of the interrupt with ID77 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS76 ,Controls Non-secure access of the interrupt with ID76 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS75 ,Controls Non-secure access of the interrupt with ID75 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS74 ,Controls Non-secure access of the interrupt with ID74 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS73 ,Controls Non-secure access of the interrupt with ID73 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS72 ,Controls Non-secure access of the interrupt with ID72 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS71 ,Controls Non-secure access of the interrupt with ID71 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS70 ,Controls Non-secure access of the interrupt with ID70 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS69 ,Controls Non-secure access of the interrupt with ID69 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS68 ,Controls Non-secure access of the interrupt with ID68 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS67 ,Controls Non-secure access of the interrupt with ID67 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS66 ,Controls Non-secure access of the interrupt with ID66 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS65 ,Controls Non-secure access of the interrupt with ID65 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS64 ,Controls Non-secure access of the interrupt with ID64 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE10++0x03 hide.long 0x00 "GICD_NSACR4,Non-secure Access Control Register 4" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE14))) group.long 0xE14++0x03 line.long 0x00 "GICD_NSACR5,Non-secure Access Control Register 5" bitfld.long 0x00 30.--31. " NS_ACCESS95 ,Controls Non-secure access of the interrupt with ID95 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS94 ,Controls Non-secure access of the interrupt with ID94 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS93 ,Controls Non-secure access of the interrupt with ID93 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS92 ,Controls Non-secure access of the interrupt with ID92 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS91 ,Controls Non-secure access of the interrupt with ID91 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS90 ,Controls Non-secure access of the interrupt with ID90 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS89 ,Controls Non-secure access of the interrupt with ID89 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS88 ,Controls Non-secure access of the interrupt with ID88 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS87 ,Controls Non-secure access of the interrupt with ID87 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS86 ,Controls Non-secure access of the interrupt with ID86 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS85 ,Controls Non-secure access of the interrupt with ID85 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS84 ,Controls Non-secure access of the interrupt with ID84 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS83 ,Controls Non-secure access of the interrupt with ID83 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS82 ,Controls Non-secure access of the interrupt with ID82 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS81 ,Controls Non-secure access of the interrupt with ID81 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS80 ,Controls Non-secure access of the interrupt with ID80 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE14++0x03 hide.long 0x00 "GICD_NSACR5,Non-secure Access Control Register 5" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE18))) group.long 0xE18++0x03 line.long 0x00 "GICD_NSACR6,Non-secure Access Control Register 6" bitfld.long 0x00 30.--31. " NS_ACCESS111 ,Controls Non-secure access of the interrupt with ID111" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS110 ,Controls Non-secure access of the interrupt with ID110" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS109 ,Controls Non-secure access of the interrupt with ID109" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS108 ,Controls Non-secure access of the interrupt with ID108" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS107 ,Controls Non-secure access of the interrupt with ID107" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS106 ,Controls Non-secure access of the interrupt with ID106" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS105 ,Controls Non-secure access of the interrupt with ID105" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS104 ,Controls Non-secure access of the interrupt with ID104" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS103 ,Controls Non-secure access of the interrupt with ID103" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS102 ,Controls Non-secure access of the interrupt with ID102" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS101 ,Controls Non-secure access of the interrupt with ID101" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS100 ,Controls Non-secure access of the interrupt with ID100" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS99 ,Controls Non-secure access of the interrupt with ID99 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS98 ,Controls Non-secure access of the interrupt with ID98 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS97 ,Controls Non-secure access of the interrupt with ID97 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS96 ,Controls Non-secure access of the interrupt with ID96 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE18++0x03 hide.long 0x00 "GICD_NSACR6,Non-secure Access Control Register 6" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE1C))) group.long 0xE1C++0x03 line.long 0x00 "GICD_NSACR7,Non-secure Access Control Register 7" bitfld.long 0x00 30.--31. " NS_ACCESS127 ,Controls Non-secure access of the interrupt with ID127" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS126 ,Controls Non-secure access of the interrupt with ID126" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS125 ,Controls Non-secure access of the interrupt with ID125" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS124 ,Controls Non-secure access of the interrupt with ID124" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS123 ,Controls Non-secure access of the interrupt with ID123" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS122 ,Controls Non-secure access of the interrupt with ID122" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS121 ,Controls Non-secure access of the interrupt with ID121" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS120 ,Controls Non-secure access of the interrupt with ID120" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS119 ,Controls Non-secure access of the interrupt with ID119" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS118 ,Controls Non-secure access of the interrupt with ID118" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS117 ,Controls Non-secure access of the interrupt with ID117" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS116 ,Controls Non-secure access of the interrupt with ID116" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS115 ,Controls Non-secure access of the interrupt with ID115" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS114 ,Controls Non-secure access of the interrupt with ID114" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS113 ,Controls Non-secure access of the interrupt with ID113" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS112 ,Controls Non-secure access of the interrupt with ID112" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE1C++0x03 hide.long 0x00 "GICD_NSACR7,Non-secure Access Control Register 7" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE20))) group.long 0xE20++0x03 line.long 0x00 "GICD_NSACR8,Non-secure Access Control Register 8" bitfld.long 0x00 30.--31. " NS_ACCESS143 ,Controls Non-secure access of the interrupt with ID143" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS142 ,Controls Non-secure access of the interrupt with ID142" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS141 ,Controls Non-secure access of the interrupt with ID141" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS140 ,Controls Non-secure access of the interrupt with ID140" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS139 ,Controls Non-secure access of the interrupt with ID139" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS138 ,Controls Non-secure access of the interrupt with ID138" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS137 ,Controls Non-secure access of the interrupt with ID137" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS136 ,Controls Non-secure access of the interrupt with ID136" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS135 ,Controls Non-secure access of the interrupt with ID135" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS134 ,Controls Non-secure access of the interrupt with ID134" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS133 ,Controls Non-secure access of the interrupt with ID133" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS132 ,Controls Non-secure access of the interrupt with ID132" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS131 ,Controls Non-secure access of the interrupt with ID131" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS130 ,Controls Non-secure access of the interrupt with ID130" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS129 ,Controls Non-secure access of the interrupt with ID129" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS128 ,Controls Non-secure access of the interrupt with ID128" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE20++0x03 hide.long 0x00 "GICD_NSACR8,Non-secure Access Control Register 8" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE24))) group.long 0xE24++0x03 line.long 0x00 "GICD_NSACR9,Non-secure Access Control Register 9" bitfld.long 0x00 30.--31. " NS_ACCESS159 ,Controls Non-secure access of the interrupt with ID159" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS158 ,Controls Non-secure access of the interrupt with ID158" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS157 ,Controls Non-secure access of the interrupt with ID157" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS156 ,Controls Non-secure access of the interrupt with ID156" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS155 ,Controls Non-secure access of the interrupt with ID155" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS154 ,Controls Non-secure access of the interrupt with ID154" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS153 ,Controls Non-secure access of the interrupt with ID153" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS152 ,Controls Non-secure access of the interrupt with ID152" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS151 ,Controls Non-secure access of the interrupt with ID151" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS150 ,Controls Non-secure access of the interrupt with ID150" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS149 ,Controls Non-secure access of the interrupt with ID149" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS148 ,Controls Non-secure access of the interrupt with ID148" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS147 ,Controls Non-secure access of the interrupt with ID147" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS146 ,Controls Non-secure access of the interrupt with ID146" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS145 ,Controls Non-secure access of the interrupt with ID145" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS144 ,Controls Non-secure access of the interrupt with ID144" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE24++0x03 hide.long 0x00 "GICD_NSACR9,Non-secure Access Control Register 9" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE28))) group.long 0xE28++0x03 line.long 0x00 "GICD_NSACR10,Non-secure Access Control Register 10" bitfld.long 0x00 30.--31. " NS_ACCESS175 ,Controls Non-secure access of the interrupt with ID175" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS174 ,Controls Non-secure access of the interrupt with ID174" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS173 ,Controls Non-secure access of the interrupt with ID173" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS172 ,Controls Non-secure access of the interrupt with ID172" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS171 ,Controls Non-secure access of the interrupt with ID171" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS170 ,Controls Non-secure access of the interrupt with ID170" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS169 ,Controls Non-secure access of the interrupt with ID169" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS168 ,Controls Non-secure access of the interrupt with ID168" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS167 ,Controls Non-secure access of the interrupt with ID167" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS166 ,Controls Non-secure access of the interrupt with ID166" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS165 ,Controls Non-secure access of the interrupt with ID165" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS164 ,Controls Non-secure access of the interrupt with ID164" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS163 ,Controls Non-secure access of the interrupt with ID163" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS162 ,Controls Non-secure access of the interrupt with ID162" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS161 ,Controls Non-secure access of the interrupt with ID161" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS160 ,Controls Non-secure access of the interrupt with ID160" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE28++0x03 hide.long 0x00 "GICD_NSACR10,Non-secure Access Control Register 10" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE2C))) group.long 0xE2C++0x03 line.long 0x00 "GICD_NSACR11,Non-secure Access Control Register 11" bitfld.long 0x00 30.--31. " NS_ACCESS191 ,Controls Non-secure access of the interrupt with ID191" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS190 ,Controls Non-secure access of the interrupt with ID190" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS189 ,Controls Non-secure access of the interrupt with ID189" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS188 ,Controls Non-secure access of the interrupt with ID188" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS187 ,Controls Non-secure access of the interrupt with ID187" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS186 ,Controls Non-secure access of the interrupt with ID186" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS185 ,Controls Non-secure access of the interrupt with ID185" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS184 ,Controls Non-secure access of the interrupt with ID184" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS183 ,Controls Non-secure access of the interrupt with ID183" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS182 ,Controls Non-secure access of the interrupt with ID182" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS181 ,Controls Non-secure access of the interrupt with ID181" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS180 ,Controls Non-secure access of the interrupt with ID180" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS179 ,Controls Non-secure access of the interrupt with ID179" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS178 ,Controls Non-secure access of the interrupt with ID178" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS177 ,Controls Non-secure access of the interrupt with ID177" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS176 ,Controls Non-secure access of the interrupt with ID176" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE2C++0x03 hide.long 0x00 "GICD_NSACR11,Non-secure Access Control Register 11" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE30))) group.long 0xE30++0x03 line.long 0x00 "GICD_NSACR12,Non-secure Access Control Register 12" bitfld.long 0x00 30.--31. " NS_ACCESS207 ,Controls Non-secure access of the interrupt with ID207" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS206 ,Controls Non-secure access of the interrupt with ID206" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS205 ,Controls Non-secure access of the interrupt with ID205" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS204 ,Controls Non-secure access of the interrupt with ID204" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS203 ,Controls Non-secure access of the interrupt with ID203" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS202 ,Controls Non-secure access of the interrupt with ID202" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS201 ,Controls Non-secure access of the interrupt with ID201" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS200 ,Controls Non-secure access of the interrupt with ID200" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS199 ,Controls Non-secure access of the interrupt with ID199" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS198 ,Controls Non-secure access of the interrupt with ID198" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS197 ,Controls Non-secure access of the interrupt with ID197" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS196 ,Controls Non-secure access of the interrupt with ID196" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS195 ,Controls Non-secure access of the interrupt with ID195" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS194 ,Controls Non-secure access of the interrupt with ID194" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS193 ,Controls Non-secure access of the interrupt with ID193" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS192 ,Controls Non-secure access of the interrupt with ID192" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE30++0x03 hide.long 0x00 "GICD_NSACR12,Non-secure Access Control Register 12" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE34))) group.long 0xE34++0x03 line.long 0x00 "GICD_NSACR13,Non-secure Access Control Register 13" bitfld.long 0x00 30.--31. " NS_ACCESS223 ,Controls Non-secure access of the interrupt with ID223" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS222 ,Controls Non-secure access of the interrupt with ID222" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS221 ,Controls Non-secure access of the interrupt with ID221" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS220 ,Controls Non-secure access of the interrupt with ID220" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS219 ,Controls Non-secure access of the interrupt with ID219" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS218 ,Controls Non-secure access of the interrupt with ID218" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS217 ,Controls Non-secure access of the interrupt with ID217" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS216 ,Controls Non-secure access of the interrupt with ID216" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS215 ,Controls Non-secure access of the interrupt with ID215" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS214 ,Controls Non-secure access of the interrupt with ID214" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS213 ,Controls Non-secure access of the interrupt with ID213" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS212 ,Controls Non-secure access of the interrupt with ID212" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS211 ,Controls Non-secure access of the interrupt with ID211" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS210 ,Controls Non-secure access of the interrupt with ID210" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS209 ,Controls Non-secure access of the interrupt with ID209" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS208 ,Controls Non-secure access of the interrupt with ID208" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE34++0x03 hide.long 0x00 "GICD_NSACR13,Non-secure Access Control Register 13" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE38))) group.long 0xE38++0x03 line.long 0x00 "GICD_NSACR14,Non-secure Access Control Register 14" bitfld.long 0x00 30.--31. " NS_ACCESS239 ,Controls Non-secure access of the interrupt with ID239" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS238 ,Controls Non-secure access of the interrupt with ID238" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS237 ,Controls Non-secure access of the interrupt with ID237" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS236 ,Controls Non-secure access of the interrupt with ID236" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS235 ,Controls Non-secure access of the interrupt with ID235" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS234 ,Controls Non-secure access of the interrupt with ID234" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS233 ,Controls Non-secure access of the interrupt with ID233" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS232 ,Controls Non-secure access of the interrupt with ID232" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS231 ,Controls Non-secure access of the interrupt with ID231" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS230 ,Controls Non-secure access of the interrupt with ID230" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS229 ,Controls Non-secure access of the interrupt with ID229" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS228 ,Controls Non-secure access of the interrupt with ID228" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS227 ,Controls Non-secure access of the interrupt with ID227" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS226 ,Controls Non-secure access of the interrupt with ID226" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS225 ,Controls Non-secure access of the interrupt with ID225" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS224 ,Controls Non-secure access of the interrupt with ID224" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE38++0x03 hide.long 0x00 "GICD_NSACR14,Non-secure Access Control Register 14" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE3C))) group.long 0xE3C++0x03 line.long 0x00 "GICD_NSACR15,Non-secure Access Control Register 15" bitfld.long 0x00 30.--31. " NS_ACCESS255 ,Controls Non-secure access of the interrupt with ID255" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS254 ,Controls Non-secure access of the interrupt with ID254" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS253 ,Controls Non-secure access of the interrupt with ID253" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS252 ,Controls Non-secure access of the interrupt with ID252" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS251 ,Controls Non-secure access of the interrupt with ID251" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS250 ,Controls Non-secure access of the interrupt with ID250" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS249 ,Controls Non-secure access of the interrupt with ID249" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS248 ,Controls Non-secure access of the interrupt with ID248" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS247 ,Controls Non-secure access of the interrupt with ID247" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS246 ,Controls Non-secure access of the interrupt with ID246" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS245 ,Controls Non-secure access of the interrupt with ID245" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS244 ,Controls Non-secure access of the interrupt with ID244" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS243 ,Controls Non-secure access of the interrupt with ID243" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS242 ,Controls Non-secure access of the interrupt with ID242" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS241 ,Controls Non-secure access of the interrupt with ID241" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS240 ,Controls Non-secure access of the interrupt with ID240" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE3C++0x03 hide.long 0x00 "GICD_NSACR15,Non-secure Access Control Register 15" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE40))) group.long 0xE40++0x03 line.long 0x00 "GICD_NSACR16,Non-secure Access Control Register 16" bitfld.long 0x00 30.--31. " NS_ACCESS271 ,Controls Non-secure access of the interrupt with ID271" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS270 ,Controls Non-secure access of the interrupt with ID270" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS269 ,Controls Non-secure access of the interrupt with ID269" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS268 ,Controls Non-secure access of the interrupt with ID268" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS267 ,Controls Non-secure access of the interrupt with ID267" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS266 ,Controls Non-secure access of the interrupt with ID266" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS265 ,Controls Non-secure access of the interrupt with ID265" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS264 ,Controls Non-secure access of the interrupt with ID264" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS263 ,Controls Non-secure access of the interrupt with ID263" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS262 ,Controls Non-secure access of the interrupt with ID262" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS261 ,Controls Non-secure access of the interrupt with ID261" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS260 ,Controls Non-secure access of the interrupt with ID260" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS259 ,Controls Non-secure access of the interrupt with ID259" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS258 ,Controls Non-secure access of the interrupt with ID258" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS257 ,Controls Non-secure access of the interrupt with ID257" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS256 ,Controls Non-secure access of the interrupt with ID256" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE40++0x03 hide.long 0x00 "GICD_NSACR16,Non-secure Access Control Register 16" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE44))) group.long 0xE44++0x03 line.long 0x00 "GICD_NSACR17,Non-secure Access Control Register 17" bitfld.long 0x00 30.--31. " NS_ACCESS287 ,Controls Non-secure access of the interrupt with ID287" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS286 ,Controls Non-secure access of the interrupt with ID286" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS285 ,Controls Non-secure access of the interrupt with ID285" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS284 ,Controls Non-secure access of the interrupt with ID284" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS283 ,Controls Non-secure access of the interrupt with ID283" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS282 ,Controls Non-secure access of the interrupt with ID282" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS281 ,Controls Non-secure access of the interrupt with ID281" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS280 ,Controls Non-secure access of the interrupt with ID280" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS279 ,Controls Non-secure access of the interrupt with ID279" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS278 ,Controls Non-secure access of the interrupt with ID278" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS277 ,Controls Non-secure access of the interrupt with ID277" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS276 ,Controls Non-secure access of the interrupt with ID276" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS275 ,Controls Non-secure access of the interrupt with ID275" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS274 ,Controls Non-secure access of the interrupt with ID274" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS273 ,Controls Non-secure access of the interrupt with ID273" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS272 ,Controls Non-secure access of the interrupt with ID272" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE44++0x03 hide.long 0x00 "GICD_NSACR17,Non-secure Access Control Register 17" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE48))) group.long 0xE48++0x03 line.long 0x00 "GICD_NSACR18,Non-secure Access Control Register 18" bitfld.long 0x00 30.--31. " NS_ACCESS303 ,Controls Non-secure access of the interrupt with ID303" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS302 ,Controls Non-secure access of the interrupt with ID302" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS301 ,Controls Non-secure access of the interrupt with ID301" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS300 ,Controls Non-secure access of the interrupt with ID300" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS299 ,Controls Non-secure access of the interrupt with ID299" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS298 ,Controls Non-secure access of the interrupt with ID298" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS297 ,Controls Non-secure access of the interrupt with ID297" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS296 ,Controls Non-secure access of the interrupt with ID296" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS295 ,Controls Non-secure access of the interrupt with ID295" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS294 ,Controls Non-secure access of the interrupt with ID294" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS293 ,Controls Non-secure access of the interrupt with ID293" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS292 ,Controls Non-secure access of the interrupt with ID292" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS291 ,Controls Non-secure access of the interrupt with ID291" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS290 ,Controls Non-secure access of the interrupt with ID290" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS289 ,Controls Non-secure access of the interrupt with ID289" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS288 ,Controls Non-secure access of the interrupt with ID288" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE48++0x03 hide.long 0x00 "GICD_NSACR18,Non-secure Access Control Register 18" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE4C))) group.long 0xE4C++0x03 line.long 0x00 "GICD_NSACR19,Non-secure Access Control Register 19" bitfld.long 0x00 30.--31. " NS_ACCESS319 ,Controls Non-secure access of the interrupt with ID319" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS318 ,Controls Non-secure access of the interrupt with ID318" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS317 ,Controls Non-secure access of the interrupt with ID317" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS316 ,Controls Non-secure access of the interrupt with ID316" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS315 ,Controls Non-secure access of the interrupt with ID315" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS314 ,Controls Non-secure access of the interrupt with ID314" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS313 ,Controls Non-secure access of the interrupt with ID313" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS312 ,Controls Non-secure access of the interrupt with ID312" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS311 ,Controls Non-secure access of the interrupt with ID311" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS310 ,Controls Non-secure access of the interrupt with ID310" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS309 ,Controls Non-secure access of the interrupt with ID309" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS308 ,Controls Non-secure access of the interrupt with ID308" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS307 ,Controls Non-secure access of the interrupt with ID307" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS306 ,Controls Non-secure access of the interrupt with ID306" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS305 ,Controls Non-secure access of the interrupt with ID305" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS304 ,Controls Non-secure access of the interrupt with ID304" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE4C++0x03 hide.long 0x00 "GICD_NSACR19,Non-secure Access Control Register 19" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE50))) group.long 0xE50++0x03 line.long 0x00 "GICD_NSACR20,Non-secure Access Control Register 20" bitfld.long 0x00 30.--31. " NS_ACCESS335 ,Controls Non-secure access of the interrupt with ID335" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS334 ,Controls Non-secure access of the interrupt with ID334" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS333 ,Controls Non-secure access of the interrupt with ID333" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS332 ,Controls Non-secure access of the interrupt with ID332" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS331 ,Controls Non-secure access of the interrupt with ID331" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS330 ,Controls Non-secure access of the interrupt with ID330" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS329 ,Controls Non-secure access of the interrupt with ID329" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS328 ,Controls Non-secure access of the interrupt with ID328" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS327 ,Controls Non-secure access of the interrupt with ID327" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS326 ,Controls Non-secure access of the interrupt with ID326" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS325 ,Controls Non-secure access of the interrupt with ID325" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS324 ,Controls Non-secure access of the interrupt with ID324" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS323 ,Controls Non-secure access of the interrupt with ID323" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS322 ,Controls Non-secure access of the interrupt with ID322" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS321 ,Controls Non-secure access of the interrupt with ID321" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS320 ,Controls Non-secure access of the interrupt with ID320" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE50++0x03 hide.long 0x00 "GICD_NSACR20,Non-secure Access Control Register 20" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE54))) group.long 0xE54++0x03 line.long 0x00 "GICD_NSACR21,Non-secure Access Control Register 21" bitfld.long 0x00 30.--31. " NS_ACCESS351 ,Controls Non-secure access of the interrupt with ID351" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS350 ,Controls Non-secure access of the interrupt with ID350" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS349 ,Controls Non-secure access of the interrupt with ID349" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS348 ,Controls Non-secure access of the interrupt with ID348" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS347 ,Controls Non-secure access of the interrupt with ID347" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS346 ,Controls Non-secure access of the interrupt with ID346" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS345 ,Controls Non-secure access of the interrupt with ID345" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS344 ,Controls Non-secure access of the interrupt with ID344" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS343 ,Controls Non-secure access of the interrupt with ID343" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS342 ,Controls Non-secure access of the interrupt with ID342" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS341 ,Controls Non-secure access of the interrupt with ID341" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS340 ,Controls Non-secure access of the interrupt with ID340" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS339 ,Controls Non-secure access of the interrupt with ID339" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS338 ,Controls Non-secure access of the interrupt with ID338" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS337 ,Controls Non-secure access of the interrupt with ID337" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS336 ,Controls Non-secure access of the interrupt with ID336" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE54++0x03 hide.long 0x00 "GICD_NSACR21,Non-secure Access Control Register 21" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE58))) group.long 0xE58++0x03 line.long 0x00 "GICD_NSACR22,Non-secure Access Control Register 22" bitfld.long 0x00 30.--31. " NS_ACCESS367 ,Controls Non-secure access of the interrupt with ID367" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS366 ,Controls Non-secure access of the interrupt with ID366" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS365 ,Controls Non-secure access of the interrupt with ID365" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS364 ,Controls Non-secure access of the interrupt with ID364" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS363 ,Controls Non-secure access of the interrupt with ID363" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS362 ,Controls Non-secure access of the interrupt with ID362" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS361 ,Controls Non-secure access of the interrupt with ID361" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS360 ,Controls Non-secure access of the interrupt with ID360" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS359 ,Controls Non-secure access of the interrupt with ID359" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS358 ,Controls Non-secure access of the interrupt with ID358" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS357 ,Controls Non-secure access of the interrupt with ID357" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS356 ,Controls Non-secure access of the interrupt with ID356" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS355 ,Controls Non-secure access of the interrupt with ID355" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS354 ,Controls Non-secure access of the interrupt with ID354" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS353 ,Controls Non-secure access of the interrupt with ID353" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS352 ,Controls Non-secure access of the interrupt with ID352" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE58++0x03 hide.long 0x00 "GICD_NSACR22,Non-secure Access Control Register 22" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE5C))) group.long 0xE5C++0x03 line.long 0x00 "GICD_NSACR23,Non-secure Access Control Register 23" bitfld.long 0x00 30.--31. " NS_ACCESS383 ,Controls Non-secure access of the interrupt with ID383" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS382 ,Controls Non-secure access of the interrupt with ID382" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS381 ,Controls Non-secure access of the interrupt with ID381" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS380 ,Controls Non-secure access of the interrupt with ID380" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS379 ,Controls Non-secure access of the interrupt with ID379" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS378 ,Controls Non-secure access of the interrupt with ID378" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS377 ,Controls Non-secure access of the interrupt with ID377" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS376 ,Controls Non-secure access of the interrupt with ID376" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS375 ,Controls Non-secure access of the interrupt with ID375" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS374 ,Controls Non-secure access of the interrupt with ID374" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS373 ,Controls Non-secure access of the interrupt with ID373" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS372 ,Controls Non-secure access of the interrupt with ID372" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS371 ,Controls Non-secure access of the interrupt with ID371" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS370 ,Controls Non-secure access of the interrupt with ID370" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS369 ,Controls Non-secure access of the interrupt with ID369" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS368 ,Controls Non-secure access of the interrupt with ID368" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE5C++0x03 hide.long 0x00 "GICD_NSACR23,Non-secure Access Control Register 23" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE60))) group.long 0xE60++0x03 line.long 0x00 "GICD_NSACR24,Non-secure Access Control Register 24" bitfld.long 0x00 30.--31. " NS_ACCESS399 ,Controls Non-secure access of the interrupt with ID399" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS398 ,Controls Non-secure access of the interrupt with ID398" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS397 ,Controls Non-secure access of the interrupt with ID397" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS396 ,Controls Non-secure access of the interrupt with ID396" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS395 ,Controls Non-secure access of the interrupt with ID395" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS394 ,Controls Non-secure access of the interrupt with ID394" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS393 ,Controls Non-secure access of the interrupt with ID393" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS392 ,Controls Non-secure access of the interrupt with ID392" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS391 ,Controls Non-secure access of the interrupt with ID391" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS390 ,Controls Non-secure access of the interrupt with ID390" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS389 ,Controls Non-secure access of the interrupt with ID389" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS388 ,Controls Non-secure access of the interrupt with ID388" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS387 ,Controls Non-secure access of the interrupt with ID387" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS386 ,Controls Non-secure access of the interrupt with ID386" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS385 ,Controls Non-secure access of the interrupt with ID385" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS384 ,Controls Non-secure access of the interrupt with ID384" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE60++0x03 hide.long 0x00 "GICD_NSACR24,Non-secure Access Control Register 24" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE64))) group.long 0xE64++0x03 line.long 0x00 "GICD_NSACR25,Non-secure Access Control Register 25" bitfld.long 0x00 30.--31. " NS_ACCESS415 ,Controls Non-secure access of the interrupt with ID415" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS414 ,Controls Non-secure access of the interrupt with ID414" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS413 ,Controls Non-secure access of the interrupt with ID413" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS412 ,Controls Non-secure access of the interrupt with ID412" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS411 ,Controls Non-secure access of the interrupt with ID411" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS410 ,Controls Non-secure access of the interrupt with ID410" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS409 ,Controls Non-secure access of the interrupt with ID409" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS408 ,Controls Non-secure access of the interrupt with ID408" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS407 ,Controls Non-secure access of the interrupt with ID407" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS406 ,Controls Non-secure access of the interrupt with ID406" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS405 ,Controls Non-secure access of the interrupt with ID405" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS404 ,Controls Non-secure access of the interrupt with ID404" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS403 ,Controls Non-secure access of the interrupt with ID403" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS402 ,Controls Non-secure access of the interrupt with ID402" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS401 ,Controls Non-secure access of the interrupt with ID401" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS400 ,Controls Non-secure access of the interrupt with ID400" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE64++0x03 hide.long 0x00 "GICD_NSACR25,Non-secure Access Control Register 25" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE68))) group.long 0xE68++0x03 line.long 0x00 "GICD_NSACR26,Non-secure Access Control Register 26" bitfld.long 0x00 30.--31. " NS_ACCESS431 ,Controls Non-secure access of the interrupt with ID431" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS430 ,Controls Non-secure access of the interrupt with ID430" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS429 ,Controls Non-secure access of the interrupt with ID429" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS428 ,Controls Non-secure access of the interrupt with ID428" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS427 ,Controls Non-secure access of the interrupt with ID427" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS426 ,Controls Non-secure access of the interrupt with ID426" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS425 ,Controls Non-secure access of the interrupt with ID425" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS424 ,Controls Non-secure access of the interrupt with ID424" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS423 ,Controls Non-secure access of the interrupt with ID423" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS422 ,Controls Non-secure access of the interrupt with ID422" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS421 ,Controls Non-secure access of the interrupt with ID421" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS420 ,Controls Non-secure access of the interrupt with ID420" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS419 ,Controls Non-secure access of the interrupt with ID419" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS418 ,Controls Non-secure access of the interrupt with ID418" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS417 ,Controls Non-secure access of the interrupt with ID417" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS416 ,Controls Non-secure access of the interrupt with ID416" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE68++0x03 hide.long 0x00 "GICD_NSACR26,Non-secure Access Control Register 26" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE6C))) group.long 0xE6C++0x03 line.long 0x00 "GICD_NSACR27,Non-secure Access Control Register 27" bitfld.long 0x00 30.--31. " NS_ACCESS447 ,Controls Non-secure access of the interrupt with ID447" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS446 ,Controls Non-secure access of the interrupt with ID446" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS445 ,Controls Non-secure access of the interrupt with ID445" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS444 ,Controls Non-secure access of the interrupt with ID444" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS443 ,Controls Non-secure access of the interrupt with ID443" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS442 ,Controls Non-secure access of the interrupt with ID442" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS441 ,Controls Non-secure access of the interrupt with ID441" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS440 ,Controls Non-secure access of the interrupt with ID440" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS439 ,Controls Non-secure access of the interrupt with ID439" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS438 ,Controls Non-secure access of the interrupt with ID438" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS437 ,Controls Non-secure access of the interrupt with ID437" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS436 ,Controls Non-secure access of the interrupt with ID436" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS435 ,Controls Non-secure access of the interrupt with ID435" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS434 ,Controls Non-secure access of the interrupt with ID434" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS433 ,Controls Non-secure access of the interrupt with ID433" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS432 ,Controls Non-secure access of the interrupt with ID432" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE6C++0x03 hide.long 0x00 "GICD_NSACR27,Non-secure Access Control Register 27" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE70))) group.long 0xE70++0x03 line.long 0x00 "GICD_NSACR28,Non-secure Access Control Register 28" bitfld.long 0x00 30.--31. " NS_ACCESS463 ,Controls Non-secure access of the interrupt with ID463" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS462 ,Controls Non-secure access of the interrupt with ID462" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS461 ,Controls Non-secure access of the interrupt with ID461" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS460 ,Controls Non-secure access of the interrupt with ID460" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS459 ,Controls Non-secure access of the interrupt with ID459" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS458 ,Controls Non-secure access of the interrupt with ID458" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS457 ,Controls Non-secure access of the interrupt with ID457" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS456 ,Controls Non-secure access of the interrupt with ID456" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS455 ,Controls Non-secure access of the interrupt with ID455" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS454 ,Controls Non-secure access of the interrupt with ID454" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS453 ,Controls Non-secure access of the interrupt with ID453" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS452 ,Controls Non-secure access of the interrupt with ID452" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS451 ,Controls Non-secure access of the interrupt with ID451" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS450 ,Controls Non-secure access of the interrupt with ID450" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS449 ,Controls Non-secure access of the interrupt with ID449" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS448 ,Controls Non-secure access of the interrupt with ID448" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE70++0x03 hide.long 0x00 "GICD_NSACR28,Non-secure Access Control Register 28" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE74))) group.long 0xE74++0x03 line.long 0x00 "GICD_NSACR29,Non-secure Access Control Register 29" bitfld.long 0x00 30.--31. " NS_ACCESS479 ,Controls Non-secure access of the interrupt with ID479" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS478 ,Controls Non-secure access of the interrupt with ID478" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS477 ,Controls Non-secure access of the interrupt with ID477" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS476 ,Controls Non-secure access of the interrupt with ID476" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS475 ,Controls Non-secure access of the interrupt with ID475" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS474 ,Controls Non-secure access of the interrupt with ID474" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS473 ,Controls Non-secure access of the interrupt with ID473" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS472 ,Controls Non-secure access of the interrupt with ID472" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS471 ,Controls Non-secure access of the interrupt with ID471" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS470 ,Controls Non-secure access of the interrupt with ID470" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS469 ,Controls Non-secure access of the interrupt with ID469" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS468 ,Controls Non-secure access of the interrupt with ID468" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS467 ,Controls Non-secure access of the interrupt with ID467" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS466 ,Controls Non-secure access of the interrupt with ID466" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS465 ,Controls Non-secure access of the interrupt with ID465" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS464 ,Controls Non-secure access of the interrupt with ID464" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE74++0x03 hide.long 0x00 "GICD_NSACR29,Non-secure Access Control Register 29" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE78))) group.long 0xE78++0x03 line.long 0x00 "GICD_NSACR30,Non-secure Access Control Register 30" bitfld.long 0x00 30.--31. " NS_ACCESS495 ,Controls Non-secure access of the interrupt with ID495" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS494 ,Controls Non-secure access of the interrupt with ID494" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS493 ,Controls Non-secure access of the interrupt with ID493" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS492 ,Controls Non-secure access of the interrupt with ID492" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS491 ,Controls Non-secure access of the interrupt with ID491" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS490 ,Controls Non-secure access of the interrupt with ID490" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS489 ,Controls Non-secure access of the interrupt with ID489" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS488 ,Controls Non-secure access of the interrupt with ID488" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS487 ,Controls Non-secure access of the interrupt with ID487" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS486 ,Controls Non-secure access of the interrupt with ID486" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS485 ,Controls Non-secure access of the interrupt with ID485" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS484 ,Controls Non-secure access of the interrupt with ID484" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS483 ,Controls Non-secure access of the interrupt with ID483" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS482 ,Controls Non-secure access of the interrupt with ID482" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS481 ,Controls Non-secure access of the interrupt with ID481" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS480 ,Controls Non-secure access of the interrupt with ID480" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE78++0x03 hide.long 0x00 "GICD_NSACR30,Non-secure Access Control Register 30" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE7C))) group.long 0xE7C++0x03 line.long 0x00 "GICD_NSACR31,Non-secure Access Control Register 31" bitfld.long 0x00 30.--31. " NS_ACCESS511 ,Controls Non-secure access of the interrupt with ID511" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS510 ,Controls Non-secure access of the interrupt with ID510" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS509 ,Controls Non-secure access of the interrupt with ID509" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS508 ,Controls Non-secure access of the interrupt with ID508" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS507 ,Controls Non-secure access of the interrupt with ID507" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS506 ,Controls Non-secure access of the interrupt with ID506" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS505 ,Controls Non-secure access of the interrupt with ID505" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS504 ,Controls Non-secure access of the interrupt with ID504" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS503 ,Controls Non-secure access of the interrupt with ID503" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS502 ,Controls Non-secure access of the interrupt with ID502" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS501 ,Controls Non-secure access of the interrupt with ID501" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS500 ,Controls Non-secure access of the interrupt with ID500" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS499 ,Controls Non-secure access of the interrupt with ID499" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS498 ,Controls Non-secure access of the interrupt with ID498" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS497 ,Controls Non-secure access of the interrupt with ID497" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS496 ,Controls Non-secure access of the interrupt with ID496" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE7C++0x03 hide.long 0x00 "GICD_NSACR31,Non-secure Access Control Register 31" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE80))) group.long 0xE80++0x03 line.long 0x00 "GICD_NSACR32,Non-secure Access Control Register 32" bitfld.long 0x00 30.--31. " NS_ACCESS527 ,Controls Non-secure access of the interrupt with ID527" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS526 ,Controls Non-secure access of the interrupt with ID526" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS525 ,Controls Non-secure access of the interrupt with ID525" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS524 ,Controls Non-secure access of the interrupt with ID524" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS523 ,Controls Non-secure access of the interrupt with ID523" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS522 ,Controls Non-secure access of the interrupt with ID522" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS521 ,Controls Non-secure access of the interrupt with ID521" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS520 ,Controls Non-secure access of the interrupt with ID520" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS519 ,Controls Non-secure access of the interrupt with ID519" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS518 ,Controls Non-secure access of the interrupt with ID518" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS517 ,Controls Non-secure access of the interrupt with ID517" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS516 ,Controls Non-secure access of the interrupt with ID516" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS515 ,Controls Non-secure access of the interrupt with ID515" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS514 ,Controls Non-secure access of the interrupt with ID514" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS513 ,Controls Non-secure access of the interrupt with ID513" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS512 ,Controls Non-secure access of the interrupt with ID512" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE80++0x03 hide.long 0x00 "GICD_NSACR32,Non-secure Access Control Register 32" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE84))) group.long 0xE84++0x03 line.long 0x00 "GICD_NSACR33,Non-secure Access Control Register 33" bitfld.long 0x00 30.--31. " NS_ACCESS543 ,Controls Non-secure access of the interrupt with ID543" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS542 ,Controls Non-secure access of the interrupt with ID542" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS541 ,Controls Non-secure access of the interrupt with ID541" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS540 ,Controls Non-secure access of the interrupt with ID540" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS539 ,Controls Non-secure access of the interrupt with ID539" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS538 ,Controls Non-secure access of the interrupt with ID538" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS537 ,Controls Non-secure access of the interrupt with ID537" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS536 ,Controls Non-secure access of the interrupt with ID536" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS535 ,Controls Non-secure access of the interrupt with ID535" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS534 ,Controls Non-secure access of the interrupt with ID534" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS533 ,Controls Non-secure access of the interrupt with ID533" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS532 ,Controls Non-secure access of the interrupt with ID532" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS531 ,Controls Non-secure access of the interrupt with ID531" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS530 ,Controls Non-secure access of the interrupt with ID530" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS529 ,Controls Non-secure access of the interrupt with ID529" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS528 ,Controls Non-secure access of the interrupt with ID528" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE84++0x03 hide.long 0x00 "GICD_NSACR33,Non-secure Access Control Register 33" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE88))) group.long 0xE88++0x03 line.long 0x00 "GICD_NSACR34,Non-secure Access Control Register 34" bitfld.long 0x00 30.--31. " NS_ACCESS559 ,Controls Non-secure access of the interrupt with ID559" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS558 ,Controls Non-secure access of the interrupt with ID558" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS557 ,Controls Non-secure access of the interrupt with ID557" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS556 ,Controls Non-secure access of the interrupt with ID556" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS555 ,Controls Non-secure access of the interrupt with ID555" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS554 ,Controls Non-secure access of the interrupt with ID554" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS553 ,Controls Non-secure access of the interrupt with ID553" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS552 ,Controls Non-secure access of the interrupt with ID552" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS551 ,Controls Non-secure access of the interrupt with ID551" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS550 ,Controls Non-secure access of the interrupt with ID550" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS549 ,Controls Non-secure access of the interrupt with ID549" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS548 ,Controls Non-secure access of the interrupt with ID548" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS547 ,Controls Non-secure access of the interrupt with ID547" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS546 ,Controls Non-secure access of the interrupt with ID546" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS545 ,Controls Non-secure access of the interrupt with ID545" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS544 ,Controls Non-secure access of the interrupt with ID544" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE88++0x03 hide.long 0x00 "GICD_NSACR34,Non-secure Access Control Register 34" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE8C))) group.long 0xE8C++0x03 line.long 0x00 "GICD_NSACR35,Non-secure Access Control Register 35" bitfld.long 0x00 30.--31. " NS_ACCESS575 ,Controls Non-secure access of the interrupt with ID575" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS574 ,Controls Non-secure access of the interrupt with ID574" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS573 ,Controls Non-secure access of the interrupt with ID573" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS572 ,Controls Non-secure access of the interrupt with ID572" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS571 ,Controls Non-secure access of the interrupt with ID571" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS570 ,Controls Non-secure access of the interrupt with ID570" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS569 ,Controls Non-secure access of the interrupt with ID569" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS568 ,Controls Non-secure access of the interrupt with ID568" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS567 ,Controls Non-secure access of the interrupt with ID567" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS566 ,Controls Non-secure access of the interrupt with ID566" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS565 ,Controls Non-secure access of the interrupt with ID565" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS564 ,Controls Non-secure access of the interrupt with ID564" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS563 ,Controls Non-secure access of the interrupt with ID563" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS562 ,Controls Non-secure access of the interrupt with ID562" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS561 ,Controls Non-secure access of the interrupt with ID561" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS560 ,Controls Non-secure access of the interrupt with ID560" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE8C++0x03 hide.long 0x00 "GICD_NSACR35,Non-secure Access Control Register 35" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE90))) group.long 0xE90++0x03 line.long 0x00 "GICD_NSACR36,Non-secure Access Control Register 36" bitfld.long 0x00 30.--31. " NS_ACCESS591 ,Controls Non-secure access of the interrupt with ID591" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS590 ,Controls Non-secure access of the interrupt with ID590" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS589 ,Controls Non-secure access of the interrupt with ID589" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS588 ,Controls Non-secure access of the interrupt with ID588" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS587 ,Controls Non-secure access of the interrupt with ID587" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS586 ,Controls Non-secure access of the interrupt with ID586" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS585 ,Controls Non-secure access of the interrupt with ID585" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS584 ,Controls Non-secure access of the interrupt with ID584" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS583 ,Controls Non-secure access of the interrupt with ID583" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS582 ,Controls Non-secure access of the interrupt with ID582" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS581 ,Controls Non-secure access of the interrupt with ID581" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS580 ,Controls Non-secure access of the interrupt with ID580" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS579 ,Controls Non-secure access of the interrupt with ID579" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS578 ,Controls Non-secure access of the interrupt with ID578" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS577 ,Controls Non-secure access of the interrupt with ID577" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS576 ,Controls Non-secure access of the interrupt with ID576" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE90++0x03 hide.long 0x00 "GICD_NSACR36,Non-secure Access Control Register 36" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE94))) group.long 0xE94++0x03 line.long 0x00 "GICD_NSACR37,Non-secure Access Control Register 37" bitfld.long 0x00 30.--31. " NS_ACCESS607 ,Controls Non-secure access of the interrupt with ID607" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS606 ,Controls Non-secure access of the interrupt with ID606" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS605 ,Controls Non-secure access of the interrupt with ID605" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS604 ,Controls Non-secure access of the interrupt with ID604" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS603 ,Controls Non-secure access of the interrupt with ID603" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS602 ,Controls Non-secure access of the interrupt with ID602" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS601 ,Controls Non-secure access of the interrupt with ID601" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS600 ,Controls Non-secure access of the interrupt with ID600" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS599 ,Controls Non-secure access of the interrupt with ID599" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS598 ,Controls Non-secure access of the interrupt with ID598" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS597 ,Controls Non-secure access of the interrupt with ID597" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS596 ,Controls Non-secure access of the interrupt with ID596" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS595 ,Controls Non-secure access of the interrupt with ID595" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS594 ,Controls Non-secure access of the interrupt with ID594" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS593 ,Controls Non-secure access of the interrupt with ID593" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS592 ,Controls Non-secure access of the interrupt with ID592" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE94++0x03 hide.long 0x00 "GICD_NSACR37,Non-secure Access Control Register 37" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE98))) group.long 0xE98++0x03 line.long 0x00 "GICD_NSACR38,Non-secure Access Control Register 38" bitfld.long 0x00 30.--31. " NS_ACCESS623 ,Controls Non-secure access of the interrupt with ID623" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS622 ,Controls Non-secure access of the interrupt with ID622" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS621 ,Controls Non-secure access of the interrupt with ID621" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS620 ,Controls Non-secure access of the interrupt with ID620" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS619 ,Controls Non-secure access of the interrupt with ID619" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS618 ,Controls Non-secure access of the interrupt with ID618" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS617 ,Controls Non-secure access of the interrupt with ID617" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS616 ,Controls Non-secure access of the interrupt with ID616" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS615 ,Controls Non-secure access of the interrupt with ID615" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS614 ,Controls Non-secure access of the interrupt with ID614" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS613 ,Controls Non-secure access of the interrupt with ID613" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS612 ,Controls Non-secure access of the interrupt with ID612" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS611 ,Controls Non-secure access of the interrupt with ID611" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS610 ,Controls Non-secure access of the interrupt with ID610" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS609 ,Controls Non-secure access of the interrupt with ID609" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS608 ,Controls Non-secure access of the interrupt with ID608" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE98++0x03 hide.long 0x00 "GICD_NSACR38,Non-secure Access Control Register 38" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE9C))) group.long 0xE9C++0x03 line.long 0x00 "GICD_NSACR39,Non-secure Access Control Register 39" bitfld.long 0x00 30.--31. " NS_ACCESS639 ,Controls Non-secure access of the interrupt with ID639" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS638 ,Controls Non-secure access of the interrupt with ID638" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS637 ,Controls Non-secure access of the interrupt with ID637" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS636 ,Controls Non-secure access of the interrupt with ID636" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS635 ,Controls Non-secure access of the interrupt with ID635" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS634 ,Controls Non-secure access of the interrupt with ID634" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS633 ,Controls Non-secure access of the interrupt with ID633" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS632 ,Controls Non-secure access of the interrupt with ID632" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS631 ,Controls Non-secure access of the interrupt with ID631" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS630 ,Controls Non-secure access of the interrupt with ID630" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS629 ,Controls Non-secure access of the interrupt with ID629" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS628 ,Controls Non-secure access of the interrupt with ID628" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS627 ,Controls Non-secure access of the interrupt with ID627" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS626 ,Controls Non-secure access of the interrupt with ID626" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS625 ,Controls Non-secure access of the interrupt with ID625" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS624 ,Controls Non-secure access of the interrupt with ID624" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE9C++0x03 hide.long 0x00 "GICD_NSACR39,Non-secure Access Control Register 39" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA0))) group.long 0xEA0++0x03 line.long 0x00 "GICD_NSACR40,Non-secure Access Control Register 40" bitfld.long 0x00 30.--31. " NS_ACCESS655 ,Controls Non-secure access of the interrupt with ID655" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS654 ,Controls Non-secure access of the interrupt with ID654" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS653 ,Controls Non-secure access of the interrupt with ID653" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS652 ,Controls Non-secure access of the interrupt with ID652" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS651 ,Controls Non-secure access of the interrupt with ID651" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS650 ,Controls Non-secure access of the interrupt with ID650" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS649 ,Controls Non-secure access of the interrupt with ID649" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS648 ,Controls Non-secure access of the interrupt with ID648" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS647 ,Controls Non-secure access of the interrupt with ID647" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS646 ,Controls Non-secure access of the interrupt with ID646" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS645 ,Controls Non-secure access of the interrupt with ID645" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS644 ,Controls Non-secure access of the interrupt with ID644" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS643 ,Controls Non-secure access of the interrupt with ID643" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS642 ,Controls Non-secure access of the interrupt with ID642" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS641 ,Controls Non-secure access of the interrupt with ID641" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS640 ,Controls Non-secure access of the interrupt with ID640" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEA0++0x03 hide.long 0x00 "GICD_NSACR40,Non-secure Access Control Register 40" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA4))) group.long 0xEA4++0x03 line.long 0x00 "GICD_NSACR41,Non-secure Access Control Register 41" bitfld.long 0x00 30.--31. " NS_ACCESS671 ,Controls Non-secure access of the interrupt with ID671" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS670 ,Controls Non-secure access of the interrupt with ID670" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS669 ,Controls Non-secure access of the interrupt with ID669" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS668 ,Controls Non-secure access of the interrupt with ID668" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS667 ,Controls Non-secure access of the interrupt with ID667" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS666 ,Controls Non-secure access of the interrupt with ID666" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS665 ,Controls Non-secure access of the interrupt with ID665" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS664 ,Controls Non-secure access of the interrupt with ID664" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS663 ,Controls Non-secure access of the interrupt with ID663" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS662 ,Controls Non-secure access of the interrupt with ID662" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS661 ,Controls Non-secure access of the interrupt with ID661" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS660 ,Controls Non-secure access of the interrupt with ID660" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS659 ,Controls Non-secure access of the interrupt with ID659" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS658 ,Controls Non-secure access of the interrupt with ID658" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS657 ,Controls Non-secure access of the interrupt with ID657" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS656 ,Controls Non-secure access of the interrupt with ID656" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEA4++0x03 hide.long 0x00 "GICD_NSACR41,Non-secure Access Control Register 41" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA8))) group.long 0xEA8++0x03 line.long 0x00 "GICD_NSACR42,Non-secure Access Control Register 42" bitfld.long 0x00 30.--31. " NS_ACCESS687 ,Controls Non-secure access of the interrupt with ID687" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS686 ,Controls Non-secure access of the interrupt with ID686" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS685 ,Controls Non-secure access of the interrupt with ID685" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS684 ,Controls Non-secure access of the interrupt with ID684" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS683 ,Controls Non-secure access of the interrupt with ID683" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS682 ,Controls Non-secure access of the interrupt with ID682" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS681 ,Controls Non-secure access of the interrupt with ID681" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS680 ,Controls Non-secure access of the interrupt with ID680" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS679 ,Controls Non-secure access of the interrupt with ID679" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS678 ,Controls Non-secure access of the interrupt with ID678" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS677 ,Controls Non-secure access of the interrupt with ID677" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS676 ,Controls Non-secure access of the interrupt with ID676" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS675 ,Controls Non-secure access of the interrupt with ID675" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS674 ,Controls Non-secure access of the interrupt with ID674" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS673 ,Controls Non-secure access of the interrupt with ID673" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS672 ,Controls Non-secure access of the interrupt with ID672" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEA8++0x03 hide.long 0x00 "GICD_NSACR42,Non-secure Access Control Register 42" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEAC))) group.long 0xEAC++0x03 line.long 0x00 "GICD_NSACR43,Non-secure Access Control Register 43" bitfld.long 0x00 30.--31. " NS_ACCESS703 ,Controls Non-secure access of the interrupt with ID703" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS702 ,Controls Non-secure access of the interrupt with ID702" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS701 ,Controls Non-secure access of the interrupt with ID701" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS700 ,Controls Non-secure access of the interrupt with ID700" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS699 ,Controls Non-secure access of the interrupt with ID699" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS698 ,Controls Non-secure access of the interrupt with ID698" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS697 ,Controls Non-secure access of the interrupt with ID697" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS696 ,Controls Non-secure access of the interrupt with ID696" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS695 ,Controls Non-secure access of the interrupt with ID695" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS694 ,Controls Non-secure access of the interrupt with ID694" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS693 ,Controls Non-secure access of the interrupt with ID693" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS692 ,Controls Non-secure access of the interrupt with ID692" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS691 ,Controls Non-secure access of the interrupt with ID691" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS690 ,Controls Non-secure access of the interrupt with ID690" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS689 ,Controls Non-secure access of the interrupt with ID689" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS688 ,Controls Non-secure access of the interrupt with ID688" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEAC++0x03 hide.long 0x00 "GICD_NSACR43,Non-secure Access Control Register 43" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB0))) group.long 0xEB0++0x03 line.long 0x00 "GICD_NSACR44,Non-secure Access Control Register 44" bitfld.long 0x00 30.--31. " NS_ACCESS719 ,Controls Non-secure access of the interrupt with ID719" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS718 ,Controls Non-secure access of the interrupt with ID718" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS717 ,Controls Non-secure access of the interrupt with ID717" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS716 ,Controls Non-secure access of the interrupt with ID716" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS715 ,Controls Non-secure access of the interrupt with ID715" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS714 ,Controls Non-secure access of the interrupt with ID714" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS713 ,Controls Non-secure access of the interrupt with ID713" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS712 ,Controls Non-secure access of the interrupt with ID712" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS711 ,Controls Non-secure access of the interrupt with ID711" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS710 ,Controls Non-secure access of the interrupt with ID710" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS709 ,Controls Non-secure access of the interrupt with ID709" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS708 ,Controls Non-secure access of the interrupt with ID708" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS707 ,Controls Non-secure access of the interrupt with ID707" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS706 ,Controls Non-secure access of the interrupt with ID706" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS705 ,Controls Non-secure access of the interrupt with ID705" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS704 ,Controls Non-secure access of the interrupt with ID704" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEB0++0x03 hide.long 0x00 "GICD_NSACR44,Non-secure Access Control Register 44" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB4))) group.long 0xEB4++0x03 line.long 0x00 "GICD_NSACR45,Non-secure Access Control Register 45" bitfld.long 0x00 30.--31. " NS_ACCESS735 ,Controls Non-secure access of the interrupt with ID735" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS734 ,Controls Non-secure access of the interrupt with ID734" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS733 ,Controls Non-secure access of the interrupt with ID733" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS732 ,Controls Non-secure access of the interrupt with ID732" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS731 ,Controls Non-secure access of the interrupt with ID731" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS730 ,Controls Non-secure access of the interrupt with ID730" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS729 ,Controls Non-secure access of the interrupt with ID729" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS728 ,Controls Non-secure access of the interrupt with ID728" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS727 ,Controls Non-secure access of the interrupt with ID727" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS726 ,Controls Non-secure access of the interrupt with ID726" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS725 ,Controls Non-secure access of the interrupt with ID725" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS724 ,Controls Non-secure access of the interrupt with ID724" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS723 ,Controls Non-secure access of the interrupt with ID723" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS722 ,Controls Non-secure access of the interrupt with ID722" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS721 ,Controls Non-secure access of the interrupt with ID721" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS720 ,Controls Non-secure access of the interrupt with ID720" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEB4++0x03 hide.long 0x00 "GICD_NSACR45,Non-secure Access Control Register 45" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB8))) group.long 0xEB8++0x03 line.long 0x00 "GICD_NSACR46,Non-secure Access Control Register 46" bitfld.long 0x00 30.--31. " NS_ACCESS751 ,Controls Non-secure access of the interrupt with ID751" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS750 ,Controls Non-secure access of the interrupt with ID750" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS749 ,Controls Non-secure access of the interrupt with ID749" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS748 ,Controls Non-secure access of the interrupt with ID748" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS747 ,Controls Non-secure access of the interrupt with ID747" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS746 ,Controls Non-secure access of the interrupt with ID746" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS745 ,Controls Non-secure access of the interrupt with ID745" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS744 ,Controls Non-secure access of the interrupt with ID744" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS743 ,Controls Non-secure access of the interrupt with ID743" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS742 ,Controls Non-secure access of the interrupt with ID742" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS741 ,Controls Non-secure access of the interrupt with ID741" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS740 ,Controls Non-secure access of the interrupt with ID740" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS739 ,Controls Non-secure access of the interrupt with ID739" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS738 ,Controls Non-secure access of the interrupt with ID738" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS737 ,Controls Non-secure access of the interrupt with ID737" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS736 ,Controls Non-secure access of the interrupt with ID736" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEB8++0x03 hide.long 0x00 "GICD_NSACR46,Non-secure Access Control Register 46" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEBC))) group.long 0xEBC++0x03 line.long 0x00 "GICD_NSACR47,Non-secure Access Control Register 47" bitfld.long 0x00 30.--31. " NS_ACCESS767 ,Controls Non-secure access of the interrupt with ID767" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS766 ,Controls Non-secure access of the interrupt with ID766" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS765 ,Controls Non-secure access of the interrupt with ID765" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS764 ,Controls Non-secure access of the interrupt with ID764" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS763 ,Controls Non-secure access of the interrupt with ID763" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS762 ,Controls Non-secure access of the interrupt with ID762" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS761 ,Controls Non-secure access of the interrupt with ID761" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS760 ,Controls Non-secure access of the interrupt with ID760" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS759 ,Controls Non-secure access of the interrupt with ID759" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS758 ,Controls Non-secure access of the interrupt with ID758" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS757 ,Controls Non-secure access of the interrupt with ID757" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS756 ,Controls Non-secure access of the interrupt with ID756" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS755 ,Controls Non-secure access of the interrupt with ID755" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS754 ,Controls Non-secure access of the interrupt with ID754" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS753 ,Controls Non-secure access of the interrupt with ID753" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS752 ,Controls Non-secure access of the interrupt with ID752" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEBC++0x03 hide.long 0x00 "GICD_NSACR47,Non-secure Access Control Register 47" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC0))) group.long 0xEC0++0x03 line.long 0x00 "GICD_NSACR48,Non-secure Access Control Register 48" bitfld.long 0x00 30.--31. " NS_ACCESS783 ,Controls Non-secure access of the interrupt with ID783" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS782 ,Controls Non-secure access of the interrupt with ID782" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS781 ,Controls Non-secure access of the interrupt with ID781" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS780 ,Controls Non-secure access of the interrupt with ID780" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS779 ,Controls Non-secure access of the interrupt with ID779" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS778 ,Controls Non-secure access of the interrupt with ID778" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS777 ,Controls Non-secure access of the interrupt with ID777" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS776 ,Controls Non-secure access of the interrupt with ID776" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS775 ,Controls Non-secure access of the interrupt with ID775" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS774 ,Controls Non-secure access of the interrupt with ID774" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS773 ,Controls Non-secure access of the interrupt with ID773" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS772 ,Controls Non-secure access of the interrupt with ID772" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS771 ,Controls Non-secure access of the interrupt with ID771" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS770 ,Controls Non-secure access of the interrupt with ID770" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS769 ,Controls Non-secure access of the interrupt with ID769" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS768 ,Controls Non-secure access of the interrupt with ID768" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEC0++0x03 hide.long 0x00 "GICD_NSACR48,Non-secure Access Control Register 48" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC4))) group.long 0xEC4++0x03 line.long 0x00 "GICD_NSACR49,Non-secure Access Control Register 49" bitfld.long 0x00 30.--31. " NS_ACCESS799 ,Controls Non-secure access of the interrupt with ID799" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS798 ,Controls Non-secure access of the interrupt with ID798" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS797 ,Controls Non-secure access of the interrupt with ID797" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS796 ,Controls Non-secure access of the interrupt with ID796" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS795 ,Controls Non-secure access of the interrupt with ID795" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS794 ,Controls Non-secure access of the interrupt with ID794" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS793 ,Controls Non-secure access of the interrupt with ID793" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS792 ,Controls Non-secure access of the interrupt with ID792" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS791 ,Controls Non-secure access of the interrupt with ID791" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS790 ,Controls Non-secure access of the interrupt with ID790" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS789 ,Controls Non-secure access of the interrupt with ID789" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS788 ,Controls Non-secure access of the interrupt with ID788" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS787 ,Controls Non-secure access of the interrupt with ID787" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS786 ,Controls Non-secure access of the interrupt with ID786" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS785 ,Controls Non-secure access of the interrupt with ID785" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS784 ,Controls Non-secure access of the interrupt with ID784" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEC4++0x03 hide.long 0x00 "GICD_NSACR49,Non-secure Access Control Register 49" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC8))) group.long 0xEC8++0x03 line.long 0x00 "GICD_NSACR50,Non-secure Access Control Register 50" bitfld.long 0x00 30.--31. " NS_ACCESS815 ,Controls Non-secure access of the interrupt with ID815" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS814 ,Controls Non-secure access of the interrupt with ID814" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS813 ,Controls Non-secure access of the interrupt with ID813" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS812 ,Controls Non-secure access of the interrupt with ID812" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS811 ,Controls Non-secure access of the interrupt with ID811" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS810 ,Controls Non-secure access of the interrupt with ID810" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS809 ,Controls Non-secure access of the interrupt with ID809" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS808 ,Controls Non-secure access of the interrupt with ID808" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS807 ,Controls Non-secure access of the interrupt with ID807" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS806 ,Controls Non-secure access of the interrupt with ID806" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS805 ,Controls Non-secure access of the interrupt with ID805" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS804 ,Controls Non-secure access of the interrupt with ID804" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS803 ,Controls Non-secure access of the interrupt with ID803" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS802 ,Controls Non-secure access of the interrupt with ID802" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS801 ,Controls Non-secure access of the interrupt with ID801" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS800 ,Controls Non-secure access of the interrupt with ID800" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEC8++0x03 hide.long 0x00 "GICD_NSACR50,Non-secure Access Control Register 50" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xECC))) group.long 0xECC++0x03 line.long 0x00 "GICD_NSACR51,Non-secure Access Control Register 51" bitfld.long 0x00 30.--31. " NS_ACCESS831 ,Controls Non-secure access of the interrupt with ID831" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS830 ,Controls Non-secure access of the interrupt with ID830" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS829 ,Controls Non-secure access of the interrupt with ID829" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS828 ,Controls Non-secure access of the interrupt with ID828" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS827 ,Controls Non-secure access of the interrupt with ID827" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS826 ,Controls Non-secure access of the interrupt with ID826" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS825 ,Controls Non-secure access of the interrupt with ID825" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS824 ,Controls Non-secure access of the interrupt with ID824" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS823 ,Controls Non-secure access of the interrupt with ID823" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS822 ,Controls Non-secure access of the interrupt with ID822" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS821 ,Controls Non-secure access of the interrupt with ID821" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS820 ,Controls Non-secure access of the interrupt with ID820" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS819 ,Controls Non-secure access of the interrupt with ID819" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS818 ,Controls Non-secure access of the interrupt with ID818" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS817 ,Controls Non-secure access of the interrupt with ID817" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS816 ,Controls Non-secure access of the interrupt with ID816" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xECC++0x03 hide.long 0x00 "GICD_NSACR51,Non-secure Access Control Register 51" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED0))) group.long 0xED0++0x03 line.long 0x00 "GICD_NSACR52,Non-secure Access Control Register 52" bitfld.long 0x00 30.--31. " NS_ACCESS847 ,Controls Non-secure access of the interrupt with ID847" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS846 ,Controls Non-secure access of the interrupt with ID846" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS845 ,Controls Non-secure access of the interrupt with ID845" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS844 ,Controls Non-secure access of the interrupt with ID844" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS843 ,Controls Non-secure access of the interrupt with ID843" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS842 ,Controls Non-secure access of the interrupt with ID842" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS841 ,Controls Non-secure access of the interrupt with ID841" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS840 ,Controls Non-secure access of the interrupt with ID840" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS839 ,Controls Non-secure access of the interrupt with ID839" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS838 ,Controls Non-secure access of the interrupt with ID838" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS837 ,Controls Non-secure access of the interrupt with ID837" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS836 ,Controls Non-secure access of the interrupt with ID836" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS835 ,Controls Non-secure access of the interrupt with ID835" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS834 ,Controls Non-secure access of the interrupt with ID834" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS833 ,Controls Non-secure access of the interrupt with ID833" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS832 ,Controls Non-secure access of the interrupt with ID832" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xED0++0x03 hide.long 0x00 "GICD_NSACR52,Non-secure Access Control Register 52" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED4))) group.long 0xED4++0x03 line.long 0x00 "GICD_NSACR53,Non-secure Access Control Register 53" bitfld.long 0x00 30.--31. " NS_ACCESS863 ,Controls Non-secure access of the interrupt with ID863" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS862 ,Controls Non-secure access of the interrupt with ID862" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS861 ,Controls Non-secure access of the interrupt with ID861" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS860 ,Controls Non-secure access of the interrupt with ID860" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS859 ,Controls Non-secure access of the interrupt with ID859" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS858 ,Controls Non-secure access of the interrupt with ID858" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS857 ,Controls Non-secure access of the interrupt with ID857" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS856 ,Controls Non-secure access of the interrupt with ID856" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS855 ,Controls Non-secure access of the interrupt with ID855" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS854 ,Controls Non-secure access of the interrupt with ID854" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS853 ,Controls Non-secure access of the interrupt with ID853" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS852 ,Controls Non-secure access of the interrupt with ID852" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS851 ,Controls Non-secure access of the interrupt with ID851" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS850 ,Controls Non-secure access of the interrupt with ID850" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS849 ,Controls Non-secure access of the interrupt with ID849" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS848 ,Controls Non-secure access of the interrupt with ID848" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xED4++0x03 hide.long 0x00 "GICD_NSACR53,Non-secure Access Control Register 53" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED8))) group.long 0xED8++0x03 line.long 0x00 "GICD_NSACR54,Non-secure Access Control Register 54" bitfld.long 0x00 30.--31. " NS_ACCESS879 ,Controls Non-secure access of the interrupt with ID879" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS878 ,Controls Non-secure access of the interrupt with ID878" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS877 ,Controls Non-secure access of the interrupt with ID877" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS876 ,Controls Non-secure access of the interrupt with ID876" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS875 ,Controls Non-secure access of the interrupt with ID875" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS874 ,Controls Non-secure access of the interrupt with ID874" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS873 ,Controls Non-secure access of the interrupt with ID873" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS872 ,Controls Non-secure access of the interrupt with ID872" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS871 ,Controls Non-secure access of the interrupt with ID871" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS870 ,Controls Non-secure access of the interrupt with ID870" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS869 ,Controls Non-secure access of the interrupt with ID869" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS868 ,Controls Non-secure access of the interrupt with ID868" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS867 ,Controls Non-secure access of the interrupt with ID867" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS866 ,Controls Non-secure access of the interrupt with ID866" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS865 ,Controls Non-secure access of the interrupt with ID865" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS864 ,Controls Non-secure access of the interrupt with ID864" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xED8++0x03 hide.long 0x00 "GICD_NSACR54,Non-secure Access Control Register 54" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEDC))) group.long 0xEDC++0x03 line.long 0x00 "GICD_NSACR55,Non-secure Access Control Register 55" bitfld.long 0x00 30.--31. " NS_ACCESS895 ,Controls Non-secure access of the interrupt with ID895" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS894 ,Controls Non-secure access of the interrupt with ID894" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS893 ,Controls Non-secure access of the interrupt with ID893" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS892 ,Controls Non-secure access of the interrupt with ID892" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS891 ,Controls Non-secure access of the interrupt with ID891" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS890 ,Controls Non-secure access of the interrupt with ID890" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS889 ,Controls Non-secure access of the interrupt with ID889" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS888 ,Controls Non-secure access of the interrupt with ID888" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS887 ,Controls Non-secure access of the interrupt with ID887" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS886 ,Controls Non-secure access of the interrupt with ID886" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS885 ,Controls Non-secure access of the interrupt with ID885" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS884 ,Controls Non-secure access of the interrupt with ID884" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS883 ,Controls Non-secure access of the interrupt with ID883" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS882 ,Controls Non-secure access of the interrupt with ID882" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS881 ,Controls Non-secure access of the interrupt with ID881" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS880 ,Controls Non-secure access of the interrupt with ID880" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEDC++0x03 hide.long 0x00 "GICD_NSACR55,Non-secure Access Control Register 55" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE0))) group.long 0xEE0++0x03 line.long 0x00 "GICD_NSACR56,Non-secure Access Control Register 56" bitfld.long 0x00 30.--31. " NS_ACCESS911 ,Controls Non-secure access of the interrupt with ID911" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS910 ,Controls Non-secure access of the interrupt with ID910" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS909 ,Controls Non-secure access of the interrupt with ID909" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS908 ,Controls Non-secure access of the interrupt with ID908" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS907 ,Controls Non-secure access of the interrupt with ID907" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS906 ,Controls Non-secure access of the interrupt with ID906" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS905 ,Controls Non-secure access of the interrupt with ID905" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS904 ,Controls Non-secure access of the interrupt with ID904" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS903 ,Controls Non-secure access of the interrupt with ID903" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS902 ,Controls Non-secure access of the interrupt with ID902" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS901 ,Controls Non-secure access of the interrupt with ID901" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS900 ,Controls Non-secure access of the interrupt with ID900" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS899 ,Controls Non-secure access of the interrupt with ID899" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS898 ,Controls Non-secure access of the interrupt with ID898" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS897 ,Controls Non-secure access of the interrupt with ID897" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS896 ,Controls Non-secure access of the interrupt with ID896" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEE0++0x03 hide.long 0x00 "GICD_NSACR56,Non-secure Access Control Register 56" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE4))) group.long 0xEE4++0x03 line.long 0x00 "GICD_NSACR57,Non-secure Access Control Register 57" bitfld.long 0x00 30.--31. " NS_ACCESS927 ,Controls Non-secure access of the interrupt with ID927" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS926 ,Controls Non-secure access of the interrupt with ID926" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS925 ,Controls Non-secure access of the interrupt with ID925" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS924 ,Controls Non-secure access of the interrupt with ID924" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS923 ,Controls Non-secure access of the interrupt with ID923" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS922 ,Controls Non-secure access of the interrupt with ID922" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS921 ,Controls Non-secure access of the interrupt with ID921" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS920 ,Controls Non-secure access of the interrupt with ID920" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS919 ,Controls Non-secure access of the interrupt with ID919" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS918 ,Controls Non-secure access of the interrupt with ID918" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS917 ,Controls Non-secure access of the interrupt with ID917" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS916 ,Controls Non-secure access of the interrupt with ID916" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS915 ,Controls Non-secure access of the interrupt with ID915" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS914 ,Controls Non-secure access of the interrupt with ID914" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS913 ,Controls Non-secure access of the interrupt with ID913" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS912 ,Controls Non-secure access of the interrupt with ID912" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEE4++0x03 hide.long 0x00 "GICD_NSACR57,Non-secure Access Control Register 57" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE8))) group.long 0xEE8++0x03 line.long 0x00 "GICD_NSACR58,Non-secure Access Control Register 58" bitfld.long 0x00 30.--31. " NS_ACCESS943 ,Controls Non-secure access of the interrupt with ID943" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS942 ,Controls Non-secure access of the interrupt with ID942" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS941 ,Controls Non-secure access of the interrupt with ID941" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS940 ,Controls Non-secure access of the interrupt with ID940" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS939 ,Controls Non-secure access of the interrupt with ID939" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS938 ,Controls Non-secure access of the interrupt with ID938" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS937 ,Controls Non-secure access of the interrupt with ID937" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS936 ,Controls Non-secure access of the interrupt with ID936" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS935 ,Controls Non-secure access of the interrupt with ID935" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS934 ,Controls Non-secure access of the interrupt with ID934" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS933 ,Controls Non-secure access of the interrupt with ID933" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS932 ,Controls Non-secure access of the interrupt with ID932" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS931 ,Controls Non-secure access of the interrupt with ID931" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS930 ,Controls Non-secure access of the interrupt with ID930" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS929 ,Controls Non-secure access of the interrupt with ID929" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS928 ,Controls Non-secure access of the interrupt with ID928" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEE8++0x03 hide.long 0x00 "GICD_NSACR58,Non-secure Access Control Register 58" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEEC))) group.long 0xEEC++0x03 line.long 0x00 "GICD_NSACR59,Non-secure Access Control Register 59" bitfld.long 0x00 30.--31. " NS_ACCESS959 ,Controls Non-secure access of the interrupt with ID959" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS958 ,Controls Non-secure access of the interrupt with ID958" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS957 ,Controls Non-secure access of the interrupt with ID957" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS956 ,Controls Non-secure access of the interrupt with ID956" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS955 ,Controls Non-secure access of the interrupt with ID955" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS954 ,Controls Non-secure access of the interrupt with ID954" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS953 ,Controls Non-secure access of the interrupt with ID953" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS952 ,Controls Non-secure access of the interrupt with ID952" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS951 ,Controls Non-secure access of the interrupt with ID951" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS950 ,Controls Non-secure access of the interrupt with ID950" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS949 ,Controls Non-secure access of the interrupt with ID949" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS948 ,Controls Non-secure access of the interrupt with ID948" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS947 ,Controls Non-secure access of the interrupt with ID947" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS946 ,Controls Non-secure access of the interrupt with ID946" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS945 ,Controls Non-secure access of the interrupt with ID945" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS944 ,Controls Non-secure access of the interrupt with ID944" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEEC++0x03 hide.long 0x00 "GICD_NSACR59,Non-secure Access Control Register 59" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEF0))) group.long 0xEF0++0x03 line.long 0x00 "GICD_NSACR60,Non-secure Access Control Register 60" bitfld.long 0x00 30.--31. " NS_ACCESS975 ,Controls Non-secure access of the interrupt with ID975" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS974 ,Controls Non-secure access of the interrupt with ID974" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS973 ,Controls Non-secure access of the interrupt with ID973" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS972 ,Controls Non-secure access of the interrupt with ID972" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS971 ,Controls Non-secure access of the interrupt with ID971" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS970 ,Controls Non-secure access of the interrupt with ID970" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS969 ,Controls Non-secure access of the interrupt with ID969" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS968 ,Controls Non-secure access of the interrupt with ID968" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS967 ,Controls Non-secure access of the interrupt with ID967" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS966 ,Controls Non-secure access of the interrupt with ID966" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS965 ,Controls Non-secure access of the interrupt with ID965" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS964 ,Controls Non-secure access of the interrupt with ID964" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS963 ,Controls Non-secure access of the interrupt with ID963" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS962 ,Controls Non-secure access of the interrupt with ID962" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS961 ,Controls Non-secure access of the interrupt with ID961" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS960 ,Controls Non-secure access of the interrupt with ID960" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEF0++0x03 hide.long 0x00 "GICD_NSACR60,Non-secure Access Control Register 60" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEF4))) group.long 0xEF4++0x03 line.long 0x00 "GICD_NSACR61,Non-secure Access Control Register 61" bitfld.long 0x00 30.--31. " NS_ACCESS991 ,Controls Non-secure access of the interrupt with ID991" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS990 ,Controls Non-secure access of the interrupt with ID990" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS989 ,Controls Non-secure access of the interrupt with ID989" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS988 ,Controls Non-secure access of the interrupt with ID988" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS987 ,Controls Non-secure access of the interrupt with ID987" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS986 ,Controls Non-secure access of the interrupt with ID986" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS985 ,Controls Non-secure access of the interrupt with ID985" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS984 ,Controls Non-secure access of the interrupt with ID984" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS983 ,Controls Non-secure access of the interrupt with ID983" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS982 ,Controls Non-secure access of the interrupt with ID982" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS981 ,Controls Non-secure access of the interrupt with ID981" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS980 ,Controls Non-secure access of the interrupt with ID980" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS979 ,Controls Non-secure access of the interrupt with ID979" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS978 ,Controls Non-secure access of the interrupt with ID978" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS977 ,Controls Non-secure access of the interrupt with ID977" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS976 ,Controls Non-secure access of the interrupt with ID976" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEF4++0x03 hide.long 0x00 "GICD_NSACR61,Non-secure Access Control Register 61" endif tree.end width 25. tree "Software Generated Interrupt" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x0F00++0x03 hide.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" hgroup.long 0xF10++0x03 hide.long 0x00 "GICD_CLR_PENDSGIR0,SGI Clear Pending Register 0" hgroup.long 0xF14++0x03 hide.long 0x00 "GICD_CLR_PENDSGIR1,SGI Clear Pending Register 1" hgroup.long 0xF18++0x03 hide.long 0x00 "GICD_CLR_PENDSGIR2,SGI Clear Pending Register 2" hgroup.long 0xF1C++0x03 hide.long 0x00 "GICD_CLR_PENDSGIR3,SGI Clear Pending Register 3" hgroup.long 0xF20++0x03 hide.long 0x00 "GICD_SET_PENDSGIR0,SGI Set Pending Register 0" hgroup.long 0xF24++0x03 hide.long 0x00 "GICD_SET_PENDSGIR1,SGI Set Pending Register 1" hgroup.long 0xF28++0x03 hide.long 0x00 "GICD_SET_PENDSGIR2,SGI Set Pending Register 2" hgroup.long 0xF2C++0x03 hide.long 0x00 "GICD_SET_PENDSGIR3,SGI Set Pending Register 3" else wgroup.long 0x0F00++0x03 line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" group.long 0xF10++0x03 line.long 0x00 "GICD_CLR_PENDSGIR0,SGI Clear Pending Register 0" group.long 0xF14++0x03 line.long 0x00 "GICD_CLR_PENDSGIR1,SGI Clear Pending Register 1" group.long 0xF18++0x03 line.long 0x00 "GICD_CLR_PENDSGIR2,SGI Clear Pending Register 2" group.long 0xF1C++0x03 line.long 0x00 "GICD_CLR_PENDSGIR3,SGI Clear Pending Register 3" group.long 0xF20++0x03 line.long 0x00 "GICD_SET_PENDSGIR0,SGI Set Pending Register 0" group.long 0xF24++0x03 line.long 0x00 "GICD_SET_PENDSGIR1,SGI Set Pending Register 1" group.long 0xF28++0x03 line.long 0x00 "GICD_SET_PENDSGIR2,SGI Set Pending Register 2" group.long 0xF2C++0x03 line.long 0x00 "GICD_SET_PENDSGIR3,SGI Set Pending Register 3" endif tree.end width 24. tree "Interrupt Routing Registers" group.quad 0x6100++0x07 line.quad 0x00 "GICD_IROUTER32 ,Interrupt Routing Register 32 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6108++0x07 line.quad 0x00 "GICD_IROUTER33 ,Interrupt Routing Register 33 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6110++0x07 line.quad 0x00 "GICD_IROUTER34 ,Interrupt Routing Register 34 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6118++0x07 line.quad 0x00 "GICD_IROUTER35 ,Interrupt Routing Register 35 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6120++0x07 line.quad 0x00 "GICD_IROUTER36 ,Interrupt Routing Register 36 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6128++0x07 line.quad 0x00 "GICD_IROUTER37 ,Interrupt Routing Register 37 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6130++0x07 line.quad 0x00 "GICD_IROUTER38 ,Interrupt Routing Register 38 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6138++0x07 line.quad 0x00 "GICD_IROUTER39 ,Interrupt Routing Register 39 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6140++0x07 line.quad 0x00 "GICD_IROUTER40 ,Interrupt Routing Register 40 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6148++0x07 line.quad 0x00 "GICD_IROUTER41 ,Interrupt Routing Register 41 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6150++0x07 line.quad 0x00 "GICD_IROUTER42 ,Interrupt Routing Register 42 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6158++0x07 line.quad 0x00 "GICD_IROUTER43 ,Interrupt Routing Register 43 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6160++0x07 line.quad 0x00 "GICD_IROUTER44 ,Interrupt Routing Register 44 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6168++0x07 line.quad 0x00 "GICD_IROUTER45 ,Interrupt Routing Register 45 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6170++0x07 line.quad 0x00 "GICD_IROUTER46 ,Interrupt Routing Register 46 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6178++0x07 line.quad 0x00 "GICD_IROUTER47 ,Interrupt Routing Register 47 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6180++0x07 line.quad 0x00 "GICD_IROUTER48 ,Interrupt Routing Register 48 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6188++0x07 line.quad 0x00 "GICD_IROUTER49 ,Interrupt Routing Register 49 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6190++0x07 line.quad 0x00 "GICD_IROUTER50 ,Interrupt Routing Register 50 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6198++0x07 line.quad 0x00 "GICD_IROUTER51 ,Interrupt Routing Register 51 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61A0++0x07 line.quad 0x00 "GICD_IROUTER52 ,Interrupt Routing Register 52 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61A8++0x07 line.quad 0x00 "GICD_IROUTER53 ,Interrupt Routing Register 53 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61B0++0x07 line.quad 0x00 "GICD_IROUTER54 ,Interrupt Routing Register 54 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61B8++0x07 line.quad 0x00 "GICD_IROUTER55 ,Interrupt Routing Register 55 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61C0++0x07 line.quad 0x00 "GICD_IROUTER56 ,Interrupt Routing Register 56 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61C8++0x07 line.quad 0x00 "GICD_IROUTER57 ,Interrupt Routing Register 57 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61D0++0x07 line.quad 0x00 "GICD_IROUTER58 ,Interrupt Routing Register 58 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61D8++0x07 line.quad 0x00 "GICD_IROUTER59 ,Interrupt Routing Register 59 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61E0++0x07 line.quad 0x00 "GICD_IROUTER60 ,Interrupt Routing Register 60 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61E8++0x07 line.quad 0x00 "GICD_IROUTER61 ,Interrupt Routing Register 61 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61F0++0x07 line.quad 0x00 "GICD_IROUTER62 ,Interrupt Routing Register 62 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61F8++0x07 line.quad 0x00 "GICD_IROUTER63 ,Interrupt Routing Register 63 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6200++0x07 line.quad 0x00 "GICD_IROUTER64 ,Interrupt Routing Register 64 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6208++0x07 line.quad 0x00 "GICD_IROUTER65 ,Interrupt Routing Register 65 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6210++0x07 line.quad 0x00 "GICD_IROUTER66 ,Interrupt Routing Register 66 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6218++0x07 line.quad 0x00 "GICD_IROUTER67 ,Interrupt Routing Register 67 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6220++0x07 line.quad 0x00 "GICD_IROUTER68 ,Interrupt Routing Register 68 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6228++0x07 line.quad 0x00 "GICD_IROUTER69 ,Interrupt Routing Register 69 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6230++0x07 line.quad 0x00 "GICD_IROUTER70 ,Interrupt Routing Register 70 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6238++0x07 line.quad 0x00 "GICD_IROUTER71 ,Interrupt Routing Register 71 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6240++0x07 line.quad 0x00 "GICD_IROUTER72 ,Interrupt Routing Register 72 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6248++0x07 line.quad 0x00 "GICD_IROUTER73 ,Interrupt Routing Register 73 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6250++0x07 line.quad 0x00 "GICD_IROUTER74 ,Interrupt Routing Register 74 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6258++0x07 line.quad 0x00 "GICD_IROUTER75 ,Interrupt Routing Register 75 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6260++0x07 line.quad 0x00 "GICD_IROUTER76 ,Interrupt Routing Register 76 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6268++0x07 line.quad 0x00 "GICD_IROUTER77 ,Interrupt Routing Register 77 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6270++0x07 line.quad 0x00 "GICD_IROUTER78 ,Interrupt Routing Register 78 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6278++0x07 line.quad 0x00 "GICD_IROUTER79 ,Interrupt Routing Register 79 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6280++0x07 line.quad 0x00 "GICD_IROUTER80 ,Interrupt Routing Register 80 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6288++0x07 line.quad 0x00 "GICD_IROUTER81 ,Interrupt Routing Register 81 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6290++0x07 line.quad 0x00 "GICD_IROUTER82 ,Interrupt Routing Register 82 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6298++0x07 line.quad 0x00 "GICD_IROUTER83 ,Interrupt Routing Register 83 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62A0++0x07 line.quad 0x00 "GICD_IROUTER84 ,Interrupt Routing Register 84 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62A8++0x07 line.quad 0x00 "GICD_IROUTER85 ,Interrupt Routing Register 85 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62B0++0x07 line.quad 0x00 "GICD_IROUTER86 ,Interrupt Routing Register 86 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62B8++0x07 line.quad 0x00 "GICD_IROUTER87 ,Interrupt Routing Register 87 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62C0++0x07 line.quad 0x00 "GICD_IROUTER88 ,Interrupt Routing Register 88 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62C8++0x07 line.quad 0x00 "GICD_IROUTER89 ,Interrupt Routing Register 89 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62D0++0x07 line.quad 0x00 "GICD_IROUTER90 ,Interrupt Routing Register 90 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62D8++0x07 line.quad 0x00 "GICD_IROUTER91 ,Interrupt Routing Register 91 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62E0++0x07 line.quad 0x00 "GICD_IROUTER92 ,Interrupt Routing Register 92 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62E8++0x07 line.quad 0x00 "GICD_IROUTER93 ,Interrupt Routing Register 93 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62F0++0x07 line.quad 0x00 "GICD_IROUTER94 ,Interrupt Routing Register 94 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62F8++0x07 line.quad 0x00 "GICD_IROUTER95 ,Interrupt Routing Register 95 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6300++0x07 line.quad 0x00 "GICD_IROUTER96 ,Interrupt Routing Register 96 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6308++0x07 line.quad 0x00 "GICD_IROUTER97 ,Interrupt Routing Register 97 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6310++0x07 line.quad 0x00 "GICD_IROUTER98 ,Interrupt Routing Register 98 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6318++0x07 line.quad 0x00 "GICD_IROUTER99 ,Interrupt Routing Register 99 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6320++0x07 line.quad 0x00 "GICD_IROUTER100,Interrupt Routing Register 100" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6328++0x07 line.quad 0x00 "GICD_IROUTER101,Interrupt Routing Register 101" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6330++0x07 line.quad 0x00 "GICD_IROUTER102,Interrupt Routing Register 102" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6338++0x07 line.quad 0x00 "GICD_IROUTER103,Interrupt Routing Register 103" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6340++0x07 line.quad 0x00 "GICD_IROUTER104,Interrupt Routing Register 104" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6348++0x07 line.quad 0x00 "GICD_IROUTER105,Interrupt Routing Register 105" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6350++0x07 line.quad 0x00 "GICD_IROUTER106,Interrupt Routing Register 106" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6358++0x07 line.quad 0x00 "GICD_IROUTER107,Interrupt Routing Register 107" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6360++0x07 line.quad 0x00 "GICD_IROUTER108,Interrupt Routing Register 108" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6368++0x07 line.quad 0x00 "GICD_IROUTER109,Interrupt Routing Register 109" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6370++0x07 line.quad 0x00 "GICD_IROUTER110,Interrupt Routing Register 110" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6378++0x07 line.quad 0x00 "GICD_IROUTER111,Interrupt Routing Register 111" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6380++0x07 line.quad 0x00 "GICD_IROUTER112,Interrupt Routing Register 112" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6388++0x07 line.quad 0x00 "GICD_IROUTER113,Interrupt Routing Register 113" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6390++0x07 line.quad 0x00 "GICD_IROUTER114,Interrupt Routing Register 114" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6398++0x07 line.quad 0x00 "GICD_IROUTER115,Interrupt Routing Register 115" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63A0++0x07 line.quad 0x00 "GICD_IROUTER116,Interrupt Routing Register 116" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63A8++0x07 line.quad 0x00 "GICD_IROUTER117,Interrupt Routing Register 117" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63B0++0x07 line.quad 0x00 "GICD_IROUTER118,Interrupt Routing Register 118" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63B8++0x07 line.quad 0x00 "GICD_IROUTER119,Interrupt Routing Register 119" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63C0++0x07 line.quad 0x00 "GICD_IROUTER120,Interrupt Routing Register 120" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63C8++0x07 line.quad 0x00 "GICD_IROUTER121,Interrupt Routing Register 121" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63D0++0x07 line.quad 0x00 "GICD_IROUTER122,Interrupt Routing Register 122" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63D8++0x07 line.quad 0x00 "GICD_IROUTER123,Interrupt Routing Register 123" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63E0++0x07 line.quad 0x00 "GICD_IROUTER124,Interrupt Routing Register 124" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63E8++0x07 line.quad 0x00 "GICD_IROUTER125,Interrupt Routing Register 125" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63F0++0x07 line.quad 0x00 "GICD_IROUTER126,Interrupt Routing Register 126" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63F8++0x07 line.quad 0x00 "GICD_IROUTER127,Interrupt Routing Register 127" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6400++0x07 line.quad 0x00 "GICD_IROUTER128,Interrupt Routing Register 128" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6408++0x07 line.quad 0x00 "GICD_IROUTER129,Interrupt Routing Register 129" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6410++0x07 line.quad 0x00 "GICD_IROUTER130,Interrupt Routing Register 130" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6418++0x07 line.quad 0x00 "GICD_IROUTER131,Interrupt Routing Register 131" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6420++0x07 line.quad 0x00 "GICD_IROUTER132,Interrupt Routing Register 132" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6428++0x07 line.quad 0x00 "GICD_IROUTER133,Interrupt Routing Register 133" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6430++0x07 line.quad 0x00 "GICD_IROUTER134,Interrupt Routing Register 134" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6438++0x07 line.quad 0x00 "GICD_IROUTER135,Interrupt Routing Register 135" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6440++0x07 line.quad 0x00 "GICD_IROUTER136,Interrupt Routing Register 136" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6448++0x07 line.quad 0x00 "GICD_IROUTER137,Interrupt Routing Register 137" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6450++0x07 line.quad 0x00 "GICD_IROUTER138,Interrupt Routing Register 138" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6458++0x07 line.quad 0x00 "GICD_IROUTER139,Interrupt Routing Register 139" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6460++0x07 line.quad 0x00 "GICD_IROUTER140,Interrupt Routing Register 140" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6468++0x07 line.quad 0x00 "GICD_IROUTER141,Interrupt Routing Register 141" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6470++0x07 line.quad 0x00 "GICD_IROUTER142,Interrupt Routing Register 142" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6478++0x07 line.quad 0x00 "GICD_IROUTER143,Interrupt Routing Register 143" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6480++0x07 line.quad 0x00 "GICD_IROUTER144,Interrupt Routing Register 144" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6488++0x07 line.quad 0x00 "GICD_IROUTER145,Interrupt Routing Register 145" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6490++0x07 line.quad 0x00 "GICD_IROUTER146,Interrupt Routing Register 146" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6498++0x07 line.quad 0x00 "GICD_IROUTER147,Interrupt Routing Register 147" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64A0++0x07 line.quad 0x00 "GICD_IROUTER148,Interrupt Routing Register 148" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64A8++0x07 line.quad 0x00 "GICD_IROUTER149,Interrupt Routing Register 149" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64B0++0x07 line.quad 0x00 "GICD_IROUTER150,Interrupt Routing Register 150" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64B8++0x07 line.quad 0x00 "GICD_IROUTER151,Interrupt Routing Register 151" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64C0++0x07 line.quad 0x00 "GICD_IROUTER152,Interrupt Routing Register 152" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64C8++0x07 line.quad 0x00 "GICD_IROUTER153,Interrupt Routing Register 153" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64D0++0x07 line.quad 0x00 "GICD_IROUTER154,Interrupt Routing Register 154" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64D8++0x07 line.quad 0x00 "GICD_IROUTER155,Interrupt Routing Register 155" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64E0++0x07 line.quad 0x00 "GICD_IROUTER156,Interrupt Routing Register 156" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64E8++0x07 line.quad 0x00 "GICD_IROUTER157,Interrupt Routing Register 157" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64F0++0x07 line.quad 0x00 "GICD_IROUTER158,Interrupt Routing Register 158" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64F8++0x07 line.quad 0x00 "GICD_IROUTER159,Interrupt Routing Register 159" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6500++0x07 line.quad 0x00 "GICD_IROUTER160,Interrupt Routing Register 160" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6508++0x07 line.quad 0x00 "GICD_IROUTER161,Interrupt Routing Register 161" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6510++0x07 line.quad 0x00 "GICD_IROUTER162,Interrupt Routing Register 162" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6518++0x07 line.quad 0x00 "GICD_IROUTER163,Interrupt Routing Register 163" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6520++0x07 line.quad 0x00 "GICD_IROUTER164,Interrupt Routing Register 164" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6528++0x07 line.quad 0x00 "GICD_IROUTER165,Interrupt Routing Register 165" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6530++0x07 line.quad 0x00 "GICD_IROUTER166,Interrupt Routing Register 166" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6538++0x07 line.quad 0x00 "GICD_IROUTER167,Interrupt Routing Register 167" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6540++0x07 line.quad 0x00 "GICD_IROUTER168,Interrupt Routing Register 168" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6548++0x07 line.quad 0x00 "GICD_IROUTER169,Interrupt Routing Register 169" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6550++0x07 line.quad 0x00 "GICD_IROUTER170,Interrupt Routing Register 170" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6558++0x07 line.quad 0x00 "GICD_IROUTER171,Interrupt Routing Register 171" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6560++0x07 line.quad 0x00 "GICD_IROUTER172,Interrupt Routing Register 172" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6568++0x07 line.quad 0x00 "GICD_IROUTER173,Interrupt Routing Register 173" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6570++0x07 line.quad 0x00 "GICD_IROUTER174,Interrupt Routing Register 174" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6578++0x07 line.quad 0x00 "GICD_IROUTER175,Interrupt Routing Register 175" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6580++0x07 line.quad 0x00 "GICD_IROUTER176,Interrupt Routing Register 176" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6588++0x07 line.quad 0x00 "GICD_IROUTER177,Interrupt Routing Register 177" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6590++0x07 line.quad 0x00 "GICD_IROUTER178,Interrupt Routing Register 178" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6598++0x07 line.quad 0x00 "GICD_IROUTER179,Interrupt Routing Register 179" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65A0++0x07 line.quad 0x00 "GICD_IROUTER180,Interrupt Routing Register 180" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65A8++0x07 line.quad 0x00 "GICD_IROUTER181,Interrupt Routing Register 181" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65B0++0x07 line.quad 0x00 "GICD_IROUTER182,Interrupt Routing Register 182" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65B8++0x07 line.quad 0x00 "GICD_IROUTER183,Interrupt Routing Register 183" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65C0++0x07 line.quad 0x00 "GICD_IROUTER184,Interrupt Routing Register 184" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65C8++0x07 line.quad 0x00 "GICD_IROUTER185,Interrupt Routing Register 185" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65D0++0x07 line.quad 0x00 "GICD_IROUTER186,Interrupt Routing Register 186" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65D8++0x07 line.quad 0x00 "GICD_IROUTER187,Interrupt Routing Register 187" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65E0++0x07 line.quad 0x00 "GICD_IROUTER188,Interrupt Routing Register 188" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65E8++0x07 line.quad 0x00 "GICD_IROUTER189,Interrupt Routing Register 189" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65F0++0x07 line.quad 0x00 "GICD_IROUTER190,Interrupt Routing Register 190" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65F8++0x07 line.quad 0x00 "GICD_IROUTER191,Interrupt Routing Register 191" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6600++0x07 line.quad 0x00 "GICD_IROUTER192,Interrupt Routing Register 192" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6608++0x07 line.quad 0x00 "GICD_IROUTER193,Interrupt Routing Register 193" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6610++0x07 line.quad 0x00 "GICD_IROUTER194,Interrupt Routing Register 194" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6618++0x07 line.quad 0x00 "GICD_IROUTER195,Interrupt Routing Register 195" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6620++0x07 line.quad 0x00 "GICD_IROUTER196,Interrupt Routing Register 196" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6628++0x07 line.quad 0x00 "GICD_IROUTER197,Interrupt Routing Register 197" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6630++0x07 line.quad 0x00 "GICD_IROUTER198,Interrupt Routing Register 198" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6638++0x07 line.quad 0x00 "GICD_IROUTER199,Interrupt Routing Register 199" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6640++0x07 line.quad 0x00 "GICD_IROUTER200,Interrupt Routing Register 200" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6648++0x07 line.quad 0x00 "GICD_IROUTER201,Interrupt Routing Register 201" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6650++0x07 line.quad 0x00 "GICD_IROUTER202,Interrupt Routing Register 202" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6658++0x07 line.quad 0x00 "GICD_IROUTER203,Interrupt Routing Register 203" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6660++0x07 line.quad 0x00 "GICD_IROUTER204,Interrupt Routing Register 204" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6668++0x07 line.quad 0x00 "GICD_IROUTER205,Interrupt Routing Register 205" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6670++0x07 line.quad 0x00 "GICD_IROUTER206,Interrupt Routing Register 206" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6678++0x07 line.quad 0x00 "GICD_IROUTER207,Interrupt Routing Register 207" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6680++0x07 line.quad 0x00 "GICD_IROUTER208,Interrupt Routing Register 208" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6688++0x07 line.quad 0x00 "GICD_IROUTER209,Interrupt Routing Register 209" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6690++0x07 line.quad 0x00 "GICD_IROUTER210,Interrupt Routing Register 210" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6698++0x07 line.quad 0x00 "GICD_IROUTER211,Interrupt Routing Register 211" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66A0++0x07 line.quad 0x00 "GICD_IROUTER212,Interrupt Routing Register 212" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66A8++0x07 line.quad 0x00 "GICD_IROUTER213,Interrupt Routing Register 213" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66B0++0x07 line.quad 0x00 "GICD_IROUTER214,Interrupt Routing Register 214" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66B8++0x07 line.quad 0x00 "GICD_IROUTER215,Interrupt Routing Register 215" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66C0++0x07 line.quad 0x00 "GICD_IROUTER216,Interrupt Routing Register 216" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66C8++0x07 line.quad 0x00 "GICD_IROUTER217,Interrupt Routing Register 217" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66D0++0x07 line.quad 0x00 "GICD_IROUTER218,Interrupt Routing Register 218" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66D8++0x07 line.quad 0x00 "GICD_IROUTER219,Interrupt Routing Register 219" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66E0++0x07 line.quad 0x00 "GICD_IROUTER220,Interrupt Routing Register 220" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66E8++0x07 line.quad 0x00 "GICD_IROUTER221,Interrupt Routing Register 221" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66F0++0x07 line.quad 0x00 "GICD_IROUTER222,Interrupt Routing Register 222" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66F8++0x07 line.quad 0x00 "GICD_IROUTER223,Interrupt Routing Register 223" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6700++0x07 line.quad 0x00 "GICD_IROUTER224,Interrupt Routing Register 224" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6708++0x07 line.quad 0x00 "GICD_IROUTER225,Interrupt Routing Register 225" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6710++0x07 line.quad 0x00 "GICD_IROUTER226,Interrupt Routing Register 226" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6718++0x07 line.quad 0x00 "GICD_IROUTER227,Interrupt Routing Register 227" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6720++0x07 line.quad 0x00 "GICD_IROUTER228,Interrupt Routing Register 228" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6728++0x07 line.quad 0x00 "GICD_IROUTER229,Interrupt Routing Register 229" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6730++0x07 line.quad 0x00 "GICD_IROUTER230,Interrupt Routing Register 230" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6738++0x07 line.quad 0x00 "GICD_IROUTER231,Interrupt Routing Register 231" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6740++0x07 line.quad 0x00 "GICD_IROUTER232,Interrupt Routing Register 232" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6748++0x07 line.quad 0x00 "GICD_IROUTER233,Interrupt Routing Register 233" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6750++0x07 line.quad 0x00 "GICD_IROUTER234,Interrupt Routing Register 234" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6758++0x07 line.quad 0x00 "GICD_IROUTER235,Interrupt Routing Register 235" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6760++0x07 line.quad 0x00 "GICD_IROUTER236,Interrupt Routing Register 236" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6768++0x07 line.quad 0x00 "GICD_IROUTER237,Interrupt Routing Register 237" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6770++0x07 line.quad 0x00 "GICD_IROUTER238,Interrupt Routing Register 238" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6778++0x07 line.quad 0x00 "GICD_IROUTER239,Interrupt Routing Register 239" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6780++0x07 line.quad 0x00 "GICD_IROUTER240,Interrupt Routing Register 240" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6788++0x07 line.quad 0x00 "GICD_IROUTER241,Interrupt Routing Register 241" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6790++0x07 line.quad 0x00 "GICD_IROUTER242,Interrupt Routing Register 242" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6798++0x07 line.quad 0x00 "GICD_IROUTER243,Interrupt Routing Register 243" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67A0++0x07 line.quad 0x00 "GICD_IROUTER244,Interrupt Routing Register 244" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67A8++0x07 line.quad 0x00 "GICD_IROUTER245,Interrupt Routing Register 245" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67B0++0x07 line.quad 0x00 "GICD_IROUTER246,Interrupt Routing Register 246" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67B8++0x07 line.quad 0x00 "GICD_IROUTER247,Interrupt Routing Register 247" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67C0++0x07 line.quad 0x00 "GICD_IROUTER248,Interrupt Routing Register 248" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67C8++0x07 line.quad 0x00 "GICD_IROUTER249,Interrupt Routing Register 249" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67D0++0x07 line.quad 0x00 "GICD_IROUTER250,Interrupt Routing Register 250" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67D8++0x07 line.quad 0x00 "GICD_IROUTER251,Interrupt Routing Register 251" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67E0++0x07 line.quad 0x00 "GICD_IROUTER252,Interrupt Routing Register 252" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67E8++0x07 line.quad 0x00 "GICD_IROUTER253,Interrupt Routing Register 253" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67F0++0x07 line.quad 0x00 "GICD_IROUTER254,Interrupt Routing Register 254" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67F8++0x07 line.quad 0x00 "GICD_IROUTER255,Interrupt Routing Register 255" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6800++0x07 line.quad 0x00 "GICD_IROUTER256,Interrupt Routing Register 256" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6808++0x07 line.quad 0x00 "GICD_IROUTER257,Interrupt Routing Register 257" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6810++0x07 line.quad 0x00 "GICD_IROUTER258,Interrupt Routing Register 258" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6818++0x07 line.quad 0x00 "GICD_IROUTER259,Interrupt Routing Register 259" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6820++0x07 line.quad 0x00 "GICD_IROUTER260,Interrupt Routing Register 260" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6828++0x07 line.quad 0x00 "GICD_IROUTER261,Interrupt Routing Register 261" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6830++0x07 line.quad 0x00 "GICD_IROUTER262,Interrupt Routing Register 262" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6838++0x07 line.quad 0x00 "GICD_IROUTER263,Interrupt Routing Register 263" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6840++0x07 line.quad 0x00 "GICD_IROUTER264,Interrupt Routing Register 264" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6848++0x07 line.quad 0x00 "GICD_IROUTER265,Interrupt Routing Register 265" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6850++0x07 line.quad 0x00 "GICD_IROUTER266,Interrupt Routing Register 266" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6858++0x07 line.quad 0x00 "GICD_IROUTER267,Interrupt Routing Register 267" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6860++0x07 line.quad 0x00 "GICD_IROUTER268,Interrupt Routing Register 268" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6868++0x07 line.quad 0x00 "GICD_IROUTER269,Interrupt Routing Register 269" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6870++0x07 line.quad 0x00 "GICD_IROUTER270,Interrupt Routing Register 270" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6878++0x07 line.quad 0x00 "GICD_IROUTER271,Interrupt Routing Register 271" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6880++0x07 line.quad 0x00 "GICD_IROUTER272,Interrupt Routing Register 272" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6888++0x07 line.quad 0x00 "GICD_IROUTER273,Interrupt Routing Register 273" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6890++0x07 line.quad 0x00 "GICD_IROUTER274,Interrupt Routing Register 274" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6898++0x07 line.quad 0x00 "GICD_IROUTER275,Interrupt Routing Register 275" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68A0++0x07 line.quad 0x00 "GICD_IROUTER276,Interrupt Routing Register 276" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68A8++0x07 line.quad 0x00 "GICD_IROUTER277,Interrupt Routing Register 277" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68B0++0x07 line.quad 0x00 "GICD_IROUTER278,Interrupt Routing Register 278" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68B8++0x07 line.quad 0x00 "GICD_IROUTER279,Interrupt Routing Register 279" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68C0++0x07 line.quad 0x00 "GICD_IROUTER280,Interrupt Routing Register 280" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68C8++0x07 line.quad 0x00 "GICD_IROUTER281,Interrupt Routing Register 281" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68D0++0x07 line.quad 0x00 "GICD_IROUTER282,Interrupt Routing Register 282" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68D8++0x07 line.quad 0x00 "GICD_IROUTER283,Interrupt Routing Register 283" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68E0++0x07 line.quad 0x00 "GICD_IROUTER284,Interrupt Routing Register 284" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68E8++0x07 line.quad 0x00 "GICD_IROUTER285,Interrupt Routing Register 285" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68F0++0x07 line.quad 0x00 "GICD_IROUTER286,Interrupt Routing Register 286" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68F8++0x07 line.quad 0x00 "GICD_IROUTER287,Interrupt Routing Register 287" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6900++0x07 line.quad 0x00 "GICD_IROUTER288,Interrupt Routing Register 288" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6908++0x07 line.quad 0x00 "GICD_IROUTER289,Interrupt Routing Register 289" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6910++0x07 line.quad 0x00 "GICD_IROUTER290,Interrupt Routing Register 290" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6918++0x07 line.quad 0x00 "GICD_IROUTER291,Interrupt Routing Register 291" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6920++0x07 line.quad 0x00 "GICD_IROUTER292,Interrupt Routing Register 292" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6928++0x07 line.quad 0x00 "GICD_IROUTER293,Interrupt Routing Register 293" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6930++0x07 line.quad 0x00 "GICD_IROUTER294,Interrupt Routing Register 294" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6938++0x07 line.quad 0x00 "GICD_IROUTER295,Interrupt Routing Register 295" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6940++0x07 line.quad 0x00 "GICD_IROUTER296,Interrupt Routing Register 296" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6948++0x07 line.quad 0x00 "GICD_IROUTER297,Interrupt Routing Register 297" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6950++0x07 line.quad 0x00 "GICD_IROUTER298,Interrupt Routing Register 298" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6958++0x07 line.quad 0x00 "GICD_IROUTER299,Interrupt Routing Register 299" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6960++0x07 line.quad 0x00 "GICD_IROUTER300,Interrupt Routing Register 300" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6968++0x07 line.quad 0x00 "GICD_IROUTER301,Interrupt Routing Register 301" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6970++0x07 line.quad 0x00 "GICD_IROUTER302,Interrupt Routing Register 302" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6978++0x07 line.quad 0x00 "GICD_IROUTER303,Interrupt Routing Register 303" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6980++0x07 line.quad 0x00 "GICD_IROUTER304,Interrupt Routing Register 304" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6988++0x07 line.quad 0x00 "GICD_IROUTER305,Interrupt Routing Register 305" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6990++0x07 line.quad 0x00 "GICD_IROUTER306,Interrupt Routing Register 306" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6998++0x07 line.quad 0x00 "GICD_IROUTER307,Interrupt Routing Register 307" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69A0++0x07 line.quad 0x00 "GICD_IROUTER308,Interrupt Routing Register 308" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69A8++0x07 line.quad 0x00 "GICD_IROUTER309,Interrupt Routing Register 309" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69B0++0x07 line.quad 0x00 "GICD_IROUTER310,Interrupt Routing Register 310" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69B8++0x07 line.quad 0x00 "GICD_IROUTER311,Interrupt Routing Register 311" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69C0++0x07 line.quad 0x00 "GICD_IROUTER312,Interrupt Routing Register 312" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69C8++0x07 line.quad 0x00 "GICD_IROUTER313,Interrupt Routing Register 313" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69D0++0x07 line.quad 0x00 "GICD_IROUTER314,Interrupt Routing Register 314" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69D8++0x07 line.quad 0x00 "GICD_IROUTER315,Interrupt Routing Register 315" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69E0++0x07 line.quad 0x00 "GICD_IROUTER316,Interrupt Routing Register 316" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69E8++0x07 line.quad 0x00 "GICD_IROUTER317,Interrupt Routing Register 317" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69F0++0x07 line.quad 0x00 "GICD_IROUTER318,Interrupt Routing Register 318" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69F8++0x07 line.quad 0x00 "GICD_IROUTER319,Interrupt Routing Register 319" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A00++0x07 line.quad 0x00 "GICD_IROUTER320,Interrupt Routing Register 320" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A08++0x07 line.quad 0x00 "GICD_IROUTER321,Interrupt Routing Register 321" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A10++0x07 line.quad 0x00 "GICD_IROUTER322,Interrupt Routing Register 322" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A18++0x07 line.quad 0x00 "GICD_IROUTER323,Interrupt Routing Register 323" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A20++0x07 line.quad 0x00 "GICD_IROUTER324,Interrupt Routing Register 324" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A28++0x07 line.quad 0x00 "GICD_IROUTER325,Interrupt Routing Register 325" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A30++0x07 line.quad 0x00 "GICD_IROUTER326,Interrupt Routing Register 326" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A38++0x07 line.quad 0x00 "GICD_IROUTER327,Interrupt Routing Register 327" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A40++0x07 line.quad 0x00 "GICD_IROUTER328,Interrupt Routing Register 328" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A48++0x07 line.quad 0x00 "GICD_IROUTER329,Interrupt Routing Register 329" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A50++0x07 line.quad 0x00 "GICD_IROUTER330,Interrupt Routing Register 330" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A58++0x07 line.quad 0x00 "GICD_IROUTER331,Interrupt Routing Register 331" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A60++0x07 line.quad 0x00 "GICD_IROUTER332,Interrupt Routing Register 332" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A68++0x07 line.quad 0x00 "GICD_IROUTER333,Interrupt Routing Register 333" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A70++0x07 line.quad 0x00 "GICD_IROUTER334,Interrupt Routing Register 334" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A78++0x07 line.quad 0x00 "GICD_IROUTER335,Interrupt Routing Register 335" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A80++0x07 line.quad 0x00 "GICD_IROUTER336,Interrupt Routing Register 336" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A88++0x07 line.quad 0x00 "GICD_IROUTER337,Interrupt Routing Register 337" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A90++0x07 line.quad 0x00 "GICD_IROUTER338,Interrupt Routing Register 338" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A98++0x07 line.quad 0x00 "GICD_IROUTER339,Interrupt Routing Register 339" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AA0++0x07 line.quad 0x00 "GICD_IROUTER340,Interrupt Routing Register 340" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AA8++0x07 line.quad 0x00 "GICD_IROUTER341,Interrupt Routing Register 341" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AB0++0x07 line.quad 0x00 "GICD_IROUTER342,Interrupt Routing Register 342" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AB8++0x07 line.quad 0x00 "GICD_IROUTER343,Interrupt Routing Register 343" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AC0++0x07 line.quad 0x00 "GICD_IROUTER344,Interrupt Routing Register 344" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AC8++0x07 line.quad 0x00 "GICD_IROUTER345,Interrupt Routing Register 345" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AD0++0x07 line.quad 0x00 "GICD_IROUTER346,Interrupt Routing Register 346" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AD8++0x07 line.quad 0x00 "GICD_IROUTER347,Interrupt Routing Register 347" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AE0++0x07 line.quad 0x00 "GICD_IROUTER348,Interrupt Routing Register 348" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AE8++0x07 line.quad 0x00 "GICD_IROUTER349,Interrupt Routing Register 349" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AF0++0x07 line.quad 0x00 "GICD_IROUTER350,Interrupt Routing Register 350" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AF8++0x07 line.quad 0x00 "GICD_IROUTER351,Interrupt Routing Register 351" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B00++0x07 line.quad 0x00 "GICD_IROUTER352,Interrupt Routing Register 352" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B08++0x07 line.quad 0x00 "GICD_IROUTER353,Interrupt Routing Register 353" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B10++0x07 line.quad 0x00 "GICD_IROUTER354,Interrupt Routing Register 354" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B18++0x07 line.quad 0x00 "GICD_IROUTER355,Interrupt Routing Register 355" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B20++0x07 line.quad 0x00 "GICD_IROUTER356,Interrupt Routing Register 356" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B28++0x07 line.quad 0x00 "GICD_IROUTER357,Interrupt Routing Register 357" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B30++0x07 line.quad 0x00 "GICD_IROUTER358,Interrupt Routing Register 358" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B38++0x07 line.quad 0x00 "GICD_IROUTER359,Interrupt Routing Register 359" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B40++0x07 line.quad 0x00 "GICD_IROUTER360,Interrupt Routing Register 360" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B48++0x07 line.quad 0x00 "GICD_IROUTER361,Interrupt Routing Register 361" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B50++0x07 line.quad 0x00 "GICD_IROUTER362,Interrupt Routing Register 362" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B58++0x07 line.quad 0x00 "GICD_IROUTER363,Interrupt Routing Register 363" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B60++0x07 line.quad 0x00 "GICD_IROUTER364,Interrupt Routing Register 364" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B68++0x07 line.quad 0x00 "GICD_IROUTER365,Interrupt Routing Register 365" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B70++0x07 line.quad 0x00 "GICD_IROUTER366,Interrupt Routing Register 366" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B78++0x07 line.quad 0x00 "GICD_IROUTER367,Interrupt Routing Register 367" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B80++0x07 line.quad 0x00 "GICD_IROUTER368,Interrupt Routing Register 368" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B88++0x07 line.quad 0x00 "GICD_IROUTER369,Interrupt Routing Register 369" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B90++0x07 line.quad 0x00 "GICD_IROUTER370,Interrupt Routing Register 370" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B98++0x07 line.quad 0x00 "GICD_IROUTER371,Interrupt Routing Register 371" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BA0++0x07 line.quad 0x00 "GICD_IROUTER372,Interrupt Routing Register 372" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BA8++0x07 line.quad 0x00 "GICD_IROUTER373,Interrupt Routing Register 373" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BB0++0x07 line.quad 0x00 "GICD_IROUTER374,Interrupt Routing Register 374" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BB8++0x07 line.quad 0x00 "GICD_IROUTER375,Interrupt Routing Register 375" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BC0++0x07 line.quad 0x00 "GICD_IROUTER376,Interrupt Routing Register 376" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BC8++0x07 line.quad 0x00 "GICD_IROUTER377,Interrupt Routing Register 377" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BD0++0x07 line.quad 0x00 "GICD_IROUTER378,Interrupt Routing Register 378" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BD8++0x07 line.quad 0x00 "GICD_IROUTER379,Interrupt Routing Register 379" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BE0++0x07 line.quad 0x00 "GICD_IROUTER380,Interrupt Routing Register 380" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BE8++0x07 line.quad 0x00 "GICD_IROUTER381,Interrupt Routing Register 381" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BF0++0x07 line.quad 0x00 "GICD_IROUTER382,Interrupt Routing Register 382" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BF8++0x07 line.quad 0x00 "GICD_IROUTER383,Interrupt Routing Register 383" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C00++0x07 line.quad 0x00 "GICD_IROUTER384,Interrupt Routing Register 384" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C08++0x07 line.quad 0x00 "GICD_IROUTER385,Interrupt Routing Register 385" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C10++0x07 line.quad 0x00 "GICD_IROUTER386,Interrupt Routing Register 386" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C18++0x07 line.quad 0x00 "GICD_IROUTER387,Interrupt Routing Register 387" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C20++0x07 line.quad 0x00 "GICD_IROUTER388,Interrupt Routing Register 388" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C28++0x07 line.quad 0x00 "GICD_IROUTER389,Interrupt Routing Register 389" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C30++0x07 line.quad 0x00 "GICD_IROUTER390,Interrupt Routing Register 390" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C38++0x07 line.quad 0x00 "GICD_IROUTER391,Interrupt Routing Register 391" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C40++0x07 line.quad 0x00 "GICD_IROUTER392,Interrupt Routing Register 392" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C48++0x07 line.quad 0x00 "GICD_IROUTER393,Interrupt Routing Register 393" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C50++0x07 line.quad 0x00 "GICD_IROUTER394,Interrupt Routing Register 394" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C58++0x07 line.quad 0x00 "GICD_IROUTER395,Interrupt Routing Register 395" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C60++0x07 line.quad 0x00 "GICD_IROUTER396,Interrupt Routing Register 396" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C68++0x07 line.quad 0x00 "GICD_IROUTER397,Interrupt Routing Register 397" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C70++0x07 line.quad 0x00 "GICD_IROUTER398,Interrupt Routing Register 398" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C78++0x07 line.quad 0x00 "GICD_IROUTER399,Interrupt Routing Register 399" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C80++0x07 line.quad 0x00 "GICD_IROUTER400,Interrupt Routing Register 400" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C88++0x07 line.quad 0x00 "GICD_IROUTER401,Interrupt Routing Register 401" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C90++0x07 line.quad 0x00 "GICD_IROUTER402,Interrupt Routing Register 402" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C98++0x07 line.quad 0x00 "GICD_IROUTER403,Interrupt Routing Register 403" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CA0++0x07 line.quad 0x00 "GICD_IROUTER404,Interrupt Routing Register 404" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CA8++0x07 line.quad 0x00 "GICD_IROUTER405,Interrupt Routing Register 405" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CB0++0x07 line.quad 0x00 "GICD_IROUTER406,Interrupt Routing Register 406" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CB8++0x07 line.quad 0x00 "GICD_IROUTER407,Interrupt Routing Register 407" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CC0++0x07 line.quad 0x00 "GICD_IROUTER408,Interrupt Routing Register 408" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CC8++0x07 line.quad 0x00 "GICD_IROUTER409,Interrupt Routing Register 409" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CD0++0x07 line.quad 0x00 "GICD_IROUTER410,Interrupt Routing Register 410" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CD8++0x07 line.quad 0x00 "GICD_IROUTER411,Interrupt Routing Register 411" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CE0++0x07 line.quad 0x00 "GICD_IROUTER412,Interrupt Routing Register 412" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CE8++0x07 line.quad 0x00 "GICD_IROUTER413,Interrupt Routing Register 413" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CF0++0x07 line.quad 0x00 "GICD_IROUTER414,Interrupt Routing Register 414" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CF8++0x07 line.quad 0x00 "GICD_IROUTER415,Interrupt Routing Register 415" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D00++0x07 line.quad 0x00 "GICD_IROUTER416,Interrupt Routing Register 416" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D08++0x07 line.quad 0x00 "GICD_IROUTER417,Interrupt Routing Register 417" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D10++0x07 line.quad 0x00 "GICD_IROUTER418,Interrupt Routing Register 418" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D18++0x07 line.quad 0x00 "GICD_IROUTER419,Interrupt Routing Register 419" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D20++0x07 line.quad 0x00 "GICD_IROUTER420,Interrupt Routing Register 420" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D28++0x07 line.quad 0x00 "GICD_IROUTER421,Interrupt Routing Register 421" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D30++0x07 line.quad 0x00 "GICD_IROUTER422,Interrupt Routing Register 422" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D38++0x07 line.quad 0x00 "GICD_IROUTER423,Interrupt Routing Register 423" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D40++0x07 line.quad 0x00 "GICD_IROUTER424,Interrupt Routing Register 424" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D48++0x07 line.quad 0x00 "GICD_IROUTER425,Interrupt Routing Register 425" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D50++0x07 line.quad 0x00 "GICD_IROUTER426,Interrupt Routing Register 426" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D58++0x07 line.quad 0x00 "GICD_IROUTER427,Interrupt Routing Register 427" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D60++0x07 line.quad 0x00 "GICD_IROUTER428,Interrupt Routing Register 428" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D68++0x07 line.quad 0x00 "GICD_IROUTER429,Interrupt Routing Register 429" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D70++0x07 line.quad 0x00 "GICD_IROUTER430,Interrupt Routing Register 430" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D78++0x07 line.quad 0x00 "GICD_IROUTER431,Interrupt Routing Register 431" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D80++0x07 line.quad 0x00 "GICD_IROUTER432,Interrupt Routing Register 432" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D88++0x07 line.quad 0x00 "GICD_IROUTER433,Interrupt Routing Register 433" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D90++0x07 line.quad 0x00 "GICD_IROUTER434,Interrupt Routing Register 434" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D98++0x07 line.quad 0x00 "GICD_IROUTER435,Interrupt Routing Register 435" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DA0++0x07 line.quad 0x00 "GICD_IROUTER436,Interrupt Routing Register 436" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DA8++0x07 line.quad 0x00 "GICD_IROUTER437,Interrupt Routing Register 437" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DB0++0x07 line.quad 0x00 "GICD_IROUTER438,Interrupt Routing Register 438" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DB8++0x07 line.quad 0x00 "GICD_IROUTER439,Interrupt Routing Register 439" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DC0++0x07 line.quad 0x00 "GICD_IROUTER440,Interrupt Routing Register 440" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DC8++0x07 line.quad 0x00 "GICD_IROUTER441,Interrupt Routing Register 441" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DD0++0x07 line.quad 0x00 "GICD_IROUTER442,Interrupt Routing Register 442" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DD8++0x07 line.quad 0x00 "GICD_IROUTER443,Interrupt Routing Register 443" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DE0++0x07 line.quad 0x00 "GICD_IROUTER444,Interrupt Routing Register 444" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DE8++0x07 line.quad 0x00 "GICD_IROUTER445,Interrupt Routing Register 445" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DF0++0x07 line.quad 0x00 "GICD_IROUTER446,Interrupt Routing Register 446" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DF8++0x07 line.quad 0x00 "GICD_IROUTER447,Interrupt Routing Register 447" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E00++0x07 line.quad 0x00 "GICD_IROUTER448,Interrupt Routing Register 448" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E08++0x07 line.quad 0x00 "GICD_IROUTER449,Interrupt Routing Register 449" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E10++0x07 line.quad 0x00 "GICD_IROUTER450,Interrupt Routing Register 450" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E18++0x07 line.quad 0x00 "GICD_IROUTER451,Interrupt Routing Register 451" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E20++0x07 line.quad 0x00 "GICD_IROUTER452,Interrupt Routing Register 452" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E28++0x07 line.quad 0x00 "GICD_IROUTER453,Interrupt Routing Register 453" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E30++0x07 line.quad 0x00 "GICD_IROUTER454,Interrupt Routing Register 454" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E38++0x07 line.quad 0x00 "GICD_IROUTER455,Interrupt Routing Register 455" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E40++0x07 line.quad 0x00 "GICD_IROUTER456,Interrupt Routing Register 456" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E48++0x07 line.quad 0x00 "GICD_IROUTER457,Interrupt Routing Register 457" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E50++0x07 line.quad 0x00 "GICD_IROUTER458,Interrupt Routing Register 458" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E58++0x07 line.quad 0x00 "GICD_IROUTER459,Interrupt Routing Register 459" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E60++0x07 line.quad 0x00 "GICD_IROUTER460,Interrupt Routing Register 460" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E68++0x07 line.quad 0x00 "GICD_IROUTER461,Interrupt Routing Register 461" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E70++0x07 line.quad 0x00 "GICD_IROUTER462,Interrupt Routing Register 462" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E78++0x07 line.quad 0x00 "GICD_IROUTER463,Interrupt Routing Register 463" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E80++0x07 line.quad 0x00 "GICD_IROUTER464,Interrupt Routing Register 464" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E88++0x07 line.quad 0x00 "GICD_IROUTER465,Interrupt Routing Register 465" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E90++0x07 line.quad 0x00 "GICD_IROUTER466,Interrupt Routing Register 466" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E98++0x07 line.quad 0x00 "GICD_IROUTER467,Interrupt Routing Register 467" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EA0++0x07 line.quad 0x00 "GICD_IROUTER468,Interrupt Routing Register 468" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EA8++0x07 line.quad 0x00 "GICD_IROUTER469,Interrupt Routing Register 469" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EB0++0x07 line.quad 0x00 "GICD_IROUTER470,Interrupt Routing Register 470" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EB8++0x07 line.quad 0x00 "GICD_IROUTER471,Interrupt Routing Register 471" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EC0++0x07 line.quad 0x00 "GICD_IROUTER472,Interrupt Routing Register 472" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EC8++0x07 line.quad 0x00 "GICD_IROUTER473,Interrupt Routing Register 473" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6ED0++0x07 line.quad 0x00 "GICD_IROUTER474,Interrupt Routing Register 474" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6ED8++0x07 line.quad 0x00 "GICD_IROUTER475,Interrupt Routing Register 475" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EE0++0x07 line.quad 0x00 "GICD_IROUTER476,Interrupt Routing Register 476" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EE8++0x07 line.quad 0x00 "GICD_IROUTER477,Interrupt Routing Register 477" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EF0++0x07 line.quad 0x00 "GICD_IROUTER478,Interrupt Routing Register 478" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EF8++0x07 line.quad 0x00 "GICD_IROUTER479,Interrupt Routing Register 479" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F00++0x07 line.quad 0x00 "GICD_IROUTER480,Interrupt Routing Register 480" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F08++0x07 line.quad 0x00 "GICD_IROUTER481,Interrupt Routing Register 481" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F10++0x07 line.quad 0x00 "GICD_IROUTER482,Interrupt Routing Register 482" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F18++0x07 line.quad 0x00 "GICD_IROUTER483,Interrupt Routing Register 483" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F20++0x07 line.quad 0x00 "GICD_IROUTER484,Interrupt Routing Register 484" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F28++0x07 line.quad 0x00 "GICD_IROUTER485,Interrupt Routing Register 485" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F30++0x07 line.quad 0x00 "GICD_IROUTER486,Interrupt Routing Register 486" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F38++0x07 line.quad 0x00 "GICD_IROUTER487,Interrupt Routing Register 487" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F40++0x07 line.quad 0x00 "GICD_IROUTER488,Interrupt Routing Register 488" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F48++0x07 line.quad 0x00 "GICD_IROUTER489,Interrupt Routing Register 489" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F50++0x07 line.quad 0x00 "GICD_IROUTER490,Interrupt Routing Register 490" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F58++0x07 line.quad 0x00 "GICD_IROUTER491,Interrupt Routing Register 491" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F60++0x07 line.quad 0x00 "GICD_IROUTER492,Interrupt Routing Register 492" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F68++0x07 line.quad 0x00 "GICD_IROUTER493,Interrupt Routing Register 493" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F70++0x07 line.quad 0x00 "GICD_IROUTER494,Interrupt Routing Register 494" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F78++0x07 line.quad 0x00 "GICD_IROUTER495,Interrupt Routing Register 495" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F80++0x07 line.quad 0x00 "GICD_IROUTER496,Interrupt Routing Register 496" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F88++0x07 line.quad 0x00 "GICD_IROUTER497,Interrupt Routing Register 497" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F90++0x07 line.quad 0x00 "GICD_IROUTER498,Interrupt Routing Register 498" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F98++0x07 line.quad 0x00 "GICD_IROUTER499,Interrupt Routing Register 499" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FA0++0x07 line.quad 0x00 "GICD_IROUTER500,Interrupt Routing Register 500" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FA8++0x07 line.quad 0x00 "GICD_IROUTER501,Interrupt Routing Register 501" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FB0++0x07 line.quad 0x00 "GICD_IROUTER502,Interrupt Routing Register 502" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FB8++0x07 line.quad 0x00 "GICD_IROUTER503,Interrupt Routing Register 503" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FC0++0x07 line.quad 0x00 "GICD_IROUTER504,Interrupt Routing Register 504" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FC8++0x07 line.quad 0x00 "GICD_IROUTER505,Interrupt Routing Register 505" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FD0++0x07 line.quad 0x00 "GICD_IROUTER506,Interrupt Routing Register 506" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FD8++0x07 line.quad 0x00 "GICD_IROUTER507,Interrupt Routing Register 507" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FE0++0x07 line.quad 0x00 "GICD_IROUTER508,Interrupt Routing Register 508" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FE8++0x07 line.quad 0x00 "GICD_IROUTER509,Interrupt Routing Register 509" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FF0++0x07 line.quad 0x00 "GICD_IROUTER510,Interrupt Routing Register 510" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FF8++0x07 line.quad 0x00 "GICD_IROUTER511,Interrupt Routing Register 511" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7000++0x07 line.quad 0x00 "GICD_IROUTER512,Interrupt Routing Register 512" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7008++0x07 line.quad 0x00 "GICD_IROUTER513,Interrupt Routing Register 513" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7010++0x07 line.quad 0x00 "GICD_IROUTER514,Interrupt Routing Register 514" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7018++0x07 line.quad 0x00 "GICD_IROUTER515,Interrupt Routing Register 515" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7020++0x07 line.quad 0x00 "GICD_IROUTER516,Interrupt Routing Register 516" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7028++0x07 line.quad 0x00 "GICD_IROUTER517,Interrupt Routing Register 517" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7030++0x07 line.quad 0x00 "GICD_IROUTER518,Interrupt Routing Register 518" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7038++0x07 line.quad 0x00 "GICD_IROUTER519,Interrupt Routing Register 519" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7040++0x07 line.quad 0x00 "GICD_IROUTER520,Interrupt Routing Register 520" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7048++0x07 line.quad 0x00 "GICD_IROUTER521,Interrupt Routing Register 521" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7050++0x07 line.quad 0x00 "GICD_IROUTER522,Interrupt Routing Register 522" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7058++0x07 line.quad 0x00 "GICD_IROUTER523,Interrupt Routing Register 523" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7060++0x07 line.quad 0x00 "GICD_IROUTER524,Interrupt Routing Register 524" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7068++0x07 line.quad 0x00 "GICD_IROUTER525,Interrupt Routing Register 525" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7070++0x07 line.quad 0x00 "GICD_IROUTER526,Interrupt Routing Register 526" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7078++0x07 line.quad 0x00 "GICD_IROUTER527,Interrupt Routing Register 527" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7080++0x07 line.quad 0x00 "GICD_IROUTER528,Interrupt Routing Register 528" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7088++0x07 line.quad 0x00 "GICD_IROUTER529,Interrupt Routing Register 529" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7090++0x07 line.quad 0x00 "GICD_IROUTER530,Interrupt Routing Register 530" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7098++0x07 line.quad 0x00 "GICD_IROUTER531,Interrupt Routing Register 531" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70A0++0x07 line.quad 0x00 "GICD_IROUTER532,Interrupt Routing Register 532" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70A8++0x07 line.quad 0x00 "GICD_IROUTER533,Interrupt Routing Register 533" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70B0++0x07 line.quad 0x00 "GICD_IROUTER534,Interrupt Routing Register 534" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70B8++0x07 line.quad 0x00 "GICD_IROUTER535,Interrupt Routing Register 535" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70C0++0x07 line.quad 0x00 "GICD_IROUTER536,Interrupt Routing Register 536" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70C8++0x07 line.quad 0x00 "GICD_IROUTER537,Interrupt Routing Register 537" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70D0++0x07 line.quad 0x00 "GICD_IROUTER538,Interrupt Routing Register 538" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70D8++0x07 line.quad 0x00 "GICD_IROUTER539,Interrupt Routing Register 539" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70E0++0x07 line.quad 0x00 "GICD_IROUTER540,Interrupt Routing Register 540" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70E8++0x07 line.quad 0x00 "GICD_IROUTER541,Interrupt Routing Register 541" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70F0++0x07 line.quad 0x00 "GICD_IROUTER542,Interrupt Routing Register 542" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70F8++0x07 line.quad 0x00 "GICD_IROUTER543,Interrupt Routing Register 543" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7100++0x07 line.quad 0x00 "GICD_IROUTER544,Interrupt Routing Register 544" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7108++0x07 line.quad 0x00 "GICD_IROUTER545,Interrupt Routing Register 545" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7110++0x07 line.quad 0x00 "GICD_IROUTER546,Interrupt Routing Register 546" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7118++0x07 line.quad 0x00 "GICD_IROUTER547,Interrupt Routing Register 547" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7120++0x07 line.quad 0x00 "GICD_IROUTER548,Interrupt Routing Register 548" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7128++0x07 line.quad 0x00 "GICD_IROUTER549,Interrupt Routing Register 549" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7130++0x07 line.quad 0x00 "GICD_IROUTER550,Interrupt Routing Register 550" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7138++0x07 line.quad 0x00 "GICD_IROUTER551,Interrupt Routing Register 551" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7140++0x07 line.quad 0x00 "GICD_IROUTER552,Interrupt Routing Register 552" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7148++0x07 line.quad 0x00 "GICD_IROUTER553,Interrupt Routing Register 553" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7150++0x07 line.quad 0x00 "GICD_IROUTER554,Interrupt Routing Register 554" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7158++0x07 line.quad 0x00 "GICD_IROUTER555,Interrupt Routing Register 555" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7160++0x07 line.quad 0x00 "GICD_IROUTER556,Interrupt Routing Register 556" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7168++0x07 line.quad 0x00 "GICD_IROUTER557,Interrupt Routing Register 557" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7170++0x07 line.quad 0x00 "GICD_IROUTER558,Interrupt Routing Register 558" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7178++0x07 line.quad 0x00 "GICD_IROUTER559,Interrupt Routing Register 559" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7180++0x07 line.quad 0x00 "GICD_IROUTER560,Interrupt Routing Register 560" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7188++0x07 line.quad 0x00 "GICD_IROUTER561,Interrupt Routing Register 561" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7190++0x07 line.quad 0x00 "GICD_IROUTER562,Interrupt Routing Register 562" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7198++0x07 line.quad 0x00 "GICD_IROUTER563,Interrupt Routing Register 563" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71A0++0x07 line.quad 0x00 "GICD_IROUTER564,Interrupt Routing Register 564" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71A8++0x07 line.quad 0x00 "GICD_IROUTER565,Interrupt Routing Register 565" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71B0++0x07 line.quad 0x00 "GICD_IROUTER566,Interrupt Routing Register 566" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71B8++0x07 line.quad 0x00 "GICD_IROUTER567,Interrupt Routing Register 567" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71C0++0x07 line.quad 0x00 "GICD_IROUTER568,Interrupt Routing Register 568" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71C8++0x07 line.quad 0x00 "GICD_IROUTER569,Interrupt Routing Register 569" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71D0++0x07 line.quad 0x00 "GICD_IROUTER570,Interrupt Routing Register 570" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71D8++0x07 line.quad 0x00 "GICD_IROUTER571,Interrupt Routing Register 571" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71E0++0x07 line.quad 0x00 "GICD_IROUTER572,Interrupt Routing Register 572" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71E8++0x07 line.quad 0x00 "GICD_IROUTER573,Interrupt Routing Register 573" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71F0++0x07 line.quad 0x00 "GICD_IROUTER574,Interrupt Routing Register 574" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71F8++0x07 line.quad 0x00 "GICD_IROUTER575,Interrupt Routing Register 575" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7200++0x07 line.quad 0x00 "GICD_IROUTER576,Interrupt Routing Register 576" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7208++0x07 line.quad 0x00 "GICD_IROUTER577,Interrupt Routing Register 577" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7210++0x07 line.quad 0x00 "GICD_IROUTER578,Interrupt Routing Register 578" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7218++0x07 line.quad 0x00 "GICD_IROUTER579,Interrupt Routing Register 579" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7220++0x07 line.quad 0x00 "GICD_IROUTER580,Interrupt Routing Register 580" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7228++0x07 line.quad 0x00 "GICD_IROUTER581,Interrupt Routing Register 581" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7230++0x07 line.quad 0x00 "GICD_IROUTER582,Interrupt Routing Register 582" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7238++0x07 line.quad 0x00 "GICD_IROUTER583,Interrupt Routing Register 583" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7240++0x07 line.quad 0x00 "GICD_IROUTER584,Interrupt Routing Register 584" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7248++0x07 line.quad 0x00 "GICD_IROUTER585,Interrupt Routing Register 585" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7250++0x07 line.quad 0x00 "GICD_IROUTER586,Interrupt Routing Register 586" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7258++0x07 line.quad 0x00 "GICD_IROUTER587,Interrupt Routing Register 587" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7260++0x07 line.quad 0x00 "GICD_IROUTER588,Interrupt Routing Register 588" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7268++0x07 line.quad 0x00 "GICD_IROUTER589,Interrupt Routing Register 589" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7270++0x07 line.quad 0x00 "GICD_IROUTER590,Interrupt Routing Register 590" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7278++0x07 line.quad 0x00 "GICD_IROUTER591,Interrupt Routing Register 591" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7280++0x07 line.quad 0x00 "GICD_IROUTER592,Interrupt Routing Register 592" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7288++0x07 line.quad 0x00 "GICD_IROUTER593,Interrupt Routing Register 593" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7290++0x07 line.quad 0x00 "GICD_IROUTER594,Interrupt Routing Register 594" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7298++0x07 line.quad 0x00 "GICD_IROUTER595,Interrupt Routing Register 595" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72A0++0x07 line.quad 0x00 "GICD_IROUTER596,Interrupt Routing Register 596" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72A8++0x07 line.quad 0x00 "GICD_IROUTER597,Interrupt Routing Register 597" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72B0++0x07 line.quad 0x00 "GICD_IROUTER598,Interrupt Routing Register 598" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72B8++0x07 line.quad 0x00 "GICD_IROUTER599,Interrupt Routing Register 599" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72C0++0x07 line.quad 0x00 "GICD_IROUTER600,Interrupt Routing Register 600" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72C8++0x07 line.quad 0x00 "GICD_IROUTER601,Interrupt Routing Register 601" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72D0++0x07 line.quad 0x00 "GICD_IROUTER602,Interrupt Routing Register 602" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72D8++0x07 line.quad 0x00 "GICD_IROUTER603,Interrupt Routing Register 603" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72E0++0x07 line.quad 0x00 "GICD_IROUTER604,Interrupt Routing Register 604" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72E8++0x07 line.quad 0x00 "GICD_IROUTER605,Interrupt Routing Register 605" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72F0++0x07 line.quad 0x00 "GICD_IROUTER606,Interrupt Routing Register 606" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72F8++0x07 line.quad 0x00 "GICD_IROUTER607,Interrupt Routing Register 607" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7300++0x07 line.quad 0x00 "GICD_IROUTER608,Interrupt Routing Register 608" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7308++0x07 line.quad 0x00 "GICD_IROUTER609,Interrupt Routing Register 609" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7310++0x07 line.quad 0x00 "GICD_IROUTER610,Interrupt Routing Register 610" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7318++0x07 line.quad 0x00 "GICD_IROUTER611,Interrupt Routing Register 611" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7320++0x07 line.quad 0x00 "GICD_IROUTER612,Interrupt Routing Register 612" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7328++0x07 line.quad 0x00 "GICD_IROUTER613,Interrupt Routing Register 613" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7330++0x07 line.quad 0x00 "GICD_IROUTER614,Interrupt Routing Register 614" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7338++0x07 line.quad 0x00 "GICD_IROUTER615,Interrupt Routing Register 615" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7340++0x07 line.quad 0x00 "GICD_IROUTER616,Interrupt Routing Register 616" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7348++0x07 line.quad 0x00 "GICD_IROUTER617,Interrupt Routing Register 617" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7350++0x07 line.quad 0x00 "GICD_IROUTER618,Interrupt Routing Register 618" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7358++0x07 line.quad 0x00 "GICD_IROUTER619,Interrupt Routing Register 619" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7360++0x07 line.quad 0x00 "GICD_IROUTER620,Interrupt Routing Register 620" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7368++0x07 line.quad 0x00 "GICD_IROUTER621,Interrupt Routing Register 621" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7370++0x07 line.quad 0x00 "GICD_IROUTER622,Interrupt Routing Register 622" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7378++0x07 line.quad 0x00 "GICD_IROUTER623,Interrupt Routing Register 623" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7380++0x07 line.quad 0x00 "GICD_IROUTER624,Interrupt Routing Register 624" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7388++0x07 line.quad 0x00 "GICD_IROUTER625,Interrupt Routing Register 625" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7390++0x07 line.quad 0x00 "GICD_IROUTER626,Interrupt Routing Register 626" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7398++0x07 line.quad 0x00 "GICD_IROUTER627,Interrupt Routing Register 627" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73A0++0x07 line.quad 0x00 "GICD_IROUTER628,Interrupt Routing Register 628" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73A8++0x07 line.quad 0x00 "GICD_IROUTER629,Interrupt Routing Register 629" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73B0++0x07 line.quad 0x00 "GICD_IROUTER630,Interrupt Routing Register 630" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73B8++0x07 line.quad 0x00 "GICD_IROUTER631,Interrupt Routing Register 631" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73C0++0x07 line.quad 0x00 "GICD_IROUTER632,Interrupt Routing Register 632" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73C8++0x07 line.quad 0x00 "GICD_IROUTER633,Interrupt Routing Register 633" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73D0++0x07 line.quad 0x00 "GICD_IROUTER634,Interrupt Routing Register 634" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73D8++0x07 line.quad 0x00 "GICD_IROUTER635,Interrupt Routing Register 635" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73E0++0x07 line.quad 0x00 "GICD_IROUTER636,Interrupt Routing Register 636" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73E8++0x07 line.quad 0x00 "GICD_IROUTER637,Interrupt Routing Register 637" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73F0++0x07 line.quad 0x00 "GICD_IROUTER638,Interrupt Routing Register 638" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73F8++0x07 line.quad 0x00 "GICD_IROUTER639,Interrupt Routing Register 639" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7400++0x07 line.quad 0x00 "GICD_IROUTER640,Interrupt Routing Register 640" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7408++0x07 line.quad 0x00 "GICD_IROUTER641,Interrupt Routing Register 641" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7410++0x07 line.quad 0x00 "GICD_IROUTER642,Interrupt Routing Register 642" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7418++0x07 line.quad 0x00 "GICD_IROUTER643,Interrupt Routing Register 643" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7420++0x07 line.quad 0x00 "GICD_IROUTER644,Interrupt Routing Register 644" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7428++0x07 line.quad 0x00 "GICD_IROUTER645,Interrupt Routing Register 645" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7430++0x07 line.quad 0x00 "GICD_IROUTER646,Interrupt Routing Register 646" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7438++0x07 line.quad 0x00 "GICD_IROUTER647,Interrupt Routing Register 647" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7440++0x07 line.quad 0x00 "GICD_IROUTER648,Interrupt Routing Register 648" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7448++0x07 line.quad 0x00 "GICD_IROUTER649,Interrupt Routing Register 649" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7450++0x07 line.quad 0x00 "GICD_IROUTER650,Interrupt Routing Register 650" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7458++0x07 line.quad 0x00 "GICD_IROUTER651,Interrupt Routing Register 651" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7460++0x07 line.quad 0x00 "GICD_IROUTER652,Interrupt Routing Register 652" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7468++0x07 line.quad 0x00 "GICD_IROUTER653,Interrupt Routing Register 653" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7470++0x07 line.quad 0x00 "GICD_IROUTER654,Interrupt Routing Register 654" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7478++0x07 line.quad 0x00 "GICD_IROUTER655,Interrupt Routing Register 655" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7480++0x07 line.quad 0x00 "GICD_IROUTER656,Interrupt Routing Register 656" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7488++0x07 line.quad 0x00 "GICD_IROUTER657,Interrupt Routing Register 657" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7490++0x07 line.quad 0x00 "GICD_IROUTER658,Interrupt Routing Register 658" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7498++0x07 line.quad 0x00 "GICD_IROUTER659,Interrupt Routing Register 659" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74A0++0x07 line.quad 0x00 "GICD_IROUTER660,Interrupt Routing Register 660" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74A8++0x07 line.quad 0x00 "GICD_IROUTER661,Interrupt Routing Register 661" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74B0++0x07 line.quad 0x00 "GICD_IROUTER662,Interrupt Routing Register 662" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74B8++0x07 line.quad 0x00 "GICD_IROUTER663,Interrupt Routing Register 663" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74C0++0x07 line.quad 0x00 "GICD_IROUTER664,Interrupt Routing Register 664" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74C8++0x07 line.quad 0x00 "GICD_IROUTER665,Interrupt Routing Register 665" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74D0++0x07 line.quad 0x00 "GICD_IROUTER666,Interrupt Routing Register 666" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74D8++0x07 line.quad 0x00 "GICD_IROUTER667,Interrupt Routing Register 667" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74E0++0x07 line.quad 0x00 "GICD_IROUTER668,Interrupt Routing Register 668" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74E8++0x07 line.quad 0x00 "GICD_IROUTER669,Interrupt Routing Register 669" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74F0++0x07 line.quad 0x00 "GICD_IROUTER670,Interrupt Routing Register 670" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74F8++0x07 line.quad 0x00 "GICD_IROUTER671,Interrupt Routing Register 671" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7500++0x07 line.quad 0x00 "GICD_IROUTER672,Interrupt Routing Register 672" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7508++0x07 line.quad 0x00 "GICD_IROUTER673,Interrupt Routing Register 673" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7510++0x07 line.quad 0x00 "GICD_IROUTER674,Interrupt Routing Register 674" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7518++0x07 line.quad 0x00 "GICD_IROUTER675,Interrupt Routing Register 675" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7520++0x07 line.quad 0x00 "GICD_IROUTER676,Interrupt Routing Register 676" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7528++0x07 line.quad 0x00 "GICD_IROUTER677,Interrupt Routing Register 677" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7530++0x07 line.quad 0x00 "GICD_IROUTER678,Interrupt Routing Register 678" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7538++0x07 line.quad 0x00 "GICD_IROUTER679,Interrupt Routing Register 679" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7540++0x07 line.quad 0x00 "GICD_IROUTER680,Interrupt Routing Register 680" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7548++0x07 line.quad 0x00 "GICD_IROUTER681,Interrupt Routing Register 681" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7550++0x07 line.quad 0x00 "GICD_IROUTER682,Interrupt Routing Register 682" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7558++0x07 line.quad 0x00 "GICD_IROUTER683,Interrupt Routing Register 683" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7560++0x07 line.quad 0x00 "GICD_IROUTER684,Interrupt Routing Register 684" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7568++0x07 line.quad 0x00 "GICD_IROUTER685,Interrupt Routing Register 685" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7570++0x07 line.quad 0x00 "GICD_IROUTER686,Interrupt Routing Register 686" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7578++0x07 line.quad 0x00 "GICD_IROUTER687,Interrupt Routing Register 687" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7580++0x07 line.quad 0x00 "GICD_IROUTER688,Interrupt Routing Register 688" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7588++0x07 line.quad 0x00 "GICD_IROUTER689,Interrupt Routing Register 689" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7590++0x07 line.quad 0x00 "GICD_IROUTER690,Interrupt Routing Register 690" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7598++0x07 line.quad 0x00 "GICD_IROUTER691,Interrupt Routing Register 691" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75A0++0x07 line.quad 0x00 "GICD_IROUTER692,Interrupt Routing Register 692" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75A8++0x07 line.quad 0x00 "GICD_IROUTER693,Interrupt Routing Register 693" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75B0++0x07 line.quad 0x00 "GICD_IROUTER694,Interrupt Routing Register 694" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75B8++0x07 line.quad 0x00 "GICD_IROUTER695,Interrupt Routing Register 695" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75C0++0x07 line.quad 0x00 "GICD_IROUTER696,Interrupt Routing Register 696" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75C8++0x07 line.quad 0x00 "GICD_IROUTER697,Interrupt Routing Register 697" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75D0++0x07 line.quad 0x00 "GICD_IROUTER698,Interrupt Routing Register 698" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75D8++0x07 line.quad 0x00 "GICD_IROUTER699,Interrupt Routing Register 699" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75E0++0x07 line.quad 0x00 "GICD_IROUTER700,Interrupt Routing Register 700" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75E8++0x07 line.quad 0x00 "GICD_IROUTER701,Interrupt Routing Register 701" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75F0++0x07 line.quad 0x00 "GICD_IROUTER702,Interrupt Routing Register 702" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75F8++0x07 line.quad 0x00 "GICD_IROUTER703,Interrupt Routing Register 703" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7600++0x07 line.quad 0x00 "GICD_IROUTER704,Interrupt Routing Register 704" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7608++0x07 line.quad 0x00 "GICD_IROUTER705,Interrupt Routing Register 705" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7610++0x07 line.quad 0x00 "GICD_IROUTER706,Interrupt Routing Register 706" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7618++0x07 line.quad 0x00 "GICD_IROUTER707,Interrupt Routing Register 707" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7620++0x07 line.quad 0x00 "GICD_IROUTER708,Interrupt Routing Register 708" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7628++0x07 line.quad 0x00 "GICD_IROUTER709,Interrupt Routing Register 709" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7630++0x07 line.quad 0x00 "GICD_IROUTER710,Interrupt Routing Register 710" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7638++0x07 line.quad 0x00 "GICD_IROUTER711,Interrupt Routing Register 711" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7640++0x07 line.quad 0x00 "GICD_IROUTER712,Interrupt Routing Register 712" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7648++0x07 line.quad 0x00 "GICD_IROUTER713,Interrupt Routing Register 713" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7650++0x07 line.quad 0x00 "GICD_IROUTER714,Interrupt Routing Register 714" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7658++0x07 line.quad 0x00 "GICD_IROUTER715,Interrupt Routing Register 715" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7660++0x07 line.quad 0x00 "GICD_IROUTER716,Interrupt Routing Register 716" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7668++0x07 line.quad 0x00 "GICD_IROUTER717,Interrupt Routing Register 717" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7670++0x07 line.quad 0x00 "GICD_IROUTER718,Interrupt Routing Register 718" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7678++0x07 line.quad 0x00 "GICD_IROUTER719,Interrupt Routing Register 719" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7680++0x07 line.quad 0x00 "GICD_IROUTER720,Interrupt Routing Register 720" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7688++0x07 line.quad 0x00 "GICD_IROUTER721,Interrupt Routing Register 721" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7690++0x07 line.quad 0x00 "GICD_IROUTER722,Interrupt Routing Register 722" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7698++0x07 line.quad 0x00 "GICD_IROUTER723,Interrupt Routing Register 723" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76A0++0x07 line.quad 0x00 "GICD_IROUTER724,Interrupt Routing Register 724" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76A8++0x07 line.quad 0x00 "GICD_IROUTER725,Interrupt Routing Register 725" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76B0++0x07 line.quad 0x00 "GICD_IROUTER726,Interrupt Routing Register 726" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76B8++0x07 line.quad 0x00 "GICD_IROUTER727,Interrupt Routing Register 727" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76C0++0x07 line.quad 0x00 "GICD_IROUTER728,Interrupt Routing Register 728" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76C8++0x07 line.quad 0x00 "GICD_IROUTER729,Interrupt Routing Register 729" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76D0++0x07 line.quad 0x00 "GICD_IROUTER730,Interrupt Routing Register 730" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76D8++0x07 line.quad 0x00 "GICD_IROUTER731,Interrupt Routing Register 731" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76E0++0x07 line.quad 0x00 "GICD_IROUTER732,Interrupt Routing Register 732" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76E8++0x07 line.quad 0x00 "GICD_IROUTER733,Interrupt Routing Register 733" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76F0++0x07 line.quad 0x00 "GICD_IROUTER734,Interrupt Routing Register 734" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76F8++0x07 line.quad 0x00 "GICD_IROUTER735,Interrupt Routing Register 735" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7700++0x07 line.quad 0x00 "GICD_IROUTER736,Interrupt Routing Register 736" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7708++0x07 line.quad 0x00 "GICD_IROUTER737,Interrupt Routing Register 737" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7710++0x07 line.quad 0x00 "GICD_IROUTER738,Interrupt Routing Register 738" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7718++0x07 line.quad 0x00 "GICD_IROUTER739,Interrupt Routing Register 739" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7720++0x07 line.quad 0x00 "GICD_IROUTER740,Interrupt Routing Register 740" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7728++0x07 line.quad 0x00 "GICD_IROUTER741,Interrupt Routing Register 741" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7730++0x07 line.quad 0x00 "GICD_IROUTER742,Interrupt Routing Register 742" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7738++0x07 line.quad 0x00 "GICD_IROUTER743,Interrupt Routing Register 743" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7740++0x07 line.quad 0x00 "GICD_IROUTER744,Interrupt Routing Register 744" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7748++0x07 line.quad 0x00 "GICD_IROUTER745,Interrupt Routing Register 745" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7750++0x07 line.quad 0x00 "GICD_IROUTER746,Interrupt Routing Register 746" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7758++0x07 line.quad 0x00 "GICD_IROUTER747,Interrupt Routing Register 747" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7760++0x07 line.quad 0x00 "GICD_IROUTER748,Interrupt Routing Register 748" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7768++0x07 line.quad 0x00 "GICD_IROUTER749,Interrupt Routing Register 749" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7770++0x07 line.quad 0x00 "GICD_IROUTER750,Interrupt Routing Register 750" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7778++0x07 line.quad 0x00 "GICD_IROUTER751,Interrupt Routing Register 751" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7780++0x07 line.quad 0x00 "GICD_IROUTER752,Interrupt Routing Register 752" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7788++0x07 line.quad 0x00 "GICD_IROUTER753,Interrupt Routing Register 753" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7790++0x07 line.quad 0x00 "GICD_IROUTER754,Interrupt Routing Register 754" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7798++0x07 line.quad 0x00 "GICD_IROUTER755,Interrupt Routing Register 755" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77A0++0x07 line.quad 0x00 "GICD_IROUTER756,Interrupt Routing Register 756" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77A8++0x07 line.quad 0x00 "GICD_IROUTER757,Interrupt Routing Register 757" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77B0++0x07 line.quad 0x00 "GICD_IROUTER758,Interrupt Routing Register 758" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77B8++0x07 line.quad 0x00 "GICD_IROUTER759,Interrupt Routing Register 759" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77C0++0x07 line.quad 0x00 "GICD_IROUTER760,Interrupt Routing Register 760" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77C8++0x07 line.quad 0x00 "GICD_IROUTER761,Interrupt Routing Register 761" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77D0++0x07 line.quad 0x00 "GICD_IROUTER762,Interrupt Routing Register 762" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77D8++0x07 line.quad 0x00 "GICD_IROUTER763,Interrupt Routing Register 763" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77E0++0x07 line.quad 0x00 "GICD_IROUTER764,Interrupt Routing Register 764" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77E8++0x07 line.quad 0x00 "GICD_IROUTER765,Interrupt Routing Register 765" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77F0++0x07 line.quad 0x00 "GICD_IROUTER766,Interrupt Routing Register 766" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77F8++0x07 line.quad 0x00 "GICD_IROUTER767,Interrupt Routing Register 767" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7800++0x07 line.quad 0x00 "GICD_IROUTER768,Interrupt Routing Register 768" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7808++0x07 line.quad 0x00 "GICD_IROUTER769,Interrupt Routing Register 769" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7810++0x07 line.quad 0x00 "GICD_IROUTER770,Interrupt Routing Register 770" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7818++0x07 line.quad 0x00 "GICD_IROUTER771,Interrupt Routing Register 771" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7820++0x07 line.quad 0x00 "GICD_IROUTER772,Interrupt Routing Register 772" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7828++0x07 line.quad 0x00 "GICD_IROUTER773,Interrupt Routing Register 773" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7830++0x07 line.quad 0x00 "GICD_IROUTER774,Interrupt Routing Register 774" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7838++0x07 line.quad 0x00 "GICD_IROUTER775,Interrupt Routing Register 775" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7840++0x07 line.quad 0x00 "GICD_IROUTER776,Interrupt Routing Register 776" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7848++0x07 line.quad 0x00 "GICD_IROUTER777,Interrupt Routing Register 777" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7850++0x07 line.quad 0x00 "GICD_IROUTER778,Interrupt Routing Register 778" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7858++0x07 line.quad 0x00 "GICD_IROUTER779,Interrupt Routing Register 779" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7860++0x07 line.quad 0x00 "GICD_IROUTER780,Interrupt Routing Register 780" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7868++0x07 line.quad 0x00 "GICD_IROUTER781,Interrupt Routing Register 781" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7870++0x07 line.quad 0x00 "GICD_IROUTER782,Interrupt Routing Register 782" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7878++0x07 line.quad 0x00 "GICD_IROUTER783,Interrupt Routing Register 783" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7880++0x07 line.quad 0x00 "GICD_IROUTER784,Interrupt Routing Register 784" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7888++0x07 line.quad 0x00 "GICD_IROUTER785,Interrupt Routing Register 785" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7890++0x07 line.quad 0x00 "GICD_IROUTER786,Interrupt Routing Register 786" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7898++0x07 line.quad 0x00 "GICD_IROUTER787,Interrupt Routing Register 787" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78A0++0x07 line.quad 0x00 "GICD_IROUTER788,Interrupt Routing Register 788" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78A8++0x07 line.quad 0x00 "GICD_IROUTER789,Interrupt Routing Register 789" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78B0++0x07 line.quad 0x00 "GICD_IROUTER790,Interrupt Routing Register 790" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78B8++0x07 line.quad 0x00 "GICD_IROUTER791,Interrupt Routing Register 791" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78C0++0x07 line.quad 0x00 "GICD_IROUTER792,Interrupt Routing Register 792" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78C8++0x07 line.quad 0x00 "GICD_IROUTER793,Interrupt Routing Register 793" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78D0++0x07 line.quad 0x00 "GICD_IROUTER794,Interrupt Routing Register 794" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78D8++0x07 line.quad 0x00 "GICD_IROUTER795,Interrupt Routing Register 795" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78E0++0x07 line.quad 0x00 "GICD_IROUTER796,Interrupt Routing Register 796" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78E8++0x07 line.quad 0x00 "GICD_IROUTER797,Interrupt Routing Register 797" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78F0++0x07 line.quad 0x00 "GICD_IROUTER798,Interrupt Routing Register 798" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78F8++0x07 line.quad 0x00 "GICD_IROUTER799,Interrupt Routing Register 799" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7900++0x07 line.quad 0x00 "GICD_IROUTER800,Interrupt Routing Register 800" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7908++0x07 line.quad 0x00 "GICD_IROUTER801,Interrupt Routing Register 801" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7910++0x07 line.quad 0x00 "GICD_IROUTER802,Interrupt Routing Register 802" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7918++0x07 line.quad 0x00 "GICD_IROUTER803,Interrupt Routing Register 803" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7920++0x07 line.quad 0x00 "GICD_IROUTER804,Interrupt Routing Register 804" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7928++0x07 line.quad 0x00 "GICD_IROUTER805,Interrupt Routing Register 805" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7930++0x07 line.quad 0x00 "GICD_IROUTER806,Interrupt Routing Register 806" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7938++0x07 line.quad 0x00 "GICD_IROUTER807,Interrupt Routing Register 807" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7940++0x07 line.quad 0x00 "GICD_IROUTER808,Interrupt Routing Register 808" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7948++0x07 line.quad 0x00 "GICD_IROUTER809,Interrupt Routing Register 809" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7950++0x07 line.quad 0x00 "GICD_IROUTER810,Interrupt Routing Register 810" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7958++0x07 line.quad 0x00 "GICD_IROUTER811,Interrupt Routing Register 811" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7960++0x07 line.quad 0x00 "GICD_IROUTER812,Interrupt Routing Register 812" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7968++0x07 line.quad 0x00 "GICD_IROUTER813,Interrupt Routing Register 813" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7970++0x07 line.quad 0x00 "GICD_IROUTER814,Interrupt Routing Register 814" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7978++0x07 line.quad 0x00 "GICD_IROUTER815,Interrupt Routing Register 815" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7980++0x07 line.quad 0x00 "GICD_IROUTER816,Interrupt Routing Register 816" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7988++0x07 line.quad 0x00 "GICD_IROUTER817,Interrupt Routing Register 817" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7990++0x07 line.quad 0x00 "GICD_IROUTER818,Interrupt Routing Register 818" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7998++0x07 line.quad 0x00 "GICD_IROUTER819,Interrupt Routing Register 819" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79A0++0x07 line.quad 0x00 "GICD_IROUTER820,Interrupt Routing Register 820" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79A8++0x07 line.quad 0x00 "GICD_IROUTER821,Interrupt Routing Register 821" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79B0++0x07 line.quad 0x00 "GICD_IROUTER822,Interrupt Routing Register 822" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79B8++0x07 line.quad 0x00 "GICD_IROUTER823,Interrupt Routing Register 823" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79C0++0x07 line.quad 0x00 "GICD_IROUTER824,Interrupt Routing Register 824" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79C8++0x07 line.quad 0x00 "GICD_IROUTER825,Interrupt Routing Register 825" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79D0++0x07 line.quad 0x00 "GICD_IROUTER826,Interrupt Routing Register 826" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79D8++0x07 line.quad 0x00 "GICD_IROUTER827,Interrupt Routing Register 827" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79E0++0x07 line.quad 0x00 "GICD_IROUTER828,Interrupt Routing Register 828" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79E8++0x07 line.quad 0x00 "GICD_IROUTER829,Interrupt Routing Register 829" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79F0++0x07 line.quad 0x00 "GICD_IROUTER830,Interrupt Routing Register 830" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79F8++0x07 line.quad 0x00 "GICD_IROUTER831,Interrupt Routing Register 831" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A00++0x07 line.quad 0x00 "GICD_IROUTER832,Interrupt Routing Register 832" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A08++0x07 line.quad 0x00 "GICD_IROUTER833,Interrupt Routing Register 833" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A10++0x07 line.quad 0x00 "GICD_IROUTER834,Interrupt Routing Register 834" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A18++0x07 line.quad 0x00 "GICD_IROUTER835,Interrupt Routing Register 835" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A20++0x07 line.quad 0x00 "GICD_IROUTER836,Interrupt Routing Register 836" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A28++0x07 line.quad 0x00 "GICD_IROUTER837,Interrupt Routing Register 837" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A30++0x07 line.quad 0x00 "GICD_IROUTER838,Interrupt Routing Register 838" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A38++0x07 line.quad 0x00 "GICD_IROUTER839,Interrupt Routing Register 839" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A40++0x07 line.quad 0x00 "GICD_IROUTER840,Interrupt Routing Register 840" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A48++0x07 line.quad 0x00 "GICD_IROUTER841,Interrupt Routing Register 841" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A50++0x07 line.quad 0x00 "GICD_IROUTER842,Interrupt Routing Register 842" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A58++0x07 line.quad 0x00 "GICD_IROUTER843,Interrupt Routing Register 843" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A60++0x07 line.quad 0x00 "GICD_IROUTER844,Interrupt Routing Register 844" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A68++0x07 line.quad 0x00 "GICD_IROUTER845,Interrupt Routing Register 845" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A70++0x07 line.quad 0x00 "GICD_IROUTER846,Interrupt Routing Register 846" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A78++0x07 line.quad 0x00 "GICD_IROUTER847,Interrupt Routing Register 847" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A80++0x07 line.quad 0x00 "GICD_IROUTER848,Interrupt Routing Register 848" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A88++0x07 line.quad 0x00 "GICD_IROUTER849,Interrupt Routing Register 849" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A90++0x07 line.quad 0x00 "GICD_IROUTER850,Interrupt Routing Register 850" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A98++0x07 line.quad 0x00 "GICD_IROUTER851,Interrupt Routing Register 851" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AA0++0x07 line.quad 0x00 "GICD_IROUTER852,Interrupt Routing Register 852" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AA8++0x07 line.quad 0x00 "GICD_IROUTER853,Interrupt Routing Register 853" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AB0++0x07 line.quad 0x00 "GICD_IROUTER854,Interrupt Routing Register 854" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AB8++0x07 line.quad 0x00 "GICD_IROUTER855,Interrupt Routing Register 855" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AC0++0x07 line.quad 0x00 "GICD_IROUTER856,Interrupt Routing Register 856" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AC8++0x07 line.quad 0x00 "GICD_IROUTER857,Interrupt Routing Register 857" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AD0++0x07 line.quad 0x00 "GICD_IROUTER858,Interrupt Routing Register 858" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AD8++0x07 line.quad 0x00 "GICD_IROUTER859,Interrupt Routing Register 859" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AE0++0x07 line.quad 0x00 "GICD_IROUTER860,Interrupt Routing Register 860" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AE8++0x07 line.quad 0x00 "GICD_IROUTER861,Interrupt Routing Register 861" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AF0++0x07 line.quad 0x00 "GICD_IROUTER862,Interrupt Routing Register 862" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AF8++0x07 line.quad 0x00 "GICD_IROUTER863,Interrupt Routing Register 863" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B00++0x07 line.quad 0x00 "GICD_IROUTER864,Interrupt Routing Register 864" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B08++0x07 line.quad 0x00 "GICD_IROUTER865,Interrupt Routing Register 865" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B10++0x07 line.quad 0x00 "GICD_IROUTER866,Interrupt Routing Register 866" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B18++0x07 line.quad 0x00 "GICD_IROUTER867,Interrupt Routing Register 867" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B20++0x07 line.quad 0x00 "GICD_IROUTER868,Interrupt Routing Register 868" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B28++0x07 line.quad 0x00 "GICD_IROUTER869,Interrupt Routing Register 869" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B30++0x07 line.quad 0x00 "GICD_IROUTER870,Interrupt Routing Register 870" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B38++0x07 line.quad 0x00 "GICD_IROUTER871,Interrupt Routing Register 871" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B40++0x07 line.quad 0x00 "GICD_IROUTER872,Interrupt Routing Register 872" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B48++0x07 line.quad 0x00 "GICD_IROUTER873,Interrupt Routing Register 873" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B50++0x07 line.quad 0x00 "GICD_IROUTER874,Interrupt Routing Register 874" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B58++0x07 line.quad 0x00 "GICD_IROUTER875,Interrupt Routing Register 875" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B60++0x07 line.quad 0x00 "GICD_IROUTER876,Interrupt Routing Register 876" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B68++0x07 line.quad 0x00 "GICD_IROUTER877,Interrupt Routing Register 877" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B70++0x07 line.quad 0x00 "GICD_IROUTER878,Interrupt Routing Register 878" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B78++0x07 line.quad 0x00 "GICD_IROUTER879,Interrupt Routing Register 879" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B80++0x07 line.quad 0x00 "GICD_IROUTER880,Interrupt Routing Register 880" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B88++0x07 line.quad 0x00 "GICD_IROUTER881,Interrupt Routing Register 881" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B90++0x07 line.quad 0x00 "GICD_IROUTER882,Interrupt Routing Register 882" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B98++0x07 line.quad 0x00 "GICD_IROUTER883,Interrupt Routing Register 883" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BA0++0x07 line.quad 0x00 "GICD_IROUTER884,Interrupt Routing Register 884" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BA8++0x07 line.quad 0x00 "GICD_IROUTER885,Interrupt Routing Register 885" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BB0++0x07 line.quad 0x00 "GICD_IROUTER886,Interrupt Routing Register 886" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BB8++0x07 line.quad 0x00 "GICD_IROUTER887,Interrupt Routing Register 887" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BC0++0x07 line.quad 0x00 "GICD_IROUTER888,Interrupt Routing Register 888" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BC8++0x07 line.quad 0x00 "GICD_IROUTER889,Interrupt Routing Register 889" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BD0++0x07 line.quad 0x00 "GICD_IROUTER890,Interrupt Routing Register 890" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BD8++0x07 line.quad 0x00 "GICD_IROUTER891,Interrupt Routing Register 891" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BE0++0x07 line.quad 0x00 "GICD_IROUTER892,Interrupt Routing Register 892" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BE8++0x07 line.quad 0x00 "GICD_IROUTER893,Interrupt Routing Register 893" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BF0++0x07 line.quad 0x00 "GICD_IROUTER894,Interrupt Routing Register 894" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BF8++0x07 line.quad 0x00 "GICD_IROUTER895,Interrupt Routing Register 895" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C00++0x07 line.quad 0x00 "GICD_IROUTER896,Interrupt Routing Register 896" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C08++0x07 line.quad 0x00 "GICD_IROUTER897,Interrupt Routing Register 897" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C10++0x07 line.quad 0x00 "GICD_IROUTER898,Interrupt Routing Register 898" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C18++0x07 line.quad 0x00 "GICD_IROUTER899,Interrupt Routing Register 899" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C20++0x07 line.quad 0x00 "GICD_IROUTER900,Interrupt Routing Register 900" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C28++0x07 line.quad 0x00 "GICD_IROUTER901,Interrupt Routing Register 901" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C30++0x07 line.quad 0x00 "GICD_IROUTER902,Interrupt Routing Register 902" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C38++0x07 line.quad 0x00 "GICD_IROUTER903,Interrupt Routing Register 903" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C40++0x07 line.quad 0x00 "GICD_IROUTER904,Interrupt Routing Register 904" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C48++0x07 line.quad 0x00 "GICD_IROUTER905,Interrupt Routing Register 905" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C50++0x07 line.quad 0x00 "GICD_IROUTER906,Interrupt Routing Register 906" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C58++0x07 line.quad 0x00 "GICD_IROUTER907,Interrupt Routing Register 907" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C60++0x07 line.quad 0x00 "GICD_IROUTER908,Interrupt Routing Register 908" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C68++0x07 line.quad 0x00 "GICD_IROUTER909,Interrupt Routing Register 909" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C70++0x07 line.quad 0x00 "GICD_IROUTER910,Interrupt Routing Register 910" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C78++0x07 line.quad 0x00 "GICD_IROUTER911,Interrupt Routing Register 911" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C80++0x07 line.quad 0x00 "GICD_IROUTER912,Interrupt Routing Register 912" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C88++0x07 line.quad 0x00 "GICD_IROUTER913,Interrupt Routing Register 913" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C90++0x07 line.quad 0x00 "GICD_IROUTER914,Interrupt Routing Register 914" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C98++0x07 line.quad 0x00 "GICD_IROUTER915,Interrupt Routing Register 915" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CA0++0x07 line.quad 0x00 "GICD_IROUTER916,Interrupt Routing Register 916" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CA8++0x07 line.quad 0x00 "GICD_IROUTER917,Interrupt Routing Register 917" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CB0++0x07 line.quad 0x00 "GICD_IROUTER918,Interrupt Routing Register 918" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CB8++0x07 line.quad 0x00 "GICD_IROUTER919,Interrupt Routing Register 919" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CC0++0x07 line.quad 0x00 "GICD_IROUTER920,Interrupt Routing Register 920" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CC8++0x07 line.quad 0x00 "GICD_IROUTER921,Interrupt Routing Register 921" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CD0++0x07 line.quad 0x00 "GICD_IROUTER922,Interrupt Routing Register 922" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CD8++0x07 line.quad 0x00 "GICD_IROUTER923,Interrupt Routing Register 923" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CE0++0x07 line.quad 0x00 "GICD_IROUTER924,Interrupt Routing Register 924" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CE8++0x07 line.quad 0x00 "GICD_IROUTER925,Interrupt Routing Register 925" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CF0++0x07 line.quad 0x00 "GICD_IROUTER926,Interrupt Routing Register 926" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CF8++0x07 line.quad 0x00 "GICD_IROUTER927,Interrupt Routing Register 927" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D00++0x07 line.quad 0x00 "GICD_IROUTER928,Interrupt Routing Register 928" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D08++0x07 line.quad 0x00 "GICD_IROUTER929,Interrupt Routing Register 929" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D10++0x07 line.quad 0x00 "GICD_IROUTER930,Interrupt Routing Register 930" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D18++0x07 line.quad 0x00 "GICD_IROUTER931,Interrupt Routing Register 931" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D20++0x07 line.quad 0x00 "GICD_IROUTER932,Interrupt Routing Register 932" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D28++0x07 line.quad 0x00 "GICD_IROUTER933,Interrupt Routing Register 933" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D30++0x07 line.quad 0x00 "GICD_IROUTER934,Interrupt Routing Register 934" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D38++0x07 line.quad 0x00 "GICD_IROUTER935,Interrupt Routing Register 935" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D40++0x07 line.quad 0x00 "GICD_IROUTER936,Interrupt Routing Register 936" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D48++0x07 line.quad 0x00 "GICD_IROUTER937,Interrupt Routing Register 937" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D50++0x07 line.quad 0x00 "GICD_IROUTER938,Interrupt Routing Register 938" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D58++0x07 line.quad 0x00 "GICD_IROUTER939,Interrupt Routing Register 939" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D60++0x07 line.quad 0x00 "GICD_IROUTER940,Interrupt Routing Register 940" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D68++0x07 line.quad 0x00 "GICD_IROUTER941,Interrupt Routing Register 941" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D70++0x07 line.quad 0x00 "GICD_IROUTER942,Interrupt Routing Register 942" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D78++0x07 line.quad 0x00 "GICD_IROUTER943,Interrupt Routing Register 943" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D80++0x07 line.quad 0x00 "GICD_IROUTER944,Interrupt Routing Register 944" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D88++0x07 line.quad 0x00 "GICD_IROUTER945,Interrupt Routing Register 945" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D90++0x07 line.quad 0x00 "GICD_IROUTER946,Interrupt Routing Register 946" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D98++0x07 line.quad 0x00 "GICD_IROUTER947,Interrupt Routing Register 947" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DA0++0x07 line.quad 0x00 "GICD_IROUTER948,Interrupt Routing Register 948" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DA8++0x07 line.quad 0x00 "GICD_IROUTER949,Interrupt Routing Register 949" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DB0++0x07 line.quad 0x00 "GICD_IROUTER950,Interrupt Routing Register 950" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DB8++0x07 line.quad 0x00 "GICD_IROUTER951,Interrupt Routing Register 951" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DC0++0x07 line.quad 0x00 "GICD_IROUTER952,Interrupt Routing Register 952" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DC8++0x07 line.quad 0x00 "GICD_IROUTER953,Interrupt Routing Register 953" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DD0++0x07 line.quad 0x00 "GICD_IROUTER954,Interrupt Routing Register 954" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DD8++0x07 line.quad 0x00 "GICD_IROUTER955,Interrupt Routing Register 955" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DE0++0x07 line.quad 0x00 "GICD_IROUTER956,Interrupt Routing Register 956" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DE8++0x07 line.quad 0x00 "GICD_IROUTER957,Interrupt Routing Register 957" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DF0++0x07 line.quad 0x00 "GICD_IROUTER958,Interrupt Routing Register 958" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DF8++0x07 line.quad 0x00 "GICD_IROUTER959,Interrupt Routing Register 959" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E00++0x07 line.quad 0x00 "GICD_IROUTER960,Interrupt Routing Register 960" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E08++0x07 line.quad 0x00 "GICD_IROUTER961,Interrupt Routing Register 961" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E10++0x07 line.quad 0x00 "GICD_IROUTER962,Interrupt Routing Register 962" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E18++0x07 line.quad 0x00 "GICD_IROUTER963,Interrupt Routing Register 963" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E20++0x07 line.quad 0x00 "GICD_IROUTER964,Interrupt Routing Register 964" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E28++0x07 line.quad 0x00 "GICD_IROUTER965,Interrupt Routing Register 965" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E30++0x07 line.quad 0x00 "GICD_IROUTER966,Interrupt Routing Register 966" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E38++0x07 line.quad 0x00 "GICD_IROUTER967,Interrupt Routing Register 967" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E40++0x07 line.quad 0x00 "GICD_IROUTER968,Interrupt Routing Register 968" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E48++0x07 line.quad 0x00 "GICD_IROUTER969,Interrupt Routing Register 969" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E50++0x07 line.quad 0x00 "GICD_IROUTER970,Interrupt Routing Register 970" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E58++0x07 line.quad 0x00 "GICD_IROUTER971,Interrupt Routing Register 971" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E60++0x07 line.quad 0x00 "GICD_IROUTER972,Interrupt Routing Register 972" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E68++0x07 line.quad 0x00 "GICD_IROUTER973,Interrupt Routing Register 973" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E70++0x07 line.quad 0x00 "GICD_IROUTER974,Interrupt Routing Register 974" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E78++0x07 line.quad 0x00 "GICD_IROUTER975,Interrupt Routing Register 975" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E80++0x07 line.quad 0x00 "GICD_IROUTER976,Interrupt Routing Register 976" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E88++0x07 line.quad 0x00 "GICD_IROUTER977,Interrupt Routing Register 977" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E90++0x07 line.quad 0x00 "GICD_IROUTER978,Interrupt Routing Register 978" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E98++0x07 line.quad 0x00 "GICD_IROUTER979,Interrupt Routing Register 979" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EA0++0x07 line.quad 0x00 "GICD_IROUTER980,Interrupt Routing Register 980" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EA8++0x07 line.quad 0x00 "GICD_IROUTER981,Interrupt Routing Register 981" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EB0++0x07 line.quad 0x00 "GICD_IROUTER982,Interrupt Routing Register 982" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EB8++0x07 line.quad 0x00 "GICD_IROUTER983,Interrupt Routing Register 983" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EC0++0x07 line.quad 0x00 "GICD_IROUTER984,Interrupt Routing Register 984" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EC8++0x07 line.quad 0x00 "GICD_IROUTER985,Interrupt Routing Register 985" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7ED0++0x07 line.quad 0x00 "GICD_IROUTER986,Interrupt Routing Register 986" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7ED8++0x07 line.quad 0x00 "GICD_IROUTER987,Interrupt Routing Register 987" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EE0++0x07 line.quad 0x00 "GICD_IROUTER988,Interrupt Routing Register 988" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EE8++0x07 line.quad 0x00 "GICD_IROUTER989,Interrupt Routing Register 989" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EF0++0x07 line.quad 0x00 "GICD_IROUTER990,Interrupt Routing Register 990" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EF8++0x07 line.quad 0x00 "GICD_IROUTER991,Interrupt Routing Register 991" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" tree.end width 22. tree "Implementation Defined Test Registers" rgroup.long 0xC000++0x03 line.long 0x00 "GICD_ESTATUSR,GICD_ESTATUSR" bitfld.long 0x00 31. " SRWP ,Super Register Write Pending" "Not pending,Pending" wgroup.long 0xC004++0x03 line.long 0x00 "GICD_ERRTESTR,Error Test Register" bitfld.long 0x00 1. " AXIM_ERR ,Drives the axim_err pin to 0b1 for 1 cycle" "Low,High" bitfld.long 0x00 0. " ECC_FATAL ,Drives the ecc_fatal pin to 0b1 for 1 cycle" "Low,High" textline " " if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) rgroup.long 0xC084++0x03 line.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0" bitfld.long 0x00 31. " SPIS63 ,SPI Status Bit 63" "Low,High" bitfld.long 0x00 30. " SPIS62 ,SPI Status Bit 62" "Low,High" bitfld.long 0x00 29. " SPIS61 ,SPI Status Bit 61" "Low,High" textline " " bitfld.long 0x00 28. " SPIS60 ,SPI Status Bit 60" "Low,High" bitfld.long 0x00 27. " SPIS59 ,SPI Status Bit 59" "Low,High" bitfld.long 0x00 26. " SPIS58 ,SPI Status Bit 58" "Low,High" textline " " bitfld.long 0x00 25. " SPIS57 ,SPI Status Bit 57" "Low,High" bitfld.long 0x00 24. " SPIS56 ,SPI Status Bit 56" "Low,High" bitfld.long 0x00 23. " SPIS55 ,SPI Status Bit 55" "Low,High" textline " " bitfld.long 0x00 22. " SPIS54 ,SPI Status Bit 54" "Low,High" bitfld.long 0x00 21. " SPIS53 ,SPI Status Bit 53" "Low,High" bitfld.long 0x00 20. " SPIS52 ,SPI Status Bit 52" "Low,High" textline " " bitfld.long 0x00 19. " SPIS51 ,SPI Status Bit 51" "Low,High" bitfld.long 0x00 18. " SPIS50 ,SPI Status Bit 50" "Low,High" bitfld.long 0x00 17. " SPIS49 ,SPI Status Bit 49" "Low,High" textline " " bitfld.long 0x00 16. " SPIS48 ,SPI Status Bit 48" "Low,High" bitfld.long 0x00 15. " SPIS47 ,SPI Status Bit 47" "Low,High" bitfld.long 0x00 14. " SPIS46 ,SPI Status Bit 46" "Low,High" textline " " bitfld.long 0x00 13. " SPIS45 ,SPI Status Bit 45" "Low,High" bitfld.long 0x00 12. " SPIS44 ,SPI Status Bit 44" "Low,High" bitfld.long 0x00 11. " SPIS43 ,SPI Status Bit 43" "Low,High" textline " " bitfld.long 0x00 10. " SPIS42 ,SPI Status Bit 42" "Low,High" bitfld.long 0x00 9. " SPIS41 ,SPI Status Bit 41" "Low,High" bitfld.long 0x00 8. " SPIS40 ,SPI Status Bit 40" "Low,High" textline " " bitfld.long 0x00 7. " SPIS39 ,SPI Status Bit 39" "Low,High" bitfld.long 0x00 6. " SPIS38 ,SPI Status Bit 38" "Low,High" bitfld.long 0x00 5. " SPIS37 ,SPI Status Bit 37" "Low,High" textline " " bitfld.long 0x00 4. " SPIS36 ,SPI Status Bit 36" "Low,High" bitfld.long 0x00 3. " SPIS35 ,SPI Status Bit 35" "Low,High" bitfld.long 0x00 2. " SPIS34 ,SPI Status Bit 34" "Low,High" textline " " bitfld.long 0x00 1. " SPIS33 ,SPI Status Bit 33" "Low,High" bitfld.long 0x00 0. " SPIS32 ,SPI Status Bit 32" "Low,High" else hgroup.long 0xC084++0x03 hide.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) rgroup.long 0xC088++0x03 line.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1" bitfld.long 0x00 31. " SPIS95 ,SPI Status Bit 95" "Low,High" bitfld.long 0x00 30. " SPIS94 ,SPI Status Bit 94" "Low,High" bitfld.long 0x00 29. " SPIS93 ,SPI Status Bit 93" "Low,High" textline " " bitfld.long 0x00 28. " SPIS92 ,SPI Status Bit 92" "Low,High" bitfld.long 0x00 27. " SPIS91 ,SPI Status Bit 91" "Low,High" bitfld.long 0x00 26. " SPIS90 ,SPI Status Bit 90" "Low,High" textline " " bitfld.long 0x00 25. " SPIS89 ,SPI Status Bit 89" "Low,High" bitfld.long 0x00 24. " SPIS88 ,SPI Status Bit 88" "Low,High" bitfld.long 0x00 23. " SPIS87 ,SPI Status Bit 87" "Low,High" textline " " bitfld.long 0x00 22. " SPIS86 ,SPI Status Bit 86" "Low,High" bitfld.long 0x00 21. " SPIS85 ,SPI Status Bit 85" "Low,High" bitfld.long 0x00 20. " SPIS84 ,SPI Status Bit 84" "Low,High" textline " " bitfld.long 0x00 19. " SPIS83 ,SPI Status Bit 83" "Low,High" bitfld.long 0x00 18. " SPIS82 ,SPI Status Bit 82" "Low,High" bitfld.long 0x00 17. " SPIS81 ,SPI Status Bit 81" "Low,High" textline " " bitfld.long 0x00 16. " SPIS80 ,SPI Status Bit 80" "Low,High" bitfld.long 0x00 15. " SPIS79 ,SPI Status Bit 79" "Low,High" bitfld.long 0x00 14. " SPIS78 ,SPI Status Bit 78" "Low,High" textline " " bitfld.long 0x00 13. " SPIS77 ,SPI Status Bit 77" "Low,High" bitfld.long 0x00 12. " SPIS76 ,SPI Status Bit 76" "Low,High" bitfld.long 0x00 11. " SPIS75 ,SPI Status Bit 75" "Low,High" textline " " bitfld.long 0x00 10. " SPIS74 ,SPI Status Bit 74" "Low,High" bitfld.long 0x00 9. " SPIS73 ,SPI Status Bit 73" "Low,High" bitfld.long 0x00 8. " SPIS72 ,SPI Status Bit 72" "Low,High" textline " " bitfld.long 0x00 7. " SPIS71 ,SPI Status Bit 71" "Low,High" bitfld.long 0x00 6. " SPIS70 ,SPI Status Bit 70" "Low,High" bitfld.long 0x00 5. " SPIS69 ,SPI Status Bit 69" "Low,High" textline " " bitfld.long 0x00 4. " SPIS68 ,SPI Status Bit 68" "Low,High" bitfld.long 0x00 3. " SPIS67 ,SPI Status Bit 67" "Low,High" bitfld.long 0x00 2. " SPIS66 ,SPI Status Bit 66" "Low,High" textline " " bitfld.long 0x00 1. " SPIS65 ,SPI Status Bit 65" "Low,High" bitfld.long 0x00 0. " SPIS64 ,SPI Status Bit 64" "Low,High" else hgroup.long 0xC088++0x03 hide.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) rgroup.long 0xC08C++0x03 line.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2" bitfld.long 0x00 31. " SPIS127 ,SPI Status Bit 127" "Low,High" bitfld.long 0x00 30. " SPIS126 ,SPI Status Bit 126" "Low,High" bitfld.long 0x00 29. " SPIS125 ,SPI Status Bit 125" "Low,High" textline " " bitfld.long 0x00 28. " SPIS124 ,SPI Status Bit 124" "Low,High" bitfld.long 0x00 27. " SPIS123 ,SPI Status Bit 123" "Low,High" bitfld.long 0x00 26. " SPIS122 ,SPI Status Bit 122" "Low,High" textline " " bitfld.long 0x00 25. " SPIS121 ,SPI Status Bit 121" "Low,High" bitfld.long 0x00 24. " SPIS120 ,SPI Status Bit 120" "Low,High" bitfld.long 0x00 23. " SPIS119 ,SPI Status Bit 119" "Low,High" textline " " bitfld.long 0x00 22. " SPIS118 ,SPI Status Bit 118" "Low,High" bitfld.long 0x00 21. " SPIS117 ,SPI Status Bit 117" "Low,High" bitfld.long 0x00 20. " SPIS116 ,SPI Status Bit 116" "Low,High" textline " " bitfld.long 0x00 19. " SPIS115 ,SPI Status Bit 115" "Low,High" bitfld.long 0x00 18. " SPIS114 ,SPI Status Bit 114" "Low,High" bitfld.long 0x00 17. " SPIS113 ,SPI Status Bit 113" "Low,High" textline " " bitfld.long 0x00 16. " SPIS112 ,SPI Status Bit 112" "Low,High" bitfld.long 0x00 15. " SPIS111 ,SPI Status Bit 111" "Low,High" bitfld.long 0x00 14. " SPIS110 ,SPI Status Bit 110" "Low,High" textline " " bitfld.long 0x00 13. " SPIS109 ,SPI Status Bit 109" "Low,High" bitfld.long 0x00 12. " SPIS108 ,SPI Status Bit 108" "Low,High" bitfld.long 0x00 11. " SPIS107 ,SPI Status Bit 107" "Low,High" textline " " bitfld.long 0x00 10. " SPIS106 ,SPI Status Bit 106" "Low,High" bitfld.long 0x00 9. " SPIS105 ,SPI Status Bit 105" "Low,High" bitfld.long 0x00 8. " SPIS104 ,SPI Status Bit 104" "Low,High" textline " " bitfld.long 0x00 7. " SPIS103 ,SPI Status Bit 103" "Low,High" bitfld.long 0x00 6. " SPIS102 ,SPI Status Bit 102" "Low,High" bitfld.long 0x00 5. " SPIS101 ,SPI Status Bit 101" "Low,High" textline " " bitfld.long 0x00 4. " SPIS100 ,SPI Status Bit 100" "Low,High" bitfld.long 0x00 3. " SPIS99 ,SPI Status Bit 99" "Low,High" bitfld.long 0x00 2. " SPIS98 ,SPI Status Bit 98" "Low,High" textline " " bitfld.long 0x00 1. " SPIS97 ,SPI Status Bit 97" "Low,High" bitfld.long 0x00 0. " SPIS96 ,SPI Status Bit 96" "Low,High" else hgroup.long 0xC08C++0x03 hide.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) rgroup.long 0xC090++0x03 line.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3" bitfld.long 0x00 31. " SPIS159 ,SPI Status Bit 159" "Low,High" bitfld.long 0x00 30. " SPIS158 ,SPI Status Bit 158" "Low,High" bitfld.long 0x00 29. " SPIS157 ,SPI Status Bit 157" "Low,High" textline " " bitfld.long 0x00 28. " SPIS156 ,SPI Status Bit 156" "Low,High" bitfld.long 0x00 27. " SPIS155 ,SPI Status Bit 155" "Low,High" bitfld.long 0x00 26. " SPIS154 ,SPI Status Bit 154" "Low,High" textline " " bitfld.long 0x00 25. " SPIS153 ,SPI Status Bit 153" "Low,High" bitfld.long 0x00 24. " SPIS152 ,SPI Status Bit 152" "Low,High" bitfld.long 0x00 23. " SPIS151 ,SPI Status Bit 151" "Low,High" textline " " bitfld.long 0x00 22. " SPIS150 ,SPI Status Bit 150" "Low,High" bitfld.long 0x00 21. " SPIS149 ,SPI Status Bit 149" "Low,High" bitfld.long 0x00 20. " SPIS148 ,SPI Status Bit 148" "Low,High" textline " " bitfld.long 0x00 19. " SPIS147 ,SPI Status Bit 147" "Low,High" bitfld.long 0x00 18. " SPIS146 ,SPI Status Bit 146" "Low,High" bitfld.long 0x00 17. " SPIS145 ,SPI Status Bit 145" "Low,High" textline " " bitfld.long 0x00 16. " SPIS144 ,SPI Status Bit 144" "Low,High" bitfld.long 0x00 15. " SPIS143 ,SPI Status Bit 143" "Low,High" bitfld.long 0x00 14. " SPIS142 ,SPI Status Bit 142" "Low,High" textline " " bitfld.long 0x00 13. " SPIS141 ,SPI Status Bit 141" "Low,High" bitfld.long 0x00 12. " SPIS140 ,SPI Status Bit 140" "Low,High" bitfld.long 0x00 11. " SPIS139 ,SPI Status Bit 139" "Low,High" textline " " bitfld.long 0x00 10. " SPIS138 ,SPI Status Bit 138" "Low,High" bitfld.long 0x00 9. " SPIS137 ,SPI Status Bit 137" "Low,High" bitfld.long 0x00 8. " SPIS136 ,SPI Status Bit 136" "Low,High" textline " " bitfld.long 0x00 7. " SPIS135 ,SPI Status Bit 135" "Low,High" bitfld.long 0x00 6. " SPIS134 ,SPI Status Bit 134" "Low,High" bitfld.long 0x00 5. " SPIS133 ,SPI Status Bit 133" "Low,High" textline " " bitfld.long 0x00 4. " SPIS132 ,SPI Status Bit 132" "Low,High" bitfld.long 0x00 3. " SPIS131 ,SPI Status Bit 131" "Low,High" bitfld.long 0x00 2. " SPIS130 ,SPI Status Bit 130" "Low,High" textline " " bitfld.long 0x00 1. " SPIS129 ,SPI Status Bit 129" "Low,High" bitfld.long 0x00 0. " SPIS128 ,SPI Status Bit 128" "Low,High" else hgroup.long 0xC090++0x03 hide.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) rgroup.long 0xC094++0x03 line.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4" bitfld.long 0x00 31. " SPIS191 ,SPI Status Bit 191" "Low,High" bitfld.long 0x00 30. " SPIS190 ,SPI Status Bit 190" "Low,High" bitfld.long 0x00 29. " SPIS189 ,SPI Status Bit 189" "Low,High" textline " " bitfld.long 0x00 28. " SPIS188 ,SPI Status Bit 188" "Low,High" bitfld.long 0x00 27. " SPIS187 ,SPI Status Bit 187" "Low,High" bitfld.long 0x00 26. " SPIS186 ,SPI Status Bit 186" "Low,High" textline " " bitfld.long 0x00 25. " SPIS185 ,SPI Status Bit 185" "Low,High" bitfld.long 0x00 24. " SPIS184 ,SPI Status Bit 184" "Low,High" bitfld.long 0x00 23. " SPIS183 ,SPI Status Bit 183" "Low,High" textline " " bitfld.long 0x00 22. " SPIS182 ,SPI Status Bit 182" "Low,High" bitfld.long 0x00 21. " SPIS181 ,SPI Status Bit 181" "Low,High" bitfld.long 0x00 20. " SPIS180 ,SPI Status Bit 180" "Low,High" textline " " bitfld.long 0x00 19. " SPIS179 ,SPI Status Bit 179" "Low,High" bitfld.long 0x00 18. " SPIS178 ,SPI Status Bit 178" "Low,High" bitfld.long 0x00 17. " SPIS177 ,SPI Status Bit 177" "Low,High" textline " " bitfld.long 0x00 16. " SPIS176 ,SPI Status Bit 176" "Low,High" bitfld.long 0x00 15. " SPIS175 ,SPI Status Bit 175" "Low,High" bitfld.long 0x00 14. " SPIS174 ,SPI Status Bit 174" "Low,High" textline " " bitfld.long 0x00 13. " SPIS173 ,SPI Status Bit 173" "Low,High" bitfld.long 0x00 12. " SPIS172 ,SPI Status Bit 172" "Low,High" bitfld.long 0x00 11. " SPIS171 ,SPI Status Bit 171" "Low,High" textline " " bitfld.long 0x00 10. " SPIS170 ,SPI Status Bit 170" "Low,High" bitfld.long 0x00 9. " SPIS169 ,SPI Status Bit 169" "Low,High" bitfld.long 0x00 8. " SPIS168 ,SPI Status Bit 168" "Low,High" textline " " bitfld.long 0x00 7. " SPIS167 ,SPI Status Bit 167" "Low,High" bitfld.long 0x00 6. " SPIS166 ,SPI Status Bit 166" "Low,High" bitfld.long 0x00 5. " SPIS165 ,SPI Status Bit 165" "Low,High" textline " " bitfld.long 0x00 4. " SPIS164 ,SPI Status Bit 164" "Low,High" bitfld.long 0x00 3. " SPIS163 ,SPI Status Bit 163" "Low,High" bitfld.long 0x00 2. " SPIS162 ,SPI Status Bit 162" "Low,High" textline " " bitfld.long 0x00 1. " SPIS161 ,SPI Status Bit 161" "Low,High" bitfld.long 0x00 0. " SPIS160 ,SPI Status Bit 160" "Low,High" else hgroup.long 0xC094++0x03 hide.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) rgroup.long 0xC098++0x03 line.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5" bitfld.long 0x00 31. " SPIS223 ,SPI Status Bit 223" "Low,High" bitfld.long 0x00 30. " SPIS222 ,SPI Status Bit 222" "Low,High" bitfld.long 0x00 29. " SPIS221 ,SPI Status Bit 221" "Low,High" textline " " bitfld.long 0x00 28. " SPIS220 ,SPI Status Bit 220" "Low,High" bitfld.long 0x00 27. " SPIS219 ,SPI Status Bit 219" "Low,High" bitfld.long 0x00 26. " SPIS218 ,SPI Status Bit 218" "Low,High" textline " " bitfld.long 0x00 25. " SPIS217 ,SPI Status Bit 217" "Low,High" bitfld.long 0x00 24. " SPIS216 ,SPI Status Bit 216" "Low,High" bitfld.long 0x00 23. " SPIS215 ,SPI Status Bit 215" "Low,High" textline " " bitfld.long 0x00 22. " SPIS214 ,SPI Status Bit 214" "Low,High" bitfld.long 0x00 21. " SPIS213 ,SPI Status Bit 213" "Low,High" bitfld.long 0x00 20. " SPIS212 ,SPI Status Bit 212" "Low,High" textline " " bitfld.long 0x00 19. " SPIS211 ,SPI Status Bit 211" "Low,High" bitfld.long 0x00 18. " SPIS210 ,SPI Status Bit 210" "Low,High" bitfld.long 0x00 17. " SPIS209 ,SPI Status Bit 209" "Low,High" textline " " bitfld.long 0x00 16. " SPIS208 ,SPI Status Bit 208" "Low,High" bitfld.long 0x00 15. " SPIS207 ,SPI Status Bit 207" "Low,High" bitfld.long 0x00 14. " SPIS206 ,SPI Status Bit 206" "Low,High" textline " " bitfld.long 0x00 13. " SPIS205 ,SPI Status Bit 205" "Low,High" bitfld.long 0x00 12. " SPIS204 ,SPI Status Bit 204" "Low,High" bitfld.long 0x00 11. " SPIS203 ,SPI Status Bit 203" "Low,High" textline " " bitfld.long 0x00 10. " SPIS202 ,SPI Status Bit 202" "Low,High" bitfld.long 0x00 9. " SPIS201 ,SPI Status Bit 201" "Low,High" bitfld.long 0x00 8. " SPIS200 ,SPI Status Bit 200" "Low,High" textline " " bitfld.long 0x00 7. " SPIS199 ,SPI Status Bit 199" "Low,High" bitfld.long 0x00 6. " SPIS198 ,SPI Status Bit 198" "Low,High" bitfld.long 0x00 5. " SPIS197 ,SPI Status Bit 197" "Low,High" textline " " bitfld.long 0x00 4. " SPIS196 ,SPI Status Bit 196" "Low,High" bitfld.long 0x00 3. " SPIS195 ,SPI Status Bit 195" "Low,High" bitfld.long 0x00 2. " SPIS194 ,SPI Status Bit 194" "Low,High" textline " " bitfld.long 0x00 1. " SPIS193 ,SPI Status Bit 193" "Low,High" bitfld.long 0x00 0. " SPIS192 ,SPI Status Bit 192" "Low,High" else hgroup.long 0xC098++0x03 hide.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) rgroup.long 0xC09C++0x03 line.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6" bitfld.long 0x00 31. " SPIS255 ,SPI Status Bit 255" "Low,High" bitfld.long 0x00 30. " SPIS254 ,SPI Status Bit 254" "Low,High" bitfld.long 0x00 29. " SPIS253 ,SPI Status Bit 253" "Low,High" textline " " bitfld.long 0x00 28. " SPIS252 ,SPI Status Bit 252" "Low,High" bitfld.long 0x00 27. " SPIS251 ,SPI Status Bit 251" "Low,High" bitfld.long 0x00 26. " SPIS250 ,SPI Status Bit 250" "Low,High" textline " " bitfld.long 0x00 25. " SPIS249 ,SPI Status Bit 249" "Low,High" bitfld.long 0x00 24. " SPIS248 ,SPI Status Bit 248" "Low,High" bitfld.long 0x00 23. " SPIS247 ,SPI Status Bit 247" "Low,High" textline " " bitfld.long 0x00 22. " SPIS246 ,SPI Status Bit 246" "Low,High" bitfld.long 0x00 21. " SPIS245 ,SPI Status Bit 245" "Low,High" bitfld.long 0x00 20. " SPIS244 ,SPI Status Bit 244" "Low,High" textline " " bitfld.long 0x00 19. " SPIS243 ,SPI Status Bit 243" "Low,High" bitfld.long 0x00 18. " SPIS242 ,SPI Status Bit 242" "Low,High" bitfld.long 0x00 17. " SPIS241 ,SPI Status Bit 241" "Low,High" textline " " bitfld.long 0x00 16. " SPIS240 ,SPI Status Bit 240" "Low,High" bitfld.long 0x00 15. " SPIS239 ,SPI Status Bit 239" "Low,High" bitfld.long 0x00 14. " SPIS238 ,SPI Status Bit 238" "Low,High" textline " " bitfld.long 0x00 13. " SPIS237 ,SPI Status Bit 237" "Low,High" bitfld.long 0x00 12. " SPIS236 ,SPI Status Bit 236" "Low,High" bitfld.long 0x00 11. " SPIS235 ,SPI Status Bit 235" "Low,High" textline " " bitfld.long 0x00 10. " SPIS234 ,SPI Status Bit 234" "Low,High" bitfld.long 0x00 9. " SPIS233 ,SPI Status Bit 233" "Low,High" bitfld.long 0x00 8. " SPIS232 ,SPI Status Bit 232" "Low,High" textline " " bitfld.long 0x00 7. " SPIS231 ,SPI Status Bit 231" "Low,High" bitfld.long 0x00 6. " SPIS230 ,SPI Status Bit 230" "Low,High" bitfld.long 0x00 5. " SPIS229 ,SPI Status Bit 229" "Low,High" textline " " bitfld.long 0x00 4. " SPIS228 ,SPI Status Bit 228" "Low,High" bitfld.long 0x00 3. " SPIS227 ,SPI Status Bit 227" "Low,High" bitfld.long 0x00 2. " SPIS226 ,SPI Status Bit 226" "Low,High" textline " " bitfld.long 0x00 1. " SPIS225 ,SPI Status Bit 225" "Low,High" bitfld.long 0x00 0. " SPIS224 ,SPI Status Bit 224" "Low,High" else hgroup.long 0xC09C++0x03 hide.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) rgroup.long 0xC0A0++0x03 line.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7" bitfld.long 0x00 31. " SPIS287 ,SPI Status Bit 287" "Low,High" bitfld.long 0x00 30. " SPIS286 ,SPI Status Bit 286" "Low,High" bitfld.long 0x00 29. " SPIS285 ,SPI Status Bit 285" "Low,High" textline " " bitfld.long 0x00 28. " SPIS284 ,SPI Status Bit 284" "Low,High" bitfld.long 0x00 27. " SPIS283 ,SPI Status Bit 283" "Low,High" bitfld.long 0x00 26. " SPIS282 ,SPI Status Bit 282" "Low,High" textline " " bitfld.long 0x00 25. " SPIS281 ,SPI Status Bit 281" "Low,High" bitfld.long 0x00 24. " SPIS280 ,SPI Status Bit 280" "Low,High" bitfld.long 0x00 23. " SPIS279 ,SPI Status Bit 279" "Low,High" textline " " bitfld.long 0x00 22. " SPIS278 ,SPI Status Bit 278" "Low,High" bitfld.long 0x00 21. " SPIS277 ,SPI Status Bit 277" "Low,High" bitfld.long 0x00 20. " SPIS276 ,SPI Status Bit 276" "Low,High" textline " " bitfld.long 0x00 19. " SPIS275 ,SPI Status Bit 275" "Low,High" bitfld.long 0x00 18. " SPIS274 ,SPI Status Bit 274" "Low,High" bitfld.long 0x00 17. " SPIS273 ,SPI Status Bit 273" "Low,High" textline " " bitfld.long 0x00 16. " SPIS272 ,SPI Status Bit 272" "Low,High" bitfld.long 0x00 15. " SPIS271 ,SPI Status Bit 271" "Low,High" bitfld.long 0x00 14. " SPIS270 ,SPI Status Bit 270" "Low,High" textline " " bitfld.long 0x00 13. " SPIS269 ,SPI Status Bit 269" "Low,High" bitfld.long 0x00 12. " SPIS268 ,SPI Status Bit 268" "Low,High" bitfld.long 0x00 11. " SPIS267 ,SPI Status Bit 267" "Low,High" textline " " bitfld.long 0x00 10. " SPIS266 ,SPI Status Bit 266" "Low,High" bitfld.long 0x00 9. " SPIS265 ,SPI Status Bit 265" "Low,High" bitfld.long 0x00 8. " SPIS264 ,SPI Status Bit 264" "Low,High" textline " " bitfld.long 0x00 7. " SPIS263 ,SPI Status Bit 263" "Low,High" bitfld.long 0x00 6. " SPIS262 ,SPI Status Bit 262" "Low,High" bitfld.long 0x00 5. " SPIS261 ,SPI Status Bit 261" "Low,High" textline " " bitfld.long 0x00 4. " SPIS260 ,SPI Status Bit 260" "Low,High" bitfld.long 0x00 3. " SPIS259 ,SPI Status Bit 259" "Low,High" bitfld.long 0x00 2. " SPIS258 ,SPI Status Bit 258" "Low,High" textline " " bitfld.long 0x00 1. " SPIS257 ,SPI Status Bit 257" "Low,High" bitfld.long 0x00 0. " SPIS256 ,SPI Status Bit 256" "Low,High" else hgroup.long 0xC0A0++0x03 hide.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) rgroup.long 0xC0A4++0x03 line.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8" bitfld.long 0x00 31. " SPIS319 ,SPI Status Bit 319" "Low,High" bitfld.long 0x00 30. " SPIS318 ,SPI Status Bit 318" "Low,High" bitfld.long 0x00 29. " SPIS317 ,SPI Status Bit 317" "Low,High" textline " " bitfld.long 0x00 28. " SPIS316 ,SPI Status Bit 316" "Low,High" bitfld.long 0x00 27. " SPIS315 ,SPI Status Bit 315" "Low,High" bitfld.long 0x00 26. " SPIS314 ,SPI Status Bit 314" "Low,High" textline " " bitfld.long 0x00 25. " SPIS313 ,SPI Status Bit 313" "Low,High" bitfld.long 0x00 24. " SPIS312 ,SPI Status Bit 312" "Low,High" bitfld.long 0x00 23. " SPIS311 ,SPI Status Bit 311" "Low,High" textline " " bitfld.long 0x00 22. " SPIS310 ,SPI Status Bit 310" "Low,High" bitfld.long 0x00 21. " SPIS309 ,SPI Status Bit 309" "Low,High" bitfld.long 0x00 20. " SPIS308 ,SPI Status Bit 308" "Low,High" textline " " bitfld.long 0x00 19. " SPIS307 ,SPI Status Bit 307" "Low,High" bitfld.long 0x00 18. " SPIS306 ,SPI Status Bit 306" "Low,High" bitfld.long 0x00 17. " SPIS305 ,SPI Status Bit 305" "Low,High" textline " " bitfld.long 0x00 16. " SPIS304 ,SPI Status Bit 304" "Low,High" bitfld.long 0x00 15. " SPIS303 ,SPI Status Bit 303" "Low,High" bitfld.long 0x00 14. " SPIS302 ,SPI Status Bit 302" "Low,High" textline " " bitfld.long 0x00 13. " SPIS301 ,SPI Status Bit 301" "Low,High" bitfld.long 0x00 12. " SPIS300 ,SPI Status Bit 300" "Low,High" bitfld.long 0x00 11. " SPIS299 ,SPI Status Bit 299" "Low,High" textline " " bitfld.long 0x00 10. " SPIS298 ,SPI Status Bit 298" "Low,High" bitfld.long 0x00 9. " SPIS297 ,SPI Status Bit 297" "Low,High" bitfld.long 0x00 8. " SPIS296 ,SPI Status Bit 296" "Low,High" textline " " bitfld.long 0x00 7. " SPIS295 ,SPI Status Bit 295" "Low,High" bitfld.long 0x00 6. " SPIS294 ,SPI Status Bit 294" "Low,High" bitfld.long 0x00 5. " SPIS293 ,SPI Status Bit 293" "Low,High" textline " " bitfld.long 0x00 4. " SPIS292 ,SPI Status Bit 292" "Low,High" bitfld.long 0x00 3. " SPIS291 ,SPI Status Bit 291" "Low,High" bitfld.long 0x00 2. " SPIS290 ,SPI Status Bit 290" "Low,High" textline " " bitfld.long 0x00 1. " SPIS289 ,SPI Status Bit 289" "Low,High" bitfld.long 0x00 0. " SPIS288 ,SPI Status Bit 288" "Low,High" else hgroup.long 0xC0A4++0x03 hide.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) rgroup.long 0xC0A8++0x03 line.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9" bitfld.long 0x00 31. " SPIS351 ,SPI Status Bit 351" "Low,High" bitfld.long 0x00 30. " SPIS350 ,SPI Status Bit 350" "Low,High" bitfld.long 0x00 29. " SPIS349 ,SPI Status Bit 349" "Low,High" textline " " bitfld.long 0x00 28. " SPIS348 ,SPI Status Bit 348" "Low,High" bitfld.long 0x00 27. " SPIS347 ,SPI Status Bit 347" "Low,High" bitfld.long 0x00 26. " SPIS346 ,SPI Status Bit 346" "Low,High" textline " " bitfld.long 0x00 25. " SPIS345 ,SPI Status Bit 345" "Low,High" bitfld.long 0x00 24. " SPIS344 ,SPI Status Bit 344" "Low,High" bitfld.long 0x00 23. " SPIS343 ,SPI Status Bit 343" "Low,High" textline " " bitfld.long 0x00 22. " SPIS342 ,SPI Status Bit 342" "Low,High" bitfld.long 0x00 21. " SPIS341 ,SPI Status Bit 341" "Low,High" bitfld.long 0x00 20. " SPIS340 ,SPI Status Bit 340" "Low,High" textline " " bitfld.long 0x00 19. " SPIS339 ,SPI Status Bit 339" "Low,High" bitfld.long 0x00 18. " SPIS338 ,SPI Status Bit 338" "Low,High" bitfld.long 0x00 17. " SPIS337 ,SPI Status Bit 337" "Low,High" textline " " bitfld.long 0x00 16. " SPIS336 ,SPI Status Bit 336" "Low,High" bitfld.long 0x00 15. " SPIS335 ,SPI Status Bit 335" "Low,High" bitfld.long 0x00 14. " SPIS334 ,SPI Status Bit 334" "Low,High" textline " " bitfld.long 0x00 13. " SPIS333 ,SPI Status Bit 333" "Low,High" bitfld.long 0x00 12. " SPIS332 ,SPI Status Bit 332" "Low,High" bitfld.long 0x00 11. " SPIS331 ,SPI Status Bit 331" "Low,High" textline " " bitfld.long 0x00 10. " SPIS330 ,SPI Status Bit 330" "Low,High" bitfld.long 0x00 9. " SPIS329 ,SPI Status Bit 329" "Low,High" bitfld.long 0x00 8. " SPIS328 ,SPI Status Bit 328" "Low,High" textline " " bitfld.long 0x00 7. " SPIS327 ,SPI Status Bit 327" "Low,High" bitfld.long 0x00 6. " SPIS326 ,SPI Status Bit 326" "Low,High" bitfld.long 0x00 5. " SPIS325 ,SPI Status Bit 325" "Low,High" textline " " bitfld.long 0x00 4. " SPIS324 ,SPI Status Bit 324" "Low,High" bitfld.long 0x00 3. " SPIS323 ,SPI Status Bit 323" "Low,High" bitfld.long 0x00 2. " SPIS322 ,SPI Status Bit 322" "Low,High" textline " " bitfld.long 0x00 1. " SPIS321 ,SPI Status Bit 321" "Low,High" bitfld.long 0x00 0. " SPIS320 ,SPI Status Bit 320" "Low,High" else hgroup.long 0xC0A8++0x03 hide.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) rgroup.long 0xC0AC++0x03 line.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10" bitfld.long 0x00 31. " SPIS383 ,SPI Status Bit 383" "Low,High" bitfld.long 0x00 30. " SPIS382 ,SPI Status Bit 382" "Low,High" bitfld.long 0x00 29. " SPIS381 ,SPI Status Bit 381" "Low,High" textline " " bitfld.long 0x00 28. " SPIS380 ,SPI Status Bit 380" "Low,High" bitfld.long 0x00 27. " SPIS379 ,SPI Status Bit 379" "Low,High" bitfld.long 0x00 26. " SPIS378 ,SPI Status Bit 378" "Low,High" textline " " bitfld.long 0x00 25. " SPIS377 ,SPI Status Bit 377" "Low,High" bitfld.long 0x00 24. " SPIS376 ,SPI Status Bit 376" "Low,High" bitfld.long 0x00 23. " SPIS375 ,SPI Status Bit 375" "Low,High" textline " " bitfld.long 0x00 22. " SPIS374 ,SPI Status Bit 374" "Low,High" bitfld.long 0x00 21. " SPIS373 ,SPI Status Bit 373" "Low,High" bitfld.long 0x00 20. " SPIS372 ,SPI Status Bit 372" "Low,High" textline " " bitfld.long 0x00 19. " SPIS371 ,SPI Status Bit 371" "Low,High" bitfld.long 0x00 18. " SPIS370 ,SPI Status Bit 370" "Low,High" bitfld.long 0x00 17. " SPIS369 ,SPI Status Bit 369" "Low,High" textline " " bitfld.long 0x00 16. " SPIS368 ,SPI Status Bit 368" "Low,High" bitfld.long 0x00 15. " SPIS367 ,SPI Status Bit 367" "Low,High" bitfld.long 0x00 14. " SPIS366 ,SPI Status Bit 366" "Low,High" textline " " bitfld.long 0x00 13. " SPIS365 ,SPI Status Bit 365" "Low,High" bitfld.long 0x00 12. " SPIS364 ,SPI Status Bit 364" "Low,High" bitfld.long 0x00 11. " SPIS363 ,SPI Status Bit 363" "Low,High" textline " " bitfld.long 0x00 10. " SPIS362 ,SPI Status Bit 362" "Low,High" bitfld.long 0x00 9. " SPIS361 ,SPI Status Bit 361" "Low,High" bitfld.long 0x00 8. " SPIS360 ,SPI Status Bit 360" "Low,High" textline " " bitfld.long 0x00 7. " SPIS359 ,SPI Status Bit 359" "Low,High" bitfld.long 0x00 6. " SPIS358 ,SPI Status Bit 358" "Low,High" bitfld.long 0x00 5. " SPIS357 ,SPI Status Bit 357" "Low,High" textline " " bitfld.long 0x00 4. " SPIS356 ,SPI Status Bit 356" "Low,High" bitfld.long 0x00 3. " SPIS355 ,SPI Status Bit 355" "Low,High" bitfld.long 0x00 2. " SPIS354 ,SPI Status Bit 354" "Low,High" textline " " bitfld.long 0x00 1. " SPIS353 ,SPI Status Bit 353" "Low,High" bitfld.long 0x00 0. " SPIS352 ,SPI Status Bit 352" "Low,High" else hgroup.long 0xC0AC++0x03 hide.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) rgroup.long 0xC0B0++0x03 line.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11" bitfld.long 0x00 31. " SPIS415 ,SPI Status Bit 415" "Low,High" bitfld.long 0x00 30. " SPIS414 ,SPI Status Bit 414" "Low,High" bitfld.long 0x00 29. " SPIS413 ,SPI Status Bit 413" "Low,High" textline " " bitfld.long 0x00 28. " SPIS412 ,SPI Status Bit 412" "Low,High" bitfld.long 0x00 27. " SPIS411 ,SPI Status Bit 411" "Low,High" bitfld.long 0x00 26. " SPIS410 ,SPI Status Bit 410" "Low,High" textline " " bitfld.long 0x00 25. " SPIS409 ,SPI Status Bit 409" "Low,High" bitfld.long 0x00 24. " SPIS408 ,SPI Status Bit 408" "Low,High" bitfld.long 0x00 23. " SPIS407 ,SPI Status Bit 407" "Low,High" textline " " bitfld.long 0x00 22. " SPIS406 ,SPI Status Bit 406" "Low,High" bitfld.long 0x00 21. " SPIS405 ,SPI Status Bit 405" "Low,High" bitfld.long 0x00 20. " SPIS404 ,SPI Status Bit 404" "Low,High" textline " " bitfld.long 0x00 19. " SPIS403 ,SPI Status Bit 403" "Low,High" bitfld.long 0x00 18. " SPIS402 ,SPI Status Bit 402" "Low,High" bitfld.long 0x00 17. " SPIS401 ,SPI Status Bit 401" "Low,High" textline " " bitfld.long 0x00 16. " SPIS400 ,SPI Status Bit 400" "Low,High" bitfld.long 0x00 15. " SPIS399 ,SPI Status Bit 399" "Low,High" bitfld.long 0x00 14. " SPIS398 ,SPI Status Bit 398" "Low,High" textline " " bitfld.long 0x00 13. " SPIS397 ,SPI Status Bit 397" "Low,High" bitfld.long 0x00 12. " SPIS396 ,SPI Status Bit 396" "Low,High" bitfld.long 0x00 11. " SPIS395 ,SPI Status Bit 395" "Low,High" textline " " bitfld.long 0x00 10. " SPIS394 ,SPI Status Bit 394" "Low,High" bitfld.long 0x00 9. " SPIS393 ,SPI Status Bit 393" "Low,High" bitfld.long 0x00 8. " SPIS392 ,SPI Status Bit 392" "Low,High" textline " " bitfld.long 0x00 7. " SPIS391 ,SPI Status Bit 391" "Low,High" bitfld.long 0x00 6. " SPIS390 ,SPI Status Bit 390" "Low,High" bitfld.long 0x00 5. " SPIS389 ,SPI Status Bit 389" "Low,High" textline " " bitfld.long 0x00 4. " SPIS388 ,SPI Status Bit 388" "Low,High" bitfld.long 0x00 3. " SPIS387 ,SPI Status Bit 387" "Low,High" bitfld.long 0x00 2. " SPIS386 ,SPI Status Bit 386" "Low,High" textline " " bitfld.long 0x00 1. " SPIS385 ,SPI Status Bit 385" "Low,High" bitfld.long 0x00 0. " SPIS384 ,SPI Status Bit 384" "Low,High" else hgroup.long 0xC0B0++0x03 hide.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) rgroup.long 0xC0B4++0x03 line.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12" bitfld.long 0x00 31. " SPIS447 ,SPI Status Bit 447" "Low,High" bitfld.long 0x00 30. " SPIS446 ,SPI Status Bit 446" "Low,High" bitfld.long 0x00 29. " SPIS445 ,SPI Status Bit 445" "Low,High" textline " " bitfld.long 0x00 28. " SPIS444 ,SPI Status Bit 444" "Low,High" bitfld.long 0x00 27. " SPIS443 ,SPI Status Bit 443" "Low,High" bitfld.long 0x00 26. " SPIS442 ,SPI Status Bit 442" "Low,High" textline " " bitfld.long 0x00 25. " SPIS441 ,SPI Status Bit 441" "Low,High" bitfld.long 0x00 24. " SPIS440 ,SPI Status Bit 440" "Low,High" bitfld.long 0x00 23. " SPIS439 ,SPI Status Bit 439" "Low,High" textline " " bitfld.long 0x00 22. " SPIS438 ,SPI Status Bit 438" "Low,High" bitfld.long 0x00 21. " SPIS437 ,SPI Status Bit 437" "Low,High" bitfld.long 0x00 20. " SPIS436 ,SPI Status Bit 436" "Low,High" textline " " bitfld.long 0x00 19. " SPIS435 ,SPI Status Bit 435" "Low,High" bitfld.long 0x00 18. " SPIS434 ,SPI Status Bit 434" "Low,High" bitfld.long 0x00 17. " SPIS433 ,SPI Status Bit 433" "Low,High" textline " " bitfld.long 0x00 16. " SPIS432 ,SPI Status Bit 432" "Low,High" bitfld.long 0x00 15. " SPIS431 ,SPI Status Bit 431" "Low,High" bitfld.long 0x00 14. " SPIS430 ,SPI Status Bit 430" "Low,High" textline " " bitfld.long 0x00 13. " SPIS429 ,SPI Status Bit 429" "Low,High" bitfld.long 0x00 12. " SPIS428 ,SPI Status Bit 428" "Low,High" bitfld.long 0x00 11. " SPIS427 ,SPI Status Bit 427" "Low,High" textline " " bitfld.long 0x00 10. " SPIS426 ,SPI Status Bit 426" "Low,High" bitfld.long 0x00 9. " SPIS425 ,SPI Status Bit 425" "Low,High" bitfld.long 0x00 8. " SPIS424 ,SPI Status Bit 424" "Low,High" textline " " bitfld.long 0x00 7. " SPIS423 ,SPI Status Bit 423" "Low,High" bitfld.long 0x00 6. " SPIS422 ,SPI Status Bit 422" "Low,High" bitfld.long 0x00 5. " SPIS421 ,SPI Status Bit 421" "Low,High" textline " " bitfld.long 0x00 4. " SPIS420 ,SPI Status Bit 420" "Low,High" bitfld.long 0x00 3. " SPIS419 ,SPI Status Bit 419" "Low,High" bitfld.long 0x00 2. " SPIS418 ,SPI Status Bit 418" "Low,High" textline " " bitfld.long 0x00 1. " SPIS417 ,SPI Status Bit 417" "Low,High" bitfld.long 0x00 0. " SPIS416 ,SPI Status Bit 416" "Low,High" else hgroup.long 0xC0B4++0x03 hide.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) rgroup.long 0xC0B8++0x03 line.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13" bitfld.long 0x00 31. " SPIS479 ,SPI Status Bit 479" "Low,High" bitfld.long 0x00 30. " SPIS478 ,SPI Status Bit 478" "Low,High" bitfld.long 0x00 29. " SPIS477 ,SPI Status Bit 477" "Low,High" textline " " bitfld.long 0x00 28. " SPIS476 ,SPI Status Bit 476" "Low,High" bitfld.long 0x00 27. " SPIS475 ,SPI Status Bit 475" "Low,High" bitfld.long 0x00 26. " SPIS474 ,SPI Status Bit 474" "Low,High" textline " " bitfld.long 0x00 25. " SPIS473 ,SPI Status Bit 473" "Low,High" bitfld.long 0x00 24. " SPIS472 ,SPI Status Bit 472" "Low,High" bitfld.long 0x00 23. " SPIS471 ,SPI Status Bit 471" "Low,High" textline " " bitfld.long 0x00 22. " SPIS470 ,SPI Status Bit 470" "Low,High" bitfld.long 0x00 21. " SPIS469 ,SPI Status Bit 469" "Low,High" bitfld.long 0x00 20. " SPIS468 ,SPI Status Bit 468" "Low,High" textline " " bitfld.long 0x00 19. " SPIS467 ,SPI Status Bit 467" "Low,High" bitfld.long 0x00 18. " SPIS466 ,SPI Status Bit 466" "Low,High" bitfld.long 0x00 17. " SPIS465 ,SPI Status Bit 465" "Low,High" textline " " bitfld.long 0x00 16. " SPIS464 ,SPI Status Bit 464" "Low,High" bitfld.long 0x00 15. " SPIS463 ,SPI Status Bit 463" "Low,High" bitfld.long 0x00 14. " SPIS462 ,SPI Status Bit 462" "Low,High" textline " " bitfld.long 0x00 13. " SPIS461 ,SPI Status Bit 461" "Low,High" bitfld.long 0x00 12. " SPIS460 ,SPI Status Bit 460" "Low,High" bitfld.long 0x00 11. " SPIS459 ,SPI Status Bit 459" "Low,High" textline " " bitfld.long 0x00 10. " SPIS458 ,SPI Status Bit 458" "Low,High" bitfld.long 0x00 9. " SPIS457 ,SPI Status Bit 457" "Low,High" bitfld.long 0x00 8. " SPIS456 ,SPI Status Bit 456" "Low,High" textline " " bitfld.long 0x00 7. " SPIS455 ,SPI Status Bit 455" "Low,High" bitfld.long 0x00 6. " SPIS454 ,SPI Status Bit 454" "Low,High" bitfld.long 0x00 5. " SPIS453 ,SPI Status Bit 453" "Low,High" textline " " bitfld.long 0x00 4. " SPIS452 ,SPI Status Bit 452" "Low,High" bitfld.long 0x00 3. " SPIS451 ,SPI Status Bit 451" "Low,High" bitfld.long 0x00 2. " SPIS450 ,SPI Status Bit 450" "Low,High" textline " " bitfld.long 0x00 1. " SPIS449 ,SPI Status Bit 449" "Low,High" bitfld.long 0x00 0. " SPIS448 ,SPI Status Bit 448" "Low,High" else hgroup.long 0xC0B8++0x03 hide.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) rgroup.long 0xC0BC++0x03 line.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14" bitfld.long 0x00 31. " SPIS511 ,SPI Status Bit 511" "Low,High" bitfld.long 0x00 30. " SPIS510 ,SPI Status Bit 510" "Low,High" bitfld.long 0x00 29. " SPIS509 ,SPI Status Bit 509" "Low,High" textline " " bitfld.long 0x00 28. " SPIS508 ,SPI Status Bit 508" "Low,High" bitfld.long 0x00 27. " SPIS507 ,SPI Status Bit 507" "Low,High" bitfld.long 0x00 26. " SPIS506 ,SPI Status Bit 506" "Low,High" textline " " bitfld.long 0x00 25. " SPIS505 ,SPI Status Bit 505" "Low,High" bitfld.long 0x00 24. " SPIS504 ,SPI Status Bit 504" "Low,High" bitfld.long 0x00 23. " SPIS503 ,SPI Status Bit 503" "Low,High" textline " " bitfld.long 0x00 22. " SPIS502 ,SPI Status Bit 502" "Low,High" bitfld.long 0x00 21. " SPIS501 ,SPI Status Bit 501" "Low,High" bitfld.long 0x00 20. " SPIS500 ,SPI Status Bit 500" "Low,High" textline " " bitfld.long 0x00 19. " SPIS499 ,SPI Status Bit 499" "Low,High" bitfld.long 0x00 18. " SPIS498 ,SPI Status Bit 498" "Low,High" bitfld.long 0x00 17. " SPIS497 ,SPI Status Bit 497" "Low,High" textline " " bitfld.long 0x00 16. " SPIS496 ,SPI Status Bit 496" "Low,High" bitfld.long 0x00 15. " SPIS495 ,SPI Status Bit 495" "Low,High" bitfld.long 0x00 14. " SPIS494 ,SPI Status Bit 494" "Low,High" textline " " bitfld.long 0x00 13. " SPIS493 ,SPI Status Bit 493" "Low,High" bitfld.long 0x00 12. " SPIS492 ,SPI Status Bit 492" "Low,High" bitfld.long 0x00 11. " SPIS491 ,SPI Status Bit 491" "Low,High" textline " " bitfld.long 0x00 10. " SPIS490 ,SPI Status Bit 490" "Low,High" bitfld.long 0x00 9. " SPIS489 ,SPI Status Bit 489" "Low,High" bitfld.long 0x00 8. " SPIS488 ,SPI Status Bit 488" "Low,High" textline " " bitfld.long 0x00 7. " SPIS487 ,SPI Status Bit 487" "Low,High" bitfld.long 0x00 6. " SPIS486 ,SPI Status Bit 486" "Low,High" bitfld.long 0x00 5. " SPIS485 ,SPI Status Bit 485" "Low,High" textline " " bitfld.long 0x00 4. " SPIS484 ,SPI Status Bit 484" "Low,High" bitfld.long 0x00 3. " SPIS483 ,SPI Status Bit 483" "Low,High" bitfld.long 0x00 2. " SPIS482 ,SPI Status Bit 482" "Low,High" textline " " bitfld.long 0x00 1. " SPIS481 ,SPI Status Bit 481" "Low,High" bitfld.long 0x00 0. " SPIS480 ,SPI Status Bit 480" "Low,High" else hgroup.long 0xC0BC++0x03 hide.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) rgroup.long 0xC0C0++0x03 line.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15" bitfld.long 0x00 31. " SPIS543 ,SPI Status Bit 543" "Low,High" bitfld.long 0x00 30. " SPIS542 ,SPI Status Bit 542" "Low,High" bitfld.long 0x00 29. " SPIS541 ,SPI Status Bit 541" "Low,High" textline " " bitfld.long 0x00 28. " SPIS540 ,SPI Status Bit 540" "Low,High" bitfld.long 0x00 27. " SPIS539 ,SPI Status Bit 539" "Low,High" bitfld.long 0x00 26. " SPIS538 ,SPI Status Bit 538" "Low,High" textline " " bitfld.long 0x00 25. " SPIS537 ,SPI Status Bit 537" "Low,High" bitfld.long 0x00 24. " SPIS536 ,SPI Status Bit 536" "Low,High" bitfld.long 0x00 23. " SPIS535 ,SPI Status Bit 535" "Low,High" textline " " bitfld.long 0x00 22. " SPIS534 ,SPI Status Bit 534" "Low,High" bitfld.long 0x00 21. " SPIS533 ,SPI Status Bit 533" "Low,High" bitfld.long 0x00 20. " SPIS532 ,SPI Status Bit 532" "Low,High" textline " " bitfld.long 0x00 19. " SPIS531 ,SPI Status Bit 531" "Low,High" bitfld.long 0x00 18. " SPIS530 ,SPI Status Bit 530" "Low,High" bitfld.long 0x00 17. " SPIS529 ,SPI Status Bit 529" "Low,High" textline " " bitfld.long 0x00 16. " SPIS528 ,SPI Status Bit 528" "Low,High" bitfld.long 0x00 15. " SPIS527 ,SPI Status Bit 527" "Low,High" bitfld.long 0x00 14. " SPIS526 ,SPI Status Bit 526" "Low,High" textline " " bitfld.long 0x00 13. " SPIS525 ,SPI Status Bit 525" "Low,High" bitfld.long 0x00 12. " SPIS524 ,SPI Status Bit 524" "Low,High" bitfld.long 0x00 11. " SPIS523 ,SPI Status Bit 523" "Low,High" textline " " bitfld.long 0x00 10. " SPIS522 ,SPI Status Bit 522" "Low,High" bitfld.long 0x00 9. " SPIS521 ,SPI Status Bit 521" "Low,High" bitfld.long 0x00 8. " SPIS520 ,SPI Status Bit 520" "Low,High" textline " " bitfld.long 0x00 7. " SPIS519 ,SPI Status Bit 519" "Low,High" bitfld.long 0x00 6. " SPIS518 ,SPI Status Bit 518" "Low,High" bitfld.long 0x00 5. " SPIS517 ,SPI Status Bit 517" "Low,High" textline " " bitfld.long 0x00 4. " SPIS516 ,SPI Status Bit 516" "Low,High" bitfld.long 0x00 3. " SPIS515 ,SPI Status Bit 515" "Low,High" bitfld.long 0x00 2. " SPIS514 ,SPI Status Bit 514" "Low,High" textline " " bitfld.long 0x00 1. " SPIS513 ,SPI Status Bit 513" "Low,High" bitfld.long 0x00 0. " SPIS512 ,SPI Status Bit 512" "Low,High" else hgroup.long 0xC0C0++0x03 hide.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) rgroup.long 0xC0C4++0x03 line.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16" bitfld.long 0x00 31. " SPIS575 ,SPI Status Bit 575" "Low,High" bitfld.long 0x00 30. " SPIS574 ,SPI Status Bit 574" "Low,High" bitfld.long 0x00 29. " SPIS573 ,SPI Status Bit 573" "Low,High" textline " " bitfld.long 0x00 28. " SPIS572 ,SPI Status Bit 572" "Low,High" bitfld.long 0x00 27. " SPIS571 ,SPI Status Bit 571" "Low,High" bitfld.long 0x00 26. " SPIS570 ,SPI Status Bit 570" "Low,High" textline " " bitfld.long 0x00 25. " SPIS569 ,SPI Status Bit 569" "Low,High" bitfld.long 0x00 24. " SPIS568 ,SPI Status Bit 568" "Low,High" bitfld.long 0x00 23. " SPIS567 ,SPI Status Bit 567" "Low,High" textline " " bitfld.long 0x00 22. " SPIS566 ,SPI Status Bit 566" "Low,High" bitfld.long 0x00 21. " SPIS565 ,SPI Status Bit 565" "Low,High" bitfld.long 0x00 20. " SPIS564 ,SPI Status Bit 564" "Low,High" textline " " bitfld.long 0x00 19. " SPIS563 ,SPI Status Bit 563" "Low,High" bitfld.long 0x00 18. " SPIS562 ,SPI Status Bit 562" "Low,High" bitfld.long 0x00 17. " SPIS561 ,SPI Status Bit 561" "Low,High" textline " " bitfld.long 0x00 16. " SPIS560 ,SPI Status Bit 560" "Low,High" bitfld.long 0x00 15. " SPIS559 ,SPI Status Bit 559" "Low,High" bitfld.long 0x00 14. " SPIS558 ,SPI Status Bit 558" "Low,High" textline " " bitfld.long 0x00 13. " SPIS557 ,SPI Status Bit 557" "Low,High" bitfld.long 0x00 12. " SPIS556 ,SPI Status Bit 556" "Low,High" bitfld.long 0x00 11. " SPIS555 ,SPI Status Bit 555" "Low,High" textline " " bitfld.long 0x00 10. " SPIS554 ,SPI Status Bit 554" "Low,High" bitfld.long 0x00 9. " SPIS553 ,SPI Status Bit 553" "Low,High" bitfld.long 0x00 8. " SPIS552 ,SPI Status Bit 552" "Low,High" textline " " bitfld.long 0x00 7. " SPIS551 ,SPI Status Bit 551" "Low,High" bitfld.long 0x00 6. " SPIS550 ,SPI Status Bit 550" "Low,High" bitfld.long 0x00 5. " SPIS549 ,SPI Status Bit 549" "Low,High" textline " " bitfld.long 0x00 4. " SPIS548 ,SPI Status Bit 548" "Low,High" bitfld.long 0x00 3. " SPIS547 ,SPI Status Bit 547" "Low,High" bitfld.long 0x00 2. " SPIS546 ,SPI Status Bit 546" "Low,High" textline " " bitfld.long 0x00 1. " SPIS545 ,SPI Status Bit 545" "Low,High" bitfld.long 0x00 0. " SPIS544 ,SPI Status Bit 544" "Low,High" else hgroup.long 0xC0C4++0x03 hide.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) rgroup.long 0xC0C8++0x03 line.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17" bitfld.long 0x00 31. " SPIS607 ,SPI Status Bit 607" "Low,High" bitfld.long 0x00 30. " SPIS606 ,SPI Status Bit 606" "Low,High" bitfld.long 0x00 29. " SPIS605 ,SPI Status Bit 605" "Low,High" textline " " bitfld.long 0x00 28. " SPIS604 ,SPI Status Bit 604" "Low,High" bitfld.long 0x00 27. " SPIS603 ,SPI Status Bit 603" "Low,High" bitfld.long 0x00 26. " SPIS602 ,SPI Status Bit 602" "Low,High" textline " " bitfld.long 0x00 25. " SPIS601 ,SPI Status Bit 601" "Low,High" bitfld.long 0x00 24. " SPIS600 ,SPI Status Bit 600" "Low,High" bitfld.long 0x00 23. " SPIS599 ,SPI Status Bit 599" "Low,High" textline " " bitfld.long 0x00 22. " SPIS598 ,SPI Status Bit 598" "Low,High" bitfld.long 0x00 21. " SPIS597 ,SPI Status Bit 597" "Low,High" bitfld.long 0x00 20. " SPIS596 ,SPI Status Bit 596" "Low,High" textline " " bitfld.long 0x00 19. " SPIS595 ,SPI Status Bit 595" "Low,High" bitfld.long 0x00 18. " SPIS594 ,SPI Status Bit 594" "Low,High" bitfld.long 0x00 17. " SPIS593 ,SPI Status Bit 593" "Low,High" textline " " bitfld.long 0x00 16. " SPIS592 ,SPI Status Bit 592" "Low,High" bitfld.long 0x00 15. " SPIS591 ,SPI Status Bit 591" "Low,High" bitfld.long 0x00 14. " SPIS590 ,SPI Status Bit 590" "Low,High" textline " " bitfld.long 0x00 13. " SPIS589 ,SPI Status Bit 589" "Low,High" bitfld.long 0x00 12. " SPIS588 ,SPI Status Bit 588" "Low,High" bitfld.long 0x00 11. " SPIS587 ,SPI Status Bit 587" "Low,High" textline " " bitfld.long 0x00 10. " SPIS586 ,SPI Status Bit 586" "Low,High" bitfld.long 0x00 9. " SPIS585 ,SPI Status Bit 585" "Low,High" bitfld.long 0x00 8. " SPIS584 ,SPI Status Bit 584" "Low,High" textline " " bitfld.long 0x00 7. " SPIS583 ,SPI Status Bit 583" "Low,High" bitfld.long 0x00 6. " SPIS582 ,SPI Status Bit 582" "Low,High" bitfld.long 0x00 5. " SPIS581 ,SPI Status Bit 581" "Low,High" textline " " bitfld.long 0x00 4. " SPIS580 ,SPI Status Bit 580" "Low,High" bitfld.long 0x00 3. " SPIS579 ,SPI Status Bit 579" "Low,High" bitfld.long 0x00 2. " SPIS578 ,SPI Status Bit 578" "Low,High" textline " " bitfld.long 0x00 1. " SPIS577 ,SPI Status Bit 577" "Low,High" bitfld.long 0x00 0. " SPIS576 ,SPI Status Bit 576" "Low,High" else hgroup.long 0xC0C8++0x03 hide.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) rgroup.long 0xC0CC++0x03 line.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18" bitfld.long 0x00 31. " SPIS639 ,SPI Status Bit 639" "Low,High" bitfld.long 0x00 30. " SPIS638 ,SPI Status Bit 638" "Low,High" bitfld.long 0x00 29. " SPIS637 ,SPI Status Bit 637" "Low,High" textline " " bitfld.long 0x00 28. " SPIS636 ,SPI Status Bit 636" "Low,High" bitfld.long 0x00 27. " SPIS635 ,SPI Status Bit 635" "Low,High" bitfld.long 0x00 26. " SPIS634 ,SPI Status Bit 634" "Low,High" textline " " bitfld.long 0x00 25. " SPIS633 ,SPI Status Bit 633" "Low,High" bitfld.long 0x00 24. " SPIS632 ,SPI Status Bit 632" "Low,High" bitfld.long 0x00 23. " SPIS631 ,SPI Status Bit 631" "Low,High" textline " " bitfld.long 0x00 22. " SPIS630 ,SPI Status Bit 630" "Low,High" bitfld.long 0x00 21. " SPIS629 ,SPI Status Bit 629" "Low,High" bitfld.long 0x00 20. " SPIS628 ,SPI Status Bit 628" "Low,High" textline " " bitfld.long 0x00 19. " SPIS627 ,SPI Status Bit 627" "Low,High" bitfld.long 0x00 18. " SPIS626 ,SPI Status Bit 626" "Low,High" bitfld.long 0x00 17. " SPIS625 ,SPI Status Bit 625" "Low,High" textline " " bitfld.long 0x00 16. " SPIS624 ,SPI Status Bit 624" "Low,High" bitfld.long 0x00 15. " SPIS623 ,SPI Status Bit 623" "Low,High" bitfld.long 0x00 14. " SPIS622 ,SPI Status Bit 622" "Low,High" textline " " bitfld.long 0x00 13. " SPIS621 ,SPI Status Bit 621" "Low,High" bitfld.long 0x00 12. " SPIS620 ,SPI Status Bit 620" "Low,High" bitfld.long 0x00 11. " SPIS619 ,SPI Status Bit 619" "Low,High" textline " " bitfld.long 0x00 10. " SPIS618 ,SPI Status Bit 618" "Low,High" bitfld.long 0x00 9. " SPIS617 ,SPI Status Bit 617" "Low,High" bitfld.long 0x00 8. " SPIS616 ,SPI Status Bit 616" "Low,High" textline " " bitfld.long 0x00 7. " SPIS615 ,SPI Status Bit 615" "Low,High" bitfld.long 0x00 6. " SPIS614 ,SPI Status Bit 614" "Low,High" bitfld.long 0x00 5. " SPIS613 ,SPI Status Bit 613" "Low,High" textline " " bitfld.long 0x00 4. " SPIS612 ,SPI Status Bit 612" "Low,High" bitfld.long 0x00 3. " SPIS611 ,SPI Status Bit 611" "Low,High" bitfld.long 0x00 2. " SPIS610 ,SPI Status Bit 610" "Low,High" textline " " bitfld.long 0x00 1. " SPIS609 ,SPI Status Bit 609" "Low,High" bitfld.long 0x00 0. " SPIS608 ,SPI Status Bit 608" "Low,High" else hgroup.long 0xC0CC++0x03 hide.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) rgroup.long 0xC0D0++0x03 line.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19" bitfld.long 0x00 31. " SPIS671 ,SPI Status Bit 671" "Low,High" bitfld.long 0x00 30. " SPIS670 ,SPI Status Bit 670" "Low,High" bitfld.long 0x00 29. " SPIS669 ,SPI Status Bit 669" "Low,High" textline " " bitfld.long 0x00 28. " SPIS668 ,SPI Status Bit 668" "Low,High" bitfld.long 0x00 27. " SPIS667 ,SPI Status Bit 667" "Low,High" bitfld.long 0x00 26. " SPIS666 ,SPI Status Bit 666" "Low,High" textline " " bitfld.long 0x00 25. " SPIS665 ,SPI Status Bit 665" "Low,High" bitfld.long 0x00 24. " SPIS664 ,SPI Status Bit 664" "Low,High" bitfld.long 0x00 23. " SPIS663 ,SPI Status Bit 663" "Low,High" textline " " bitfld.long 0x00 22. " SPIS662 ,SPI Status Bit 662" "Low,High" bitfld.long 0x00 21. " SPIS661 ,SPI Status Bit 661" "Low,High" bitfld.long 0x00 20. " SPIS660 ,SPI Status Bit 660" "Low,High" textline " " bitfld.long 0x00 19. " SPIS659 ,SPI Status Bit 659" "Low,High" bitfld.long 0x00 18. " SPIS658 ,SPI Status Bit 658" "Low,High" bitfld.long 0x00 17. " SPIS657 ,SPI Status Bit 657" "Low,High" textline " " bitfld.long 0x00 16. " SPIS656 ,SPI Status Bit 656" "Low,High" bitfld.long 0x00 15. " SPIS655 ,SPI Status Bit 655" "Low,High" bitfld.long 0x00 14. " SPIS654 ,SPI Status Bit 654" "Low,High" textline " " bitfld.long 0x00 13. " SPIS653 ,SPI Status Bit 653" "Low,High" bitfld.long 0x00 12. " SPIS652 ,SPI Status Bit 652" "Low,High" bitfld.long 0x00 11. " SPIS651 ,SPI Status Bit 651" "Low,High" textline " " bitfld.long 0x00 10. " SPIS650 ,SPI Status Bit 650" "Low,High" bitfld.long 0x00 9. " SPIS649 ,SPI Status Bit 649" "Low,High" bitfld.long 0x00 8. " SPIS648 ,SPI Status Bit 648" "Low,High" textline " " bitfld.long 0x00 7. " SPIS647 ,SPI Status Bit 647" "Low,High" bitfld.long 0x00 6. " SPIS646 ,SPI Status Bit 646" "Low,High" bitfld.long 0x00 5. " SPIS645 ,SPI Status Bit 645" "Low,High" textline " " bitfld.long 0x00 4. " SPIS644 ,SPI Status Bit 644" "Low,High" bitfld.long 0x00 3. " SPIS643 ,SPI Status Bit 643" "Low,High" bitfld.long 0x00 2. " SPIS642 ,SPI Status Bit 642" "Low,High" textline " " bitfld.long 0x00 1. " SPIS641 ,SPI Status Bit 641" "Low,High" bitfld.long 0x00 0. " SPIS640 ,SPI Status Bit 640" "Low,High" else hgroup.long 0xC0D0++0x03 hide.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) rgroup.long 0xC0D4++0x03 line.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20" bitfld.long 0x00 31. " SPIS703 ,SPI Status Bit 703" "Low,High" bitfld.long 0x00 30. " SPIS702 ,SPI Status Bit 702" "Low,High" bitfld.long 0x00 29. " SPIS701 ,SPI Status Bit 701" "Low,High" textline " " bitfld.long 0x00 28. " SPIS700 ,SPI Status Bit 700" "Low,High" bitfld.long 0x00 27. " SPIS699 ,SPI Status Bit 699" "Low,High" bitfld.long 0x00 26. " SPIS698 ,SPI Status Bit 698" "Low,High" textline " " bitfld.long 0x00 25. " SPIS697 ,SPI Status Bit 697" "Low,High" bitfld.long 0x00 24. " SPIS696 ,SPI Status Bit 696" "Low,High" bitfld.long 0x00 23. " SPIS695 ,SPI Status Bit 695" "Low,High" textline " " bitfld.long 0x00 22. " SPIS694 ,SPI Status Bit 694" "Low,High" bitfld.long 0x00 21. " SPIS693 ,SPI Status Bit 693" "Low,High" bitfld.long 0x00 20. " SPIS692 ,SPI Status Bit 692" "Low,High" textline " " bitfld.long 0x00 19. " SPIS691 ,SPI Status Bit 691" "Low,High" bitfld.long 0x00 18. " SPIS690 ,SPI Status Bit 690" "Low,High" bitfld.long 0x00 17. " SPIS689 ,SPI Status Bit 689" "Low,High" textline " " bitfld.long 0x00 16. " SPIS688 ,SPI Status Bit 688" "Low,High" bitfld.long 0x00 15. " SPIS687 ,SPI Status Bit 687" "Low,High" bitfld.long 0x00 14. " SPIS686 ,SPI Status Bit 686" "Low,High" textline " " bitfld.long 0x00 13. " SPIS685 ,SPI Status Bit 685" "Low,High" bitfld.long 0x00 12. " SPIS684 ,SPI Status Bit 684" "Low,High" bitfld.long 0x00 11. " SPIS683 ,SPI Status Bit 683" "Low,High" textline " " bitfld.long 0x00 10. " SPIS682 ,SPI Status Bit 682" "Low,High" bitfld.long 0x00 9. " SPIS681 ,SPI Status Bit 681" "Low,High" bitfld.long 0x00 8. " SPIS680 ,SPI Status Bit 680" "Low,High" textline " " bitfld.long 0x00 7. " SPIS679 ,SPI Status Bit 679" "Low,High" bitfld.long 0x00 6. " SPIS678 ,SPI Status Bit 678" "Low,High" bitfld.long 0x00 5. " SPIS677 ,SPI Status Bit 677" "Low,High" textline " " bitfld.long 0x00 4. " SPIS676 ,SPI Status Bit 676" "Low,High" bitfld.long 0x00 3. " SPIS675 ,SPI Status Bit 675" "Low,High" bitfld.long 0x00 2. " SPIS674 ,SPI Status Bit 674" "Low,High" textline " " bitfld.long 0x00 1. " SPIS673 ,SPI Status Bit 673" "Low,High" bitfld.long 0x00 0. " SPIS672 ,SPI Status Bit 672" "Low,High" else hgroup.long 0xC0D4++0x03 hide.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) rgroup.long 0xC0D8++0x03 line.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21" bitfld.long 0x00 31. " SPIS735 ,SPI Status Bit 735" "Low,High" bitfld.long 0x00 30. " SPIS734 ,SPI Status Bit 734" "Low,High" bitfld.long 0x00 29. " SPIS733 ,SPI Status Bit 733" "Low,High" textline " " bitfld.long 0x00 28. " SPIS732 ,SPI Status Bit 732" "Low,High" bitfld.long 0x00 27. " SPIS731 ,SPI Status Bit 731" "Low,High" bitfld.long 0x00 26. " SPIS730 ,SPI Status Bit 730" "Low,High" textline " " bitfld.long 0x00 25. " SPIS729 ,SPI Status Bit 729" "Low,High" bitfld.long 0x00 24. " SPIS728 ,SPI Status Bit 728" "Low,High" bitfld.long 0x00 23. " SPIS727 ,SPI Status Bit 727" "Low,High" textline " " bitfld.long 0x00 22. " SPIS726 ,SPI Status Bit 726" "Low,High" bitfld.long 0x00 21. " SPIS725 ,SPI Status Bit 725" "Low,High" bitfld.long 0x00 20. " SPIS724 ,SPI Status Bit 724" "Low,High" textline " " bitfld.long 0x00 19. " SPIS723 ,SPI Status Bit 723" "Low,High" bitfld.long 0x00 18. " SPIS722 ,SPI Status Bit 722" "Low,High" bitfld.long 0x00 17. " SPIS721 ,SPI Status Bit 721" "Low,High" textline " " bitfld.long 0x00 16. " SPIS720 ,SPI Status Bit 720" "Low,High" bitfld.long 0x00 15. " SPIS719 ,SPI Status Bit 719" "Low,High" bitfld.long 0x00 14. " SPIS718 ,SPI Status Bit 718" "Low,High" textline " " bitfld.long 0x00 13. " SPIS717 ,SPI Status Bit 717" "Low,High" bitfld.long 0x00 12. " SPIS716 ,SPI Status Bit 716" "Low,High" bitfld.long 0x00 11. " SPIS715 ,SPI Status Bit 715" "Low,High" textline " " bitfld.long 0x00 10. " SPIS714 ,SPI Status Bit 714" "Low,High" bitfld.long 0x00 9. " SPIS713 ,SPI Status Bit 713" "Low,High" bitfld.long 0x00 8. " SPIS712 ,SPI Status Bit 712" "Low,High" textline " " bitfld.long 0x00 7. " SPIS711 ,SPI Status Bit 711" "Low,High" bitfld.long 0x00 6. " SPIS710 ,SPI Status Bit 710" "Low,High" bitfld.long 0x00 5. " SPIS709 ,SPI Status Bit 709" "Low,High" textline " " bitfld.long 0x00 4. " SPIS708 ,SPI Status Bit 708" "Low,High" bitfld.long 0x00 3. " SPIS707 ,SPI Status Bit 707" "Low,High" bitfld.long 0x00 2. " SPIS706 ,SPI Status Bit 706" "Low,High" textline " " bitfld.long 0x00 1. " SPIS705 ,SPI Status Bit 705" "Low,High" bitfld.long 0x00 0. " SPIS704 ,SPI Status Bit 704" "Low,High" else hgroup.long 0xC0D8++0x03 hide.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) rgroup.long 0xC0DC++0x03 line.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22" bitfld.long 0x00 31. " SPIS767 ,SPI Status Bit 767" "Low,High" bitfld.long 0x00 30. " SPIS766 ,SPI Status Bit 766" "Low,High" bitfld.long 0x00 29. " SPIS765 ,SPI Status Bit 765" "Low,High" textline " " bitfld.long 0x00 28. " SPIS764 ,SPI Status Bit 764" "Low,High" bitfld.long 0x00 27. " SPIS763 ,SPI Status Bit 763" "Low,High" bitfld.long 0x00 26. " SPIS762 ,SPI Status Bit 762" "Low,High" textline " " bitfld.long 0x00 25. " SPIS761 ,SPI Status Bit 761" "Low,High" bitfld.long 0x00 24. " SPIS760 ,SPI Status Bit 760" "Low,High" bitfld.long 0x00 23. " SPIS759 ,SPI Status Bit 759" "Low,High" textline " " bitfld.long 0x00 22. " SPIS758 ,SPI Status Bit 758" "Low,High" bitfld.long 0x00 21. " SPIS757 ,SPI Status Bit 757" "Low,High" bitfld.long 0x00 20. " SPIS756 ,SPI Status Bit 756" "Low,High" textline " " bitfld.long 0x00 19. " SPIS755 ,SPI Status Bit 755" "Low,High" bitfld.long 0x00 18. " SPIS754 ,SPI Status Bit 754" "Low,High" bitfld.long 0x00 17. " SPIS753 ,SPI Status Bit 753" "Low,High" textline " " bitfld.long 0x00 16. " SPIS752 ,SPI Status Bit 752" "Low,High" bitfld.long 0x00 15. " SPIS751 ,SPI Status Bit 751" "Low,High" bitfld.long 0x00 14. " SPIS750 ,SPI Status Bit 750" "Low,High" textline " " bitfld.long 0x00 13. " SPIS749 ,SPI Status Bit 749" "Low,High" bitfld.long 0x00 12. " SPIS748 ,SPI Status Bit 748" "Low,High" bitfld.long 0x00 11. " SPIS747 ,SPI Status Bit 747" "Low,High" textline " " bitfld.long 0x00 10. " SPIS746 ,SPI Status Bit 746" "Low,High" bitfld.long 0x00 9. " SPIS745 ,SPI Status Bit 745" "Low,High" bitfld.long 0x00 8. " SPIS744 ,SPI Status Bit 744" "Low,High" textline " " bitfld.long 0x00 7. " SPIS743 ,SPI Status Bit 743" "Low,High" bitfld.long 0x00 6. " SPIS742 ,SPI Status Bit 742" "Low,High" bitfld.long 0x00 5. " SPIS741 ,SPI Status Bit 741" "Low,High" textline " " bitfld.long 0x00 4. " SPIS740 ,SPI Status Bit 740" "Low,High" bitfld.long 0x00 3. " SPIS739 ,SPI Status Bit 739" "Low,High" bitfld.long 0x00 2. " SPIS738 ,SPI Status Bit 738" "Low,High" textline " " bitfld.long 0x00 1. " SPIS737 ,SPI Status Bit 737" "Low,High" bitfld.long 0x00 0. " SPIS736 ,SPI Status Bit 736" "Low,High" else hgroup.long 0xC0DC++0x03 hide.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) rgroup.long 0xC0E0++0x03 line.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23" bitfld.long 0x00 31. " SPIS799 ,SPI Status Bit 799" "Low,High" bitfld.long 0x00 30. " SPIS798 ,SPI Status Bit 798" "Low,High" bitfld.long 0x00 29. " SPIS797 ,SPI Status Bit 797" "Low,High" textline " " bitfld.long 0x00 28. " SPIS796 ,SPI Status Bit 796" "Low,High" bitfld.long 0x00 27. " SPIS795 ,SPI Status Bit 795" "Low,High" bitfld.long 0x00 26. " SPIS794 ,SPI Status Bit 794" "Low,High" textline " " bitfld.long 0x00 25. " SPIS793 ,SPI Status Bit 793" "Low,High" bitfld.long 0x00 24. " SPIS792 ,SPI Status Bit 792" "Low,High" bitfld.long 0x00 23. " SPIS791 ,SPI Status Bit 791" "Low,High" textline " " bitfld.long 0x00 22. " SPIS790 ,SPI Status Bit 790" "Low,High" bitfld.long 0x00 21. " SPIS789 ,SPI Status Bit 789" "Low,High" bitfld.long 0x00 20. " SPIS788 ,SPI Status Bit 788" "Low,High" textline " " bitfld.long 0x00 19. " SPIS787 ,SPI Status Bit 787" "Low,High" bitfld.long 0x00 18. " SPIS786 ,SPI Status Bit 786" "Low,High" bitfld.long 0x00 17. " SPIS785 ,SPI Status Bit 785" "Low,High" textline " " bitfld.long 0x00 16. " SPIS784 ,SPI Status Bit 784" "Low,High" bitfld.long 0x00 15. " SPIS783 ,SPI Status Bit 783" "Low,High" bitfld.long 0x00 14. " SPIS782 ,SPI Status Bit 782" "Low,High" textline " " bitfld.long 0x00 13. " SPIS781 ,SPI Status Bit 781" "Low,High" bitfld.long 0x00 12. " SPIS780 ,SPI Status Bit 780" "Low,High" bitfld.long 0x00 11. " SPIS779 ,SPI Status Bit 779" "Low,High" textline " " bitfld.long 0x00 10. " SPIS778 ,SPI Status Bit 778" "Low,High" bitfld.long 0x00 9. " SPIS777 ,SPI Status Bit 777" "Low,High" bitfld.long 0x00 8. " SPIS776 ,SPI Status Bit 776" "Low,High" textline " " bitfld.long 0x00 7. " SPIS775 ,SPI Status Bit 775" "Low,High" bitfld.long 0x00 6. " SPIS774 ,SPI Status Bit 774" "Low,High" bitfld.long 0x00 5. " SPIS773 ,SPI Status Bit 773" "Low,High" textline " " bitfld.long 0x00 4. " SPIS772 ,SPI Status Bit 772" "Low,High" bitfld.long 0x00 3. " SPIS771 ,SPI Status Bit 771" "Low,High" bitfld.long 0x00 2. " SPIS770 ,SPI Status Bit 770" "Low,High" textline " " bitfld.long 0x00 1. " SPIS769 ,SPI Status Bit 769" "Low,High" bitfld.long 0x00 0. " SPIS768 ,SPI Status Bit 768" "Low,High" else hgroup.long 0xC0E0++0x03 hide.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) rgroup.long 0xC0E4++0x03 line.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24" bitfld.long 0x00 31. " SPIS831 ,SPI Status Bit 831" "Low,High" bitfld.long 0x00 30. " SPIS830 ,SPI Status Bit 830" "Low,High" bitfld.long 0x00 29. " SPIS829 ,SPI Status Bit 829" "Low,High" textline " " bitfld.long 0x00 28. " SPIS828 ,SPI Status Bit 828" "Low,High" bitfld.long 0x00 27. " SPIS827 ,SPI Status Bit 827" "Low,High" bitfld.long 0x00 26. " SPIS826 ,SPI Status Bit 826" "Low,High" textline " " bitfld.long 0x00 25. " SPIS825 ,SPI Status Bit 825" "Low,High" bitfld.long 0x00 24. " SPIS824 ,SPI Status Bit 824" "Low,High" bitfld.long 0x00 23. " SPIS823 ,SPI Status Bit 823" "Low,High" textline " " bitfld.long 0x00 22. " SPIS822 ,SPI Status Bit 822" "Low,High" bitfld.long 0x00 21. " SPIS821 ,SPI Status Bit 821" "Low,High" bitfld.long 0x00 20. " SPIS820 ,SPI Status Bit 820" "Low,High" textline " " bitfld.long 0x00 19. " SPIS819 ,SPI Status Bit 819" "Low,High" bitfld.long 0x00 18. " SPIS818 ,SPI Status Bit 818" "Low,High" bitfld.long 0x00 17. " SPIS817 ,SPI Status Bit 817" "Low,High" textline " " bitfld.long 0x00 16. " SPIS816 ,SPI Status Bit 816" "Low,High" bitfld.long 0x00 15. " SPIS815 ,SPI Status Bit 815" "Low,High" bitfld.long 0x00 14. " SPIS814 ,SPI Status Bit 814" "Low,High" textline " " bitfld.long 0x00 13. " SPIS813 ,SPI Status Bit 813" "Low,High" bitfld.long 0x00 12. " SPIS812 ,SPI Status Bit 812" "Low,High" bitfld.long 0x00 11. " SPIS811 ,SPI Status Bit 811" "Low,High" textline " " bitfld.long 0x00 10. " SPIS810 ,SPI Status Bit 810" "Low,High" bitfld.long 0x00 9. " SPIS809 ,SPI Status Bit 809" "Low,High" bitfld.long 0x00 8. " SPIS808 ,SPI Status Bit 808" "Low,High" textline " " bitfld.long 0x00 7. " SPIS807 ,SPI Status Bit 807" "Low,High" bitfld.long 0x00 6. " SPIS806 ,SPI Status Bit 806" "Low,High" bitfld.long 0x00 5. " SPIS805 ,SPI Status Bit 805" "Low,High" textline " " bitfld.long 0x00 4. " SPIS804 ,SPI Status Bit 804" "Low,High" bitfld.long 0x00 3. " SPIS803 ,SPI Status Bit 803" "Low,High" bitfld.long 0x00 2. " SPIS802 ,SPI Status Bit 802" "Low,High" textline " " bitfld.long 0x00 1. " SPIS801 ,SPI Status Bit 801" "Low,High" bitfld.long 0x00 0. " SPIS800 ,SPI Status Bit 800" "Low,High" else hgroup.long 0xC0E4++0x03 hide.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) rgroup.long 0xC0E8++0x03 line.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25" bitfld.long 0x00 31. " SPIS863 ,SPI Status Bit 863" "Low,High" bitfld.long 0x00 30. " SPIS862 ,SPI Status Bit 862" "Low,High" bitfld.long 0x00 29. " SPIS861 ,SPI Status Bit 861" "Low,High" textline " " bitfld.long 0x00 28. " SPIS860 ,SPI Status Bit 860" "Low,High" bitfld.long 0x00 27. " SPIS859 ,SPI Status Bit 859" "Low,High" bitfld.long 0x00 26. " SPIS858 ,SPI Status Bit 858" "Low,High" textline " " bitfld.long 0x00 25. " SPIS857 ,SPI Status Bit 857" "Low,High" bitfld.long 0x00 24. " SPIS856 ,SPI Status Bit 856" "Low,High" bitfld.long 0x00 23. " SPIS855 ,SPI Status Bit 855" "Low,High" textline " " bitfld.long 0x00 22. " SPIS854 ,SPI Status Bit 854" "Low,High" bitfld.long 0x00 21. " SPIS853 ,SPI Status Bit 853" "Low,High" bitfld.long 0x00 20. " SPIS852 ,SPI Status Bit 852" "Low,High" textline " " bitfld.long 0x00 19. " SPIS851 ,SPI Status Bit 851" "Low,High" bitfld.long 0x00 18. " SPIS850 ,SPI Status Bit 850" "Low,High" bitfld.long 0x00 17. " SPIS849 ,SPI Status Bit 849" "Low,High" textline " " bitfld.long 0x00 16. " SPIS848 ,SPI Status Bit 848" "Low,High" bitfld.long 0x00 15. " SPIS847 ,SPI Status Bit 847" "Low,High" bitfld.long 0x00 14. " SPIS846 ,SPI Status Bit 846" "Low,High" textline " " bitfld.long 0x00 13. " SPIS845 ,SPI Status Bit 845" "Low,High" bitfld.long 0x00 12. " SPIS844 ,SPI Status Bit 844" "Low,High" bitfld.long 0x00 11. " SPIS843 ,SPI Status Bit 843" "Low,High" textline " " bitfld.long 0x00 10. " SPIS842 ,SPI Status Bit 842" "Low,High" bitfld.long 0x00 9. " SPIS841 ,SPI Status Bit 841" "Low,High" bitfld.long 0x00 8. " SPIS840 ,SPI Status Bit 840" "Low,High" textline " " bitfld.long 0x00 7. " SPIS839 ,SPI Status Bit 839" "Low,High" bitfld.long 0x00 6. " SPIS838 ,SPI Status Bit 838" "Low,High" bitfld.long 0x00 5. " SPIS837 ,SPI Status Bit 837" "Low,High" textline " " bitfld.long 0x00 4. " SPIS836 ,SPI Status Bit 836" "Low,High" bitfld.long 0x00 3. " SPIS835 ,SPI Status Bit 835" "Low,High" bitfld.long 0x00 2. " SPIS834 ,SPI Status Bit 834" "Low,High" textline " " bitfld.long 0x00 1. " SPIS833 ,SPI Status Bit 833" "Low,High" bitfld.long 0x00 0. " SPIS832 ,SPI Status Bit 832" "Low,High" else hgroup.long 0xC0E8++0x03 hide.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) rgroup.long 0xC0EC++0x03 line.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26" bitfld.long 0x00 31. " SPIS895 ,SPI Status Bit 895" "Low,High" bitfld.long 0x00 30. " SPIS894 ,SPI Status Bit 894" "Low,High" bitfld.long 0x00 29. " SPIS893 ,SPI Status Bit 893" "Low,High" textline " " bitfld.long 0x00 28. " SPIS892 ,SPI Status Bit 892" "Low,High" bitfld.long 0x00 27. " SPIS891 ,SPI Status Bit 891" "Low,High" bitfld.long 0x00 26. " SPIS890 ,SPI Status Bit 890" "Low,High" textline " " bitfld.long 0x00 25. " SPIS889 ,SPI Status Bit 889" "Low,High" bitfld.long 0x00 24. " SPIS888 ,SPI Status Bit 888" "Low,High" bitfld.long 0x00 23. " SPIS887 ,SPI Status Bit 887" "Low,High" textline " " bitfld.long 0x00 22. " SPIS886 ,SPI Status Bit 886" "Low,High" bitfld.long 0x00 21. " SPIS885 ,SPI Status Bit 885" "Low,High" bitfld.long 0x00 20. " SPIS884 ,SPI Status Bit 884" "Low,High" textline " " bitfld.long 0x00 19. " SPIS883 ,SPI Status Bit 883" "Low,High" bitfld.long 0x00 18. " SPIS882 ,SPI Status Bit 882" "Low,High" bitfld.long 0x00 17. " SPIS881 ,SPI Status Bit 881" "Low,High" textline " " bitfld.long 0x00 16. " SPIS880 ,SPI Status Bit 880" "Low,High" bitfld.long 0x00 15. " SPIS879 ,SPI Status Bit 879" "Low,High" bitfld.long 0x00 14. " SPIS878 ,SPI Status Bit 878" "Low,High" textline " " bitfld.long 0x00 13. " SPIS877 ,SPI Status Bit 877" "Low,High" bitfld.long 0x00 12. " SPIS876 ,SPI Status Bit 876" "Low,High" bitfld.long 0x00 11. " SPIS875 ,SPI Status Bit 875" "Low,High" textline " " bitfld.long 0x00 10. " SPIS874 ,SPI Status Bit 874" "Low,High" bitfld.long 0x00 9. " SPIS873 ,SPI Status Bit 873" "Low,High" bitfld.long 0x00 8. " SPIS872 ,SPI Status Bit 872" "Low,High" textline " " bitfld.long 0x00 7. " SPIS871 ,SPI Status Bit 871" "Low,High" bitfld.long 0x00 6. " SPIS870 ,SPI Status Bit 870" "Low,High" bitfld.long 0x00 5. " SPIS869 ,SPI Status Bit 869" "Low,High" textline " " bitfld.long 0x00 4. " SPIS868 ,SPI Status Bit 868" "Low,High" bitfld.long 0x00 3. " SPIS867 ,SPI Status Bit 867" "Low,High" bitfld.long 0x00 2. " SPIS866 ,SPI Status Bit 866" "Low,High" textline " " bitfld.long 0x00 1. " SPIS865 ,SPI Status Bit 865" "Low,High" bitfld.long 0x00 0. " SPIS864 ,SPI Status Bit 864" "Low,High" else hgroup.long 0xC0EC++0x03 hide.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) rgroup.long 0xC0F0++0x03 line.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27" bitfld.long 0x00 31. " SPIS927 ,SPI Status Bit 927" "Low,High" bitfld.long 0x00 30. " SPIS926 ,SPI Status Bit 926" "Low,High" bitfld.long 0x00 29. " SPIS925 ,SPI Status Bit 925" "Low,High" textline " " bitfld.long 0x00 28. " SPIS924 ,SPI Status Bit 924" "Low,High" bitfld.long 0x00 27. " SPIS923 ,SPI Status Bit 923" "Low,High" bitfld.long 0x00 26. " SPIS922 ,SPI Status Bit 922" "Low,High" textline " " bitfld.long 0x00 25. " SPIS921 ,SPI Status Bit 921" "Low,High" bitfld.long 0x00 24. " SPIS920 ,SPI Status Bit 920" "Low,High" bitfld.long 0x00 23. " SPIS919 ,SPI Status Bit 919" "Low,High" textline " " bitfld.long 0x00 22. " SPIS918 ,SPI Status Bit 918" "Low,High" bitfld.long 0x00 21. " SPIS917 ,SPI Status Bit 917" "Low,High" bitfld.long 0x00 20. " SPIS916 ,SPI Status Bit 916" "Low,High" textline " " bitfld.long 0x00 19. " SPIS915 ,SPI Status Bit 915" "Low,High" bitfld.long 0x00 18. " SPIS914 ,SPI Status Bit 914" "Low,High" bitfld.long 0x00 17. " SPIS913 ,SPI Status Bit 913" "Low,High" textline " " bitfld.long 0x00 16. " SPIS912 ,SPI Status Bit 912" "Low,High" bitfld.long 0x00 15. " SPIS911 ,SPI Status Bit 911" "Low,High" bitfld.long 0x00 14. " SPIS910 ,SPI Status Bit 910" "Low,High" textline " " bitfld.long 0x00 13. " SPIS909 ,SPI Status Bit 909" "Low,High" bitfld.long 0x00 12. " SPIS908 ,SPI Status Bit 908" "Low,High" bitfld.long 0x00 11. " SPIS907 ,SPI Status Bit 907" "Low,High" textline " " bitfld.long 0x00 10. " SPIS906 ,SPI Status Bit 906" "Low,High" bitfld.long 0x00 9. " SPIS905 ,SPI Status Bit 905" "Low,High" bitfld.long 0x00 8. " SPIS904 ,SPI Status Bit 904" "Low,High" textline " " bitfld.long 0x00 7. " SPIS903 ,SPI Status Bit 903" "Low,High" bitfld.long 0x00 6. " SPIS902 ,SPI Status Bit 902" "Low,High" bitfld.long 0x00 5. " SPIS901 ,SPI Status Bit 901" "Low,High" textline " " bitfld.long 0x00 4. " SPIS900 ,SPI Status Bit 900" "Low,High" bitfld.long 0x00 3. " SPIS899 ,SPI Status Bit 899" "Low,High" bitfld.long 0x00 2. " SPIS898 ,SPI Status Bit 898" "Low,High" textline " " bitfld.long 0x00 1. " SPIS897 ,SPI Status Bit 897" "Low,High" bitfld.long 0x00 0. " SPIS896 ,SPI Status Bit 896" "Low,High" else hgroup.long 0xC0F0++0x03 hide.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) rgroup.long 0xC0F4++0x03 line.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28" bitfld.long 0x00 31. " SPIS959 ,SPI Status Bit 959" "Low,High" bitfld.long 0x00 30. " SPIS958 ,SPI Status Bit 958" "Low,High" bitfld.long 0x00 29. " SPIS957 ,SPI Status Bit 957" "Low,High" textline " " bitfld.long 0x00 28. " SPIS956 ,SPI Status Bit 956" "Low,High" bitfld.long 0x00 27. " SPIS955 ,SPI Status Bit 955" "Low,High" bitfld.long 0x00 26. " SPIS954 ,SPI Status Bit 954" "Low,High" textline " " bitfld.long 0x00 25. " SPIS953 ,SPI Status Bit 953" "Low,High" bitfld.long 0x00 24. " SPIS952 ,SPI Status Bit 952" "Low,High" bitfld.long 0x00 23. " SPIS951 ,SPI Status Bit 951" "Low,High" textline " " bitfld.long 0x00 22. " SPIS950 ,SPI Status Bit 950" "Low,High" bitfld.long 0x00 21. " SPIS949 ,SPI Status Bit 949" "Low,High" bitfld.long 0x00 20. " SPIS948 ,SPI Status Bit 948" "Low,High" textline " " bitfld.long 0x00 19. " SPIS947 ,SPI Status Bit 947" "Low,High" bitfld.long 0x00 18. " SPIS946 ,SPI Status Bit 946" "Low,High" bitfld.long 0x00 17. " SPIS945 ,SPI Status Bit 945" "Low,High" textline " " bitfld.long 0x00 16. " SPIS944 ,SPI Status Bit 944" "Low,High" bitfld.long 0x00 15. " SPIS943 ,SPI Status Bit 943" "Low,High" bitfld.long 0x00 14. " SPIS942 ,SPI Status Bit 942" "Low,High" textline " " bitfld.long 0x00 13. " SPIS941 ,SPI Status Bit 941" "Low,High" bitfld.long 0x00 12. " SPIS940 ,SPI Status Bit 940" "Low,High" bitfld.long 0x00 11. " SPIS939 ,SPI Status Bit 939" "Low,High" textline " " bitfld.long 0x00 10. " SPIS938 ,SPI Status Bit 938" "Low,High" bitfld.long 0x00 9. " SPIS937 ,SPI Status Bit 937" "Low,High" bitfld.long 0x00 8. " SPIS936 ,SPI Status Bit 936" "Low,High" textline " " bitfld.long 0x00 7. " SPIS935 ,SPI Status Bit 935" "Low,High" bitfld.long 0x00 6. " SPIS934 ,SPI Status Bit 934" "Low,High" bitfld.long 0x00 5. " SPIS933 ,SPI Status Bit 933" "Low,High" textline " " bitfld.long 0x00 4. " SPIS932 ,SPI Status Bit 932" "Low,High" bitfld.long 0x00 3. " SPIS931 ,SPI Status Bit 931" "Low,High" bitfld.long 0x00 2. " SPIS930 ,SPI Status Bit 930" "Low,High" textline " " bitfld.long 0x00 1. " SPIS929 ,SPI Status Bit 929" "Low,High" bitfld.long 0x00 0. " SPIS928 ,SPI Status Bit 928" "Low,High" else hgroup.long 0xC0F4++0x03 hide.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) rgroup.long 0xC0F8++0x03 line.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29" bitfld.long 0x00 31. " SPIS991 ,SPI Status Bit 991" "Low,High" bitfld.long 0x00 30. " SPIS990 ,SPI Status Bit 990" "Low,High" bitfld.long 0x00 29. " SPIS989 ,SPI Status Bit 989" "Low,High" textline " " bitfld.long 0x00 28. " SPIS988 ,SPI Status Bit 988" "Low,High" bitfld.long 0x00 27. " SPIS987 ,SPI Status Bit 987" "Low,High" bitfld.long 0x00 26. " SPIS986 ,SPI Status Bit 986" "Low,High" textline " " bitfld.long 0x00 25. " SPIS985 ,SPI Status Bit 985" "Low,High" bitfld.long 0x00 24. " SPIS984 ,SPI Status Bit 984" "Low,High" bitfld.long 0x00 23. " SPIS983 ,SPI Status Bit 983" "Low,High" textline " " bitfld.long 0x00 22. " SPIS982 ,SPI Status Bit 982" "Low,High" bitfld.long 0x00 21. " SPIS981 ,SPI Status Bit 981" "Low,High" bitfld.long 0x00 20. " SPIS980 ,SPI Status Bit 980" "Low,High" textline " " bitfld.long 0x00 19. " SPIS979 ,SPI Status Bit 979" "Low,High" bitfld.long 0x00 18. " SPIS978 ,SPI Status Bit 978" "Low,High" bitfld.long 0x00 17. " SPIS977 ,SPI Status Bit 977" "Low,High" textline " " bitfld.long 0x00 16. " SPIS976 ,SPI Status Bit 976" "Low,High" bitfld.long 0x00 15. " SPIS975 ,SPI Status Bit 975" "Low,High" bitfld.long 0x00 14. " SPIS974 ,SPI Status Bit 974" "Low,High" textline " " bitfld.long 0x00 13. " SPIS973 ,SPI Status Bit 973" "Low,High" bitfld.long 0x00 12. " SPIS972 ,SPI Status Bit 972" "Low,High" bitfld.long 0x00 11. " SPIS971 ,SPI Status Bit 971" "Low,High" textline " " bitfld.long 0x00 10. " SPIS970 ,SPI Status Bit 970" "Low,High" bitfld.long 0x00 9. " SPIS969 ,SPI Status Bit 969" "Low,High" bitfld.long 0x00 8. " SPIS968 ,SPI Status Bit 968" "Low,High" textline " " bitfld.long 0x00 7. " SPIS967 ,SPI Status Bit 967" "Low,High" bitfld.long 0x00 6. " SPIS966 ,SPI Status Bit 966" "Low,High" bitfld.long 0x00 5. " SPIS965 ,SPI Status Bit 965" "Low,High" textline " " bitfld.long 0x00 4. " SPIS964 ,SPI Status Bit 964" "Low,High" bitfld.long 0x00 3. " SPIS963 ,SPI Status Bit 963" "Low,High" bitfld.long 0x00 2. " SPIS962 ,SPI Status Bit 962" "Low,High" textline " " bitfld.long 0x00 1. " SPIS961 ,SPI Status Bit 961" "Low,High" bitfld.long 0x00 0. " SPIS960 ,SPI Status Bit 960" "Low,High" else hgroup.long 0xC0F8++0x03 hide.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29" endif tree.end width 12. tree "Peripheral/Component ID Registers" rgroup.long 0xFFE0++0x03 line.long 0x00 "GICD_PIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_0 ,Part number[7:0]" rgroup.long 0xFFE4++0x03 line.long 0x00 "GICD_PIDR1,Peripheral ID1 Register" bitfld.long 0x00 4.--7. " DES_1 ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PART_1 , Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFE8++0x03 line.long 0x00 "GICD_PIDR2,Peripheral ID2 Register" bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..." bitfld.long 0x00 3. " JEDEC ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Not Used,Used" bitfld.long 0x00 0.--2. " DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7" rgroup.long 0xFFEC++0x03 line.long 0x00 "GICD_PIDR3,Peripheral ID3 Register" bitfld.long 0x00 4.--7. " REVAND ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CMOD ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFD0++0x03 line.long 0x00 "GICD_PIDR4,Peripheral ID4 Register" bitfld.long 0x00 4.--7. " SIZE ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DES_2 ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0xFFD4++0x03 hide.long 0x00 "GICD_PIDR5,Peripheral ID5 Register" hgroup.long 0xFFD8++0x03 hide.long 0x00 "GICD_PIDR6,Peripheral ID6 Register" hgroup.long 0xFFDC++0x03 hide.long 0x00 "GICD_PIDR7,Peripheral ID7 Register" rgroup.long 0xFFF0++0x03 line.long 0x00 "GICD_CIDR0,Component ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF4++0x03 line.long 0x00 "GICD_CIDR1,Component ID1 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF8++0x03 line.long 0x00 "GICD_CIDR2,Component ID2 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFFC++0x03 line.long 0x00 "GICD_CIDR3,Component ID3 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" tree.end tree.end width 0x0B base (COMP.BASE("GICD",-1.)+0x20000) width 24. tree "Interrupt Translation Service" group.long 0x00++0x03 line.long 0x00 "GITS_CTLR,ITS Control Register" rbitfld.long 0x00 31. " QUIESCENT ,Indicates completion of all ITS operations" "Not quiescent,Quiescent" bitfld.long 0x00 0. " ENABLED ,Controls whether the ITS is enabled" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "GITS_IIDR,ITS Implementer Identification Register" bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "GIC-500,?..." bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" if (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0x1000000000)==0x1000000000)&&(((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0xFF000000)!=0x00) rgroup.quad 0x08++0x07 line.quad 0x00 "GITS_TYPER,ITS Type Register" bitfld.quad 0x00 37. " VMOVP ,Indicates the form of the VMOVP command" "All ITSs,One ITS" bitfld.quad 0x00 36. " CIL ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value" textline " " bitfld.quad 0x00 32.--35. " CIDBITS ,Number of Collection ID bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 24.--31. 1. " HCC ,Hardware Collection Count" textline " " bitfld.quad 0x00 19. " PTA ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address" bitfld.quad 0x00 18. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported" textline " " bitfld.quad 0x00 13.--17. " DEVBITS ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 8.--12. " ID_BITS ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 2. " CCT ,Cumulative Collection Tables" "0,1" elif (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0x1000000000)==0x1000000000) rgroup.quad 0x08++0x07 line.quad 0x00 "GITS_TYPER,ITS Type Register" bitfld.quad 0x00 37. " VMOVP ,Indicates the form of the VMOVP command" "All ITSs,One ITS" bitfld.quad 0x00 36. " CIL ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value" textline " " bitfld.quad 0x00 32.--35. " CIDBITS ,Number of Collection ID bits minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 24.--31. 1. " HCC ,Hardware Collection Count" textline " " bitfld.quad 0x00 19. " PTA ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address" bitfld.quad 0x00 18. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported" textline " " bitfld.quad 0x00 13.--17. " DEVBITS ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 8.--12. " ID_BITS ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0xFF000000)!=0x00) rgroup.quad 0x08++0x07 line.quad 0x00 "GITS_TYPER,ITS Type Register" bitfld.quad 0x00 37. " VMOVP ,Indicates the form of the VMOVP command" "All ITSs,One ITS" bitfld.quad 0x00 36. " CIL ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value" textline " " hexmask.quad.byte 0x00 24.--31. 1. " HCC ,Hardware Collection Count" bitfld.quad 0x00 19. " PTA ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address" textline " " bitfld.quad 0x00 18. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported" bitfld.quad 0x00 13.--17. " DEVBITS ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.quad 0x00 8.--12. " ID_BITS ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.quad 0x00 2. " CCT ,Cumulative Collection Tables" "0,1" else rgroup.quad 0x08++0x07 line.quad 0x00 "GITS_TYPER,ITS Type Register" bitfld.quad 0x00 37. " VMOVP ,Indicates the form of the VMOVP command" "All ITSs,One ITS" bitfld.quad 0x00 36. " CIL ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value" textline " " hexmask.quad.byte 0x00 24.--31. 1. " HCC ,Hardware Collection Count" bitfld.quad 0x00 19. " PTA ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address" textline " " bitfld.quad 0x00 18. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported" bitfld.quad 0x00 13.--17. " DEVBITS ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.quad 0x00 8.--12. " ID_BITS ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.quad 0x80++0x07 line.quad 0x00 "GITS_CBASER,The command queue control register" bitfld.quad 0x00 63. " VALID ,Indicates whether software has allocated memory for the command queue" "Not allocated,Allocated" bitfld.quad 0x00 59.--61. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the command queue" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" textline " " bitfld.quad 0x00 53.--55. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the command queue" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" hexmask.quad 0x00 12.--51. 0x10 " PHYSICAL_ADDRESS ,Bits [51:12] of the base physical address of the command queue" textline " " bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the command queue" "Non-shareable,Inner Shareable,Outer Shareable,?..." hexmask.quad.byte 0x00 0.--7. 1. " SIZE ,The number of 4KB pages of physical memory allocated to the command queue minus one" group.quad 0x88++0x7 line.quad 0x00 "GITS_CWRITER,The command queue write pointer" hexmask.quad.word 0x00 5.--19. 0x20 " OFFSET ,Bits [19:5] of the offset from GITS_CBASER" bitfld.quad 0x00 0. " RETRY ,Restarts the processing of commands by the ITS if it stalled because of a command error" "No effect,Restarted" group.quad 0x90++0x07 line.quad 0x00 "GITS_CREADR,The command queue read pointer" hexmask.quad.word 0x00 5.--19. 0x20 " OFFSET ,Bits [19:5] of the offset from GITS_CBASER" bitfld.quad 0x00 0. " STALLED ,Reports whether the processing of commands is stalled because of a command error" "Not stalled,Stalled" if (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0100))&0x700000000000000)==0x00) group.quad 0x100++0x07 line.quad 0x00 "GITS_BASER0,ITS table control register" bitfld.quad 0x00 63. " VALID ,Indicates whether software has allocated memory for the translation table" "Not allocated,Allocated" bitfld.quad 0x00 62. " INDIRECT ,This field indicates whether an implemented register specifies a single flat table or a two-level table where the first level contains a list of descriptors" "Single Level,Two Level" textline " " bitfld.quad 0x00 59.--61. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" rbitfld.quad 0x00 56.--58. " TYPE ,Specifies the type of entity that requires entries in the corresponding translation table" "Unimplemented,Devices,Reserved,Reserved,Interrupt collections,?..." textline " " bitfld.quad 0x00 53.--55. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" rbitfld.quad 0x00 48.--52. " ENTRY_SIZE ,Specifies the number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.quad 0x00 12.--47. 1. " PHYSICAL_ADDRESS ,Physical Address" bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the table" "Non-shareable,Inner Shareable,Outer Shareable,?..." textline " " bitfld.quad 0x00 8.--9. " PAGE_SIZE ,The size of page that the translation table uses" "4KB,16KB,64KB,?..." else group.quad 0x100++0x07 line.quad 0x00 "GITS_BASER0,ITS table control register" bitfld.quad 0x00 63. " VALID ,Indicates whether software has allocated memory for the translation table" "Not allocated,Allocated" bitfld.quad 0x00 62. " INDIRECT ,This field indicates whether an implemented register specifies a single flat table or a two-level table where the first level contains a list of descriptors" "Single Level,Two Level" textline " " bitfld.quad 0x00 59.--61. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" rbitfld.quad 0x00 56.--58. " TYPE ,Specifies the type of entity that requires entries in the corresponding translation table" "Unimplemented,Devices,Reserved,Reserved,Interrupt collections,?..." textline " " bitfld.quad 0x00 53.--55. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" rbitfld.quad 0x00 48.--52. " ENTRY_SIZE ,Specifies the number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.quad 0x00 12.--47. 0x10 " PHYSICAL_ADDRESS ,Physical Address" bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the table" "Non-shareable,Inner Shareable,Outer Shareable,?..." textline " " bitfld.quad 0x00 8.--9. " PAGE_SIZE ,The size of page that the translation table uses" "4KB,16KB,64KB,?..." hexmask.quad.byte 0x00 0.--7. 1. " SIZE ,The number of pages of physical memory allocated to the table minus one" endif textline " " wgroup.long 0xC000++0x03 line.long 0x00 "GITS_TRKCTLR,Tracking Control Register" bitfld.long 0x00 1. " LPI_TRACK ,Write 0b1 to capture information about the next interrupt that the ITS generated or failed to generate because of misprogramming" "No effect,Capture" bitfld.long 0x00 0. " CACHE_COUNT_RESET ,Write 0b1 to reset the cache hit and miss counters in GITS_TRKICR and GITS_TRKLCR" "No effect,Reset" if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x1F)==0x01) rgroup.long 0xC004++0x03 line.long 0x00 "GITS_TRKR,Tracking Status Register" bitfld.long 0x00 6. " PID_OUT_OF_RANGE ,Indicates that the LPI PID is larger than that allowed by the IDbits field in the GICR_PROPBASER" "0,1" bitfld.long 0x00 5. " TARGET_OUT_OF_RANGE ,Indicates that target collection has not been successfully mapped using MAPC or that the target core does not have LPIs enabled in GICR_CTLR" "0,1" textline " " bitfld.long 0x00 4. " NO_TRANSLATION ,Indicates that no valid MAPI or MAPVI has successfully been performed for this combination of input ID and Device ID" "0,1" bitfld.long 0x00 3. " INPUT_ID_OUT_OF_RANGE ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1" textline " " bitfld.long 0x00 2. " DEVICE_ID_UNMAPPED ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1" bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1" textline " " bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid" elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0xF)==0x01) rgroup.long 0xC004++0x03 line.long 0x00 "GITS_TRKR,Tracking Status Register" bitfld.long 0x00 4. " NO_TRANSLATION ,Indicates that no valid MAPI or MAPVI has successfully been performed for this combination of input ID and Device ID" "0,1" bitfld.long 0x00 3. " INPUT_ID_OUT_OF_RANGE ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1" textline " " bitfld.long 0x00 2. " DEVICE_ID_UNMAPPED ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1" bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1" textline " " bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid" elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7)==0x01) rgroup.long 0xC004++0x03 line.long 0x00 "GITS_TRKR,Tracking Status Register" bitfld.long 0x00 3. " INPUT_ID_OUT_OF_RANGE ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1" bitfld.long 0x00 2. " DEVICE_ID_UNMAPPED ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1" textline " " bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1" bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid" elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x3)==0x01) rgroup.long 0xC004++0x03 line.long 0x00 "GITS_TRKR,Tracking Status Register" bitfld.long 0x00 2. " DEVICE_ID_UNMAPPED ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1" bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1" textline " " bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid" else rgroup.long 0xC004++0x03 line.long 0x00 "GITS_TRKR,Tracking Status Register" bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1" bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid" endif if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x01)==0x01) rgroup.long 0xC008++0x03 line.long 0x00 "GITS_TRKDIDR,Debug Tracked DID Register" hexmask.long.tbyte 0x00 0.--19. 1. " LPI_DID ,The Device ID for the interrupt that was tracked" else hgroup.long 0xC008++0x03 hide.long 0x00 "GITS_TRKDIDR,Debug Tracked DID Register" endif if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7F)==0x01) rgroup.long 0xC00C++0x03 line.long 0x00 "GITS_TRKPIDR,Debug Tracked PID Register" hexmask.long.word 0x00 0.--15. 1. " LPI_PID ,The ID after translation for an interrupt that was tracked and generated an LPI successfully" else hgroup.long 0xC00C++0x03 hide.long 0x00 "GITS_TRKPIDR,Debug Tracked PID Register" endif if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x01)==0x01) rgroup.long 0xC010++0x03 line.long 0x00 "GITS_TRKVIDR,Debug Tracked ID Register" hexmask.long.word 0x00 0.--15. 1. " LPI_ID ,The ID before translation of the interrupt that was tracked" else hgroup.long 0xC010++0x03 hide.long 0x00 "GITS_TRKVIDR,Debug Tracked ID Register" endif if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7F)==0x01) rgroup.long 0xC014++0x03 line.long 0x00 "GITS_TRKTGTR,Debug Tracked Target Register" hexmask.long.byte 0x00 0.--6. 1. " LPI_TARGET_CORE ,The target core for an interrupt that was tracked and generated an LPI successfully" else hgroup.long 0xC014++0x03 hide.long 0x00 "GITS_TRKTGTR,Debug Tracked Target Register" endif rgroup.long 0xC018++0x03 line.long 0x00 "GITS_TRKICR,Debug ITE Cache Statistics" hexmask.long.word 0x00 16.--31. 1. " ITE_CACHE_HITS ,Number of hits in the ITE cache" hexmask.long.word 0x00 0.--15. 1. " ITE_CACHE_MISSES ,Number of misses in the ITE cache" rgroup.long 0xC01C++0x03 line.long 0x00 "GITS_TRKLCR,Debug LPI Cache Statistics" hexmask.long.word 0x00 16.--31. 1. " LPI_CACHE_HITS ,Number of hits in the LPI cache" hexmask.long.word 0x00 0.--15. 1. " LPI_CACHE_MISSES ,Number of misses in the LPI cache" rgroup.long 0xFFE0++0x03 line.long 0x00 "GITS_PIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_0 ,Part number[7:0]" rgroup.long 0xFFE4++0x03 line.long 0x00 "GITS_PIDR1,Peripheral ID1 Register" bitfld.long 0x00 4.--7. " DES_1 ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PART_1 , Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFE8++0x03 line.long 0x00 "GITS_PIDR2,Peripheral ID2 Register" bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..." bitfld.long 0x00 3. " JEDEC ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Low,High" textline " " bitfld.long 0x00 0.--2. " DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7" rgroup.long 0xFFEC++0x03 line.long 0x00 "GITS_PIDR3,Peripheral ID3 Register" bitfld.long 0x00 4.--7. " REVAND ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CMOD ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFD0++0x03 line.long 0x00 "GITS_PIDR4,Peripheral ID4 Register" bitfld.long 0x00 4.--7. " SIZE ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DES_2 ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0xFFD4++0x03 hide.long 0x00 "GITS_PIDR5,Peripheral ID5 Register" hgroup.long 0xFFD8++0x03 hide.long 0x00 "GITS_PIDR6,Peripheral ID6 Register" hgroup.long 0xFFDC++0x03 hide.long 0x00 "GITS_PIDR7,Peripheral ID7 Register" rgroup.long 0xFFF0++0x03 line.long 0x00 "GITS_CIDR0,Component ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF4++0x03 line.long 0x00 "GITS_CIDR1,Component ID1 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF8++0x03 line.long 0x00 "GITS_CIDR2,Component ID2 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFFC++0x03 line.long 0x00 "GITS_CIDR3,Component ID3 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" textline " " base (COMP.BASE("GICD",-1.)+0x20000)+0x10000 if (((per.l((COMP.BASE("GICD",-1.)+0x20000)))&0x01)==0x01) wgroup.long 0x40++0x03 line.long 0x00 "GITS_TRANSLATER,ITS Translation Register" else hgroup.long 0x40++0x03 hide.long 0x00 "GITS_TRANSLATER,ITS Translation Register" endif tree.end width 0x0B base COMP.BASE("GICR",-1.) width 17. tree "Redistributor Interface" tree "Control Registers" if (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x21) group.long 0x0000++0x03 line.long 0x00 "GICR_CTLR,Redistributor Control Register" rbitfld.long 0x00 31. " UWP ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending" bitfld.long 0x00 26. " DPG1S ,Disable Processor selection for Group 1 Secure interrupts" "No,Yes" bitfld.long 0x00 25. " DPG1NS ,Disable Processor selection for Group 1 Non-secure interrupts" "No,Yes" textline " " bitfld.long 0x00 24. " DPG0 ,Disable Processor selection for Group 0 interrupts" "No,Yes" bitfld.long 0x00 3. " RWP ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending" bitfld.long 0x00 0. " ENABLE_LPIS ,Enables LPIs in implementations where affinity routing is enabled for Security state" "Disabled,Enabled" elif (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x20) group.long 0x0000++0x03 line.long 0x00 "GICR_CTLR,Redistributor Control Register" rbitfld.long 0x00 31. " UWP ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending" bitfld.long 0x00 26. " DPG1S ,Disable Processor selection for Group 1 Secure interrupts" "No,Yes" bitfld.long 0x00 25. " DPG1NS ,Disable Processor selection for Group 1 Non-secure interrupts" "No,Yes" textline " " bitfld.long 0x00 24. " DPG0 ,Disable Processor selection for Group 0 interrupts" "No,Yes" bitfld.long 0x00 3. " RWP ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending" elif (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x01) group.long 0x0000++0x03 line.long 0x00 "GICR_CTLR,Redistributor Control Register" rbitfld.long 0x00 31. " UWP ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending" bitfld.long 0x00 3. " RWP ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending" bitfld.long 0x00 0. " ENABLE_LPIS ,Enables LPIs in implementations where affinity routing is enabled for Security state" "Disabled,Enabled" else group.long 0x0000++0x03 line.long 0x00 "GICR_CTLR,Redistributor Control Register" rbitfld.long 0x00 31. " UWP ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending" bitfld.long 0x00 3. " RWP ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending" endif rgroup.long 0x0004++0x03 line.long 0x00 "GICR_IIDR,Distributor Implementer Identification Register" bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "GIC-500,?..." bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" rgroup.quad 0x0008++0x07 line.quad 0x00 "GICR_TYPER,Interrupt Controller Type Register" hexmask.quad.byte 0x00 56.--63. 1. " AFF3 ,Affinity level 3 value for the Redistributor" hexmask.quad.byte 0x00 48.--55. 1. " AFF2 ,Affinity level 2 value for the Redistributor" hexmask.quad.byte 0x00 40.--47. 1. " AFF1 ,Affinity level 1 value for the Redistributor" textline " " hexmask.quad.byte 0x00 32.--39. 1. " AFF0 ,Affinity level 0 value for the Redistributor" bitfld.quad 0x00 24.--25. " COMMONLPIAFF ,The affinity level at which Redistributors share a LPI Configuration table" "All levels,AFF3,AFF3/AFF2,AFF3/AFF2/AFF1" hexmask.quad.word 0x00 8.--23. 1. " PROCESSOR_NUMBER ,A unique identifier for the PE" textline " " bitfld.quad 0x00 5. " DPGS ,Sets support for GICR_CTLR.DPG* bits" "Not supported,Supported" bitfld.quad 0x00 4. " LAST ,Indicates whether this Redistributor is the highest-numbered Redistributor in a series of contiguous Redistributor pages" "Not highest,Highest" bitfld.quad 0x00 3. " DIRECTLPI ,Indicates whether this Redistributor supports direct injection of LPIs" "Not supported,Supported" textline " " bitfld.quad 0x00 0. " PLPIS ,Indicates whether the GIC implementation supports physical LPIs" "Not supported,Supported" if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)||((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x0014)))) group.long 0x0014++0x03 line.long 0x00 "GICR_WAKER,Power Management Control Register" bitfld.long 0x00 31. " QUIESCENT ,This bit shows that the GIC-500 is idle and can be powered down if required" "Not quiescent,Quiescent" bitfld.long 0x00 2. " CHILDRENASLEEP ,Indicates the bus between the CPU interface and this Redistributor is quiescent" "Not quiescent,Quiescent" bitfld.long 0x00 1. " PROCESSORASLEEP ,Indicates if this Redistributor must assert a WakeRequest if there is a pending interrupt targeted at the connected core" "No,Yes" textline " " bitfld.long 0x00 0. " SLEEP ,Indicates if GIC-500 ensures that all the caches are consistent with external memory and that it is safe to power off" "No,Yes" textline " " else hgroup.long 0x0014++0x03 hide.long 0x00 "GICR_WAKER,Power Management Control Register" endif group.quad 0x070++0x07 line.quad 0x00 "GICR_PROPBASER,Common LPI configuration table base register" bitfld.quad 0x00 56.--58. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the LPI Configuration table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" hexmask.quad 0x00 12.--51. 0x10 " PHYSICAL_ADDRESS ,Bits [51:12] of the physical address containing the LPI Configuration table" textline " " bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the LPI Configuration table" "Non-shareable,Inner Shareable,Outer Shareable,?..." bitfld.quad 0x00 7.--9. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the LPI Configuration table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" textline " " bitfld.quad 0x00 0.--4. " IDBITS ,The number of bits of LPI INTID supported minus one by the LPI Configuration table starting at Physical_Address" group.quad 0x78++0x07 line.quad 0x00 "GICR_PENDBASER,LPI pending table base register" bitfld.quad 0x00 62. " PTZ ,Pending Table Zero" "Not zero,Zero" bitfld.quad 0x00 56.--58. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the LPI Pending table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" textline " " hexmask.quad 0x00 16.--51. 0x10 " PHYSICAL_ADDRESS ,Bits [51:16] of the physical address containing the LPI Pending table" bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the LPI Pending table" "Non-shareable,Inner Shareable,Outer Shareable,?..." textline " " bitfld.quad 0x00 7.--9. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the LPI Pending table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" textline " " tree.end tree "SGI and PPI Registers" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10080)) group.long 0x10080++0x03 line.long 0x0 "GICR_IGROUPR0,Interrupt Group Register 0" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Secure,Non-secure Group 1" elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x000) group.long 0x10080++0x03 line.long 0x0 "GICR_IGROUPR0,Interrupt Group Register 0" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0,Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0,Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0,Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0,Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0,Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0,Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0,Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0,Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0,Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0,Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0,Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0,Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0,Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0,Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0,Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0,Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0,Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0,Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0,Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0,Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0,Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0,Group 1" else hgroup.long 0x10080++0x03 hide.long 0x00 "GICR_IGROUPR0,Interrupt Group Register 0" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif textline " " width 24. group.long 0x10100++0x03 line.long 0x0 "GICR_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31 ,Set/Clear Enable Bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB30 ,Set/Clear Enable Bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB29 ,Set/Clear Enable Bit 29" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28 ,Set/Clear Enable Bit 28" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB27 ,Set/Clear Enable Bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB26 ,Set/Clear Enable Bit 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25 ,Set/Clear Enable Bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB24 ,Set/Clear Enable Bit 24" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB23 ,Set/Clear Enable Bit 23" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22 ,Set/Clear Enable Bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB21 ,Set/Clear Enable Bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB20 ,Set/Clear Enable Bit 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19 ,Set/Clear Enable Bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB18 ,Set/Clear Enable Bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB17 ,Set/Clear Enable Bit 17" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16 ,Set/Clear Enable Bit 16" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB15 ,Set/Clear Enable Bit 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB14 ,Set/Clear Enable Bit 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB13 ,Set/Clear Enable Bit 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB12 ,Set/Clear Enable Bit 12" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB11 ,Set/Clear Enable Bit 11" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB10 ,Set/Clear Enable Bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB9 ,Set/Clear Enable Bit 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB8 ,Set/Clear Enable Bit 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB7 ,Set/Clear Enable Bit 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB6 ,Set/Clear Enable Bit 6" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB5 ,Set/Clear Enable Bit 5" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB4 ,Set/Clear Enable Bit 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB3 ,Set/Clear Enable Bit 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB2 ,Set/Clear Enable Bit 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB1 ,Set/Clear Enable Bit 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB0 ,Set/Clear Enable Bit 0" "Disabled,Enabled" group.long 0x10200++0x03 line.long 0x0 "GICR_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31 ,Set/Clear Pending Bit 31" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND30 ,Set/Clear Pending Bit 30" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND29 ,Set/Clear Pending Bit 29" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28 ,Set/Clear Pending Bit 28" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND27 ,Set/Clear Pending Bit 27" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND26 ,Set/Clear Pending Bit 26" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25 ,Set/Clear Pending Bit 25" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND24 ,Set/Clear Pending Bit 24" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND23 ,Set/Clear Pending Bit 23" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22 ,Set/Clear Pending Bit 22" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND21 ,Set/Clear Pending Bit 21" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND20 ,Set/Clear Pending Bit 20" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19 ,Set/Clear Pending Bit 19" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND18 ,Set/Clear Pending Bit 18" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND17 ,Set/Clear Pending Bit 17" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16 ,Set/Clear Pending Bit 16" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND15 ,Set/Clear Pending Bit 15" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND14 ,Set/Clear Pending Bit 14" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13 ,Set/Clear Pending Bit 13" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND12 ,Set/Clear Pending Bit 12" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND11 ,Set/Clear Pending Bit 11" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10 ,Set/Clear Pending Bit 10" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND9 ,Set/Clear Pending Bit 9" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND8 ,Set/Clear Pending Bit 8" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7 ,Set/Clear Pending Bit 7" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND6 ,Set/Clear Pending Bit 6" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND5 ,Set/Clear Pending Bit 5" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4 ,Set/Clear Pending Bit 4" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND3 ,Set/Clear Pending Bit 3" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND2 ,Set/Clear Pending Bit 2" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1 ,Set/Clear Pending Bit 1" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND0 ,Set/Clear Pending Bit 0" "Not pending,Pending" group.long 0x10300++0x03 line.long 0x0 "GICR_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE31 ,Set/Clear Active Bit 31" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE30 ,Set/Clear Active Bit 30" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE29 ,Set/Clear Active Bit 29" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE28 ,Set/Clear Active Bit 28" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE27 ,Set/Clear Active Bit 27" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE26 ,Set/Clear Active Bit 26" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE25 ,Set/Clear Active Bit 25" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE24 ,Set/Clear Active Bit 24" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE23 ,Set/Clear Active Bit 23" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE22 ,Set/Clear Active Bit 22" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE21 ,Set/Clear Active Bit 21" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE20 ,Set/Clear Active Bit 20" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE19 ,Set/Clear Active Bit 19" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE18 ,Set/Clear Active Bit 18" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE17 ,Set/Clear Active Bit 17" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE16 ,Set/Clear Active Bit 16" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE15 ,Set/Clear Active Bit 15" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE14 ,Set/Clear Active Bit 14" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE13 ,Set/Clear Active Bit 13" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE12 ,Set/Clear Active Bit 12" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE11 ,Set/Clear Active Bit 11" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE10 ,Set/Clear Active Bit 10" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE9 ,Set/Clear Active Bit 9" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE8 ,Set/Clear Active Bit 8" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE7 ,Set/Clear Active Bit 7" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE6 ,Set/Clear Active Bit 6" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE5 ,Set/Clear Active Bit 5" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE4 ,Set/Clear Active Bit 4" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE3 ,Set/Clear Active Bit 3" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE2 ,Set/Clear Active Bit 2" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE1 ,Set/Clear Active Bit 1" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE0 ,Set/Clear Active Bit 0" "Not active,Active" textline " " width 18. group.long 0x10400++0x03 line.long 0x00 "GICR_IPRIORITYR0,Interrupt Priority Register 0" hexmask.long.byte 0x00 24.--31. 1. " INTID3 ,Interrupt ID3 Priority/Priority Byte Offset 3 " hexmask.long.byte 0x00 16.--23. 1. " INTID2 ,Interrupt ID2 Priority/Priority Byte Offset 2 " hexmask.long.byte 0x00 8.--15. 1. " INTID1 ,Interrupt ID1 Priority/Priority Byte Offset 1 " hexmask.long.byte 0x00 0.--7. 1. " INTID0 ,Interrupt ID0 Priority/Priority Byte Offset 0 " group.long 0x10404++0x03 line.long 0x00 "GICR_IPRIORITYR1,Interrupt Priority Register 1" hexmask.long.byte 0x00 24.--31. 1. " INTID7 ,Interrupt ID7 Priority/Priority Byte Offset 7 " hexmask.long.byte 0x00 16.--23. 1. " INTID6 ,Interrupt ID6 Priority/Priority Byte Offset 6 " hexmask.long.byte 0x00 8.--15. 1. " INTID5 ,Interrupt ID5 Priority/Priority Byte Offset 5 " hexmask.long.byte 0x00 0.--7. 1. " INTID4 ,Interrupt ID4 Priority/Priority Byte Offset 4 " group.long 0x10408++0x03 line.long 0x00 "GICR_IPRIORITYR2,Interrupt Priority Register 2" hexmask.long.byte 0x00 24.--31. 1. " INTID11 ,Interrupt ID11 Priority/Priority Byte Offset 11 " hexmask.long.byte 0x00 16.--23. 1. " INTID10 ,Interrupt ID10 Priority/Priority Byte Offset 10 " hexmask.long.byte 0x00 8.--15. 1. " INTID9 ,Interrupt ID9 Priority/Priority Byte Offset 9 " hexmask.long.byte 0x00 0.--7. 1. " INTID8 ,Interrupt ID8 Priority/Priority Byte Offset 8 " group.long 0x1040C++0x03 line.long 0x00 "GICR_IPRIORITYR3,Interrupt Priority Register 3" hexmask.long.byte 0x00 24.--31. 1. " INTID15 ,Interrupt ID15 Priority/Priority Byte Offset 15 " hexmask.long.byte 0x00 16.--23. 1. " INTID14 ,Interrupt ID14 Priority/Priority Byte Offset 14 " hexmask.long.byte 0x00 8.--15. 1. " INTID13 ,Interrupt ID13 Priority/Priority Byte Offset 13 " hexmask.long.byte 0x00 0.--7. 1. " INTID12 ,Interrupt ID12 Priority/Priority Byte Offset 12 " group.long 0x10410++0x03 line.long 0x00 "GICR_IPRIORITYR4,Interrupt Priority Register 4" hexmask.long.byte 0x00 24.--31. 1. " INTID19 ,Interrupt ID19 Priority/Priority Byte Offset 19 " hexmask.long.byte 0x00 16.--23. 1. " INTID18 ,Interrupt ID18 Priority/Priority Byte Offset 18 " hexmask.long.byte 0x00 8.--15. 1. " INTID17 ,Interrupt ID17 Priority/Priority Byte Offset 17 " hexmask.long.byte 0x00 0.--7. 1. " INTID16 ,Interrupt ID16 Priority/Priority Byte Offset 16 " group.long 0x10414++0x03 line.long 0x00 "GICR_IPRIORITYR5,Interrupt Priority Register 5" hexmask.long.byte 0x00 24.--31. 1. " INTID23 ,Interrupt ID23 Priority/Priority Byte Offset 23 " hexmask.long.byte 0x00 16.--23. 1. " INTID22 ,Interrupt ID22 Priority/Priority Byte Offset 22 " hexmask.long.byte 0x00 8.--15. 1. " INTID21 ,Interrupt ID21 Priority/Priority Byte Offset 21 " hexmask.long.byte 0x00 0.--7. 1. " INTID20 ,Interrupt ID20 Priority/Priority Byte Offset 20 " group.long 0x10418++0x03 line.long 0x00 "GICR_IPRIORITYR6,Interrupt Priority Register 6" hexmask.long.byte 0x00 24.--31. 1. " INTID27 ,Interrupt ID27 Priority/Priority Byte Offset 27 " hexmask.long.byte 0x00 16.--23. 1. " INTID26 ,Interrupt ID26 Priority/Priority Byte Offset 26 " hexmask.long.byte 0x00 8.--15. 1. " INTID25 ,Interrupt ID25 Priority/Priority Byte Offset 25 " hexmask.long.byte 0x00 0.--7. 1. " INTID24 ,Interrupt ID24 Priority/Priority Byte Offset 24 " group.long 0x1041C++0x03 line.long 0x00 "GICR_IPRIORITYR7,Interrupt Priority Register 7" hexmask.long.byte 0x00 24.--31. 1. " INTID31 ,Interrupt ID31 Priority/Priority Byte Offset 31 " hexmask.long.byte 0x00 16.--23. 1. " INTID30 ,Interrupt ID30 Priority/Priority Byte Offset 30 " hexmask.long.byte 0x00 8.--15. 1. " INTID29 ,Interrupt ID29 Priority/Priority Byte Offset 29 " hexmask.long.byte 0x00 0.--7. 1. " INTID28 ,Interrupt ID28 Priority/Priority Byte Offset 28 " textline " " rgroup.long 0x10C00++0x03 line.long 0x00 "GICR_ICFGR0,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SGI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SGI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SGI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SGI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SGI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SGI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SGI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SGI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SGI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SGI)" "Level,Edge" group.long 0x10C04++0x03 line.long 0x00 "GICR_ICFGR1,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (PPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (PPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (PPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (PPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (PPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (PPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (PPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (PPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (PPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (PPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (PPI)" "Level,Edge" textline " " width 18. if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10D00)) group.long 0x10D00++0x03 line.long 0x0 "GICR_IGRPMODR0,Interrupt Group Modifier Register 0" bitfld.long 0x00 31. " GMB31 ,Group Modifier Bit 31" "0,1" bitfld.long 0x00 30. " GMB30 ,Group Modifier Bit 30" "0,1" bitfld.long 0x00 29. " GMB29 ,Group Modifier Bit 29" "0,1" textline " " bitfld.long 0x00 28. " GMB28 ,Group Modifier Bit 28" "0,1" bitfld.long 0x00 27. " GMB27 ,Group Modifier Bit 27" "0,1" bitfld.long 0x00 26. " GMB26 ,Group Modifier Bit 26" "0,1" textline " " bitfld.long 0x00 25. " GMB25 ,Group Modifier Bit 25" "0,1" bitfld.long 0x00 24. " GMB24 ,Group Modifier Bit 24" "0,1" bitfld.long 0x00 23. " GMB23 ,Group Modifier Bit 23" "0,1" textline " " bitfld.long 0x00 22. " GMB22 ,Group Modifier Bit 22" "0,1" bitfld.long 0x00 21. " GMB21 ,Group Modifier Bit 21" "0,1" bitfld.long 0x00 20. " GMB20 ,Group Modifier Bit 20" "0,1" textline " " bitfld.long 0x00 19. " GMB19 ,Group Modifier Bit 19" "0,1" bitfld.long 0x00 18. " GMB18 ,Group Modifier Bit 18" "0,1" bitfld.long 0x00 17. " GMB17 ,Group Modifier Bit 17" "0,1" textline " " bitfld.long 0x00 16. " GMB16 ,Group Modifier Bit 16" "0,1" bitfld.long 0x00 15. " GMB15 ,Group Modifier Bit 15" "0,1" bitfld.long 0x00 14. " GMB14 ,Group Modifier Bit 14" "0,1" textline " " bitfld.long 0x00 13. " GMB13 ,Group Modifier Bit 13" "0,1" bitfld.long 0x00 12. " GMB12 ,Group Modifier Bit 12" "0,1" bitfld.long 0x00 11. " GMB11 ,Group Modifier Bit 11" "0,1" textline " " bitfld.long 0x00 10. " GMB10 ,Group Modifier Bit 10" "0,1" bitfld.long 0x00 9. " GMB9 ,Group Modifier Bit 9" "0,1" bitfld.long 0x00 8. " GMB8 ,Group Modifier Bit 8" "0,1" textline " " bitfld.long 0x00 7. " GMB7 ,Group Modifier Bit 7" "0,1" bitfld.long 0x00 6. " GMB6 ,Group Modifier Bit 6" "0,1" bitfld.long 0x00 5. " GMB5 ,Group Modifier Bit 5" "0,1" textline " " bitfld.long 0x00 4. " GMB4 ,Group Modifier Bit 4" "0,1" bitfld.long 0x00 3. " GMB3 ,Group Modifier Bit 3" "0,1" bitfld.long 0x00 2. " GMB2 ,Group Modifier Bit 2" "0,1" textline " " bitfld.long 0x00 1. " GMB1 ,Group Modifier Bit 1" "0,1" bitfld.long 0x00 0. " GMB0 ,Group Modifier Bit 0" "0,1" textline " " else hgroup.long 0x10D00++0x03 hide.long 0x0 "GICR_IGRPMODR0,Interrupt Group Modifier Register 0" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10E00)) group.long 0x10E00++0x03 line.long 0x00 "GICR_NSACR,Non-secure Access Control Register" bitfld.long 0x00 30.--31. " NS_ACCESS15 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID15" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 28.--29. " NS_ACCESS14 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID14" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 26.--27. " NS_ACCESS13 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID13" "No access,G0S,G0S/G1S,?..." textline " " bitfld.long 0x00 24.--25. " NS_ACCESS12 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID12" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 22.--23. " NS_ACCESS11 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID11" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 20.--21. " NS_ACCESS10 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID10" "No access,G0S,G0S/G1S,?..." textline " " bitfld.long 0x00 18.--19. " NS_ACCESS9 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID9" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 16.--17. " NS_ACCESS8 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID8" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 14.--15. " NS_ACCESS7 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID7" "No access,G0S,G0S/G1S,?..." textline " " bitfld.long 0x00 12.--13. " NS_ACCESS6 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID6" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 10.--11. " NS_ACCESS5 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID5" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 8.--9. " NS_ACCESS4 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID4" "No access,G0S,G0S/G1S,?..." textline " " bitfld.long 0x00 6.--7. " NS_ACCESS3 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID3" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 4.--5. " NS_ACCESS2 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID2" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 2.--3. " NS_ACCESS1 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID1" "No access,G0S,G0S/G1S,?..." textline " " bitfld.long 0x00 0.--1. " NS_ACCESS0 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID0" "No access,G0S,G0S/G1S,?..." textline " " else hgroup.long 0x10E00++0x03 hide.long 0x00 "GICR_NSACR,Non-secure Access Control Register" textline " " textline " " textline " " textline " " textline " " endif rgroup.long 0x1C000++0x03 line.long 0x00 "GICR_MISCSTATUSR,Miscellaneous Status Register" bitfld.long 0x00 31. " CPU_AS ,CPU active state. This bit returns the actual status of the cpu_active signal for the core corresponding to the Redistributor whose register is being read" "Low,High" bitfld.long 0x00 2. " ENABLEGRP1_S ,EnableGrp1 Secure" "0,1" bitfld.long 0x00 1. " ENABLEGRP1_NS ,EnableGrp1 Non-secure" "0,1" textline " " bitfld.long 0x00 0. " ENABLEGRP0 ,EnableGrp0" "0,1" rgroup.long 0x1C080++0x03 line.long 0x00 "GICR_PPISR,Private Peripheral Interrupt Status Register" bitfld.long 0x00 31. " PPI31S ,Actual status of the PPI31 input signal" "Low,High" bitfld.long 0x00 30. " PPI30S ,Actual status of the PPI30 input signal" "Low,High" bitfld.long 0x00 29. " PPI29S ,Actual status of the PPI29 input signal" "Low,High" textline " " bitfld.long 0x00 28. " PPI28S ,Actual status of the PPI28 input signal" "Low,High" bitfld.long 0x00 27. " PPI27S ,Actual status of the PPI27 input signal" "Low,High" bitfld.long 0x00 26. " PPI26S ,Actual status of the PPI26 input signal" "Low,High" textline " " bitfld.long 0x00 25. " PPI25S ,Actual status of the PPI25 input signal" "Low,High" bitfld.long 0x00 24. " PPI24S ,Actual status of the PPI24 input signal" "Low,High" bitfld.long 0x00 23. " PPI23S ,Actual status of the PPI23 input signal" "Low,High" textline " " bitfld.long 0x00 22. " PPI22S ,Actual status of the PPI22 input signal" "Low,High" bitfld.long 0x00 21. " PPI21S ,Actual status of the PPI21 input signal" "Low,High" bitfld.long 0x00 20. " PPI20S ,Actual status of the PPI20 input signal" "Low,High" textline " " bitfld.long 0x00 19. " PPI19S ,Actual status of the PPI19 input signal" "Low,High" bitfld.long 0x00 18. " PPI18S ,Actual status of the PPI18 input signal" "Low,High" bitfld.long 0x00 17. " PPI17S ,Actual status of the PPI17 input signal" "Low,High" textline " " bitfld.long 0x00 16. " PPI16S ,Actual status of the PPI16 input signal" "Low,High" tree.end width 12. tree "Peripheral/Component ID Registers" rgroup.long 0xFFE0++0x03 line.long 0x00 "GICR_PIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_0 ,Part number[7:0]" rgroup.long 0xFFE4++0x03 line.long 0x00 "GICR_PIDR1,Peripheral ID1 Register" bitfld.long 0x00 4.--7. " DES_1 ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PART_1 , Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFE8++0x03 line.long 0x00 "GICR_PIDR2,Peripheral ID2 Register" bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..." bitfld.long 0x00 3. " JEDEC ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Low,High" bitfld.long 0x00 0.--2. " DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7" rgroup.long 0xFFEC++0x03 line.long 0x00 "GICR_PIDR3,Peripheral ID3 Register" bitfld.long 0x00 4.--7. " REVAND ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CMOD ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFD0++0x03 line.long 0x00 "GICR_PIDR4,Peripheral ID4 Register" bitfld.long 0x00 4.--7. " SIZE ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DES_2 ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0xFFD4++0x03 hide.long 0x00 "GICR_PIDR5,Peripheral ID5 Register" hgroup.long 0xFFD8++0x03 hide.long 0x00 "GICR_PIDR6,Peripheral ID6 Register" hgroup.long 0xFFDC++0x03 hide.long 0x00 "GICR_PIDR7,Peripheral ID7 Register" rgroup.long 0xFFF0++0x03 line.long 0x00 "GICR_CIDR0,Component ID0 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF4++0x03 line.long 0x00 "GICR_CIDR1,Component ID1 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF8++0x03 line.long 0x00 "GICR_CIDR2,Component ID2 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFFC++0x03 line.long 0x00 "GICR_CIDR3,Component ID3 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" tree.end tree.end width 0x0B sif COMP.AVAILABLE("GICC") base COMP.BASE("GICC",-1.) width 14. tree "CPU Interface" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICC",-1.))) group.long 0x00++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register" bitfld.long 0x00 10. " EOIMODENS ,Controls the behavior of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 9. " EOIMODES ,Controls the behavior of Secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 8. " IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" textline " " bitfld.long 0x00 7. " FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" bitfld.long 0x00 6. " IRQBYPDISGRP0 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 0" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP0 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 0" "Signaled,Not signaled" textline " " bitfld.long 0x00 4. " CBPR ,Controls whether GICC_BPR provides common control of preemption to Group 0 and Group 1 interrupts" "Group 0,Both" bitfld.long 0x00 3. " FIQEN ,Controls whether the CPU interface signals Group 0 interrupts to a target PE using the FIQ or IRQ signal" "IRQ,FIQ" bitfld.long 0x00 1. " ENABLEGRP1 ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " ENABLEGRP0 ,Enables the signaling of Group 0 interrupts by the CPU interface to a target PE" "Disabled,Enabled" elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400) group.long 0x00++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register" bitfld.long 0x00 9. " EOIMODENS ,Controls the behavior of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 6. " IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" textline " " bitfld.long 0x00 0. " ENABLEGRP1 ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register" bitfld.long 0x00 9. " EOIMODE ,Controls the behavior of accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 8. " IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" bitfld.long 0x00 7. " FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" textline " " bitfld.long 0x00 6. " IRQBYPDISGRP0 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 0" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP0 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 0" "Signaled,Not signaled" bitfld.long 0x00 4. " CBPR ,Controls whether GICC_BPR provides common control of preemption to Group 0 and Group 1 interrupts" "Group 0,Both" textline " " bitfld.long 0x00 3. " FIQEN ,Controls whether the CPU interface signals Group 0 interrupts to a target PE using the FIQ or IRQ signal" "IRQ,FIQ" bitfld.long 0x00 1. " ENABLEGRP1 ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enables the signaling of Group 0 interrupts by the CPU interface to a target PE" "Disabled,Enabled" endif textline " " group.long 0x04++0x03 line.long 0x00 "GICC_PMR,Interrupt Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for CPU interface" group.long 0x08++0x03 line.long 0x00 "GICC_BPR,Binary Point Register" bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7" hgroup.long 0x0C++0x03 hide.long 0x00 "GICC_IAR,Interrupt Acknowledge Register" in wgroup.long 0x10++0x03 line.long 0x00 "GICC_EOIR,End Of Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" rgroup.long 0x14++0x03 line.long 0x00 "GICC_RPR,Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority value of highest priority interrupt" rgroup.long 0x18++0x03 line.long 0x00 "GICC_HPPIR,Highest Priority Pending Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" group.long 0x1C++0x03 line.long 0x00 "GICC_ABPR,Aliased Binary Point Register" bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7" hgroup.long 0x20++0x03 hide.long 0x00 "GICC_AIAR,Aliased Interrupt Acknowledge Register" in wgroup.long 0x24++0x03 line.long 0x00 "GICC_AEOIR,Aliased End of Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" rgroup.long 0x28++0x03 line.long 0x00 "GICC_AHPPIR,Aliased Highest Priority Pending Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" rgroup.long 0x2C++0x03 line.long 0x00 "GICC_STATUSR,CPU Interface Status Register" bitfld.long 0x00 4. " ASV ,Attempted security violation" "Not detected,Detected" bitfld.long 0x00 3. " WROD ,Write to an RO location" "Not detected,Detected" bitfld.long 0x00 2. " RWOD ,Read of a WO location" "Not detected,Detected" textline " " bitfld.long 0x00 1. " WRD ,Write to a reserved location" "Not detected,Detected" bitfld.long 0x00 0. " RRD ,Read of a reserved location" "Not detected,Detected" group.long 0xD0++0x03 line.long 0x00 "GICC_APR0,Active Priorities Register 0" group.long 0xD4++0x03 line.long 0x00 "GICC_APR1,Active Priorities Register 1" group.long 0xD8++0x03 line.long 0x00 "GICC_APR2,Active Priorities Register 2" group.long 0xDC++0x03 line.long 0x00 "GICC_APR3,Active Priorities Register 3" group.long 0xE0++0x03 line.long 0x00 "GICC_NSAPR0,Non-Secure Active Priorities Register 0" group.long 0xE4++0x03 line.long 0x00 "GICC_NSAPR1,Non-Secure Active Priorities Register 1" group.long 0xE8++0x03 line.long 0x00 "GICC_NSAPR2,Non-Secure Active Priorities Register 2" group.long 0xEC++0x03 line.long 0x00 "GICC_NSAPR3,Non-Secure Active Priorities Register 3" rgroup.long 0xFC++0x03 line.long 0x00 "GICC_IIDR,CPU Interface Identification Register" hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 16.--19. " ARCHVER ,The version of the GIC architecture that is implemented" ",,,GICv3,?..." bitfld.long 0x00 12.--15. " REV ,Revision number for the CPU interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" wgroup.long 0x1000++0x03 line.long 0x00 "GICC_DIR,Deactivate Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" tree.end width 0x0b endif sif COMP.AVAILABLE("GICH") base COMP.BASE("GICH",-1.) width 13. tree "Virtual CPU Control Interface" group.long 0x00++0x03 line.long 0x00 "GICH_HCR,Hypervisor Control Register" bitfld.long 0x00 27.--31. " EOICOUNT ,Counts the number of EOIs received that do not have a corresponding entry in the List registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " VGRP1DIE ,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " VGRP1EIE ,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " VGRP0DIE ,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " VGRP0EIE ,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " NPIE ,No Pending Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " LRENPIE ,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " UIE ,Underflow Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " EN ,Virtual CPU interface Enable" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "GICH_VTR,Virtual Type Register" bitfld.long 0x00 29.--31. " PRIBITS ,Number of priority bits" "1,2,3,4,5,6,7,8" bitfld.long 0x00 26.--28. " PREBITS ,Number of pre-emption bits" "1,2,3,4,5,6,7,8" bitfld.long 0x00 23.--25. " IDBITS ,The number of virtual interrupt identifier bits supported" "16 bits,24 bits,?..." textline " " bitfld.long 0x00 22. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not supported,Supported" bitfld.long 0x00 21. " A3V ,Affinity 3 valid" "Invalid,Valid" bitfld.long 0x00 0.--4. " LISTREGS ,List regs number" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" group.long 0x08++0x03 line.long 0x00 "GICH_VMCR,Virtual Machine Control Register" hexmask.long.byte 0x00 24.--31. 1. " VPMR ,Virtual priority mask" bitfld.long 0x00 21.--23. " VBPR0 ,Defines the point at which the priority value fields split into two parts the group priority field and the subpriority field (group 0)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " VBPR1 ,Defines the point at which the priority value fields split into two parts the group priority field and the subpriority field (group 1)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9. " VEOIM ,Virtual EOImode. DP - Drop the priority / ID - interrupt deactivate" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" textline " " bitfld.long 0x00 4. " VCBPR ,Virtual Common Binary Point Register" "ABPR,BPR" bitfld.long 0x00 3. " VFIQEN ,Virtual FIQ enable" "Disabled,Enabled" bitfld.long 0x00 2. " VACKCTL ,Virtual AckCtl" "INTID=1022,INTID=corresponding" bitfld.long 0x00 1. " VENG1 ,Virtual interrupt enable for group 1" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " VENG0 ,Virtual interrupt enable for group 0" "Disabled,Enabled" rgroup.long 0x10++0x03 line.long 0x00 "GICH_MISR,Maintenance Interrupt Status Register" bitfld.long 0x00 7. " VGRP1D ,vPE Group 1 Disabled maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 6. " VGRP1E ,vPE Group 1 Enabled maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 5. " VGRP0D ,vPE Group 0 Disabled maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 4. " VGRP0E ,vPE Group 0 Enabled maintenance interrupt assertion" "Not asserted,Asserted" textline " " bitfld.long 0x00 3. " NP ,No Pending maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 2. " LRENP ,List Register Entry Not Present maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 1. " U ,Underflow maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 0. " EOI ,End Of Interrupt maintenance interrupt assertion" "Not asserted,Asserted" rgroup.long 0x20++0x03 line.long 0x00 "GICH_EISR0,End of Interrupt Status Register" bitfld.long 0x00 15. " STATUS15 ,EOI maintenance interrupt status for List register 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " STATUS14 ,EOI maintenance interrupt status for List register 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " STATUS13 ,EOI maintenance interrupt status for List register 13" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " STATUS12 ,EOI maintenance interrupt status for List register 12" "No interrupt,Interrupt" bitfld.long 0x00 11. " STATUS11 ,EOI maintenance interrupt status for List register 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " STATUS10 ,EOI maintenance interrupt status for List register 10" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " STATUS9 ,EOI maintenance interrupt status for List register 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " STATUS8 ,EOI maintenance interrupt status for List register 8" "No interrupt,Interrupt" bitfld.long 0x00 7. " STATUS7 ,EOI maintenance interrupt status for List register 7" "No interrupt,Interrupt" textline " " bitfld.long 0x00 6. " STATUS6 ,EOI maintenance interrupt status for List register 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " STATUS5 ,EOI maintenance interrupt status for List register 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " STATUS4 ,EOI maintenance interrupt status for List register 4" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " STATUS3 ,EOI maintenance interrupt status for List register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " STATUS2 ,EOI maintenance interrupt status for List register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " STATUS1 ,EOI maintenance interrupt status for List register 1" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " STATUS0 ,EOI maintenance interrupt status for List register 0" "No interrupt,Interrupt" rgroup.long 0x30++0x03 line.long 0x00 "GICH_ELRSR0,Empty List register Status Register" bitfld.long 0x00 15. " STATUS15 ,Status bit for List register 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " STATUS14 ,Status bit for List register 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " STATUS13 ,Status bit for List register 13" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " STATUS12 ,Status bit for List register 12" "No interrupt,Interrupt" bitfld.long 0x00 11. " STATUS11 ,Status bit for List register 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " STATUS10 ,Status bit for List register 10" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " STATUS9 ,Status bit for List register 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " STATUS8 ,Status bit for List register 8" "No interrupt,Interrupt" bitfld.long 0x00 7. " STATUS7 ,Status bit for List register 7" "No interrupt,Interrupt" textline " " bitfld.long 0x00 6. " STATUS6 ,Status bit for List register 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " STATUS5 ,Status bit for List register 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " STATUS4 ,Status bit for List register 4" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " STATUS3 ,Status bit for List register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " STATUS2 ,Status bit for List register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " STATUS1 ,Status bit for List register 1" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " STATUS0 ,Status bit for List register 0" "No interrupt,Interrupt" textline " " group.long 0xF0++0x03 line.long 0x00 "GICH_APR0,Active Priorities Register 0" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xF4++0x03 line.long 0x00 "GICH_APR1,Active Priorities Register 1" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xF8++0x03 line.long 0x00 "GICH_APR2,Active Priorities Register 2" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xFC++0x03 line.long 0x00 "GICH_APR3,Active Priorities Register 3" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" textline " " group.long 0x100++0x03 line.long 0x00 "GICH_LR0,List Register 0" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x104++0x03 line.long 0x00 "GICH_LR1,List Register 1" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x108++0x03 line.long 0x00 "GICH_LR2,List Register 2" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x10C++0x03 line.long 0x00 "GICH_LR3,List Register 3" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x110++0x03 line.long 0x00 "GICH_LR4,List Register 4" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x114++0x03 line.long 0x00 "GICH_LR5,List Register 5" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x118++0x03 line.long 0x00 "GICH_LR6,List Register 6" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x11C++0x03 line.long 0x00 "GICH_LR7,List Register 7" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x120++0x03 line.long 0x00 "GICH_LR8,List Register 8" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x124++0x03 line.long 0x00 "GICH_LR9,List Register 9" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x128++0x03 line.long 0x00 "GICH_LR10,List Register 10" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x12C++0x03 line.long 0x00 "GICH_LR11,List Register 11" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x130++0x03 line.long 0x00 "GICH_LR12,List Register 12" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x134++0x03 line.long 0x00 "GICH_LR13,List Register 13" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x138++0x03 line.long 0x00 "GICH_LR14,List Register 14" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" tree.end width 0x0b endif sif COMP.AVAILABLE("GICV") base COMP.BASE("GICV",-1.) width 14. tree "Virtual CPU Interface" group.long 0x00++0x03 line.long 0x00 "GICV_CTLR,VM Control Register" bitfld.long 0x00 9. " EOIMODE ,Controls the behaviour of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 4. " CBPR ,Controls whether GICV_BPR affects both Group 0 and Group 1 interrupts" "Group 0,Both" bitfld.long 0x00 3. " FIQEN ,FIQ Enable" "Disabled,Enabled" bitfld.long 0x00 2. " ACKCTL ,Acknowledge control. Return ID of the corresponding interrupt" "1022,Corresponding" textline " " bitfld.long 0x00 1. " ENABLEGRP1 ,Enables the signalling of Group 1 interrupts by the CPU interface to the virtual machine" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enables the signalling of Group 0 interrupts by the CPU interface to the virtual machine" "Disabled,Enabled" group.long 0x04++0x03 line.long 0x00 "GICV_PMR,VM Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for the virtual CPU interface" group.long 0x08++0x03 line.long 0x00 "GICV_BPR,VM Binary Point Register" bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7" rgroup.long 0x0C++0x03 line.long 0x00 "GICV_IAR,VM Interrupt Acknowledge Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" wgroup.long 0x10++0x03 line.long 0x00 "GICV_EOIR,VM End Of Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" rgroup.long 0x14++0x03 line.long 0x00 "GICV_RPR,VM Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority value of highest priority interrupt" rgroup.long 0x18++0x03 line.long 0x00 "GICV_HPPIR,VM Highest Priority Pending Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" group.long 0x1C++0x03 line.long 0x00 "GICV_ABPR,VM Aliased Binary Point Register" bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7" rgroup.long 0x20++0x03 line.long 0x00 "GICV_AIAR,VM Aliased Interrupt Acknowledge Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" wgroup.long 0x24++0x03 line.long 0x00 "GICV_AEOIR,VM Aliased End of Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" rgroup.long 0x28++0x03 line.long 0x00 "GICV_AHPPIR,VM Aliased Highest Priority Pending Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" textline "" group.long 0xD0++0x03 line.long 0x00 "GICV_APR0,VM Active Priority Register 0" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xD4++0x03 line.long 0x00 "GICV_APR1,VM Active Priority Register 1" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xD8++0x03 line.long 0x00 "GICV_APR2,VM Active Priority Register 2" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xDC++0x03 line.long 0x00 "GICV_APR3,VM Active Priority Register 3" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" textline " " rgroup.long 0xFC++0x03 line.long 0x00 "GICV_IIDR,Virtual Machine CPU Interface Identification Register" hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 16.--19. " ARCHVER ,The version of the GIC architecture that is implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " REV ,Revision number for the CPU interface" ",,,GICv3,?..." hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" wgroup.long 0x1000++0x03 line.long 0x00 "GICV_DIR,VM Deactivate Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" tree.end width 0x0b endif width 0x0B tree.end tree.end elif (CORENAME()=="CORTEXM4F") tree.close "Core Registers (Cortex-M4F)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes" bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes" textline " " bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes" bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes" group.long 0x10++0x0B line.long 0x00 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled" line.long 0x04 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x08 "SYST_CVR,SysTick Current Value Register" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code" bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..." bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number" bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active" bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending" bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed" textline " " bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending" bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed" bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active" textline " " bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending" hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field" bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active" textline " " hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key" rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big" bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear" bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment" bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled" bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed" bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level" line.long 0x14 "SHPR1,SSystem Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)" hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10" hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9" textline " " hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)" hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13" textline " " hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "USAFAULT,Usage Fault Status Register" bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" textline " " bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error" bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x07 line.long 0x00 "HFSR,Hard Fault Status Register" bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred" bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" line.long 0x04 "DFSR,Debug Fault Status Register" bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted" bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred" bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred" textline " " bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed" bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested" group.long 0xD34++0x0B line.long 0x00 "MMFAR,MemManage Fault Address Register" line.long 0x04 "BFAR,BusFault Address Register" line.long 0x08 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access" wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Trigger Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered" width 10. tree "Feature Registers" rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..." hgroup.long 0xD4C++0x03 hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..." bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..." hgroup.long 0xD54++0x03 hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD60++0x13 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..." line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..." bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..." line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..." textline " " bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..." line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..." bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..." textline " " bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..." bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..." tree.end width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported" group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. rgroup.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..." tree "Interrupt Enable Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x100++0x7 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x100++0x0B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x100++0x0F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x100++0x13 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x100++0x17 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x100++0x1B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x100++0x1F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x100++0x1F hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" endif tree.end tree "Interrupt Pending Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x200++0x07 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x200++0x0B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x200++0x0F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x200++0x13 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x200++0x17 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x200++0x1B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x200++0x1F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x200++0x1F hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" endif tree.end tree "Interrupt Active Bit Registers" width 9. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) rgroup.long 0x300++0x07 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) rgroup.long 0x300++0x0B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) rgroup.long 0x300++0x0F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) rgroup.long 0x300++0x13 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) rgroup.long 0x300++0x17 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) rgroup.long 0x300++0x1B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) rgroup.long 0x300++0x1F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" line.long 0x1c "ACTIVE8,Active Bit Register 8" bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x300++0x1F hide.long 0x00 "ACTIVE1,Active Bit Register 1" hide.long 0x04 "ACTIVE2,Active Bit Register 2" hide.long 0x08 "ACTIVE3,Active Bit Register 3" hide.long 0x0c "ACTIVE4,Active Bit Register 4" hide.long 0x10 "ACTIVE5,Active Bit Register 5" hide.long 0x14 "ACTIVE6,Active Bit Register 6" hide.long 0x18 "ACTIVE7,Active Bit Register 7" hide.long 0x1c "ACTIVE8,Active Bit Register 8" endif tree.end tree "Interrupt Priority Registers" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x400++0x3F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x400++0x5F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x400++0x7F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x400++0x9F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x400++0xBF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x400++0xDF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x400++0xEF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" line.long 0xE0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0xE4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0xE8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xEC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" else hgroup.long 0x400++0xEF hide.long 0x0 "IPR0,Interrupt Priority Register" hide.long 0x4 "IPR1,Interrupt Priority Register" hide.long 0x8 "IPR2,Interrupt Priority Register" hide.long 0xC "IPR3,Interrupt Priority Register" hide.long 0x10 "IPR4,Interrupt Priority Register" hide.long 0x14 "IPR5,Interrupt Priority Register" hide.long 0x18 "IPR6,Interrupt Priority Register" hide.long 0x1C "IPR7,Interrupt Priority Register" hide.long 0x20 "IPR8,Interrupt Priority Register" hide.long 0x24 "IPR9,Interrupt Priority Register" hide.long 0x28 "IPR10,Interrupt Priority Register" hide.long 0x2C "IPR11,Interrupt Priority Register" hide.long 0x30 "IPR12,Interrupt Priority Register" hide.long 0x34 "IPR13,Interrupt Priority Register" hide.long 0x38 "IPR14,Interrupt Priority Register" hide.long 0x3C "IPR15,Interrupt Priority Register" hide.long 0x40 "IPR16,Interrupt Priority Register" hide.long 0x44 "IPR17,Interrupt Priority Register" hide.long 0x48 "IPR18,Interrupt Priority Register" hide.long 0x4C "IPR19,Interrupt Priority Register" hide.long 0x50 "IPR20,Interrupt Priority Register" hide.long 0x54 "IPR21,Interrupt Priority Register" hide.long 0x58 "IPR22,Interrupt Priority Register" hide.long 0x5C "IPR23,Interrupt Priority Register" hide.long 0x60 "IPR24,Interrupt Priority Register" hide.long 0x64 "IPR25,Interrupt Priority Register" hide.long 0x68 "IPR26,Interrupt Priority Register" hide.long 0x6C "IPR27,Interrupt Priority Register" hide.long 0x70 "IPR28,Interrupt Priority Register" hide.long 0x74 "IPR29,Interrupt Priority Register" hide.long 0x78 "IPR30,Interrupt Priority Register" hide.long 0x7C "IPR31,Interrupt Priority Register" hide.long 0x80 "IPR32,Interrupt Priority Register" hide.long 0x84 "IPR33,Interrupt Priority Register" hide.long 0x88 "IPR34,Interrupt Priority Register" hide.long 0x8C "IPR35,Interrupt Priority Register" hide.long 0x90 "IPR36,Interrupt Priority Register" hide.long 0x94 "IPR37,Interrupt Priority Register" hide.long 0x98 "IPR38,Interrupt Priority Register" hide.long 0x9C "IPR39,Interrupt Priority Register" hide.long 0xA0 "IPR40,Interrupt Priority Register" hide.long 0xA4 "IPR41,Interrupt Priority Register" hide.long 0xA8 "IPR42,Interrupt Priority Register" hide.long 0xAC "IPR43,Interrupt Priority Register" hide.long 0xB0 "IPR44,Interrupt Priority Register" hide.long 0xB4 "IPR45,Interrupt Priority Register" hide.long 0xB8 "IPR46,Interrupt Priority Register" hide.long 0xBC "IPR47,Interrupt Priority Register" hide.long 0xC0 "IPR48,Interrupt Priority Register" hide.long 0xC4 "IPR49,Interrupt Priority Register" hide.long 0xC8 "IPR50,Interrupt Priority Register" hide.long 0xCC "IPR51,Interrupt Priority Register" hide.long 0xD0 "IPR52,Interrupt Priority Register" hide.long 0xD4 "IPR53,Interrupt Priority Register" hide.long 0xD8 "IPR54,Interrupt Priority Register" hide.long 0xDC "IPR55,Interrupt Priority Register" hide.long 0xE0 "IPR56,Interrupt Priority Register" hide.long 0xE4 "IPR57,Interrupt Priority Register" hide.long 0xE8 "IPR58,Interrupt Priority Register" hide.long 0xEC "IPR59,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end sif CORENAME()=="CORTEXM4F" tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" textline " " bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" textline " " bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" textline " " bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0xF40++0x07 line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." textline " " bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..." bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." textline " " bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..." width 0xB else newline textline "COREDEBUG component base address not specified" newline endif tree.end endif tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 7. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" newline eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 10. group.long 0x00++0x07 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" textline "" line.long 0x04 "FP_REMAP,Flash Patch Remap Register" bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region" hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0xB else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 15. group.long 0x00++0x1B line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported" textline " " rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" textline " " bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" line.long 0x04 "DWT_CYCCNT,Cycle Count Register" line.long 0x08 "DWT_CPICNT,CPI Count Register" hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter" line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x14 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter" line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register" hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter" rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" textline " " group.long 0x20++0x07 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" line.long 0x04 "DWT_MASK0,DWT Mask Registers 0" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" else group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x30)++0x07 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" line.long 0x04 "DWT_MASK1,DWT Mask Registers 1" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x40)++0x07 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" line.long 0x04 "DWT_MASK2,DWT Mask Registers 2" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x50)++0x07 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" line.long 0x04 "DWT_MASK3,DWT Mask Registers 3" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0x0B else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end endif config 16. 8. tree.open "Clocking" sif (!cpuis("IMX8*-CM4")&&!cpuis("IMX8*-SCU")) tree "ADMA (Audio DMA)" base ad:0x59000000 width 18. tree "SSI Registers" group.long 0x400000++0x03 line.long 0x00 "ASRC0,ASRC0 CLocks Register" rbitfld.long 0x00 19. " ASRC0_IPG_CLK_STOP ,ASRC0_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " ASRC0_IPG_CLK_SWEN ,ASRC0_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " ASRC0_IPG_CLK_HWEN ,ASRC0_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x410000++0x03 line.long 0x00 "ESAI0,ESAI0 Clocks Register" rbitfld.long 0x00 19. " ESAI0_IPG_CLK_S_STOP ,ESAI0_IPG_CLK_S clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " ESAI0_IPG_CLK_S_SWEN ,ESAI0_IPG_CLK_S clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " ESAI0_IPG_CLK_S_HWEN ,ESAI0_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " ESAI0_EXTAL_CLK_STOP ,ESAI0_EXTAL_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " ESAI0_EXTAL_CLK_SWEN ,ESAI0_EXTAL_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " ESAI0_EXTAL_CLK_HWEN ,ESAI0_EXTAL_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x420000++0x03 line.long 0x00 "SPDIF0,SPDIF Clocks Register" rbitfld.long 0x00 19. " SPDIF0_IPG_CLK_S_STOP ,SPDIF0_IPG_CLK_S clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " SPDIF0_IPG_CLK_S_SWEN ,SPDIF0_IPG_CLK_S clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " SPDIF0_IPG_CLK_S_HWEN ,SPDIF0_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " SPDIF0_TX_CLK_STOP ,SPDIF0_TX_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " SPDIF0_TX_CLK_SWEN ,SPDIF0_TX_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " SPDIF0_TX_CLK_HWEN ,SPDIF0_TX_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x440000++0x03 line.long 0x00 "SAI0,SAI0 Clocks Register" rbitfld.long 0x00 19. " SAI0_IPG_CLK_STOP ,SAI0_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " SAI0_IPG_CLK_SWEN ,SAI0_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " SAI0_IPG_CLK_HWEN ,SAI0_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " SAI0_IPG_CLK_SAI_MCLK_1_STOP ,SAI0_IPG_CLK_SAI_MCLK_1 clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " SAI0_IPG_CLK_SAI_MCLK_1_SWEN ,SAI0_IPG_CLK_SAI_MCLK_1 clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " SAI0_IPG_CLK_SAI_MCLK_1_HWEN ,SAI0_IPG_CLK_SAI_MCLK_1 clock HW signal treatment" "Ignored,Automatically gated" group.long 0x450000++0x03 line.long 0x00 "SAI1,SAI1 Clocks Register" rbitfld.long 0x00 19. " SAI1_IPG_CLK_STOP ,SAI1_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " SAI1_IPG_CLK_SWEN ,SAI1_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " SAI1_IPG_CLK_HWEN ,SAI1_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " SAI1_IPG_CLK_SAI_MCLK_1_STOP ,SAI1_IPG_CLK_SAI_MCLK_1 clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " SAI1_IPG_CLK_SAI_MCLK_1_SWEN ,SAI1_IPG_CLK_SAI_MCLK_1 clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " SAI1_IPG_CLK_SAI_MCLK_1_HWEN ,SAI1_IPG_CLK_SAI_MCLK_1 clock HW signal treatment" "Ignored,Automatically gated" group.long 0x460000++0x03 line.long 0x00 "SAI2,SAI2 Clocks Register" rbitfld.long 0x00 19. " SAI2_IPG_CLK_STOP ,SAI2_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " SAI2_IPG_CLK_SWEN ,SAI2_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " SAI2_IPG_CLK_HWEN ,SAI2_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " SAI2_IPG_CLK_SAI_MCLK_1_STOP ,SAI2_IPG_CLK_SAI_MCLK_1 clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " SAI2_IPG_CLK_SAI_MCLK_1_SWEN ,SAI2_IPG_CLK_SAI_MCLK_1 clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " SAI2_IPG_CLK_SAI_MCLK_1_HWEN ,SAI2_IPG_CLK_SAI_MCLK_1 clock HW signal treatment" "Ignored,Automatically gated" group.long 0x470000++0x03 line.long 0x00 "SAI3,SAI3 Clocks Register" rbitfld.long 0x00 19. " SAI3_IPG_CLK_STOP ,SAI3_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " SAI3_IPG_CLK_SWEN ,SAI3_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " SAI3_IPG_CLK_HWEN ,SAI3_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " SAI3_IPG_CLK_SAI_MCLK_1_STOP ,SAI3_IPG_CLK_SAI_MCLK_1 clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " SAI3_IPG_CLK_SAI_MCLK_1_SWEN ,SAI3_IPG_CLK_SAI_MCLK_1 clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " SAI3_IPG_CLK_SAI_MCLK_1_HWEN ,SAI3_IPG_CLK_SAI_MCLK_1 clock HW signal treatment" "Ignored,Automatically gated" group.long 0x4B0000++0x03 line.long 0x00 "GPT0,GPT0 Clocks Register" rbitfld.long 0x00 19. " GPT0_IPG_CLK_STOP ,GPT0_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " GPT0_IPG_CLK_SWEN ,GPT0_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " GPT0_IPG_CLK_HWEN ,GPT0_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " GPT0_IPP_IND_CLKIN_STOP ,GPT0_IPP_IND_CLKIN clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " GPT0_IPP_IND_CLKIN_SWEN ,GPT0_IPP_IND_CLKIN clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " GPT0_IPP_IND_CLKIN_HWEN ,GPT0_IPP_IND_CLKIN clock HW signal treatment" "Ignored,Automatically gated" group.long 0x4C0000++0x03 line.long 0x00 "GPT1,GPT1 Clocks Register" rbitfld.long 0x00 19. " GPT1_IPG_CLK_STOP ,GPT1_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " GPT1_IPG_CLK_SWEN ,GPT1_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " GPT1_IPG_CLK_HWEN ,GPT1_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " GPT1_IPP_IND_CLKIN_STOP ,GPT1_IPP_IND_CLKIN clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " GPT1_IPP_IND_CLKIN_SWEN ,GPT1_IPP_IND_CLKIN clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " GPT1_IPP_IND_CLKIN_HWEN ,GPT1_IPP_IND_CLKIN clock HW signal treatment" "Ignored,Automatically gated" group.long 0x4D0000++0x03 line.long 0x00 "GPT2,GPT2 Clocks Register" rbitfld.long 0x00 19. " GPT2_IPG_CLK_STOP ,GPT2_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " GPT2_IPG_CLK_SWEN ,GPT2_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " GPT2_IPG_CLK_HWEN ,GPT2_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " GPT2_IPP_IND_CLKIN_STOP ,GPT2_IPP_IND_CLKIN clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " GPT2_IPP_IND_CLKIN_SWEN ,GPT2_IPP_IND_CLKIN clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " GPT2_IPP_IND_CLKIN_HWEN ,GPT2_IPP_IND_CLKIN clock HW signal treatment" "Ignored,Automatically gated" group.long 0x4E0000++0x03 line.long 0x00 "GPT3,GPT3 Clocks Register" rbitfld.long 0x00 19. " GPT3_IPG_CLK_STOP ,GPT3_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " GPT3_IPG_CLK_SWEN ,GPT3_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " GPT3_IPG_CLK_HWEN ,GPT3_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " GPT3_IPP_IND_CLKIN_STOP ,GPT3_IPP_IND_CLKIN clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " GPT3_IPP_IND_CLKIN_SWEN ,GPT3_IPP_IND_CLKIN clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " GPT3_IPP_IND_CLKIN_HWEN ,GPT3_IPP_IND_CLKIN clock HW signal treatment" "Ignored,Automatically gated" group.long 0x4F0000++0x03 line.long 0x00 "GPT4,GPT4 Clocks Register" rbitfld.long 0x00 19. " GPT4_IPG_CLK_STOP ,GPT4_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " GPT4_IPG_CLK_SWEN ,GPT4_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " GPT4_IPG_CLK_HWEN ,GPT4_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " GPT4_IPP_IND_CLKIN_STOP ,GPT4_IPP_IND_CLKIN clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " GPT4_IPP_IND_CLKIN_SWEN ,GPT4_IPP_IND_CLKIN clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " GPT4_IPP_IND_CLKIN_HWEN ,GPT4_IPP_IND_CLKIN clock HW signal treatment" "Ignored,Automatically gated" group.long 0x500000++0x03 line.long 0x00 "GPT5,GPT5 Clocks Register" rbitfld.long 0x00 19. " GPT5_IPG_CLK_STOP ,GPT5_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " GPT5_IPG_CLK_SWEN ,GPT5_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " GPT5_IPG_CLK_HWEN ,GPT5_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " GPT5_IPP_IND_CLKIN_STOP ,GPT5_IPP_IND_CLKIN clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " GPT5_IPP_IND_CLKIN_SWEN ,GPT5_IPP_IND_CLKIN clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " GPT5_IPP_IND_CLKIN_HWEN ,GPT5_IPP_IND_CLKIN clock HW signal treatment" "Ignored,Automatically gated" group.long 0x580000++0x03 line.long 0x00 "HIFI,HIFI Clocks Register" rbitfld.long 0x00 31. " HIFI_CORE_PBCLK_STOP ,HIFI_CORE_PBCLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 29. " HIFI_CORE_PBCLK_SWEN ,HIFI_CORE_PBCLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " HIFI_CORE_PBCLK_HWEN ,HIFI_CORE_PBCLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 23. " HIFI_CORE_CLK_STOP ,HIFI_CORE_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 21. " HIFI_CORE_CLK_SWEN ,HIFI_CORE_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 20. " HIFI_CORE_CLK_HWEN ,HIFI_CORE_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 19. " ADB_NIC0NIC1_SLV_ACLK_STOP ,ADB_NIC0NIC1_SLV_ACLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " ADB_NIC0NIC1_SLV_ACLK_SWEN ,ADB_NIC0NIC1_SLV_ACLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " ADB_NIC0NIC1_SLV_ACLK_HWEN ,ADB_NIC0NIC1_SLV_ACLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x590000++0x03 line.long 0x00 "OCRAM,OCRAM Clock Register" rbitfld.long 0x00 19. " OCRAM_CTRL_CLK_STOP ,OCRAM_CTRL_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " OCRAM_CTRL_CLK_SWEN ,OCRAM_CTRL_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " OCRAM_CTRL_CLK_HWEN ,OCRAM_CTRL_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x5F0000++0x03 line.long 0x00 "EDMA0,EDMA0 Clocks Register" rbitfld.long 0x00 19. " EDMA0_IPG_CLK_STOP ,EDMA0_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " EDMA0_IPG_CLK_SWEN ,EDMA0_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " EDMA0_IPG_CLK_HWEN ,EDMA0_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " EDMA0_HCLK_STOP ,EDMA0_HCLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " EDMA0_HCLK_SWEN ,EDMA0_HCLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " EDMA0_HCLK_HWEN ,EDMA0_HCLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0xC00000++0x03 line.long 0x00 "ASRC1,ASRC1 CLock Register" rbitfld.long 0x00 19. " ASRC1_IPG_CLK_STOP ,ASRC1_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " ASRC1_IPG_CLK_SWEN ,ASRC1_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " ASRC1_IPG_CLK_HWEN ,ASRC1_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0xC20000++0x03 line.long 0x00 "SAI4,SAI4 Clocks Register" rbitfld.long 0x00 19. " SAI4_IPG_CLK_STOP ,SAI4_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " SAI4_IPG_CLK_SWEN ,SAI4_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " SAI4_IPG_CLK_HWEN ,SAI4_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " SAI4_IPG_CLK_SAI_MCLK_1_STOP ,SAI4_IPG_CLK_SAI_MCLK_1 clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " SAI4_IPG_CLK_SAI_MCLK_1_SWEN ,SAI4_IPG_CLK_SAI_MCLK_1 clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " SAI4_IPG_CLK_SAI_MCLK_1_HWEN ,SAI4_IPG_CLK_SAI_MCLK_1 clock HW signal treatment" "Ignored,Automatically gated" group.long 0xC30000++0x03 line.long 0x00 "SAI5,SAI5 Clocks Register" rbitfld.long 0x00 19. " SAI5_IPG_CLK_STOP ,SAI5_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " SAI5_IPG_CLK_SWEN ,SAI5_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " SAI5_IPG_CLK_HWEN ,SAI5_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " SAI5_IPG_CLK_SAI_MCLK_1_STOP ,SAI5_IPG_CLK_SAI_MCLK_1 clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " SAI5_IPG_CLK_SAI_MCLK_1_SWEN ,SAI5_IPG_CLK_SAI_MCLK_1 clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " SAI5_IPG_CLK_SAI_MCLK_1_HWEN ,SAI5_IPG_CLK_SAI_MCLK_1 clock HW signal treatment" "Ignored,Automatically gated" group.long 0xC40000++0x03 line.long 0x00 "AMIX,AMIX Clock Register" rbitfld.long 0x00 3. " AMIX_IPG_CLK_STOP ,AMIX_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " AMIX_IPG_CLK_SWEN ,AMIX_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " AMIX_IPG_CLK_HWEN ,AMIX_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0xC50000++0x03 line.long 0x00 "MQS,MQS Clocks Register" rbitfld.long 0x00 19. " MQS_IPG_CLK_STOP ,MQS_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " MQS_IPG_CLK_SWEN ,MQS_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " MQS_IPG_CLK_HWEN ,MQS_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " MQS_HMCLK_STOP ,MQS_HMCLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " MQS_HMCLK_SWEN ,MQS_HMCLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " MQS_HMCLK_HWEN ,MQS_HMCLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0xC60000++0x03 line.long 0x00 "ACM,ACM CLocks Register" rbitfld.long 0x00 19. " ACM_IPG_CLK_STOP ,ACM_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " ACM_IPG_CLK_SWEN ,ACM_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " ACM_IPG_CLK_HWEN ,ACM_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0xD00000++0x03 line.long 0x00 "AUD_REC_CLK0,ACM_AUD_REC_CLK0 Clock Register" rbitfld.long 0x00 3. " ACM_AUD_REC_CLK0_STOP ,ACM_AUD_REC_CLK0 clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " ACM_AUD_REC_CLK0_SWEN ,ACM_AUD_REC_CLK0 clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " ACM_AUD_REC_CLK0_HWEN ,ACM_AUD_REC_CLK0 clock HW signal treatment" "Ignored,Automatically gated" group.long 0xD10000++0x03 line.long 0x00 "AUD_REC_CLK1,ACM_AUD_REC_CLK1 Clock Register" rbitfld.long 0x00 3. " ACM_AUD_REC_CLK1_STOP ,ACM_AUD_REC_CLK1 clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " ACM_AUD_REC_CLK1_SWEN ,ACM_AUD_REC_CLK1 clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " ACM_AUD_REC_CLK1_HWEN ,ACM_AUD_REC_CLK1 clock HW signal treatment" "Ignored,Automatically gated" group.long 0xD20000++0x03 line.long 0x00 "AUD_PLL_DIV_CLK0,AUD_PLL_DIV_CLK0 Clock Register" rbitfld.long 0x00 3. " ACM_AUD_PLL_DIV_CLK0_STOP ,ACM_AUD_PLL_DIV_CLK0 clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " ACM_AUD_PLL_DIV_CLK0_SWEN ,ACM_AUD_PLL_DIV_CLK0 clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " ACM_AUD_PLL_DIV_CLK0_HWEN ,ACM_AUD_PLL_DIV_CLK0 clock HW signal treatment" "Ignored,Automatically gated" group.long 0xD30000++0x03 line.long 0x00 "AUD_PLL_DIV_CLK1,AUD_PLL_DIV_CLK1 Clock Register" rbitfld.long 0x00 3. " ACM_AUD_PLL_DIV_CLK1_STOP ,ACM_AUD_PLL_DIV_CLK1 clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " ACM_AUD_PLL_DIV_CLK1_SWEN ,ACM_AUD_PLL_DIV_CLK1 clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " ACM_AUD_PLL_DIV_CLK1_HWEN ,ACM_AUD_PLL_DIV_CLK1 clock HW signal treatment" "Ignored,Automatically gated" group.long 0xD50000++0x03 line.long 0x00 "MCLKOUT0,MCLKOUT0 Clock Register" rbitfld.long 0x00 3. " MCLKOUT0_STOP ,MCLKOUT0 clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " MCLKOUT0_SWEN ,MCLKOUT0 clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " MCLKOUT0_HWEN ,MCLKOUT0 clock HW signal treatment" "Ignored,Automatically gated" group.long 0xD60000++0x03 line.long 0x00 "MCLKOUT1,MCLKOUT1 Clock Register" rbitfld.long 0x00 3. " MCLKOUT1_STOP ,MCLKOUT1 clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " MCLKOUT1_SWEN ,MCLKOUT1 clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " MCLKOUT1_HWEN ,MCLKOUT1 clock HW signal treatment" "Ignored,Automatically gated" group.long 0xDF0000++0x03 line.long 0x00 "EDMA1,EDMA1 Clocks Register" rbitfld.long 0x00 19. " EDMA1_IPG_CLK_STOP ,EDMA1_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " EDMA1_IPG_CLK_SWEN ,EDMA1_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " EDMA1_IPG_CLK_HWEN ,EDMA1_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " EDMA1_HCLK_STOP ,EDMA1_HCLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " EDMA1_HCLK_SWEN ,EDMA1_HCLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " EDMA1_HCLK_HWEN ,EDMA1_HCLK clock HW signal treatment" "Ignored,Automatically gated" tree.end base ad:0x5A000000 width 11. tree "SSI2 Registers" group.long 0x400000++0x03 line.long 0x00 "SPI0,SPI0 Clocks Register" rbitfld.long 0x00 19. " SPI0_IPG_CLK_STOP ,SPI0_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " SPI0_IPG_CLK_SWEN ,SPI0_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " SPI0_IPG_CLK_HWEN ,SPI0_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " SPI0_LPSPI_CLK_STOP ,SPI0_LPSPI_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " SPI0_LPSPI_CLK_SWEN ,SPI0_LPSPI_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " SPI0_LPSPI_CLK_HWEN ,SPI0_LPSPI_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x410000++0x03 line.long 0x00 "SPI1,SPI1 Clocks Register" rbitfld.long 0x00 19. " SPI1_IPG_CLK_STOP ,SPI1_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " SPI1_IPG_CLK_SWEN ,SPI1_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " SPI1_IPG_CLK_HWEN ,SPI1_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " SPI1_LPSPI_CLK_STOP ,SPI1_LPSPI_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " SPI1_LPSPI_CLK_SWEN ,SPI1_LPSPI_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " SPI1_LPSPI_CLK_HWEN ,SPI1_LPSPI_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x420000++0x03 line.long 0x00 "SPI2,SPI2 Clocks Register" rbitfld.long 0x00 19. " SPI2_IPG_CLK_STOP ,SPI2_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " SPI2_IPG_CLK_SWEN ,SPI2_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " SPI2_IPG_CLK_HWEN ,SPI2_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " SPI2_LPSPI_CLK_STOP ,SPI2_LPSPI_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " SPI2_LPSPI_CLK_SWEN ,SPI2_LPSPI_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " SPI2_LPSPI_CLK_HWEN ,SPI2_LPSPI_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x430000++0x03 line.long 0x00 "SPI3,SPI3 Clocks Register" rbitfld.long 0x00 19. " SPI3_IPG_CLK_STOP ,SPI3_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " SPI3_IPG_CLK_SWEN ,SPI3_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " SPI3_IPG_CLK_HWEN ,SPI3_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " SPI3_LPSPI_CLK_STOP ,SPI3_LPSPI_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " SPI3_LPSPI_CLK_SWEN ,SPI3_LPSPI_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " SPI3_LPSPI_CLK_HWEN ,SPI3_LPSPI_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x460000++0x03 line.long 0x00 "UART0,UART0 Clocks Register" rbitfld.long 0x00 19. " UART0_IPG_CLK_STOP ,UART0_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " UART0_IPG_CLK_SWEN ,UART0_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " UART0_IPG_CLK_HWEN ,UART0_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " UART0_LPUART_BAUD_CLK_STOP ,UART0_LPUART_BAUD_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " UART0_LPUART_BAUD_CLK_SWEN ,UART0_LPUART_BAUD_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " UART0_LPUART_BAUD_CLK_HWEN ,UART0_LPUART_BAUD_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x470000++0x03 line.long 0x00 "UART1,UART1 Clocks Register" rbitfld.long 0x00 19. " UART1_IPG_CLK_STOP ,UART1_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " UART1_IPG_CLK_SWEN ,UART1_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " UART1_IPG_CLK_HWEN ,UART1_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " UART1_LPUART_BAUD_CLK_STOP ,UART1_LPUART_BAUD_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " UART1_LPUART_BAUD_CLK_SWEN ,UART1_LPUART_BAUD_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " UART1_LPUART_BAUD_CLK_HWEN ,UART1_LPUART_BAUD_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x480000++0x03 line.long 0x00 "UART2,UART2 Clocks Register" rbitfld.long 0x00 19. " UART2_IPG_CLK_STOP ,UART2_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " UART2_IPG_CLK_SWEN ,UART2_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " UART2_IPG_CLK_HWEN ,UART2_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " UART2_LPUART_BAUD_CLK_STOP ,UART2_LPUART_BAUD_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " UART2_LPUART_BAUD_CLK_SWEN ,UART2_LPUART_BAUD_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " UART2_LPUART_BAUD_CLK_HWEN ,UART2_LPUART_BAUD_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x490000++0x03 line.long 0x00 "UART3,UART3 Clocks Register" rbitfld.long 0x00 19. " UART3_IPG_CLK_STOP ,UART3_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " UART3_IPG_CLK_SWEN ,UART3_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " UART3_IPG_CLK_HWEN ,UART3_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " UART3_LPUART_BAUD_CLK_STOP ,UART3_LPUART_BAUD_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " UART3_LPUART_BAUD_CLK_SWEN ,UART3_LPUART_BAUD_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " UART3_LPUART_BAUD_CLK_HWEN ,UART3_LPUART_BAUD_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x570000++0x03 line.long 0x00 "LCDIF_MUX,CLDIF_MUX Clocks Register" rbitfld.long 0x00 19. " LCDIF_MUX_IPG_CLK_STOP ,LCDIF_MUX_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " LCDIF_MUX_IPG_CLK_SWEN ,LCDIF_MUX_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " LCDIF_MUX_IPG_CLK_HWEN ,LCDIF_MUX_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 7. " LCDIF_MUX_PIXEL_LINK_SLV_CLK_STOP ,LCDIF_MUX_PIXEL_LINK_SLV_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 5. " LCDIF_MUX_PIXEL_LINK_SLV_CLK_SWEN ,LCDIF_MUX_PIXEL_LINK_SLV_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 4. " LCDIF_MUX_PIXEL_LINK_SLV_CLK_HWEN ,LCDIF_MUX_PIXEL_LINK_SLV_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 3. " PIXEL_LINK_SLV_INGRESS_CLK_STOP ,PIXEL_LINK_SLV_INGRESS_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " PIXEL_LINK_SLV_INGRESS_CLK_SWEN ,PIXEL_LINK_SLV_INGRESS_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PIXEL_LINK_SLV_INGRESS_CLK_HWEN ,PIXEL_LINK_SLV_INGRESS_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x580000++0x03 line.long 0x00 "LCDIF,LCDIF Clocks Register" rbitfld.long 0x00 19. " LCDIF_APB_CLK_STOP ,LCDIF_APB_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " LCDIF_APB_CLK_SWEN ,LCDIF_APB_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " LCDIF_APB_CLK_HWEN ,LCDIF_APB_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " LCDIF_PIX_CLK_STOP ,LCDIF_PIX_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " LCDIF_PIX_CLK_SWEN ,LCDIF_PIX_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " LCDIF_PIX_CLK_HWEN ,LCDIF_PIX_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x590000++0x03 line.long 0x00 "PWM,PWM Clocks Register" rbitfld.long 0x00 19. " PWM_IPG_CLK_STOP ,PWM_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " PWM_IPG_CLK_SWEN ,PWM_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " PWM_IPG_CLK_HWEN ,PWM_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " PWM_IPG_CLK_HIGHFREQ_STOP ,PWM_IPG_CLK_HIGHFREQ clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " PWM_IPG_CLK_HIGHFREQ_SWEN ,PWM_IPG_CLK_HIGHFREQ clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " PWM_IPG_CLK_HIGHFREQ_HWEN ,PWM_IPG_CLK_HIGHFREQ clock HW signal treatment" "Ignored,Automatically gated" group.long 0x5F0000++0x03 line.long 0x00 "EDMA2,EDMA2 Clocks Register" rbitfld.long 0x00 19. " EDMA2_IPG_CLK_STOP ,EDMA2_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " EDMA2_IPG_CLK_SWEN ,EDMA2_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " EDMA2_IPG_CLK_HWEN ,EDMA2_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " EDMA2_HCLK_STOP ,EDMA2_HCLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " EDMA2_HCLK_SWEN ,EDMA2_HCLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " EDMA2_HCLK_HWEN ,EDMA2_HCLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0xC00000++0x03 line.long 0x00 "I2C0,I2C0 Clocks Register" rbitfld.long 0x00 19. " I2C0_IPG_CLK_STOP ,I2C0_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " I2C0_IPG_CLK_SWEN ,I2C0_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " I2C0_IPG_CLK_HWEN ,I2C0_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " I2C0_LPI2C_CLK_STOP ,I2C0_LPI2C_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " I2C0_LPI2C_CLK_SWEN ,I2C0_LPI2C_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " I2C0_LPI2C_CLK_HWEN ,I2C0_LPI2C_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0xC10000++0x03 line.long 0x00 "I2C1,I2C1 Clocks Register" rbitfld.long 0x00 19. " I2C1_IPG_CLK_STOP ,I2C1_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " I2C1_IPG_CLK_SWEN ,I2C1_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " I2C1_IPG_CLK_HWEN ,I2C1_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " I2C1_LPI2C_CLK_STOP ,I2C1_LPI2C_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " I2C1_LPI2C_CLK_SWEN ,I2C1_LPI2C_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " I2C1_LPI2C_CLK_HWEN ,I2C1_LPI2C_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0xC20000++0x03 line.long 0x00 "I2C2,I2C2 Clocks Register" rbitfld.long 0x00 19. " I2C2_IPG_CLK_STOP ,I2C2_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " I2C2_IPG_CLK_SWEN ,I2C2_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " I2C2_IPG_CLK_HWEN ,I2C2_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " I2C2_LPI2C_CLK_STOP ,I2C2_LPI2C_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " I2C2_LPI2C_CLK_SWEN ,I2C2_LPI2C_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " I2C2_LPI2C_CLK_HWEN ,I2C2_LPI2C_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0xC30000++0x03 line.long 0x00 "I2C3,I2C3 Clocks Register" rbitfld.long 0x00 19. " I2C3_IPG_CLK_STOP ,I2C3_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " I2C3_IPG_CLK_SWEN ,I2C3_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " I2C3_IPG_CLK_HWEN ,I2C3_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " I2C3_LPI2C_CLK_STOP ,I2C3_LPI2C_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " I2C3_LPI2C_CLK_SWEN ,I2C3_LPI2C_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " I2C3_LPI2C_CLK_HWEN ,I2C3_LPI2C_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x00++0x03 line.long 0x00 "ADC0,ADC0 Clocks Register" rbitfld.long 0x00 19. " ANAMIX_IPG_CLK/CLK_S_ADC0_STOP ,ANAMIX_IPG_CLK/CLK_S clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " ANAMIX_IPG_CLK/CLK_S_ADC0_SWEN ,ANAMIX_IPG_CLK/CLK_S clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " ANAMIX_IPG_CLK/CLK_S_ADC0_HWEN ,ANAMIX_IPG_CLK/CLK_S clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " ANAMIX_IPG_CLK_ADC0_STOP ,ANAMIX_IPG_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " ANAMIX_IPG_CLK_ADC0_SWEN ,ANAMIX_IPG_CLK clock enable" "Disabled,Enabled" group.long 0xCA0000++0x03 line.long 0x00 "FTM0,FTM0 Clocks Register" rbitfld.long 0x00 19. " FTM0_IPG_CLK_STOP ,FTM0_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " FTM0_IPG_CLK_SWEN ,FTM0_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " FTM0_IPG_CLK_HWEN ,FTM0_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " FTM0_IPP_IND_EXTCLK_STOP ,FTM0_IPP_IND_EXTCLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " FTM0_IPP_IND_EXTCLK_SWEN ,FTM0_IPP_IND_EXTCLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " FTM0_IPP_IND_EXTCLK_HWEN ,FTM0_IPP_IND_EXTCLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0xCB0000++0x03 line.long 0x00 "FTM1,FTM1 Clocks Register" rbitfld.long 0x00 19. " FTM1_IPG_CLK_STOP ,FTM1_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " FTM1_IPG_CLK_SWEN ,FTM1_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " FTM1_IPG_CLK_HWEN ,FTM1_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " FTM1_IPP_IND_EXTCLK_STOP ,FTM1_IPP_IND_EXTCLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " FTM1_IPP_IND_EXTCLK_SWEN ,FTM1_IPP_IND_EXTCLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " FTM1_IPP_IND_EXTCLK_HWEN ,FTM1_IPP_IND_EXTCLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0xCD0000++0x03 line.long 0x00 "CAN0,CAN0 Clocks Register" rbitfld.long 0x00 23. " CAN0_IPG_CLK_CHI_STOP ,CAN0_IPG_CLK_CHI clock root status" "Not stopped,Stopped" bitfld.long 0x00 21. " CAN0_IPG_CLK_CHI_SWEN ,CAN0_IPG_CLK_CHI clock enable" "Disabled,Enabled" newline bitfld.long 0x00 20. " CAN0_IPG_CLK_CHI_HWEN ,CAN0_IPG_CLK_CHI clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 19. " CAN0_IPG_CLK_STOP ,CAN0_IPG_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 17. " CAN0_IPG_CLK_SWEN ,CAN0_IPG_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAN0_IPG_CLK_HWEN ,CAN0_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 3. " CAN0_IPG_CLK_PE_NOGATE_STOP ,CAN0_IPG_CLK_PE_NOGATE clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " CAN0_IPG_CLK_PE_NOGATE_SWEN ,CAN0_IPG_CLK_PE_NOGATE clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " CAN0_IPG_CLK_PE_NOGATE_HWEN ,CAN0_IPG_CLK_PE_NOGATE clock HW signal treatment" "Ignored,Automatically gated" group.long 0xCE0000++0x03 line.long 0x00 "CAN1,CAN1 Clocks Register" rbitfld.long 0x00 23. " CAN1_IPG_CLK_CHI_STOP ,CAN1_IPG_CLK_CHI clock root status" "Not stopped,Stopped" bitfld.long 0x00 21. " CAN1_IPG_CLK_CHI_SWEN ,CAN1_IPG_CLK_CHI clock enable" "Disabled,Enabled" newline bitfld.long 0x00 20. " CAN1_IPG_CLK_CHI_HWEN ,CAN1_IPG_CLK_CHI clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 19. " CAN1_IPG_CLK_STOP ,CAN1_IPG_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 17. " CAN1_IPG_CLK_SWEN ,CAN1_IPG_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAN1_IPG_CLK_HWEN ,CAN1_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 3. " CAN1_IPG_CLK_PE_NOGATE_STOP ,CAN1_IPG_CLK_PE_NOGATE clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " CAN1_IPG_CLK_PE_NOGATE_SWEN ,CAN1_IPG_CLK_PE_NOGATE clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " CAN1_IPG_CLK_PE_NOGATE_HWEN ,CAN1_IPG_CLK_PE_NOGATE clock HW signal treatment" "Ignored,Automatically gated" group.long 0xCF0000++0x03 line.long 0x00 "CAN2,CAN2 Clocks Register" rbitfld.long 0x00 23. " CAN2_IPG_CLK_CHI_STOP ,CAN2_IPG_CLK_CHI clock root status" "Not stopped,Stopped" bitfld.long 0x00 21. " CAN2_IPG_CLK_CHI_SWEN ,CAN2_IPG_CLK_CHI clock enable" "Disabled,Enabled" newline bitfld.long 0x00 20. " CAN2_IPG_CLK_CHI_HWEN ,CAN2_IPG_CLK_CHI clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 19. " CAN2_IPG_CLK_STOP ,CAN2_IPG_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 17. " CAN2_IPG_CLK_SWEN ,CAN2_IPG_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAN2_IPG_CLK_HWEN ,CAN2_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 3. " CAN2_IPG_CLK_PE_NOGATE_STOP ,CAN2_IPG_CLK_PE_NOGATE clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " CAN2_IPG_CLK_PE_NOGATE_SWEN ,CAN2_IPG_CLK_PE_NOGATE clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " CAN2_IPG_CLK_PE_NOGATE_HWEN ,CAN2_IPG_CLK_PE_NOGATE clock HW signal treatment" "Ignored,Automatically gated" group.long 0xDF0000++0x03 line.long 0x00 "EDMA3,EDMA3 Clocks Register" rbitfld.long 0x00 19. " EDMA3_IPG_CLK_STOP ,EDMA3_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " EDMA3_IPG_CLK_SWEN ,EDMA3_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " EDMA3_IPG_CLK_HWEN ,EDMA3_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " EDMA3_HCLK_STOP ,EDMA3_HCLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " EDMA3_HCLK_SWEN ,EDMA3_HCLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " EDMA3_HCLK_HWEN ,EDMA3_HCLK clock HW signal treatment" "Ignored,Automatically gated" tree.end base ad:0x51000000 width 5. tree "SSI3 Registers" group.long 0xF0000++0x03 line.long 0x00 "IRQ,IRQ Clocks Register" rbitfld.long 0x00 23. " GIC_CLK_STOP ,GIC_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 21. " GIC_CLK_SWEN ,GIC_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 20. " GIC_CLK_HWEN ,GIC_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 19. " IRQSTR_IPG_CLK_STOP ,IRQSTR_IPG_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 17. " IRQSTR_IPG_CLK_SWEN ,IRQSTR_IPG_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 16. " IRQSTR_IPG_CLK_HWEN ,IRQSTR_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 7. " ADB_S0_ACLK_STOP ,ADB_S0_ACLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 5. " ADB_S0_ACLK_SWEN ,ADB_S0_ACLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " ADB_S0_ACLK_HWEN ,ADB_S0_ACLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " ADB_M0_ACLK_STOP ,ADB_M0_ACLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " ADB_M0_ACLK_SWEN ,ADB_M0_ACLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " ADB_M0_ACLK_HWEN ,ADB_M0_ACLK clock HW signal treatment" "Ignored,Automatically gated" tree.end width 0x0B tree.end endif sif (cpuis("IMX8*-CM4")) tree "CM4 (ARM Cortex-M4)" base ad:0x37000000 width 14. group.long 0x5E0000++0x03 line.long 0x00 "TCMC_HCLK_0,TCMC_HCLK Clock Register" rbitfld.long 0x00 3. " CM4_TCMC_HCLK_STOP ,TCMC_HCLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " CM4_TCMC_HCLK_SWEN ,TCMC_HCLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " CM4_TCMC_HCLK_HWEN ,TCMC_HCLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x5F0000++0x03 line.long 0x00 "MMCAU_HCLK_0,MMCAU_HCLK Clock Register" rbitfld.long 0x00 3. " CM4_MMCAU_HCLK_STOP ,MMCAU_HCLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " CM4_MMCAU_HCLK_SWEN ,MMCAU_HCLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " CM4_MMCAU_HCLK_HWEN ,MMCAU_HCLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x600000++0x03 line.long 0x00 "TPM_0,TPM Clocks Register" rbitfld.long 0x00 7. " TPM1_IPG_CLK_STOP ,TPM1_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 5. " TPM1_IPG_CLK_SWEN ,TPM1_IPG_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 4. " TPM1_IPG_CLK_HWEN ,TPM1_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 3. " TPM1_LPTPM_CLK_STOP ,TPM1_LPTPM_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " TPM1_LPTPM_CLK_SWEN ,TPM1_LPTPM_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " TPM1_LPTPM_CLK_HWEN ,TPM1_LPTPM_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x610000++0x03 line.long 0x00 "LPIT_0,LPIT Clocks Register" rbitfld.long 0x00 7. " LPIT1_IPG_CLK_STOP ,LPIT1_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 5. " LPIT1_IPG_CLK_SWEN ,LPIT1_IPG_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 4. " LPIT1_IPG_CLK_HWEN ,LPIT1_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 3. " LPIT_IPG_PER_CLK_STOP ,LPIT_IPG_PER_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " LPIT_IPG_PER_CLK_SWEN ,LPIT_IPG_PER_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " LPIT_IPG_PER_CLK_HWEN ,LPIT_IPG_PER_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x620000++0x03 line.long 0x00 "LPUART_0,LPUART Clocks Register" rbitfld.long 0x00 7. " LPUART_IPG_CLK_STOP ,LPUART_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 5. " LPUART_IPG_CLK_SWEN ,LPUART_IPG_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 4. " LPUART_IPG_CLK_HWEN ,LPUART_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 3. " LPUART1_LPUART_BAUD_CLK_STOP ,LPUART1_LPUART_BAUD_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " LPUART1_LPUART_BAUD_CLK_SWEN ,LPUART1_LPUART_BAUD_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " LPUART1_LPUART_BAUD_CLK_HWEN ,LPUART1_LPUART_BAUD_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x630000++0x03 line.long 0x00 "LPI2C_0,LPI2C Clocks Register" rbitfld.long 0x00 7. " LPI2C1_IPG_CLK_STOP ,LPI2C1_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 5. " LPI2C1_IPG_CLK_SWEN ,LPI2C1_IPG_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 4. " LPI2C1_IPG_CLK_HWEN ,LPI2C1_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 3. " LPI2C1_LPI2C_CLK_STOP ,LPI2C1_LPI2C_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " LPI2C1_LPI2C_CLK_SWEN ,LPI2C1_LPI2C_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " LPI2C1_LPI2C_CLK_HWEN ,LPI2C1_LPI2C_CLK clock HW signal treatment" "Ignored,Automatically gated" width 0x0B tree.end endif sif (!cpuis("IMX8*-CM4")&&!cpuis("IMX8*-SCU")) tree "CONNECTIVITY" base ad:0x5B000000 width 11. group.long 0x200000++0x03 line.long 0x00 "USDHC1,USDHC1 Clocks Register" rbitfld.long 0x00 23. " USDHC1_HCLK_STOP ,USDHC1_HCLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 21. " USDHC1_HCLK_SWEN ,USDHC1_HCLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 20. " USDHC1_HCLK_HWEN ,USDHC1_HCLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 19. " USDHC1_IPG_CLK_S_STOP ,USDHC1_IPG_CLK_S clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 17. " USDHC1_IPG_CLK_S_SWEN ,USDHC1_IPG_CLK_S clock enable" "Disabled,Enabled" bitfld.long 0x00 16. " USDHC1_IPG_CLK_S_HWEN ,USDHC1_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 3. " USDHC1_IPG_CLK_PERCLK_STOP ,USDHC1_IPG_CLK_PERCLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " USDHC1_IPG_CLK_PERCLK_SWEN ,USDHC1_IPG_CLK_PERCLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " USDHC1_IPG_CLK_PERCLK_HWEN ,USDHC1_IPG_CLK_PERCLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x210000++0x03 line.long 0x00 "USDHC2,USDHC2 Clocks Register" rbitfld.long 0x00 23. " USDHC2_HCLK_STOP ,USDHC2_HCLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 21. " USDHC2_HCLK_SWEN ,USDHC2_HCLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 20. " USDHC2_HCLK_HWEN ,USDHC2_HCLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 19. " USDHC2_IPG_CLK_S_STOP ,USDHC2_IPG_CLK_S clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 17. " USDHC2_IPG_CLK_S_SWEN ,USDHC2_IPG_CLK_S clock enable" "Disabled,Enabled" bitfld.long 0x00 16. " USDHC2_IPG_CLK_S_HWEN ,USDHC2_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 3. " USDHC2_IPG_CLK_PERCLK_STOP ,USDHC2_IPG_CLK_PERCLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " USDHC2_IPG_CLK_PERCLK_SWEN ,USDHC2_IPG_CLK_PERCLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " USDHC2_IPG_CLK_PERCLK_HWEN ,USDHC2_IPG_CLK_PERCLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x220000++0x03 line.long 0x00 "USDHC3,USDHC3 Clocks Register" rbitfld.long 0x00 23. " USDHC3_HCLK_STOP ,USDHC3_HCLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 21. " USDHC3_HCLK_SWEN ,USDHC3_HCLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 20. " USDHC3_HCLK_HWEN ,USDHC3_HCLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 19. " USDHC3_IPG_CLK_S_STOP ,USDHC3_IPG_CLK_S clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 17. " USDHC3_IPG_CLK_S_SWEN ,USDHC3_IPG_CLK_S clock enable" "Disabled,Enabled" bitfld.long 0x00 16. " USDHC3_IPG_CLK_S_HWEN ,USDHC3_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 3. " USDHC3_IPG_CLK_PERCLK_STOP ,USDHC3_IPG_CLK_PERCLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " USDHC3_IPG_CLK_PERCLK_SWEN ,USDHC3_IPG_CLK_PERCLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " USDHC3_IPG_CLK_PERCLK_HWEN ,USDHC3_IPG_CLK_PERCLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x230000++0x07 line.long 0x00 "ENET0_0,ENET0_0 Clocks Register" rbitfld.long 0x00 23. " ENET1_IPG_CLK_MAC0_S_STOP ,ENET1_IPG_CLK_MAC0_S clock root status" "Not stopped,Stopped" bitfld.long 0x00 21. " ENET1_IPG_CLK_MAC0_S_SWEN ,ENET1_IPG_CLK_MAC0_S clock enable" "Disabled,Enabled" newline bitfld.long 0x00 20. " ENET1_IPG_CLK_MAC0_S_HWEN ,ENET1_IPG_CLK_MAC0_S clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 19. " ENET1_IPG_CLK_STOP ,ENET1_IPG_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 17. " ENET1_IPG_CLK_SWEN ,ENET1_IPG_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 16. " ENET1_IPG_CLK_HWEN ,ENET1_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 15. " ENET1_CLKDIV_CLK_IN_STOP ,ENET1_CLKDIV_CLK_IN clock root status" "Not stopped,Stopped" bitfld.long 0x00 13. " ENET1_CLKDIV_CLK_IN_SWEN ,ENET1_CLKDIV_CLK_IN clock enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " ENET1_CLKDIV_CLK_IN_HWEN ,ENET1_CLKDIV_CLK_IN clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 11. " ENET_MEM1_MAC0_TXMEM_CLK_STOP ,ENET_MEM1_MAC0_TXMEM_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 9. " ENET_MEM1_MAC0_TXMEM_CLK_SWEN ,ENET_MEM1_MAC0_TXMEM_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 8. " ENET_MEM1_MAC0_TXMEM_CLK_HWEN ,ENET_MEM1_MAC0_TXMEM_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 7. " ENET1_2X_TXCLK_STOP ,ENET1_2X_TXCLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 5. " ENET1_2X_TXCLK_SWEN ,ENET1_2X_TXCLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " ENET1_2X_TXCLK_HWEN ,ENET1_2X_TXCLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " ENET1_IPG_CLK_TIME_STOP ,ENET1_IPG_CLK_TIME clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " ENET1_IPG_CLK_TIME_SWEN ,ENET1_IPG_CLK_TIME clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " ENET1_IPG_CLK_TIME_HWEN ,ENET1_IPG_CLK_TIME clock HW signal treatment" "Ignored,Automatically gated" line.long 0x04 "ENET0_4,ENET0_4 Clocks Register" rbitfld.long 0x04 3. " ENET1_MAC0_RXCLK_STOP ,ENET1_MAC0_RXCLK clock root status" "Not stopped,Stopped" bitfld.long 0x04 1. " ENET1_MAC0_RXCLK_SWEN ,ENET1_MAC0_RXCLK clock enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " ENET1_MAC0_RXCLK_HWEN ,ENET1_MAC0_RXCLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x240000++0x07 line.long 0x00 "ENET1_0,ENET1_0 Clocks Register" rbitfld.long 0x00 23. " ENET2_IPG_CLK_MAC0_S_STOP ,ENET2_IPG_CLK_MAC0_S clock root status" "Not stopped,Stopped" bitfld.long 0x00 21. " ENET2_IPG_CLK_MAC0_S_SWEN ,ENET2_IPG_CLK_MAC0_S clock enable" "Disabled,Enabled" newline bitfld.long 0x00 20. " ENET2_IPG_CLK_MAC0_S_HWEN ,ENET2_IPG_CLK_MAC0_S clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 19. " ENET2_IPG_CLK_STOP ,ENET2_IPG_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 17. " ENET2_IPG_CLK_SWEN ,ENET2_IPG_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 16. " ENET2_IPG_CLK_HWEN ,ENET2_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 15. " ENET2_CLKDIV_CLK_IN_STOP ,ENET2_CLKDIV_CLK_IN clock root status" "Not stopped,Stopped" bitfld.long 0x00 13. " ENET2_CLKDIV_CLK_IN_SWEN ,ENET2_CLKDIV_CLK_IN clock enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " ENET2_CLKDIV_CLK_IN_HWEN ,ENET2_CLKDIV_CLK_IN clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 11. " ENET_MEM2_MAC0_TXMEM_CLK_STOP ,ENET_MEM2_MAC0_TXMEM_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 9. " ENET_MEM2_MAC0_TXMEM_CLK_SWEN ,ENET_MEM2_MAC0_TXMEM_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 8. " ENET_MEM2_MAC0_TXMEM_CLK_HWEN ,ENET_MEM2_MAC0_TXMEM_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 7. " ENET2_2X_TXCLK_STOP ,ENET2_2X_TXCLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 5. " ENET2_2X_TXCLK_SWEN ,ENET2_2X_TXCLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " ENET2_2X_TXCLK_HWEN ,ENET2_2X_TXCLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " ENET2_IPG_CLK_TIME_STOP ,ENET2_IPG_CLK_TIME clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " ENET2_IPG_CLK_TIME_SWEN ,ENET2_IPG_CLK_TIME clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " ENET2_IPG_CLK_TIME_HWEN ,ENET2_IPG_CLK_TIME clock HW signal treatment" "Ignored,Automatically gated" line.long 0x04 "ENET1_4,ENET1_4 Clocks Register" rbitfld.long 0x04 3. " ENET2_MAC0_RXCLK_STOP ,ENET2_MAC0_RXCLK clock root status" "Not stopped,Stopped" bitfld.long 0x04 1. " ENET2_MAC0_RXCLK_SWEN ,ENET2_MAC0_RXCLK clock enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " ENET2_MAC0_RXCLK_HWEN ,ENET2_MAC0_RXCLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x260000++0x03 line.long 0x00 "MLB,MLB Clocks Register" rbitfld.long 0x00 23. " MLB_HCLK_STOP ,MLB_HCLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 21. " MLB_HCLK_SWEN ,MLB_HCLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 20. " MLB_HCLK_HWEN ,MLB_HCLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 19. " MLB_IPG_CLK_S_STOP ,MLB_IPG_CLK_S clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 17. " MLB_IPG_CLK_S_SWEN ,MLB_IPG_CLK_S clock enable" "Disabled,Enabled" bitfld.long 0x00 16. " MLB_IPG_CLK_S_HWEN ,MLB_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 3. " MLB_SYS_CLK_STOP ,MLB_SYS_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " MLB_SYS_CLK_SWEN ,MLB_SYS_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " MLB_SYS_CLK_HWEN ,MLB_SYS_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x270000++0x03 line.long 0x00 "USB2,USB2 Clocks Register" rbitfld.long 0x00 31. " DA_IP_HS_USB2PHY_28FDSOI_IPG_CLK_STOP ,DA_IP_HS_USB2PHY_28FDSOI_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 29. " DA_IP_HS_USB2PHY_28FDSOI_IPG_CLK_SWEN ,DA_IP_HS_USB2PHY_28FDSOI_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " DA_IP_HS_USB2PHY_28FDSOI_IPG_CLK_HWEN ,DA_IP_HS_USB2PHY_28FDSOI_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 27. " USBOH_IPG_AHB_CLK_STOP ,USBOH_IPG_AHB_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 25. " USBOH_IPG_AHB_CLK_SWEN ,USBOH_IPG_AHB_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 24. " USBOH_IPG_AHB_CLK_HWEN ,USBOH_IPG_AHB_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 23. " USBOH_IPG_CLK_S_PL301_STOP ,USBOH_IPG_CLK_S_PL301 clock root status" "Not stopped,Stopped" bitfld.long 0x00 21. " USBOH_IPG_CLK_S_PL301_SWEN ,USBOH_IPG_CLK_S_PL301 clock enable" "Disabled,Enabled" newline bitfld.long 0x00 20. " USBOH_IPG_CLK_S_PL301_HWEN ,USBOH_IPG_CLK_S_PL301 clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 19. " USBOH_IPG_CLK_S_STOP ,USBOH_IPG_CLK_S clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 17. " USBOH_IPG_CLK_S_SWEN ,USBOH_IPG_CLK_S clock enable" "Disabled,Enabled" bitfld.long 0x00 16. " USBOH_IPG_CLK_S_HWEN ,USBOH_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" group.long 0x280000++0x03 line.long 0x00 "USB3,USB3 Clocks Register" rbitfld.long 0x00 31. " DA_IP_USB3_WRAP_USB3_ACLK_STOP ,DA_IP_USB3_WRAP_USB3_ACLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 29. " DA_IP_USB3_WRAP_USB3_ACLK_SWEN ,DA_IP_USB3_WRAP_USB3_ACLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " DA_IP_USB3_WRAP_USB3_ACLK_HWEN ,DA_IP_USB3_WRAP_USB3_ACLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 27. " DA_IP_USB3_WRAP_USB3_SSPHY_PCLK_STOP ,DA_IP_USB3_WRAP_USB3_SSPHY_PCLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 25. " DA_IP_USB3_WRAP_USB3_SSPHY_PCLK_SWEN ,DA_IP_USB3_WRAP_USB3_SSPHY_PCLK clock enable" "Disabled,Enabled" bitfld.long 0x00 24. " DA_IP_USB3_WRAP_USB3_SSPHY_PCLK_HWEN ,DA_IP_USB3_WRAP_USB3_SSPHY_PCLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 23. " DA_IP_USB3_WRAP_USB3_CORE_PCLK_STOP ,DA_IP_USB3_WRAP_USB3_CORE_PCLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 21. " DA_IP_USB3_WRAP_USB3_CORE_PCLK_SWEN ,DA_IP_USB3_WRAP_USB3_CORE_PCLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 20. " DA_IP_USB3_WRAP_USB3_CORE_PCLK_HWEN ,DA_IP_USB3_WRAP_USB3_CORE_PCLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 19. " DA_IP_USB3_WRAP_IPG_CLK_STOP ,DA_IP_USB3_WRAP_IPG_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 17. " DA_IP_USB3_WRAP_IPG_CLK_SWEN ,DA_IP_USB3_WRAP_IPG_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 16. " DA_IP_USB3_WRAP_IPG_CLK_HWEN ,DA_IP_USB3_WRAP_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 7. " DA_IP_USB3_WRAP_LPM_CLK_PREDFT_STOP ,DA_IP_USB3_WRAP_LPM_CLK_PREDFT clock root status" "Not stopped,Stopped" bitfld.long 0x00 5. " DA_IP_USB3_WRAP_LPM_CLK_PREDFT_SWEN ,DA_IP_USB3_WRAP_LPM_CLK_PREDFT clock enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " DA_IP_USB3_WRAP_LPM_CLK_PREDFT_HWEN ,DA_IP_USB3_WRAP_LPM_CLK_PREDFT clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " DA_IP_USB3_WRAP_APP_CLK_125_PREDFT_STOP ,DA_IP_USB3_WRAP_APP_CLK_125_PREDFT clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " DA_IP_USB3_WRAP_APP_CLK_125_PREDFT_SWEN ,DA_IP_USB3_WRAP_APP_CLK_125_PREDFT clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " DA_IP_USB3_WRAP_APP_CLK_125_PREDFT_HWEN ,DA_IP_USB3_WRAP_APP_CLK_125_PREDFT clock HW signal treatment" "Ignored,Automatically gated" group.long 0x290000++0x07 line.long 0x00 "RAWNAND_0,RAWNAND_0 Clocks Register" rbitfld.long 0x00 23. " RAWNAND_U_BCH_INPUT_APB_CLK_STOP ,RAWNAND_U_BCH_INPUT_APB_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 21. " RAWNAND_U_BCH_INPUT_APB_CLK_SWEN ,RAWNAND_U_BCH_INPUT_APB_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 20. " RAWNAND_U_BCH_INPUT_APB_CLK_HWEN ,RAWNAND_U_BCH_INPUT_APB_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 19. " RAWNAND_U_GPMI_INPUT_APB_CLK_STOP ,RAWNAND_U_GPMI_INPUT_APB_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 17. " RAWNAND_U_GPMI_INPUT_APB_CLK_SWEN ,RAWNAND_U_GPMI_INPUT_APB_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 16. " RAWNAND_U_GPMI_INPUT_APB_CLK_HWEN ,RAWNAND_U_GPMI_INPUT_APB_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 7. " RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_CLK_STOP ,RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 5. " RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_CLK_SWEN ,RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_CLK_HWEN ,RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " RAWNAND_U_GPMI_BCH_INPUT_BCH_CLK_STOP ,RAWNAND_U_GPMI_BCH_INPUT_BCH_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " RAWNAND_U_GPMI_BCH_INPUT_BCH_CLK_SWEN ,RAWNAND_U_GPMI_BCH_INPUT_BCH_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " RAWNAND_U_GPMI_BCH_INPUT_BCH_CLK_HWEN ,RAWNAND_U_GPMI_BCH_INPUT_BCH_CLK clock HW signal treatment" "Ignored,Automatically gated" line.long 0x04 "RAWNAND_4,RAWNAND_4 Clocks Register" rbitfld.long 0x04 19. " APBHDMA_HCLK_STOP ,APBHDMA_HCLK clock root status" "Not stopped,Stopped" bitfld.long 0x04 17. " APBHDMA_HCLK_SWEN ,APBHDMA_HCLK clock enable" "Disabled,Enabled" newline bitfld.long 0x04 16. " APBHDMA_HCLK_HWEN ,APBHDMA_HCLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x2A0000++0x03 line.long 0x00 "EDMA,EDMA Clocks Register" rbitfld.long 0x00 19. " EDMA_IPG_CLK_STOP ,EDMA_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " EDMA_IPG_CLK_SWEN ,EDMA_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " EDMA_IPG_CLK_HWEN ,EDMA_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " EDMA_HCLK_STOP ,EDMA_HCLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " EDMA_HCLK_SWEN ,EDMA_HCLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " EDMA_HCLK_HWEN ,EDMA_HCLK clock HW signal treatment" "Ignored,Automatically gated" width 0x0B tree.end endif sif (cpuis("IMX8*-SCU")) tree "DB (DRAM Block)" base ad:0x5C000000 width 5. group.long 0x4F0000++0x03 line.long 0x00 "PG0,PG0 Clocks Register" rbitfld.long 0x00 23. " PG0_F_GATED_STOP ,PG0_F_GATED clock root status" "Not stopped,Stopped" bitfld.long 0x00 21. " PG0_F_GATED_SWEN ,PG0_F_GATED clock enable" "Disabled,Enabled" bitfld.long 0x00 20. " PG0_F_GATED_HWEN ,PG0_F_GATED clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 19. " PG0_E_GATED_STOP ,PG0_E_GATED clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " PG0_E_GATED_SWEN ,PG0_E_GATED clock enable" "Disabled,Enabled" bitfld.long 0x00 16. " PG0_E_GATED_HWEN ,PG0_E_GATED clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 15. " PG0_D_GATED_STOP ,PG0_D_GATED clock root status" "Not stopped,Stopped" bitfld.long 0x00 13. " PG0_D_GATED_SWEN ,PG0_D_GATED clock enable" "Disabled,Enabled" bitfld.long 0x00 12. " PG0_D_GATED_HWEN ,PG0_D_GATED clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 11. " PG0_C_GATED_STOP ,PG0_C_GATED clock root status" "Not stopped,Stopped" bitfld.long 0x00 9. " PG0_C_GATED_SWEN ,PG0_C_GATED clock enable" "Disabled,Enabled" bitfld.long 0x00 8. " PG0_C_GATED_HWEN ,PG0_C_GATED clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 7. " PG0_B_GATED_STOP ,PG0_B_GATED clock root status" "Not stopped,Stopped" bitfld.long 0x00 5. " PG0_B_GATED_SWEN ,PG0_B_GATED clock enable" "Disabled,Enabled" bitfld.long 0x00 4. " PG0_B_GATED_HWEN ,PG0_B_GATED clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 3. " PG0_A_GATED_STOP ,PG0_A_GATED clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " PG0_A_GATED_SWEN ,PG0_A_GATED clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " PG0_A_GATED_HWEN ,PG0_A_GATED clock HW signal treatment" "Ignored,Automatically gated" group.long 0x5F0000++0x03 line.long 0x00 "PG1,PG1 Clocks Register" rbitfld.long 0x00 23. " PG1_F_GATED_STOP ,PG1_F_GATED clock root status" "Not stopped,Stopped" bitfld.long 0x00 21. " PG1_F_GATED_SWEN ,PG1_F_GATED clock enable" "Disabled,Enabled" bitfld.long 0x00 20. " PG1_F_GATED_HWEN ,PG1_F_GATED clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 19. " PG1_E_GATED_STOP ,PG1_E_GATED clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " PG1_E_GATED_SWEN ,PG1_E_GATED clock enable" "Disabled,Enabled" bitfld.long 0x00 16. " PG1_E_GATED_HWEN ,PG1_E_GATED clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 15. " PG1_D_GATED_STOP ,PG1_D_GATED clock root status" "Not stopped,Stopped" bitfld.long 0x00 13. " PG1_D_GATED_SWEN ,PG1_D_GATED clock enable" "Disabled,Enabled" bitfld.long 0x00 12. " PG1_D_GATED_HWEN ,PG1_D_GATED clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 11. " PG1_C_GATED_STOP ,PG1_C_GATED clock root status" "Not stopped,Stopped" bitfld.long 0x00 9. " PG1_C_GATED_SWEN ,PG1_C_GATED clock enable" "Disabled,Enabled" bitfld.long 0x00 8. " PG1_C_GATED_HWEN ,PG1_C_GATED clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 7. " PG1_B_GATED_STOP ,PG1_B_GATED clock root status" "Not stopped,Stopped" bitfld.long 0x00 5. " PG1_B_GATED_SWEN ,PG1_B_GATED clock enable" "Disabled,Enabled" bitfld.long 0x00 4. " PG1_B_GATED_HWEN ,PG1_B_GATED clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 3. " PG1_A_GATED_STOP ,PG1_A_GATED clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " PG1_A_GATED_SWEN ,PG1_A_GATED clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " PG1_A_GATED_HWEN ,PG1_A_GATED clock HW signal treatment" "Ignored,Automatically gated" group.long 0x6F0000++0x03 line.long 0x00 "PG2,PG2 Clocks Register" rbitfld.long 0x00 23. " PG2_F_GATED_STOP ,PG2_F_GATED clock root status" "Not stopped,Stopped" bitfld.long 0x00 21. " PG2_F_GATED_SWEN ,PG2_F_GATED clock enable" "Disabled,Enabled" bitfld.long 0x00 20. " PG2_F_GATED_HWEN ,PG2_F_GATED clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 19. " PG2_E_GATED_STOP ,PG2_E_GATED clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " PG2_E_GATED_SWEN ,PG2_E_GATED clock enable" "Disabled,Enabled" bitfld.long 0x00 16. " PG2_E_GATED_HWEN ,PG2_E_GATED clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 15. " PG2_D_GATED_STOP ,PG2_D_GATED clock root status" "Not stopped,Stopped" bitfld.long 0x00 13. " PG2_D_GATED_SWEN ,PG2_D_GATED clock enable" "Disabled,Enabled" bitfld.long 0x00 12. " PG2_D_GATED_HWEN ,PG2_D_GATED clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 11. " PG2_C_GATED_STOP ,PG2_C_GATED clock root status" "Not stopped,Stopped" bitfld.long 0x00 9. " PG2_C_GATED_SWEN ,PG2_C_GATED clock enable" "Disabled,Enabled" bitfld.long 0x00 8. " PG2_C_GATED_HWEN ,PG2_C_GATED clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 7. " PG2_B_GATED_STOP ,PG2_B_GATED clock root status" "Not stopped,Stopped" bitfld.long 0x00 5. " PG2_B_GATED_SWEN ,PG2_B_GATED clock enable" "Disabled,Enabled" bitfld.long 0x00 4. " PG2_B_GATED_HWEN ,PG2_B_GATED clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 3. " PG2_A_GATED_STOP ,PG2_A_GATED clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " PG2_A_GATED_SWEN ,PG2_A_GATED clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " PG2_A_GATED_HWEN ,PG2_A_GATED clock HW signal treatment" "Ignored,Automatically gated" group.long 0xAF0000++0x03 line.long 0x00 "BN,BN Clock Register" rbitfld.long 0x00 3. " BN_GATED_STOP ,BN_GATED clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " BN_GATED_SWEN ,BN_GATED clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " BN_GATED_HWEN ,BN_GATED clock HW signal treatment" "Ignored,Automatically gated" width 0x0B tree.end endif sif (!cpuis("IMX8*-CM4")&&!cpuis("IMX8*-SCU")) tree.open "Display/Imaging/Camera" tree "DC (Display Controller)" base ad:0x56000000 width 4. group.long 0x10000++0x0B line.long 0x00 "0,DC_0 Clocks Register" rbitfld.long 0x00 7. " DSP1_CLK_STOP ,DSP1_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 5. " DSP1_CLK_SWEN ,DSP1_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " DSP1_CLK_HWEN ,DSP1_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " DSP0_CLK_STOP ,DSP0_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " DSP0_CLK_SWEN ,DSP0_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " DSP0_CLK_HWEN ,DSP0_CLK clock HW signal treatment" "Ignored,Automatically gated" line.long 0x04 "4,DC_4 Clocks Register" rbitfld.long 0x04 19. " LIS_IPG_CLK_STOP ,LIS_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x04 17. " LIS_IPG_CLK_SWEN ,LIS_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x04 16. " LIS_IPG_CLK_HWEN ,LIS_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" line.long 0x08 "8,DC_8 Clocks Register" rbitfld.long 0x08 19. " DISPLAY_CTRL_LINK_MST0_MSI_CLK_STOP ,DISPLAY_CTRL_LINK_MST0_MSI_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x08 17. " DISPLAY_CTRL_LINK_MST0_MSI_CLK_SWEN ,DISPLAY_CTRL_LINK_MST0_MSI_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x08 16. " DISPLAY_CTRL_LINK_MST0_MSI_CLK_HWEN ,DISPLAY_CTRL_LINK_MST0_MSI_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x10010++0x0F line.long 0x00 "16,DC_16 Clocks Register" rbitfld.long 0x00 19. " PIXEL_COMBINER_APB_CLK_STOP ,PIXEL_COMBINER_APB_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " PIXEL_COMBINER_APB_CLK_SWEN ,PIXEL_COMBINER_APB_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " PIXEL_COMBINER_APB_CLK_HWEN ,PIXEL_COMBINER_APB_CLK clock HW signal treatment" "Ignored,Automatically gated" line.long 0x04 "20,DC_20 Clocks Register" rbitfld.long 0x04 23. " IRIS_MVPL_AXI_CLK_STOP ,IRIS_MVPL_AXI_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x04 21. " IRIS_MVPL_AXI_CLK_SWEN ,IRIS_MVPL_AXI_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x04 20. " IRIS_MVPL_AXI_CLK_HWEN ,IRIS_MVPL_AXI_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x04 19. " IRIS_MVPL_CFG_CLK_STOP ,IRIS_MVPL_CFG_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x04 17. " IRIS_MVPL_CFG_CLK_SWEN ,IRIS_MVPL_CFG_CLK clock enable" "Disabled,Enabled" bitfld.long 0x04 16. " IRIS_MVPL_CFG_CLK_HWEN ,IRIS_MVPL_CFG_CLK clock HW signal treatment" "Ignored,Automatically gated" line.long 0x08 "24,DC_24 Clocks Register" rbitfld.long 0x08 23. " DPR0_DPR_B_CLKG_STOP ,DPR0_DPR_B_CLKG clock root status" "Not stopped,Stopped" bitfld.long 0x08 21. " DPR0_DPR_B_CLKG_SWEN ,DPR0_DPR_B_CLKG clock enable" "Disabled,Enabled" newline bitfld.long 0x08 20. " DPR0_DPR_B_CLKG_HWEN ,DPR0_DPR_B_CLKG clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x08 19. " DPR0_DPR_APB_CLKG_STOP ,DPR0_DPR_APB_CLKG clock root status" "Not stopped,Stopped" newline bitfld.long 0x08 17. " DPR0_DPR_APB_CLKG_SWEN ,DPR0_DPR_APB_CLKG clock enable" "Disabled,Enabled" bitfld.long 0x08 16. " DPR0_DPR_APB_CLKG_HWEN ,DPR0_DPR_APB_CLKG clock HW signal treatment" "Ignored,Automatically gated" line.long 0x0C "28,DC_28 Clocks Register" rbitfld.long 0x0C 3. " RTRAM0_RTR_CLK_G_STOP ,RTRAM0_RTR_CLK_G clock root status" "Not stopped,Stopped" bitfld.long 0x0C 1. " RTRAM0_RTR_CLK_G_SWEN ,RTRAM0_RTR_CLK_G clock enable" "Disabled,Enabled" newline bitfld.long 0x0C 0. " RTRAM0_RTR_CLK_G_HWEN ,RTRAM0_RTR_CLK_G clock HW signal treatment" "Ignored,Automatically gated" group.long 0x10020++0x03 line.long 0x00 "32,DC_32 Clocks Register" rbitfld.long 0x00 19. " PRG0_APB_CLK_STOP ,PRG0_APB_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " PRG0_APB_CLK_SWEN ,PRG0_APB_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " PRG0_APB_CLK_HWEN ,PRG0_APB_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " PRG0_RTRAM_CLK_STOP ,PRG0_RTRAM_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " PRG0_RTRAM_CLK_SWEN ,PRG0_RTRAM_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " PRG0_RTRAM_CLK_HWEN ,PRG0_RTRAM_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x10024++0x03 line.long 0x00 "36,DC_36 Clocks Register" rbitfld.long 0x00 19. " PRG1_APB_CLK_STOP ,PRG1_APB_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " PRG1_APB_CLK_SWEN ,PRG1_APB_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " PRG1_APB_CLK_HWEN ,PRG1_APB_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " PRG1_RTRAM_CLK_STOP ,PRG1_RTRAM_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " PRG1_RTRAM_CLK_SWEN ,PRG1_RTRAM_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " PRG1_RTRAM_CLK_HWEN ,PRG1_RTRAM_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x10028++0x03 line.long 0x00 "40,DC_40 Clocks Register" rbitfld.long 0x00 19. " PRG2_APB_CLK_STOP ,PRG2_APB_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " PRG2_APB_CLK_SWEN ,PRG2_APB_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " PRG2_APB_CLK_HWEN ,PRG2_APB_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " PRG2_RTRAM_CLK_STOP ,PRG2_RTRAM_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " PRG2_RTRAM_CLK_SWEN ,PRG2_RTRAM_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " PRG2_RTRAM_CLK_HWEN ,PRG2_RTRAM_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x1002C++0x07 line.long 0x00 "44,DC_44 Clocks Register" rbitfld.long 0x00 23. " DPR1_DPR_B_CLKG_STOP ,DPR1_DPR_B_CLKG clock root status" "Not stopped,Stopped" bitfld.long 0x00 21. " DPR1_DPR_B_CLKG_SWEN ,DPR1_DPR_B_CLKG clock enable" "Disabled,Enabled" newline bitfld.long 0x00 20. " DPR1_DPR_B_CLKG_HWEN ,DPR1_DPR_B_CLKG clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 19. " DPR1_DPR_APB_CLKG_STOP ,DPR1_DPR_APB_CLKG clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 17. " DPR1_DPR_APB_CLKG_SWEN ,DPR1_DPR_APB_CLKG clock enable" "Disabled,Enabled" bitfld.long 0x00 16. " DPR1_DPR_APB_CLKG_HWEN ,DPR1_DPR_APB_CLKG clock HW signal treatment" "Ignored,Automatically gated" line.long 0x04 "48,DC_48 Clocks Register" rbitfld.long 0x04 3. " RTRAM1_RTR_CLK_G_STOP ,RTRAM1_RTR_CLK_G clock root status" "Not stopped,Stopped" bitfld.long 0x04 1. " RTRAM1_RTR_CLK_G_SWEN ,RTRAM1_RTR_CLK_G clock enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " RTRAM1_RTR_CLK_G_HWEN ,RTRAM1_RTR_CLK_G clock HW signal treatment" "Ignored,Automatically gated" group.long 0x10034++0x03 line.long 0x00 "52,DC_52 Clocks Register" rbitfld.long 0x00 19. " PRG3_APB_CLK_STOP ,PRG3_APB_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " PRG3_APB_CLK_SWEN ,PRG3_APB_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " PRG3_APB_CLK_HWEN ,PRG3_APB_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " PRG3_RTRAM_CLK_STOP ,PRG3_RTRAM_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " PRG3_RTRAM_CLK_SWEN ,PRG3_RTRAM_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " PRG3_RTRAM_CLK_HWEN ,PRG3_RTRAM_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x10038++0x03 line.long 0x00 "56,DC_56 Clocks Register" rbitfld.long 0x00 19. " PRG4_APB_CLK_STOP ,PRG4_APB_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " PRG4_APB_CLK_SWEN ,PRG4_APB_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " PRG4_APB_CLK_HWEN ,PRG4_APB_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " PRG4_RTRAM_CLK_STOP ,PRG4_RTRAM_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " PRG4_RTRAM_CLK_SWEN ,PRG4_RTRAM_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " PRG4_RTRAM_CLK_HWEN ,PRG4_RTRAM_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x1003C++0x03 line.long 0x00 "60,DC_60 Clocks Register" rbitfld.long 0x00 19. " PRG5_APB_CLK_STOP ,PRG5_APB_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " PRG5_APB_CLK_SWEN ,PRG5_APB_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " PRG5_APB_CLK_HWEN ,PRG5_APB_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " PRG5_RTRAM_CLK_STOP ,PRG5_RTRAM_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " PRG5_RTRAM_CLK_SWEN ,PRG5_RTRAM_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " PRG5_RTRAM_CLK_HWEN ,PRG5_RTRAM_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x10040++0x03 line.long 0x00 "64,DC_64 Clocks Register" rbitfld.long 0x00 19. " PRG6_APB_CLK_STOP ,PRG6_APB_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " PRG6_APB_CLK_SWEN ,PRG6_APB_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " PRG6_APB_CLK_HWEN ,PRG6_APB_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " PRG6_RTRAM_CLK_STOP ,PRG6_RTRAM_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " PRG6_RTRAM_CLK_SWEN ,PRG6_RTRAM_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " PRG6_RTRAM_CLK_HWEN ,PRG6_RTRAM_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x10044++0x03 line.long 0x00 "68,DC_68 Clocks Register" rbitfld.long 0x00 19. " PRG7_APB_CLK_STOP ,PRG7_APB_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " PRG7_APB_CLK_SWEN ,PRG7_APB_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " PRG7_APB_CLK_HWEN ,PRG7_APB_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " PRG7_RTRAM_CLK_STOP ,PRG7_RTRAM_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " PRG7_RTRAM_CLK_SWEN ,PRG7_RTRAM_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " PRG7_RTRAM_CLK_HWEN ,PRG7_RTRAM_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x10048++0x03 line.long 0x00 "72,DC_72 Clocks Register" rbitfld.long 0x00 19. " PRG8_APB_CLK_STOP ,PRG8_APB_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " PRG8_APB_CLK_SWEN ,PRG8_APB_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " PRG8_APB_CLK_HWEN ,PRG8_APB_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " PRG8_RTRAM_CLK_STOP ,PRG8_RTRAM_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " PRG8_RTRAM_CLK_SWEN ,PRG8_RTRAM_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " PRG8_RTRAM_CLK_HWEN ,PRG8_RTRAM_CLK clock HW signal treatment" "Ignored,Automatically gated" width 0x0B tree.end tree "IMAGING" base ad:0x58000000 width 26. group.long 0x500000++0x03 line.long 0x00 "PDMA0,PDMA0 Clock Register" rbitfld.long 0x00 3. " IPG_PROC_CLK_0_STOP ,IPG_PROC_CLK_0 clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " IPG_PROC_CLK_0_SWEN ,IPG_PROC_CLK_0 clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " IPG_PROC_CLK_0_HWEN ,IPG_PROC_CLK_0 clock HW signal treatment" "Ignored,Automatically gated" group.long 0x510000++0x03 line.long 0x00 "PDMA1,PDMA1 Clock Register" rbitfld.long 0x00 3. " IPG_PROC_CLK_1_STOP ,IPG_PROC_CLK_1 clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " IPG_PROC_CLK_1_SWEN ,IPG_PROC_CLK_1 clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " IPG_PROC_CLK_1_HWEN ,IPG_PROC_CLK_1 clock HW signal treatment" "Ignored,Automatically gated" group.long 0x520000++0x03 line.long 0x00 "PDMA2,PDMA2 Clock Register" rbitfld.long 0x00 3. " IPG_PROC_CLK_2_STOP ,IPG_PROC_CLK_2 clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " IPG_PROC_CLK_2_SWEN ,IPG_PROC_CLK_2 clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " IPG_PROC_CLK_2_HWEN ,IPG_PROC_CLK_2 clock HW signal treatment" "Ignored,Automatically gated" group.long 0x530000++0x03 line.long 0x00 "PDMA3,PDMA3 Clock Register" rbitfld.long 0x00 3. " IPG_PROC_CLK_3_STOP ,IPG_PROC_CLK_3 clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " IPG_PROC_CLK_3_SWEN ,IPG_PROC_CLK_3 clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " IPG_PROC_CLK_3_HWEN ,IPG_PROC_CLK_3 clock HW signal treatment" "Ignored,Automatically gated" group.long 0x540000++0x03 line.long 0x00 "PDMA4,PDMA4 Clock Register" rbitfld.long 0x00 3. " IPG_PROC_CLK_4_STOP ,IPG_PROC_CLK_4 clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " IPG_PROC_CLK_4_SWEN ,IPG_PROC_CLK_4 clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " IPG_PROC_CLK_4_HWEN ,IPG_PROC_CLK_4 clock HW signal treatment" "Ignored,Automatically gated" group.long 0x550000++0x03 line.long 0x00 "PDMA5,PDMA5 Clock Register" rbitfld.long 0x00 3. " IPG_PROC_CLK_5_STOP ,IPG_PROC_CLK_5 clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " IPG_PROC_CLK_5_SWEN ,IPG_PROC_CLK_5 clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " IPG_PROC_CLK_5_HWEN ,IPG_PROC_CLK_5 clock HW signal treatment" "Ignored,Automatically gated" group.long 0x560000++0x03 line.long 0x00 "PDMA6,PDMA6 Clock Register" rbitfld.long 0x00 3. " IPG_PROC_CLK_6_STOP ,IPG_PROC_CLK_6 clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " IPG_PROC_CLK_6_SWEN ,IPG_PROC_CLK_6 clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " IPG_PROC_CLK_6_HWEN ,IPG_PROC_CLK_6 clock HW signal treatment" "Ignored,Automatically gated" group.long 0x570000++0x03 line.long 0x00 "PDMA7,PDMA7 Clock Register" rbitfld.long 0x00 3. " IPG_PROC_CLK_7_STOP ,IPG_PROC_CLK_7 clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " IPG_PROC_CLK_7_SWEN ,IPG_PROC_CLK_7 clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " IPG_PROC_CLK_7_HWEN ,IPG_PROC_CLK_7 clock HW signal treatment" "Ignored,Automatically gated" group.long 0x580000++0x03 line.long 0x00 "PIXEL_LINK_SLAVE_CSI1,PIXEL_LINK_SLAVE_CSI1 Clock Register" rbitfld.long 0x00 3. " PIXEL_LINK_SLV_CSI1_INGRESS_CLK_STOP ,PIXEL_LINK_SLV_CSI1_INGRESS_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " PIXEL_LINK_SLV_CSI1_INGRESS_CLK_SWEN ,PIXEL_LINK_SLV_CSI1_INGRESS_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PIXEL_LINK_SLV_CSI1_INGRESS_CLK_HWEN ,PIXEL_LINK_SLV_CSI1_INGRESS_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x590000++0x03 line.long 0x00 "PIXEL_LINK_SLAVE_CSI2,PIXEL_LINK_SLAVE_CSI2 Clock Register" rbitfld.long 0x00 3. " PIXEL_LINK_SLV_CSI2_INGRESS_CLK_STOP ,PIXEL_LINK_SLV_CSI2_INGRESS_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " PIXEL_LINK_SLV_CSI2_INGRESS_CLK_SWEN ,PIXEL_LINK_SLV_CSI2_INGRESS_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PIXEL_LINK_SLV_CSI2_INGRESS_CLK_HWEN ,PIXEL_LINK_SLV_CSI2_INGRESS_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x5A0000++0x03 line.long 0x00 "PIXEL_LINK_SLAVE_HDMI_IN,PIXEL_LINK_SLAVE_HDMI_IN Clock Register" rbitfld.long 0x00 3. " PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK_STOP ,PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK_SWEN ,PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK_HWEN ,PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x5C0000++0x03 line.long 0x00 "PIXEL_LINK_SLAVE_DC0,PIXEL_LINK_SLAVE_DC0 Clock Register" rbitfld.long 0x00 3. " PIXEL_LINK_SLV_DC0_INGRESS_CLK_STOP ,PIXEL_LINK_SLV_DC0_INGRESS_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " PIXEL_LINK_SLV_DC0_INGRESS_CLK_SWEN ,PIXEL_LINK_SLV_DC0_INGRESS_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PIXEL_LINK_SLV_DC0_INGRESS_CLK_HWEN ,PIXEL_LINK_SLV_DC0_INGRESS_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x5D0000++0x03 line.long 0x00 "MJPEG_COMMON_DEC,MJPEG_COMMON_DEC Clocks Register" rbitfld.long 0x00 19. " DECODE_IPS_CLK_STOP ,DECODE_IPS_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " DECODE_IPS_CLK_SWEN ,DECODE_IPS_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " DECODE_IPS_CLK_HWEN ,DECODE_IPS_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " DECODE_JPEG_CLK_STOP ,DECODE_JPEG_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " DECODE_JPEG_CLK_SWEN ,DECODE_JPEG_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " DECODE_JPEG_CLK_HWEN ,DECODE_JPEG_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x5E0000++0x03 line.long 0x00 "PIXEL_LINK_SLAVE_DC1,PIXEL_LINK_SLAVE_DC1 Clock Register" rbitfld.long 0x00 3. " PIXEL_LINK_SLV_DC1_INGRESS_CLK_STOP ,PIXEL_LINK_SLV_DC1_INGRESS_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " PIXEL_LINK_SLV_DC1_INGRESS_CLK_SWEN ,PIXEL_LINK_SLV_DC1_INGRESS_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PIXEL_LINK_SLV_DC1_INGRESS_CLK_HWEN ,PIXEL_LINK_SLV_DC1_INGRESS_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x5F0000++0x03 line.long 0x00 "MJPEG_COMMON_ENC,MJPEG_COMMON_ENC Clocks Register" rbitfld.long 0x00 19. " ENCODE_IPS_CLK_STOP ,ENCODE_IPS_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " ENCODE_IPS_CLK_SWEN ,ENCODE_IPS_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " ENCODE_IPS_CLK_HWEN ,ENCODE_IPS_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " ENCODE_JPEG_CLK_STOP ,ENCODE_JPEG_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " ENCODE_JPEG_CLK_SWEN ,ENCODE_JPEG_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " ENCODE_JPEG_CLK_HWEN ,ENCODE_JPEG_CLK clock HW signal treatment" "Ignored,Automatically gated" width 0x0B tree.end tree "MIPI DSI/LVDS 0" base ad:0x56220000 width 14. group.long 0x3000++0x0F line.long 0x00 "MIPI_LVDS_0,MIPI_LVDS_0 Clock Register" rbitfld.long 0x00 19. " LIS_IPG_CLK_STOP ,LIS_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " LIS_IPG_CLK_SWEN ,LIS_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " LIS_IPG_CLK_HWEN ,LIS_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" line.long 0x04 "MIPI_LVDS_4,MIPI_LVDS_4 Clock Register" rbitfld.long 0x04 19. " DI_MIPI_DSI_LVDS_IPG_CLK_STOP ,DI_MIPI_DSI_LVDS_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x04 17. " DI_MIPI_DSI_LVDS_IPG_CLK_SWEN ,DI_MIPI_DSI_LVDS_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x04 16. " DI_MIPI_DSI_LVDS_IPG_CLK_HWEN ,DI_MIPI_DSI_LVDS_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" line.long 0x08 "MIPI_LVDS_8,MIPI_LVDS_8 Clock Register" rbitfld.long 0x08 19. " GPIO_IPG_CLK_S_STOP ,GPIO_IPG_CLK_S clock root status" "Not stopped,Stopped" bitfld.long 0x08 17. " GPIO_IPG_CLK_S_SWEN ,GPIO_IPG_CLK_S clock enable" "Disabled,Enabled" newline bitfld.long 0x08 16. " GPIO_IPG_CLK_S_HWEN ,GPIO_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" line.long 0x0C "MIPI_LVDS_12,MIPI_LVDS_12 Clocks Register" rbitfld.long 0x0C 27. " IPSYNC_PWM_IPG_SLAVE_CLK_STOP ,IPSYNC_PWM_IPG_SLAVE_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x0C 25. " IPSYNC_PWM_IPG_SLAVE_CLK_SWEN ,IPSYNC_PWM_IPG_SLAVE_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x0C 24. " IPSYNC_PWM_IPG_SLAVE_CLK_HWEN ,IPSYNC_PWM_IPG_SLAVE_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x0C 23. " IPSYNC_PWM_IPG_MASTER_CLK_STOP ,IPSYNC_PWM_IPG_MASTER_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x0C 21. " IPSYNC_PWM_IPG_MASTER_CLK_SWEN ,IPSYNC_PWM_IPG_MASTER_CLK clock enable" "Disabled,Enabled" bitfld.long 0x0C 20. " IPSYNC_PWM_IPG_MASTER_CLK_HWEN ,IPSYNC_PWM_IPG_MASTER_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x0C 19. " PWM_IPG_CLK_STOP ,PWM_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x0C 17. " PWM_IPG_CLK_SWEN ,PWM_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x0C 16. " PWM_IPG_CLK_HWEN ,PWM_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x0C 7. " CCM_CKIL_SYNC_WRAPPER_CLK_IN_STOP ,CCM_CKIL_SYNC_WRAPPER_CLK_IN clock root status" "Not stopped,Stopped" newline bitfld.long 0x0C 5. " CCM_CKIL_SYNC_WRAPPER_CLK_IN_SWEN ,CCM_CKIL_SYNC_WRAPPER_CLK_IN clock enable" "Disabled,Enabled" bitfld.long 0x0C 4. " CCM_CKIL_SYNC_WRAPPER_CLK_IN_HWEN ,CCM_CKIL_SYNC_WRAPPER_CLK_IN clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x0C 3. " PWM_IPG_CLK_HIGHFREQ_STOP ,PWM_IPG_CLK_HIGHFREQ clock root status" "Not stopped,Stopped" bitfld.long 0x0C 1. " PWM_IPG_CLK_HIGHFREQ_SWEN ,PWM_IPG_CLK_HIGHFREQ clock enable" "Disabled,Enabled" newline bitfld.long 0x0C 0. " PWM_IPG_CLK_HIGHFREQ_HWEN ,PWM_IPG_CLK_HIGHFREQ clock HW signal treatment" "Ignored,Automatically gated" group.long 0x3010++0x03 line.long 0x00 "MIPI_LVDS_16,MIPI_LVDS_16 Clocks Register" rbitfld.long 0x00 19. " LPI2C0_IPG_CLK_STOP ,LPI2C0_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " LPI2C0_IPG_CLK_SWEN ,LPI2C0_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " LPI2C0_IPG_CLK_HWEN ,LPI2C0_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " LPI2C0_LPI2C_CLK_STOP ,LPI2C0_LPI2C_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " LPI2C0_LPI2C_CLK_SWEN ,LPI2C0_LPI2C_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " LPI2C0_LPI2C_CLK_HWEN ,LPI2C0_LPI2C_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x3014++0x03 line.long 0x00 "MIPI_LVDS_20,MIPI_LVDS_20 Clocks Register" rbitfld.long 0x00 19. " LPI2C1_IPG_CLK_STOP ,LPI2C1_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " LPI2C1_IPG_CLK_SWEN ,LPI2C1_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " LPI2C1_IPG_CLK_HWEN ,LPI2C1_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " LPI2C1_LPI2C_CLK_STOP ,LPI2C1_LPI2C_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " LPI2C1_LPI2C_CLK_SWEN ,LPI2C1_LPI2C_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " LPI2C1_LPI2C_CLK_HWEN ,LPI2C1_LPI2C_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x3018++0x03 line.long 0x00 "MIPI_LVDS_24,MIPI_LVDS_24 Clocks Register" rbitfld.long 0x00 19. " MIPI_DSI_CTRL_PCLK_STOP ,MIPI_DSI_CTRL_PCLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " MIPI_DSI_CTRL_PCLK_SWEN ,MIPI_DSI_CTRL_PCLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " MIPI_DSI_CTRL_PCLK_HWEN ,MIPI_DSI_CTRL_PCLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 11. " MIPI_CLKREF_STOP ,MIPI_CLKREF clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 9. " MIPI_CLKREF_SWEN ,MIPI_CLKREF clock enable" "Disabled,Enabled" bitfld.long 0x00 8. " MIPI_CLKREF_HWEN ,MIPI_CLKREF clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 7. " MIPI_DSI_CTRL_RXCLKESC_STOP ,MIPI_DSI_CTRL_RXCLKESC clock root status" "Not stopped,Stopped" bitfld.long 0x00 5. " MIPI_DSI_CTRL_RXCLKESC_SWEN ,MIPI_DSI_CTRL_RXCLKESC clock enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " MIPI_DSI_CTRL_RXCLKESC_HWEN ,MIPI_DSI_CTRL_RXCLKESC clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " MIPI_DSI_CTRL_TXCLKESC_STOP ,MIPI_DSI_CTRL_TXCLKESC clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " MIPI_DSI_CTRL_TXCLKESC_SWEN ,MIPI_DSI_CTRL_TXCLKESC clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " MIPI_DSI_CTRL_TXCLKESC_HWEN ,MIPI_DSI_CTRL_TXCLKESC clock HW signal treatment" "Ignored,Automatically gated" width 0x0B tree.end tree "MIPI DSI/LVDS 1" base ad:0x56240000 width 14. group.long 0x3000++0x0F line.long 0x00 "MIPI_LVDS_0,MIPI_LVDS_0 Clock Register" rbitfld.long 0x00 19. " LIS_IPG_CLK_STOP ,LIS_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " LIS_IPG_CLK_SWEN ,LIS_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " LIS_IPG_CLK_HWEN ,LIS_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" line.long 0x04 "MIPI_LVDS_4,MIPI_LVDS_4 Clock Register" rbitfld.long 0x04 19. " DI_MIPI_DSI_LVDS_IPG_CLK_STOP ,DI_MIPI_DSI_LVDS_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x04 17. " DI_MIPI_DSI_LVDS_IPG_CLK_SWEN ,DI_MIPI_DSI_LVDS_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x04 16. " DI_MIPI_DSI_LVDS_IPG_CLK_HWEN ,DI_MIPI_DSI_LVDS_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" line.long 0x08 "MIPI_LVDS_8,MIPI_LVDS_8 Clock Register" rbitfld.long 0x08 19. " GPIO_IPG_CLK_S_STOP ,GPIO_IPG_CLK_S clock root status" "Not stopped,Stopped" bitfld.long 0x08 17. " GPIO_IPG_CLK_S_SWEN ,GPIO_IPG_CLK_S clock enable" "Disabled,Enabled" newline bitfld.long 0x08 16. " GPIO_IPG_CLK_S_HWEN ,GPIO_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" line.long 0x0C "MIPI_LVDS_12,MIPI_LVDS_12 Clocks Register" rbitfld.long 0x0C 27. " IPSYNC_PWM_IPG_SLAVE_CLK_STOP ,IPSYNC_PWM_IPG_SLAVE_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x0C 25. " IPSYNC_PWM_IPG_SLAVE_CLK_SWEN ,IPSYNC_PWM_IPG_SLAVE_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x0C 24. " IPSYNC_PWM_IPG_SLAVE_CLK_HWEN ,IPSYNC_PWM_IPG_SLAVE_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x0C 23. " IPSYNC_PWM_IPG_MASTER_CLK_STOP ,IPSYNC_PWM_IPG_MASTER_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x0C 21. " IPSYNC_PWM_IPG_MASTER_CLK_SWEN ,IPSYNC_PWM_IPG_MASTER_CLK clock enable" "Disabled,Enabled" bitfld.long 0x0C 20. " IPSYNC_PWM_IPG_MASTER_CLK_HWEN ,IPSYNC_PWM_IPG_MASTER_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x0C 19. " PWM_IPG_CLK_STOP ,PWM_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x0C 17. " PWM_IPG_CLK_SWEN ,PWM_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x0C 16. " PWM_IPG_CLK_HWEN ,PWM_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x0C 7. " CCM_CKIL_SYNC_WRAPPER_CLK_IN_STOP ,CCM_CKIL_SYNC_WRAPPER_CLK_IN clock root status" "Not stopped,Stopped" newline bitfld.long 0x0C 5. " CCM_CKIL_SYNC_WRAPPER_CLK_IN_SWEN ,CCM_CKIL_SYNC_WRAPPER_CLK_IN clock enable" "Disabled,Enabled" bitfld.long 0x0C 4. " CCM_CKIL_SYNC_WRAPPER_CLK_IN_HWEN ,CCM_CKIL_SYNC_WRAPPER_CLK_IN clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x0C 3. " PWM_IPG_CLK_HIGHFREQ_STOP ,PWM_IPG_CLK_HIGHFREQ clock root status" "Not stopped,Stopped" bitfld.long 0x0C 1. " PWM_IPG_CLK_HIGHFREQ_SWEN ,PWM_IPG_CLK_HIGHFREQ clock enable" "Disabled,Enabled" newline bitfld.long 0x0C 0. " PWM_IPG_CLK_HIGHFREQ_HWEN ,PWM_IPG_CLK_HIGHFREQ clock HW signal treatment" "Ignored,Automatically gated" group.long 0x3010++0x03 line.long 0x00 "MIPI_LVDS_16,MIPI_LVDS_16 Clocks Register" rbitfld.long 0x00 19. " LPI2C0_IPG_CLK_STOP ,LPI2C0_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " LPI2C0_IPG_CLK_SWEN ,LPI2C0_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " LPI2C0_IPG_CLK_HWEN ,LPI2C0_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " LPI2C0_LPI2C_CLK_STOP ,LPI2C0_LPI2C_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " LPI2C0_LPI2C_CLK_SWEN ,LPI2C0_LPI2C_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " LPI2C0_LPI2C_CLK_HWEN ,LPI2C0_LPI2C_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x3014++0x03 line.long 0x00 "MIPI_LVDS_20,MIPI_LVDS_20 Clocks Register" rbitfld.long 0x00 19. " LPI2C1_IPG_CLK_STOP ,LPI2C1_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " LPI2C1_IPG_CLK_SWEN ,LPI2C1_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " LPI2C1_IPG_CLK_HWEN ,LPI2C1_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " LPI2C1_LPI2C_CLK_STOP ,LPI2C1_LPI2C_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " LPI2C1_LPI2C_CLK_SWEN ,LPI2C1_LPI2C_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " LPI2C1_LPI2C_CLK_HWEN ,LPI2C1_LPI2C_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x3018++0x03 line.long 0x00 "MIPI_LVDS_24,MIPI_LVDS_24 Clocks Register" rbitfld.long 0x00 19. " MIPI_DSI_CTRL_PCLK_STOP ,MIPI_DSI_CTRL_PCLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " MIPI_DSI_CTRL_PCLK_SWEN ,MIPI_DSI_CTRL_PCLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " MIPI_DSI_CTRL_PCLK_HWEN ,MIPI_DSI_CTRL_PCLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 11. " MIPI_CLKREF_STOP ,MIPI_CLKREF clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 9. " MIPI_CLKREF_SWEN ,MIPI_CLKREF clock enable" "Disabled,Enabled" bitfld.long 0x00 8. " MIPI_CLKREF_HWEN ,MIPI_CLKREF clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 7. " MIPI_DSI_CTRL_RXCLKESC_STOP ,MIPI_DSI_CTRL_RXCLKESC clock root status" "Not stopped,Stopped" bitfld.long 0x00 5. " MIPI_DSI_CTRL_RXCLKESC_SWEN ,MIPI_DSI_CTRL_RXCLKESC clock enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " MIPI_DSI_CTRL_RXCLKESC_HWEN ,MIPI_DSI_CTRL_RXCLKESC clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " MIPI_DSI_CTRL_TXCLKESC_STOP ,MIPI_DSI_CTRL_TXCLKESC clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " MIPI_DSI_CTRL_TXCLKESC_SWEN ,MIPI_DSI_CTRL_TXCLKESC clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " MIPI_DSI_CTRL_TXCLKESC_HWEN ,MIPI_DSI_CTRL_TXCLKESC clock HW signal treatment" "Ignored,Automatically gated" width 0x0B tree.end tree "MIPI CSI" base ad:0x58220000 width 23. group.long 0x3000++0x0B line.long 0x00 "LPCG_MIPI_CSI_0_REGS,MIPI_CSI_0 Clock Register" rbitfld.long 0x00 19. " LIS_IPG_CLK_STOP ,LIS_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " LIS_IPG_CLK_SWEN ,LIS_IPG_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 16. " LIS_IPG_CLK_HWEN ,LIS_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" line.long 0x04 "LPCG_MIPI_CSI_4_REGS,MIPI_CSI_4 Clock Register" rbitfld.long 0x04 19. " MIPI_CSI_REGS_APB_CLK_STOP ,MIPI_CSI_REGS_APB_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x04 17. " MIPI_CSI_REGS_APB_CLK_SWEN ,MIPI_CSI_REGS_APB_CLK clock enable" "Disabled,Enabled" bitfld.long 0x04 16. " MIPI_CSI_REGS_APB_CLK_HWEN ,MIPI_CSI_REGS_APB_CLK clock HW signal treatment" "Ignored,Automatically gated" line.long 0x08 "LPCG_MIPI_CSI_8_REGS,MIPI_CSI_8 Clock Register" rbitfld.long 0x08 19. " GPIO_IPG_CLK_S_STOP ,GPIO_IPG_CLK_S clock root status" "Not stopped,Stopped" bitfld.long 0x08 17. " GPIO_IPG_CLK_S_SWEN ,GPIO_IPG_CLK_S clock enable" "Disabled,Enabled" bitfld.long 0x08 16. " GPIO_IPG_CLK_S_HWEN ,GPIO_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" group.long 0x3010++0x0F line.long 0x00 "LPCG_MIPI_CSI_16_REGS,MIPI_CSI_16 Clocks Register" rbitfld.long 0x00 19. " PWM_IPG_CLK_STOP ,PWM_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " PWM_IPG_CLK_SWEN ,PWM_IPG_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 16. " PWM_IPG_CLK_HWEN ,PWM_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 3. " PWM_IPG_CLK_HIGHFREQ_STOP ,PWM_IPG_CLK_HIGHFREQ clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " PWM_IPG_CLK_HIGHFREQ_SWEN ,PWM_IPG_CLK_HIGHFREQ clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " PWM_IPG_CLK_HIGHFREQ_HWEN ,PWM_IPG_CLK_HIGHFREQ clock HW signal treatment" "Ignored,Automatically gated" line.long 0x04 "LPCG_MIPI_CSI_20_REGS,MIPI_CSI_20 Clock Register" rbitfld.long 0x04 19. " LPI2C_IPG_CLK_STOP ,LPI2C_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x04 17. " LPI2C_IPG_CLK_SWEN ,LPI2C_IPG_CLK clock enable" "Disabled,Enabled" bitfld.long 0x04 16. " LPI2C_IPG_CLK_HWEN ,LPI2C_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x04 3. " LPI2C_LPI2C_CLK_STOP ,LPI2C_LPI2C_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x04 1. " LPI2C_LPI2C_CLK_SWEN ,LPI2C_LPI2C_CLK clock enable" "Disabled,Enabled" bitfld.long 0x04 0. " LPI2C_LPI2C_CLK_HWEN ,LPI2C_LPI2C_CLK clock HW signal treatment" "Ignored,Automatically gated" line.long 0x08 "LPCG_MIPI_CSI_24_REGS,MIPI_CSI_24 Clock Register" rbitfld.long 0x08 3. " CSI2_RX_TOP_CLK_STOP ,CSI2_RX_TOP_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x08 1. " CSI2_RX_TOP_CLK_SWEN ,CSI2_RX_TOP_CLK clock enable" "Disabled,Enabled" bitfld.long 0x08 0. " CSI2_RX_TOP_CLK_HWEN ,CSI2_RX_TOP_CLK clock HW signal treatment" "Ignored,Automatically gated" line.long 0x0C "LPCG_MIPI_CSI_28_REGS,MIPI_CSI_28 Clock Register" rbitfld.long 0x0C 3. " CSI2_RX_TOP_CLK_ESC_STOP ,CSI2_RX_TOP_CLK_ESC clock root status" "Not stopped,Stopped" bitfld.long 0x0C 1. " CSI2_RX_TOP_CLK_ESC_SWEN ,CSI2_RX_TOP_CLK_ESC clock enable" "Disabled,Enabled" bitfld.long 0x0C 0. " CSI2_RX_TOP_CLK_ESC_HWEN ,CSI2_RX_TOP_CLK_ESC clock HW signal treatment" "Ignored,Automatically gated" width 0x0B tree.end tree "CI PI (Parallel Capture)" base ad:0x58260000 width 20. group.long 0x3000++0x13 line.long 0x00 "LPCG_CI_PI_0_REGS,CI_PI_0 Clock Register" rbitfld.long 0x00 19. " LIS_IPG_CLK_STOP ,LIS_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " LIS_IPG_CLK_SWEN ,LIS_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " LIS_IPG_CLK_HWEN ,LIS_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" line.long 0x04 "LPCG_CI_PI_4_REGS,CI_PI_4 Clocks Register" rbitfld.long 0x04 27. " IPSYNC_CI_PI_REGS_IPG_SLAVE_CLK_STOP ,IPSYNC_CI_PI_REGS_IPG_SLAVE_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x04 25. " IPSYNC_CI_PI_REGS_IPG_SLAVE_CLK_SWEN ,IPSYNC_CI_PI_REGS_IPG_SLAVE_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x04 24. " IPSYNC_CI_PI_REGS_IPG_SLAVE_CLK_HWEN ,IPSYNC_CI_PI_REGS_IPG_SLAVE_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x04 23. " IPSYNC_CI_PI_REGS_IPG_MASTER_CLK_STOP ,IPSYNC_CI_PI_REGS_IPG_MASTER_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x04 21. " IPSYNC_CI_PI_REGS_IPG_MASTER_CLK_SWEN ,IPSYNC_CI_PI_REGS_IPG_MASTER_CLK clock enable" "Disabled,Enabled" bitfld.long 0x04 20. " IPSYNC_CI_PI_REGS_IPG_MASTER_CLK_HWEN ,IPSYNC_CI_PI_REGS_IPG_MASTER_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x04 19. " CI_PI_REGS_IPG_CLK_STOP ,CI_PI_REGS_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x04 17. " CI_PI_REGS_IPG_CLK_SWEN ,CI_PI_REGS_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x04 16. " CI_PI_REGS_IPG_CLK_HWEN ,CI_PI_REGS_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" line.long 0x08 "LPCG_CI_PI_8_REGS,CI_PI_8 Clock Register" rbitfld.long 0x08 19. " GPIO_IPG_CLK_S_STOP ,GPIO_IPG_CLK_S clock root status" "Not stopped,Stopped" bitfld.long 0x08 17. " GPIO_IPG_CLK_S_SWEN ,GPIO_IPG_CLK_S clock enable" "Disabled,Enabled" newline bitfld.long 0x08 16. " GPIO_IPG_CLK_S_HWEN ,GPIO_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" line.long 0x0C "LPCG_CI_PI_12_REGS,CI_PI_12 Clocks Register" rbitfld.long 0x0C 27. " IPSYNC_PWM_IPG_SLAVE_CLK_STOP ,IPSYNC_PWM_IPG_SLAVE_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x0C 25. " IPSYNC_PWM_IPG_SLAVE_CLK_SWEN ,IPSYNC_PWM_IPG_SLAVE_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x0C 24. " IPSYNC_PWM_IPG_SLAVE_CLK_HWEN ,IPSYNC_PWM_IPG_SLAVE_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x0C 23. " IPSYNC_PWM_IPG_MASTER_CLK_STOP ,IPSYNC_PWM_IPG_MASTER_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x0C 21. " IPSYNC_PWM_IPG_MASTER_CLK_SWEN ,IPSYNC_PWM_IPG_MASTER_CLK clock enable" "Disabled,Enabled" bitfld.long 0x0C 20. " IPSYNC_PWM_IPG_MASTER_CLK_HWEN ,IPSYNC_PWM_IPG_MASTER_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x0C 19. " PWM_IPG_CLK_STOP ,PWM_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x0C 17. " PWM_IPG_CLK_SWEN ,PWM_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x0C 16. " PWM_IPG_CLK_HWEN ,PWM_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x0C 7. " CCM_CKIL_SYNC_WRAPPER_CLK_IN_STOP ,CCM_CKIL_SYNC_WRAPPER_CLK_IN clock root status" "Not stopped,Stopped" newline bitfld.long 0x0C 5. " CCM_CKIL_SYNC_WRAPPER_CLK_IN_SWEN ,CCM_CKIL_SYNC_WRAPPER_CLK_IN clock enable" "Disabled,Enabled" bitfld.long 0x0C 4. " CCM_CKIL_SYNC_WRAPPER_CLK_IN_HWEN ,CCM_CKIL_SYNC_WRAPPER_CLK_IN clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x0C 3. " PWM_IPG_CLK_HIGHFREQ_STOP ,PWM_IPG_CLK_HIGHFREQ clock root status" "Not stopped,Stopped" bitfld.long 0x0C 1. " PWM_IPG_CLK_HIGHFREQ_SWEN ,PWM_IPG_CLK_HIGHFREQ clock enable" "Disabled,Enabled" newline bitfld.long 0x0C 0. " PWM_IPG_CLK_HIGHFREQ_HWEN ,PWM_IPG_CLK_HIGHFREQ clock HW signal treatment" "Ignored,Automatically gated" line.long 0x10 "LPCG_CI_PI_16_REGS,CI_PI_16 Clock Register" rbitfld.long 0x10 19. " LPI2C0_IPG_CLK_STOP ,LPI2C0_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x10 17. " LPI2C0_IPG_CLK_SWEN ,LPI2C0_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x10 16. " LPI2C0_IPG_CLK_HWEN ,LPI2C0_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x10 3. " LPI2C0_LPI2C_CLK_STOP ,LPI2C0_LPI2C_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x10 1. " LPI2C0_LPI2C_CLK_SWEN ,LPI2C0_LPI2C_CLK clock enable" "Disabled,Enabled" bitfld.long 0x10 0. " LPI2C0_LPI2C_CLK_HWEN ,LPI2C0_LPI2C_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x3018++0x07 line.long 0x00 "LPCG_CI_PI_24_REGS,CI_PI_24 Clock Register" rbitfld.long 0x00 3. " CSI_INTERFACE_CLK_STOP ,CSI_INTERFACE_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " CSI_INTERFACE_CLK_SWEN ,CSI_INTERFACE_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " CSI_INTERFACE_CLK_HWEN ,CSI_INTERFACE_CLK clock HW signal treatment" "Ignored,Automatically gated" line.long 0x04 "LPCG_CI_PI_28_REGS,CI_PI_28 Clock Register" rbitfld.long 0x04 3. " MCLK_STOP ,MCLK clock root status" "Not stopped,Stopped" bitfld.long 0x04 1. " MCLK_SWEN ,MCLK clock enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " MCLK_HWEN ,MCLK clock HW signal treatment" "Ignored,Automatically gated" width 0x0B tree.end tree.end endif tree "DRC (DRAM)" base ad:0x5C090000 width 17. group.long 0x00++0x03 line.long 0x00 "LPCG_DRC_6_REGS,DRC_6 Clock Register" rbitfld.long 0x00 3. " ATPG_PHY_PUB_CLK_CLK_MUX_D0_STOP ,Clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " ATPG_PHY_PUB_CLK_CLK_MUX_D0_SWEN ,Clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " ATPG_PHY_PUB_CLK_CLK_MUX_D0_HWEN ,Clock HW signal treatment" "Ignored,Automatically gated" group.long 0x10000++0x03 line.long 0x00 "LPCG_DRC_5_REGS,DRC_5 Clock Register" rbitfld.long 0x00 3. " DDR_PHY_PHY_CTL_REF_LPDDR_INIT_CLK_CG_CP_STOP ,Clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " DDR_PHY_PHY_CTL_REF_LPDDR_INIT_CLK_CG_CP_SWEN ,Clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DDR_PHY_PHY_CTL_REF_LPDDR_INIT_CLK_CG_CP_HWEN ,Clock HW signal treatment" "Ignored,Automatically gated" group.long 0x20000++0x03 line.long 0x00 "LPCG_DRC_4_0,DRC_4_0 Clock Register" rbitfld.long 0x00 3. " DDR_CTL_SBR_CLK_STOP ,Clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " DDR_CTL_SBR_CLK_SWEN ,Clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DDR_CTL_SBR_CLK_HWEN ,Clock HW signal treatment" "Ignored,Automatically gated" group.long 0x30000++0x03 line.long 0x00 "LPCG_DRC_0,DRC_0 Clock Register" rbitfld.long 0x00 3. " SSI_PORT0_CLK_STOP ,Clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " SSI_PORT0_CLK_SWEN ,Clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " SSI_PORT0_CLK_HWEN ,Clock HW signal treatment" "Ignored,Automatically gated" group.long 0x40000++0x03 line.long 0x00 "LPCG_DRC_1,DRC_1 Clock Register" rbitfld.long 0x00 3. " DDR_CTL_CORE_DDRC_CORE_CLK_STOP ,Clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " DDR_CTL_CORE_DDRC_CORE_CLK_SWEN ,Clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DDR_CTL_CORE_DDRC_CORE_CLK_HWEN ,Clock HW signal treatment" "Ignored,Automatically gated" group.long 0x60000++0x07 line.long 0x00 "LPCG_DRC_3_0,DRC_3_0 Clock Register" rbitfld.long 0x00 3. " DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0_STOP ,Clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0_SWEN ,Clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0_HWEN ,Clock HW signal treatment" "Ignored,Automatically gated" line.long 0x04 "LPCG_DRC_3_4,DRC_3_4 Clock Register" rbitfld.long 0x04 3. " DDR_PHY_PCLK_LPDDR_INIT_CLK_MUX_D0_STOP ,Clock root status" "Not stopped,Stopped" bitfld.long 0x04 1. " DDR_PHY_PCLK_LPDDR_INIT_CLK_MUX_D0_SWEN ,Clock enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " DDR_PHY_PCLK_LPDDR_INIT_CLK_MUX_D0_HWEN ,Clock HW signal treatment" "Ignored,Automatically gated" width 0x0B tree.end tree "HSIO (High Speed I/O)" base ad:0x5F000000 width 23. group.long 0x60000++0x03 line.long 0x00 "LPCG_PCIEX1_REGS,PCIEX1 Clocks Register" rbitfld.long 0x00 27. " PCIE_CLK_RST_DBI_AXI_CLK_STOP ,PCIE_CLK_RST_DBI_AXI_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 25. " PCIE_CLK_RST_DBI_AXI_CLK_SWEN ,PCIE_CLK_RST_DBI_AXI_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " PCIE_CLK_RST_DBI_AXI_CLK_HWEN ,PCIE_CLK_RST_DBI_AXI_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 23. " PCIE_CLK_RST_SLV_AXI_CLK_STOP ,PCIE_CLK_RST_SLV_AXI_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 21. " PCIE_CLK_RST_SLV_AXI_CLK_SWEN ,PCIE_CLK_RST_SLV_AXI_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 20. " PCIE_CLK_RST_SLV_AXI_CLK_HWEN ,PCIE_CLK_RST_SLV_AXI_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 19. " PCIE_CLK_RST_MSTR_AXI_CLK_STOP ,PCIE_CLK_RST_MSTR_AXI_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " PCIE_CLK_RST_MSTR_AXI_CLK_SWEN ,PCIE_CLK_RST_MSTR_AXI_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " PCIE_CLK_RST_MSTR_AXI_CLK_HWEN ,PCIE_CLK_RST_MSTR_AXI_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x70000++0x03 line.long 0x00 "LPCG_SSI_REGS,SSI Clock Register" rbitfld.long 0x00 3. " SSI_PCLK_STOP ,SSI_PCLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " SSI_PCLK_SWEN ,SSI_PCLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " SSI_PCLK_HWEN ,SSI_PCLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x90000++0x03 line.long 0x00 "LPCG_PHYX1_REGS,PHYX1 Clock Register" rbitfld.long 0x00 19. " PCS_PHY_X1_APB_PCLK_0_STOP ,PCS_PHY_X1_APB_PCLK_0 clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " PCS_PHY_X1_APB_PCLK_0_SWEN ,PCS_PHY_X1_APB_PCLK_0 clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " PCS_PHY_X1_APB_PCLK_0_HWEN ,PCS_PHY_X1_APB_PCLK_0 clock HW signal treatment" "Ignored,Automatically gated" group.long 0xB0000++0x03 line.long 0x00 "LPCG_PHYX1_CRR1_REGS,PHYX1_CRR1 Clock Register" rbitfld.long 0x00 19. " HSIO_PHYX1_REGS_IPG_CLK_STOP ,HSIO_PHYX1_REGS_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " HSIO_PHYX1_REGS_IPG_CLK_SWEN ,HSIO_PHYX1_REGS_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HSIO_PHYX1_REGS_IPG_CLK_HWEN ,HSIO_PHYX1_REGS_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0xD0000++0x03 line.long 0x00 "LPCG_PCIEX1_CRR3_REGS,PCIEX1_CRR3 Clock Register" rbitfld.long 0x00 19. " HSIO_PCIEX1_REGS_IPG_CLK_STOP ,HSIO_PCIEX1_REGS_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " HSIO_PCIEX1_REGS_IPG_CLK_SWEN ,HSIO_PCIEX1_REGS_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HSIO_PCIEX1_REGS_IPG_CLK_HWEN ,HSIO_PCIEX1_REGS_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0xF0000++0x03 line.long 0x00 "LPCG_MISC_CRR5_REGS,MISC_CCR5 Clock Register" rbitfld.long 0x00 19. " HSIO_MISC_REGS_IPG_CLK_STOP ,HSIO_MISC_REGS_IPG_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " HSIO_MISC_REGS_IPG_CLK_SWEN ,HSIO_MISC_REGS_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " HSIO_MISC_REGS_IPG_CLK_HWEN ,HSIO_MISC_REGS_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x100000++0x03 line.long 0x00 "LPCG_GPIO_CLK_REGS,GPIO_CLK Clock Register" rbitfld.long 0x00 19. " GPIO_IPG_CLK_S_STOP ,GPIO_IPG_CLK_S clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " GPIO_IPG_CLK_S_SWEN ,GPIO_IPG_CLK_S clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " GPIO_IPG_CLK_S_HWEN ,GPIO_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" width 0x0B tree.end tree "LSIO (Low Speed I/O)" base ad:0x5D000000 width 26. group.long 0x400000++0x03 line.long 0x00 "LPCG_IPS_SYNC_PWM0_REGS,IPS_SYNC_PWM0 Clocks Register" rbitfld.long 0x00 27. " IPS_SYNC_PWM0_IPG_MASTER_CLK_STOP ,IPS_SYNC_PWM0_IPG_MASTER_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 25. " IPS_SYNC_PWM0_IPG_MASTER_CLK_SWEN ,IPS_SYNC_PWM0_IPG_MASTER_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " IPS_SYNC_PWM0_IPG_MASTER_CLK_HWEN ,IPS_SYNC_PWM0_IPG_MASTER_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 23. " IPS_SYNC_PWM0_IPG_SLAVE_CLK_STOP ,IPS_SYNC_PWM0_IPG_SLAVE_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 21. " IPS_SYNC_PWM0_IPG_SLAVE_CLK_SWEN ,IPS_SYNC_PWM0_IPG_SLAVE_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 20. " IPS_SYNC_PWM0_IPG_SLAVE_CLK_HWEN ,IPS_SYNC_PWM0_IPG_SLAVE_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 19. " PWM0_IPG_CLK_S_STOP ,PWM0_IPG_CLK_S clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " PWM0_IPG_CLK_S_SWEN ,PWM0_IPG_CLK_S clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " PWM0_IPG_CLK_S_HWEN ,PWM0_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 11. " OCM_CKIL_SYNC_WRAPPER5_CLK_IN_STOP ,OCM_CKIL_SYNC_WRAPPER5_CLK_IN clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 9. " OCM_CKIL_SYNC_WRAPPER5_CLK_IN_SWEN ,OCM_CKIL_SYNC_WRAPPER5_CLK_IN clock enable" "Disabled,Enabled" bitfld.long 0x00 8. " OCM_CKIL_SYNC_WRAPPER5_CLK_IN_HWEN ,OCM_CKIL_SYNC_WRAPPER5_CLK_IN clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 7. " PWM0_IPG_CLK_HIGHFREQ_STOP ,PWM0_IPG_CLK_HIGHFREQ clock root status" "Not stopped,Stopped" bitfld.long 0x00 5. " PWM0_IPG_CLK_HIGHFREQ_SWEN ,PWM0_IPG_CLK_HIGHFREQ clock enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PWM0_IPG_CLK_HIGHFREQ_HWEN ,PWM0_IPG_CLK_HIGHFREQ clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " PWM_IPG_CLK_STOP ,PWM_IPG_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " PWM_IPG_CLK_SWEN ,PWM_IPG_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " PWM_IPG_CLK_HWEN ,PWM_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x410000++0x03 line.long 0x00 "LPCG_IPS_SYNC_PWM1_REGS,IPS_SYNC_PWM1 Clocks Register" rbitfld.long 0x00 27. " IPS_SYNC_PWM1_IPG_MASTER_CLK_STOP ,IPS_SYNC_PWM1_IPG_MASTER_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 25. " IPS_SYNC_PWM1_IPG_MASTER_CLK_SWEN ,IPS_SYNC_PWM1_IPG_MASTER_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " IPS_SYNC_PWM1_IPG_MASTER_CLK_HWEN ,IPS_SYNC_PWM1_IPG_MASTER_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 23. " IPS_SYNC_PWM1_IPG_SLAVE_CLK_STOP ,IPS_SYNC_PWM1_IPG_SLAVE_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 21. " IPS_SYNC_PWM1_IPG_SLAVE_CLK_SWEN ,IPS_SYNC_PWM1_IPG_SLAVE_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 20. " IPS_SYNC_PWM1_IPG_SLAVE_CLK_HWEN ,IPS_SYNC_PWM1_IPG_SLAVE_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 19. " PWM1_IPG_CLK_S_STOP ,PWM1_IPG_CLK_S clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " PWM1_IPG_CLK_S_SWEN ,PWM1_IPG_CLK_S clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " PWM1_IPG_CLK_S_HWEN ,PWM1_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 11. " OCM_CKIL_SYNC_WRAPPER6_CLK_IN_STOP ,OCM_CKIL_SYNC_WRAPPER6_CLK_IN clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 9. " OCM_CKIL_SYNC_WRAPPER6_CLK_IN_SWEN ,OCM_CKIL_SYNC_WRAPPER6_CLK_IN clock enable" "Disabled,Enabled" bitfld.long 0x00 8. " OCM_CKIL_SYNC_WRAPPER6_CLK_IN_HWEN ,OCM_CKIL_SYNC_WRAPPER6_CLK_IN clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 7. " PWM1_IPG_CLK_HIGHFREQ_STOP ,PWM1_IPG_CLK_HIGHFREQ clock root status" "Not stopped,Stopped" bitfld.long 0x00 5. " PWM1_IPG_CLK_HIGHFREQ_SWEN ,PWM1_IPG_CLK_HIGHFREQ clock enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PWM1_IPG_CLK_HIGHFREQ_HWEN ,PWM1_IPG_CLK_HIGHFREQ clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " PWM_IPG_CLK_STOP ,PWM_IPG_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " PWM_IPG_CLK_SWEN ,PWM_IPG_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " PWM_IPG_CLK_HWEN ,PWM_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x420000++0x03 line.long 0x00 "LPCG_IPS_SYNC_PWM2_REGS,IPS_SYNC_PWM2 Clocks Register" rbitfld.long 0x00 27. " IPS_SYNC_PWM2_IPG_MASTER_CLK_STOP ,IPS_SYNC_PWM2_IPG_MASTER_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 25. " IPS_SYNC_PWM2_IPG_MASTER_CLK_SWEN ,IPS_SYNC_PWM2_IPG_MASTER_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " IPS_SYNC_PWM2_IPG_MASTER_CLK_HWEN ,IPS_SYNC_PWM2_IPG_MASTER_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 23. " IPS_SYNC_PWM2_IPG_SLAVE_CLK_STOP ,IPS_SYNC_PWM2_IPG_SLAVE_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 21. " IPS_SYNC_PWM2_IPG_SLAVE_CLK_SWEN ,IPS_SYNC_PWM2_IPG_SLAVE_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 20. " IPS_SYNC_PWM2_IPG_SLAVE_CLK_HWEN ,IPS_SYNC_PWM2_IPG_SLAVE_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 19. " PWM2_IPG_CLK_S_STOP ,PWM2_IPG_CLK_S clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " PWM2_IPG_CLK_S_SWEN ,PWM2_IPG_CLK_S clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " PWM2_IPG_CLK_S_HWEN ,PWM2_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 11. " OCM_CKIL_SYNC_WRAPPER7_CLK_IN_STOP ,OCM_CKIL_SYNC_WRAPPER7_CLK_IN clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 9. " OCM_CKIL_SYNC_WRAPPER7_CLK_IN_SWEN ,OCM_CKIL_SYNC_WRAPPER7_CLK_IN clock enable" "Disabled,Enabled" bitfld.long 0x00 8. " OCM_CKIL_SYNC_WRAPPER7_CLK_IN_HWEN ,OCM_CKIL_SYNC_WRAPPER7_CLK_IN clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 7. " PWM2_IPG_CLK_HIGHFREQ_STOP ,PWM2_IPG_CLK_HIGHFREQ clock root status" "Not stopped,Stopped" bitfld.long 0x00 5. " PWM2_IPG_CLK_HIGHFREQ_SWEN ,PWM2_IPG_CLK_HIGHFREQ clock enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PWM2_IPG_CLK_HIGHFREQ_HWEN ,PWM2_IPG_CLK_HIGHFREQ clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " PWM_IPG_CLK_STOP ,PWM_IPG_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " PWM_IPG_CLK_SWEN ,PWM_IPG_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " PWM_IPG_CLK_HWEN ,PWM_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x430000++0x03 line.long 0x00 "LPCG_IPS_SYNC_PWM3_REGS,IPS_SYNC_PWM3 Clocks Register" rbitfld.long 0x00 27. " IPS_SYNC_PWM3_IPG_MASTER_CLK_STOP ,IPS_SYNC_PWM3_IPG_MASTER_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 25. " IPS_SYNC_PWM3_IPG_MASTER_CLK_SWEN ,IPS_SYNC_PWM3_IPG_MASTER_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " IPS_SYNC_PWM3_IPG_MASTER_CLK_HWEN ,IPS_SYNC_PWM3_IPG_MASTER_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 23. " IPS_SYNC_PWM3_IPG_SLAVE_CLK_STOP ,IPS_SYNC_PWM3_IPG_SLAVE_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 21. " IPS_SYNC_PWM3_IPG_SLAVE_CLK_SWEN ,IPS_SYNC_PWM3_IPG_SLAVE_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 20. " IPS_SYNC_PWM3_IPG_SLAVE_CLK_HWEN ,IPS_SYNC_PWM3_IPG_SLAVE_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 19. " PWM3_IPG_CLK_S_STOP ,PWM3_IPG_CLK_S clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " PWM3_IPG_CLK_S_SWEN ,PWM3_IPG_CLK_S clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " PWM3_IPG_CLK_S_HWEN ,PWM3_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 11. " OCM_CKIL_SYNC_WRAPPER8_CLK_IN_STOP ,OCM_CKIL_SYNC_WRAPPER8_CLK_IN clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 9. " OCM_CKIL_SYNC_WRAPPER8_CLK_IN_SWEN ,OCM_CKIL_SYNC_WRAPPER8_CLK_IN clock enable" "Disabled,Enabled" bitfld.long 0x00 8. " OCM_CKIL_SYNC_WRAPPER8_CLK_IN_HWEN ,OCM_CKIL_SYNC_WRAPPER8_CLK_IN clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 7. " PWM3_IPG_CLK_HIGHFREQ_STOP ,PWM3_IPG_CLK_HIGHFREQ clock root status" "Not stopped,Stopped" bitfld.long 0x00 5. " PWM3_IPG_CLK_HIGHFREQ_SWEN ,PWM3_IPG_CLK_HIGHFREQ clock enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PWM3_IPG_CLK_HIGHFREQ_HWEN ,PWM3_IPG_CLK_HIGHFREQ clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " PWM_IPG_CLK_STOP ,PWM_IPG_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " PWM_IPG_CLK_SWEN ,PWM_IPG_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " PWM_IPG_CLK_HWEN ,PWM_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x440000++0x03 line.long 0x00 "LPCG_IPS_SYNC_PWM4_REGS,IPS_SYNC_PWM4 Clocks Register" rbitfld.long 0x00 27. " IPS_SYNC_PWM4_IPG_MASTER_CLK_STOP ,IPS_SYNC_PWM4_IPG_MASTER_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 25. " IPS_SYNC_PWM4_IPG_MASTER_CLK_SWEN ,IPS_SYNC_PWM4_IPG_MASTER_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " IPS_SYNC_PWM4_IPG_MASTER_CLK_HWEN ,IPS_SYNC_PWM4_IPG_MASTER_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 23. " IPS_SYNC_PWM4_IPG_SLAVE_CLK_STOP ,IPS_SYNC_PWM4_IPG_SLAVE_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 21. " IPS_SYNC_PWM4_IPG_SLAVE_CLK_SWEN ,IPS_SYNC_PWM4_IPG_SLAVE_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 20. " IPS_SYNC_PWM4_IPG_SLAVE_CLK_HWEN ,IPS_SYNC_PWM4_IPG_SLAVE_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 19. " PWM4_IPG_CLK_S_STOP ,PWM4_IPG_CLK_S clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " PWM4_IPG_CLK_S_SWEN ,PWM4_IPG_CLK_S clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " PWM4_IPG_CLK_S_HWEN ,PWM4_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 11. " OCM_CKIL_SYNC_WRAPPER9_CLK_IN_STOP ,OCM_CKIL_SYNC_WRAPPER9_CLK_IN clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 9. " OCM_CKIL_SYNC_WRAPPER9_CLK_IN_SWEN ,OCM_CKIL_SYNC_WRAPPER9_CLK_IN clock enable" "Disabled,Enabled" bitfld.long 0x00 8. " OCM_CKIL_SYNC_WRAPPER9_CLK_IN_HWEN ,OCM_CKIL_SYNC_WRAPPER9_CLK_IN clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 7. " PWM4_IPG_CLK_HIGHFREQ_STOP ,PWM4_IPG_CLK_HIGHFREQ clock root status" "Not stopped,Stopped" bitfld.long 0x00 5. " PWM4_IPG_CLK_HIGHFREQ_SWEN ,PWM4_IPG_CLK_HIGHFREQ clock enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PWM4_IPG_CLK_HIGHFREQ_HWEN ,PWM4_IPG_CLK_HIGHFREQ clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " PWM_IPG_CLK_STOP ,PWM_IPG_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " PWM_IPG_CLK_SWEN ,PWM_IPG_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " PWM_IPG_CLK_HWEN ,PWM_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x450000++0x03 line.long 0x00 "LPCG_IPS_SYNC_PWM5_REGS,IPS_SYNC_PWM5 Clocks Register" rbitfld.long 0x00 27. " IPS_SYNC_PWM5_IPG_MASTER_CLK_STOP ,IPS_SYNC_PWM5_IPG_MASTER_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 25. " IPS_SYNC_PWM5_IPG_MASTER_CLK_SWEN ,IPS_SYNC_PWM5_IPG_MASTER_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " IPS_SYNC_PWM5_IPG_MASTER_CLK_HWEN ,IPS_SYNC_PWM5_IPG_MASTER_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 23. " IPS_SYNC_PWM5_IPG_SLAVE_CLK_STOP ,IPS_SYNC_PWM5_IPG_SLAVE_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 21. " IPS_SYNC_PWM5_IPG_SLAVE_CLK_SWEN ,IPS_SYNC_PWM5_IPG_SLAVE_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 20. " IPS_SYNC_PWM5_IPG_SLAVE_CLK_HWEN ,IPS_SYNC_PWM5_IPG_SLAVE_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 19. " PWM5_IPG_CLK_S_STOP ,PWM5_IPG_CLK_S clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " PWM5_IPG_CLK_S_SWEN ,PWM5_IPG_CLK_S clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " PWM5_IPG_CLK_S_HWEN ,PWM5_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 11. " CCM_CKIL_SYNC_WRAPPER10_CLK_IN_STOP ,OCM_CKIL_SYNC_WRAPPER10_CLK_IN clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 9. " CCM_CKIL_SYNC_WRAPPER10_CLK_IN_SWEN ,OCM_CKIL_SYNC_WRAPPER10_CLK_IN clock enable" "Disabled,Enabled" bitfld.long 0x00 8. " CCM_CKIL_SYNC_WRAPPER10_CLK_IN_HWEN ,OCM_CKIL_SYNC_WRAPPER10_CLK_IN clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 7. " PWM5_IPG_CLK_HIGHFREQ_STOP ,PWM5_IPG_CLK_HIGHFREQ clock root status" "Not stopped,Stopped" bitfld.long 0x00 5. " PWM5_IPG_CLK_HIGHFREQ_SWEN ,PWM5_IPG_CLK_HIGHFREQ clock enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PWM5_IPG_CLK_HIGHFREQ_HWEN ,PWM5_IPG_CLK_HIGHFREQ clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " PWM_IPG_CLK_STOP ,PWM_IPG_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " PWM_IPG_CLK_SWEN ,PWM_IPG_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " PWM_IPG_CLK_HWEN ,PWM_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x460000++0x03 line.long 0x00 "LPCG_IPS_SYNC_PWM6_REGS,IPS_SYNC_PWM6 Clocks Register" rbitfld.long 0x00 27. " IPS_SYNC_PWM6_IPG_MASTER_CLK_STOP ,IPS_SYNC_PWM6_IPG_MASTER_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 25. " IPS_SYNC_PWM6_IPG_MASTER_CLK_SWEN ,IPS_SYNC_PWM6_IPG_MASTER_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " IPS_SYNC_PWM6_IPG_MASTER_CLK_HWEN ,IPS_SYNC_PWM6_IPG_MASTER_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 23. " IPS_SYNC_PWM6_IPG_SLAVE_CLK_STOP ,IPS_SYNC_PWM6_IPG_SLAVE_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 21. " IPS_SYNC_PWM6_IPG_SLAVE_CLK_SWEN ,IPS_SYNC_PWM6_IPG_SLAVE_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 20. " IPS_SYNC_PWM6_IPG_SLAVE_CLK_HWEN ,IPS_SYNC_PWM6_IPG_SLAVE_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 19. " PWM6_IPG_CLK_S_STOP ,PWM6_IPG_CLK_S clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " PWM6_IPG_CLK_S_SWEN ,PWM6_IPG_CLK_S clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " PWM6_IPG_CLK_S_HWEN ,PWM6_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 11. " CCM_CKIL_SYNC_WRAPPER11_CLK_IN_STOP ,OCM_CKIL_SYNC_WRAPPER11_CLK_IN clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 9. " CCM_CKIL_SYNC_WRAPPER11_CLK_IN_SWEN ,OCM_CKIL_SYNC_WRAPPER11_CLK_IN clock enable" "Disabled,Enabled" bitfld.long 0x00 8. " CCM_CKIL_SYNC_WRAPPER11_CLK_IN_HWEN ,OCM_CKIL_SYNC_WRAPPER11_CLK_IN clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 7. " PWM6_IPG_CLK_HIGHFREQ_STOP ,PWM6_IPG_CLK_HIGHFREQ clock root status" "Not stopped,Stopped" bitfld.long 0x00 5. " PWM6_IPG_CLK_HIGHFREQ_SWEN ,PWM6_IPG_CLK_HIGHFREQ clock enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PWM6_IPG_CLK_HIGHFREQ_HWEN ,PWM6_IPG_CLK_HIGHFREQ clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " PWM_IPG_CLK_STOP ,PWM_IPG_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " PWM_IPG_CLK_SWEN ,PWM_IPG_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " PWM_IPG_CLK_HWEN ,PWM_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x470000++0x03 line.long 0x00 "LPCG_IPS_SYNC_PWM7_REGS,IPS_SYNC_PWM7 Clocks Register" rbitfld.long 0x00 27. " IPS_SYNC_PWM7_IPG_MASTER_CLK_STOP ,IPS_SYNC_PWM7_IPG_MASTER_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 25. " IPS_SYNC_PWM7_IPG_MASTER_CLK_SWEN ,IPS_SYNC_PWM7_IPG_MASTER_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " IPS_SYNC_PWM7_IPG_MASTER_CLK_HWEN ,IPS_SYNC_PWM7_IPG_MASTER_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 23. " IPS_SYNC_PWM7_IPG_SLAVE_CLK_STOP ,IPS_SYNC_PWM7_IPG_SLAVE_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 21. " IPS_SYNC_PWM7_IPG_SLAVE_CLK_SWEN ,IPS_SYNC_PWM7_IPG_SLAVE_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 20. " IPS_SYNC_PWM7_IPG_SLAVE_CLK_HWEN ,IPS_SYNC_PWM7_IPG_SLAVE_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 19. " PWM7_IPG_CLK_S_STOP ,PWM7_IPG_CLK_S clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " PWM7_IPG_CLK_S_SWEN ,PWM7_IPG_CLK_S clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " PWM7_IPG_CLK_S_HWEN ,PWM7_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 11. " CCM_CKIL_SYNC_WRAPPER12_CLK_IN_STOP ,OCM_CKIL_SYNC_WRAPPER12_CLK_IN clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 9. " CCM_CKIL_SYNC_WRAPPER12_CLK_IN_SWEN ,OCM_CKIL_SYNC_WRAPPER12_CLK_IN clock enable" "Disabled,Enabled" bitfld.long 0x00 8. " CCM_CKIL_SYNC_WRAPPER12_CLK_IN_HWEN ,OCM_CKIL_SYNC_WRAPPER12_CLK_IN clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 7. " PWM7_IPG_CLK_HIGHFREQ_STOP ,PWM7_IPG_CLK_HIGHFREQ clock root status" "Not stopped,Stopped" bitfld.long 0x00 5. " PWM7_IPG_CLK_HIGHFREQ_SWEN ,PWM7_IPG_CLK_HIGHFREQ clock enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PWM7_IPG_CLK_HIGHFREQ_HWEN ,PWM7_IPG_CLK_HIGHFREQ clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " PWM_IPG_CLK_STOP ,PWM_IPG_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " PWM_IPG_CLK_SWEN ,PWM_IPG_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " PWM_IPG_CLK_HWEN ,PWM_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x480000++0x03 line.long 0x00 "LPCG_GPIO0_REGS,GPIO0 Clock Register" rbitfld.long 0x00 19. " GPIO0_IPG_CLK_S_STOP ,GPIO0_IPG_CLK_S clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " GPIO0_IPG_CLK_S_SWEN ,GPIO0_IPG_CLK_S clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " GPIO0_IPG_CLK_S_HWEN ,GPIO0_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" group.long 0x490000++0x03 line.long 0x00 "LPCG_GPIO1_REGS,GPIO1 Clock Register" rbitfld.long 0x00 19. " GPIO1_IPG_CLK_S_STOP ,GPIO1_IPG_CLK_S clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " GPIO1_IPG_CLK_S_SWEN ,GPIO1_IPG_CLK_S clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " GPIO1_IPG_CLK_S_HWEN ,GPIO1_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" group.long 0x4A0000++0x03 line.long 0x00 "LPCG_GPIO2_REGS,GPIO2 Clock Register" rbitfld.long 0x00 19. " GPIO2_IPG_CLK_S_STOP ,GPIO2_IPG_CLK_S clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " GPIO2_IPG_CLK_S_SWEN ,GPIO2_IPG_CLK_S clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " GPIO2_IPG_CLK_S_HWEN ,GPIO2_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" group.long 0x4B0000++0x03 line.long 0x00 "LPCG_GPIO3_REGS,GPIO3 Clock Register" rbitfld.long 0x00 19. " GPIO3_IPG_CLK_S_STOP ,GPIO3_IPG_CLK_S clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " GPIO3_IPG_CLK_S_SWEN ,GPIO3_IPG_CLK_S clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " GPIO3_IPG_CLK_S_HWEN ,GPIO3_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" group.long 0x4C0000++0x03 line.long 0x00 "LPCG_GPIO4_REGS,GPIO4 Clock Register" rbitfld.long 0x00 19. " GPIO4_IPG_CLK_S_STOP ,GPIO4_IPG_CLK_S clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " GPIO4_IPG_CLK_S_SWEN ,GPIO4_IPG_CLK_S clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " GPIO4_IPG_CLK_S_HWEN ,GPIO4_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" group.long 0x4D0000++0x03 line.long 0x00 "LPCG_GPIO5_REGS,GPIO5 Clock Register" rbitfld.long 0x00 19. " GPIO5_IPG_CLK_S_STOP ,GPIO5_IPG_CLK_S clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " GPIO5_IPG_CLK_S_SWEN ,GPIO5_IPG_CLK_S clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " GPIO5_IPG_CLK_S_HWEN ,GPIO5_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" group.long 0x4E0000++0x03 line.long 0x00 "LPCG_GPIO6_REGS,GPIO6 Clock Register" rbitfld.long 0x00 19. " GPIO6_IPG_CLK_S_STOP ,GPIO6_IPG_CLK_S clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " GPIO6_IPG_CLK_S_SWEN ,GPIO6_IPG_CLK_S clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " GPIO6_IPG_CLK_S_HWEN ,GPIO6_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" group.long 0x4F0000++0x03 line.long 0x00 "LPCG_GPIO7_REGS,GPIO7 Clock Register" rbitfld.long 0x00 19. " GPIO7_IPG_CLK_S_STOP ,GPIO7_IPG_CLK_S clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " GPIO7_IPG_CLK_S_SWEN ,GPIO7_IPG_CLK_S clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " GPIO7_IPG_CLK_S_HWEN ,GPIO7_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" group.long 0x500000++0x03 line.long 0x00 "LPCG_ROMCP_REGS,ROMCP Clocks Register" rbitfld.long 0x00 19. " ROMCP_HCLK_REG_STOP ,ROMCP_HCLK_REG clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " ROMCP_HCLK_REG_SWEN ,ROMCP_HCLK_REG clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " ROMCP_HCLK_REG_HWEN ,ROMCP_HCLK_REG clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 7. " LSIO_96KROM_MEM_ROM_CLK_STOP ,LSIO_96KROM_MEM_ROM_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 5. " LSIO_96KROM_MEM_ROM_CLK_SWEN ,LSIO_96KROM_MEM_ROM_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 4. " LSIO_96KROM_MEM_ROM_CLK_HWEN ,LSIO_96KROM_MEM_ROM_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 3. " ROMCP_HCLK_STOP ,ROMCP_HCLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 1. " ROMCP_HCLK_SWEN ,ROMCP_HCLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " ROMCP_HCLK_HWEN ,ROMCP_HCLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x520000++0x03 line.long 0x00 "LPCG_QSPI0_REGS,QSPI0 Clocks Register" rbitfld.long 0x00 27. " QSPI0_IPG_CLK_S_STOP ,QSPI0_IPG_CLK_S clock root status" "Not stopped,Stopped" bitfld.long 0x00 25. " QSPI0_IPG_CLK_S_SWEN ,QSPI0_IPG_CLK_S clock enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " QSPI0_IPG_CLK_S_HWEN ,QSPI0_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 23. " QSPI0_IPG_CLK_STOP ,QSPI0_IPG_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 21. " QSPI0_IPG_CLK_SWEN ,QSPI0_IPG_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 20. " QSPI0_IPG_CLK_HWEN ,QSPI0_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 19. " QSPI0_HCLK_STOP ,QSPI0_HCLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " QSPI0_HCLK_SWEN ,QSPI0_HCLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " QSPI0_HCLK_HWEN ,QSPI0_HCLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " QSPI0_IPG_CLK_SFCK_STOP ,QSPI0_IPG_CLK_SFCK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " QSPI0_IPG_CLK_SFCK_SWEN ,QSPI0_IPG_CLK_SFCK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " QSPI0_IPG_CLK_SFCK_HWEN ,QSPI0_IPG_CLK_SFCK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x530000++0x03 line.long 0x00 "LPCG_QSPI1_REGS,QSPI1 Clocks Register" rbitfld.long 0x00 27. " QSPI1_IPG_CLK_S_STOP ,QSPI1_IPG_CLK_S clock root status" "Not stopped,Stopped" bitfld.long 0x00 25. " QSPI1_IPG_CLK_S_SWEN ,QSPI1_IPG_CLK_S clock enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " QSPI1_IPG_CLK_S_HWEN ,QSPI1_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 23. " QSPI1_IPG_CLK_STOP ,QSPI1_IPG_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 21. " QSPI1_IPG_CLK_SWEN ,QSPI1_IPG_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 20. " QSPI1_IPG_CLK_HWEN ,QSPI1_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 19. " QSPI1_HCLK_STOP ,QSPI1_HCLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " QSPI1_HCLK_SWEN ,QSPI1_HCLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " QSPI1_HCLK_HWEN ,QSPI1_HCLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " QSPI0_IPG_CLK_SFCK_STOP ,QSPI0_IPG_CLK_SFCK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " QSPI0_IPG_CLK_SFCK_SWEN ,QSPI0_IPG_CLK_SFCK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " QSPI0_IPG_CLK_SFCK_HWEN ,QSPI0_IPG_CLK_SFCK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x540000++0x03 line.long 0x00 "LPCG_IPS_SYNC_GPT0_REGS,GPT0 Clocks Register" rbitfld.long 0x00 27. " IPS_SYNC_GPT0_IPG_MASTER_CLK_STOP ,IPS_SYNC_GPT0_IPG_MASTER_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 25. " IPS_SYNC_GPT0_IPG_MASTER_CLK_SWEN ,IPS_SYNC_GPT0_IPG_MASTER_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " IPS_SYNC_GPT0_IPG_MASTER_CLK_HWEN ,IPS_SYNC_GPT0_IPG_MASTER_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 23. " IPS_SYNC_GPT0_IPG_SLAVE_CLK_STOP ,IPS_SYNC_GPT0_IPG_SLAVE_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 21. " IPS_SYNC_GPT0_IPG_SLAVE_CLK_SWEN ,IPS_SYNC_GPT0_IPG_SLAVE_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 20. " IPS_SYNC_GPT0_IPG_SLAVE_CLK_HWEN ,IPS_SYNC_GPT0_IPG_SLAVE_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 19. " GPT0_IPG_CLK_S_STOP ,GPT0_IPG_CLK_S clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " GPT0_IPG_CLK_S_SWEN ,GPT0_IPG_CLK_S clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " GPT0_IPG_CLK_S_HWEN ,GPT0_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 11. " CCM_CKIL_SYNC_WRAPPER0_CLK_IN_STOP ,CCM_CKIL_SYNC_WRAPPER0_CLK_IN clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 9. " CCM_CKIL_SYNC_WRAPPER0_CLK_IN_SWEN ,CCM_CKIL_SYNC_WRAPPER0_CLK_IN clock enable" "Disabled,Enabled" bitfld.long 0x00 8. " CCM_CKIL_SYNC_WRAPPER0_CLK_IN_HWEN ,CCM_CKIL_SYNC_WRAPPER0_CLK_IN clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 7. " GPT$0_IPG_CLK_HIGHFREQ_STOP ,GPT$0_IPG_CLK_HIGHFREQ clock root status" "Not stopped,Stopped" bitfld.long 0x00 5. " GPT$0_IPG_CLK_HIGHFREQ_SWEN ,GPT$0_IPG_CLK_HIGHFREQ clock enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " GPT$0_IPG_CLK_HIGHFREQ_HWEN ,GPT$0_IPG_CLK_HIGHFREQ clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " GPT0_IPG_CLK_STOP ,GPT0_IPG_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " GPT0_IPG_CLK_SWEN ,GPT0_IPG_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " GPT0_IPG_CLK_HWEN ,GPT0_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x550000++0x03 line.long 0x00 "LPCG_IPS_SYNC_GPT1_REGS,GPT1 Clocks Register" rbitfld.long 0x00 27. " IPS_SYNC_GPT1_IPG_MASTER_CLK_STOP ,IPS_SYNC_GPT1_IPG_MASTER_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 25. " IPS_SYNC_GPT1_IPG_MASTER_CLK_SWEN ,IPS_SYNC_GPT1_IPG_MASTER_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " IPS_SYNC_GPT1_IPG_MASTER_CLK_HWEN ,IPS_SYNC_GPT1_IPG_MASTER_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 23. " IPS_SYNC_GPT1_IPG_SLAVE_CLK_STOP ,IPS_SYNC_GPT1_IPG_SLAVE_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 21. " IPS_SYNC_GPT1_IPG_SLAVE_CLK_SWEN ,IPS_SYNC_GPT1_IPG_SLAVE_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 20. " IPS_SYNC_GPT1_IPG_SLAVE_CLK_HWEN ,IPS_SYNC_GPT1_IPG_SLAVE_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 19. " GPT1_IPG_CLK_S_STOP ,GPT1_IPG_CLK_S clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " GPT1_IPG_CLK_S_SWEN ,GPT1_IPG_CLK_S clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " GPT1_IPG_CLK_S_HWEN ,GPT1_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 11. " CCM_CKIL_SYNC_WRAPPER1_CLK_IN_STOP ,CCM_CKIL_SYNC_WRAPPER1_CLK_IN clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 9. " CCM_CKIL_SYNC_WRAPPER1_CLK_IN_SWEN ,CCM_CKIL_SYNC_WRAPPER1_CLK_IN clock enable" "Disabled,Enabled" bitfld.long 0x00 8. " CCM_CKIL_SYNC_WRAPPER1_CLK_IN_HWEN ,CCM_CKIL_SYNC_WRAPPER1_CLK_IN clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 7. " GPT$0_IPG_CLK_HIGHFREQ_STOP ,GPT$0_IPG_CLK_HIGHFREQ clock root status" "Not stopped,Stopped" bitfld.long 0x00 5. " GPT$0_IPG_CLK_HIGHFREQ_SWEN ,GPT$0_IPG_CLK_HIGHFREQ clock enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " GPT$0_IPG_CLK_HIGHFREQ_HWEN ,GPT$0_IPG_CLK_HIGHFREQ clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " GPT1_IPG_CLK_STOP ,GPT1_IPG_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " GPT1_IPG_CLK_SWEN ,GPT1_IPG_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " GPT1_IPG_CLK_HWEN ,GPT1_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x560000++0x03 line.long 0x00 "LPCG_IPS_SYNC_GPT2_REGS,GPT2 Clocks Register" rbitfld.long 0x00 27. " IPS_SYNC_GPT2_IPG_MASTER_CLK_STOP ,IPS_SYNC_GPT2_IPG_MASTER_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 25. " IPS_SYNC_GPT2_IPG_MASTER_CLK_SWEN ,IPS_SYNC_GPT2_IPG_MASTER_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " IPS_SYNC_GPT2_IPG_MASTER_CLK_HWEN ,IPS_SYNC_GPT2_IPG_MASTER_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 23. " IPS_SYNC_GPT2_IPG_SLAVE_CLK_STOP ,IPS_SYNC_GPT2_IPG_SLAVE_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 21. " IPS_SYNC_GPT2_IPG_SLAVE_CLK_SWEN ,IPS_SYNC_GPT2_IPG_SLAVE_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 20. " IPS_SYNC_GPT2_IPG_SLAVE_CLK_HWEN ,IPS_SYNC_GPT2_IPG_SLAVE_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 19. " GPT2_IPG_CLK_S_STOP ,GPT2_IPG_CLK_S clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " GPT2_IPG_CLK_S_SWEN ,GPT2_IPG_CLK_S clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " GPT2_IPG_CLK_S_HWEN ,GPT2_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 11. " CCM_CKIL_SYNC_WRAPPER2_CLK_IN_STOP ,CCM_CKIL_SYNC_WRAPPER2_CLK_IN clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 9. " CCM_CKIL_SYNC_WRAPPER2_CLK_IN_SWEN ,CCM_CKIL_SYNC_WRAPPER2_CLK_IN clock enable" "Disabled,Enabled" bitfld.long 0x00 8. " CCM_CKIL_SYNC_WRAPPER2_CLK_IN_HWEN ,CCM_CKIL_SYNC_WRAPPER2_CLK_IN clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 7. " GPT$0_IPG_CLK_HIGHFREQ_STOP ,GPT$0_IPG_CLK_HIGHFREQ clock root status" "Not stopped,Stopped" bitfld.long 0x00 5. " GPT$0_IPG_CLK_HIGHFREQ_SWEN ,GPT$0_IPG_CLK_HIGHFREQ clock enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " GPT$0_IPG_CLK_HIGHFREQ_HWEN ,GPT$0_IPG_CLK_HIGHFREQ clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " GPT2_IPG_CLK_STOP ,GPT2_IPG_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " GPT2_IPG_CLK_SWEN ,GPT2_IPG_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " GPT2_IPG_CLK_HWEN ,GPT2_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x570000++0x03 line.long 0x00 "LPCG_IPS_SYNC_GPT3_REGS,GPT3 Clocks Register" rbitfld.long 0x00 27. " IPS_SYNC_GPT3_IPG_MASTER_CLK_STOP ,IPS_SYNC_GPT3_IPG_MASTER_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 25. " IPS_SYNC_GPT3_IPG_MASTER_CLK_SWEN ,IPS_SYNC_GPT3_IPG_MASTER_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " IPS_SYNC_GPT3_IPG_MASTER_CLK_HWEN ,IPS_SYNC_GPT3_IPG_MASTER_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 23. " IPS_SYNC_GPT3_IPG_SLAVE_CLK_STOP ,IPS_SYNC_GPT3_IPG_SLAVE_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 21. " IPS_SYNC_GPT3_IPG_SLAVE_CLK_SWEN ,IPS_SYNC_GPT3_IPG_SLAVE_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 20. " IPS_SYNC_GPT3_IPG_SLAVE_CLK_HWEN ,IPS_SYNC_GPT3_IPG_SLAVE_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 19. " GPT3_IPG_CLK_S_STOP ,GPT3_IPG_CLK_S clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " GPT3_IPG_CLK_S_SWEN ,GPT3_IPG_CLK_S clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " GPT3_IPG_CLK_S_HWEN ,GPT3_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 11. " CCM_CKIL_SYNC_WRAPPER3_CLK_IN_STOP ,CCM_CKIL_SYNC_WRAPPER3_CLK_IN clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 9. " CCM_CKIL_SYNC_WRAPPER3_CLK_IN_SWEN ,CCM_CKIL_SYNC_WRAPPER3_CLK_IN clock enable" "Disabled,Enabled" bitfld.long 0x00 8. " CCM_CKIL_SYNC_WRAPPER3_CLK_IN_HWEN ,CCM_CKIL_SYNC_WRAPPER3_CLK_IN clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 7. " GPT$0_IPG_CLK_HIGHFREQ_STOP ,GPT$0_IPG_CLK_HIGHFREQ clock root status" "Not stopped,Stopped" bitfld.long 0x00 5. " GPT$0_IPG_CLK_HIGHFREQ_SWEN ,GPT$0_IPG_CLK_HIGHFREQ clock enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " GPT$0_IPG_CLK_HIGHFREQ_HWEN ,GPT$0_IPG_CLK_HIGHFREQ clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " GPT3_IPG_CLK_STOP ,GPT3_IPG_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " GPT3_IPG_CLK_SWEN ,GPT3_IPG_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " GPT3_IPG_CLK_HWEN ,GPT3_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x580000++0x03 line.long 0x00 "LPCG_IPS_SYNC_GPT4_REGS,GPT4 Clocks Register" rbitfld.long 0x00 27. " IPS_SYNC_GPT4_IPG_MASTER_CLK_STOP ,IPS_SYNC_GPT4_IPG_MASTER_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 25. " IPS_SYNC_GPT4_IPG_MASTER_CLK_SWEN ,IPS_SYNC_GPT4_IPG_MASTER_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " IPS_SYNC_GPT4_IPG_MASTER_CLK_HWEN ,IPS_SYNC_GPT4_IPG_MASTER_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 23. " IPS_SYNC_GPT4_IPG_SLAVE_CLK_STOP ,IPS_SYNC_GPT4_IPG_SLAVE_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 21. " IPS_SYNC_GPT4_IPG_SLAVE_CLK_SWEN ,IPS_SYNC_GPT4_IPG_SLAVE_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 20. " IPS_SYNC_GPT4_IPG_SLAVE_CLK_HWEN ,IPS_SYNC_GPT4_IPG_SLAVE_CLK clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 19. " GPT4_IPG_CLK_S_STOP ,GPT4_IPG_CLK_S clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " GPT4_IPG_CLK_S_SWEN ,GPT4_IPG_CLK_S clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " GPT4_IPG_CLK_S_HWEN ,GPT4_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 11. " CCM_CKIL_SYNC_WRAPPER4_CLK_IN_STOP ,CCM_CKIL_SYNC_WRAPPER4_CLK_IN clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 9. " CCM_CKIL_SYNC_WRAPPER4_CLK_IN_SWEN ,CCM_CKIL_SYNC_WRAPPER4_CLK_IN clock enable" "Disabled,Enabled" bitfld.long 0x00 8. " CCM_CKIL_SYNC_WRAPPER4_CLK_IN_HWEN ,CCM_CKIL_SYNC_WRAPPER4_CLK_IN clock HW signal treatment" "Ignored,Automatically gated" newline rbitfld.long 0x00 7. " GPT$0_IPG_CLK_HIGHFREQ_STOP ,GPT$0_IPG_CLK_HIGHFREQ clock root status" "Not stopped,Stopped" bitfld.long 0x00 5. " GPT$0_IPG_CLK_HIGHFREQ_SWEN ,GPT$0_IPG_CLK_HIGHFREQ clock enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " GPT$0_IPG_CLK_HIGHFREQ_HWEN ,GPT$0_IPG_CLK_HIGHFREQ clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " GPT4_IPG_CLK_STOP ,GPT4_IPG_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " GPT4_IPG_CLK_SWEN ,GPT4_IPG_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " GPT4_IPG_CLK_HWEN ,GPT4_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x590000++0x03 line.long 0x00 "LPCG_OCRAM_REGS,OCRAM Clocks Register" rbitfld.long 0x00 7. " OCRAM_MEM_WRAPPER_CLK_STOP ,OCRAM_MEM_WRAPPER_CLK clock root status" "Not stopped,Stopped" bitfld.long 0x00 5. " OCRAM_MEM_WRAPPER_CLK_SWEN ,OCRAM_MEM_WRAPPER_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " OCRAM_MEM_WRAPPER_CLK_HWEN ,OCRAM_MEM_WRAPPER_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " OCRAM_CTRL_CLK_STOP ,OCRAM_CTRL_CLK clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " OCRAM_CTRL_CLK_SWEN ,OCRAM_CTRL_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " OCRAM_CTRL_CLK_HWEN ,OCRAM_CTRL_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x5A0000++0x03 line.long 0x00 "LPCG_KPP_REGS,KPP Clocks Register" rbitfld.long 0x00 19. " KPP_IPG_CLK_S_STOP ,KPP_IPG_CLK_S clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " KPP_IPG_CLK_S_SWEN ,KPP_IPG_CLK_S clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " KPP_IPG_CLK_S_HWEN ,KPP_IPG_CLK_S clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " CCM_CKIL_SYNC_WRAPPER13_CLK_IN_STOP ,CCM_CKIL_SYNC_WRAPPER13_CLK_IN clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " CCM_CKIL_SYNC_WRAPPER13_CLK_IN_SWEN ,CCM_CKIL_SYNC_WRAPPER13_CLK_IN clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " CCM_CKIL_SYNC_WRAPPER13_CLK_IN_HWEN ,CCM_CKIL_SYNC_WRAPPER13_CLK_IN clock HW signal treatment" "Ignored,Automatically gated" group.long 0x600000++0x03 line.long 0x00 "LPCG_MU5_MCU_REGS,MU5_MCU Clocks Register" rbitfld.long 0x00 19. " MU5_IPG_CLK_S_MCU_STOP ,MU5_IPG_CLK_S_MCU clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " MU5_IPG_CLK_S_MCU_SWEN ,MU5_IPG_CLK_S_MCU clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " MU5_IPG_CLK_S_MCU_HWEN ,MU5_IPG_CLK_S_MCU clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " MU5_IPG_CLK_MCU_STOP ,MU5_IPG_CLK_MCU clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " MU5_IPG_CLK_MCU_SWEN ,MU5_IPG_CLK_MCU clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " MU5_IPG_CLK_MCU_HWEN ,MU5_IPG_CLK_MCU clock HW signal treatment" "Ignored,Automatically gated" group.long 0x610000++0x03 line.long 0x00 "LPCG_MU6_MCU_REGS,MU6_MCU Clocks Register" rbitfld.long 0x00 19. " MU6_IPG_CLK_S_MCU_STOP ,MU6_IPG_CLK_S_MCU clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " MU6_IPG_CLK_S_MCU_SWEN ,MU6_IPG_CLK_S_MCU clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " MU6_IPG_CLK_S_MCU_HWEN ,MU6_IPG_CLK_S_MCU clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " MU6_IPG_CLK_MCU_STOP ,MU6_IPG_CLK_MCU clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " MU6_IPG_CLK_MCU_SWEN ,MU6_IPG_CLK_MCU clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " MU6_IPG_CLK_MCU_HWEN ,MU6_IPG_CLK_MCU clock HW signal treatment" "Ignored,Automatically gated" group.long 0x620000++0x03 line.long 0x00 "LPCG_MU7_MCU_REGS,MU7_MCU Clocks Register" rbitfld.long 0x00 19. " MU7_IPG_CLK_S_MCU_STOP ,MU7_IPG_CLK_S_MCU clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " MU7_IPG_CLK_S_MCU_SWEN ,MU7_IPG_CLK_S_MCU clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " MU7_IPG_CLK_S_MCU_HWEN ,MU7_IPG_CLK_S_MCU clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " MU7_IPG_CLK_MCU_STOP ,MU7_IPG_CLK_MCU clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " MU7_IPG_CLK_MCU_SWEN ,MU7_IPG_CLK_MCU clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " MU7_IPG_CLK_MCU_HWEN ,MU7_IPG_CLK_MCU clock HW signal treatment" "Ignored,Automatically gated" group.long 0x630000++0x03 line.long 0x00 "LPCG_MU8_MCU_REGS,MU8_MCU Clocks Register" rbitfld.long 0x00 19. " MU8_IPG_CLK_S_MCU_STOP ,MU8_IPG_CLK_S_MCU clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " MU8_IPG_CLK_S_MCU_SWEN ,MU8_IPG_CLK_S_MCU clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " MU8_IPG_CLK_S_MCU_HWEN ,MU8_IPG_CLK_S_MCU clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " MU8_IPG_CLK_MCU_STOP ,MU8_IPG_CLK_MCU clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " MU8_IPG_CLK_MCU_SWEN ,MU8_IPG_CLK_MCU clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " MU8_IPG_CLK_MCU_HWEN ,MU8_IPG_CLK_MCU clock HW signal treatment" "Ignored,Automatically gated" group.long 0x640000++0x03 line.long 0x00 "LPCG_MU9_MCU_REGS,MU9_MCU Clocks Register" rbitfld.long 0x00 19. " MU9_IPG_CLK_S_MCU_STOP ,MU9_IPG_CLK_S_MCU clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " MU9_IPG_CLK_S_MCU_SWEN ,MU9_IPG_CLK_S_MCU clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " MU9_IPG_CLK_S_MCU_HWEN ,MU9_IPG_CLK_S_MCU clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " MU9_IPG_CLK_MCU_STOP ,MU9_IPG_CLK_MCU clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " MU9_IPG_CLK_MCU_SWEN ,MU9_IPG_CLK_MCU clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " MU9_IPG_CLK_MCU_HWEN ,MU9_IPG_CLK_MCU clock HW signal treatment" "Ignored,Automatically gated" group.long 0x650000++0x03 line.long 0x00 "LPCG_MU10_MCU_REGS,MU10_MCU Clocks Register" rbitfld.long 0x00 19. " MU10_IPG_CLK_S_MCU_STOP ,MU10_IPG_CLK_S_MCU clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " MU10_IPG_CLK_S_MCU_SWEN ,MU10_IPG_CLK_S_MCU clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " MU10_IPG_CLK_S_MCU_HWEN ,MU10_IPG_CLK_S_MCU clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " MU10_IPG_CLK_MCU_STOP ,MU10_IPG_CLK_MCU clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " MU10_IPG_CLK_MCU_SWEN ,MU10_IPG_CLK_MCU clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " MU10_IPG_CLK_MCU_HWEN ,MU10_IPG_CLK_MCU clock HW signal treatment" "Ignored,Automatically gated" group.long 0x660000++0x03 line.long 0x00 "LPCG_MU11_MCU_REGS,MU11_MCU Clocks Register" rbitfld.long 0x00 19. " MU11_IPG_CLK_S_MCU_STOP ,MU11_IPG_CLK_S_MCU clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " MU11_IPG_CLK_S_MCU_SWEN ,MU11_IPG_CLK_S_MCU clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " MU11_IPG_CLK_S_MCU_HWEN ,MU11_IPG_CLK_S_MCU clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " MU11_IPG_CLK_MCU_STOP ,MU11_IPG_CLK_MCU clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " MU11_IPG_CLK_MCU_SWEN ,MU11_IPG_CLK_MCU clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " MU11_IPG_CLK_MCU_HWEN ,MU11_IPG_CLK_MCU clock HW signal treatment" "Ignored,Automatically gated" group.long 0x670000++0x03 line.long 0x00 "LPCG_MU12_MCU_REGS,MU12_MCU Clocks Register" rbitfld.long 0x00 19. " MU12_IPG_CLK_S_MCU_STOP ,MU12_IPG_CLK_S_MCU clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " MU12_IPG_CLK_S_MCU_SWEN ,MU12_IPG_CLK_S_MCU clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " MU12_IPG_CLK_S_MCU_HWEN ,MU12_IPG_CLK_S_MCU clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " MU12_IPG_CLK_MCU_STOP ,MU12_IPG_CLK_MCU clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " MU12_IPG_CLK_MCU_SWEN ,MU12_IPG_CLK_MCU clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " MU12_IPG_CLK_MCU_HWEN ,MU12_IPG_CLK_MCU clock HW signal treatment" "Ignored,Automatically gated" group.long 0x680000++0x03 line.long 0x00 "LPCG_MU13_MCU_REGS,MU13_MCU Clocks Register" rbitfld.long 0x00 19. " MU13_IPG_CLK_S_MCU_STOP ,MU13_IPG_CLK_S_MCU clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " MU13_IPG_CLK_S_MCU_SWEN ,MU13_IPG_CLK_S_MCU clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " MU13_IPG_CLK_S_MCU_HWEN ,MU13_IPG_CLK_S_MCU clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " MU13_IPG_CLK_MCU_STOP ,MU13_IPG_CLK_MCU clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " MU13_IPG_CLK_MCU_SWEN ,MU13_IPG_CLK_MCU clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " MU13_IPG_CLK_MCU_HWEN ,MU13_IPG_CLK_MCU clock HW signal treatment" "Ignored,Automatically gated" group.long 0x690000++0x03 line.long 0x00 "LPCG_MU5_MCU_DSP_REGS,MU5_MCU_DSP Clocks Register" rbitfld.long 0x00 19. " MU5_IPG_CLK_S_DSP_STOP ,MU5_IPG_CLK_S_DSP clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " MU5_IPG_CLK_S_DSP_SWEN ,MU5_IPG_CLK_S_DSP clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " MU5_IPG_CLK_S_DSP_HWEN ,MU5_IPG_CLK_S_DSP clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " MU5_IPG_CLK_DSP_STOP ,MU5_IPG_CLK_DSP clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " MU5_IPG_CLK_DSP_SWEN ,MU5_IPG_CLK_DSP clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " MU5_IPG_CLK_DSP_HWEN ,MU5_IPG_CLK_DSP clock HW signal treatment" "Ignored,Automatically gated" group.long 0x6A0000++0x03 line.long 0x00 "LPCG_MU6_MCU_DSP_REGS,MU6_MCU_DSP Clocks Register" rbitfld.long 0x00 19. " MU6_IPG_CLK_S_DSP_STOP ,MU6_IPG_CLK_S_DSP clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " MU6_IPG_CLK_S_DSP_SWEN ,MU6_IPG_CLK_S_DSP clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " MU6_IPG_CLK_S_DSP_HWEN ,MU6_IPG_CLK_S_DSP clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " MU6_IPG_CLK_DSP_STOP ,MU6_IPG_CLK_DSP clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " MU6_IPG_CLK_DSP_SWEN ,MU6_IPG_CLK_DSP clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " MU6_IPG_CLK_DSP_HWEN ,MU6_IPG_CLK_DSP clock HW signal treatment" "Ignored,Automatically gated" group.long 0x6B0000++0x03 line.long 0x00 "LPCG_MU7_MCU_DSP_REGS,MU7_MCU_DSP Clocks Register" rbitfld.long 0x00 19. " MU7_IPG_CLK_S_DSP_STOP ,MU7_IPG_CLK_S_DSP clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " MU7_IPG_CLK_S_DSP_SWEN ,MU7_IPG_CLK_S_DSP clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " MU7_IPG_CLK_S_DSP_HWEN ,MU7_IPG_CLK_S_DSP clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " MU7_IPG_CLK_DSP_STOP ,MU7_IPG_CLK_DSP clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " MU7_IPG_CLK_DSP_SWEN ,MU7_IPG_CLK_DSP clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " MU7_IPG_CLK_DSP_HWEN ,MU7_IPG_CLK_DSP clock HW signal treatment" "Ignored,Automatically gated" group.long 0x6C0000++0x03 line.long 0x00 "LPCG_MU8_MCU_DSP_REGS,MU8_MCU_DSP Clocks Register" rbitfld.long 0x00 19. " MU8_IPG_CLK_S_DSP_STOP ,MU8_IPG_CLK_S_DSP clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " MU8_IPG_CLK_S_DSP_SWEN ,MU8_IPG_CLK_S_DSP clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " MU8_IPG_CLK_S_DSP_HWEN ,MU8_IPG_CLK_S_DSP clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " MU8_IPG_CLK_DSP_STOP ,MU8_IPG_CLK_DSP clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " MU8_IPG_CLK_DSP_SWEN ,MU8_IPG_CLK_DSP clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " MU8_IPG_CLK_DSP_HWEN ,MU8_IPG_CLK_DSP clock HW signal treatment" "Ignored,Automatically gated" group.long 0x6D0000++0x03 line.long 0x00 "LPCG_MU9_MCU_DSP_REGS,MU9_MCU_DSP Clocks Register" rbitfld.long 0x00 19. " MU9_IPG_CLK_S_DSP_STOP ,MU9_IPG_CLK_S_DSP clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " MU9_IPG_CLK_S_DSP_SWEN ,MU9_IPG_CLK_S_DSP clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " MU9_IPG_CLK_S_DSP_HWEN ,MU9_IPG_CLK_S_DSP clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " MU9_IPG_CLK_DSP_STOP ,MU9_IPG_CLK_DSP clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " MU9_IPG_CLK_DSP_SWEN ,MU9_IPG_CLK_DSP clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " MU9_IPG_CLK_DSP_HWEN ,MU9_IPG_CLK_DSP clock HW signal treatment" "Ignored,Automatically gated" group.long 0x6E0000++0x03 line.long 0x00 "LPCG_MU10_MCU_DSP_REGS,MU10_MCU_DSP Clocks Register" rbitfld.long 0x00 19. " MU10_IPG_CLK_S_DSP_STOP ,MU10_IPG_CLK_S_DSP clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " MU10_IPG_CLK_S_DSP_SWEN ,MU10_IPG_CLK_S_DSP clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " MU10_IPG_CLK_S_DSP_HWEN ,MU10_IPG_CLK_S_DSP clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " MU10_IPG_CLK_DSP_STOP ,MU10_IPG_CLK_DSP clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " MU10_IPG_CLK_DSP_SWEN ,MU10_IPG_CLK_DSP clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " MU10_IPG_CLK_DSP_HWEN ,MU10_IPG_CLK_DSP clock HW signal treatment" "Ignored,Automatically gated" group.long 0x6F0000++0x03 line.long 0x00 "LPCG_MU11_MCU_DSP_REGS,MU11_MCU_DSP Clocks Register" rbitfld.long 0x00 19. " MU11_IPG_CLK_S_DSP_STOP ,MU11_IPG_CLK_S_DSP clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " MU11_IPG_CLK_S_DSP_SWEN ,MU11_IPG_CLK_S_DSP clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " MU11_IPG_CLK_S_DSP_HWEN ,MU11_IPG_CLK_S_DSP clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " MU11_IPG_CLK_DSP_STOP ,MU11_IPG_CLK_DSP clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " MU11_IPG_CLK_DSP_SWEN ,MU11_IPG_CLK_DSP clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " MU11_IPG_CLK_DSP_HWEN ,MU11_IPG_CLK_DSP clock HW signal treatment" "Ignored,Automatically gated" group.long 0x700000++0x03 line.long 0x00 "LPCG_MU12_MCU_DSP_REGS,MU12_MCU_DSP Clocks Register" rbitfld.long 0x00 19. " MU12_IPG_CLK_S_DSP_STOP ,MU12_IPG_CLK_S_DSP clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " MU12_IPG_CLK_S_DSP_SWEN ,MU12_IPG_CLK_S_DSP clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " MU12_IPG_CLK_S_DSP_HWEN ,MU12_IPG_CLK_S_DSP clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " MU12_IPG_CLK_DSP_STOP ,MU12_IPG_CLK_DSP clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " MU12_IPG_CLK_DSP_SWEN ,MU12_IPG_CLK_DSP clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " MU12_IPG_CLK_DSP_HWEN ,MU12_IPG_CLK_DSP clock HW signal treatment" "Ignored,Automatically gated" group.long 0x710000++0x03 line.long 0x00 "LPCG_MU13_MCU_DSP_REGS,MU13_MCU_DSP Clocks Register" rbitfld.long 0x00 19. " MU13_IPG_CLK_S_DSP_STOP ,MU13_IPG_CLK_S_DSP clock root status" "Not stopped,Stopped" bitfld.long 0x00 17. " MU13_IPG_CLK_S_DSP_SWEN ,MU13_IPG_CLK_S_DSP clock enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " MU13_IPG_CLK_S_DSP_HWEN ,MU13_IPG_CLK_S_DSP clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " MU13_IPG_CLK_DSP_STOP ,MU13_IPG_CLK_DSP clock root status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " MU13_IPG_CLK_DSP_SWEN ,MU13_IPG_CLK_DSP clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " MU13_IPG_CLK_DSP_HWEN ,MU13_IPG_CLK_DSP clock HW signal treatment" "Ignored,Automatically gated" width 0x0B tree.end sif (cpuis("IMX8*-SCU")) tree "SCU (System Control Unit)" base ad:0x33000000 width 22. group.long 0x5E0000++0x03 line.long 0x00 "LPCG_TCMC_HCLK_REGS,TCMC_HCLK Clock Register" rbitfld.long 0x00 3. " CM4_TCMC_HCLK_STOP ,CM4_TCMC_HCLK clock status" "Not stopped,Stopped" bitfld.long 0x00 1. " CM4_TCMC_HCLK_SWEN ,CM4_TCMC_HCLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " CM4_TCMC_HCLK_HWEN ,CM4_TCMC_HCLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x5F0000++0x03 line.long 0x00 "LPCG_MMCAU_HCLK_REGS,MMCAU_HCLK Clock Register" rbitfld.long 0x00 3. " CM4_MMCAU_HCLK_STOP ,CM4_MMCAU_HCLK clock status" "Not stopped,Stopped" bitfld.long 0x00 1. " CM4_MMCAU_HCLK_SWEN ,CM4_MMCAU_HCLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " CM4_MMCAU_HCLK_HWEN ,CM4_MMCAU_HCLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x600000++0x03 line.long 0x00 "LPCG_TPM_REGS,TPM Clocks Register" rbitfld.long 0x00 7. " TPM1_IPG_CLK_STOP_STOP ,TPM_IPG_CLK_STOP clock status" "Not stopped,Stopped" bitfld.long 0x00 5. " TPM1_IPG_CLK_STOP_SWEN ,TPM_IPG_CLK_STOP clock enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " TPM1_IPG_CLK_STOP_HWEN ,TPM_IPG_CLK_STOP clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " TPM1_LPTPM_CLK_STOP ,TPM1_LPTPM_CLK clock status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " TPM1_LPTPM_CLK_SWEN ,TPM1_LPTPM_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " TPM1_LPTPM_CLK_HWEN ,TPM1_LPTPM_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x610000++0x03 line.long 0x00 "LPCG_LPIT_REGS,LPIT Clocks Register" rbitfld.long 0x00 7. " LPIT1_IPG_CLK_STOP ,LPIT1_IPG_CLK clock status" "Not stopped,Stopped" bitfld.long 0x00 5. " LPIT1_IPG_CLK_SWEN ,LPIT1_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " LPIT1_IPG_CLK_HWEN ,LPIT1_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " LPIT_IPG_PER_CLK_STOP ,LPIT_IPG_PER_CLK clock status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " LPIT_IPG_PER_CLK_SWEN ,LPIT_IPG_PER_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " LPIT_IPG_PER_CLK_HWEN ,LPIT_IPG_PER_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x620000++0x03 line.long 0x00 "LPCG_LPUART_REGS,LPUART Clocks Register" rbitfld.long 0x00 7. " LPUART1_IPG_CLK_STOP ,LPUART1_IPG_CLK clock status" "Not stopped,Stopped" bitfld.long 0x00 5. " LPUART1_IPG_CLK_SWEN ,LPUART1_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " LPUART1_IPG_CLK_HWEN ,LPUART1_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " LPUART1_LPUART_BAUD_CLK_STOP ,LPUART1_LPUART_BAUD_CLK clock status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " LPUART1_LPUART_BAUD_CLK_SWEN ,LPUART1_LPUART_BAUD_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " LPUART1_LPUART_BAUD_CLK_HWEN ,LPUART1_LPUART_BAUD_CLK clock HW signal treatment" "Ignored,Automatically gated" group.long 0x630000++0x03 line.long 0x00 "LPCG_LPI2C_REGS,LPI2C Clocks Register" rbitfld.long 0x00 7. " LPI2C1_IPG_CLK_STOP ,LPI2C1_IPG_CLK clock status" "Not stopped,Stopped" bitfld.long 0x00 5. " LPI2C1_IPG_CLK_SWEN ,LPI2C1_IPG_CLK clock enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " LPI2C1_IPG_CLK_HWEN ,LPI2C1_IPG_CLK clock HW signal treatment" "Ignored,Automatically gated" rbitfld.long 0x00 3. " LPI2C1_LPI2C_CLK_STOP ,LPI2C1_LPI2C_CLK clock status" "Not stopped,Stopped" newline bitfld.long 0x00 1. " LPI2C1_LPI2C_CLK_SWEN ,LPI2C1_LPI2C_CLK clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " LPI2C1_LPI2C_CLK_HWEN ,LPI2C1_LPI2C_CLK clock HW signal treatment" "Ignored,Automatically gated" width 0x0B tree.end endif tree.end ; tree "IOMUX" ; base ad:0x00 ; %include imx8x/iomuxd.ph ; tree.end tree.open "DRAM (DRAM Subsystem)" tree "DRC_PERF_MON (DDR Performance Monitor)" base ad:0x5C020000 width 15. group.long 0x0++0x03 line.long 0x00 "COUNTER0_CTRL,Counter 0 Control Register" bitfld.long 0x00 2. " COUNTER0_ENABLE ,Counter 0 enable" "Disabled,Enabled" bitfld.long 0x00 1. " COUNTER0_CLEAR ,Counter 0 clear" "No effect,Cleared" rbitfld.long 0x00 0. " COUNTER0_OVRFL ,Counter 0 overflow" "No overflow,Overflow" group.long 0x4++0x03 line.long 0x00 "COUNTER1_CTRL,Counter 1 Control Register" bitfld.long 0x00 2. " COUNTER1_ENABLE ,Counter 1 enable" "Disabled,Enabled" bitfld.long 0x00 1. " COUNTER1_CLEAR ,Counter 1 clear" "No effect,Cleared" rbitfld.long 0x00 0. " COUNTER1_OVRFL ,Counter 1 overflow" "No overflow,Overflow" hexmask.long.byte 0x00 16.--23. 1. " COUNTER1_CP ,Counter 1 counter parameter" hexmask.long.byte 0x00 24.--31. 1. " COUNTER1_CSV ,Counter 1 count value select" group.long 0x8++0x03 line.long 0x00 "COUNTER2_CTRL,Counter 2 Control Register" bitfld.long 0x00 2. " COUNTER2_ENABLE ,Counter 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " COUNTER2_CLEAR ,Counter 2 clear" "No effect,Cleared" rbitfld.long 0x00 0. " COUNTER2_OVRFL ,Counter 2 overflow" "No overflow,Overflow" hexmask.long.byte 0x00 16.--23. 1. " COUNTER2_CP ,Counter 2 counter parameter" hexmask.long.byte 0x00 24.--31. 1. " COUNTER2_CSV ,Counter 2 count value select" group.long 0xC++0x03 line.long 0x00 "COUNTER3_CTRL,Counter 3 Control Register" bitfld.long 0x00 2. " COUNTER3_ENABLE ,Counter 3 enable" "Disabled,Enabled" bitfld.long 0x00 1. " COUNTER3_CLEAR ,Counter 3 clear" "No effect,Cleared" rbitfld.long 0x00 0. " COUNTER3_OVRFL ,Counter 3 overflow" "No overflow,Overflow" hexmask.long.byte 0x00 16.--23. 1. " COUNTER3_CP ,Counter 3 counter parameter" hexmask.long.byte 0x00 24.--31. 1. " COUNTER3_CSV ,Counter 3 count value select" group.long 0x20++0x03 line.long 0x00 "COUNTER0_DATA,Counter 0 Data Register" group.long 0x24++0x03 line.long 0x00 "COUNTER1_DATA,Counter 1 Data Register" group.long 0x28++0x03 line.long 0x00 "COUNTER2_DATA,Counter 2 Data Register" group.long 0x2C++0x03 line.long 0x00 "COUNTER3_DATA,Counter 3 Data Register" if (((per.l(ad:0x5C020000+0x40))&0x01)==0x01) group.long 0x40++0x03 line.long 0x00 "MRR0_DATA,MRR0 Data Register" rbitfld.long 0x00 3. " MRR0_VALID_OUT ,MRR0 data valid" "Not valid,Valid" bitfld.long 0x00 2. " MRR0_VALID_CLR ,MRR0 valid clear" "No effect,Cleared" bitfld.long 0x00 1. " MRR0_MODE_SEL ,MRR0 mode selection" ",Serial mode" newline bitfld.long 0x00 0. " MRR0_DDR_SEL ,MRR0 DDR selection" ",LPDDR3/4" else group.long 0x40++0x03 line.long 0x00 "MRR0_DATA,MRR0 Data Register" rbitfld.long 0x00 3. " MRR0_VALID_OUT ,MRR0 data valid" "Not valid,Valid" bitfld.long 0x00 2. " MRR0_VALID_CLR ,MRR0 valid clear" "No effect,Cleared" newline bitfld.long 0x00 0. " MRR0_DDR_SEL ,MRR0 DDR selection" ",LPDDR3/4" endif group.long 0x44++0x03 line.long 0x00 "MRR1_DATA,MRR1 Data Register" width 0x0B tree.end tree "DDRC0_0 (DDR Controller)" base ad:0x5C300000 width 18. group.long 0x00++0x03 line.long 0x00 "MSTR,Master Register" bitfld.long 0x00 30.--31. " DEVICE_CONFIG ,Indicates the configuration of the device used in the system" "x4,x8,x16,x32" bitfld.long 0x00 29. " FREQUENCY_MODE ,Choose which registers are used" "Original,Shadow" newline bitfld.long 0x00 24.--25. " ACTIVE_RANKS ,Only present for multi-rank configurations" ",One rank,,Two rank" bitfld.long 0x00 22. " FREQUENCY_RATIO ,Selects the frequency ratio" "1:2 mode,1:1 mode" newline bitfld.long 0x00 16.--19. " BURST_RDWR ,Controls the burst size used to access the SDRAM" ",2,4,,8,,,,16,?..." bitfld.long 0x00 15. " DLL_OFF_MODE ,Indicates whether the DDRC and DRAM have to be put in DLL-off mode" "On mode,Off mode" newline bitfld.long 0x00 12.--13. " DATA_BUS_WIDTH ,Selects proportion of DQ bus width that is used by the SDRAM" "Full,Half,Quarter,?..." bitfld.long 0x00 11. " GEARDOWN_MODE ,DRAM mode" "Normal,Geardown" newline bitfld.long 0x00 10. " EN_2T_TIMING_MODE ,Enable 2T timing" "Disabled,Enabled" bitfld.long 0x00 9. " BURSTCHOP ,Burst-chop in DDR3/DDR4" "Disabled,Enabled" newline bitfld.long 0x00 5. " LPDDR4 ,Select LPDDR4 SDRAM" "Non-LPDDR4,LPDDR4" bitfld.long 0x00 3. " LPDDR3 ,Select LPDDR3 SDRAM" "Non-LPDDR3,LPDDR3" newline bitfld.long 0x00 2. " LPDDR2 ,Select LPDDR2 SDRAM" "Non-LPDDR2,LPDDR2" bitfld.long 0x00 0. " DDR3 ,Select DDR3 SDRAM" "Non-DDR3,DDR3" if (((per.l(ad:0x5C300000))&0x20)==0x20) rgroup.long 0x04++0x03 line.long 0x00 "STAT,Operating Mode Status Register" bitfld.long 0x00 8.--9. " SELFREF_STATE ,Self refresh state" "No self refresh,Self refresh 1,Self refresh power down,Self refresh" bitfld.long 0x00 4.--5. " SELFREF_TYPE ,SR-powerdown type" "Not in SR-powerdown,,Caused not only by automatic SR control,Caused only by automatic SR control" newline bitfld.long 0x00 0.--2. " OPERATING_MODE ,Operating mode" "Init,Normal,Power-down,Self refresh power-down,?..." elif (((per.l(ad:0x5C300000))&0x10)==0x10) rgroup.long 0x04++0x03 line.long 0x00 "STAT,Operating Mode Status Register" bitfld.long 0x00 8.--9. " SELFREF_STATE ,Self refresh state" "No self refresh,Self refresh 1,Self refresh power down,Self refresh" bitfld.long 0x00 4.--5. " SELFREF_TYPE ,Self refresh type" "Not in self refresh,,Caused not only by automatic SR control,Caused only by automatic SR control" newline bitfld.long 0x00 0.--2. " OPERATING_MODE ,Operating mode" "Init,Normal,Power-down,Self refresh,Deep power-down,Deep power-down,Deep power-down,Deep power-down" else rgroup.long 0x04++0x03 line.long 0x00 "STAT,Operating Mode Status Register" bitfld.long 0x00 8.--9. " SELFREF_STATE ,Self refresh state" "No self refresh,Self refresh 1,Self refresh power down,Self refresh" bitfld.long 0x00 4.--5. " SELFREF_TYPE ,Self refresh type" "Not in self refresh,,Caused not only by automatic SR control,Caused only by automatic SR control" newline bitfld.long 0x00 0.--1. " OPERATING_MODE ,Operating mode" "Init,Normal,Power-down,Self refresh" endif group.long 0x08++0x0F line.long 0x00 "MSTR1,Operating Mode Status Register 1" bitfld.long 0x00 16. " ALT_ADDRMAP_EN ,Enable alternative address map" "Disabled,Enabled" bitfld.long 0x00 1. " RANK_TMGREG_SEL[1] ,Indicates which register set is used for each rank" "Disabled,Enabled" newline bitfld.long 0x00 0. " [0] ,Indicates which register set is used for each rank" "Disabled,Enabled" line.long 0x04 "MRCTRL3,Operating Mode Status Register 3" bitfld.long 0x04 0.--1. " MR_RANK_SEL ,Controls which rank is accessed by MRCTRL0.mr_wr" "0,1,2,3" line.long 0x08 "MRCTRL0,Mode Register Read/Write Control Register 0" bitfld.long 0x08 31. " MR_WR ,Triggers a mode register read or write operation" "Not Triggered,Triggered" bitfld.long 0x08 30. " PBA_MODE ,Indicates whether PBA access is executed" "Not executed,Executed" newline bitfld.long 0x08 12.--15. " MR_ADDR ,Address of the mode register that is to be written to" "MR0,MR1,MR2,MR3,MR4,MR5,MR6,MR7,?..." bitfld.long 0x08 4.--5. " MR_RANK ,Controls which ranks are accessed by MRCTRL0.MR_WR" "0,1,2,3" newline bitfld.long 0x08 3. " SW_INIT_INT ,Indicates whether Software intervention is allowed" "Not allowed,Allowed" bitfld.long 0x08 2. " PDA_EN ,Indicates whether the mode register operation is MRS in PDA mode" "MRS,MRS in per DRAM addressability" newline bitfld.long 0x08 1. " MPR_EN ,Indicates whether the mode register operation is MRS or WR/RD for MPR" "MRS,WR/RD for MPR" bitfld.long 0x08 0. " MR_TYPE ,Indicates whether the mode register operation is read or write" "Write,Read" line.long 0x0C "MRCTRL1,Mode Register Read/Write Control Register 1" hexmask.long.tbyte 0x0C 0.--17. 1. " MR_DATA ,Mode register write data" rgroup.long 0x18++0x03 line.long 0x00 "MRSTAT,Mode Register Read/Write Status Register" bitfld.long 0x00 8. " PDA_DONE ,The SoC core may initiate a MR write operation in PDA/PBA mod" "In progress,Completed" bitfld.long 0x00 0. " MR_WR_BUSY ,The SoC core may initiate a MR write operation" "SoC core can initiate write operation,Write operation in progress" group.long 0x1C++0x03 line.long 0x00 "MRCTRL2,Mode Register Read/Write Control Register 2" if (((per.l(ad:0x5C300000))&0x20)==0x20) group.long 0x20++0x07 line.long 0x00 "DERATEEN,Temperature Derate Enable Register" bitfld.long 0x00 8.--9. " RC_DERATE_VALUE ,Derate value of tRC for LPDDR4" "+1,+2,+3,+4" bitfld.long 0x00 4.--7. " DERATE_BYTE ,Indicates which byte of the MRR data is used for derating" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1. " DERATE_VALUE ,Derate value" "+1,+2" bitfld.long 0x00 0. " DERATE_ENABLE ,Enables derating" "Disabled,Enabled" line.long 0x04 "DERATEINT,Temperature Derate Interval Register" else hgroup.long 0x20++0x03 hide.long 0x00 "DERATEEN,Temperature Derate Enable Register" hgroup.long 0x24++0x03 hide.long 0x00 "DERATEINT,Temperature Derate Interval Register" endif group.long 0x30++0x0B line.long 0x00 "PWRCTL,Low Power Control Register" bitfld.long 0x00 6. " STAY_IN_SELFREF ,Transition from Self refresh state" "Allow,Prohibit" bitfld.long 0x00 5. " SELFREF_SW ,Software entry transition to/from Self-refresh" "Exited,Entered" newline bitfld.long 0x00 4. " MPSM_EN ,DDRC maximum power saving mode" "Disabled,Enabled" bitfld.long 0x00 3. " EN_DFI_DRAM_CLK_DISABLE ,Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM" "No,Yes" newline bitfld.long 0x00 2. " DEEPPOWERDOWN_EN ,Enable for deep power-down" "Disabled,Enabled" bitfld.long 0x00 1. " POWERDOWN_EN ,Enable for power-down" "Disabled,Enabled" newline bitfld.long 0x00 0. " SELFREF_EN ,Enable for self refresh" "Disabled,Enabled" line.long 0x04 "PWRTMG,Low Power Timing Register" hexmask.long.byte 0x04 16.--23. 1. " SELFREF_TO_X32 ,SELFREF_TO_X32" hexmask.long.byte 0x04 8.--15. 1. " T_DPD_X4096 ,Minimum deep power-down time" newline bitfld.long 0x04 0.--4. " POWERDOWN_TO_X32 ,After this many clocks of NOP or deselect the DDRC automatically puts the SDRAM into power-down" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "HWLPCTL,Hardware Low Power Control Register" hexmask.long.word 0x08 16.--27. 1. " HW_LP_IDLE_X32 ,Hardware idle period" bitfld.long 0x08 1. " HW_LP_EXIT_IDLE_EN ,Enable for exit from the automatic clock stop automatic power down or automatic self-refresh modes" "Disabled,Enabled" newline bitfld.long 0x08 0. " HW_LP_EN ,Enable for hardware low power interface" "Disabled,Enabled" if (((per.l(ad:0x5C300000))&0x20)==0x20) group.long 0x50++0x03 line.long 0x00 "RFSHCTL0,Refresh Control Register 0" bitfld.long 0x00 20.--23. " REFRESH_MARGIN ,Threshold value in number of clock cycles before the critical refresh or page timer expires" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--16. " REFRESH_TO_X32 ,Speculative refreshes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4.--8. " REFRESH_BURST ,Number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute" "1 refresh,2 refresh,3 refresh,4 refresh,5 refresh,6 refresh,7 refresh,8 refresh,9 refresh,10 refresh,11 refresh,12 refresh,13 refresh,14 refresh,15 refresh,16 refresh,17 refresh,18 refresh,19 refresh,20 refresh,21 refresh,22 refresh,23 refresh,24 refresh,25 refresh,26 refresh,27 refresh,28 refresh,29 refresh,30 refresh,31 refresh,32 refresh" bitfld.long 0x00 2. " PER_BANK_REFRESH ,Allows traffic to flow to other banks" "All bank refresh,Per bank refresh" else group.long 0x50++0x03 line.long 0x00 "RFSHCTL0,Refresh Control Register 0" bitfld.long 0x00 20.--23. " REFRESH_MARGIN ,Threshold value in number of clock cycles before the critical refresh or page timer expires" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--16. " REFRESH_TO_X32 ,Speculative refreshes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4.--8. " REFRESH_BURST ,Number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute" "1 refresh,2 refresh,3 refresh,4 refresh,5 refresh,6 refresh,7 refresh,8 refresh,9 refresh,10 refresh,11 refresh,12 refresh,13 refresh,14 refresh,15 refresh,16 refresh,17 refresh,18 refresh,19 refresh,20 refresh,21 refresh,22 refresh,23 refresh,24 refresh,25 refresh,26 refresh,27 refresh,28 refresh,29 refresh,30 refresh,31 refresh,32 refresh" endif group.long 0x54++0x03 line.long 0x00 "RFSHCTL1,Refresh Control Register 1" hexmask.long.word 0x00 16.--27. 1. " REFRESH_TIMER1_START_VALUE_X32 ,Refresh timer start for rank 1" hexmask.long.word 0x00 0.--11. 1. " REFRESH_TIMER0_START_VALUE_X32 ,Refresh timer start for rank 0" group.long 0x60++0x07 line.long 0x00 "RFSHCTL3,Refresh Control Register 3" bitfld.long 0x00 4.--6. " REFRESH_MODE ,Fine granularity refresh mode" "Fixed,Fixed 2x,Fixed x4,,,Enabled on the fly x2,Enabled on the fly x4,?..." bitfld.long 0x00 1. " REFRESH_UPDATE_LEVEL ,Indicates that the refresh Register(S) have been updated" "0,1" newline bitfld.long 0x00 0. " DIS_AUTO_REFRESH ,Disables auto-refresh generated by the DDRC" "No,Yes" line.long 0x04 "RFSHTMG,Refresh Timing Register" hexmask.long.word 0x04 16.--27. 1. " T_RFC_NOM_X32 ,Average time interval between refreshes per rank" hexmask.long.word 0x04 0.--9. 1. " T_RFC_MIN ,Minimum time from refresh to refresh or activate" group.long 0xD0++0x03 line.long 0x00 "INIT0,SDRAM Initialization Register 0" bitfld.long 0x00 30.--31. " SKIP_DRAM_INIT ,If lower bit is enabled the SDRAM initialization routine is skipped" "Run after power-up,Skipped after power-up,Run after power-up,Skipped after power-up" hexmask.long.word 0x00 16.--25. 1. " POST_CKE_X1024 ,Cycles to wait after driving CKE high to start the SDRAM initialization sequence" newline hexmask.long.word 0x00 0.--11. 1. " PRE_CKE_X1024 ,Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence" if ((((per.l(ad:0x5C300000))&0x20)==0x20)||(((per.l(ad:0x5C300000))&0x01)==0x01)) group.long 0xD4++0x03 line.long 0x00 "INIT1,SDRAM Initialization Register 1" hexmask.long.word 0x00 16.--24. 1. " DRAM_RSTN_X1024 ,Number of cycles to assert SDRAM reset signal during init sequence" bitfld.long 0x00 0.--3. " PRE_OCD_X32 ,Wait period before driving the OCD complete command to SDRAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xD4++0x03 line.long 0x00 "INIT1,SDRAM Initialization Register 1" bitfld.long 0x00 0.--3. " PRE_OCD_X32 ,Wait period before driving the OCD complete command to SDRAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hgroup.long 0xD8++0x03 hide.long 0x00 "INIT2,SDRAM Initialization Register 2" group.long 0xDC++0x07 line.long 0x00 "INIT3,SDRAM Initialization Register 3" hexmask.long.word 0x00 16.--31. 1. " MR ,Value write to MR register" hexmask.long.word 0x00 0.--15. 1. " EMR ,Value write to EMR register" line.long 0x04 "INIT4,SDRAM Initialization Register 4" hexmask.long.word 0x04 16.--31. 1. " EMR2 ,Value write to EMR2 register" hexmask.long.word 0x04 0.--15. 1. " EMR3 ,Value write to EMR3 register" if (((per.l(ad:0x5C300000))&0x01)==0x01) group.long 0xE4++0x03 line.long 0x00 "INIT5,SDRAM Initialization Register 5" hexmask.long.byte 0x00 16.--23. 1. " DEV_ZQINIT_X32 ,ZQ initial calibration" hexmask.long.word 0x00 0.--9. 1. " MAX_AUTO_INIT_X_1024 ,Maximum duration of the auto initialization tINIT5" else hgroup.long 0xE4++0x03 hide.long 0x00 "INIT5,SDRAM Initialization Register 5" endif hgroup.long 0xE8++0x03 hide.long 0x00 "INIT6,SDRAM Initialization Register 6" hgroup.long 0xEC++0x03 hide.long 0x00 "INIT7,SDRAM Initialization Register 7" if (((per.l(ad:0x5C300000))&0x10)==0x10) group.long 0xF0++0x03 line.long 0x00 "DIMMCTL,DIMM Control Register" bitfld.long 0x00 6. " LRDIMM_BCOM_CMD_PROT ,Protects the timing restrictions" "0,1" bitfld.long 0x00 5. " DIMM_DIS_BG_MIRRORING ,Disabling address mirroring for BG bits" "Swapped,Not swapped" newline bitfld.long 0x00 4. " MRS_BG1_EN ,Enable for BG1 bit of MRS command" "Disabled,Enabled" bitfld.long 0x00 3. " MRS_A17_EN ,Enable for A17 bit of MRS command" "Disabled,Enabled" newline bitfld.long 0x00 2. " DIMM_OUTPUT_INV_EN ,Output inversion enable" "Disabled,Enabled" bitfld.long 0x00 1. " DIMM_ADDR_MIRR_EN ,Address mirroring enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DIMM_STAGGER_CS_EN ,Staggering enable for multi-rank accesses" "Disabled,Enabled" elif (((per.l(ad:0x5C300000))&0x20)==0x20) group.long 0xF0++0x03 line.long 0x00 "DIMMCTL,DIMM Control Register" bitfld.long 0x00 6. " LRDIMM_BCOM_CMD_PROT ,Protects the timing restrictions" "0,1" bitfld.long 0x00 5. " DIMM_DIS_BG_MIRRORING ,Disabling address mirroring for BG bits" "Swapped,Not swapped" newline bitfld.long 0x00 4. " MRS_BG1_EN ,Enable for BG1 bit of MRS command" "Disabled,Enabled" bitfld.long 0x00 3. " MRS_A17_EN ,Enable for A17 bit of MRS command" "Disabled,Enabled" newline bitfld.long 0x00 2. " DIMM_OUTPUT_INV_EN ,Output inversion enable" "Disabled,Enabled" else group.long 0xF0++0x03 line.long 0x00 "DIMMCTL,DIMM Control Register" bitfld.long 0x00 6. " LRDIMM_BCOM_CMD_PROT ,Protects the timing restrictions" "0,1" bitfld.long 0x00 5. " DIMM_DIS_BG_MIRRORING ,Disabling address mirroring for BG bits" "Swapped,Not swapped" newline bitfld.long 0x00 4. " MRS_BG1_EN ,Enable for BG1 bit of MRS command" "Disabled,Enabled" bitfld.long 0x00 3. " MRS_A17_EN ,Enable for A17 bit of MRS command" "Disabled,Enabled" endif group.long 0xF4++0x03 line.long 0x00 "RANKCTL,Rank Control Register" bitfld.long 0x00 8.--11. " DIFF_RANK_WR_GAP ,Only present for multi-rank configurations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DIFF_RANK_RD_GAP ,Only present for multi-rank configurations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " MAX_RANK_RD ,Only present for multi-rank configurations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x100++0x0B line.long 0x00 "DRAMTMG0,SDRAM Timing Register 0" hexmask.long.byte 0x00 24.--30. 1. " WR2PRE ,Minimum time between write and precharge to same bank" bitfld.long 0x00 16.--21. " T_FAW ,TFAW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x00 8.--14. 1. " T_RAS_MAX ,Maximum time between activate and precharge to the same bank" bitfld.long 0x00 0.--5. " T_RAS_MIN ,Minimum time between activate and precharge to the same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DRAMTMG1,SDRAM Timing Register 1" bitfld.long 0x04 16.--20. " T_XP ,Minimum time after power-down exit to any operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--13. " RD2PRE ,Minimum time from read to precharge of same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x04 0.--6. 1. " T_RC ,Minimum time between activates to same bank" line.long 0x08 "DRAMTMG2,SDRAM Timing Register 2" bitfld.long 0x08 24.--29. " WRITE_LATENCY ,Time from write command to write data on SDRAM interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " READ_LATENCY ,Time from read command to read data on SDRAM interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " RD2WR ,Minimum time from read command to write command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " WR2RD ,Minimum time from write command to read command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0x5C300000))&0x20)==0x20) group.long 0x10C++0x03 line.long 0x00 "DRAMTMG3,SDRAM Timing Register 3" hexmask.long.word 0x00 20.--29. 1. " T_MRW ,Time to wait after a mode register write or read" bitfld.long 0x00 12.--17. " T_MRD ,Cycles between loadmode commands" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.l(ad:0x5C300000))&0x01)==0x01) group.long 0x10C++0x03 line.long 0x00 "DRAMTMG3,SDRAM Timing Register 3" bitfld.long 0x00 12.--17. " T_MRD ,Cycles between loadmode commands" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 0.--9. 1. " T_MOD ,Cycles between loadmode command and following non-load mode command" else group.long 0x10C++0x03 line.long 0x00 "DRAMTMG3,SDRAM Timing Register 3" bitfld.long 0x00 12.--17. " T_MRD ,Cycles between loadmode commands" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x110++0x07 line.long 0x00 "DRAMTMG4,SDRAM Timing Register 4" bitfld.long 0x00 24.--28. " T_RCD ,Minimum time from activate to read or write command to same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--19. " T_CCD ,Minimum time between two reads or two writes for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " T_RRD ,Minimum time between activates from bank a to bank b for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " T_RP ,Minimum time from precharge to activate of same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DRAMTMG5,SDRAM Timing Register5" bitfld.long 0x04 24.--27. " T_CKSRX ,Time before self refresh exit that CK is maintained as a valid clock before issuing SRX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " T_CKSRE ,Time after self refresh down entry that CK is maintained as a valid clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--13. " T_CKESR ,Minimum CKE low width for self refresh entry to exit timing in memory clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--4. " T_CKE ,Minimum number of cycles of CKE HIGH / LOW during power-down and self refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x5C300000))&0x20)==0x20) group.long 0x118++0x07 line.long 0x00 "DRAMTMG6,SDRAM Timing Register 6" bitfld.long 0x00 0.--3. " T_CKCSX ,Time before clock stop exit that CK is maintained as a valid clock before issuing clock stop exit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DRAMTMG7,SDRAM Timing Register 7" bitfld.long 0x04 8.--11. " T_CKPDE ,Time after power down entry that CK is maintained as a valid clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " T_CKPDX ,Time before power down exit that CK is maintained as a valid clock before issuing PDX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else hgroup.long 0x118++0x03 hide.long 0x00 "DRAMTMG6,SDRAM Timing Register 6" hgroup.long 0x11C++0x03 hide.long 0x00 "DRAMTMG7,SDRAM Timing Register 7" endif if (((per.l(ad:0x5C300000))&0x01)==0x01) group.long 0x120++0x03 line.long 0x00 "DRAMTMG8,SDRAM Timing Register 8" hexmask.long.byte 0x00 24.--30. 1. " T_XS_FAST_X32 ,Exit Self refresh to ZQC ZQCS and MRS" hexmask.long.byte 0x00 16.--22. 1. " T_XS_ABORT_X32 ,Exit self refresh to commands not requiring a locked DLL in self refresh abort" newline hexmask.long.byte 0x00 8.--14. 1. " T_XS_DLL_X32 ,Exit self refresh to commands requiring a locked DLL" hexmask.long.byte 0x00 0.--6. 1. " T_XS_X32 ,Exit self refresh to commands not requiring a locked DLL" else group.long 0x120++0x03 line.long 0x00 "DRAMTMG8,SDRAM Timing Register 8" hexmask.long.byte 0x00 24.--30. 1. " T_XS_FAST_X32 ,Exit self refresh to ZQCL ZQCS and MRS" hexmask.long.byte 0x00 16.--22. 1. " T_XS_ABORT_X32 ,Exit Self Refresh to commands not requiring a locked DLL in self refresh abort" endif hgroup.long 0x124++0x03 hide.long 0x00 "DRAMTMG9,SDRAM Timing Register 9" group.long 0x128++0x03 line.long 0x00 "DRAMTMG10,SDRAM Timing Register 10" bitfld.long 0x00 16.--20. " T_SYNC_GEAR ,Indicates the time between MRS command and the sync pulse time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " T_CMD_GEAR ,Sync pulse to first valid command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 2.--3. " T_GEAR_SETUP ,Geardown setup time" ",1,2,3" bitfld.long 0x00 0.--1. " T_GEAR_HOLD ,Geardown hold time" ",1,2,3" hgroup.long 0x12C++0x03 hide.long 0x00 "DRAMTMG11,SDRAM Timing Register 11" group.long 0x130++0x07 line.long 0x00 "DRAMTMG12,SDRAM Timing Register 12" bitfld.long 0x00 16.--17. " T_CMDCKE ,Delay from valid command to CKE input LOW" "0,1,2,3" bitfld.long 0x00 8.--11. " T_CKEHCMD ,Valid command requirement after CKE input HIGH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--4. " T_MRD_PDA ,This is the mode register set command cycle time in PDA mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DRAMTMG13,SDRAM Timing Register 13" hexmask.long.byte 0x04 24.--30. 1. " ODTLOFF ,This is the latency from CAS-2 command to tODToff reference" bitfld.long 0x04 16.--21. " T_CCD_MW ,This is the minimum time from write or masked write to masked write command for same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 0.--2. " T_PPD ,This is the minimum time from precharge to precharge command" "0,1,2,3,4,5,6,7" if (((per.l(ad:0x5C300000))&0x20)==0x20) group.long 0x138++0x03 line.long 0x00 "DRAMTMG14,SDRAM Timing Register 14" hexmask.long.word 0x00 0.--11. 1. " T_XSR ,Exit self refresh to any command" else hgroup.long 0x138++0x03 hide.long 0x00 "DRAMTMG14,SDRAM Timing Register 14" endif group.long 0x13C++0x03 line.long 0x00 "DRAMTMG15,SDRAM Timing Register 15" bitfld.long 0x00 31. " EN_DFI_LP_T_STAB ,Enable DFI tSTAB" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " T_STAB_X32 ,Stabilization time" group.long 0x180++0x03 line.long 0x00 "ZQCTL0,ZQ Control Register 0" bitfld.long 0x00 31. " DIS_AUTO_ZQ ,Disable auto ZQCS/MPC" "No,Yes" bitfld.long 0x00 30. " DIS_SRX_ZQCL ,Disable ZQCL/MPC" "No,Yes" newline bitfld.long 0x00 29. " ZQ_RESISTOR_SHARED ,ZQ resistor sharing" "Not shared,Shared" newline hexmask.long.word 0x00 16.--26. 1. " T_ZQ_LONG_NOP ,Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to SDRAM" hexmask.long.word 0x00 0.--9. 1. " T_ZQ_SHORT_NOP ,Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to SDRAM" if (((per.l(ad:0x5C300000))&0x20)==0x20) group.long 0x184++0x03 line.long 0x00 "ZQCTL1,ZQ Control Register 1" hexmask.long.word 0x00 20.--29. 1. " T_ZQ_RESET_NOP ,Number of cycles of NOP required after a ZQReset (ZQ calibration reset) command is issued to SDRAM" hexmask.long.tbyte 0x00 0.--19. 1. " T_ZQ_SHORT_INTERVAL_X1024 ,Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands" elif ((((per.l(ad:0x5C300000))&0x01)==0x01)) group.long 0x184++0x03 line.long 0x00 "ZQCTL1,ZQ Control Register 1" hexmask.long.tbyte 0x00 0.--19. 1. " T_ZQ_SHORT_INTERVAL_X1024 ,Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands" else hgroup.long 0x184++0x03 hide.long 0x00 "ZQCTL1,ZQ Control Register 1" endif if (((per.l(ad:0x5C300000))&0x20)==0x20) group.long 0x188++0x03 line.long 0x00 "ZQCTL2,ZQ Control Register 2" bitfld.long 0x00 0. " ZQ_RESET ,Setting this register bit to 1 triggers a ZQ Reset operation" "Not triggered,Triggered" else hgroup.long 0x188++0x03 hide.long 0x00 "ZQCTL2,ZQ Control Register 2" endif rgroup.long 0x18C++0x03 line.long 0x00 "ZQSTAT,ZQ Status Register" bitfld.long 0x00 0. " ZQ_RESET_BUSY ,ZQ reset operation initialization by soc core" "Possibility of initialization,In progress" group.long 0x190++0x1B line.long 0x00 "DFITMG0,DFI Timing Register 0" bitfld.long 0x00 24.--28. " DFI_T_CTRL_DELAY ,Specifies the number of DFI clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 23. " DFI_RDDATA_USE_SDR ,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values" "HDR,SDR" newline hexmask.long.byte 0x00 16.--22. 1. " DFI_RDDATA_USE_SDR ,Time from the assertion of a read command on the DFI interface to the assertion of the DFI_RDDATA_EN signal" bitfld.long 0x00 15. " DFI_WRDATA_USE_SDR ,Selects whether value in DFITMG0.DFI_TPHY_WRLAT is in terms of SDR or HDR clock cycles" "HDR,SDR" newline bitfld.long 0x00 8.--13. " DFI_TPHY_WRDATA ,Specifies the number of clock cycles between when DFI_WRDATA_EN is asserted to when the associated write data is driven on the dfi_wrdata signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DFI_TPHY_WRLAT ,Number of clocks from the write command to write data enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DFITMG1,DFI Timing Register 1" bitfld.long 0x04 28.--31. " DFI_T_CMD_LAT ,Specifies the number of DFI PHY clock cycles" "0,,,3,4,5,6,,8,?..." bitfld.long 0x04 24.--25. " DFI_T_PARIN_LAT ,Number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven" "0,1,2,3" newline bitfld.long 0x04 16.--20. " DFI_T_WRDATA_DELAY ,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " DFI_T_DRAM_CLK_DISABLE ,Number of DFI clock cycles from the assertion of the DFI_DRAM_CLK_DISABLE signal on the DFI until the clock to the DRAM memory devices at the PHY-DRAM boundary maintains a low value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--4. " DFI_T_DRAM_CLK_ENABLE ,Specifies the number of DFI clock cycles from the de-assertion of the DFI_DRAM_CLK_DISABLE signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "DFILPCFG0,DFI Low Power Configuration Register 0" bitfld.long 0x08 24.--28. " DFI_TLP_RESP ,DFI_TLP_RESP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 20.--23. " DFI_LP_WAKEUP_DPD ,Value in DFI clock cycles to drive on dfi_lp_wakeup signal" "16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,262144,Unlimited" newline bitfld.long 0x08 16. " DFI_LP_EN_DPD ,Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit" "Disabled,Enabled" bitfld.long 0x08 12.--15. " DFI_LP_WAKEUP_SR ,Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered" "16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,262144,Unlimited" newline bitfld.long 0x08 8. " DFI_LP_EN_SR ,Enables DFI low power interface handshaking during self refresh entry/exit" "Disabled,Enabled" bitfld.long 0x08 4.--7. " DFI_LP_WAKEUP_PD ,Value to drive on dfi_lp_wakeup signal when Power Down mode is entered" "16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,262144,Unlimited" newline bitfld.long 0x08 0. " DFI_LP_EN_PD ,Enables DFI low power interface handshaking during power down entry/exit" "Disabled,Enabled" line.long 0x0C "DFILPCFG1,DFI Low Power Configuration Register 1" bitfld.long 0x0C 4.--7. " DFI_LP_WAKEUP_MPSM ,Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "DFIUPD0,DFI Update Register 0" bitfld.long 0x10 31. " DIS_AUTO_CTRLUPD ,Automatic dfi_ctrlupd_req generation by the DDRC" "No,Yes" bitfld.long 0x10 30. " DIS_AUTO_CTRLUPD_SRX ,Auto ctrlupd request generation" "No,Yes" newline bitfld.long 0x10 29. " CTRLUPD_PRE_SRX ,Selects dfi_ctrlupd_req requirements at SRX" "After SRX,Before SRX" hexmask.long.word 0x10 16.--25. 1. " DFI_T_CTRLUP_MAX ,Specifies the maximum number of clock cycles that the dfi_ctrlupd_req signal can assert" newline hexmask.long.word 0x10 0.--9. 1. " DFI_T_CTRLUP_MIN ,Specifies the minimum number of clock cycles that the dfi_ctrlupd_req signal must be asserted" line.long 0x14 "DFIUPD1,DFI Update Register 1" hexmask.long.byte 0x14 16.--23. 1. " DFI_T_CTRLUPD_INTERVAL_MIN_X1024 ,The minimum amount of time between DDRC initiated DFI update requests" hexmask.long.byte 0x14 0.--7. 1. " DFI_T_CTRLUPD_INTERVAL_MAX_X1024 ,The maximum amount of time between DDRC initiated DFI update requests" line.long 0x18 "DFIUPD2,DFI Update Register 2" bitfld.long 0x18 31. " DFI_PHYUPD_EN ,Enables the support for acknowledging PHY- initiated updates" "Disabled,Enabled" if (((per.l(ad:0x5C300000))&0x20)==0x20) group.long 0x1B0++0x03 line.long 0x00 "DFIMISC,DFI Miscellaneous Control Register" bitfld.long 0x00 8.--12. " DFI_FREQUENCY ,Indicates the operating frequency of the system" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " DFI_INIT_START ,PHY init start request signal" "Not started,Started" newline bitfld.long 0x00 4. " CTL_IDLE_EN ,Enables support of ctl_idle signal" "Disabled,Enabled" bitfld.long 0x00 2. " DFI_DATA_CS_POLARITY ,Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals" "Low,High" newline bitfld.long 0x00 1. " PHY_DBI_MODE ,DBI implemented in DDRC or PHY" "DDRC,PHY" bitfld.long 0x00 0. " DFI_INIT_COMPLETE_EN ,PHY initialization complete enable signal" "Disabled,Enabled" else group.long 0x1B0++0x03 line.long 0x00 "DFIMISC,DFI Miscellaneous Control Register" bitfld.long 0x00 8.--12. " DFI_FREQUENCY ,Indicates the operating frequency of the system" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " DFI_INIT_START ,PHY init start request signal" "Not started,Started" newline bitfld.long 0x00 4. " CTL_IDLE_EN ,Enables support of ctl_idle signal" "Disabled,Enabled" bitfld.long 0x00 2. " DFI_DATA_CS_POLARITY ,Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals" "Low,High" newline bitfld.long 0x00 0. " DFI_INIT_COMPLETE_EN ,PHY initialization complete enable signal" "Disabled,Enabled" endif group.long 0x1B4++0x07 line.long 0x00 "DFITMG2,DFI Timing Register 2" hexmask.long.byte 0x00 8.--14. 1. " DFI_TPHY_RDCSLAT ,Number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted" bitfld.long 0x00 0.--5. " DFI_TPHY_WRCSLAT ,Number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DFITMG3,DFI Timing Register 3" bitfld.long 0x04 0.--4. " DFI_T_GEARDOWN_DELAY ,Delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x1BC++0x03 line.long 0x00 "DFISTAT,DFI Status Register" bitfld.long 0x00 1. " DFI_LP_ACK ,Stores the value of the dfi_lp_ack input to the controller" "0,1" bitfld.long 0x00 0. " DFI_INIT_COMPLETE ,The status flag register which announces when the DFI initialization has been completed" "Not completed,Completed" group.long 0x1C0++0x03 line.long 0x00 "DBICTL,DM/DBI Control Register" bitfld.long 0x00 2. " RD_DBI_EN ,Read DBI enable signal in DDRC" "Disabled,Enabled" bitfld.long 0x00 1. " WR_DBI_EN ,Write DBI enable signal in DDRC" "Disabled,Enabled" newline bitfld.long 0x00 0. " DM_EN ,DM enable signal in DDRC" "Disabled,Enabled" group.long 0x200++0x23 line.long 0x00 "ADDRMAP0,Address Map Register 0" bitfld.long 0x00 0.--4. " ADDRMAP_CS_BIT0 ,Selects the HIF address bit used as rank address bit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,,,31" line.long 0x04 "ADDRMAP1,Address Map Register 1" bitfld.long 0x04 16.--20. " ADDRMAP_BANK_B2 ,Selects the HIF address bit used as bank address bit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " ADDRMAP_BANK_B1 ,Selects the HIF address bits used as bank address bit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--4. " ADDRMAP_BANK_B0 ,Selects the HIF address bits used as bank address bit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "ADDRMAP2,Address Map Register 2" bitfld.long 0x08 24.--27. " ADDRMAP_COL_B5 ,Selects the HIF address bit used as column address bit 5" "0,1,2,3,4,5,6,7,,,,,,,,15" bitfld.long 0x08 16.--19. " ADDRMAP_COL_B4 ,Selects the HIF address bit used as column address bit 4" "0,1,2,3,4,5,6,7,,,,,,,,15" newline bitfld.long 0x08 8.--11. " ADDRMAP_COL_B3 ,Selects the HIF address bit used as column address bit 3" "0,1,2,3,4,5,6,7,?..." bitfld.long 0x08 0.--3. " ADDRMAP_COL_B2 ,Selects the HIF address bit used as column address bit 2" "0,1,2,3,4,5,6,7,?..." line.long 0x0C "ADDRMAP3,Address Map Register 3" bitfld.long 0x0C 24.--27. " ADDRMAP_COL_B9 ,Selects the HIF address bit used as column address bit 9" "0,1,2,3,4,5,6,7,,,,,,,,15" bitfld.long 0x0C 16.--19. " ADDRMAP_COL_B8 ,Selects the HIF address bit used as column address bit 8" "0,1,2,3,4,5,6,7,,,,,,,,15" newline bitfld.long 0x0C 8.--11. " ADDRMAP_COL_B7 ,Selects the HIF address bit used as column address bit 7" "0,1,2,3,4,5,6,7,,,,,,,,15" bitfld.long 0x0C 0.--3. " ADDRMAP_COL_B6 ,Selects the HIF address bit used as column address bit 6" "0,1,2,3,4,5,6,7,,,,,,,,15" line.long 0x10 "ADDRMAP4,Address Map Register 4" bitfld.long 0x10 8.--11. " ADDRMAP_COL_B11 ,Selects the HIF address bit used as column address bit 13" "0,1,2,3,4,5,6,7,,,,,,,,15" bitfld.long 0x10 0.--3. " ADDRMAP_COL_B10 ,Selects the HIF address bit used as column address bit 11" "0,1,2,3,4,5,6,7,,,,,,,,15" line.long 0x14 "ADDRMAP5,Address Map Register 5" bitfld.long 0x14 24.--27. " ADDRMAP_ROW_B11 ,Selects the HIF address bit used as row address bit 11" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" bitfld.long 0x14 16.--19. " ADDRMAP_ROW_B2_10 ,Selects the HIF address bit used as row address bit 2 to 10" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" newline bitfld.long 0x14 8.--11. " ADDRMAP_ROW_B1 ,Selects the HIF address bits used as row address bit 1" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x14 0.--3. " ADDRMAP_ROW_B0 ,Selects the HIF address bits used as row address bit 0" "0,1,2,3,4,5,6,7,8,9,10,11,?..." line.long 0x18 "ADDRMAP6,Address Map Register 6" bitfld.long 0x18 24.--27. " ADDRMAP_ROW_B15 ,Selects the HIF address bit used as row address bit 15" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" bitfld.long 0x18 16.--19. " ADDRMAP_ROW_B14 ,Selects the HIF address bit used as row address bit 14" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" newline bitfld.long 0x18 8.--11. " ADDRMAP_ROW_B13 ,Selects the HIF address bit used as row address bit 13" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" bitfld.long 0x18 0.--3. " ADDRMAP_ROW_B12 ,Selects the HIF address bit used as row address bit 12" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" line.long 0x1C "ADDRMAP7,Address Map Register 7" bitfld.long 0x1C 8.--11. " ADDRMAP_ROW_B17 ,Selects the HIF address bit used as row address bit 17" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" bitfld.long 0x1C 0.--3. " ADDRMAP_ROW_B16 ,Selects the HIF address bit used as row address bit 16" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" line.long 0x20 "ADDRMAP8,Address Map Register 8" bitfld.long 0x20 8.--13. " ADDRMAP_BG_B1 ,Selects the HIF address bits used as bank group address bit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,63" bitfld.long 0x20 0.--4. " ADDRMAP_BG_B0 ,Selects the HIF address bits used as bank group address bit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x5C300000+0x214))&0xF0000)==0xF0000) group.long 0x224++0x0B line.long 0x00 "ADDRMAP9,Address Map Register 9" bitfld.long 0x00 24.--27. " ADDRMAP_ROW_B5 ,Selects the HIF address bits used as row address bit 5" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x00 16.--19. " ADDRMAP_ROW_B4 ,Selects the HIF address bits used as row address bit 4" "0,1,2,3,4,5,6,7,8,9,10,11,?..." newline bitfld.long 0x00 8.--11. " ADDRMAP_ROW_B3 ,Selects the HIF address bits used as row address bit 3" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x00 0.--3. " ADDRMAP_ROW_B2 ,Selects the HIF address bits used as row address bit 2" "0,1,2,3,4,5,6,7,8,9,10,11,?..." line.long 0x04 "ADDRMAP10,Address Map Register 10" bitfld.long 0x04 24.--27. " ADDRMAP_ROW_B9 ,Selects the HIF address bits used as row address bit 9" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" bitfld.long 0x04 16.--19. " ADDRMAP_ROW_B8 ,Selects the HIF address bits used as row address bit 8" "0,1,2,3,4,5,6,7,8,9,10,11,?..." newline bitfld.long 0x04 8.--11. " ADDRMAP_ROW_B7 ,Selects the HIF address bits used as row address bit 7" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x04 0.--3. " ADDRMAP_ROW_B6 ,Selects the HIF address bits used as row address bit 6" "0,1,2,3,4,5,6,7,8,9,10,11,?..." line.long 0x08 "ADDRMAP11,Address Map Register 11" bitfld.long 0x08 0.--3. " ADDRMAP_ROW_B10 ,Selects the HIF address bits used as row address bit 10" "0,1,2,3,4,5,6,7,8,9,10,11,?..." else hgroup.long 0x224++0x03 hide.long 0x00 "ADDRMAP9,Address Map Register 9" hgroup.long 0x228++0x03 hide.long 0x00 "ADDRMAP10,Address Map Register 10" hgroup.long 0x230++0x03 hide.long 0x00 "ADDRMAP11,Address Map Register 11" endif group.long 0x240++0x07 line.long 0x00 "ODTCFG,ODT configuration register" bitfld.long 0x00 24.--27. " WR_ODT_HOLD ,DFI PHY clock cycles to hold ODT for a write command" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " WR_ODT_DELAY ,Delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--11. " RD_ODT_HOLD ,DFI PHY clock cycles to hold ODT for a read command" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--6. " RD_ODT_DELAY ,Delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "ODTMAP,ODT/Rank Map Register" bitfld.long 0x04 13. " RANK1_RD_ODT[1] ,Indicates bit next to the LSB must be turned on during a read from rank 1" "Not occurred,Occurred" bitfld.long 0x04 12. " [0] ,Indicates LSB must be turned on during a read from rank 1" "Not occurred,Occurred" newline bitfld.long 0x04 9. " RANK1_WR_ODT[1] ,Indicates bit next to the LSB must be turned on during a write to rank 1" "Not occurred,Occurred" bitfld.long 0x04 8. " [0] ,Indicates LSB must be turned on during a write to rank 1" "Not occurred,Occurred" newline bitfld.long 0x04 5. " RANK0_RD_ODT[1] ,Indicates bit next to the LSB must be turned on during a read from rank 0" "0,1" bitfld.long 0x04 4. " [0] ,Indicates LSB must be turned on during a read from rank 0" "0,1" newline bitfld.long 0x04 1. " RANK0_WR_ODT[1] ,Indicates bit next to the LSB must be turned on during a write to rank 0" "0,1" bitfld.long 0x04 0. " [0] ,Indicates LSB must be turned on during a write to rank 0" "0,1" group.long 0x250++0x03 line.long 0x00 "SCHED,Scheduler Control Register" hexmask.long.byte 0x00 24.--30. 1. " RDWR_IDLE_GAP ,When the preferred transaction store is empty for these many clock cycles switch to the alternate transaction store if it is non-empty" bitfld.long 0x00 8.--12. " LPR_NUM_ENTRIES ,Number of entries in the low priority transaction store" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 2. " PAGECLOSE ,Provides a midway between open and close page policies" "Open page policy,Close page policy" bitfld.long 0x00 1. " PREFER_WRITE ,Bank selector prefers writes over reads" "Reads over writes,Writes over reads" newline bitfld.long 0x00 0. " FORCE_LOW_PRI_N ,Active low signal" "Not forced,Forced" if (((per.l(ad:0x5C300000+0x250))&0x04)==0x04) group.long 0x254++0x03 line.long 0x00 "SCHED1,Scheduler Control Register 1" hexmask.long.byte 0x00 0.--7. 1. " PAGECLOSE_TIMER ,Pageclose timer" else hgroup.long 0x254++0x03 hide.long 0x00 "SCHED1,Scheduler Control Register 1" endif group.long 0x25C++0x03 line.long 0x00 "PERFHPR1,High Priority Read CAM Register 1" hexmask.long.byte 0x00 24.--31. 1. " HPR_XACT_RUN_LENGTH ,Number of transactions that are serviced once the HPR queue goes critical" hexmask.long.word 0x00 0.--15. 1. " HPR_MAX_STARVE ,Number of DFI clocks that the HPR queue can be starved before it goes critical" group.long 0x264++0x03 line.long 0x00 "PERFLPR1,Low Priority Read CAM Register 1" hexmask.long.byte 0x00 24.--31. 1. " LPR_XACT_RUN_LENGTH ,Number of transactions that are serviced once the LPR queue goes critical" hexmask.long.word 0x00 0.--15. 1. " LPR_MAX_STARVE ,Number of DFI clocks that the LPR queue can be starved before it goes critical" group.long 0x26C++0x03 line.long 0x00 "PERFWR1,Write CAM Register 1" hexmask.long.byte 0x00 24.--31. 1. " W_XACT_RUN_LENGTH ,Number of transactions that are serviced once the WR queue goes critical" hexmask.long.word 0x00 0.--15. 1. " W_MAX_STARVE ,Number of DFI clocks that the WR queue can be starved before it goes critical" group.long 0x300++0x07 line.long 0x00 "DBG0,Debug Register 0" bitfld.long 0x00 4. " DIS_COLLISION_PAGE_OPT ,Auto-precharge enable" "Disabled,Enabled" bitfld.long 0x00 2. " DIS_ACT_BYPASS ,Disable bypass path for high priority read activates" "No,Yes" newline bitfld.long 0x00 1. " DIS_RD_BYPASS ,Disable bypass path for high priority read page hits" "No,Yes" bitfld.long 0x00 0. " DIS_WC ,Disable write combine" "No,Yes" line.long 0x04 "DBG1,Debug Register 1" bitfld.long 0x04 1. " DIS_HIF ,HIF disable" "No,Yes" bitfld.long 0x04 0. " DIS_DQ ,De-queue from the CAM disable" "No,Yes" rgroup.long 0x308++0x03 line.long 0x00 "DBGCAM,CAM Debug Register" bitfld.long 0x00 31. " DBG_STALL_RD ,Stall for read channel" "Not stalled,Stalled" bitfld.long 0x00 30. " DBG_STALL_WR ,Stall for write channel" "Not stalled,Stalled" newline bitfld.long 0x00 29. " WR_DATA_PIPELINE_EMPTY ,Indicates that the write data pipeline on the DFI interface is empty" "Not empty,Empty" bitfld.long 0x00 28. " RD_DATA_PIPELINE_EMPTY ,Indicates that the read data pipeline on the DFI interface is empty" "Not empty,Empty" newline bitfld.long 0x00 26. " DBG_WR_Q_EMPTY ,Indicates that all the write command queues and write data buffers inside DDRC are empty" "Not empty,Empty" bitfld.long 0x00 25. " DBG_RD_Q_EMPTY ,Indicates that all the read command queues and read data buffers inside DDRC are empty" "Not empty,Empty" newline bitfld.long 0x00 24. " DBG_STALL ,Stall" "Not stalled,Stalled" bitfld.long 0x00 16.--21. " DBG_W_Q_DEPTH ,Write queue depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " DBG_LPR_Q_DEPTH ,Low priority read queue depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DBG_HPR_Q_DEPTH ,High priority read queue depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x30C++0x03 line.long 0x00 "DBGCMD,Command Debug Register" bitfld.long 0x00 5. " CTRLUPD ,Indicates to the DDRC to issue a dfi_ctrlupd_req to the PHY" "Not issued,Issued" bitfld.long 0x00 4. " ZQ_CALIB_SHORT ,Indicates to the DDRC to issue a ZQCS command to the SDRAM" "No calibration,Calibration" newline bitfld.long 0x00 1. " RANK1_REFRESH ,Indicates to the DDRC to issue a refresh to rank 1" "No refresh,Refresh" bitfld.long 0x00 0. " RANK0_REFRESH ,Indicates to the DDRC to issue a refresh to rank 0" "No refresh,Refresh" rgroup.long 0x310++0x03 line.long 0x00 "DBGSTAT,Status Debug Register" bitfld.long 0x00 5. " CTRLUPD_BUSY ,Ctrlupd operation busy" "Not busy,Busy" bitfld.long 0x00 4. " ZQ_CALIB_SHORT_BUSY ,ZQCS operation busy" "Not busy,Busy" newline bitfld.long 0x00 1. " RANK1_REFRESH_BUSY ,Rank1_refresh operation busy" "Not busy,Busy" bitfld.long 0x00 0. " RANK0_REFRESH_BUSY ,Rank0_refresh operation busy" "Not busy,Busy" group.long 0x320++0x03 line.long 0x00 "SWCTL,Software Register Programming Control Enable" bitfld.long 0x00 0. " SW_DONE ,Enable quasi dynamic register programming outside reset" "Disabled,Enabled" rgroup.long 0x324++0x03 line.long 0x00 "SWSTAT,Software Register Programming Control Status" bitfld.long 0x00 0. " SW_DONE_ACK ,Register programming done" "Not done,Done" group.long 0x36C++0x03 line.long 0x00 "POISONCFG,AXI Poison Configuration Register" bitfld.long 0x00 24. " RD_POISON_INTR_CLR ,Interrupt clear for read transaction poisoning" "Not cleared,Cleared" bitfld.long 0x00 20. " RD_POISON_INTR_EN ,Enables interrupts for read transaction poisoning" "Disabled,Enabled" newline bitfld.long 0x00 16. " RD_POISON_SLVERR_EN ,Enables SLVERR response for read transaction poisoning" "Disabled,Enabled" bitfld.long 0x00 8. " WR_POISON_INTR_CLR ,Interrupt clear for write transaction poisoning" "Not cleared,Cleared" newline bitfld.long 0x00 4. " WR_POISON_INTR_EN ,Enables interrupts for write transaction poisoning" "Disabled,Enabled" bitfld.long 0x00 0. " WR_POISON_SLVERR_EN ,Enables SLVERR response for write transaction poisoning" "Disabled,Enabled" rgroup.long 0x370++0x03 line.long 0x00 "POISONSTAT,AXI Poison Status Register" bitfld.long 0x00 16. " RD_POISON_INTR_0 ,Read transaction poisoning error interrupt for port 0" "Not occurred,Occurred" bitfld.long 0x00 0. " WR_POISON_INTR_0 ,Write transaction poisoning error interrupt for port 0" "Not occurred,Occurred" rgroup.long 0x3FC++0x03 line.long 0x00 "PSTAT,Port Status Register" bitfld.long 0x00 16. " WR_PORT_BUSY_0 ,Indicates if there are outstanding writes for AXI port 0" "Not busy,Busy" bitfld.long 0x00 0. " RD_PORT_BUSY_0 ,Indicates if there are outstanding reads for AXI port 0" "Not busy,Busy" group.long 0x400++0x0B line.long 0x00 "PCCFG,Port Common Configuration Register" bitfld.long 0x00 8. " BL_EXP_MODE ,Burst length expansion mode" "0,1" bitfld.long 0x00 4. " PAGEMATCH_LIMIT ,Page match four limit" "No limit,Limit" newline bitfld.long 0x00 0. " GO2CRITICAL_EN ,Sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals" "Disabled,Enabled" line.long 0x04 "PCFGR_0,Port 0 Configuration Read Register" bitfld.long 0x04 16. " RDWR_ORDERED_EN ,Enable ordered read/writes" "Disabled,Enabled" bitfld.long 0x04 14. " RD_PORT_PAGEMATCH_EN ,Enables the Page Match feature" "Disabled,Enabled" newline bitfld.long 0x04 13. " RD_PORT_PAGEMATCH_EN ,Enables the AXI urgent sideband signal" "Disabled,Enabled" bitfld.long 0x04 12. " RD_PORT_AGING_EN ,Enables aging function for the read channel of the port" "Disabled,Enabled" newline hexmask.long.word 0x04 0.--9. 1. " RD_PORT_PRIORITY ,Determines the initial load value of read aging counters" line.long 0x08 "PCFGW_0,Port n Configuration Write Register" bitfld.long 0x08 14. " WR_PORT_PAGEMATCH_EN ,Enables the Page Match feature" "Disabled,Enabled" bitfld.long 0x08 13. " WR_PORT_URGENT_EN ,Enables the AXI urgent sideband signal" "Disabled,Enabled" newline bitfld.long 0x08 12. " WR_PORT_AGING_EN ,Enables aging function for the write channel of the port" "Disabled,Enabled" hexmask.long.word 0x08 0.--9. 1. " WR_PORT_PRIORITY ,Determines the initial load value of write aging counters" group.long 0x490++0x13 line.long 0x00 "PCTRL_0,Port 0 Control Register" bitfld.long 0x00 0. " PORT_EN ,Enables AXI port n" "Disabled,Enabled" line.long 0x04 "PCFGQOS0_0,Port 0 Read QoS Configuration Register 0" bitfld.long 0x04 20.--21. " RQOS_MAP_REGION1 ,Indicates the traffic class of region 1" "LPR,VPR,HPR,?..." bitfld.long 0x04 16.--17. " RQOS_MAP_REGION0 ,This bitfield indicates the traffic class of region 0" "LPR,VPR,HPR,?..." newline bitfld.long 0x04 0.--3. " RQOS_MAP_LEVEL1 ,Separation level1 indicating the end of region0 mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,?..." line.long 0x08 "PCFGQOS1_0,Port n Read QoS Configuration Register 1" hexmask.long.word 0x08 16.--26. 1. " RQOS_MAP_TIMEOUTR ,Specifies the timeout value for transactions mapped to the red address queue" hexmask.long.word 0x08 0.--10. 1. " RQOS_MAP_TIMEOUTB ,Specifies the timeout value for transactions mapped to the blue address queue" line.long 0x0C "PCFGWQOS0_0,Port n Write QoS Configuration Register 0" bitfld.long 0x0C 20.--21. " WQOS_MAP_REGION1 ,This bitfield indicates the traffic class of region 1" "NPW,VPW,?..." bitfld.long 0x0C 16.--17. " WQOS_MAP_REGION0 ,This bitfield indicates the traffic class of region 0" "NPW,VPW,?..." newline bitfld.long 0x0C 0.--3. " WQOS_MAP_LEVEL ,Separation level indicating the end of region0 mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,?..." line.long 0x10 "PCFGWQOS1_0,Port n Write QoS Configuration Register 1" hexmask.long.word 0x10 0.--10. 1. " WQOS_MAP_TIMEOUT ,Specifies the timeout value for write transactions" newline tree "SHADOW Registers" if (((per.l(ad:0x5C300000))&0x20)==0x20) group.long 0x2020++0x07 line.long 0x00 "DERATEEN_SHADOW,Temperature Derate Enable Register" bitfld.long 0x00 8.--9. " RC_DERATE_VALUE ,Derate value of tRC for LPDDR4" "+1,+2,+3,+4" bitfld.long 0x00 4.--7. " DERATE_BYTE ,Derate value of tRC for LPDDR4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1. " DERATE_VALUE ,Derate value" "+1,+2" bitfld.long 0x00 0. " DERATE_ENABLE ,Enables derating" "Disabled,Enabled" line.long 0x04 "DERATEINT_SHADOW,Temperature Derate Interval Register" elif ((((per.l(ad:0x5C300000))&0x08)==0x08)||(((per.l(ad:0x5C300000))&0x04)==0x04)) group.long 0x2020++0x07 line.long 0x00 "DERATEEN_SHADOW,Temperature Derate Enable Register" bitfld.long 0x00 4.--7. " DERATE_BYTE ,Derate value of tRC for LPDDR4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " DERATE_VALUE ,Derate value" "+1,+2" newline bitfld.long 0x00 0. " DERATE_ENABLE ,Enables derating" "Disabled,Enabled" line.long 0x04 "DERATEINT_SHADOW,Temperature Derate Interval Register" else hgroup.long 0x2020++0x03 hide.long 0x00 "DERATEEN_SHADOW,Temperature Derate Enable Register" hgroup.long 0x2024++0x03 hide.long 0x00 "DERATEINT_SHADOW,Temperature Derate Interval Register" endif if (((per.l(ad:0x5C300000))&0x20)==0x20) group.long 0x2050++0x03 line.long 0x00 "RFSHCTL0_SHADOW,Refresh Control Register 0" bitfld.long 0x00 20.--23. " REFRESH_MARGIN ,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--16. " REFRESH_TO_X32 ,Speculative refreshes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4.--8. " REFRESH_BURST ,Number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 2. " PER_BANK_REFRESH ,Per bank refresh" "Per bank,All bank" else group.long 0x2050++0x03 line.long 0x00 "RFSHCTL0_SHADOW,Refresh Control Register 0" bitfld.long 0x00 20.--23. " REFRESH_MARGIN ,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--16. " REFRESH_TO_X32 ,Speculative refreshes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4.--8. " REFRESH_BURST ,Number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif group.long 0x2064++0x03 line.long 0x00 "RFSHTMG_SHADOW,Refresh Timing Register" hexmask.long.word 0x00 16.--27. 1. " T_RFC_NOM_X32 ,Average time interval between refreshes per rank" bitfld.long 0x00 15. " LPDDR3_TREFBW_EN ,tREFBW parameter enabled" "Disabled,Enabled" newline hexmask.long.word 0x00 0.--9. 1. " T_RFC_MIN ,Minimum time from refresh to refresh or activate" group.long 0x20DC++0x07 line.long 0x00 "INIT3_SHADOW,SDRAM Initialization Register 3" hexmask.long.word 0x00 16.--31. 1. " MR ,Value to write to MR register" hexmask.long.word 0x00 0.--15. 1. " EMR ,Value to write to EMR register" line.long 0x04 "INIT4_SHADOW,SDRAM Initialization Register 4" hexmask.long.word 0x04 16.--31. 1. " EMR2 ,Value to write to EMR2 register" hexmask.long.word 0x04 0.--15. 1. " EMR3 ,Value to write to EMR3 register" hgroup.long 0x20E8++0x03 hide.long 0x00 "INIT6_SHADOW,SDRAM Initialization Register 6" hgroup.long 0x20EC++0x03 hide.long 0x00 "INIT7_SHADOW,SDRAM Initialization Register 7" group.long 0x2100++0x0B line.long 0x00 "DRAMTMG0_SHADOW,SDRAM Timing Register 0" hexmask.long.byte 0x00 24.--30. 1. " WR2PRE ,Minimum time between write and precharge to same bank" bitfld.long 0x00 16.--21. " T_FAW ,T_FAW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x00 8.--14. 1. " T_RAS_MAX ,Maximum time between activate and precharge to same bank" bitfld.long 0x00 0.--5. " T_RAS_MIN ,Minimum time between activate and precharge to the same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DRAMTMG1_SHADOW,SDRAM Timing Register 1" bitfld.long 0x04 16.--20. " T_XP ,Minimum time after power-down exit to any operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--13. " RD2PRE ,Minimum time from read to precharge of same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x04 0.--6. 1. " T_RC ,Minimum time between activates to same bank" line.long 0x08 "DRAMTMG2_SHADOW,SDRAM Timing Register 2" bitfld.long 0x08 24.--29. " WRITE_LATENCY ,Set to WL time from write command to write data on SDRAM interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " READ_LATENCY ,Set to RL time from read command to read data on SDRAM interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " RD2WR ,Minimum time from read command to write command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " WR2RD ,Minimum time from write command to read command for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if ((((per.l(ad:0x5C300000))&0x20)==0x20)||(((per.l(ad:0x5C300000))&0x08)==0x08)||(((per.l(ad:0x5C300000))&0x04)==0x04)) group.long 0x210C++0x03 line.long 0x00 "DRAMTMG3_SHADOW,SDRAM Timing Register 3" hexmask.long.word 0x00 20.--29. 1. " T_MRW ,Time to wait after a mode register write or read (MRW or MRR)" bitfld.long 0x00 12.--17. " T_MRD ,Cycles to wait after a mode register write or read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.l(ad:0x5C300000))&0x01)==0x01) group.long 0x210C++0x03 line.long 0x00 "DRAMTMG3_SHADOW,SDRAM Timing Register 3" textfld " " bitfld.long 0x00 12.--17. " T_MRD ,Cycles to wait after a mode register write or read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 0.--9. 1. " T_MOD ,Cycles between load mode command and following non-load mode command" else group.long 0x210C++0x03 line.long 0x00 "DRAMTMG3_SHADOW,SDRAM Timing Register 3" textfld " " bitfld.long 0x00 12.--17. " T_MRD ,Cycles to wait after a mode register write or read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x2110++0x07 line.long 0x00 "DRAMTMG4_SHADOW,SDRAM Timing Register 4" bitfld.long 0x00 24.--28. " T_RCD ,Minimum time from activate to read or write command to same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--19. " T_CCD ,This is the minimum time between two reads or two writes for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " T_RRD ,Minimum time between activates from bank a to bank b for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " T_RP ,Minimum time from precharge to activate of same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DRAMTMG5_SHADOW,SDRAM Timing Register 5" bitfld.long 0x04 24.--27. " T_CKSRX ,Time before self refresh exit that ck is maintained as a valid clock before issuing SRX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " T_CKSRE ,Time after self refresh down entry that CK is maintained as a valid clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--13. " T_CKESR ,Minimum CKE low width for self refresh or self refresh power down entry to exit timing in memory clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--4. " T_CKE ,Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x5C300000))&0x20)==0x20) group.long 0x2118++0x07 line.long 0x00 "DRAMTMG6_SHADOW,SDRAM Timing Register 6" bitfld.long 0x00 24.--27. " T_CKDPDE ,Time after deep power down entry that CK is maintained as a valid clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " T_CKDPDX ,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " T_CKCSX ,Time before clock stop exit that CK is maintained as a valid clock before issuing clock stop exit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DRAMTMG7_SHADOW,SDRAM Timing Register 7" bitfld.long 0x04 8.--11. " T_CKPDE ,This is the time after Power Down Entry that CK is maintained as a valid clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " T_CKPDX ,This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x2118++0x03 line.long 0x00 "DRAMTMG6_SHADOW,SDRAM Timing Register 6" bitfld.long 0x00 24.--27. " T_CKDPDE ,Time after deep power down entry that CK is maintained as a valid clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " T_CKDPDX ,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0x211C++0x03 hide.long 0x00 "DRAMTMG7_SHADOW,SDRAM Timing Register 7" endif if (((per.l(ad:0x5C300000))&0x01)==0x01) group.long 0x2120++0x03 line.long 0x00 "DRAMTMG8_SHADOW,SDRAM Timing Register 8" hexmask.long.byte 0x00 24.--30. 1. " T_XS_FAST_X32 ,Exit self refresh to ZQCL ZQCS and MRS" hexmask.long.byte 0x00 16.--22. 1. " T_XS_ABORT_X32 ,Exit Self Refresh to commands not requiring a locked DLL in self refresh abort" newline hexmask.long.byte 0x00 8.--14. 1. " T_XS_DLL_X32 ,Exit self refresh to commands requiring a locked DLL" hexmask.long.byte 0x00 0.--6. 1. " T_XS_X32 ,Exit self refresh to commands not requiring a locked DLL" else group.long 0x2120++0x03 line.long 0x00 "DRAMTMG8_SHADOW,SDRAM Timing Register 8" hexmask.long.byte 0x00 24.--30. 1. " T_XS_FAST_X32 ,Exit self refresh to ZQCL ZQCS and MRS" hexmask.long.byte 0x00 16.--22. 1. " T_XS_ABORT_X32 ,Exit Self Refresh to commands not requiring a locked DLL in self refresh abort" endif hgroup.long 0x2124++0x03 hide.long 0x00 "DRAMTMG9_SHADOW,SDRAM Timing Register 9" group.long 0x2128++0x03 line.long 0x00 "DRAMTMG10_SHADOW,SDRAM Timing Register 10" bitfld.long 0x00 16.--20. " T_SYNC_GEAR ,Indicates the time between MRS command and the sync pulse time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " T_CMD_GEAR ,Sync pulse to first valid command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 2.--3. " T_GEAR_SETUP ,Geardown setup time" "0,1,2,3" bitfld.long 0x00 0.--1. " T_GEAR_HOLD ,Geardown hold time" "0,1,2,3" hgroup.long 0x212C++0x03 hide.long 0x00 "DRAMTMG11_SHADOW,SDRAM Timing Register 11" group.long 0x2130++0x07 line.long 0x00 "DRAMTMG12_SHADOW,SDRAM Timing Register 12" bitfld.long 0x00 16.--17. " T_CMDCKE ,Delay from valid command to CKE input LOW" "0,1,2,3" bitfld.long 0x00 8.--11. " T_CKEHCMD ,Valid command requirement after CKE input HIGH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--4. " T_MRD_PDA ,This is the Mode Register Set command cycle time in PDA mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DRAMTMG13_SHADOW,SDRAM Timing Register 13" hexmask.long.byte 0x04 24.--30. 1. " ODTLOFF ,Latency from CAS-2 command to tODToff reference" bitfld.long 0x04 16.--21. " T_CCD_MW ,This is the minimum time from write or masked write to masked write command for same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 0.--2. " T_PPD ,Minimum time from precharge to precharge command" "0,1,2,3,4,5,6,7" if (((per.l(ad:0x5C300000))&0x20)==0x20) group.long 0x2138++0x03 line.long 0x00 "DRAMTMG14_SHADOW,SDRAM Timing Register 14" hexmask.long.word 0x00 0.--11. 1. " T_XSR ,Exit Self Refresh to any command" else hgroup.long 0x2138++0x03 hide.long 0x00 "DRAMTMG14_SHADOW,SDRAM Timing Register 14" endif group.long 0x213C++0x03 line.long 0x00 "DRAMTMG15_SHADOW,SDRAM Timing Register 15" bitfld.long 0x00 31. " EN_DFI_LP_T_STAB ,Enables using tSTAB" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " T_STAB_X32 ,Stabilization time" if ((((per.l(ad:0x5C300000))&0x01)==0x01)||(((per.l(ad:0x5C300000))&0x20)==0x20)) group.long 0x2180++0x03 line.long 0x00 "ZQCTL0_SHADOW,ZQ Control Register 0" bitfld.long 0x00 31. " DIS_AUTO_ZQ ,Disable DDRC generation of ZQCS/MPC command" "No,Yes" bitfld.long 0x00 30. " DIS_SRX_ZQCL ,Disable issuing of ZQCL/MPC(ZQ calibration) command at self-refresh/sr-powerdown exit" "No,Yes" newline bitfld.long 0x00 29. " ZQ_RESISTOR_SHARED ,ZQ resistor is shared between ranks" "Not shared,Shared" newline hexmask.long.word 0x00 16.--26. 1. " T_ZQ_LONG_NOP ,Number of DFI clock cycles of NOP required after a ZQCL/MPC command is issued to SDRAM" hexmask.long.word 0x00 0.--9. 1. " T_ZQ_SHORT_NOP ,Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM" else hgroup.long 0x2180++0x03 hide.long 0x00 "ZQCTL0_SHADOW,ZQ Control Register 0" endif group.long 0x2190++0x07 line.long 0x00 "DFITMG0_SHADOW,DFI Timing Register 0" bitfld.long 0x00 24.--28. " DFI_T_CTRL_DELAY ,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 23. " DFI_RDDATA_USE_SDR ,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR(DFI PHY clock) values" "HDR,SDR" newline hexmask.long.byte 0x00 16.--22. 1. " DFI_T_RDDATA_EN ,Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal" bitfld.long 0x00 15. " DFI_WRDATA_USE_SDR ,Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values" "HDR,SDR" newline bitfld.long 0x00 8.--13. " DFI_TPHY_WRDATA ,Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal" "0,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 0.--5. " DFI_TPHY_WRLAT ,Write latency number of clocks from the write command to write data enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DFITMG1_SHADOW,DFI Timing Register 1" bitfld.long 0x04 28.--31. " DFI_T_CMD_LAT ,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven" "0,,,3,4,5,6,,8,?..." bitfld.long 0x04 24.--25. " DFI_T_PARIN_LAT ,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven" "0,1,2,3" newline bitfld.long 0x04 16.--20. " DFI_T_WRDATA_DELAY ,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " DFI_T_DRAM_CLK_DISABLE ,Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--4. " DFI_T_DRAM_CLK_ENABLE ,Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x21B4++0x07 line.long 0x00 "DFITMG2_SHADOW,DFI Timing Register 2" hexmask.long.byte 0x00 8.--14. 1. " DFI_TPHY_RDCSLAT ,Number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted" bitfld.long 0x00 0.--5. " DFI_TPHY_WRCSLAT ,Number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DFITMG3_SHADOW,DFI Timing Register 3" bitfld.long 0x04 0.--4. " DFI_T_GEARDOWN_DELAY ,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x2240++0x03 line.long 0x00 "ODTCFG_SHADOW,ODT Configuration Register" bitfld.long 0x00 24.--27. " WR_ODT_HOLD ,DFI PHY clock cycles to hold ODT for a write command" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " WR_ODT_DELAY ,The delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--11. " RD_ODT_HOLD ,DFI PHY clock cycles to hold ODT for a read command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--6. " RD_ODT_DELAY ,The delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end width 0x0B tree.end tree "DDRP0_0 (DDR PHY)" base ad:0x5C310000 width 14. rgroup.long 0x00++0x03 line.long 0x00 "RIDR,Revision Identification Register" hexmask.long.byte 0x00 24.--31. 1. " UDRID ,User-Defined revision ID" hexmask.long.byte 0x00 20.--23. 1. " PHYMJR ,PHY major revision" hexmask.long.byte 0x00 16.--19. 1. " PHYMDR ,PHY moderate revision" hexmask.long.byte 0x00 12.--15. 1. " PHYMNR ,PHY minor revision" newline hexmask.long.byte 0x00 8.--11. 1. " PUBMJR ,PUB major revision" hexmask.long.byte 0x00 4.--7. 1. " PUBMDR ,PUB moderate revision" hexmask.long.byte 0x00 0.--3. 1. " PUBMNR ,PUB minor revision" group.long 0x04++0x03 line.long 0x00 "PIR,PHY Initialization Register" bitfld.long 0x00 30. " ZCALBYP ,Impedance calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 29. " DCALPSE ,Digital delay line calibration pause" "Not paused,Paused" bitfld.long 0x00 20. " DQS2DQ ,Write DQS2DQ training" "Disabled,Enabled" bitfld.long 0x00 19. " RDIMMINIT ,RDIMM initialization" "Disabled,Enabled" newline bitfld.long 0x00 18. " CTLDINIT ,Controller DRAM initialization" "Disabled,Enabled" bitfld.long 0x00 17. " VREF ,VREF training" "Disabled,Enabled" bitfld.long 0x00 16. " SRD ,Static read training" "Disabled,Enabled" bitfld.long 0x00 15. " WREYE ,Write data eye training" "Disabled,Enabled" newline bitfld.long 0x00 14. " RDEYE ,Read data eye training" "Disabled,Enabled" bitfld.long 0x00 13. " WRDSKW ,Write data bit deskew" "Disabled,Enabled" bitfld.long 0x00 12. " RDDSKW ,Read data bit deskew" "Disabled,Enabled" bitfld.long 0x00 11. " WLADJ ,Write leveling adjust" "Disabled,Enabled" newline bitfld.long 0x00 10. " QSGATE ,Read DQS gate training" "Disabled,Enabled" bitfld.long 0x00 9. " WL ,Write leveling" "Disabled,Enabled" bitfld.long 0x00 8. " DRAMINIT ,DRAM initialization" "Disabled,Enabled" bitfld.long 0x00 7. " DRAMRST ,DRAM reset" "No reset,Reset" newline bitfld.long 0x00 6. " PHYRST ,PHY reset" "No reset,Reset" bitfld.long 0x00 5. " DCAL ,Digital delay line calibration" "Disabled,Enabled" bitfld.long 0x00 4. " PLLINIT ,PLL initialization" "Disabled,Enabled" bitfld.long 0x00 2. " CA ,CA training" "Disabled,Enabled" newline bitfld.long 0x00 1. " ZCAL ,Impedance calibration" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization trigger" "Not triggered,Triggered" group.long 0x10++0x1F line.long 0x00 "PGCR0,PHY General Configuration Register 0" bitfld.long 0x00 31. " ADCP ,Address copy" "Disabled,Enabled" bitfld.long 0x00 26. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 24.--25. " OSCACDL ,Oscillator mode address/command delay line select" "0,1,2,3" bitfld.long 0x00 14.--18. " DTOSEL ,Digital test output select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 9.--12. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "PGCR1,PHY General Configuration Register 1" bitfld.long 0x04 31. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x04 28. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value (equivalent to one CK period)" "Not loaded,Loaded" bitfld.long 0x04 27. " DLTST ,Delay line test start" "Stopped,Started" bitfld.long 0x04 26. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x04 25. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x04 24. " ACVLDTRN ,AC loopback valid train" "0,1" bitfld.long 0x04 21.--23. " ACVLDDLY ,AC loopback valid delay" "0,1,2,3,4,5,6,7" bitfld.long 0x04 20. " LRDIMMST ,LRDIMM software training" "Disabled,Enabled" newline bitfld.long 0x04 18. " UPDMSTRC0 ,DFI update master channel 0" "Not updated,Updated" bitfld.long 0x04 17. " DISDIC ,Enable/disable control for DFI_INIT_COMPLETE" "Disabled,Enabled" bitfld.long 0x04 16. " ACPDDC ,AC power-down with dual channels" "Disabled,Enabled" bitfld.long 0x04 15. " DUALCHN ,Dual channel configuration" "Disabled,Enabled" newline bitfld.long 0x04 13.--14. " FDEPTH ,Filter depth" "0,1,2,3" bitfld.long 0x04 11.--12. " LPFDEPTH ,Low-pass filter depth" "0,1,2,3" bitfld.long 0x04 10. " LPFEN ,Low-pass filter enable" "Disabled,Enabled" bitfld.long 0x04 9. " MDLEN ,Master delay line enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " PUBMODE ,Enable the PUB to control the interface to the PHY and SDRAM" "Disabled,Enabled" bitfld.long 0x04 5. " CAST ,CA software training" "Disabled,Enabled" bitfld.long 0x04 4. " DX_DQSOUT_DIFF ,Select PDIFF cell for DQS generation" "0,1" bitfld.long 0x04 3. " AC_CKOUT_DIFF ,Select PDIFF cell for CK generation" "0,1" newline bitfld.long 0x04 2. " WLSTEP ,Write leveling step" "0,1" bitfld.long 0x04 1. " WLMODE ,Write leveling software mode" "Disabled,Enabled" bitfld.long 0x04 0. " DTOMODE ,Digital test output mode" "Disabled,Enabled" line.long 0x08 "PGCR2,PHY General Configuration Register 2" bitfld.long 0x08 31. " CLRTSTAT ,Clear training status registers" "No effect,Cleared" bitfld.long 0x08 30. " CLRZCAL ,Clear impedance calibration" "No effect,Cleared" bitfld.long 0x08 29. " CLRPERR ,Clear parity error" "No effect,Cleared" bitfld.long 0x08 28. " ICPC ,Initialization complete pin configuration" "0,1" newline hexmask.long.byte 0x08 20.--27. 1. " DTPMXTMR ,Data training PUB mode exit timer" bitfld.long 0x08 19. " INITFSMBYP ,Initialization bypass" "Not bypassed,Bypassed" bitfld.long 0x08 18. " PLLFSMBYP ,PLL FSM bypass" "Not bypassed,Bypassed" hexmask.long.tbyte 0x08 0.--17. 1. " TREFPRD ,Refresh period" line.long 0x0C "PGCR3,PHY General Configuration Register 3" hexmask.long.byte 0x0C 24.--31. 1. " CKNEN ,CKN enable" hexmask.long.byte 0x0C 16.--23. 1. " CKEN ,CK enable" bitfld.long 0x0C 13.--14. " GATEACRDCLK ,Enable clock gating for AC [0] CTL_RD_CLK" "0,1,2,3" bitfld.long 0x0C 11.--12. " GATEACDDRCLK ,Enable clock gating for AC [0] DDR_CLK" "0,1,2,3" newline bitfld.long 0x0C 9.--10. " GATEACCTLCLK ,Enable clock gating for AC [0] CTL_CLK" "0,1,2,3" bitfld.long 0x0C 6.--7. " DDLBYPMODE ,Controls DDL bypass modes" "0,1,2,3" bitfld.long 0x0C 5. " IOLB ,IO loopback select" "0,1" bitfld.long 0x0C 3.--4. " RDMODE ,AC receive FIFO read mode" "0,1,2,3" newline bitfld.long 0x0C 2. " DISRST ,Read FIFO reset disable" "No,Yes" bitfld.long 0x0C 0.--1. " CLKLEVEL ,Clock level when clock gating" "0,1,2,3" line.long 0x10 "PGCR4,PHY General Configuration Register 4" bitfld.long 0x10 29. " ACDDLLD ,AC DDL delay select dynamic load" "Disabled,Enabled" bitfld.long 0x10 24.--28. " ACDDLBYP ,AC DDL bypass" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 23. " OEDDLBYP ,AC OE DDL bypass" "Not bypassed,Bypassed" bitfld.long 0x10 22. " TEDDLBYP ,AC ODT DDL bypass" "Not bypassed,Bypassed" newline bitfld.long 0x10 21. " PDRDDLBYP ,AC PDR DDL bypass" "Not bypassed,Bypassed" bitfld.long 0x10 20. " RRRMODE ,AC macro read path rise-to-rise mode" "Disabled,Enabled" bitfld.long 0x10 19. " WRRMODE ,AC macro write path rise-to-rise mode" "Disabled,Enabled" bitfld.long 0x10 17. " DCALTYPE ,DDL calibration type" "0,1" newline hexmask.long.word 0x10 8.--16. 1. " DCALSVAL ,DDL calibration starting value" bitfld.long 0x10 4.--7. " LPWAKEUP_THRSH ,AC low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 1. " LPPLLPD ,AC low power PLL power down" "Disabled,Enabled" bitfld.long 0x10 0. " LPIOPD ,AC low power IO power down" "Disabled,Enabled" line.long 0x14 "PGCR5,PHY General Configuration Register 5" hexmask.long.byte 0x14 24.--31. 1. " FRQBT ,Frequency B ratio term" hexmask.long.byte 0x14 16.--23. 1. " FRQAT ,Frequency A ratio term" hexmask.long.byte 0x14 8.--15. 1. " DISCNPERIOD ,DFI disconnect time period" bitfld.long 0x14 4.--7. " VREF_RBCTRL ,Receiver bias core side control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 2. " DXREFISELRANGE ,Internal VREF generator REFSEL range select" "0,1" bitfld.long 0x14 1. " DDLPGACT ,DDL page read write select" "Read,Write" bitfld.long 0x14 0. " DDLPGRW ,DDL page read write select" "Read,Write" line.long 0x18 "PGCR6,PHY General Configuration Register 6" hexmask.long.byte 0x18 16.--23. 1. " DLDLMT ,Delay line VT drift limit" bitfld.long 0x18 13. " ACDLVT ,AC address/command delay LCDL VT compensation" "Disabled,Enabled" bitfld.long 0x18 12. " ACBVT ,Address/command bit delay VT compensation" "Disabled,Enabled" bitfld.long 0x18 11. " ODTBVT ,ODT bit delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x18 10. " CKEBVT ,CKE bit delay VT compensation" "Disabled,Enabled" bitfld.long 0x18 9. " CSNBVT ,CSN bit delay VT compensation" "Disabled,Enabled" bitfld.long 0x18 8. " CKBVT ,CK bit delay VT compensation" "Disabled,Enabled" bitfld.long 0x18 1. " FVT ,Forced VT compensation trigger" "Not triggered,Triggered" newline bitfld.long 0x18 0. " INHVT ,VT calculation inhibit" "Disabled,Enabled" line.long 0x1C "PGCR7,PHY General Configuration Register 7" bitfld.long 0x1C 5. " ACCALCLK ,AC calibration clock select" "0,1" bitfld.long 0x1C 4. " ACRCLKMD ,AC read clock mode" "Disabled,Enabled" bitfld.long 0x1C 3. " ACDLDT ,AC DDL load type" "0,1" bitfld.long 0x1C 1. " ACDTOSEL ,AC digital test output select" "0,1" newline bitfld.long 0x1C 0. " ACTMODE ,AC test mode" "Disabled,Enabled" rgroup.long 0x30++0x0B line.long 0x00 "PGSR0,PHY General Status Register 0" bitfld.long 0x00 31. " APLOCK ,AC PLL lock" "Not locked,Locked" bitfld.long 0x00 30. " SRDERR ,Static read error" "No error,Error" bitfld.long 0x00 29. " CAWRN ,CA training warning" "Not occurred,Occurred" bitfld.long 0x00 28. " CAERR ,CA training error" "No error,Error" newline bitfld.long 0x00 27. " WEERR ,Write eye training error" "No error,Error" bitfld.long 0x00 26. " REERR ,Read eye training error" "No error,Error" bitfld.long 0x00 25. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x00 24. " RDERR ,Read bit deskew error" "No error,Error" newline bitfld.long 0x00 23. " WLAERR ,Write leveling adjustment error" "No error,Error" bitfld.long 0x00 22. " QSGERR ,DQS gate training error" "No error,Error" bitfld.long 0x00 21. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x00 20. " ZCERR ,Impedance calibration error" "No error,Error" newline bitfld.long 0x00 19. " VERR ,VREF training error" "No error,Error" bitfld.long 0x00 18. " DQS2DQERR ,Write DQS2DQ training error" "No error,Error" bitfld.long 0x00 15. " DQS2DQDONE ,Write DQS2DQ training done" "Not done,Done" bitfld.long 0x00 14. " VDONE ,VREF training done" "Not done,Done" newline bitfld.long 0x00 13. " SRDDONE ,Static read done" "Not done,Done" bitfld.long 0x00 12. " CADONE ,CA training done" "Not done,Done" bitfld.long 0x00 11. " WEDONE ,Write eye training done" "Not done,Done" bitfld.long 0x00 10. " REDONE ,Read eye training done" "Not done,Done" newline bitfld.long 0x00 9. " WDDONE ,Write bit deskew done" "Not done,Done" bitfld.long 0x00 8. " RDDONE ,Read bit deskew done" "Not done,Done" bitfld.long 0x00 7. " WLADONE ,Write leveling adjustment done" "Not done,Done" bitfld.long 0x00 6. " QSGDONE ,DQS gate training done" "Not done,Done" newline bitfld.long 0x00 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x00 4. " DIDONE ,DRAM initialization done" "Not done,Done" bitfld.long 0x00 3. " ZCDONE ,Impedance calibration done" "Not done,Done" bitfld.long 0x00 2. " DCDONE ,Digital delay line calibration done" "Not done,Done" newline bitfld.long 0x00 1. " PLDONE ,PLL lock done" "Not done,Done" bitfld.long 0x00 0. " IDONE ,Initialization done" "Not done,Done" line.long 0x04 "PGSR1,PHY General Status Register 1" bitfld.long 0x04 31. " PARERR ,RDIMM parity error" "No error,Error" bitfld.long 0x04 30. " VTSTOP ,VT stop" "Not stopped,Stopped" hexmask.long.tbyte 0x04 1.--24. 1. " DLTCODE ,Delay line test code for AC macro 0" bitfld.long 0x04 0. " DLTDONE ,Delay line test done for AC macro 0" "Not done,Done" line.long 0x08 "PGSR2,PHY General Status Register 2" hexmask.long.tbyte 0x08 1.--24. 1. " DLTCODE ,Delay line test code for AC macro 1" bitfld.long 0x08 0. " DLTDONE ,Delay line test done for AC macro 1" "Not done,Done" newline group.long 0x40++0x1B line.long 0x00 "PTR0,PHY Timing Register 0" hexmask.long.word 0x00 21.--31. 1. " TPLLPD ,PLL power-down time" hexmask.long.tbyte 0x00 6.--20. 1. " TPLLGS ,PLL gear shift time" bitfld.long 0x00 0.--5. " TPHYRST ,PHY reset time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "PTR1,PHY Timing Register 1" hexmask.long.word 0x04 16.--31. 1. " TPLLLOCK ,PLL lock time" hexmask.long.word 0x04 0.--12. 1. " TPLLRST ,PLL reset time" line.long 0x08 "PTR2,PHY Timing Register 2" bitfld.long 0x08 15.--19. " TWLDLYS ,Write leveling delay settling time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 10.--14. " TCALH ,Calibration hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 5.--9. " TCALS ,Calibration setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 0.--4. " TCALON ,Calibration on time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "PTR3,PHY Timing Register 3" hexmask.long.tbyte 0x0C 0.--22. 1. " TDINIT0 ,DRAM initialization time 0" line.long 0x10 "PTR4,PHY Timing Register 4" hexmask.long.word 0x10 0.--12. 1. " TDINIT1 ,DRAM initialization time 1" line.long 0x14 "PTR5,PHY Timing Register 5" hexmask.long.tbyte 0x14 0.--18. 1. " TDINIT2 ,DRAM initialization time 2" line.long 0x18 "PTR6,PHY Timing Register 6" hexmask.long.byte 0x18 20.--26. 1. " TDINIT4 ,DRAM initialization time 4" hexmask.long.word 0x18 0.--11. 1. " TDINIT3 ,DRAM initialization time 3" group.long 0x68++0x17 line.long 0x00 "PLLCR0,PLL Control Register 0" bitfld.long 0x00 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x00 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x00 28. " RSTOPM ,Reference stop mode" "Disabled,Enabled" newline bitfld.long 0x00 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x00 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12. " GSHIFT ,Gear shift" "Disabled,Enabled" bitfld.long 0x00 8. " ATOEN ,Analog test enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "PLLCR1,PLL Control Register 1" hexmask.long.word 0x04 16.--31. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x04 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x04 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypassed,Bypassed" bitfld.long 0x04 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x04 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x04 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x04 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x08 "PLLCR2,PLL Control Register 2" line.long 0x0C "PLLCR3,PLL Control Register 3" line.long 0x10 "PLLCR4,PLL Control Register 4" line.long 0x14 "PLLCR5,PLL Control Register 5" hexmask.long.byte 0x14 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL generator control bus PLL_CTRL" group.long 0x88++0x03 line.long 0x00 "DXCCR,DATX8 Common Configuration Register" bitfld.long 0x00 29. " RKLOOP ,Rank looping (per-rank eye centering) enable" "Disabled,Enabled" bitfld.long 0x00 3.--6. " DQS2DQMPER ,Write DQS2DQ training measurement period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x90++0x03 line.long 0x00 "DSGCR,DDR System General Configuration Register" bitfld.long 0x00 27. " RDBICLSEL ,Select RDBI CL calculation" "Default,RDBICL" bitfld.long 0x00 24.--26. " RDBICL ,RDBI CL adjust value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " PHYZUEN ,PHY impedance update enable" "Disabled,Enabled" bitfld.long 0x00 21. " RSTOE ,SDRAM reset output enable" "Disabled,Enabled" newline bitfld.long 0x00 19.--20. " SDRMODE ,Single data rate mode" "0,1,2,3" bitfld.long 0x00 17. " ATOAE ,ATO analog test enable" "Disabled,Enabled" bitfld.long 0x00 16. " DTOOE ,DTO output enable" "Disabled,Enabled" bitfld.long 0x00 15. " DTOIOM ,DTO I/O mode" "Disabled,Enabled" newline bitfld.long 0x00 14. " DTOPDR ,DTO power down receiver" "Disabled,Enabled" bitfld.long 0x00 12. " DTOODT ,DTO on-die termination" "Disabled,Enabled" bitfld.long 0x00 6.--11. " PUAD ,PHY update acknowledge delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 5. " CUAEN ,Controller update acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " MSTRVER ,Controller impedance update enable" "Disabled,Enabled" bitfld.long 0x00 2. " CTLZUEN ,Controller impedance update enable" "Disabled,Enabled" bitfld.long 0x00 1. " MREN ,Master request enable" "Disabled,Enabled" bitfld.long 0x00 0. " PUREN ,PHY update request enable" "Disabled,Enabled" group.long 0x98++0x03 line.long 0x00 "ODTCR,ODT Configuration Register" bitfld.long 0x00 16. " WRODT ,Write ODT" "0,1" bitfld.long 0x00 0. " RDODT ,Read ODT" "0,1" group.long 0xA0++0x03 line.long 0x00 "AACR,Anti-Aging Control Register" bitfld.long 0x00 31. " AAOENC ,Anti-aging PAD output enable control" "Disabled,Enabled" bitfld.long 0x00 30. " AAENC ,Anti-aging enable control" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " AATR ,Anti-aging toggle rate" group.long 0xC0++0x07 line.long 0x00 "GPR0,General Purpose Register 0" line.long 0x04 "GPR1,General Purpose Register 1" group.long 0x100++0x03 line.long 0x00 "DCR,DRAM Configuration Register" bitfld.long 0x00 31. " GEARDN ,DDR4 gear down timing" "0,1" bitfld.long 0x00 30. " UBG ,Un-used bank group" "0,1" bitfld.long 0x00 29. " UDIMM ,Un-buffered DIMM address mirroring" "Disabled,Enabled" bitfld.long 0x00 28. " DDR2T ,DDR 2T timing" "0,1" newline bitfld.long 0x00 27. " NOSRA ,No simultaneous rank access" "No,Yes" hexmask.long.word 0x00 10.--17. 1. " BYTEMASK ,Byte mask" bitfld.long 0x00 8.--9. " DDRTYPE ,DDR type" "0,1,2,3" bitfld.long 0x00 7. " MPRDQ ,Multi-purpose register DQ" "0,1" newline bitfld.long 0x00 4.--6. " PDQ ,Primary DQ" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " DDR8BNK ,DDR 8-bank" "Disabled,Enabled" bitfld.long 0x00 0.--2. " DDRMD ,DDR mode" "0,1,2,3,4,5,6,7" group.long 0x110++0x1B line.long 0x00 "DTPR0,DRAM Timing Parameters Register 0" bitfld.long 0x00 24.--28. " TRRD ,Activate to activate command delay on different banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 16.--22. 1. " TRAS ,Activate to precharge command delay" hexmask.long.byte 0x00 8.--14. 1. " TRP ,Precharge command period" bitfld.long 0x00 0.--4. " TRTP ,Internal read to precharge command delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DTPR1,DRAM Timing Parameters Register 1" hexmask.long.byte 0x04 24.--30. 1. " TWLMRD ,Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge" hexmask.long.byte 0x04 16.--22. 1. " TFAW ,4-bank activate period" bitfld.long 0x04 8.--10. " TMOD ,Load mode update delay" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--4. " TMRD ,Load mode cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "DTPR2,DRAM Timing Parameters Register 2" bitfld.long 0x08 28. " TRTW ,Read to write command delay" "0,1" bitfld.long 0x08 24. " TRTODT ,Read to ODT delay" "0,1" bitfld.long 0x08 16.--19. " TCKE ,CKE minimum pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x08 0.--9. 1. " TXS ,Self refresh exit delay" line.long 0x0C "DTPR3,DRAM Timing Parameters Register 3" bitfld.long 0x0C 29.--31. " TOFDX ,ODT turn-off delay extension" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 26.--28. " TCCD ,Read to read and write to write command delay" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 16.--25. 1. " TDLLK ,DLL locking time" bitfld.long 0x0C 8.--11. " TDQSCKMAX ,Maximum DQS output access time from CK/CK#" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 0.--2. " TDQSCK ,DQS output access time from CK/CK#" "0,1,2,3,4,5,6,7" line.long 0x10 "DTPR4,DRAM Timing Parameters Register 4" bitfld.long 0x10 28.--29. " TAOND_TAOFD ,ODT turn-on/turn-off delays" "0,1,2,3" hexmask.long.word 0x10 16.--25. 1. " TRFC ,Refresh-to-refresh" bitfld.long 0x10 8.--13. " TWLO ,Write leveling output delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 0.--4. " TXP ,Power down exit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "DTPR5,DRAM Timing Parameters Register 5" hexmask.long.byte 0x14 16.--23. 1. " TRC ,Activate to activate command delay same bank" hexmask.long.byte 0x14 8.--14. 1. " TRCD ,Activate to read or write delay" bitfld.long 0x14 0.--4. " TWTR ,Internal write to read command delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "DTPR6,DRAM Timing Parameters Register 6" bitfld.long 0x18 31. " PUBWLEN ,PUB write latency enable" "Disabled,Enabled" bitfld.long 0x18 30. " PUBRLEN ,PUB read latency enable" "Disabled,Enabled" bitfld.long 0x18 8.--13. " PUBWL ,Write latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " PUBRL ,Read latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x140++0x0B line.long 0x00 "RDIMMGCR0,RDIMM General Configuration Register 0" bitfld.long 0x00 30. " QCSEN ,RDMIMM quad CS enable" "Disabled,Enabled" bitfld.long 0x00 27. " RDIMMIOM ,RDIMM outputs I/O mode" "Disabled,Enabled" bitfld.long 0x00 23. " ERROUTOE ,ERROUT# output enable" "Disabled,Enabled" bitfld.long 0x00 22. " ERROUTIOM ,ERROUT# I/O mode" "Disabled,Enabled" newline bitfld.long 0x00 21. " ERROUTPDR ,ERROUT# power down receiver" "No,Yes" bitfld.long 0x00 19. " ERROUTODT ,ERROUT# on-die termination" "Disabled,Enabled" bitfld.long 0x00 18. " LRDIMM ,Load reduced DIMM" "Disabled,Enabled" bitfld.long 0x00 17. " PARINIOM ,PAR_IN I/O mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " RNKMRREN ,Rank mirror enable" "Disabled,Enabled" bitfld.long 0x00 2. " SOPERR ,Stop on parity error" "Disabled,Enabled" bitfld.long 0x00 1. " ERRNOREG ,Parity error no registering" "No,Yes" bitfld.long 0x00 0. " RDIMM ,Registered DIMM" "Not registered,Registered" line.long 0x04 "RDIMMGCR1,RDIMM General Configuration Register 1" bitfld.long 0x04 28. " A17BID ,Address [17] B-side inversion disable" "No,Yes" bitfld.long 0x04 24.--26. " TBCMRD_L2 ,Command word to command word programming delay" "0,1,2,3,4,5,6,7" bitfld.long 0x04 20.--22. " TBCMRD_L ,Command word to command word programming delay" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " TBCMRD ,Command word to command word programming delay" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x04 0.--13. 1. " TBCSTAB ,Stabilization time" line.long 0x08 "RDIMMGCR2,RDIMM General Configuration Register 2" group.long 0x150++0x13 line.long 0x00 "RDIMMCR0,RDIMM Control Register 0" bitfld.long 0x00 28.--31. " RC7 ,DDR3 control word 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " RC5 ,DDR3 CK driver characteristics control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " RC4 ,DDR3 control signals driver characteristics control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " RC3 ,DDR3 control signals driver characteristics control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " RC2 ,DDR3 timing control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " RC1 ,DDR3 clock driver enable control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RC0 ,DDR3 global features control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "RDIMMCR1,RDIMM Control Register 1" bitfld.long 0x04 28.--31. " RC15 ,Control word 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 12.--15. " RC11 ,DDR3 operation voltage VDD control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " RC10 ,DDR3 RDIMM operating speed control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " RC9 ,DDR3 power saving settings control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " RC8 ,DDR3 additional input bus termination setting control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "RDIMMCR2,RDIMM Control Register 2" hexmask.long.byte 0x08 24.--31. 1. " RC4X ,Control word RC4X" hexmask.long.byte 0x08 16.--23. 1. " RC3X ,Control word RC3X" hexmask.long.byte 0x08 8.--15. 1. " RC2X ,Control word RC2X" hexmask.long.byte 0x08 0.--7. 1. " RC1X ,Control word RC1X" line.long 0x0C "RDIMMCR3,RDIMM Control Register 3" hexmask.long.byte 0x0C 24.--31. 1. " RC8X ,Control word RC8X" hexmask.long.byte 0x0C 16.--23. 1. " RC7X ,Control word RC7X" hexmask.long.byte 0x0C 8.--15. 1. " RC6X ,Control word RC6X" hexmask.long.byte 0x0C 0.--7. 1. " RC5X ,Control word RC5X" line.long 0x10 "RDIMMCR4,RDIMM Control Register 4" hexmask.long.byte 0x10 16.--23. 1. " RCBX ,Control word RC11X" hexmask.long.byte 0x10 8.--15. 1. " RCAX ,Control word RC10X" hexmask.long.byte 0x10 0.--7. 1. " RC9X ,Control word RC9X" group.long 0x168++0x07 line.long 0x00 "SCHCR0,Scheduler Command Register 0" hexmask.long.word 0x00 16.--24. 1. " SCHDQV ,Scheduler command DQ value" bitfld.long 0x00 8.--11. " SP_CMD ,Special command codes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CMD ,Specifies the command to be issued" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " SCHTRIG ,Mode register command trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SCHCR1,Scheduler Command Register 1" bitfld.long 0x04 28.--31. " SCRNK ,Scheduler rank address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x04 8.--27. 0x01 " SCADDR ,Scheduler command address specifies the value to be driven on the address bus" bitfld.long 0x04 6.--7. " SCBG ,Scheduler command bank group" "0,1,2,3" bitfld.long 0x04 4.--5. " SCBK ,Scheduler command bank address" "0,1,2,3" newline bitfld.long 0x04 2. " ALLRANK ,All ranks enabled" "Disabled,Enabled" group.long 0x180++0x0F line.long 0x00 "MR0,LPDDR4 Mode Register 0" bitfld.long 0x00 7. " CATR ,CA terminating rank" "0,1" bitfld.long 0x00 3.--4. " RZQI ,Built-in self-test for RZQ" "0,1,2,3" line.long 0x04 "MR1,LPDDR4 Mode Register 1" bitfld.long 0x04 7. " RDPST ,Read postamble length" "0,1" bitfld.long 0x04 4.--6. " NWR ,Write-recovery for auto-precharge command" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3. " RDPRE ,Read preamble length" "0,1" bitfld.long 0x04 2. " WRPRE ,Write preamble length" "0,1" newline bitfld.long 0x04 0.--1. " BL ,Burst length" "0,1,2,3" line.long 0x08 "MR2,LPDDR4 Mode Register 2" bitfld.long 0x08 7. " WRL ,Write leveling" "Disabled,Enabled" bitfld.long 0x08 6. " WLS ,Write latency set" "0,1" bitfld.long 0x08 3.--5. " WL ,Write latency" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0.--2. " RL ,Read latency" "0,1,2,3,4,5,6,7" line.long 0x0C "MR3,LPDDR4 Mode Register 3" bitfld.long 0x0C 7. " DBIWR ,DBI-write enable" "Disabled,Enabled" bitfld.long 0x0C 6. " DBIRD ,DBI-read enable" "Disabled,Enabled" bitfld.long 0x0C 3.--5. " PDDS ,Pull-down drive strength" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 1. " WRPST ,Write postamble length" "0,1" newline bitfld.long 0x0C 0. " PUCAL ,Pull-up calibration point" "0,1" group.long 0x1AC++0x0F line.long 0x00 "MR11,LPDDR4 Mode Register 11" bitfld.long 0x00 4.--6. " CAODT ,CA bus receiver on-die-termination" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " DQODT ,DQ bus receiver on-die-termination" "0,1,2,3,4,5,6,7" line.long 0x04 "MR12,LPDDR4 Mode Register 12" bitfld.long 0x04 6. " VR_CA ,VREF_CA range select" "0,1" bitfld.long 0x04 0.--5. " VREF_CA ,Controls the VREF_CA levels for frequency-set-point[1:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "MR13,LPDDR4 Mode Register 13" bitfld.long 0x08 7. " FSPOP ,Frequency set point operation mode" "0,1" bitfld.long 0x08 6. " FSPWR ,Frequency set point write enable" "Disabled,Enabled" bitfld.long 0x08 5. " DMD ,Data mask enable" "Disabled,Enabled" bitfld.long 0x08 4. " RRO ,Refresh rate option" "0,1" newline bitfld.long 0x08 3. " VRCG ,VREF current generator" "0,1" bitfld.long 0x08 2. " VRO ,VREF output" "0,1" bitfld.long 0x08 1. " RPT ,Read preamble training mode" "Disabled,Enabled" bitfld.long 0x08 0. " CBT ,Command bus training" "Disabled,Enabled" line.long 0x0C "MR14,LPDDR4 Mode Register 14" bitfld.long 0x0C 6. " VR_DQ ,VREFDQ range selects" "0,1" group.long 0x1D8++0x03 line.long 0x00 "MR22,LPDDR4 Mode Register 22" bitfld.long 0x00 5. " ODTD_CA ,CA ODT termination disable" "No,Yes" bitfld.long 0x00 4. " ODTE_CS ,ODT CS override" "No override,Override" bitfld.long 0x00 3. " ODTE_CK ,ODT CK override" "No override,Override" bitfld.long 0x00 0.--2. " CODT ,Controller ODT value for VOH calibration" "0,1,2,3,4,5,6,7" group.long 0x200++0x13 line.long 0x00 "DTCR0,Data Training Configuration Register 0" bitfld.long 0x00 28.--31. " RFSHDT ,Refresh during training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--25. " DTDRS ,Data training debug rank select" "0,1,2,3" bitfld.long 0x00 23. " DTEXG ,Data training with early/extended gate" "Disabled,Enabled" bitfld.long 0x00 22. " DTEXD ,Data training extended write DQS" "Disabled,Enabled" newline bitfld.long 0x00 21. " DTDSTP ,Data training debug step" "0,1" bitfld.long 0x00 20. " DTDEN ,Data training debug enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " DTDBS ,Data training debug byte select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " DTRDBITR ,Data training read DBI deskewing configuration" "0,1,2,3" newline bitfld.long 0x00 13. " DTBDC ,Data training bit deskew centering" "0,1" bitfld.long 0x00 12. " DTWBDDM ,Data training write bit deskew data mask" "Not masked,Masked" bitfld.long 0x00 8.--11. " RFSHEN ,Refreshes issued during entry to training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " DTCMPD ,Data training compare data" "0,1" newline bitfld.long 0x00 6. " DTMPR ,Data training using MPR" "Disabled,Enabled" bitfld.long 0x00 4. " INCWEYE ,WEYE training using MPC FIFO commands" "0,1" bitfld.long 0x00 0.--3. " DTRPTN ,Data training repeat number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DTCR1,Data Training Configuration Register 1" bitfld.long 0x04 16. " RANKEN ,Rank enable" "Disabled,Enabled" bitfld.long 0x04 12.--13. " DTRANK ,Data training rank" "0,1,2,3" bitfld.long 0x04 8.--10. " RDLVLGDIFF ,Read leveling gate sampling difference" "0,1,2,3,4,5,6,7" bitfld.long 0x04 4.--6. " RDLVLGS ,Read leveling gate shift" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 2. " RDPRMVL_TRN ,Read preamble training enable" "Disabled,Enabled" bitfld.long 0x04 1. " RDLVLEN ,Read leveling enable" "Disabled,Enabled" bitfld.long 0x04 0. " BSTEN ,Basic gate training enable" "Disabled,Enabled" line.long 0x08 "DTAR0,Data Training Address Register 0" bitfld.long 0x08 28.--29. " MPRLOC ,Multi-Purpose register MPR location" "0,1,2,3" hexmask.long.byte 0x08 24.--27. 0x01 " DTBGBK1 ,Data training bank group and bank address" hexmask.long.byte 0x08 20.--23. 0x10 " DTBGBK0 ,Data training bank group and bank address" hexmask.long.tbyte 0x08 0.--17. 0x01 " DTROW ,Data training row address" line.long 0x0C "DTAR1,Data Training Address Register 1" hexmask.long.word 0x0C 16.--24. 0x01 " DTCOL1 ,Data training column address" hexmask.long.word 0x0C 0.--8. 0x01 " DTCOL0 ,Data training column address" line.long 0x10 "DTAR2,Data Training Address Register 2" hexmask.long.word 0x10 16.--24. 0x01 " DTCOL3 ,Data training column address" hexmask.long.word 0x10 0.--8. 0x01 " DTCOL2 ,Data training column address" group.long 0x218++0x07 line.long 0x00 "DTDR0,Data Training Data Register 0" hexmask.long.byte 0x00 24.--31. 1. " DTBYTE3 ,Data training data" hexmask.long.byte 0x00 16.--23. 1. " DTBYTE2 ,Data training data" hexmask.long.byte 0x00 8.--15. 1. " DTBYTE1 ,Data training data" hexmask.long.byte 0x00 0.--7. 1. " DTBYTE0 ,Data training data" line.long 0x04 "DTDR1,Data Training Data Register 1" hexmask.long.byte 0x04 24.--31. 1. " DTBYTE7 ,Data training data" hexmask.long.byte 0x04 16.--23. 1. " DTBYTE6 ,Data training data" hexmask.long.byte 0x04 8.--15. 1. " DTBYTE5 ,Data training data" hexmask.long.byte 0x04 0.--7. 1. " DTBYTE4 ,Data training data" rgroup.long 0x230++0x0F line.long 0x00 "DTEDR0,Data Training Eye Data Register 0" hexmask.long.byte 0x00 24.--31. 1. " WDQMBX ,Data training write BDL shift maximum" bitfld.long 0x00 18.--23. " WDQBMN ,Data training write BDL shift minimum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 9.--17. 1. " WDQLMX ,Data training WDQ LCDL maximum" hexmask.long.word 0x00 0.--8. 1. " WDQLMN ,Data training WDQ LCDL minimum" line.long 0x04 "DTEDR1,Data Training Eye Data Register 1" hexmask.long.byte 0x04 24.--31. 1. " RDQSBMX ,Data training read BDL shift maximum" bitfld.long 0x04 18.--23. " RDQSBMN ,Data training read BDL shift minimum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x04 9.--17. 1. " RDQSLMX ,Data training RDQS LCDL maximum" hexmask.long.word 0x04 0.--8. 1. " RDQSLMN ,Data training RDQS LCDL minimum" line.long 0x08 "DTEDR2,Data Training Eye Data Register 2" hexmask.long.byte 0x08 24.--31. 1. " RDQSNBMX ,Data training read BDL shift maximum" bitfld.long 0x08 18.--23. " RDQSNBMN ,Data training read BDL shift minimum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x08 9.--17. 1. " RDQSNLMX ,Data training RDQSN LCDL maximum" hexmask.long.word 0x08 0.--8. 1. " RDQSNLMN ,Data training RDQSN LCDL minimum" line.long 0x0C "VTDR,VREF Training Data Register" hexmask.long.byte 0x0C 24.--30. 1. " HVREFMX ,DRAM DQ VREF maximum" hexmask.long.byte 0x0C 16.--22. 1. " HVREFMN ,DRAM DQ VREF minimum" bitfld.long 0x0C 8.--13. " DVREFMX ,DRAM DQ VREF maximum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " DVREFMN ,DRAM DQ VREF minimum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x240++0x0B line.long 0x00 "CATR0,CA Training Register 0" bitfld.long 0x00 16.--20. " CACD ,Minimum time between two consecutive CA calibration command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " CAADR ,Minimum wait time before sampling the CA response after calibration command has been sent to the memory" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " CA1BYTE1 ,CA_1 response byte lane 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CA1BYTE0 ,CA_1 response byte lane 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "CATR1,CA Training Register 1" bitfld.long 0x04 24.--27. " CA0BYTE1 ,CA_0 response byte lane 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 20.--23. " CA0BYTE0 ,CA_0 response byte lane 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " CAMRZ ,Minimum time for DRAM DQ going tristate after MRW CA exit calibration command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 12.--15. " CACKEH ,Minimum time for CKE high after last CA calibration response is driven by memory" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " CACKEL ,Minimum time for CKE going low after CA calibration mode is programmed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " CAEXT ,Minimum time for CA calibration exit command after CKE is high" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CAENT ,Minimum time for first CA calibration command after CKE is low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "PGCR8,PHY General Configuration Register 8" bitfld.long 0x08 28.--31. " CF ,Counter cycles factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x08 20.--27. 1. " CM ,Counter cycle multiplier" bitfld.long 0x08 16. " RANKEN ,Rank enable" "Disabled,Enabled" bitfld.long 0x08 15. " MODE ,Self incremental DQS2DQ training" "Disabled,Enabled" newline bitfld.long 0x08 14. " EN ,Incremental DQS2DQ training" "Disabled,Enabled" bitfld.long 0x08 8. " BSWAPMSB[8] ,PHY 8 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" bitfld.long 0x08 7. " [7] ,PHY 7 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" bitfld.long 0x08 6. " [6] ,PHY 6 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" newline bitfld.long 0x08 5. " [5] ,PHY 5 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" bitfld.long 0x08 4. " [4] ,PHY 4 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" bitfld.long 0x08 3. " [3] ,PHY 3 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" bitfld.long 0x08 2. " [2] ,PHY 2 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" newline bitfld.long 0x08 1. " [1] ,PHY 1 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" bitfld.long 0x08 0. " [0] ,PHY 0 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" group.long 0x250++0x0B line.long 0x00 "DQSDR0,DQS Drift Register 0" bitfld.long 0x00 28.--31. " DFTDLY ,Number of delay taps by which the DQS gate LCDL will be updated when DQS drift is detected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. " DFTZQUP ,Drift impedance update" "Not updated,Updated" bitfld.long 0x00 26. " DFTDDLUP ,Drift DDL update" "Not updated,Updated" bitfld.long 0x00 20.--21. " DFTRDSPC ,Drift read spacing" "0,1,2,3" newline bitfld.long 0x00 16.--19. " DFTB2BRD ,Drift back-to-back reads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DFTIDLRD ,Drift idle reads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DFTGPULSE ,Gate pulse enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--3. " DFTUPMODE ,DQS drift update mode" "0,1,2,3" newline bitfld.long 0x00 1. " DFTDTMODE ,DQS drift detection mode" "0,1" bitfld.long 0x00 0. " DFTDTEN ,DQS drift detection enable" "Disabled,Enabled" line.long 0x04 "DQSDR1,DQS Drift Register 1" bitfld.long 0x04 29.--31. " DFTUPDACKF ,Drift DFU update request ACK to DQS drift FSM issuing IDLE read cycles factor" "0,1,2,3,4,5,6,7" bitfld.long 0x04 24.--28. " DFTUPDACKC ,Drift DFI update request ACK to DQS drift FSM issuing IDLE read cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 20.--23. " DFTRDB2BF ,Drift Back-to-Back read cycles factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " DFTRDIDLF ,Drift idle read cycles factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x04 8.--15. 1. " DFTRDB2BC ,Drift Back-to-Back read cycles" hexmask.long.byte 0x04 0.--7. 1. " DFTRDIDLC ,Drift idle read cycles" line.long 0x08 "DQSDR2,DQS Drift Register 2" hexmask.long.byte 0x08 16.--23. 1. " DFTTHRSH ,Drift threshold" hexmask.long.word 0x08 0.--15. 1. " DFTMNTPRD ,Drift monitor period" group.long 0x300++0x17 line.long 0x00 "DCUAR,DCU Address Register" hexmask.long.byte 0x00 16.--19. 0x01 " CSADDR_R ,Cache slice address" hexmask.long.byte 0x00 12.--15. 0x10 " CWADDR_R ,Cache word address" bitfld.long 0x00 11. " ATYPE ,Access type" "0,1" bitfld.long 0x00 10. " INCA ,Increment address" "0,1" newline bitfld.long 0x00 8.--9. " CSEL ,Cache select" "0,1,2,3" hexmask.long.byte 0x00 4.--7. 0x10 " CSADDR_W ,Cache slice address" hexmask.long.byte 0x00 0.--3. 0x01 " CWADDR_W ,Cache word address" line.long 0x04 "DCUDR,DCU Data Register" line.long 0x08 "DCURR,DCU Run Register" bitfld.long 0x08 23. " XCEN ,Expected compare enable" "Disabled,Enabled" bitfld.long 0x08 22. " RCEN ,Read capture enable" "Disabled,Enabled" bitfld.long 0x08 21. " SCOF ,Stop capture on full" "0,1" bitfld.long 0x08 20. " SONF ,Stop on n-th fail" "0,1" newline hexmask.long.byte 0x08 12.--19. 1. " NFAIL ,Number of failures" hexmask.long.byte 0x08 8.--11. 0x01 " EADDR ,End address" hexmask.long.byte 0x08 4.--7. 0x10 " SADDR ,Start address" bitfld.long 0x08 0.--3. " DINST ,DCU instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "DCULR,DCU Loop Register" hexmask.long.byte 0x0C 28.--31. 0x10 " XLEADDR ,Expected data loop end address" bitfld.long 0x0C 17. " IDA ,Increment DRAM address" "0,1" bitfld.long 0x0C 16. " LINF ,Loop infinite" "0,1" hexmask.long.byte 0x0C 8.--15. 1. " LCNT ,Loop count" newline hexmask.long.byte 0x0C 4.--7. 0x10 " LEADDR ,Loop end address" hexmask.long.byte 0x0C 0.--3. 0x01 " LSADDR ,Loop start address" line.long 0x10 "DCUGCR,DCU General Configuration Register" hexmask.long.word 0x10 0.--15. 1. " RCSW ,Read capture start word" line.long 0x14 "DCUTPR,DCU Timing Parameters Register" hexmask.long.word 0x14 16.--31. 1. " TDCUT2 ,DCU generic timing parameter 2" hexmask.long.byte 0x14 8.--15. 1. " TDCUT1 ,DCU generic timing parameter 1" hexmask.long.byte 0x14 0.--7. 1. " TDCUT0 ,DCU generic timing parameter 0" rgroup.long 0x318++0x07 line.long 0x00 "DCUSR0,DCU Status Register 0" bitfld.long 0x00 2. " CFULL ,Capture full" "Not full,Full" bitfld.long 0x00 1. " CFAIL ,Capture fail" "Not failed,Failed" bitfld.long 0x00 0. " RDONE ,Run done" "Not done,Done" line.long 0x04 "DCUSR1,DCU Status Register 1" hexmask.long.byte 0x04 24.--31. 1. " LPCNT ,Loop count" hexmask.long.byte 0x04 16.--23. 1. " FLCNT ,Fail count" hexmask.long.word 0x04 0.--15. 1. " RDCNT ,Read count" group.long 0x400++0x2F line.long 0x00 "BISTRR,BIST Run Register" bitfld.long 0x00 29. " BPRBST ,BIST PRBS type" "0,1" bitfld.long 0x00 28. " BSOMA ,BIST stop on maximum address" "Disabled,Enabled" bitfld.long 0x00 26.--27. " BACDPAT ,BIST AC data pattern" "0,1,2,3" bitfld.long 0x00 25. " BCCSEL ,BIST clock cycle select" "0,1" newline bitfld.long 0x00 23.--24. " BCKSEL ,BIST CK select" "0,1,2,3" bitfld.long 0x00 19.--22. " BDXSEL ,BIST DATX8 select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 17.--18. " BDXDPAT ,BIST data pattern" "0,1,2,3" bitfld.long 0x00 16. " BDMEN ,BIST data mask enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " BACEN ,BIST AC enable" "Disabled,Enabled" bitfld.long 0x00 14. " BDXEN ,BIST DATX8 enable" "Disabled,Enabled" bitfld.long 0x00 13. " BSONF ,BIST stop on nth fail" "Disabled,Enabled" hexmask.long.word 0x00 5.--12. 1. " NFAIL ,Number of failures" newline bitfld.long 0x00 4. " BINF ,BIST infinite run" "0,1" bitfld.long 0x00 3. " BMODE ,BIST mode" "0,1" bitfld.long 0x00 0.--2. " BINST ,BIST instruction" "0,1,2,3,4,5,6,7" line.long 0x04 "BISTWCR,BIST Word Count Register" hexmask.long.word 0x04 16.--31. 1. " BACWCNT ,BIST AC word count" hexmask.long.word 0x04 0.--15. 1. " BDXWCNT ,BIST DX word count" newline line.long 0x08 "BISTMSKR0,BIST Mask Register 0" bitfld.long 0x08 20. " CSMSK ,Mask bit for CS_N bit 0" "0,1" bitfld.long 0x08 19. " ACTMSK ,Mask bit for the RAS" "0,1" newline bitfld.long 0x08 17. " AMSK[17:0] ,Mask bit for address bit 17" "0,1" bitfld.long 0x08 16. ",Mask bit for address bit 16" "0,1" bitfld.long 0x08 15. ",Mask bit for address bit 15" "0,1" bitfld.long 0x08 14. ",Mask bit for address bit 14" "0,1" bitfld.long 0x08 13. ",Mask bit for address bit 13" "0,1" bitfld.long 0x08 12. ",Mask bit for address bit 12" "0,1" bitfld.long 0x08 11. ",Mask bit for address bit 11" "0,1" bitfld.long 0x08 10. ",Mask bit for address bit 10" "0,1" bitfld.long 0x08 9. ",Mask bit for address bit 9" "0,1" bitfld.long 0x08 8. ",Mask bit for address bit 8" "0,1" bitfld.long 0x08 7. ",Mask bit for address bit 7" "0,1" bitfld.long 0x08 6. ",Mask bit for address bit 6" "0,1" bitfld.long 0x08 5. ",Mask bit for address bit 5" "0,1" bitfld.long 0x08 4. ",Mask bit for address bit 4" "0,1" bitfld.long 0x08 3. ",Mask bit for address bit 3" "0,1" bitfld.long 0x08 2. ",Mask bit for address bit 2" "0,1" bitfld.long 0x08 1. ",Mask bit for address bit 1" "0,1" bitfld.long 0x08 0. ",Mask bit for address bit 0" "0,1" line.long 0x0C "BISTMSKR1,BIST Mask Register 1" bitfld.long 0x0C 31. " DMMSK[3] ,Mask bit for the data mask DM bit 3" "0,1" bitfld.long 0x0C 30. " [2] ,Mask bit for the data mask DM bit 2" "0,1" bitfld.long 0x0C 29. " [1] ,Mask bit for the data mask DM bit 1" "0,1" bitfld.long 0x0C 28. " [0] ,Mask bit for the data mask DM bit 0" "0,1" newline bitfld.long 0x0C 27. " PARINMSK ,Mask bit for the PAR_IN" "0,1" bitfld.long 0x0C 24. " CIDMSK ,Mask bits for chip IP bits" "0,1" bitfld.long 0x0C 16. " ODTMSK ,Mask bit for ODT bit" "0,1" bitfld.long 0x0C 8. " CKEMSK ,Mask bit for CKE bit" "0,1" newline bitfld.long 0x0C 7. " BAMSK[3] ,Mask bit for bank address bit 3" "0,1" bitfld.long 0x0C 6. " [2] ,Mask bit for bank address bit 2" "0,1" bitfld.long 0x0C 5. " [1] ,Mask bit for bank address bit 1" "0,1" bitfld.long 0x0C 4. " [0] ,Mask bit for bank address bit 0" "0,1" line.long 0x10 "BISTMSKR2,BIST Mask Register 2" newline line.long 0x14 "BISTLSR,BIST LFSR Seed Register" line.long 0x18 "BISTAR0,BIST Address Register 0" hexmask.long.byte 0x18 28.--31. 0x10 " BBANK ,BIST bank address" hexmask.long.word 0x18 0.--11. 0x01 " BCOL ,BIST column address" line.long 0x1C "BISTAR1,BIST Address Register 1" bitfld.long 0x1C 16.--19. " BMRANK ,BIST maximum rank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x1C 4.--15. 1. " BAINC ,BIST address increment" bitfld.long 0x1C 0.--3. " BRANK ,BIST rank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x20 "BISTAR2,BIST Address Register 2" hexmask.long.byte 0x20 28.--31. 0x10 " BMBANK ,BIST maximum bank address" hexmask.long.word 0x20 0.--11. 0x01 " BMCOL ,BIST maximum column address" line.long 0x24 "BISTAR3,BIST Address Register 3" hexmask.long.tbyte 0x24 0.--17. 0x01 " BROW ,BIST row address" line.long 0x28 "BISTAR4,BIST Address Register 4" hexmask.long.tbyte 0x28 0.--17. 0x01 " BMROW ,BIST maximum row address" line.long 0x2C "BISTUDPR,BIST User Data Pattern Register" hexmask.long.word 0x2C 16.--31. 1. " BUDP1 ,BIST user data pattern 1" hexmask.long.word 0x2C 0.--15. 1. " BUDP0 ,BIST user data pattern 0" rgroup.long 0x430++0x33 line.long 0x00 "BISTGSR,BIST General Status Register" bitfld.long 0x00 28.--29. " RASBER ,RAS_n/ACT_n bit error" "0,1,2,3" hexmask.long.byte 0x00 20.--27. 1. " DMBER ,DM bit error" hexmask.long.word 0x00 2.--10. 1. " BDXERR ,BIST data error" bitfld.long 0x00 1. " BACERR ,BIST address/command error" "No error,Error" newline bitfld.long 0x00 0. " BDONE ,BIST done" "Not done,Done" line.long 0x04 "BISTWER0,BIST Word Error Register 0" hexmask.long.tbyte 0x04 0.--17. 1. " ACWER ,Address/command word error" line.long 0x08 "BISTWER1,BIST Word Error Register 1" hexmask.long.word 0x08 0.--15. 1. " DXWER ,Byte word error" line.long 0x0C "BISTBER0,BIST Bit Error Register 0" line.long 0x10 "BISTBER1,BIST Bit Error Register 1" bitfld.long 0x10 8.--9. " CSBER ,CS_N bit error" "0,1,2,3" hexmask.long.byte 0x10 0.--7. 1. " BABER ,Bank address bit error" line.long 0x14 "BISTBER2,BIST Bit Error Register 2" line.long 0x18 "BISTBER3,BIST Bit Error Register 3" line.long 0x1C "BISTBER4,BIST Bit Error Register 4" bitfld.long 0x1C 8.--9. " CIDBER ,Chip ID bit error" "0,1,2,3" bitfld.long 0x1C 0.--3. " ABER ,Address bit error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x20 "BISTWCSR,BIST Word Count Status Register" hexmask.long.word 0x20 16.--31. 1. " DXWCNT ,Byte word count" hexmask.long.word 0x20 0.--15. 1. " ACWCNT ,Address/command word count" line.long 0x24 "BISTFWR0,BIST Fail Word Register 0" bitfld.long 0x24 20. " CSWEBS ,Bit status during a word error for CS# bits" "No error,Error" bitfld.long 0x24 18. " ACTWEBS ,Bit status during a word error for the RAS" "No error,Error" hexmask.long.tbyte 0x24 0.--17. 1. " AWEBS ,Bit status during a word error for address bits" line.long 0x28 "BISTFWR1,BIST Fail Word Register 1" bitfld.long 0x28 31. " DMWEBS[3] ,Bit status during a word error for the data mask DM bit 3" "No error,Error" bitfld.long 0x28 30. " [2] ,Bit status during a word error for the data mask DM bit 2" "No error,Error" bitfld.long 0x28 29. " [1] ,Bit status during a word error for the data mask DM bit 1" "No error,Error" bitfld.long 0x28 28. " [0] ,Bit status during a word error for the data mask DM bit 0" "No error,Error" newline bitfld.long 0x28 20. " CIDWEBS ,Bit status during a word error for chip ID bits" "No error,Error" bitfld.long 0x28 19. " BAWEBS[3] ,Bit status during a word error for the bank address bit 3" "No error,Error" bitfld.long 0x28 18. " [2] ,Bit status during a word error for the bank address bit 2" "No error,Error" bitfld.long 0x28 17. " [1] ,Bit status during a word error for the bank address bit 1" "No error,Error" newline bitfld.long 0x28 16. " [0] ,Bit status during a word error for the bank address bit 0" "No error,Error" bitfld.long 0x28 8. " ODTWEBS ,Bit status during a word error for the ODT bits" "No error,Error" bitfld.long 0x28 0. " CKEWEBS ,Bit status during a word error for the CKE bits" "No error,Error" line.long 0x2C "BISTFWR2,BIST Fail Word Register 2" line.long 0x30 "BISTBER5,BIST Bit Error Register 5" bitfld.long 0x30 16.--17. " ODTBER ,ODT bit error" "0,1,2,3" bitfld.long 0x30 0.--1. " CKEBER ,CKE bit error" "0,1,2,3" group.long 0x4DC++0x03 line.long 0x00 "RANKIDR,Rank ID Register" bitfld.long 0x00 16.--19. " RANKRID ,Rank read ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RANKWID ,Rank write ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4E8++0x03 line.long 0x00 "RIOCR2,Rank I/O Configuration Register 2" bitfld.long 0x00 24.--25. " COEMODE ,SDRAM C output enable (OE) mode selection" "0,1,2,3" bitfld.long 0x00 0.--1. " CSOEMODE ,SDRAM CS_n output enable (OE) mode selection" "0,1,2,3" group.long 0x4F0++0x07 line.long 0x00 "RIOCR4,Rank I/O Configuration Register 4" bitfld.long 0x00 0.--1. " CKEOEMODE ,SDRAM CKE output enable (OE) mode selection" "0,1,2,3" line.long 0x04 "RIOCR5,Rank I/O Configuration Register 5" bitfld.long 0x04 0.--1. " ODTOEMODE ,SDRAM On-die termination output enable (OE) mode selection" "0,1,2,3" newline group.long 0x500++0x17 line.long 0x00 "ACIOCR0,AC I/O Configuration Register 0" bitfld.long 0x00 30.--31. " ACSR ,Address/command slew rate (D3F I/O only)" "0,1,2,3" bitfld.long 0x00 29. " RSTIOM ,SDRAM reset I/O mode" "0,1" bitfld.long 0x00 28. " RSTPDR ,SDRAM reset power down receiver" "0,1" bitfld.long 0x00 26. " RSTODT ,SDRAM reset on-die termination" "0,1" newline hexmask.long.byte 0x00 16.--23. 1. " ESR ,Decoupling capacitance ESR control in D5M I/O ring" bitfld.long 0x00 10.--11. " ACPNUMSEL ,Address/command custom pin mapping configuration" "0,1,2,3" bitfld.long 0x00 6.--9. " CKDCC ,CK duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--5. " ACPDRMODE ,AC power down receiver mode" "0,1,2,3" newline bitfld.long 0x00 2.--3. " ACODTMODE ,AC on-die termination mode" "0,1,2,3" bitfld.long 0x00 0. " ACRANKCLKSEL ,Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices" "0,1" line.long 0x04 "ACIOCR1,AC I/O Configuration Register 1" line.long 0x08 "ACIOCR2,AC I/O Configuration Register 2" bitfld.long 0x08 31. " CLKGENCLKGATE ,Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL slice" "No gating,Gating" bitfld.long 0x08 30. " ACOECLKGATE0 ,Clock gating for output enable D slices [0]" "No gating,Gating" bitfld.long 0x08 29. " ACPDRCLKGATE0 ,Clock gating for power down receiver D slices [0]" "No gating,Gating" bitfld.long 0x08 28. " ACTECLKGATE0 ,Clock gating for termination enable D slices [0]" "No gating,Gating" newline bitfld.long 0x08 26.--27. " CKNCLKGATE0 ,Clock gating for CK# D slices [1:0]" "0,1,2,3" bitfld.long 0x08 24.--25. " CKCLKGATE0 ,Clock gating for CK D slices [1:0]" "0,1,2,3" hexmask.long.tbyte 0x08 0.--23. 1. " ACCLKGATE0 ,Clock gating for AC D slices [23:0]" line.long 0x0C "ACIOCR3,AC I/O Configuration Register 3" bitfld.long 0x0C 30.--31. " PAROEMODE ,SDRAM parity output enable (OE) mode selection" "0,1,2,3" bitfld.long 0x0C 26.--29. " BGOEMODE ,SDRAM bank group output enable (OE) mode selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 22.--25. " BAOEMODE ,SDRAM bank address output enable (OE) mode selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 20.--21. " A17OEMODE ,SDRAM A[17] output enable (OE) mode selection" "0,1,2,3" newline bitfld.long 0x0C 18.--19. " A16OEMODE ,SDRAM A[16] / RAS_N output enable (OE) mode selection" "0,1,2,3" bitfld.long 0x0C 16.--17. " ACTOEMODE ,SDRAM ACT_N output enable (OE) mode selection" "0,1,2,3" bitfld.long 0x0C 0.--3. " CKOEMODE ,SDRAM CK output enable (OE) mode selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "ACIOCR4,AC I/O Configuration Register 4" bitfld.long 0x10 31. " LBCLKGATE ,Clock gating for AC LB slices and loopback read valid slices" "No gating,Gating" bitfld.long 0x10 30. " ACOECLKGATE1 ,Clock gating for output enable D slices [1]" "No gating,Gating" bitfld.long 0x10 29. " ACPDRCLKGATE1 ,Clock gating for power down receiver D slices [1]" "No gating,Gating" bitfld.long 0x10 28. " ACTECLKGATE1 ,Clock gating for termination enable D slices [1]" "No gating,Gating" newline bitfld.long 0x10 26.--27. " CKNCLKGATE1 ,Clock gating for CK# D slices [3:2]" "0,1,2,3" bitfld.long 0x10 24.--25. " CKCLKGATE1 ,Clock gating for CK D slices [3:2]" "0,1,2,3" hexmask.long.tbyte 0x10 0.--23. 1. " ACCLKGATE1 ,Clock gating for AC D slices [47:24]" line.long 0x14 "ACIOCR5,AC I/O Configuration Register 5" bitfld.long 0x14 25.--27. " ACVREFIOM ,IOM bits for PVREF and PVREFE cells in AC IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x14 22.--24. " ACXIOM ,AC IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x14 11.--21. 1. " ACTXM ,AC IO transmitter mode" hexmask.long.word 0x14 0.--10. 1. " ACRXM ,AC IO receiver mode" group.long 0x520++0x03 line.long 0x00 "IOVCR0,IO VREF Control Register 0" bitfld.long 0x00 28. " ACREFPEN ,Address/command lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x00 26.--27. " ACREFEEN ,Address/command lane internal VREF enable" "0,1,2,3" bitfld.long 0x00 25. " ACREFSEN ,Address/command lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x00 24. " ACREFIEN ,Address/command lane internal VREF enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " ACREFESELRANGE ,External VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x00 16.--22. 1. " ACREFESEL ,Address/command lane external VREF select" bitfld.long 0x00 15. " ACREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x00 8.--14. 1. " ACREFSSEL ,Address/command lane single-end VREF select" newline bitfld.long 0x00 7. " ACVREFISELRANGE ,Internal VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x00 0.--6. 1. " ACVREFISEL ,REFSEL control for internal AC IOs" group.long 0x528++0x07 line.long 0x00 "VTCR0,VREF Training Control Register 0" bitfld.long 0x00 29.--31. " TVREF ,Number of CTL_CLK required to meet > 150ns timing requirements during DRAM DQ VREF training" "0,1,2,3,4,5,6,7" bitfld.long 0x00 28. " DVEN ,DRM DQ VREF training enable" "Disabled,Enabled" bitfld.long 0x00 27. " PDAEN ,Per device addressability enable" "Disabled,Enabled" bitfld.long 0x00 22.--25. " VWCR ,VREF word count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 18.--21. " DVSS ,DRAM DQ VREF step size used during DRAM VREF training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--17. " DVMAX ,Maximum VREF limit value used during DRAM VREF training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 6.--11. " DVMIN ,Minimum VREF limit value used during DRAM VREF training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DVINIT ,Initial DRAM DQ VREF value used during DRAM VREF training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "VTCR1,VREF Training Control Register 1" bitfld.long 0x04 28.--31. " HVSS ,Host VREF step size used during VREF training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x04 20.--26. 1. " HVMAX ,Maximum VREF limit value used during DRAM VREF training" hexmask.long.byte 0x04 12.--18. 1. " HVMIN ,Minimum VREF limit value used during DRAM VREF training" bitfld.long 0x04 9.--10. " SHRNK ,Static host VREF rank value" "0,1,2,3" newline bitfld.long 0x04 8. " SHREN ,Static host VREF rank enable" "Disabled,Enabled" bitfld.long 0x04 5.--7. " TVREFIO ,Number of CTL_CLK required to meet > 200ns VREF settling timing requirements during host IO VREF training" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3.--4. " EOFF ,Eye LCDL offset value for VREF training" "0,1,2,3" bitfld.long 0x04 2. " ENUM ,Number of LCDL eye points for which VREF training is repeated" "0,1" newline bitfld.long 0x04 1. " HVEN ,HOST IO internal VREF training enable" "Disabled,Enabled" bitfld.long 0x04 0. " HVIO ,Host IO type control" "0,1" newline group.long 0x540++0x47 line.long 0x00 "ACBDLR0,AC Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " CK3BD ,CK3 bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " CK2BD ,CK2 bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CK1BD ,CK1 bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CK0BD ,CK0 bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "ACBDLR1,AC Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " PARBD ,Delay select for the BDL on parity" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " A16BD ,Delay select for the BDL on address A[16]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " A17BD ,Delay select for the BDL on address A[17]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " ACTBD ,Delay select for the BDL on ACTN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "ACBDLR2,AC Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " BG1BD ,Delay select for the BDL on BG[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " BG0BD ,Delay select for the BDL on BG[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " BA1BD ,Delay select for the BDL on BA[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " BA0BD ,Delay select for the BDL on BA[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "ACBDLR3,AC Bit Delay Line Register 3" bitfld.long 0x0C 24.--29. " CS3BD ,Delay select for the BDL on CS[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " CS2BD ,Delay select for the BDL on CS[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 8.--13. " CS1BD ,Delay select for the BDL on CS[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " CS0BD ,Delay select for the BDL on CS[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "ACBDLR4,AC Bit Delay Line Register 4" bitfld.long 0x10 24.--29. " ODT3BD ,Delay select for the BDL on ODT[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 16.--21. " ODT2BD ,Delay select for the BDL on ODT[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 8.--13. " ODT1BD ,Delay select for the BDL on ODT[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 0.--5. " ODT0BD ,Delay select for the BDL on ODT[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x14 "ACBDLR5,AC Bit Delay Line Register 5" bitfld.long 0x14 24.--29. " CKE3BD ,Delay select for the BDL on CKE[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 16.--21. " CKE2BD ,Delay select for the BDL on CKE[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 8.--13. " CKE1BD ,Delay select for the BDL on CKE[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 0.--5. " CKE0BD ,Delay select for the BDL on CKE[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x18 "ACBDLR6,AC Bit Delay Line Register 6" bitfld.long 0x18 24.--29. " A03BD ,Delay select for the BDL on address A[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " A02BD ,Delay select for the BDL on address A[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " A01BD ,Delay select for the BDL on address A[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " A00BD ,Delay select for the BDL on address A[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "ACBDLR7,AC Bit Delay Line Register 7" bitfld.long 0x1C 24.--29. " A07BD ,Delay select for the BDL on address A[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1C 16.--21. " A06BD ,Delay select for the BDL on address A[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1C 8.--13. " A05BD ,Delay select for the BDL on address A[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1C 0.--5. " A04BD ,Delay select for the BDL on address A[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x20 "ACBDLR8,AC Bit Delay Line Register 8" bitfld.long 0x20 24.--29. " A11BD ,Delay select for the BDL on address A[11]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x20 16.--21. " A10BD ,Delay select for the BDL on address A[10]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x20 8.--13. " A09BD ,Delay select for the BDL on address A[9]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x20 0.--5. " A08BD ,Delay select for the BDL on address A[8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x24 "ACBDLR9,AC Bit Delay Line Register 9" bitfld.long 0x24 24.--29. " A15BD ,Delay select for the BDL on address A[15]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x24 16.--21. " A14BD ,Delay select for the BDL on address A[14]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x24 8.--13. " A13BD ,Delay select for the BDL on address A[13]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x24 0.--5. " A12BD ,Delay select for the BDL on address A[12]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x28 "ACBDLR10,AC Bit Delay Line Register 10" bitfld.long 0x28 24.--29. " CID2BD ,Delay select for the BDL on chip ID CID[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x28 16.--21. " CID1BD ,Delay select for the BDL on chip ID CID[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x28 8.--13. " CID0BD ,Delay select for the BDL on chip ID CID[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x2C "ACBDLR11,AC Bit Delay Line Register 11" bitfld.long 0x2C 24.--29. " CS7BD ,Delay select for the BDL on CS[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2C 16.--21. " CS6BD ,Delay select for the BDL on CS[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2C 8.--13. " CS5BD ,Delay select for the BDL on CS[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2C 0.--5. " CS4BD ,Delay select for the BDL on CS[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x30 "ACBDLR12,AC Bit Delay Line Register 12" bitfld.long 0x30 24.--29. " CS11BD ,Delay select for the BDL on CS[11]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x30 16.--21. " CS10BD ,Delay select for the BDL on CS[10]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x30 8.--13. " CS9BD ,Delay select for the BDL on CS[9]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x30 0.--5. " CS8BD ,Delay select for the BDL on CS[8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x34 "ACBDLR13,AC Bit Delay Line Register 13" bitfld.long 0x34 24.--29. " ODT7BD ,Delay select for the BDL on ODT[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x34 16.--21. " ODT6BD ,Delay select for the BDL on ODT[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x34 8.--13. " ODT5BD ,Delay select for the BDL on ODT[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x34 0.--5. " ODT4BD ,Delay select for the BDL on ODT[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x38 "ACBDLR14,AC Bit Delay Line Register 14" bitfld.long 0x38 24.--29. " CKE7BD ,Delay select for the BDL on CKE[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x38 16.--21. " CKE6BD ,Delay select for the BDL on CKE[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x38 8.--13. " CKE5BD ,Delay select for the BDL on CKE[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x38 0.--5. " CKE4BD ,Delay select for the BDL on CKE[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x3C "ACBDLR15,AC Bit Delay Line Register 15" bitfld.long 0x3C 16.--21. " OEBD ,Delay select for the BDL on OE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3C 8.--13. " TEBD ,Delay select for the BDL on TE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3C 0.--5. " PDRBD ,Delay select for the BDL on PDR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x40 "ACBDLR16,AC Bit Delay Line Register 16" bitfld.long 0x40 24.--29. " CKN3BD ,Delay select for the BDL on CKN[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x40 16.--21. " CKN2BD ,Delay select for the BDL on CKN[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x40 8.--13. " CKN1BD ,Delay select for the BDL on CKN[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x40 0.--5. " CKN0BD ,Delay select for the BDL on CKN[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x44 "ACLCDLR,AC Local Calibrated Delay Line Register" hexmask.long.word 0x44 16.--24. 1. " ACD1 ,Address/command delay for AC macro 1" hexmask.long.word 0x44 0.--8. 1. " ACD ,Address/command delay for AC macro 0" group.long 0x5A0++0x07 line.long 0x00 "ACMDLR0,AC Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "ACMDLR1,AC Master Delay Line Register 1" hexmask.long.word 0x04 16.--24. 1. " MDLD1 ,MDL delay for AC macro 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay for AC macro 0" newline group.long 0x680++0x03 line.long 0x00 "ZQCR,ZQ Impedance Control Register" bitfld.long 0x00 25. " ZQREFISELRANGE ,ZQ VREF range" "0,1" bitfld.long 0x00 19.--24. " PGWAIT_FRQB ,Programmable wait for frequency B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 13.--18. " PGWAIT_FRQA ,Programmable wait for frequency A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12. " ZQREFPEN ,ZQ VREF pad enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ZQREFIEN ,ZQ internal VREF enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " ODT_MODE ,Choice of termination mode" "0,1,2,3" bitfld.long 0x00 8. " FORCE_ZCAL_VT_UPDATE ,Force ZCAL VT update" "0,1" bitfld.long 0x00 5.--7. " IODLMT ,IO VT drift limit" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4. " AVGEN ,Averaging algorithm enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " AVGMAX ,Maximum number of averaging rounds to be used by averaging algorithm" "0,1,2,3" bitfld.long 0x00 1. " ZCALT ,ZQ calibration type" "0,1" bitfld.long 0x00 0. " ZQPD ,ZQ power down" "No,Yes" group.long 0x684++0x07 line.long 0x00 "ZQ0PR0,ZQ 0 Impedance Control Program Register 0" bitfld.long 0x00 31. " PD_DRV_ZDEN ,Pull-down drive strength ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 30. " PU_DRV_ZDEN ,Pull-up drive strength ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 29. " PD_ODT_ZDEN ,Pull-down termination ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 28. " PU_ODT_ZDEN ,Pull-up termination ZCTRL override enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " ZSEGBYP ,Calibration segment bypass" "Not bypassed,Bypassed" bitfld.long 0x00 25.--26. " ZLE_MODE ,VREF latch mode" "0,1,2,3" bitfld.long 0x00 22.--24. " ODT_ADJUST ,Termination adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19.--21. " PD_DRV_ADJUST ,Pull-down drive strength adjustment" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. " PU_DRV_ADJUST ,Pull-up drive strength adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--15. " ZPROG_DRAM_ODT ,DRAM impedance divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " ZPROG_HOST_ODT ,HOST impedance divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " ZPROG_ASYM_DRV_PD ,Impedance divide ratio pull-down drive calibration during asymmetric drive strength calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " ZPROG_ASYM_DRV_PU ,Impedance divide ratio (pull-up drive calibration during asymmetric drive strength calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ZQ0PR1,ZQ 0 Impedance Control Program Register 1" hexmask.long.byte 0x04 8.--14. 1. " PU_REFSEL ,Pull-up REFSEL for PZCTRL cell" hexmask.long.byte 0x04 0.--6. 1. " PD_REFSEL ,Pull-down REFSEL for PZCTRL cell" rgroup.long (0x684+0x08)++0x07 line.long 0x00 "ZQ0DR0,ZQ 0 Impedance Control Data Register 0" hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_RESULT ,Pull-up drive strength calibration code result" hexmask.long.word 0x00 0.--9. 1. " ZDATA_PD_DRV_RESULT ,Pull-down drive strength calibration code result" line.long 0x04 "ZQ0DR1,ZQ 0 Impedance Control Data Register 1" hexmask.long.word 0x04 16.--25. 1. " ZDATA_PU_ODT_RESULT ,Pull-up termination calibration code result" hexmask.long.word 0x04 0.--9. 1. " ZDATA_PD_ODT_RESULT ,Pull-down termination calibration code result" group.long (0x684+0x10)++0x07 line.long 0x00 "ZQ0OR0,ZQ 0 Impedance Control Override Data Register 0" hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_OVRD ,Override value for the pull-up output impedance" hexmask.long.word 0x00 0.--9. 1. " ZDATA_PD_DRV_OVRD ,Override value for the pull-down output impedance" line.long 0x04 "ZQ0OR1,ZQ 0 Impedance Control Override Data Register 1" hexmask.long.word 0x04 16.--25. 1. " ZDATA_PU_ODT_OVRD ,Override value for the pull-up termination" hexmask.long.word 0x04 0.--9. 1. " ZDATA_PD_ODT_OVRD ,Override value for the pull-down termination" rgroup.long (0x684+0x18)++0x03 line.long 0x00 "ZQ0SR,ZQ 0 Impedance Control Status Register" bitfld.long 0x00 13. " PD_ODT_SAT ,Pull-down drive strength code saturated due to termination strength adjustment setting in ZQ0PR" "Not saturated,Saturated" bitfld.long 0x00 12. " PU_ODT_SAT ,Pull-up drive strength code saturated due to termination strength adjustment setting in ZQ0PR" "Not saturated,Saturated" bitfld.long 0x00 11. " PD_DRV_SAT ,Pull-down drive strength code saturated due to drive strength adjustment setting in ZQ0PR" "Not saturated,Saturated" bitfld.long 0x00 10. " PU_DRV_SAT ,Pull-up drive strength code saturated due to drive strength adjustment setting in ZQ0PR" "Not saturated,Saturated" newline bitfld.long 0x00 9. " ZDONE ,Impedance calibration done" "Not done,Done" bitfld.long 0x00 8. " ZERR ,Impedance calibration error" "No error,Error" bitfld.long 0x00 6.--7. " OPU ,On-die termination ODT pull-up calibration status" "0,1,2,3" bitfld.long 0x00 4.--5. " OPD ,On-die termination ODT pull-down calibration status" "0,1,2,3" newline bitfld.long 0x00 2.--3. " ZPU ,Output impedance pull-up calibration status" "0,1,2,3" bitfld.long 0x00 0.--1. " ZPD ,Output impedance pull-down calibration status" "0,1,2,3" group.long 0x6A4++0x07 line.long 0x00 "ZQ1PR0,ZQ 1 Impedance Control Program Register 0" bitfld.long 0x00 31. " PD_DRV_ZDEN ,Pull-down drive strength ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 30. " PU_DRV_ZDEN ,Pull-up drive strength ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 29. " PD_ODT_ZDEN ,Pull-down termination ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 28. " PU_ODT_ZDEN ,Pull-up termination ZCTRL override enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " ZSEGBYP ,Calibration segment bypass" "Not bypassed,Bypassed" bitfld.long 0x00 25.--26. " ZLE_MODE ,VREF latch mode" "0,1,2,3" bitfld.long 0x00 22.--24. " ODT_ADJUST ,Termination adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19.--21. " PD_DRV_ADJUST ,Pull-down drive strength adjustment" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. " PU_DRV_ADJUST ,Pull-up drive strength adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--15. " ZPROG_DRAM_ODT ,DRAM impedance divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " ZPROG_HOST_ODT ,HOST impedance divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " ZPROG_ASYM_DRV_PD ,Impedance divide ratio pull-down drive calibration during asymmetric drive strength calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " ZPROG_ASYM_DRV_PU ,Impedance divide ratio (pull-up drive calibration during asymmetric drive strength calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ZQ1PR1,ZQ 1 Impedance Control Program Register 1" hexmask.long.byte 0x04 8.--14. 1. " PU_REFSEL ,Pull-up REFSEL for PZCTRL cell" hexmask.long.byte 0x04 0.--6. 1. " PD_REFSEL ,Pull-down REFSEL for PZCTRL cell" rgroup.long (0x6A4+0x08)++0x07 line.long 0x00 "ZQ1DR0,ZQ 1 Impedance Control Data Register 0" hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_RESULT ,Pull-up drive strength calibration code result" hexmask.long.word 0x00 0.--9. 1. " ZDATA_PD_DRV_RESULT ,Pull-down drive strength calibration code result" line.long 0x04 "ZQ1DR1,ZQ 1 Impedance Control Data Register 1" hexmask.long.word 0x04 16.--25. 1. " ZDATA_PU_ODT_RESULT ,Pull-up termination calibration code result" hexmask.long.word 0x04 0.--9. 1. " ZDATA_PD_ODT_RESULT ,Pull-down termination calibration code result" group.long (0x6A4+0x10)++0x07 line.long 0x00 "ZQ1OR0,ZQ 1 Impedance Control Override Data Register 0" hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_OVRD ,Override value for the pull-up output impedance" hexmask.long.word 0x00 0.--9. 1. " ZDATA_PD_DRV_OVRD ,Override value for the pull-down output impedance" line.long 0x04 "ZQ1OR1,ZQ 1 Impedance Control Override Data Register 1" hexmask.long.word 0x04 16.--25. 1. " ZDATA_PU_ODT_OVRD ,Override value for the pull-up termination" hexmask.long.word 0x04 0.--9. 1. " ZDATA_PD_ODT_OVRD ,Override value for the pull-down termination" rgroup.long (0x6A4+0x18)++0x03 line.long 0x00 "ZQ1SR,ZQ 1 Impedance Control Status Register" bitfld.long 0x00 13. " PD_ODT_SAT ,Pull-down drive strength code saturated due to termination strength adjustment setting in ZQ1PR" "Not saturated,Saturated" bitfld.long 0x00 12. " PU_ODT_SAT ,Pull-up drive strength code saturated due to termination strength adjustment setting in ZQ1PR" "Not saturated,Saturated" bitfld.long 0x00 11. " PD_DRV_SAT ,Pull-down drive strength code saturated due to drive strength adjustment setting in ZQ1PR" "Not saturated,Saturated" bitfld.long 0x00 10. " PU_DRV_SAT ,Pull-up drive strength code saturated due to drive strength adjustment setting in ZQ1PR" "Not saturated,Saturated" newline bitfld.long 0x00 9. " ZDONE ,Impedance calibration done" "Not done,Done" bitfld.long 0x00 8. " ZERR ,Impedance calibration error" "No error,Error" bitfld.long 0x00 6.--7. " OPU ,On-die termination ODT pull-up calibration status" "0,1,2,3" bitfld.long 0x00 4.--5. " OPD ,On-die termination ODT pull-down calibration status" "0,1,2,3" newline bitfld.long 0x00 2.--3. " ZPU ,Output impedance pull-up calibration status" "0,1,2,3" bitfld.long 0x00 0.--1. " ZPD ,Output impedance pull-down calibration status" "0,1,2,3" group.long 0x6C4++0x07 line.long 0x00 "ZQ2PR0,ZQ 2 Impedance Control Program Register 0" bitfld.long 0x00 31. " PD_DRV_ZDEN ,Pull-down drive strength ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 30. " PU_DRV_ZDEN ,Pull-up drive strength ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 29. " PD_ODT_ZDEN ,Pull-down termination ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 28. " PU_ODT_ZDEN ,Pull-up termination ZCTRL override enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " ZSEGBYP ,Calibration segment bypass" "Not bypassed,Bypassed" bitfld.long 0x00 25.--26. " ZLE_MODE ,VREF latch mode" "0,1,2,3" bitfld.long 0x00 22.--24. " ODT_ADJUST ,Termination adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19.--21. " PD_DRV_ADJUST ,Pull-down drive strength adjustment" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. " PU_DRV_ADJUST ,Pull-up drive strength adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--15. " ZPROG_DRAM_ODT ,DRAM impedance divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " ZPROG_HOST_ODT ,HOST impedance divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " ZPROG_ASYM_DRV_PD ,Impedance divide ratio pull-down drive calibration during asymmetric drive strength calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " ZPROG_ASYM_DRV_PU ,Impedance divide ratio (pull-up drive calibration during asymmetric drive strength calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ZQ2PR1,ZQ 2 Impedance Control Program Register 1" hexmask.long.byte 0x04 8.--14. 1. " PU_REFSEL ,Pull-up REFSEL for PZCTRL cell" hexmask.long.byte 0x04 0.--6. 1. " PD_REFSEL ,Pull-down REFSEL for PZCTRL cell" rgroup.long (0x6C4+0x08)++0x07 line.long 0x00 "ZQ2DR0,ZQ 2 Impedance Control Data Register 0" hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_RESULT ,Pull-up drive strength calibration code result" hexmask.long.word 0x00 0.--9. 1. " ZDATA_PD_DRV_RESULT ,Pull-down drive strength calibration code result" line.long 0x04 "ZQ2DR1,ZQ 2 Impedance Control Data Register 1" hexmask.long.word 0x04 16.--25. 1. " ZDATA_PU_ODT_RESULT ,Pull-up termination calibration code result" hexmask.long.word 0x04 0.--9. 1. " ZDATA_PD_ODT_RESULT ,Pull-down termination calibration code result" group.long (0x6C4+0x10)++0x07 line.long 0x00 "ZQ2OR0,ZQ 2 Impedance Control Override Data Register 0" hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_OVRD ,Override value for the pull-up output impedance" hexmask.long.word 0x00 0.--9. 1. " ZDATA_PD_DRV_OVRD ,Override value for the pull-down output impedance" line.long 0x04 "ZQ2OR1,ZQ 2 Impedance Control Override Data Register 1" hexmask.long.word 0x04 16.--25. 1. " ZDATA_PU_ODT_OVRD ,Override value for the pull-up termination" hexmask.long.word 0x04 0.--9. 1. " ZDATA_PD_ODT_OVRD ,Override value for the pull-down termination" rgroup.long (0x6C4+0x18)++0x03 line.long 0x00 "ZQ2SR,ZQ 2 Impedance Control Status Register" bitfld.long 0x00 13. " PD_ODT_SAT ,Pull-down drive strength code saturated due to termination strength adjustment setting in ZQ2PR" "Not saturated,Saturated" bitfld.long 0x00 12. " PU_ODT_SAT ,Pull-up drive strength code saturated due to termination strength adjustment setting in ZQ2PR" "Not saturated,Saturated" bitfld.long 0x00 11. " PD_DRV_SAT ,Pull-down drive strength code saturated due to drive strength adjustment setting in ZQ2PR" "Not saturated,Saturated" bitfld.long 0x00 10. " PU_DRV_SAT ,Pull-up drive strength code saturated due to drive strength adjustment setting in ZQ2PR" "Not saturated,Saturated" newline bitfld.long 0x00 9. " ZDONE ,Impedance calibration done" "Not done,Done" bitfld.long 0x00 8. " ZERR ,Impedance calibration error" "No error,Error" bitfld.long 0x00 6.--7. " OPU ,On-die termination ODT pull-up calibration status" "0,1,2,3" bitfld.long 0x00 4.--5. " OPD ,On-die termination ODT pull-down calibration status" "0,1,2,3" newline bitfld.long 0x00 2.--3. " ZPU ,Output impedance pull-up calibration status" "0,1,2,3" bitfld.long 0x00 0.--1. " ZPD ,Output impedance pull-down calibration status" "0,1,2,3" rgroup.long 0x6E4++0x07 line.long 0x00 "ZQ3PR0,ZQ 3 Impedance Control Program Register 0" bitfld.long 0x00 31. " PD_DRV_ZDEN ,Pull-down drive strength ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 30. " PU_DRV_ZDEN ,Pull-up drive strength ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 29. " PD_ODT_ZDEN ,Pull-down termination ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 28. " PU_ODT_ZDEN ,Pull-up termination ZCTRL override enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " ZSEGBYP ,Calibration segment bypass" "Not bypassed,Bypassed" bitfld.long 0x00 25.--26. " ZLE_MODE ,VREF latch mode" "0,1,2,3" bitfld.long 0x00 22.--24. " ODT_ADJUST ,Termination adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19.--21. " PD_DRV_ADJUST ,Pull-down drive strength adjustment" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. " PU_DRV_ADJUST ,Pull-up drive strength adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--15. " ZPROG_DRAM_ODT ,DRAM impedance divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " ZPROG_HOST_ODT ,HOST impedance divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " ZPROG_ASYM_DRV_PD ,Impedance divide ratio pull-down drive calibration during asymmetric drive strength calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " ZPROG_ASYM_DRV_PU ,Impedance divide ratio (pull-up drive calibration during asymmetric drive strength calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ZQ3PR1,ZQ 3 Impedance Control Program Register 1" hexmask.long.byte 0x04 8.--14. 1. " PU_REFSEL ,Pull-up REFSEL for PZCTRL cell" hexmask.long.byte 0x04 0.--6. 1. " PD_REFSEL ,Pull-down REFSEL for PZCTRL cell" rgroup.long (0x6E4+0x08)++0x07 line.long 0x00 "ZQ3DR0,ZQ 3 Impedance Control Data Register 0" hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_RESULT ,Pull-up drive strength calibration code result" hexmask.long.word 0x00 0.--9. 1. " ZDATA_PD_DRV_RESULT ,Pull-down drive strength calibration code result" line.long 0x04 "ZQ3DR1,ZQ 3 Impedance Control Data Register 1" hexmask.long.word 0x04 16.--25. 1. " ZDATA_PU_ODT_RESULT ,Pull-up termination calibration code result" hexmask.long.word 0x04 0.--9. 1. " ZDATA_PD_ODT_RESULT ,Pull-down termination calibration code result" rgroup.long (0x6E4+0x10)++0x07 line.long 0x00 "ZQ3OR0,ZQ 3 Impedance Control Override Data Register 0" hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_OVRD ,Override value for the pull-up output impedance" hexmask.long.word 0x00 0.--9. 1. " ZDATA_PD_DRV_OVRD ,Override value for the pull-down output impedance" line.long 0x04 "ZQ3OR1,ZQ 3 Impedance Control Override Data Register 1" hexmask.long.word 0x04 16.--25. 1. " ZDATA_PU_ODT_OVRD ,Override value for the pull-up termination" hexmask.long.word 0x04 0.--9. 1. " ZDATA_PD_ODT_OVRD ,Override value for the pull-down termination" rgroup.long (0x6E4+0x18)++0x03 line.long 0x00 "ZQ3SR,ZQ 3 Impedance Control Status Register" bitfld.long 0x00 13. " PD_ODT_SAT ,Pull-down drive strength code saturated due to termination strength adjustment setting in ZQ3PR" "Not saturated,Saturated" bitfld.long 0x00 12. " PU_ODT_SAT ,Pull-up drive strength code saturated due to termination strength adjustment setting in ZQ3PR" "Not saturated,Saturated" bitfld.long 0x00 11. " PD_DRV_SAT ,Pull-down drive strength code saturated due to drive strength adjustment setting in ZQ3PR" "Not saturated,Saturated" bitfld.long 0x00 10. " PU_DRV_SAT ,Pull-up drive strength code saturated due to drive strength adjustment setting in ZQ3PR" "Not saturated,Saturated" newline bitfld.long 0x00 9. " ZDONE ,Impedance calibration done" "Not done,Done" bitfld.long 0x00 8. " ZERR ,Impedance calibration error" "No error,Error" bitfld.long 0x00 6.--7. " OPU ,On-die termination ODT pull-up calibration status" "0,1,2,3" bitfld.long 0x00 4.--5. " OPD ,On-die termination ODT pull-down calibration status" "0,1,2,3" newline bitfld.long 0x00 2.--3. " ZPU ,Output impedance pull-up calibration status" "0,1,2,3" bitfld.long 0x00 0.--1. " ZPD ,Output impedance pull-down calibration status" "0,1,2,3" newline group.long 0x700++0x1F line.long 0x00 "DX0GCR0,DATX8 0 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX0GCR1,DATX8 0 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX0GCR2,DATX8 0 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX0GCR3,DATX8 0 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX0GCR4,DATX8 0 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX0GCR5,DATX8 0 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX0GCR6,DATX8 0 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX0GCR7,DATX8 0 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" group.long (0x700+0x28)++0x07 line.long 0x00 "DX0DQMAP0,DATX8 0 DQ/DM Mapping Register 0" rbitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW0DQMAP1,DATX8 0 DQ/DM Mapping Register 1" rbitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x700+0x40)++0x0B line.long 0x00 "DX0BDLR0,DATX8 0 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX0BDLR1,DATX8 0 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX0BDLR2,DATX8 0 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x700+0x50)++0x0B line.long 0x00 "DX0BDLR3,DATX8 0 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX0BDLR4,DATX8 0 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX0BDLR5,DATX8 0 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x700+0x60)++0x03 line.long 0x00 "DX0BDLR6,DATX8 0 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x700+0x80)++0x17 line.long 0x00 "DX0LCDLR0,DATX8 0 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX0LCDLR1,DATX8 0 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX0LCDLR2,DATX8 0 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX0LCDLR3,DATX8 0 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX0LCDLR4,DATX8 0 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX0LCDLR5,DATX8 0 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" group.long (0x700+0xA0)++0x07 line.long 0x00 "DX0MDLR0,DATX8 0 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX0MDLR1,DATX8 0 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" group.long (0x700+0xC0)++0x03 line.long 0x00 "DX0GTR0,DATX8 0 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0x700+0xD0)++0x1F line.long 0x00 "DX0RSR0,DATX8 0 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX0RSR1,DATX8 0 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX0RSR2,DATX8 0 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX0RSR3,DATX8 0 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX0GSR0,DATX8 0 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX0GSR1,DATX8 0 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX0GSR2,DATX8 0 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX0GSR3,DATX8 0 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" group.long 0x800++0x1F line.long 0x00 "DX1GCR0,DATX8 1 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX1GCR1,DATX8 1 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX1GCR2,DATX8 1 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX1GCR3,DATX8 1 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX1GCR4,DATX8 1 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX1GCR5,DATX8 1 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX1GCR6,DATX8 1 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX1GCR7,DATX8 1 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" group.long (0x800+0x28)++0x07 line.long 0x00 "DX1DQMAP0,DATX8 1 DQ/DM Mapping Register 0" rbitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW1DQMAP1,DATX8 1 DQ/DM Mapping Register 1" rbitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x800+0x40)++0x0B line.long 0x00 "DX1BDLR0,DATX8 1 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX1BDLR1,DATX8 1 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX1BDLR2,DATX8 1 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x800+0x50)++0x0B line.long 0x00 "DX1BDLR3,DATX8 1 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX1BDLR4,DATX8 1 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX1BDLR5,DATX8 1 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x800+0x60)++0x03 line.long 0x00 "DX1BDLR6,DATX8 1 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x800+0x80)++0x17 line.long 0x00 "DX1LCDLR0,DATX8 1 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX1LCDLR1,DATX8 1 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX1LCDLR2,DATX8 1 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX1LCDLR3,DATX8 1 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX1LCDLR4,DATX8 1 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX1LCDLR5,DATX8 1 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" group.long (0x800+0xA0)++0x07 line.long 0x00 "DX1MDLR0,DATX8 1 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX1MDLR1,DATX8 1 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" group.long (0x800+0xC0)++0x03 line.long 0x00 "DX1GTR0,DATX8 1 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0x800+0xD0)++0x1F line.long 0x00 "DX1RSR0,DATX8 1 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX1RSR1,DATX8 1 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX1RSR2,DATX8 1 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX1RSR3,DATX8 1 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX1GSR0,DATX8 1 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX1GSR1,DATX8 1 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX1GSR2,DATX8 1 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX1GSR3,DATX8 1 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" group.long 0x900++0x1F line.long 0x00 "DX2GCR0,DATX8 2 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX2GCR1,DATX8 2 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX2GCR2,DATX8 2 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX2GCR3,DATX8 2 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX2GCR4,DATX8 2 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX2GCR5,DATX8 2 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX2GCR6,DATX8 2 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX2GCR7,DATX8 2 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" group.long (0x900+0x28)++0x07 line.long 0x00 "DX2DQMAP0,DATX8 2 DQ/DM Mapping Register 0" rbitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW2DQMAP1,DATX8 2 DQ/DM Mapping Register 1" rbitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x900+0x40)++0x0B line.long 0x00 "DX2BDLR0,DATX8 2 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX2BDLR1,DATX8 2 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX2BDLR2,DATX8 2 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x900+0x50)++0x0B line.long 0x00 "DX2BDLR3,DATX8 2 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX2BDLR4,DATX8 2 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX2BDLR5,DATX8 2 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x900+0x60)++0x03 line.long 0x00 "DX2BDLR6,DATX8 2 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x900+0x80)++0x17 line.long 0x00 "DX2LCDLR0,DATX8 2 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX2LCDLR1,DATX8 2 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX2LCDLR2,DATX8 2 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX2LCDLR3,DATX8 2 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX2LCDLR4,DATX8 2 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX2LCDLR5,DATX8 2 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" group.long (0x900+0xA0)++0x07 line.long 0x00 "DX2MDLR0,DATX8 2 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX2MDLR1,DATX8 2 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" group.long (0x900+0xC0)++0x03 line.long 0x00 "DX2GTR0,DATX8 2 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0x900+0xD0)++0x1F line.long 0x00 "DX2RSR0,DATX8 2 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX2RSR1,DATX8 2 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX2RSR2,DATX8 2 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX2RSR3,DATX8 2 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX2GSR0,DATX8 2 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX2GSR1,DATX8 2 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX2GSR2,DATX8 2 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX2GSR3,DATX8 2 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" group.long 0xA00++0x1F line.long 0x00 "DX3GCR0,DATX8 3 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX3GCR1,DATX8 3 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX3GCR2,DATX8 3 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX3GCR3,DATX8 3 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX3GCR4,DATX8 3 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX3GCR5,DATX8 3 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX3GCR6,DATX8 3 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX3GCR7,DATX8 3 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" group.long (0xA00+0x28)++0x07 line.long 0x00 "DX3DQMAP0,DATX8 3 DQ/DM Mapping Register 0" rbitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW3DQMAP1,DATX8 3 DQ/DM Mapping Register 1" rbitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0xA00+0x40)++0x0B line.long 0x00 "DX3BDLR0,DATX8 3 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX3BDLR1,DATX8 3 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX3BDLR2,DATX8 3 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0xA00+0x50)++0x0B line.long 0x00 "DX3BDLR3,DATX8 3 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX3BDLR4,DATX8 3 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX3BDLR5,DATX8 3 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0xA00+0x60)++0x03 line.long 0x00 "DX3BDLR6,DATX8 3 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0xA00+0x80)++0x17 line.long 0x00 "DX3LCDLR0,DATX8 3 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX3LCDLR1,DATX8 3 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX3LCDLR2,DATX8 3 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX3LCDLR3,DATX8 3 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX3LCDLR4,DATX8 3 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX3LCDLR5,DATX8 3 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" group.long (0xA00+0xA0)++0x07 line.long 0x00 "DX3MDLR0,DATX8 3 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX3MDLR1,DATX8 3 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" group.long (0xA00+0xC0)++0x03 line.long 0x00 "DX3GTR0,DATX8 3 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0xA00+0xD0)++0x1F line.long 0x00 "DX3RSR0,DATX8 3 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX3RSR1,DATX8 3 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX3RSR2,DATX8 3 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX3RSR3,DATX8 3 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX3GSR0,DATX8 3 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX3GSR1,DATX8 3 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX3GSR2,DATX8 3 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX3GSR3,DATX8 3 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" rgroup.long 0xB00++0x1F line.long 0x00 "DX4GCR0,DATX8 4 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX4GCR1,DATX8 4 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX4GCR2,DATX8 4 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX4GCR3,DATX8 4 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX4GCR4,DATX8 4 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX4GCR5,DATX8 4 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX4GCR6,DATX8 4 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX4GCR7,DATX8 4 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" rgroup.long (0xB00+0x28)++0x07 line.long 0x00 "DX4DQMAP0,DATX8 4 DQ/DM Mapping Register 0" bitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW4DQMAP1,DATX8 4 DQ/DM Mapping Register 1" bitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0xB00+0x40)++0x0B line.long 0x00 "DX4BDLR0,DATX8 4 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX4BDLR1,DATX8 4 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX4BDLR2,DATX8 4 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xB00+0x50)++0x0B line.long 0x00 "DX4BDLR3,DATX8 4 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX4BDLR4,DATX8 4 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX4BDLR5,DATX8 4 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xB00+0x60)++0x03 line.long 0x00 "DX4BDLR6,DATX8 4 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xB00+0x80)++0x17 line.long 0x00 "DX4LCDLR0,DATX8 4 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX4LCDLR1,DATX8 4 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX4LCDLR2,DATX8 4 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX4LCDLR3,DATX8 4 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX4LCDLR4,DATX8 4 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX4LCDLR5,DATX8 4 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" rgroup.long (0xB00+0xA0)++0x07 line.long 0x00 "DX4MDLR0,DATX8 4 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX4MDLR1,DATX8 4 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" rgroup.long (0xB00+0xC0)++0x03 line.long 0x00 "DX4GTR0,DATX8 4 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0xB00+0xD0)++0x1F line.long 0x00 "DX4RSR0,DATX8 4 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX4RSR1,DATX8 4 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX4RSR2,DATX8 4 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX4RSR3,DATX8 4 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX4GSR0,DATX8 4 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX4GSR1,DATX8 4 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX4GSR2,DATX8 4 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX4GSR3,DATX8 4 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" rgroup.long 0xC00++0x1F line.long 0x00 "DX5GCR0,DATX8 5 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX5GCR1,DATX8 5 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX5GCR2,DATX8 5 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX5GCR3,DATX8 5 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX5GCR4,DATX8 5 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX5GCR5,DATX8 5 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX5GCR6,DATX8 5 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX5GCR7,DATX8 5 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" rgroup.long (0xC00+0x28)++0x07 line.long 0x00 "DX5DQMAP0,DATX8 5 DQ/DM Mapping Register 0" bitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW5DQMAP1,DATX8 5 DQ/DM Mapping Register 1" bitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0xC00+0x40)++0x0B line.long 0x00 "DX5BDLR0,DATX8 5 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX5BDLR1,DATX8 5 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX5BDLR2,DATX8 5 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xC00+0x50)++0x0B line.long 0x00 "DX5BDLR3,DATX8 5 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX5BDLR4,DATX8 5 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX5BDLR5,DATX8 5 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xC00+0x60)++0x03 line.long 0x00 "DX5BDLR6,DATX8 5 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xC00+0x80)++0x17 line.long 0x00 "DX5LCDLR0,DATX8 5 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX5LCDLR1,DATX8 5 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX5LCDLR2,DATX8 5 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX5LCDLR3,DATX8 5 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX5LCDLR4,DATX8 5 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX5LCDLR5,DATX8 5 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" rgroup.long (0xC00+0xA0)++0x07 line.long 0x00 "DX5MDLR0,DATX8 5 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX5MDLR1,DATX8 5 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" rgroup.long (0xC00+0xC0)++0x03 line.long 0x00 "DX5GTR0,DATX8 5 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0xC00+0xD0)++0x1F line.long 0x00 "DX5RSR0,DATX8 5 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX5RSR1,DATX8 5 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX5RSR2,DATX8 5 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX5RSR3,DATX8 5 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX5GSR0,DATX8 5 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX5GSR1,DATX8 5 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX5GSR2,DATX8 5 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX5GSR3,DATX8 5 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" rgroup.long 0xD00++0x1F line.long 0x00 "DX6GCR0,DATX8 6 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX6GCR1,DATX8 6 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX6GCR2,DATX8 6 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX6GCR3,DATX8 6 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX6GCR4,DATX8 6 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX6GCR5,DATX8 6 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX6GCR6,DATX8 6 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX6GCR7,DATX8 6 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" rgroup.long (0xD00+0x28)++0x07 line.long 0x00 "DX6DQMAP0,DATX8 6 DQ/DM Mapping Register 0" bitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW6DQMAP1,DATX8 6 DQ/DM Mapping Register 1" bitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0xD00+0x40)++0x0B line.long 0x00 "DX6BDLR0,DATX8 6 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX6BDLR1,DATX8 6 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX6BDLR2,DATX8 6 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xD00+0x50)++0x0B line.long 0x00 "DX6BDLR3,DATX8 6 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX6BDLR4,DATX8 6 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX6BDLR5,DATX8 6 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xD00+0x60)++0x03 line.long 0x00 "DX6BDLR6,DATX8 6 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xD00+0x80)++0x17 line.long 0x00 "DX6LCDLR0,DATX8 6 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX6LCDLR1,DATX8 6 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX6LCDLR2,DATX8 6 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX6LCDLR3,DATX8 6 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX6LCDLR4,DATX8 6 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX6LCDLR5,DATX8 6 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" rgroup.long (0xD00+0xA0)++0x07 line.long 0x00 "DX6MDLR0,DATX8 6 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX6MDLR1,DATX8 6 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" rgroup.long (0xD00+0xC0)++0x03 line.long 0x00 "DX6GTR0,DATX8 6 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0xD00+0xD0)++0x1F line.long 0x00 "DX6RSR0,DATX8 6 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX6RSR1,DATX8 6 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX6RSR2,DATX8 6 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX6RSR3,DATX8 6 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX6GSR0,DATX8 6 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX6GSR1,DATX8 6 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX6GSR2,DATX8 6 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX6GSR3,DATX8 6 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" rgroup.long 0xE00++0x1F line.long 0x00 "DX7GCR0,DATX8 7 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX7GCR1,DATX8 7 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX7GCR2,DATX8 7 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX7GCR3,DATX8 7 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX7GCR4,DATX8 7 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX7GCR5,DATX8 7 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX7GCR6,DATX8 7 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX7GCR7,DATX8 7 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" rgroup.long (0xE00+0x28)++0x07 line.long 0x00 "DX7DQMAP0,DATX8 7 DQ/DM Mapping Register 0" bitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW7DQMAP1,DATX8 7 DQ/DM Mapping Register 1" bitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0xE00+0x40)++0x0B line.long 0x00 "DX7BDLR0,DATX8 7 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX7BDLR1,DATX8 7 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX7BDLR2,DATX8 7 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xE00+0x50)++0x0B line.long 0x00 "DX7BDLR3,DATX8 7 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX7BDLR4,DATX8 7 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX7BDLR5,DATX8 7 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xE00+0x60)++0x03 line.long 0x00 "DX7BDLR6,DATX8 7 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xE00+0x80)++0x17 line.long 0x00 "DX7LCDLR0,DATX8 7 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX7LCDLR1,DATX8 7 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX7LCDLR2,DATX8 7 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX7LCDLR3,DATX8 7 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX7LCDLR4,DATX8 7 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX7LCDLR5,DATX8 7 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" rgroup.long (0xE00+0xA0)++0x07 line.long 0x00 "DX7MDLR0,DATX8 7 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX7MDLR1,DATX8 7 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" rgroup.long (0xE00+0xC0)++0x03 line.long 0x00 "DX7GTR0,DATX8 7 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0xE00+0xD0)++0x1F line.long 0x00 "DX7RSR0,DATX8 7 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX7RSR1,DATX8 7 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX7RSR2,DATX8 7 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX7RSR3,DATX8 7 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX7GSR0,DATX8 7 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX7GSR1,DATX8 7 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX7GSR2,DATX8 7 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX7GSR3,DATX8 7 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" rgroup.long 0xF00++0x1F line.long 0x00 "DX8GCR0,DATX8 8 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX8GCR1,DATX8 8 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX8GCR2,DATX8 8 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX8GCR3,DATX8 8 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX8GCR4,DATX8 8 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX8GCR5,DATX8 8 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX8GCR6,DATX8 8 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX8GCR7,DATX8 8 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" rgroup.long (0xF00+0x28)++0x07 line.long 0x00 "DX8DQMAP0,DATX8 8 DQ/DM Mapping Register 0" bitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW8DQMAP1,DATX8 8 DQ/DM Mapping Register 1" bitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0xF00+0x40)++0x0B line.long 0x00 "DX8BDLR0,DATX8 8 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX8BDLR1,DATX8 8 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX8BDLR2,DATX8 8 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xF00+0x50)++0x0B line.long 0x00 "DX8BDLR3,DATX8 8 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX8BDLR4,DATX8 8 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX8BDLR5,DATX8 8 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xF00+0x60)++0x03 line.long 0x00 "DX8BDLR6,DATX8 8 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xF00+0x80)++0x17 line.long 0x00 "DX8LCDLR0,DATX8 8 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX8LCDLR1,DATX8 8 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX8LCDLR2,DATX8 8 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX8LCDLR3,DATX8 8 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX8LCDLR4,DATX8 8 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX8LCDLR5,DATX8 8 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" rgroup.long (0xF00+0xA0)++0x07 line.long 0x00 "DX8MDLR0,DATX8 8 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX8MDLR1,DATX8 8 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" rgroup.long (0xF00+0xC0)++0x03 line.long 0x00 "DX8GTR0,DATX8 8 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0xF00+0xD0)++0x1F line.long 0x00 "DX8RSR0,DATX8 8 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX8RSR1,DATX8 8 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX8RSR2,DATX8 8 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX8RSR3,DATX8 8 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX8GSR0,DATX8 8 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX8GSR1,DATX8 8 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX8GSR2,DATX8 8 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX8GSR3,DATX8 8 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" newline group.long 0x1400++0x1F line.long 0x00 "DX8SL0OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode write-data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode write-leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL0PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL0PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL0PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL0PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL0PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL0PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL0DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path rise-to-rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path rise-to-rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x1400+0x24)++0x0F line.long 0x00 "DX8SL0DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL0DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL0DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during postamble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during preamble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL0IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" group.long 0x1440++0x1F line.long 0x00 "DX8SL1OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode write-data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode write-leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL1PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL1PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL1PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL1PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL1PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL1PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL1DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path rise-to-rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path rise-to-rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x1440+0x24)++0x0F line.long 0x00 "DX8SL1DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL1DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL1DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during postamble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during preamble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL1IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" group.long 0x1480++0x1F line.long 0x00 "DX8SL2OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode write-data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode write-leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL2PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL2PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL2PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL2PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL2PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL2PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL2DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path rise-to-rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path rise-to-rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x1480+0x24)++0x0F line.long 0x00 "DX8SL2DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL2DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL2DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during postamble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during preamble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL2IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" rgroup.long 0x14C0++0x1F line.long 0x00 "DX8SL3OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode Write-Data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode Write-Leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL3PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable ATOEN" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL3PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL3PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL3PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL3PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL3PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL3DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0x14C0+0x24)++0x0F line.long 0x00 "DX8SL3DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL3DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL3DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during Post-amble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during Pre-amble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL3IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" rgroup.long 0x1500++0x1F line.long 0x00 "DX8SL4OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode Write-Data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode Write-Leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL4PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable ATOEN" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL4PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL4PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL4PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL4PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL4PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL4DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0x1500+0x24)++0x0F line.long 0x00 "DX8SL4DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL4DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL4DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during Post-amble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during Pre-amble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL4IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" rgroup.long 0x1540++0x1F line.long 0x00 "DX8SL5OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode Write-Data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode Write-Leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL5PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable ATOEN" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL5PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL5PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL5PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL5PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL5PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL5DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0x1540+0x24)++0x0F line.long 0x00 "DX8SL5DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL5DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL5DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during Post-amble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during Pre-amble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL5IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" rgroup.long 0x1580++0x1F line.long 0x00 "DX8SL6OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode Write-Data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode Write-Leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL6PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable ATOEN" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL6PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL6PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL6PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL6PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL6PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL6DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0x1580+0x24)++0x0F line.long 0x00 "DX8SL6DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL6DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL6DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during Post-amble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during Pre-amble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL6IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" rgroup.long 0x15C0++0x1F line.long 0x00 "DX8SL7OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode Write-Data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode Write-Leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL7PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable ATOEN" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL7PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL7PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL7PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL7PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL7PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL7DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0x15C0+0x24)++0x0F line.long 0x00 "DX8SL7DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL7DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL7DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during Post-amble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during Pre-amble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL7IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" rgroup.long 0x1600++0x1F line.long 0x00 "DX8SL8OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode Write-Data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode Write-Leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL8PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable ATOEN" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL8PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL8PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL8PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL8PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL8PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL8DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0x1600+0x24)++0x0F line.long 0x00 "DX8SL8DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL8DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL8DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during Post-amble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during Pre-amble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL8IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" wgroup.long 0x17C0++0x1F line.long 0x00 "DX8SLBOSC,DATX8 0-8 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode write-data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode write-leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SLBPLLCR0,DAXT8 0-8 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable ATOEN" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SLBPLLCR1,DAXT8 0-8 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypassed,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SLBPLLCR2,DAXT8 0-8 PLL Control Register 2" line.long 0x10 "DX8SLBPLLCR3,DAXT8 0-8 PLL Control Register 3" line.long 0x14 "DX8SLBPLLCR4,DAXT8 0-8 PLL Control Register 4" line.long 0x18 "DX8SLBPLLCR5,DAXT8 0-8 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SLBDQSCTL,DATX8 0-8 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path rise-to-rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path rise-to-rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS# resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.long 0x17E4++0x0F line.long 0x00 "DX8SLBDDLCTL,DATX8 0-8 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SLBDXCTL1,DATX8 0-8 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SLBDXCTL2,DATX8 0-8 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during postamble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during preamble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "No bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No reset,Reset" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SLBIOCR,DATX8 0-8 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" width 0x0B tree.end tree "DDRC0_1 (DDR Controller)" base ad:0x5C2000000 width 18. group.long 0x00++0x03 line.long 0x00 "MSTR,Master Register" bitfld.long 0x00 30.--31. " DEVICE_CONFIG ,Indicates the configuration of the device used in the system" "x4,x8,x16,x32" bitfld.long 0x00 29. " FREQUENCY_MODE ,Choose which registers are used" "Original,Shadow" newline bitfld.long 0x00 24.--25. " ACTIVE_RANKS ,Only present for multi-rank configurations" ",One rank,,Two rank" bitfld.long 0x00 22. " FREQUENCY_RATIO ,Selects the frequency ratio" "1:2 mode,1:1 mode" newline bitfld.long 0x00 16.--19. " BURST_RDWR ,Controls the burst size used to access the SDRAM" ",2,4,,8,,,,16,?..." bitfld.long 0x00 15. " DLL_OFF_MODE ,Indicates whether the DDRC and DRAM have to be put in DLL-off mode" "On mode,Off mode" newline bitfld.long 0x00 12.--13. " DATA_BUS_WIDTH ,Selects proportion of DQ bus width that is used by the SDRAM" "Full,Half,Quarter,?..." bitfld.long 0x00 11. " GEARDOWN_MODE ,DRAM mode" "Normal,Geardown" newline bitfld.long 0x00 10. " EN_2T_TIMING_MODE ,Enable 2T timing" "Disabled,Enabled" bitfld.long 0x00 9. " BURSTCHOP ,Burst-chop in DDR3/DDR4" "Disabled,Enabled" newline bitfld.long 0x00 5. " LPDDR4 ,Select LPDDR4 SDRAM" "Non-LPDDR4,LPDDR4" bitfld.long 0x00 3. " LPDDR3 ,Select LPDDR3 SDRAM" "Non-LPDDR3,LPDDR3" newline bitfld.long 0x00 2. " LPDDR2 ,Select LPDDR2 SDRAM" "Non-LPDDR2,LPDDR2" bitfld.long 0x00 0. " DDR3 ,Select DDR3 SDRAM" "Non-DDR3,DDR3" if (((per.l(ad:0x5C2000000))&0x20)==0x20) rgroup.long 0x04++0x03 line.long 0x00 "STAT,Operating Mode Status Register" bitfld.long 0x00 8.--9. " SELFREF_STATE ,Self refresh state" "No self refresh,Self refresh 1,Self refresh power down,Self refresh" bitfld.long 0x00 4.--5. " SELFREF_TYPE ,SR-powerdown type" "Not in SR-powerdown,,Caused not only by automatic SR control,Caused only by automatic SR control" newline bitfld.long 0x00 0.--2. " OPERATING_MODE ,Operating mode" "Init,Normal,Power-down,Self refresh power-down,?..." elif (((per.l(ad:0x5C2000000))&0x10)==0x10) rgroup.long 0x04++0x03 line.long 0x00 "STAT,Operating Mode Status Register" bitfld.long 0x00 8.--9. " SELFREF_STATE ,Self refresh state" "No self refresh,Self refresh 1,Self refresh power down,Self refresh" bitfld.long 0x00 4.--5. " SELFREF_TYPE ,Self refresh type" "Not in self refresh,,Caused not only by automatic SR control,Caused only by automatic SR control" newline bitfld.long 0x00 0.--2. " OPERATING_MODE ,Operating mode" "Init,Normal,Power-down,Self refresh,Deep power-down,Deep power-down,Deep power-down,Deep power-down" else rgroup.long 0x04++0x03 line.long 0x00 "STAT,Operating Mode Status Register" bitfld.long 0x00 8.--9. " SELFREF_STATE ,Self refresh state" "No self refresh,Self refresh 1,Self refresh power down,Self refresh" bitfld.long 0x00 4.--5. " SELFREF_TYPE ,Self refresh type" "Not in self refresh,,Caused not only by automatic SR control,Caused only by automatic SR control" newline bitfld.long 0x00 0.--1. " OPERATING_MODE ,Operating mode" "Init,Normal,Power-down,Self refresh" endif group.long 0x08++0x0F line.long 0x00 "MSTR1,Operating Mode Status Register 1" bitfld.long 0x00 16. " ALT_ADDRMAP_EN ,Enable alternative address map" "Disabled,Enabled" bitfld.long 0x00 1. " RANK_TMGREG_SEL[1] ,Indicates which register set is used for each rank" "Disabled,Enabled" newline bitfld.long 0x00 0. " [0] ,Indicates which register set is used for each rank" "Disabled,Enabled" line.long 0x04 "MRCTRL3,Operating Mode Status Register 3" bitfld.long 0x04 0.--1. " MR_RANK_SEL ,Controls which rank is accessed by MRCTRL0.mr_wr" "0,1,2,3" line.long 0x08 "MRCTRL0,Mode Register Read/Write Control Register 0" bitfld.long 0x08 31. " MR_WR ,Triggers a mode register read or write operation" "Not Triggered,Triggered" bitfld.long 0x08 30. " PBA_MODE ,Indicates whether PBA access is executed" "Not executed,Executed" newline bitfld.long 0x08 12.--15. " MR_ADDR ,Address of the mode register that is to be written to" "MR0,MR1,MR2,MR3,MR4,MR5,MR6,MR7,?..." bitfld.long 0x08 4.--5. " MR_RANK ,Controls which ranks are accessed by MRCTRL0.MR_WR" "0,1,2,3" newline bitfld.long 0x08 3. " SW_INIT_INT ,Indicates whether Software intervention is allowed" "Not allowed,Allowed" bitfld.long 0x08 2. " PDA_EN ,Indicates whether the mode register operation is MRS in PDA mode" "MRS,MRS in per DRAM addressability" newline bitfld.long 0x08 1. " MPR_EN ,Indicates whether the mode register operation is MRS or WR/RD for MPR" "MRS,WR/RD for MPR" bitfld.long 0x08 0. " MR_TYPE ,Indicates whether the mode register operation is read or write" "Write,Read" line.long 0x0C "MRCTRL1,Mode Register Read/Write Control Register 1" hexmask.long.tbyte 0x0C 0.--17. 1. " MR_DATA ,Mode register write data" rgroup.long 0x18++0x03 line.long 0x00 "MRSTAT,Mode Register Read/Write Status Register" bitfld.long 0x00 8. " PDA_DONE ,The SoC core may initiate a MR write operation in PDA/PBA mod" "In progress,Completed" bitfld.long 0x00 0. " MR_WR_BUSY ,The SoC core may initiate a MR write operation" "SoC core can initiate write operation,Write operation in progress" group.long 0x1C++0x03 line.long 0x00 "MRCTRL2,Mode Register Read/Write Control Register 2" if (((per.l(ad:0x5C2000000))&0x20)==0x20) group.long 0x20++0x07 line.long 0x00 "DERATEEN,Temperature Derate Enable Register" bitfld.long 0x00 8.--9. " RC_DERATE_VALUE ,Derate value of tRC for LPDDR4" "+1,+2,+3,+4" bitfld.long 0x00 4.--7. " DERATE_BYTE ,Indicates which byte of the MRR data is used for derating" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1. " DERATE_VALUE ,Derate value" "+1,+2" bitfld.long 0x00 0. " DERATE_ENABLE ,Enables derating" "Disabled,Enabled" line.long 0x04 "DERATEINT,Temperature Derate Interval Register" else hgroup.long 0x20++0x03 hide.long 0x00 "DERATEEN,Temperature Derate Enable Register" hgroup.long 0x24++0x03 hide.long 0x00 "DERATEINT,Temperature Derate Interval Register" endif group.long 0x30++0x0B line.long 0x00 "PWRCTL,Low Power Control Register" bitfld.long 0x00 6. " STAY_IN_SELFREF ,Transition from Self refresh state" "Allow,Prohibit" bitfld.long 0x00 5. " SELFREF_SW ,Software entry transition to/from Self-refresh" "Exited,Entered" newline bitfld.long 0x00 4. " MPSM_EN ,DDRC maximum power saving mode" "Disabled,Enabled" bitfld.long 0x00 3. " EN_DFI_DRAM_CLK_DISABLE ,Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM" "No,Yes" newline bitfld.long 0x00 2. " DEEPPOWERDOWN_EN ,Enable for deep power-down" "Disabled,Enabled" bitfld.long 0x00 1. " POWERDOWN_EN ,Enable for power-down" "Disabled,Enabled" newline bitfld.long 0x00 0. " SELFREF_EN ,Enable for self refresh" "Disabled,Enabled" line.long 0x04 "PWRTMG,Low Power Timing Register" hexmask.long.byte 0x04 16.--23. 1. " SELFREF_TO_X32 ,SELFREF_TO_X32" hexmask.long.byte 0x04 8.--15. 1. " T_DPD_X4096 ,Minimum deep power-down time" newline bitfld.long 0x04 0.--4. " POWERDOWN_TO_X32 ,After this many clocks of NOP or deselect the DDRC automatically puts the SDRAM into power-down" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "HWLPCTL,Hardware Low Power Control Register" hexmask.long.word 0x08 16.--27. 1. " HW_LP_IDLE_X32 ,Hardware idle period" bitfld.long 0x08 1. " HW_LP_EXIT_IDLE_EN ,Enable for exit from the automatic clock stop automatic power down or automatic self-refresh modes" "Disabled,Enabled" newline bitfld.long 0x08 0. " HW_LP_EN ,Enable for hardware low power interface" "Disabled,Enabled" if (((per.l(ad:0x5C2000000))&0x20)==0x20) group.long 0x50++0x03 line.long 0x00 "RFSHCTL0,Refresh Control Register 0" bitfld.long 0x00 20.--23. " REFRESH_MARGIN ,Threshold value in number of clock cycles before the critical refresh or page timer expires" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--16. " REFRESH_TO_X32 ,Speculative refreshes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4.--8. " REFRESH_BURST ,Number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute" "1 refresh,2 refresh,3 refresh,4 refresh,5 refresh,6 refresh,7 refresh,8 refresh,9 refresh,10 refresh,11 refresh,12 refresh,13 refresh,14 refresh,15 refresh,16 refresh,17 refresh,18 refresh,19 refresh,20 refresh,21 refresh,22 refresh,23 refresh,24 refresh,25 refresh,26 refresh,27 refresh,28 refresh,29 refresh,30 refresh,31 refresh,32 refresh" bitfld.long 0x00 2. " PER_BANK_REFRESH ,Allows traffic to flow to other banks" "All bank refresh,Per bank refresh" else group.long 0x50++0x03 line.long 0x00 "RFSHCTL0,Refresh Control Register 0" bitfld.long 0x00 20.--23. " REFRESH_MARGIN ,Threshold value in number of clock cycles before the critical refresh or page timer expires" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--16. " REFRESH_TO_X32 ,Speculative refreshes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4.--8. " REFRESH_BURST ,Number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute" "1 refresh,2 refresh,3 refresh,4 refresh,5 refresh,6 refresh,7 refresh,8 refresh,9 refresh,10 refresh,11 refresh,12 refresh,13 refresh,14 refresh,15 refresh,16 refresh,17 refresh,18 refresh,19 refresh,20 refresh,21 refresh,22 refresh,23 refresh,24 refresh,25 refresh,26 refresh,27 refresh,28 refresh,29 refresh,30 refresh,31 refresh,32 refresh" endif group.long 0x54++0x03 line.long 0x00 "RFSHCTL1,Refresh Control Register 1" hexmask.long.word 0x00 16.--27. 1. " REFRESH_TIMER1_START_VALUE_X32 ,Refresh timer start for rank 1" hexmask.long.word 0x00 0.--11. 1. " REFRESH_TIMER0_START_VALUE_X32 ,Refresh timer start for rank 0" group.long 0x60++0x07 line.long 0x00 "RFSHCTL3,Refresh Control Register 3" bitfld.long 0x00 4.--6. " REFRESH_MODE ,Fine granularity refresh mode" "Fixed,Fixed 2x,Fixed x4,,,Enabled on the fly x2,Enabled on the fly x4,?..." bitfld.long 0x00 1. " REFRESH_UPDATE_LEVEL ,Indicates that the refresh Register(S) have been updated" "0,1" newline bitfld.long 0x00 0. " DIS_AUTO_REFRESH ,Disables auto-refresh generated by the DDRC" "No,Yes" line.long 0x04 "RFSHTMG,Refresh Timing Register" hexmask.long.word 0x04 16.--27. 1. " T_RFC_NOM_X32 ,Average time interval between refreshes per rank" hexmask.long.word 0x04 0.--9. 1. " T_RFC_MIN ,Minimum time from refresh to refresh or activate" group.long 0xD0++0x03 line.long 0x00 "INIT0,SDRAM Initialization Register 0" bitfld.long 0x00 30.--31. " SKIP_DRAM_INIT ,If lower bit is enabled the SDRAM initialization routine is skipped" "Run after power-up,Skipped after power-up,Run after power-up,Skipped after power-up" hexmask.long.word 0x00 16.--25. 1. " POST_CKE_X1024 ,Cycles to wait after driving CKE high to start the SDRAM initialization sequence" newline hexmask.long.word 0x00 0.--11. 1. " PRE_CKE_X1024 ,Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence" if ((((per.l(ad:0x5C2000000))&0x20)==0x20)||(((per.l(ad:0x5C2000000))&0x01)==0x01)) group.long 0xD4++0x03 line.long 0x00 "INIT1,SDRAM Initialization Register 1" hexmask.long.word 0x00 16.--24. 1. " DRAM_RSTN_X1024 ,Number of cycles to assert SDRAM reset signal during init sequence" bitfld.long 0x00 0.--3. " PRE_OCD_X32 ,Wait period before driving the OCD complete command to SDRAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xD4++0x03 line.long 0x00 "INIT1,SDRAM Initialization Register 1" bitfld.long 0x00 0.--3. " PRE_OCD_X32 ,Wait period before driving the OCD complete command to SDRAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hgroup.long 0xD8++0x03 hide.long 0x00 "INIT2,SDRAM Initialization Register 2" group.long 0xDC++0x07 line.long 0x00 "INIT3,SDRAM Initialization Register 3" hexmask.long.word 0x00 16.--31. 1. " MR ,Value write to MR register" hexmask.long.word 0x00 0.--15. 1. " EMR ,Value write to EMR register" line.long 0x04 "INIT4,SDRAM Initialization Register 4" hexmask.long.word 0x04 16.--31. 1. " EMR2 ,Value write to EMR2 register" hexmask.long.word 0x04 0.--15. 1. " EMR3 ,Value write to EMR3 register" if (((per.l(ad:0x5C2000000))&0x01)==0x01) group.long 0xE4++0x03 line.long 0x00 "INIT5,SDRAM Initialization Register 5" hexmask.long.byte 0x00 16.--23. 1. " DEV_ZQINIT_X32 ,ZQ initial calibration" hexmask.long.word 0x00 0.--9. 1. " MAX_AUTO_INIT_X_1024 ,Maximum duration of the auto initialization tINIT5" else hgroup.long 0xE4++0x03 hide.long 0x00 "INIT5,SDRAM Initialization Register 5" endif hgroup.long 0xE8++0x03 hide.long 0x00 "INIT6,SDRAM Initialization Register 6" hgroup.long 0xEC++0x03 hide.long 0x00 "INIT7,SDRAM Initialization Register 7" if (((per.l(ad:0x5C2000000))&0x10)==0x10) group.long 0xF0++0x03 line.long 0x00 "DIMMCTL,DIMM Control Register" bitfld.long 0x00 6. " LRDIMM_BCOM_CMD_PROT ,Protects the timing restrictions" "0,1" bitfld.long 0x00 5. " DIMM_DIS_BG_MIRRORING ,Disabling address mirroring for BG bits" "Swapped,Not swapped" newline bitfld.long 0x00 4. " MRS_BG1_EN ,Enable for BG1 bit of MRS command" "Disabled,Enabled" bitfld.long 0x00 3. " MRS_A17_EN ,Enable for A17 bit of MRS command" "Disabled,Enabled" newline bitfld.long 0x00 2. " DIMM_OUTPUT_INV_EN ,Output inversion enable" "Disabled,Enabled" bitfld.long 0x00 1. " DIMM_ADDR_MIRR_EN ,Address mirroring enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DIMM_STAGGER_CS_EN ,Staggering enable for multi-rank accesses" "Disabled,Enabled" elif (((per.l(ad:0x5C2000000))&0x20)==0x20) group.long 0xF0++0x03 line.long 0x00 "DIMMCTL,DIMM Control Register" bitfld.long 0x00 6. " LRDIMM_BCOM_CMD_PROT ,Protects the timing restrictions" "0,1" bitfld.long 0x00 5. " DIMM_DIS_BG_MIRRORING ,Disabling address mirroring for BG bits" "Swapped,Not swapped" newline bitfld.long 0x00 4. " MRS_BG1_EN ,Enable for BG1 bit of MRS command" "Disabled,Enabled" bitfld.long 0x00 3. " MRS_A17_EN ,Enable for A17 bit of MRS command" "Disabled,Enabled" newline bitfld.long 0x00 2. " DIMM_OUTPUT_INV_EN ,Output inversion enable" "Disabled,Enabled" else group.long 0xF0++0x03 line.long 0x00 "DIMMCTL,DIMM Control Register" bitfld.long 0x00 6. " LRDIMM_BCOM_CMD_PROT ,Protects the timing restrictions" "0,1" bitfld.long 0x00 5. " DIMM_DIS_BG_MIRRORING ,Disabling address mirroring for BG bits" "Swapped,Not swapped" newline bitfld.long 0x00 4. " MRS_BG1_EN ,Enable for BG1 bit of MRS command" "Disabled,Enabled" bitfld.long 0x00 3. " MRS_A17_EN ,Enable for A17 bit of MRS command" "Disabled,Enabled" endif group.long 0xF4++0x03 line.long 0x00 "RANKCTL,Rank Control Register" bitfld.long 0x00 8.--11. " DIFF_RANK_WR_GAP ,Only present for multi-rank configurations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DIFF_RANK_RD_GAP ,Only present for multi-rank configurations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " MAX_RANK_RD ,Only present for multi-rank configurations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x100++0x0B line.long 0x00 "DRAMTMG0,SDRAM Timing Register 0" hexmask.long.byte 0x00 24.--30. 1. " WR2PRE ,Minimum time between write and precharge to same bank" bitfld.long 0x00 16.--21. " T_FAW ,TFAW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x00 8.--14. 1. " T_RAS_MAX ,Maximum time between activate and precharge to the same bank" bitfld.long 0x00 0.--5. " T_RAS_MIN ,Minimum time between activate and precharge to the same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DRAMTMG1,SDRAM Timing Register 1" bitfld.long 0x04 16.--20. " T_XP ,Minimum time after power-down exit to any operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--13. " RD2PRE ,Minimum time from read to precharge of same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x04 0.--6. 1. " T_RC ,Minimum time between activates to same bank" line.long 0x08 "DRAMTMG2,SDRAM Timing Register 2" bitfld.long 0x08 24.--29. " WRITE_LATENCY ,Time from write command to write data on SDRAM interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " READ_LATENCY ,Time from read command to read data on SDRAM interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " RD2WR ,Minimum time from read command to write command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " WR2RD ,Minimum time from write command to read command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0x5C2000000))&0x20)==0x20) group.long 0x10C++0x03 line.long 0x00 "DRAMTMG3,SDRAM Timing Register 3" hexmask.long.word 0x00 20.--29. 1. " T_MRW ,Time to wait after a mode register write or read" bitfld.long 0x00 12.--17. " T_MRD ,Cycles between loadmode commands" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.l(ad:0x5C2000000))&0x01)==0x01) group.long 0x10C++0x03 line.long 0x00 "DRAMTMG3,SDRAM Timing Register 3" bitfld.long 0x00 12.--17. " T_MRD ,Cycles between loadmode commands" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 0.--9. 1. " T_MOD ,Cycles between loadmode command and following non-load mode command" else group.long 0x10C++0x03 line.long 0x00 "DRAMTMG3,SDRAM Timing Register 3" bitfld.long 0x00 12.--17. " T_MRD ,Cycles between loadmode commands" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x110++0x07 line.long 0x00 "DRAMTMG4,SDRAM Timing Register 4" bitfld.long 0x00 24.--28. " T_RCD ,Minimum time from activate to read or write command to same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--19. " T_CCD ,Minimum time between two reads or two writes for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " T_RRD ,Minimum time between activates from bank a to bank b for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " T_RP ,Minimum time from precharge to activate of same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DRAMTMG5,SDRAM Timing Register5" bitfld.long 0x04 24.--27. " T_CKSRX ,Time before self refresh exit that CK is maintained as a valid clock before issuing SRX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " T_CKSRE ,Time after self refresh down entry that CK is maintained as a valid clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--13. " T_CKESR ,Minimum CKE low width for self refresh entry to exit timing in memory clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--4. " T_CKE ,Minimum number of cycles of CKE HIGH / LOW during power-down and self refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x5C2000000))&0x20)==0x20) group.long 0x118++0x07 line.long 0x00 "DRAMTMG6,SDRAM Timing Register 6" bitfld.long 0x00 0.--3. " T_CKCSX ,Time before clock stop exit that CK is maintained as a valid clock before issuing clock stop exit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DRAMTMG7,SDRAM Timing Register 7" bitfld.long 0x04 8.--11. " T_CKPDE ,Time after power down entry that CK is maintained as a valid clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " T_CKPDX ,Time before power down exit that CK is maintained as a valid clock before issuing PDX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else hgroup.long 0x118++0x03 hide.long 0x00 "DRAMTMG6,SDRAM Timing Register 6" hgroup.long 0x11C++0x03 hide.long 0x00 "DRAMTMG7,SDRAM Timing Register 7" endif if (((per.l(ad:0x5C2000000))&0x01)==0x01) group.long 0x120++0x03 line.long 0x00 "DRAMTMG8,SDRAM Timing Register 8" hexmask.long.byte 0x00 24.--30. 1. " T_XS_FAST_X32 ,Exit Self refresh to ZQC ZQCS and MRS" hexmask.long.byte 0x00 16.--22. 1. " T_XS_ABORT_X32 ,Exit self refresh to commands not requiring a locked DLL in self refresh abort" newline hexmask.long.byte 0x00 8.--14. 1. " T_XS_DLL_X32 ,Exit self refresh to commands requiring a locked DLL" hexmask.long.byte 0x00 0.--6. 1. " T_XS_X32 ,Exit self refresh to commands not requiring a locked DLL" else group.long 0x120++0x03 line.long 0x00 "DRAMTMG8,SDRAM Timing Register 8" hexmask.long.byte 0x00 24.--30. 1. " T_XS_FAST_X32 ,Exit self refresh to ZQCL ZQCS and MRS" hexmask.long.byte 0x00 16.--22. 1. " T_XS_ABORT_X32 ,Exit Self Refresh to commands not requiring a locked DLL in self refresh abort" endif hgroup.long 0x124++0x03 hide.long 0x00 "DRAMTMG9,SDRAM Timing Register 9" group.long 0x128++0x03 line.long 0x00 "DRAMTMG10,SDRAM Timing Register 10" bitfld.long 0x00 16.--20. " T_SYNC_GEAR ,Indicates the time between MRS command and the sync pulse time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " T_CMD_GEAR ,Sync pulse to first valid command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 2.--3. " T_GEAR_SETUP ,Geardown setup time" ",1,2,3" bitfld.long 0x00 0.--1. " T_GEAR_HOLD ,Geardown hold time" ",1,2,3" hgroup.long 0x12C++0x03 hide.long 0x00 "DRAMTMG11,SDRAM Timing Register 11" group.long 0x130++0x07 line.long 0x00 "DRAMTMG12,SDRAM Timing Register 12" bitfld.long 0x00 16.--17. " T_CMDCKE ,Delay from valid command to CKE input LOW" "0,1,2,3" bitfld.long 0x00 8.--11. " T_CKEHCMD ,Valid command requirement after CKE input HIGH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--4. " T_MRD_PDA ,This is the mode register set command cycle time in PDA mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DRAMTMG13,SDRAM Timing Register 13" hexmask.long.byte 0x04 24.--30. 1. " ODTLOFF ,This is the latency from CAS-2 command to tODToff reference" bitfld.long 0x04 16.--21. " T_CCD_MW ,This is the minimum time from write or masked write to masked write command for same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 0.--2. " T_PPD ,This is the minimum time from precharge to precharge command" "0,1,2,3,4,5,6,7" if (((per.l(ad:0x5C2000000))&0x20)==0x20) group.long 0x138++0x03 line.long 0x00 "DRAMTMG14,SDRAM Timing Register 14" hexmask.long.word 0x00 0.--11. 1. " T_XSR ,Exit self refresh to any command" else hgroup.long 0x138++0x03 hide.long 0x00 "DRAMTMG14,SDRAM Timing Register 14" endif group.long 0x13C++0x03 line.long 0x00 "DRAMTMG15,SDRAM Timing Register 15" bitfld.long 0x00 31. " EN_DFI_LP_T_STAB ,Enable DFI tSTAB" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " T_STAB_X32 ,Stabilization time" group.long 0x180++0x03 line.long 0x00 "ZQCTL0,ZQ Control Register 0" bitfld.long 0x00 31. " DIS_AUTO_ZQ ,Disable auto ZQCS/MPC" "No,Yes" bitfld.long 0x00 30. " DIS_SRX_ZQCL ,Disable ZQCL/MPC" "No,Yes" newline bitfld.long 0x00 29. " ZQ_RESISTOR_SHARED ,ZQ resistor sharing" "Not shared,Shared" newline hexmask.long.word 0x00 16.--26. 1. " T_ZQ_LONG_NOP ,Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to SDRAM" hexmask.long.word 0x00 0.--9. 1. " T_ZQ_SHORT_NOP ,Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to SDRAM" if (((per.l(ad:0x5C2000000))&0x20)==0x20) group.long 0x184++0x03 line.long 0x00 "ZQCTL1,ZQ Control Register 1" hexmask.long.word 0x00 20.--29. 1. " T_ZQ_RESET_NOP ,Number of cycles of NOP required after a ZQReset (ZQ calibration reset) command is issued to SDRAM" hexmask.long.tbyte 0x00 0.--19. 1. " T_ZQ_SHORT_INTERVAL_X1024 ,Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands" elif ((((per.l(ad:0x5C2000000))&0x01)==0x01)) group.long 0x184++0x03 line.long 0x00 "ZQCTL1,ZQ Control Register 1" hexmask.long.tbyte 0x00 0.--19. 1. " T_ZQ_SHORT_INTERVAL_X1024 ,Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands" else hgroup.long 0x184++0x03 hide.long 0x00 "ZQCTL1,ZQ Control Register 1" endif if (((per.l(ad:0x5C2000000))&0x20)==0x20) group.long 0x188++0x03 line.long 0x00 "ZQCTL2,ZQ Control Register 2" bitfld.long 0x00 0. " ZQ_RESET ,Setting this register bit to 1 triggers a ZQ Reset operation" "Not triggered,Triggered" else hgroup.long 0x188++0x03 hide.long 0x00 "ZQCTL2,ZQ Control Register 2" endif rgroup.long 0x18C++0x03 line.long 0x00 "ZQSTAT,ZQ Status Register" bitfld.long 0x00 0. " ZQ_RESET_BUSY ,ZQ reset operation initialization by soc core" "Possibility of initialization,In progress" group.long 0x190++0x1B line.long 0x00 "DFITMG0,DFI Timing Register 0" bitfld.long 0x00 24.--28. " DFI_T_CTRL_DELAY ,Specifies the number of DFI clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 23. " DFI_RDDATA_USE_SDR ,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values" "HDR,SDR" newline hexmask.long.byte 0x00 16.--22. 1. " DFI_RDDATA_USE_SDR ,Time from the assertion of a read command on the DFI interface to the assertion of the DFI_RDDATA_EN signal" bitfld.long 0x00 15. " DFI_WRDATA_USE_SDR ,Selects whether value in DFITMG0.DFI_TPHY_WRLAT is in terms of SDR or HDR clock cycles" "HDR,SDR" newline bitfld.long 0x00 8.--13. " DFI_TPHY_WRDATA ,Specifies the number of clock cycles between when DFI_WRDATA_EN is asserted to when the associated write data is driven on the dfi_wrdata signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DFI_TPHY_WRLAT ,Number of clocks from the write command to write data enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DFITMG1,DFI Timing Register 1" bitfld.long 0x04 28.--31. " DFI_T_CMD_LAT ,Specifies the number of DFI PHY clock cycles" "0,,,3,4,5,6,,8,?..." bitfld.long 0x04 24.--25. " DFI_T_PARIN_LAT ,Number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven" "0,1,2,3" newline bitfld.long 0x04 16.--20. " DFI_T_WRDATA_DELAY ,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " DFI_T_DRAM_CLK_DISABLE ,Number of DFI clock cycles from the assertion of the DFI_DRAM_CLK_DISABLE signal on the DFI until the clock to the DRAM memory devices at the PHY-DRAM boundary maintains a low value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--4. " DFI_T_DRAM_CLK_ENABLE ,Specifies the number of DFI clock cycles from the de-assertion of the DFI_DRAM_CLK_DISABLE signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "DFILPCFG0,DFI Low Power Configuration Register 0" bitfld.long 0x08 24.--28. " DFI_TLP_RESP ,DFI_TLP_RESP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 20.--23. " DFI_LP_WAKEUP_DPD ,Value in DFI clock cycles to drive on dfi_lp_wakeup signal" "16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,262144,Unlimited" newline bitfld.long 0x08 16. " DFI_LP_EN_DPD ,Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit" "Disabled,Enabled" bitfld.long 0x08 12.--15. " DFI_LP_WAKEUP_SR ,Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered" "16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,262144,Unlimited" newline bitfld.long 0x08 8. " DFI_LP_EN_SR ,Enables DFI low power interface handshaking during self refresh entry/exit" "Disabled,Enabled" bitfld.long 0x08 4.--7. " DFI_LP_WAKEUP_PD ,Value to drive on dfi_lp_wakeup signal when Power Down mode is entered" "16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,262144,Unlimited" newline bitfld.long 0x08 0. " DFI_LP_EN_PD ,Enables DFI low power interface handshaking during power down entry/exit" "Disabled,Enabled" line.long 0x0C "DFILPCFG1,DFI Low Power Configuration Register 1" bitfld.long 0x0C 4.--7. " DFI_LP_WAKEUP_MPSM ,Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "DFIUPD0,DFI Update Register 0" bitfld.long 0x10 31. " DIS_AUTO_CTRLUPD ,Automatic dfi_ctrlupd_req generation by the DDRC" "No,Yes" bitfld.long 0x10 30. " DIS_AUTO_CTRLUPD_SRX ,Auto ctrlupd request generation" "No,Yes" newline bitfld.long 0x10 29. " CTRLUPD_PRE_SRX ,Selects dfi_ctrlupd_req requirements at SRX" "After SRX,Before SRX" hexmask.long.word 0x10 16.--25. 1. " DFI_T_CTRLUP_MAX ,Specifies the maximum number of clock cycles that the dfi_ctrlupd_req signal can assert" newline hexmask.long.word 0x10 0.--9. 1. " DFI_T_CTRLUP_MIN ,Specifies the minimum number of clock cycles that the dfi_ctrlupd_req signal must be asserted" line.long 0x14 "DFIUPD1,DFI Update Register 1" hexmask.long.byte 0x14 16.--23. 1. " DFI_T_CTRLUPD_INTERVAL_MIN_X1024 ,The minimum amount of time between DDRC initiated DFI update requests" hexmask.long.byte 0x14 0.--7. 1. " DFI_T_CTRLUPD_INTERVAL_MAX_X1024 ,The maximum amount of time between DDRC initiated DFI update requests" line.long 0x18 "DFIUPD2,DFI Update Register 2" bitfld.long 0x18 31. " DFI_PHYUPD_EN ,Enables the support for acknowledging PHY- initiated updates" "Disabled,Enabled" if (((per.l(ad:0x5C2000000))&0x20)==0x20) group.long 0x1B0++0x03 line.long 0x00 "DFIMISC,DFI Miscellaneous Control Register" bitfld.long 0x00 8.--12. " DFI_FREQUENCY ,Indicates the operating frequency of the system" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " DFI_INIT_START ,PHY init start request signal" "Not started,Started" newline bitfld.long 0x00 4. " CTL_IDLE_EN ,Enables support of ctl_idle signal" "Disabled,Enabled" bitfld.long 0x00 2. " DFI_DATA_CS_POLARITY ,Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals" "Low,High" newline bitfld.long 0x00 1. " PHY_DBI_MODE ,DBI implemented in DDRC or PHY" "DDRC,PHY" bitfld.long 0x00 0. " DFI_INIT_COMPLETE_EN ,PHY initialization complete enable signal" "Disabled,Enabled" else group.long 0x1B0++0x03 line.long 0x00 "DFIMISC,DFI Miscellaneous Control Register" bitfld.long 0x00 8.--12. " DFI_FREQUENCY ,Indicates the operating frequency of the system" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " DFI_INIT_START ,PHY init start request signal" "Not started,Started" newline bitfld.long 0x00 4. " CTL_IDLE_EN ,Enables support of ctl_idle signal" "Disabled,Enabled" bitfld.long 0x00 2. " DFI_DATA_CS_POLARITY ,Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals" "Low,High" newline bitfld.long 0x00 0. " DFI_INIT_COMPLETE_EN ,PHY initialization complete enable signal" "Disabled,Enabled" endif group.long 0x1B4++0x07 line.long 0x00 "DFITMG2,DFI Timing Register 2" hexmask.long.byte 0x00 8.--14. 1. " DFI_TPHY_RDCSLAT ,Number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted" bitfld.long 0x00 0.--5. " DFI_TPHY_WRCSLAT ,Number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DFITMG3,DFI Timing Register 3" bitfld.long 0x04 0.--4. " DFI_T_GEARDOWN_DELAY ,Delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x1BC++0x03 line.long 0x00 "DFISTAT,DFI Status Register" bitfld.long 0x00 1. " DFI_LP_ACK ,Stores the value of the dfi_lp_ack input to the controller" "0,1" bitfld.long 0x00 0. " DFI_INIT_COMPLETE ,The status flag register which announces when the DFI initialization has been completed" "Not completed,Completed" group.long 0x1C0++0x03 line.long 0x00 "DBICTL,DM/DBI Control Register" bitfld.long 0x00 2. " RD_DBI_EN ,Read DBI enable signal in DDRC" "Disabled,Enabled" bitfld.long 0x00 1. " WR_DBI_EN ,Write DBI enable signal in DDRC" "Disabled,Enabled" newline bitfld.long 0x00 0. " DM_EN ,DM enable signal in DDRC" "Disabled,Enabled" group.long 0x200++0x23 line.long 0x00 "ADDRMAP0,Address Map Register 0" bitfld.long 0x00 0.--4. " ADDRMAP_CS_BIT0 ,Selects the HIF address bit used as rank address bit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,,,31" line.long 0x04 "ADDRMAP1,Address Map Register 1" bitfld.long 0x04 16.--20. " ADDRMAP_BANK_B2 ,Selects the HIF address bit used as bank address bit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " ADDRMAP_BANK_B1 ,Selects the HIF address bits used as bank address bit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--4. " ADDRMAP_BANK_B0 ,Selects the HIF address bits used as bank address bit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "ADDRMAP2,Address Map Register 2" bitfld.long 0x08 24.--27. " ADDRMAP_COL_B5 ,Selects the HIF address bit used as column address bit 5" "0,1,2,3,4,5,6,7,,,,,,,,15" bitfld.long 0x08 16.--19. " ADDRMAP_COL_B4 ,Selects the HIF address bit used as column address bit 4" "0,1,2,3,4,5,6,7,,,,,,,,15" newline bitfld.long 0x08 8.--11. " ADDRMAP_COL_B3 ,Selects the HIF address bit used as column address bit 3" "0,1,2,3,4,5,6,7,?..." bitfld.long 0x08 0.--3. " ADDRMAP_COL_B2 ,Selects the HIF address bit used as column address bit 2" "0,1,2,3,4,5,6,7,?..." line.long 0x0C "ADDRMAP3,Address Map Register 3" bitfld.long 0x0C 24.--27. " ADDRMAP_COL_B9 ,Selects the HIF address bit used as column address bit 9" "0,1,2,3,4,5,6,7,,,,,,,,15" bitfld.long 0x0C 16.--19. " ADDRMAP_COL_B8 ,Selects the HIF address bit used as column address bit 8" "0,1,2,3,4,5,6,7,,,,,,,,15" newline bitfld.long 0x0C 8.--11. " ADDRMAP_COL_B7 ,Selects the HIF address bit used as column address bit 7" "0,1,2,3,4,5,6,7,,,,,,,,15" bitfld.long 0x0C 0.--3. " ADDRMAP_COL_B6 ,Selects the HIF address bit used as column address bit 6" "0,1,2,3,4,5,6,7,,,,,,,,15" line.long 0x10 "ADDRMAP4,Address Map Register 4" bitfld.long 0x10 8.--11. " ADDRMAP_COL_B11 ,Selects the HIF address bit used as column address bit 13" "0,1,2,3,4,5,6,7,,,,,,,,15" bitfld.long 0x10 0.--3. " ADDRMAP_COL_B10 ,Selects the HIF address bit used as column address bit 11" "0,1,2,3,4,5,6,7,,,,,,,,15" line.long 0x14 "ADDRMAP5,Address Map Register 5" bitfld.long 0x14 24.--27. " ADDRMAP_ROW_B11 ,Selects the HIF address bit used as row address bit 11" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" bitfld.long 0x14 16.--19. " ADDRMAP_ROW_B2_10 ,Selects the HIF address bit used as row address bit 2 to 10" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" newline bitfld.long 0x14 8.--11. " ADDRMAP_ROW_B1 ,Selects the HIF address bits used as row address bit 1" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x14 0.--3. " ADDRMAP_ROW_B0 ,Selects the HIF address bits used as row address bit 0" "0,1,2,3,4,5,6,7,8,9,10,11,?..." line.long 0x18 "ADDRMAP6,Address Map Register 6" bitfld.long 0x18 24.--27. " ADDRMAP_ROW_B15 ,Selects the HIF address bit used as row address bit 15" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" bitfld.long 0x18 16.--19. " ADDRMAP_ROW_B14 ,Selects the HIF address bit used as row address bit 14" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" newline bitfld.long 0x18 8.--11. " ADDRMAP_ROW_B13 ,Selects the HIF address bit used as row address bit 13" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" bitfld.long 0x18 0.--3. " ADDRMAP_ROW_B12 ,Selects the HIF address bit used as row address bit 12" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" line.long 0x1C "ADDRMAP7,Address Map Register 7" bitfld.long 0x1C 8.--11. " ADDRMAP_ROW_B17 ,Selects the HIF address bit used as row address bit 17" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" bitfld.long 0x1C 0.--3. " ADDRMAP_ROW_B16 ,Selects the HIF address bit used as row address bit 16" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" line.long 0x20 "ADDRMAP8,Address Map Register 8" bitfld.long 0x20 8.--13. " ADDRMAP_BG_B1 ,Selects the HIF address bits used as bank group address bit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,63" bitfld.long 0x20 0.--4. " ADDRMAP_BG_B0 ,Selects the HIF address bits used as bank group address bit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x5C2000000+0x214))&0xF0000)==0xF0000) group.long 0x224++0x0B line.long 0x00 "ADDRMAP9,Address Map Register 9" bitfld.long 0x00 24.--27. " ADDRMAP_ROW_B5 ,Selects the HIF address bits used as row address bit 5" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x00 16.--19. " ADDRMAP_ROW_B4 ,Selects the HIF address bits used as row address bit 4" "0,1,2,3,4,5,6,7,8,9,10,11,?..." newline bitfld.long 0x00 8.--11. " ADDRMAP_ROW_B3 ,Selects the HIF address bits used as row address bit 3" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x00 0.--3. " ADDRMAP_ROW_B2 ,Selects the HIF address bits used as row address bit 2" "0,1,2,3,4,5,6,7,8,9,10,11,?..." line.long 0x04 "ADDRMAP10,Address Map Register 10" bitfld.long 0x04 24.--27. " ADDRMAP_ROW_B9 ,Selects the HIF address bits used as row address bit 9" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" bitfld.long 0x04 16.--19. " ADDRMAP_ROW_B8 ,Selects the HIF address bits used as row address bit 8" "0,1,2,3,4,5,6,7,8,9,10,11,?..." newline bitfld.long 0x04 8.--11. " ADDRMAP_ROW_B7 ,Selects the HIF address bits used as row address bit 7" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x04 0.--3. " ADDRMAP_ROW_B6 ,Selects the HIF address bits used as row address bit 6" "0,1,2,3,4,5,6,7,8,9,10,11,?..." line.long 0x08 "ADDRMAP11,Address Map Register 11" bitfld.long 0x08 0.--3. " ADDRMAP_ROW_B10 ,Selects the HIF address bits used as row address bit 10" "0,1,2,3,4,5,6,7,8,9,10,11,?..." else hgroup.long 0x224++0x03 hide.long 0x00 "ADDRMAP9,Address Map Register 9" hgroup.long 0x228++0x03 hide.long 0x00 "ADDRMAP10,Address Map Register 10" hgroup.long 0x230++0x03 hide.long 0x00 "ADDRMAP11,Address Map Register 11" endif group.long 0x240++0x07 line.long 0x00 "ODTCFG,ODT configuration register" bitfld.long 0x00 24.--27. " WR_ODT_HOLD ,DFI PHY clock cycles to hold ODT for a write command" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " WR_ODT_DELAY ,Delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--11. " RD_ODT_HOLD ,DFI PHY clock cycles to hold ODT for a read command" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--6. " RD_ODT_DELAY ,Delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "ODTMAP,ODT/Rank Map Register" bitfld.long 0x04 13. " RANK1_RD_ODT[1] ,Indicates bit next to the LSB must be turned on during a read from rank 1" "Not occurred,Occurred" bitfld.long 0x04 12. " [0] ,Indicates LSB must be turned on during a read from rank 1" "Not occurred,Occurred" newline bitfld.long 0x04 9. " RANK1_WR_ODT[1] ,Indicates bit next to the LSB must be turned on during a write to rank 1" "Not occurred,Occurred" bitfld.long 0x04 8. " [0] ,Indicates LSB must be turned on during a write to rank 1" "Not occurred,Occurred" newline bitfld.long 0x04 5. " RANK0_RD_ODT[1] ,Indicates bit next to the LSB must be turned on during a read from rank 0" "0,1" bitfld.long 0x04 4. " [0] ,Indicates LSB must be turned on during a read from rank 0" "0,1" newline bitfld.long 0x04 1. " RANK0_WR_ODT[1] ,Indicates bit next to the LSB must be turned on during a write to rank 0" "0,1" bitfld.long 0x04 0. " [0] ,Indicates LSB must be turned on during a write to rank 0" "0,1" group.long 0x250++0x03 line.long 0x00 "SCHED,Scheduler Control Register" hexmask.long.byte 0x00 24.--30. 1. " RDWR_IDLE_GAP ,When the preferred transaction store is empty for these many clock cycles switch to the alternate transaction store if it is non-empty" bitfld.long 0x00 8.--12. " LPR_NUM_ENTRIES ,Number of entries in the low priority transaction store" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 2. " PAGECLOSE ,Provides a midway between open and close page policies" "Open page policy,Close page policy" bitfld.long 0x00 1. " PREFER_WRITE ,Bank selector prefers writes over reads" "Reads over writes,Writes over reads" newline bitfld.long 0x00 0. " FORCE_LOW_PRI_N ,Active low signal" "Not forced,Forced" if (((per.l(ad:0x5C2000000+0x250))&0x04)==0x04) group.long 0x254++0x03 line.long 0x00 "SCHED1,Scheduler Control Register 1" hexmask.long.byte 0x00 0.--7. 1. " PAGECLOSE_TIMER ,Pageclose timer" else hgroup.long 0x254++0x03 hide.long 0x00 "SCHED1,Scheduler Control Register 1" endif group.long 0x25C++0x03 line.long 0x00 "PERFHPR1,High Priority Read CAM Register 1" hexmask.long.byte 0x00 24.--31. 1. " HPR_XACT_RUN_LENGTH ,Number of transactions that are serviced once the HPR queue goes critical" hexmask.long.word 0x00 0.--15. 1. " HPR_MAX_STARVE ,Number of DFI clocks that the HPR queue can be starved before it goes critical" group.long 0x264++0x03 line.long 0x00 "PERFLPR1,Low Priority Read CAM Register 1" hexmask.long.byte 0x00 24.--31. 1. " LPR_XACT_RUN_LENGTH ,Number of transactions that are serviced once the LPR queue goes critical" hexmask.long.word 0x00 0.--15. 1. " LPR_MAX_STARVE ,Number of DFI clocks that the LPR queue can be starved before it goes critical" group.long 0x26C++0x03 line.long 0x00 "PERFWR1,Write CAM Register 1" hexmask.long.byte 0x00 24.--31. 1. " W_XACT_RUN_LENGTH ,Number of transactions that are serviced once the WR queue goes critical" hexmask.long.word 0x00 0.--15. 1. " W_MAX_STARVE ,Number of DFI clocks that the WR queue can be starved before it goes critical" group.long 0x300++0x07 line.long 0x00 "DBG0,Debug Register 0" bitfld.long 0x00 4. " DIS_COLLISION_PAGE_OPT ,Auto-precharge enable" "Disabled,Enabled" bitfld.long 0x00 2. " DIS_ACT_BYPASS ,Disable bypass path for high priority read activates" "No,Yes" newline bitfld.long 0x00 1. " DIS_RD_BYPASS ,Disable bypass path for high priority read page hits" "No,Yes" bitfld.long 0x00 0. " DIS_WC ,Disable write combine" "No,Yes" line.long 0x04 "DBG1,Debug Register 1" bitfld.long 0x04 1. " DIS_HIF ,HIF disable" "No,Yes" bitfld.long 0x04 0. " DIS_DQ ,De-queue from the CAM disable" "No,Yes" rgroup.long 0x308++0x03 line.long 0x00 "DBGCAM,CAM Debug Register" bitfld.long 0x00 31. " DBG_STALL_RD ,Stall for read channel" "Not stalled,Stalled" bitfld.long 0x00 30. " DBG_STALL_WR ,Stall for write channel" "Not stalled,Stalled" newline bitfld.long 0x00 29. " WR_DATA_PIPELINE_EMPTY ,Indicates that the write data pipeline on the DFI interface is empty" "Not empty,Empty" bitfld.long 0x00 28. " RD_DATA_PIPELINE_EMPTY ,Indicates that the read data pipeline on the DFI interface is empty" "Not empty,Empty" newline bitfld.long 0x00 26. " DBG_WR_Q_EMPTY ,Indicates that all the write command queues and write data buffers inside DDRC are empty" "Not empty,Empty" bitfld.long 0x00 25. " DBG_RD_Q_EMPTY ,Indicates that all the read command queues and read data buffers inside DDRC are empty" "Not empty,Empty" newline bitfld.long 0x00 24. " DBG_STALL ,Stall" "Not stalled,Stalled" bitfld.long 0x00 16.--21. " DBG_W_Q_DEPTH ,Write queue depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " DBG_LPR_Q_DEPTH ,Low priority read queue depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DBG_HPR_Q_DEPTH ,High priority read queue depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x30C++0x03 line.long 0x00 "DBGCMD,Command Debug Register" bitfld.long 0x00 5. " CTRLUPD ,Indicates to the DDRC to issue a dfi_ctrlupd_req to the PHY" "Not issued,Issued" bitfld.long 0x00 4. " ZQ_CALIB_SHORT ,Indicates to the DDRC to issue a ZQCS command to the SDRAM" "No calibration,Calibration" newline bitfld.long 0x00 1. " RANK1_REFRESH ,Indicates to the DDRC to issue a refresh to rank 1" "No refresh,Refresh" bitfld.long 0x00 0. " RANK0_REFRESH ,Indicates to the DDRC to issue a refresh to rank 0" "No refresh,Refresh" rgroup.long 0x310++0x03 line.long 0x00 "DBGSTAT,Status Debug Register" bitfld.long 0x00 5. " CTRLUPD_BUSY ,Ctrlupd operation busy" "Not busy,Busy" bitfld.long 0x00 4. " ZQ_CALIB_SHORT_BUSY ,ZQCS operation busy" "Not busy,Busy" newline bitfld.long 0x00 1. " RANK1_REFRESH_BUSY ,Rank1_refresh operation busy" "Not busy,Busy" bitfld.long 0x00 0. " RANK0_REFRESH_BUSY ,Rank0_refresh operation busy" "Not busy,Busy" group.long 0x320++0x03 line.long 0x00 "SWCTL,Software Register Programming Control Enable" bitfld.long 0x00 0. " SW_DONE ,Enable quasi dynamic register programming outside reset" "Disabled,Enabled" rgroup.long 0x324++0x03 line.long 0x00 "SWSTAT,Software Register Programming Control Status" bitfld.long 0x00 0. " SW_DONE_ACK ,Register programming done" "Not done,Done" group.long 0x36C++0x03 line.long 0x00 "POISONCFG,AXI Poison Configuration Register" bitfld.long 0x00 24. " RD_POISON_INTR_CLR ,Interrupt clear for read transaction poisoning" "Not cleared,Cleared" bitfld.long 0x00 20. " RD_POISON_INTR_EN ,Enables interrupts for read transaction poisoning" "Disabled,Enabled" newline bitfld.long 0x00 16. " RD_POISON_SLVERR_EN ,Enables SLVERR response for read transaction poisoning" "Disabled,Enabled" bitfld.long 0x00 8. " WR_POISON_INTR_CLR ,Interrupt clear for write transaction poisoning" "Not cleared,Cleared" newline bitfld.long 0x00 4. " WR_POISON_INTR_EN ,Enables interrupts for write transaction poisoning" "Disabled,Enabled" bitfld.long 0x00 0. " WR_POISON_SLVERR_EN ,Enables SLVERR response for write transaction poisoning" "Disabled,Enabled" rgroup.long 0x370++0x03 line.long 0x00 "POISONSTAT,AXI Poison Status Register" bitfld.long 0x00 16. " RD_POISON_INTR_0 ,Read transaction poisoning error interrupt for port 0" "Not occurred,Occurred" bitfld.long 0x00 0. " WR_POISON_INTR_0 ,Write transaction poisoning error interrupt for port 0" "Not occurred,Occurred" rgroup.long 0x3FC++0x03 line.long 0x00 "PSTAT,Port Status Register" bitfld.long 0x00 16. " WR_PORT_BUSY_0 ,Indicates if there are outstanding writes for AXI port 0" "Not busy,Busy" bitfld.long 0x00 0. " RD_PORT_BUSY_0 ,Indicates if there are outstanding reads for AXI port 0" "Not busy,Busy" group.long 0x400++0x0B line.long 0x00 "PCCFG,Port Common Configuration Register" bitfld.long 0x00 8. " BL_EXP_MODE ,Burst length expansion mode" "0,1" bitfld.long 0x00 4. " PAGEMATCH_LIMIT ,Page match four limit" "No limit,Limit" newline bitfld.long 0x00 0. " GO2CRITICAL_EN ,Sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals" "Disabled,Enabled" line.long 0x04 "PCFGR_0,Port 0 Configuration Read Register" bitfld.long 0x04 16. " RDWR_ORDERED_EN ,Enable ordered read/writes" "Disabled,Enabled" bitfld.long 0x04 14. " RD_PORT_PAGEMATCH_EN ,Enables the Page Match feature" "Disabled,Enabled" newline bitfld.long 0x04 13. " RD_PORT_PAGEMATCH_EN ,Enables the AXI urgent sideband signal" "Disabled,Enabled" bitfld.long 0x04 12. " RD_PORT_AGING_EN ,Enables aging function for the read channel of the port" "Disabled,Enabled" newline hexmask.long.word 0x04 0.--9. 1. " RD_PORT_PRIORITY ,Determines the initial load value of read aging counters" line.long 0x08 "PCFGW_0,Port n Configuration Write Register" bitfld.long 0x08 14. " WR_PORT_PAGEMATCH_EN ,Enables the Page Match feature" "Disabled,Enabled" bitfld.long 0x08 13. " WR_PORT_URGENT_EN ,Enables the AXI urgent sideband signal" "Disabled,Enabled" newline bitfld.long 0x08 12. " WR_PORT_AGING_EN ,Enables aging function for the write channel of the port" "Disabled,Enabled" hexmask.long.word 0x08 0.--9. 1. " WR_PORT_PRIORITY ,Determines the initial load value of write aging counters" group.long 0x490++0x13 line.long 0x00 "PCTRL_0,Port 0 Control Register" bitfld.long 0x00 0. " PORT_EN ,Enables AXI port n" "Disabled,Enabled" line.long 0x04 "PCFGQOS0_0,Port 0 Read QoS Configuration Register 0" bitfld.long 0x04 20.--21. " RQOS_MAP_REGION1 ,Indicates the traffic class of region 1" "LPR,VPR,HPR,?..." bitfld.long 0x04 16.--17. " RQOS_MAP_REGION0 ,This bitfield indicates the traffic class of region 0" "LPR,VPR,HPR,?..." newline bitfld.long 0x04 0.--3. " RQOS_MAP_LEVEL1 ,Separation level1 indicating the end of region0 mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,?..." line.long 0x08 "PCFGQOS1_0,Port n Read QoS Configuration Register 1" hexmask.long.word 0x08 16.--26. 1. " RQOS_MAP_TIMEOUTR ,Specifies the timeout value for transactions mapped to the red address queue" hexmask.long.word 0x08 0.--10. 1. " RQOS_MAP_TIMEOUTB ,Specifies the timeout value for transactions mapped to the blue address queue" line.long 0x0C "PCFGWQOS0_0,Port n Write QoS Configuration Register 0" bitfld.long 0x0C 20.--21. " WQOS_MAP_REGION1 ,This bitfield indicates the traffic class of region 1" "NPW,VPW,?..." bitfld.long 0x0C 16.--17. " WQOS_MAP_REGION0 ,This bitfield indicates the traffic class of region 0" "NPW,VPW,?..." newline bitfld.long 0x0C 0.--3. " WQOS_MAP_LEVEL ,Separation level indicating the end of region0 mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,?..." line.long 0x10 "PCFGWQOS1_0,Port n Write QoS Configuration Register 1" hexmask.long.word 0x10 0.--10. 1. " WQOS_MAP_TIMEOUT ,Specifies the timeout value for write transactions" newline tree "SHADOW Registers" if (((per.l(ad:0x5C2000000))&0x20)==0x20) group.long 0x2020++0x07 line.long 0x00 "DERATEEN_SHADOW,Temperature Derate Enable Register" bitfld.long 0x00 8.--9. " RC_DERATE_VALUE ,Derate value of tRC for LPDDR4" "+1,+2,+3,+4" bitfld.long 0x00 4.--7. " DERATE_BYTE ,Derate value of tRC for LPDDR4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1. " DERATE_VALUE ,Derate value" "+1,+2" bitfld.long 0x00 0. " DERATE_ENABLE ,Enables derating" "Disabled,Enabled" line.long 0x04 "DERATEINT_SHADOW,Temperature Derate Interval Register" elif ((((per.l(ad:0x5C2000000))&0x08)==0x08)||(((per.l(ad:0x5C2000000))&0x04)==0x04)) group.long 0x2020++0x07 line.long 0x00 "DERATEEN_SHADOW,Temperature Derate Enable Register" bitfld.long 0x00 4.--7. " DERATE_BYTE ,Derate value of tRC for LPDDR4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " DERATE_VALUE ,Derate value" "+1,+2" newline bitfld.long 0x00 0. " DERATE_ENABLE ,Enables derating" "Disabled,Enabled" line.long 0x04 "DERATEINT_SHADOW,Temperature Derate Interval Register" else hgroup.long 0x2020++0x03 hide.long 0x00 "DERATEEN_SHADOW,Temperature Derate Enable Register" hgroup.long 0x2024++0x03 hide.long 0x00 "DERATEINT_SHADOW,Temperature Derate Interval Register" endif if (((per.l(ad:0x5C2000000))&0x20)==0x20) group.long 0x2050++0x03 line.long 0x00 "RFSHCTL0_SHADOW,Refresh Control Register 0" bitfld.long 0x00 20.--23. " REFRESH_MARGIN ,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--16. " REFRESH_TO_X32 ,Speculative refreshes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4.--8. " REFRESH_BURST ,Number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 2. " PER_BANK_REFRESH ,Per bank refresh" "Per bank,All bank" else group.long 0x2050++0x03 line.long 0x00 "RFSHCTL0_SHADOW,Refresh Control Register 0" bitfld.long 0x00 20.--23. " REFRESH_MARGIN ,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--16. " REFRESH_TO_X32 ,Speculative refreshes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4.--8. " REFRESH_BURST ,Number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif group.long 0x2064++0x03 line.long 0x00 "RFSHTMG_SHADOW,Refresh Timing Register" hexmask.long.word 0x00 16.--27. 1. " T_RFC_NOM_X32 ,Average time interval between refreshes per rank" bitfld.long 0x00 15. " LPDDR3_TREFBW_EN ,tREFBW parameter enabled" "Disabled,Enabled" newline hexmask.long.word 0x00 0.--9. 1. " T_RFC_MIN ,Minimum time from refresh to refresh or activate" group.long 0x20DC++0x07 line.long 0x00 "INIT3_SHADOW,SDRAM Initialization Register 3" hexmask.long.word 0x00 16.--31. 1. " MR ,Value to write to MR register" hexmask.long.word 0x00 0.--15. 1. " EMR ,Value to write to EMR register" line.long 0x04 "INIT4_SHADOW,SDRAM Initialization Register 4" hexmask.long.word 0x04 16.--31. 1. " EMR2 ,Value to write to EMR2 register" hexmask.long.word 0x04 0.--15. 1. " EMR3 ,Value to write to EMR3 register" hgroup.long 0x20E8++0x03 hide.long 0x00 "INIT6_SHADOW,SDRAM Initialization Register 6" hgroup.long 0x20EC++0x03 hide.long 0x00 "INIT7_SHADOW,SDRAM Initialization Register 7" group.long 0x2100++0x0B line.long 0x00 "DRAMTMG0_SHADOW,SDRAM Timing Register 0" hexmask.long.byte 0x00 24.--30. 1. " WR2PRE ,Minimum time between write and precharge to same bank" bitfld.long 0x00 16.--21. " T_FAW ,T_FAW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x00 8.--14. 1. " T_RAS_MAX ,Maximum time between activate and precharge to same bank" bitfld.long 0x00 0.--5. " T_RAS_MIN ,Minimum time between activate and precharge to the same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DRAMTMG1_SHADOW,SDRAM Timing Register 1" bitfld.long 0x04 16.--20. " T_XP ,Minimum time after power-down exit to any operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--13. " RD2PRE ,Minimum time from read to precharge of same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x04 0.--6. 1. " T_RC ,Minimum time between activates to same bank" line.long 0x08 "DRAMTMG2_SHADOW,SDRAM Timing Register 2" bitfld.long 0x08 24.--29. " WRITE_LATENCY ,Set to WL time from write command to write data on SDRAM interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " READ_LATENCY ,Set to RL time from read command to read data on SDRAM interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " RD2WR ,Minimum time from read command to write command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " WR2RD ,Minimum time from write command to read command for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if ((((per.l(ad:0x5C2000000))&0x20)==0x20)||(((per.l(ad:0x5C2000000))&0x08)==0x08)||(((per.l(ad:0x5C2000000))&0x04)==0x04)) group.long 0x210C++0x03 line.long 0x00 "DRAMTMG3_SHADOW,SDRAM Timing Register 3" hexmask.long.word 0x00 20.--29. 1. " T_MRW ,Time to wait after a mode register write or read (MRW or MRR)" bitfld.long 0x00 12.--17. " T_MRD ,Cycles to wait after a mode register write or read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.l(ad:0x5C2000000))&0x01)==0x01) group.long 0x210C++0x03 line.long 0x00 "DRAMTMG3_SHADOW,SDRAM Timing Register 3" textfld " " bitfld.long 0x00 12.--17. " T_MRD ,Cycles to wait after a mode register write or read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 0.--9. 1. " T_MOD ,Cycles between load mode command and following non-load mode command" else group.long 0x210C++0x03 line.long 0x00 "DRAMTMG3_SHADOW,SDRAM Timing Register 3" textfld " " bitfld.long 0x00 12.--17. " T_MRD ,Cycles to wait after a mode register write or read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x2110++0x07 line.long 0x00 "DRAMTMG4_SHADOW,SDRAM Timing Register 4" bitfld.long 0x00 24.--28. " T_RCD ,Minimum time from activate to read or write command to same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--19. " T_CCD ,This is the minimum time between two reads or two writes for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " T_RRD ,Minimum time between activates from bank a to bank b for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " T_RP ,Minimum time from precharge to activate of same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DRAMTMG5_SHADOW,SDRAM Timing Register 5" bitfld.long 0x04 24.--27. " T_CKSRX ,Time before self refresh exit that ck is maintained as a valid clock before issuing SRX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " T_CKSRE ,Time after self refresh down entry that CK is maintained as a valid clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--13. " T_CKESR ,Minimum CKE low width for self refresh or self refresh power down entry to exit timing in memory clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--4. " T_CKE ,Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x5C2000000))&0x20)==0x20) group.long 0x2118++0x07 line.long 0x00 "DRAMTMG6_SHADOW,SDRAM Timing Register 6" bitfld.long 0x00 24.--27. " T_CKDPDE ,Time after deep power down entry that CK is maintained as a valid clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " T_CKDPDX ,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " T_CKCSX ,Time before clock stop exit that CK is maintained as a valid clock before issuing clock stop exit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DRAMTMG7_SHADOW,SDRAM Timing Register 7" bitfld.long 0x04 8.--11. " T_CKPDE ,This is the time after Power Down Entry that CK is maintained as a valid clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " T_CKPDX ,This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x2118++0x03 line.long 0x00 "DRAMTMG6_SHADOW,SDRAM Timing Register 6" bitfld.long 0x00 24.--27. " T_CKDPDE ,Time after deep power down entry that CK is maintained as a valid clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " T_CKDPDX ,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0x211C++0x03 hide.long 0x00 "DRAMTMG7_SHADOW,SDRAM Timing Register 7" endif if (((per.l(ad:0x5C2000000))&0x01)==0x01) group.long 0x2120++0x03 line.long 0x00 "DRAMTMG8_SHADOW,SDRAM Timing Register 8" hexmask.long.byte 0x00 24.--30. 1. " T_XS_FAST_X32 ,Exit self refresh to ZQCL ZQCS and MRS" hexmask.long.byte 0x00 16.--22. 1. " T_XS_ABORT_X32 ,Exit Self Refresh to commands not requiring a locked DLL in self refresh abort" newline hexmask.long.byte 0x00 8.--14. 1. " T_XS_DLL_X32 ,Exit self refresh to commands requiring a locked DLL" hexmask.long.byte 0x00 0.--6. 1. " T_XS_X32 ,Exit self refresh to commands not requiring a locked DLL" else group.long 0x2120++0x03 line.long 0x00 "DRAMTMG8_SHADOW,SDRAM Timing Register 8" hexmask.long.byte 0x00 24.--30. 1. " T_XS_FAST_X32 ,Exit self refresh to ZQCL ZQCS and MRS" hexmask.long.byte 0x00 16.--22. 1. " T_XS_ABORT_X32 ,Exit Self Refresh to commands not requiring a locked DLL in self refresh abort" endif hgroup.long 0x2124++0x03 hide.long 0x00 "DRAMTMG9_SHADOW,SDRAM Timing Register 9" group.long 0x2128++0x03 line.long 0x00 "DRAMTMG10_SHADOW,SDRAM Timing Register 10" bitfld.long 0x00 16.--20. " T_SYNC_GEAR ,Indicates the time between MRS command and the sync pulse time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " T_CMD_GEAR ,Sync pulse to first valid command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 2.--3. " T_GEAR_SETUP ,Geardown setup time" "0,1,2,3" bitfld.long 0x00 0.--1. " T_GEAR_HOLD ,Geardown hold time" "0,1,2,3" hgroup.long 0x212C++0x03 hide.long 0x00 "DRAMTMG11_SHADOW,SDRAM Timing Register 11" group.long 0x2130++0x07 line.long 0x00 "DRAMTMG12_SHADOW,SDRAM Timing Register 12" bitfld.long 0x00 16.--17. " T_CMDCKE ,Delay from valid command to CKE input LOW" "0,1,2,3" bitfld.long 0x00 8.--11. " T_CKEHCMD ,Valid command requirement after CKE input HIGH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--4. " T_MRD_PDA ,This is the Mode Register Set command cycle time in PDA mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DRAMTMG13_SHADOW,SDRAM Timing Register 13" hexmask.long.byte 0x04 24.--30. 1. " ODTLOFF ,Latency from CAS-2 command to tODToff reference" bitfld.long 0x04 16.--21. " T_CCD_MW ,This is the minimum time from write or masked write to masked write command for same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 0.--2. " T_PPD ,Minimum time from precharge to precharge command" "0,1,2,3,4,5,6,7" if (((per.l(ad:0x5C2000000))&0x20)==0x20) group.long 0x2138++0x03 line.long 0x00 "DRAMTMG14_SHADOW,SDRAM Timing Register 14" hexmask.long.word 0x00 0.--11. 1. " T_XSR ,Exit Self Refresh to any command" else hgroup.long 0x2138++0x03 hide.long 0x00 "DRAMTMG14_SHADOW,SDRAM Timing Register 14" endif group.long 0x213C++0x03 line.long 0x00 "DRAMTMG15_SHADOW,SDRAM Timing Register 15" bitfld.long 0x00 31. " EN_DFI_LP_T_STAB ,Enables using tSTAB" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " T_STAB_X32 ,Stabilization time" if ((((per.l(ad:0x5C2000000))&0x01)==0x01)||(((per.l(ad:0x5C2000000))&0x20)==0x20)) group.long 0x2180++0x03 line.long 0x00 "ZQCTL0_SHADOW,ZQ Control Register 0" bitfld.long 0x00 31. " DIS_AUTO_ZQ ,Disable DDRC generation of ZQCS/MPC command" "No,Yes" bitfld.long 0x00 30. " DIS_SRX_ZQCL ,Disable issuing of ZQCL/MPC(ZQ calibration) command at self-refresh/sr-powerdown exit" "No,Yes" newline bitfld.long 0x00 29. " ZQ_RESISTOR_SHARED ,ZQ resistor is shared between ranks" "Not shared,Shared" newline hexmask.long.word 0x00 16.--26. 1. " T_ZQ_LONG_NOP ,Number of DFI clock cycles of NOP required after a ZQCL/MPC command is issued to SDRAM" hexmask.long.word 0x00 0.--9. 1. " T_ZQ_SHORT_NOP ,Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM" else hgroup.long 0x2180++0x03 hide.long 0x00 "ZQCTL0_SHADOW,ZQ Control Register 0" endif group.long 0x2190++0x07 line.long 0x00 "DFITMG0_SHADOW,DFI Timing Register 0" bitfld.long 0x00 24.--28. " DFI_T_CTRL_DELAY ,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 23. " DFI_RDDATA_USE_SDR ,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR(DFI PHY clock) values" "HDR,SDR" newline hexmask.long.byte 0x00 16.--22. 1. " DFI_T_RDDATA_EN ,Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal" bitfld.long 0x00 15. " DFI_WRDATA_USE_SDR ,Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values" "HDR,SDR" newline bitfld.long 0x00 8.--13. " DFI_TPHY_WRDATA ,Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal" "0,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 0.--5. " DFI_TPHY_WRLAT ,Write latency number of clocks from the write command to write data enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DFITMG1_SHADOW,DFI Timing Register 1" bitfld.long 0x04 28.--31. " DFI_T_CMD_LAT ,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven" "0,,,3,4,5,6,,8,?..." bitfld.long 0x04 24.--25. " DFI_T_PARIN_LAT ,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven" "0,1,2,3" newline bitfld.long 0x04 16.--20. " DFI_T_WRDATA_DELAY ,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " DFI_T_DRAM_CLK_DISABLE ,Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--4. " DFI_T_DRAM_CLK_ENABLE ,Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x21B4++0x07 line.long 0x00 "DFITMG2_SHADOW,DFI Timing Register 2" hexmask.long.byte 0x00 8.--14. 1. " DFI_TPHY_RDCSLAT ,Number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted" bitfld.long 0x00 0.--5. " DFI_TPHY_WRCSLAT ,Number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DFITMG3_SHADOW,DFI Timing Register 3" bitfld.long 0x04 0.--4. " DFI_T_GEARDOWN_DELAY ,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x2240++0x03 line.long 0x00 "ODTCFG_SHADOW,ODT Configuration Register" bitfld.long 0x00 24.--27. " WR_ODT_HOLD ,DFI PHY clock cycles to hold ODT for a write command" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " WR_ODT_DELAY ,The delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--11. " RD_ODT_HOLD ,DFI PHY clock cycles to hold ODT for a read command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--6. " RD_ODT_DELAY ,The delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end width 0x0B tree.end tree "DDRP0_1 (DDR PHY)" base ad:0x5C210000 width 14. rgroup.long 0x00++0x03 line.long 0x00 "RIDR,Revision Identification Register" hexmask.long.byte 0x00 24.--31. 1. " UDRID ,User-Defined revision ID" hexmask.long.byte 0x00 20.--23. 1. " PHYMJR ,PHY major revision" hexmask.long.byte 0x00 16.--19. 1. " PHYMDR ,PHY moderate revision" hexmask.long.byte 0x00 12.--15. 1. " PHYMNR ,PHY minor revision" newline hexmask.long.byte 0x00 8.--11. 1. " PUBMJR ,PUB major revision" hexmask.long.byte 0x00 4.--7. 1. " PUBMDR ,PUB moderate revision" hexmask.long.byte 0x00 0.--3. 1. " PUBMNR ,PUB minor revision" group.long 0x04++0x03 line.long 0x00 "PIR,PHY Initialization Register" bitfld.long 0x00 30. " ZCALBYP ,Impedance calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 29. " DCALPSE ,Digital delay line calibration pause" "Not paused,Paused" bitfld.long 0x00 20. " DQS2DQ ,Write DQS2DQ training" "Disabled,Enabled" bitfld.long 0x00 19. " RDIMMINIT ,RDIMM initialization" "Disabled,Enabled" newline bitfld.long 0x00 18. " CTLDINIT ,Controller DRAM initialization" "Disabled,Enabled" bitfld.long 0x00 17. " VREF ,VREF training" "Disabled,Enabled" bitfld.long 0x00 16. " SRD ,Static read training" "Disabled,Enabled" bitfld.long 0x00 15. " WREYE ,Write data eye training" "Disabled,Enabled" newline bitfld.long 0x00 14. " RDEYE ,Read data eye training" "Disabled,Enabled" bitfld.long 0x00 13. " WRDSKW ,Write data bit deskew" "Disabled,Enabled" bitfld.long 0x00 12. " RDDSKW ,Read data bit deskew" "Disabled,Enabled" bitfld.long 0x00 11. " WLADJ ,Write leveling adjust" "Disabled,Enabled" newline bitfld.long 0x00 10. " QSGATE ,Read DQS gate training" "Disabled,Enabled" bitfld.long 0x00 9. " WL ,Write leveling" "Disabled,Enabled" bitfld.long 0x00 8. " DRAMINIT ,DRAM initialization" "Disabled,Enabled" bitfld.long 0x00 7. " DRAMRST ,DRAM reset" "No reset,Reset" newline bitfld.long 0x00 6. " PHYRST ,PHY reset" "No reset,Reset" bitfld.long 0x00 5. " DCAL ,Digital delay line calibration" "Disabled,Enabled" bitfld.long 0x00 4. " PLLINIT ,PLL initialization" "Disabled,Enabled" bitfld.long 0x00 2. " CA ,CA training" "Disabled,Enabled" newline bitfld.long 0x00 1. " ZCAL ,Impedance calibration" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization trigger" "Not triggered,Triggered" group.long 0x10++0x1F line.long 0x00 "PGCR0,PHY General Configuration Register 0" bitfld.long 0x00 31. " ADCP ,Address copy" "Disabled,Enabled" bitfld.long 0x00 26. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 24.--25. " OSCACDL ,Oscillator mode address/command delay line select" "0,1,2,3" bitfld.long 0x00 14.--18. " DTOSEL ,Digital test output select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 9.--12. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "PGCR1,PHY General Configuration Register 1" bitfld.long 0x04 31. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x04 28. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value (equivalent to one CK period)" "Not loaded,Loaded" bitfld.long 0x04 27. " DLTST ,Delay line test start" "Stopped,Started" bitfld.long 0x04 26. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x04 25. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x04 24. " ACVLDTRN ,AC loopback valid train" "0,1" bitfld.long 0x04 21.--23. " ACVLDDLY ,AC loopback valid delay" "0,1,2,3,4,5,6,7" bitfld.long 0x04 20. " LRDIMMST ,LRDIMM software training" "Disabled,Enabled" newline bitfld.long 0x04 18. " UPDMSTRC0 ,DFI update master channel 0" "Not updated,Updated" bitfld.long 0x04 17. " DISDIC ,Enable/disable control for DFI_INIT_COMPLETE" "Disabled,Enabled" bitfld.long 0x04 16. " ACPDDC ,AC power-down with dual channels" "Disabled,Enabled" bitfld.long 0x04 15. " DUALCHN ,Dual channel configuration" "Disabled,Enabled" newline bitfld.long 0x04 13.--14. " FDEPTH ,Filter depth" "0,1,2,3" bitfld.long 0x04 11.--12. " LPFDEPTH ,Low-pass filter depth" "0,1,2,3" bitfld.long 0x04 10. " LPFEN ,Low-pass filter enable" "Disabled,Enabled" bitfld.long 0x04 9. " MDLEN ,Master delay line enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " PUBMODE ,Enable the PUB to control the interface to the PHY and SDRAM" "Disabled,Enabled" bitfld.long 0x04 5. " CAST ,CA software training" "Disabled,Enabled" bitfld.long 0x04 4. " DX_DQSOUT_DIFF ,Select PDIFF cell for DQS generation" "0,1" bitfld.long 0x04 3. " AC_CKOUT_DIFF ,Select PDIFF cell for CK generation" "0,1" newline bitfld.long 0x04 2. " WLSTEP ,Write leveling step" "0,1" bitfld.long 0x04 1. " WLMODE ,Write leveling software mode" "Disabled,Enabled" bitfld.long 0x04 0. " DTOMODE ,Digital test output mode" "Disabled,Enabled" line.long 0x08 "PGCR2,PHY General Configuration Register 2" bitfld.long 0x08 31. " CLRTSTAT ,Clear training status registers" "No effect,Cleared" bitfld.long 0x08 30. " CLRZCAL ,Clear impedance calibration" "No effect,Cleared" bitfld.long 0x08 29. " CLRPERR ,Clear parity error" "No effect,Cleared" bitfld.long 0x08 28. " ICPC ,Initialization complete pin configuration" "0,1" newline hexmask.long.byte 0x08 20.--27. 1. " DTPMXTMR ,Data training PUB mode exit timer" bitfld.long 0x08 19. " INITFSMBYP ,Initialization bypass" "Not bypassed,Bypassed" bitfld.long 0x08 18. " PLLFSMBYP ,PLL FSM bypass" "Not bypassed,Bypassed" hexmask.long.tbyte 0x08 0.--17. 1. " TREFPRD ,Refresh period" line.long 0x0C "PGCR3,PHY General Configuration Register 3" hexmask.long.byte 0x0C 24.--31. 1. " CKNEN ,CKN enable" hexmask.long.byte 0x0C 16.--23. 1. " CKEN ,CK enable" bitfld.long 0x0C 13.--14. " GATEACRDCLK ,Enable clock gating for AC [0] CTL_RD_CLK" "0,1,2,3" bitfld.long 0x0C 11.--12. " GATEACDDRCLK ,Enable clock gating for AC [0] DDR_CLK" "0,1,2,3" newline bitfld.long 0x0C 9.--10. " GATEACCTLCLK ,Enable clock gating for AC [0] CTL_CLK" "0,1,2,3" bitfld.long 0x0C 6.--7. " DDLBYPMODE ,Controls DDL bypass modes" "0,1,2,3" bitfld.long 0x0C 5. " IOLB ,IO loopback select" "0,1" bitfld.long 0x0C 3.--4. " RDMODE ,AC receive FIFO read mode" "0,1,2,3" newline bitfld.long 0x0C 2. " DISRST ,Read FIFO reset disable" "No,Yes" bitfld.long 0x0C 0.--1. " CLKLEVEL ,Clock level when clock gating" "0,1,2,3" line.long 0x10 "PGCR4,PHY General Configuration Register 4" bitfld.long 0x10 29. " ACDDLLD ,AC DDL delay select dynamic load" "Disabled,Enabled" bitfld.long 0x10 24.--28. " ACDDLBYP ,AC DDL bypass" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 23. " OEDDLBYP ,AC OE DDL bypass" "Not bypassed,Bypassed" bitfld.long 0x10 22. " TEDDLBYP ,AC ODT DDL bypass" "Not bypassed,Bypassed" newline bitfld.long 0x10 21. " PDRDDLBYP ,AC PDR DDL bypass" "Not bypassed,Bypassed" bitfld.long 0x10 20. " RRRMODE ,AC macro read path rise-to-rise mode" "Disabled,Enabled" bitfld.long 0x10 19. " WRRMODE ,AC macro write path rise-to-rise mode" "Disabled,Enabled" bitfld.long 0x10 17. " DCALTYPE ,DDL calibration type" "0,1" newline hexmask.long.word 0x10 8.--16. 1. " DCALSVAL ,DDL calibration starting value" bitfld.long 0x10 4.--7. " LPWAKEUP_THRSH ,AC low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 1. " LPPLLPD ,AC low power PLL power down" "Disabled,Enabled" bitfld.long 0x10 0. " LPIOPD ,AC low power IO power down" "Disabled,Enabled" line.long 0x14 "PGCR5,PHY General Configuration Register 5" hexmask.long.byte 0x14 24.--31. 1. " FRQBT ,Frequency B ratio term" hexmask.long.byte 0x14 16.--23. 1. " FRQAT ,Frequency A ratio term" hexmask.long.byte 0x14 8.--15. 1. " DISCNPERIOD ,DFI disconnect time period" bitfld.long 0x14 4.--7. " VREF_RBCTRL ,Receiver bias core side control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 2. " DXREFISELRANGE ,Internal VREF generator REFSEL range select" "0,1" bitfld.long 0x14 1. " DDLPGACT ,DDL page read write select" "Read,Write" bitfld.long 0x14 0. " DDLPGRW ,DDL page read write select" "Read,Write" line.long 0x18 "PGCR6,PHY General Configuration Register 6" hexmask.long.byte 0x18 16.--23. 1. " DLDLMT ,Delay line VT drift limit" bitfld.long 0x18 13. " ACDLVT ,AC address/command delay LCDL VT compensation" "Disabled,Enabled" bitfld.long 0x18 12. " ACBVT ,Address/command bit delay VT compensation" "Disabled,Enabled" bitfld.long 0x18 11. " ODTBVT ,ODT bit delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x18 10. " CKEBVT ,CKE bit delay VT compensation" "Disabled,Enabled" bitfld.long 0x18 9. " CSNBVT ,CSN bit delay VT compensation" "Disabled,Enabled" bitfld.long 0x18 8. " CKBVT ,CK bit delay VT compensation" "Disabled,Enabled" bitfld.long 0x18 1. " FVT ,Forced VT compensation trigger" "Not triggered,Triggered" newline bitfld.long 0x18 0. " INHVT ,VT calculation inhibit" "Disabled,Enabled" line.long 0x1C "PGCR7,PHY General Configuration Register 7" bitfld.long 0x1C 5. " ACCALCLK ,AC calibration clock select" "0,1" bitfld.long 0x1C 4. " ACRCLKMD ,AC read clock mode" "Disabled,Enabled" bitfld.long 0x1C 3. " ACDLDT ,AC DDL load type" "0,1" bitfld.long 0x1C 1. " ACDTOSEL ,AC digital test output select" "0,1" newline bitfld.long 0x1C 0. " ACTMODE ,AC test mode" "Disabled,Enabled" rgroup.long 0x30++0x0B line.long 0x00 "PGSR0,PHY General Status Register 0" bitfld.long 0x00 31. " APLOCK ,AC PLL lock" "Not locked,Locked" bitfld.long 0x00 30. " SRDERR ,Static read error" "No error,Error" bitfld.long 0x00 29. " CAWRN ,CA training warning" "Not occurred,Occurred" bitfld.long 0x00 28. " CAERR ,CA training error" "No error,Error" newline bitfld.long 0x00 27. " WEERR ,Write eye training error" "No error,Error" bitfld.long 0x00 26. " REERR ,Read eye training error" "No error,Error" bitfld.long 0x00 25. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x00 24. " RDERR ,Read bit deskew error" "No error,Error" newline bitfld.long 0x00 23. " WLAERR ,Write leveling adjustment error" "No error,Error" bitfld.long 0x00 22. " QSGERR ,DQS gate training error" "No error,Error" bitfld.long 0x00 21. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x00 20. " ZCERR ,Impedance calibration error" "No error,Error" newline bitfld.long 0x00 19. " VERR ,VREF training error" "No error,Error" bitfld.long 0x00 18. " DQS2DQERR ,Write DQS2DQ training error" "No error,Error" bitfld.long 0x00 15. " DQS2DQDONE ,Write DQS2DQ training done" "Not done,Done" bitfld.long 0x00 14. " VDONE ,VREF training done" "Not done,Done" newline bitfld.long 0x00 13. " SRDDONE ,Static read done" "Not done,Done" bitfld.long 0x00 12. " CADONE ,CA training done" "Not done,Done" bitfld.long 0x00 11. " WEDONE ,Write eye training done" "Not done,Done" bitfld.long 0x00 10. " REDONE ,Read eye training done" "Not done,Done" newline bitfld.long 0x00 9. " WDDONE ,Write bit deskew done" "Not done,Done" bitfld.long 0x00 8. " RDDONE ,Read bit deskew done" "Not done,Done" bitfld.long 0x00 7. " WLADONE ,Write leveling adjustment done" "Not done,Done" bitfld.long 0x00 6. " QSGDONE ,DQS gate training done" "Not done,Done" newline bitfld.long 0x00 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x00 4. " DIDONE ,DRAM initialization done" "Not done,Done" bitfld.long 0x00 3. " ZCDONE ,Impedance calibration done" "Not done,Done" bitfld.long 0x00 2. " DCDONE ,Digital delay line calibration done" "Not done,Done" newline bitfld.long 0x00 1. " PLDONE ,PLL lock done" "Not done,Done" bitfld.long 0x00 0. " IDONE ,Initialization done" "Not done,Done" line.long 0x04 "PGSR1,PHY General Status Register 1" bitfld.long 0x04 31. " PARERR ,RDIMM parity error" "No error,Error" bitfld.long 0x04 30. " VTSTOP ,VT stop" "Not stopped,Stopped" hexmask.long.tbyte 0x04 1.--24. 1. " DLTCODE ,Delay line test code for AC macro 0" bitfld.long 0x04 0. " DLTDONE ,Delay line test done for AC macro 0" "Not done,Done" line.long 0x08 "PGSR2,PHY General Status Register 2" hexmask.long.tbyte 0x08 1.--24. 1. " DLTCODE ,Delay line test code for AC macro 1" bitfld.long 0x08 0. " DLTDONE ,Delay line test done for AC macro 1" "Not done,Done" newline group.long 0x40++0x1B line.long 0x00 "PTR0,PHY Timing Register 0" hexmask.long.word 0x00 21.--31. 1. " TPLLPD ,PLL power-down time" hexmask.long.tbyte 0x00 6.--20. 1. " TPLLGS ,PLL gear shift time" bitfld.long 0x00 0.--5. " TPHYRST ,PHY reset time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "PTR1,PHY Timing Register 1" hexmask.long.word 0x04 16.--31. 1. " TPLLLOCK ,PLL lock time" hexmask.long.word 0x04 0.--12. 1. " TPLLRST ,PLL reset time" line.long 0x08 "PTR2,PHY Timing Register 2" bitfld.long 0x08 15.--19. " TWLDLYS ,Write leveling delay settling time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 10.--14. " TCALH ,Calibration hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 5.--9. " TCALS ,Calibration setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 0.--4. " TCALON ,Calibration on time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "PTR3,PHY Timing Register 3" hexmask.long.tbyte 0x0C 0.--22. 1. " TDINIT0 ,DRAM initialization time 0" line.long 0x10 "PTR4,PHY Timing Register 4" hexmask.long.word 0x10 0.--12. 1. " TDINIT1 ,DRAM initialization time 1" line.long 0x14 "PTR5,PHY Timing Register 5" hexmask.long.tbyte 0x14 0.--18. 1. " TDINIT2 ,DRAM initialization time 2" line.long 0x18 "PTR6,PHY Timing Register 6" hexmask.long.byte 0x18 20.--26. 1. " TDINIT4 ,DRAM initialization time 4" hexmask.long.word 0x18 0.--11. 1. " TDINIT3 ,DRAM initialization time 3" group.long 0x68++0x17 line.long 0x00 "PLLCR0,PLL Control Register 0" bitfld.long 0x00 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x00 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x00 28. " RSTOPM ,Reference stop mode" "Disabled,Enabled" newline bitfld.long 0x00 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x00 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12. " GSHIFT ,Gear shift" "Disabled,Enabled" bitfld.long 0x00 8. " ATOEN ,Analog test enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "PLLCR1,PLL Control Register 1" hexmask.long.word 0x04 16.--31. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x04 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x04 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypassed,Bypassed" bitfld.long 0x04 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x04 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x04 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x04 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x08 "PLLCR2,PLL Control Register 2" line.long 0x0C "PLLCR3,PLL Control Register 3" line.long 0x10 "PLLCR4,PLL Control Register 4" line.long 0x14 "PLLCR5,PLL Control Register 5" hexmask.long.byte 0x14 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL generator control bus PLL_CTRL" group.long 0x88++0x03 line.long 0x00 "DXCCR,DATX8 Common Configuration Register" bitfld.long 0x00 29. " RKLOOP ,Rank looping (per-rank eye centering) enable" "Disabled,Enabled" bitfld.long 0x00 3.--6. " DQS2DQMPER ,Write DQS2DQ training measurement period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x90++0x03 line.long 0x00 "DSGCR,DDR System General Configuration Register" bitfld.long 0x00 27. " RDBICLSEL ,Select RDBI CL calculation" "Default,RDBICL" bitfld.long 0x00 24.--26. " RDBICL ,RDBI CL adjust value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " PHYZUEN ,PHY impedance update enable" "Disabled,Enabled" bitfld.long 0x00 21. " RSTOE ,SDRAM reset output enable" "Disabled,Enabled" newline bitfld.long 0x00 19.--20. " SDRMODE ,Single data rate mode" "0,1,2,3" bitfld.long 0x00 17. " ATOAE ,ATO analog test enable" "Disabled,Enabled" bitfld.long 0x00 16. " DTOOE ,DTO output enable" "Disabled,Enabled" bitfld.long 0x00 15. " DTOIOM ,DTO I/O mode" "Disabled,Enabled" newline bitfld.long 0x00 14. " DTOPDR ,DTO power down receiver" "Disabled,Enabled" bitfld.long 0x00 12. " DTOODT ,DTO on-die termination" "Disabled,Enabled" bitfld.long 0x00 6.--11. " PUAD ,PHY update acknowledge delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 5. " CUAEN ,Controller update acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " MSTRVER ,Controller impedance update enable" "Disabled,Enabled" bitfld.long 0x00 2. " CTLZUEN ,Controller impedance update enable" "Disabled,Enabled" bitfld.long 0x00 1. " MREN ,Master request enable" "Disabled,Enabled" bitfld.long 0x00 0. " PUREN ,PHY update request enable" "Disabled,Enabled" group.long 0x98++0x03 line.long 0x00 "ODTCR,ODT Configuration Register" bitfld.long 0x00 16. " WRODT ,Write ODT" "0,1" bitfld.long 0x00 0. " RDODT ,Read ODT" "0,1" group.long 0xA0++0x03 line.long 0x00 "AACR,Anti-Aging Control Register" bitfld.long 0x00 31. " AAOENC ,Anti-aging PAD output enable control" "Disabled,Enabled" bitfld.long 0x00 30. " AAENC ,Anti-aging enable control" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " AATR ,Anti-aging toggle rate" group.long 0xC0++0x07 line.long 0x00 "GPR0,General Purpose Register 0" line.long 0x04 "GPR1,General Purpose Register 1" group.long 0x100++0x03 line.long 0x00 "DCR,DRAM Configuration Register" bitfld.long 0x00 31. " GEARDN ,DDR4 gear down timing" "0,1" bitfld.long 0x00 30. " UBG ,Un-used bank group" "0,1" bitfld.long 0x00 29. " UDIMM ,Un-buffered DIMM address mirroring" "Disabled,Enabled" bitfld.long 0x00 28. " DDR2T ,DDR 2T timing" "0,1" newline bitfld.long 0x00 27. " NOSRA ,No simultaneous rank access" "No,Yes" hexmask.long.word 0x00 10.--17. 1. " BYTEMASK ,Byte mask" bitfld.long 0x00 8.--9. " DDRTYPE ,DDR type" "0,1,2,3" bitfld.long 0x00 7. " MPRDQ ,Multi-purpose register DQ" "0,1" newline bitfld.long 0x00 4.--6. " PDQ ,Primary DQ" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " DDR8BNK ,DDR 8-bank" "Disabled,Enabled" bitfld.long 0x00 0.--2. " DDRMD ,DDR mode" "0,1,2,3,4,5,6,7" group.long 0x110++0x1B line.long 0x00 "DTPR0,DRAM Timing Parameters Register 0" bitfld.long 0x00 24.--28. " TRRD ,Activate to activate command delay on different banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 16.--22. 1. " TRAS ,Activate to precharge command delay" hexmask.long.byte 0x00 8.--14. 1. " TRP ,Precharge command period" bitfld.long 0x00 0.--4. " TRTP ,Internal read to precharge command delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DTPR1,DRAM Timing Parameters Register 1" hexmask.long.byte 0x04 24.--30. 1. " TWLMRD ,Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge" hexmask.long.byte 0x04 16.--22. 1. " TFAW ,4-bank activate period" bitfld.long 0x04 8.--10. " TMOD ,Load mode update delay" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--4. " TMRD ,Load mode cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "DTPR2,DRAM Timing Parameters Register 2" bitfld.long 0x08 28. " TRTW ,Read to write command delay" "0,1" bitfld.long 0x08 24. " TRTODT ,Read to ODT delay" "0,1" bitfld.long 0x08 16.--19. " TCKE ,CKE minimum pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x08 0.--9. 1. " TXS ,Self refresh exit delay" line.long 0x0C "DTPR3,DRAM Timing Parameters Register 3" bitfld.long 0x0C 29.--31. " TOFDX ,ODT turn-off delay extension" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 26.--28. " TCCD ,Read to read and write to write command delay" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 16.--25. 1. " TDLLK ,DLL locking time" bitfld.long 0x0C 8.--11. " TDQSCKMAX ,Maximum DQS output access time from CK/CK#" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 0.--2. " TDQSCK ,DQS output access time from CK/CK#" "0,1,2,3,4,5,6,7" line.long 0x10 "DTPR4,DRAM Timing Parameters Register 4" bitfld.long 0x10 28.--29. " TAOND_TAOFD ,ODT turn-on/turn-off delays" "0,1,2,3" hexmask.long.word 0x10 16.--25. 1. " TRFC ,Refresh-to-refresh" bitfld.long 0x10 8.--13. " TWLO ,Write leveling output delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 0.--4. " TXP ,Power down exit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "DTPR5,DRAM Timing Parameters Register 5" hexmask.long.byte 0x14 16.--23. 1. " TRC ,Activate to activate command delay same bank" hexmask.long.byte 0x14 8.--14. 1. " TRCD ,Activate to read or write delay" bitfld.long 0x14 0.--4. " TWTR ,Internal write to read command delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "DTPR6,DRAM Timing Parameters Register 6" bitfld.long 0x18 31. " PUBWLEN ,PUB write latency enable" "Disabled,Enabled" bitfld.long 0x18 30. " PUBRLEN ,PUB read latency enable" "Disabled,Enabled" bitfld.long 0x18 8.--13. " PUBWL ,Write latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " PUBRL ,Read latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x140++0x0B line.long 0x00 "RDIMMGCR0,RDIMM General Configuration Register 0" bitfld.long 0x00 30. " QCSEN ,RDMIMM quad CS enable" "Disabled,Enabled" bitfld.long 0x00 27. " RDIMMIOM ,RDIMM outputs I/O mode" "Disabled,Enabled" bitfld.long 0x00 23. " ERROUTOE ,ERROUT# output enable" "Disabled,Enabled" bitfld.long 0x00 22. " ERROUTIOM ,ERROUT# I/O mode" "Disabled,Enabled" newline bitfld.long 0x00 21. " ERROUTPDR ,ERROUT# power down receiver" "No,Yes" bitfld.long 0x00 19. " ERROUTODT ,ERROUT# on-die termination" "Disabled,Enabled" bitfld.long 0x00 18. " LRDIMM ,Load reduced DIMM" "Disabled,Enabled" bitfld.long 0x00 17. " PARINIOM ,PAR_IN I/O mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " RNKMRREN ,Rank mirror enable" "Disabled,Enabled" bitfld.long 0x00 2. " SOPERR ,Stop on parity error" "Disabled,Enabled" bitfld.long 0x00 1. " ERRNOREG ,Parity error no registering" "No,Yes" bitfld.long 0x00 0. " RDIMM ,Registered DIMM" "Not registered,Registered" line.long 0x04 "RDIMMGCR1,RDIMM General Configuration Register 1" bitfld.long 0x04 28. " A17BID ,Address [17] B-side inversion disable" "No,Yes" bitfld.long 0x04 24.--26. " TBCMRD_L2 ,Command word to command word programming delay" "0,1,2,3,4,5,6,7" bitfld.long 0x04 20.--22. " TBCMRD_L ,Command word to command word programming delay" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " TBCMRD ,Command word to command word programming delay" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x04 0.--13. 1. " TBCSTAB ,Stabilization time" line.long 0x08 "RDIMMGCR2,RDIMM General Configuration Register 2" group.long 0x150++0x13 line.long 0x00 "RDIMMCR0,RDIMM Control Register 0" bitfld.long 0x00 28.--31. " RC7 ,DDR3 control word 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " RC5 ,DDR3 CK driver characteristics control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " RC4 ,DDR3 control signals driver characteristics control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " RC3 ,DDR3 control signals driver characteristics control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " RC2 ,DDR3 timing control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " RC1 ,DDR3 clock driver enable control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RC0 ,DDR3 global features control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "RDIMMCR1,RDIMM Control Register 1" bitfld.long 0x04 28.--31. " RC15 ,Control word 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 12.--15. " RC11 ,DDR3 operation voltage VDD control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " RC10 ,DDR3 RDIMM operating speed control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " RC9 ,DDR3 power saving settings control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " RC8 ,DDR3 additional input bus termination setting control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "RDIMMCR2,RDIMM Control Register 2" hexmask.long.byte 0x08 24.--31. 1. " RC4X ,Control word RC4X" hexmask.long.byte 0x08 16.--23. 1. " RC3X ,Control word RC3X" hexmask.long.byte 0x08 8.--15. 1. " RC2X ,Control word RC2X" hexmask.long.byte 0x08 0.--7. 1. " RC1X ,Control word RC1X" line.long 0x0C "RDIMMCR3,RDIMM Control Register 3" hexmask.long.byte 0x0C 24.--31. 1. " RC8X ,Control word RC8X" hexmask.long.byte 0x0C 16.--23. 1. " RC7X ,Control word RC7X" hexmask.long.byte 0x0C 8.--15. 1. " RC6X ,Control word RC6X" hexmask.long.byte 0x0C 0.--7. 1. " RC5X ,Control word RC5X" line.long 0x10 "RDIMMCR4,RDIMM Control Register 4" hexmask.long.byte 0x10 16.--23. 1. " RCBX ,Control word RC11X" hexmask.long.byte 0x10 8.--15. 1. " RCAX ,Control word RC10X" hexmask.long.byte 0x10 0.--7. 1. " RC9X ,Control word RC9X" group.long 0x168++0x07 line.long 0x00 "SCHCR0,Scheduler Command Register 0" hexmask.long.word 0x00 16.--24. 1. " SCHDQV ,Scheduler command DQ value" bitfld.long 0x00 8.--11. " SP_CMD ,Special command codes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CMD ,Specifies the command to be issued" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " SCHTRIG ,Mode register command trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SCHCR1,Scheduler Command Register 1" bitfld.long 0x04 28.--31. " SCRNK ,Scheduler rank address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x04 8.--27. 0x01 " SCADDR ,Scheduler command address specifies the value to be driven on the address bus" bitfld.long 0x04 6.--7. " SCBG ,Scheduler command bank group" "0,1,2,3" bitfld.long 0x04 4.--5. " SCBK ,Scheduler command bank address" "0,1,2,3" newline bitfld.long 0x04 2. " ALLRANK ,All ranks enabled" "Disabled,Enabled" group.long 0x180++0x0F line.long 0x00 "MR0,LPDDR4 Mode Register 0" bitfld.long 0x00 7. " CATR ,CA terminating rank" "0,1" bitfld.long 0x00 3.--4. " RZQI ,Built-in self-test for RZQ" "0,1,2,3" line.long 0x04 "MR1,LPDDR4 Mode Register 1" bitfld.long 0x04 7. " RDPST ,Read postamble length" "0,1" bitfld.long 0x04 4.--6. " NWR ,Write-recovery for auto-precharge command" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3. " RDPRE ,Read preamble length" "0,1" bitfld.long 0x04 2. " WRPRE ,Write preamble length" "0,1" newline bitfld.long 0x04 0.--1. " BL ,Burst length" "0,1,2,3" line.long 0x08 "MR2,LPDDR4 Mode Register 2" bitfld.long 0x08 7. " WRL ,Write leveling" "Disabled,Enabled" bitfld.long 0x08 6. " WLS ,Write latency set" "0,1" bitfld.long 0x08 3.--5. " WL ,Write latency" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0.--2. " RL ,Read latency" "0,1,2,3,4,5,6,7" line.long 0x0C "MR3,LPDDR4 Mode Register 3" bitfld.long 0x0C 7. " DBIWR ,DBI-write enable" "Disabled,Enabled" bitfld.long 0x0C 6. " DBIRD ,DBI-read enable" "Disabled,Enabled" bitfld.long 0x0C 3.--5. " PDDS ,Pull-down drive strength" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 1. " WRPST ,Write postamble length" "0,1" newline bitfld.long 0x0C 0. " PUCAL ,Pull-up calibration point" "0,1" group.long 0x1AC++0x0F line.long 0x00 "MR11,LPDDR4 Mode Register 11" bitfld.long 0x00 4.--6. " CAODT ,CA bus receiver on-die-termination" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " DQODT ,DQ bus receiver on-die-termination" "0,1,2,3,4,5,6,7" line.long 0x04 "MR12,LPDDR4 Mode Register 12" bitfld.long 0x04 6. " VR_CA ,VREF_CA range select" "0,1" bitfld.long 0x04 0.--5. " VREF_CA ,Controls the VREF_CA levels for frequency-set-point[1:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "MR13,LPDDR4 Mode Register 13" bitfld.long 0x08 7. " FSPOP ,Frequency set point operation mode" "0,1" bitfld.long 0x08 6. " FSPWR ,Frequency set point write enable" "Disabled,Enabled" bitfld.long 0x08 5. " DMD ,Data mask enable" "Disabled,Enabled" bitfld.long 0x08 4. " RRO ,Refresh rate option" "0,1" newline bitfld.long 0x08 3. " VRCG ,VREF current generator" "0,1" bitfld.long 0x08 2. " VRO ,VREF output" "0,1" bitfld.long 0x08 1. " RPT ,Read preamble training mode" "Disabled,Enabled" bitfld.long 0x08 0. " CBT ,Command bus training" "Disabled,Enabled" line.long 0x0C "MR14,LPDDR4 Mode Register 14" bitfld.long 0x0C 6. " VR_DQ ,VREFDQ range selects" "0,1" group.long 0x1D8++0x03 line.long 0x00 "MR22,LPDDR4 Mode Register 22" bitfld.long 0x00 5. " ODTD_CA ,CA ODT termination disable" "No,Yes" bitfld.long 0x00 4. " ODTE_CS ,ODT CS override" "No override,Override" bitfld.long 0x00 3. " ODTE_CK ,ODT CK override" "No override,Override" bitfld.long 0x00 0.--2. " CODT ,Controller ODT value for VOH calibration" "0,1,2,3,4,5,6,7" group.long 0x200++0x13 line.long 0x00 "DTCR0,Data Training Configuration Register 0" bitfld.long 0x00 28.--31. " RFSHDT ,Refresh during training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--25. " DTDRS ,Data training debug rank select" "0,1,2,3" bitfld.long 0x00 23. " DTEXG ,Data training with early/extended gate" "Disabled,Enabled" bitfld.long 0x00 22. " DTEXD ,Data training extended write DQS" "Disabled,Enabled" newline bitfld.long 0x00 21. " DTDSTP ,Data training debug step" "0,1" bitfld.long 0x00 20. " DTDEN ,Data training debug enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " DTDBS ,Data training debug byte select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " DTRDBITR ,Data training read DBI deskewing configuration" "0,1,2,3" newline bitfld.long 0x00 13. " DTBDC ,Data training bit deskew centering" "0,1" bitfld.long 0x00 12. " DTWBDDM ,Data training write bit deskew data mask" "Not masked,Masked" bitfld.long 0x00 8.--11. " RFSHEN ,Refreshes issued during entry to training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " DTCMPD ,Data training compare data" "0,1" newline bitfld.long 0x00 6. " DTMPR ,Data training using MPR" "Disabled,Enabled" bitfld.long 0x00 4. " INCWEYE ,WEYE training using MPC FIFO commands" "0,1" bitfld.long 0x00 0.--3. " DTRPTN ,Data training repeat number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DTCR1,Data Training Configuration Register 1" bitfld.long 0x04 16. " RANKEN ,Rank enable" "Disabled,Enabled" bitfld.long 0x04 12.--13. " DTRANK ,Data training rank" "0,1,2,3" bitfld.long 0x04 8.--10. " RDLVLGDIFF ,Read leveling gate sampling difference" "0,1,2,3,4,5,6,7" bitfld.long 0x04 4.--6. " RDLVLGS ,Read leveling gate shift" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 2. " RDPRMVL_TRN ,Read preamble training enable" "Disabled,Enabled" bitfld.long 0x04 1. " RDLVLEN ,Read leveling enable" "Disabled,Enabled" bitfld.long 0x04 0. " BSTEN ,Basic gate training enable" "Disabled,Enabled" line.long 0x08 "DTAR0,Data Training Address Register 0" bitfld.long 0x08 28.--29. " MPRLOC ,Multi-Purpose register MPR location" "0,1,2,3" hexmask.long.byte 0x08 24.--27. 0x01 " DTBGBK1 ,Data training bank group and bank address" hexmask.long.byte 0x08 20.--23. 0x10 " DTBGBK0 ,Data training bank group and bank address" hexmask.long.tbyte 0x08 0.--17. 0x01 " DTROW ,Data training row address" line.long 0x0C "DTAR1,Data Training Address Register 1" hexmask.long.word 0x0C 16.--24. 0x01 " DTCOL1 ,Data training column address" hexmask.long.word 0x0C 0.--8. 0x01 " DTCOL0 ,Data training column address" line.long 0x10 "DTAR2,Data Training Address Register 2" hexmask.long.word 0x10 16.--24. 0x01 " DTCOL3 ,Data training column address" hexmask.long.word 0x10 0.--8. 0x01 " DTCOL2 ,Data training column address" group.long 0x218++0x07 line.long 0x00 "DTDR0,Data Training Data Register 0" hexmask.long.byte 0x00 24.--31. 1. " DTBYTE3 ,Data training data" hexmask.long.byte 0x00 16.--23. 1. " DTBYTE2 ,Data training data" hexmask.long.byte 0x00 8.--15. 1. " DTBYTE1 ,Data training data" hexmask.long.byte 0x00 0.--7. 1. " DTBYTE0 ,Data training data" line.long 0x04 "DTDR1,Data Training Data Register 1" hexmask.long.byte 0x04 24.--31. 1. " DTBYTE7 ,Data training data" hexmask.long.byte 0x04 16.--23. 1. " DTBYTE6 ,Data training data" hexmask.long.byte 0x04 8.--15. 1. " DTBYTE5 ,Data training data" hexmask.long.byte 0x04 0.--7. 1. " DTBYTE4 ,Data training data" rgroup.long 0x230++0x0F line.long 0x00 "DTEDR0,Data Training Eye Data Register 0" hexmask.long.byte 0x00 24.--31. 1. " WDQMBX ,Data training write BDL shift maximum" bitfld.long 0x00 18.--23. " WDQBMN ,Data training write BDL shift minimum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 9.--17. 1. " WDQLMX ,Data training WDQ LCDL maximum" hexmask.long.word 0x00 0.--8. 1. " WDQLMN ,Data training WDQ LCDL minimum" line.long 0x04 "DTEDR1,Data Training Eye Data Register 1" hexmask.long.byte 0x04 24.--31. 1. " RDQSBMX ,Data training read BDL shift maximum" bitfld.long 0x04 18.--23. " RDQSBMN ,Data training read BDL shift minimum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x04 9.--17. 1. " RDQSLMX ,Data training RDQS LCDL maximum" hexmask.long.word 0x04 0.--8. 1. " RDQSLMN ,Data training RDQS LCDL minimum" line.long 0x08 "DTEDR2,Data Training Eye Data Register 2" hexmask.long.byte 0x08 24.--31. 1. " RDQSNBMX ,Data training read BDL shift maximum" bitfld.long 0x08 18.--23. " RDQSNBMN ,Data training read BDL shift minimum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x08 9.--17. 1. " RDQSNLMX ,Data training RDQSN LCDL maximum" hexmask.long.word 0x08 0.--8. 1. " RDQSNLMN ,Data training RDQSN LCDL minimum" line.long 0x0C "VTDR,VREF Training Data Register" hexmask.long.byte 0x0C 24.--30. 1. " HVREFMX ,DRAM DQ VREF maximum" hexmask.long.byte 0x0C 16.--22. 1. " HVREFMN ,DRAM DQ VREF minimum" bitfld.long 0x0C 8.--13. " DVREFMX ,DRAM DQ VREF maximum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " DVREFMN ,DRAM DQ VREF minimum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x240++0x0B line.long 0x00 "CATR0,CA Training Register 0" bitfld.long 0x00 16.--20. " CACD ,Minimum time between two consecutive CA calibration command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " CAADR ,Minimum wait time before sampling the CA response after calibration command has been sent to the memory" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " CA1BYTE1 ,CA_1 response byte lane 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CA1BYTE0 ,CA_1 response byte lane 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "CATR1,CA Training Register 1" bitfld.long 0x04 24.--27. " CA0BYTE1 ,CA_0 response byte lane 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 20.--23. " CA0BYTE0 ,CA_0 response byte lane 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " CAMRZ ,Minimum time for DRAM DQ going tristate after MRW CA exit calibration command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 12.--15. " CACKEH ,Minimum time for CKE high after last CA calibration response is driven by memory" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " CACKEL ,Minimum time for CKE going low after CA calibration mode is programmed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " CAEXT ,Minimum time for CA calibration exit command after CKE is high" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CAENT ,Minimum time for first CA calibration command after CKE is low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "PGCR8,PHY General Configuration Register 8" bitfld.long 0x08 28.--31. " CF ,Counter cycles factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x08 20.--27. 1. " CM ,Counter cycle multiplier" bitfld.long 0x08 16. " RANKEN ,Rank enable" "Disabled,Enabled" bitfld.long 0x08 15. " MODE ,Self incremental DQS2DQ training" "Disabled,Enabled" newline bitfld.long 0x08 14. " EN ,Incremental DQS2DQ training" "Disabled,Enabled" bitfld.long 0x08 8. " BSWAPMSB[8] ,PHY 8 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" bitfld.long 0x08 7. " [7] ,PHY 7 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" bitfld.long 0x08 6. " [6] ,PHY 6 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" newline bitfld.long 0x08 5. " [5] ,PHY 5 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" bitfld.long 0x08 4. " [4] ,PHY 4 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" bitfld.long 0x08 3. " [3] ,PHY 3 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" bitfld.long 0x08 2. " [2] ,PHY 2 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" newline bitfld.long 0x08 1. " [1] ,PHY 1 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" bitfld.long 0x08 0. " [0] ,PHY 0 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" group.long 0x250++0x0B line.long 0x00 "DQSDR0,DQS Drift Register 0" bitfld.long 0x00 28.--31. " DFTDLY ,Number of delay taps by which the DQS gate LCDL will be updated when DQS drift is detected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. " DFTZQUP ,Drift impedance update" "Not updated,Updated" bitfld.long 0x00 26. " DFTDDLUP ,Drift DDL update" "Not updated,Updated" bitfld.long 0x00 20.--21. " DFTRDSPC ,Drift read spacing" "0,1,2,3" newline bitfld.long 0x00 16.--19. " DFTB2BRD ,Drift back-to-back reads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DFTIDLRD ,Drift idle reads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DFTGPULSE ,Gate pulse enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--3. " DFTUPMODE ,DQS drift update mode" "0,1,2,3" newline bitfld.long 0x00 1. " DFTDTMODE ,DQS drift detection mode" "0,1" bitfld.long 0x00 0. " DFTDTEN ,DQS drift detection enable" "Disabled,Enabled" line.long 0x04 "DQSDR1,DQS Drift Register 1" bitfld.long 0x04 29.--31. " DFTUPDACKF ,Drift DFU update request ACK to DQS drift FSM issuing IDLE read cycles factor" "0,1,2,3,4,5,6,7" bitfld.long 0x04 24.--28. " DFTUPDACKC ,Drift DFI update request ACK to DQS drift FSM issuing IDLE read cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 20.--23. " DFTRDB2BF ,Drift Back-to-Back read cycles factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " DFTRDIDLF ,Drift idle read cycles factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x04 8.--15. 1. " DFTRDB2BC ,Drift Back-to-Back read cycles" hexmask.long.byte 0x04 0.--7. 1. " DFTRDIDLC ,Drift idle read cycles" line.long 0x08 "DQSDR2,DQS Drift Register 2" hexmask.long.byte 0x08 16.--23. 1. " DFTTHRSH ,Drift threshold" hexmask.long.word 0x08 0.--15. 1. " DFTMNTPRD ,Drift monitor period" group.long 0x300++0x17 line.long 0x00 "DCUAR,DCU Address Register" hexmask.long.byte 0x00 16.--19. 0x01 " CSADDR_R ,Cache slice address" hexmask.long.byte 0x00 12.--15. 0x10 " CWADDR_R ,Cache word address" bitfld.long 0x00 11. " ATYPE ,Access type" "0,1" bitfld.long 0x00 10. " INCA ,Increment address" "0,1" newline bitfld.long 0x00 8.--9. " CSEL ,Cache select" "0,1,2,3" hexmask.long.byte 0x00 4.--7. 0x10 " CSADDR_W ,Cache slice address" hexmask.long.byte 0x00 0.--3. 0x01 " CWADDR_W ,Cache word address" line.long 0x04 "DCUDR,DCU Data Register" line.long 0x08 "DCURR,DCU Run Register" bitfld.long 0x08 23. " XCEN ,Expected compare enable" "Disabled,Enabled" bitfld.long 0x08 22. " RCEN ,Read capture enable" "Disabled,Enabled" bitfld.long 0x08 21. " SCOF ,Stop capture on full" "0,1" bitfld.long 0x08 20. " SONF ,Stop on n-th fail" "0,1" newline hexmask.long.byte 0x08 12.--19. 1. " NFAIL ,Number of failures" hexmask.long.byte 0x08 8.--11. 0x01 " EADDR ,End address" hexmask.long.byte 0x08 4.--7. 0x10 " SADDR ,Start address" bitfld.long 0x08 0.--3. " DINST ,DCU instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "DCULR,DCU Loop Register" hexmask.long.byte 0x0C 28.--31. 0x10 " XLEADDR ,Expected data loop end address" bitfld.long 0x0C 17. " IDA ,Increment DRAM address" "0,1" bitfld.long 0x0C 16. " LINF ,Loop infinite" "0,1" hexmask.long.byte 0x0C 8.--15. 1. " LCNT ,Loop count" newline hexmask.long.byte 0x0C 4.--7. 0x10 " LEADDR ,Loop end address" hexmask.long.byte 0x0C 0.--3. 0x01 " LSADDR ,Loop start address" line.long 0x10 "DCUGCR,DCU General Configuration Register" hexmask.long.word 0x10 0.--15. 1. " RCSW ,Read capture start word" line.long 0x14 "DCUTPR,DCU Timing Parameters Register" hexmask.long.word 0x14 16.--31. 1. " TDCUT2 ,DCU generic timing parameter 2" hexmask.long.byte 0x14 8.--15. 1. " TDCUT1 ,DCU generic timing parameter 1" hexmask.long.byte 0x14 0.--7. 1. " TDCUT0 ,DCU generic timing parameter 0" rgroup.long 0x318++0x07 line.long 0x00 "DCUSR0,DCU Status Register 0" bitfld.long 0x00 2. " CFULL ,Capture full" "Not full,Full" bitfld.long 0x00 1. " CFAIL ,Capture fail" "Not failed,Failed" bitfld.long 0x00 0. " RDONE ,Run done" "Not done,Done" line.long 0x04 "DCUSR1,DCU Status Register 1" hexmask.long.byte 0x04 24.--31. 1. " LPCNT ,Loop count" hexmask.long.byte 0x04 16.--23. 1. " FLCNT ,Fail count" hexmask.long.word 0x04 0.--15. 1. " RDCNT ,Read count" group.long 0x400++0x2F line.long 0x00 "BISTRR,BIST Run Register" bitfld.long 0x00 29. " BPRBST ,BIST PRBS type" "0,1" bitfld.long 0x00 28. " BSOMA ,BIST stop on maximum address" "Disabled,Enabled" bitfld.long 0x00 26.--27. " BACDPAT ,BIST AC data pattern" "0,1,2,3" bitfld.long 0x00 25. " BCCSEL ,BIST clock cycle select" "0,1" newline bitfld.long 0x00 23.--24. " BCKSEL ,BIST CK select" "0,1,2,3" bitfld.long 0x00 19.--22. " BDXSEL ,BIST DATX8 select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 17.--18. " BDXDPAT ,BIST data pattern" "0,1,2,3" bitfld.long 0x00 16. " BDMEN ,BIST data mask enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " BACEN ,BIST AC enable" "Disabled,Enabled" bitfld.long 0x00 14. " BDXEN ,BIST DATX8 enable" "Disabled,Enabled" bitfld.long 0x00 13. " BSONF ,BIST stop on nth fail" "Disabled,Enabled" hexmask.long.word 0x00 5.--12. 1. " NFAIL ,Number of failures" newline bitfld.long 0x00 4. " BINF ,BIST infinite run" "0,1" bitfld.long 0x00 3. " BMODE ,BIST mode" "0,1" bitfld.long 0x00 0.--2. " BINST ,BIST instruction" "0,1,2,3,4,5,6,7" line.long 0x04 "BISTWCR,BIST Word Count Register" hexmask.long.word 0x04 16.--31. 1. " BACWCNT ,BIST AC word count" hexmask.long.word 0x04 0.--15. 1. " BDXWCNT ,BIST DX word count" newline line.long 0x08 "BISTMSKR0,BIST Mask Register 0" bitfld.long 0x08 20. " CSMSK ,Mask bit for CS_N bit 0" "0,1" bitfld.long 0x08 19. " ACTMSK ,Mask bit for the RAS" "0,1" newline bitfld.long 0x08 17. " AMSK[17:0] ,Mask bit for address bit 17" "0,1" bitfld.long 0x08 16. ",Mask bit for address bit 16" "0,1" bitfld.long 0x08 15. ",Mask bit for address bit 15" "0,1" bitfld.long 0x08 14. ",Mask bit for address bit 14" "0,1" bitfld.long 0x08 13. ",Mask bit for address bit 13" "0,1" bitfld.long 0x08 12. ",Mask bit for address bit 12" "0,1" bitfld.long 0x08 11. ",Mask bit for address bit 11" "0,1" bitfld.long 0x08 10. ",Mask bit for address bit 10" "0,1" bitfld.long 0x08 9. ",Mask bit for address bit 9" "0,1" bitfld.long 0x08 8. ",Mask bit for address bit 8" "0,1" bitfld.long 0x08 7. ",Mask bit for address bit 7" "0,1" bitfld.long 0x08 6. ",Mask bit for address bit 6" "0,1" bitfld.long 0x08 5. ",Mask bit for address bit 5" "0,1" bitfld.long 0x08 4. ",Mask bit for address bit 4" "0,1" bitfld.long 0x08 3. ",Mask bit for address bit 3" "0,1" bitfld.long 0x08 2. ",Mask bit for address bit 2" "0,1" bitfld.long 0x08 1. ",Mask bit for address bit 1" "0,1" bitfld.long 0x08 0. ",Mask bit for address bit 0" "0,1" line.long 0x0C "BISTMSKR1,BIST Mask Register 1" bitfld.long 0x0C 31. " DMMSK[3] ,Mask bit for the data mask DM bit 3" "0,1" bitfld.long 0x0C 30. " [2] ,Mask bit for the data mask DM bit 2" "0,1" bitfld.long 0x0C 29. " [1] ,Mask bit for the data mask DM bit 1" "0,1" bitfld.long 0x0C 28. " [0] ,Mask bit for the data mask DM bit 0" "0,1" newline bitfld.long 0x0C 27. " PARINMSK ,Mask bit for the PAR_IN" "0,1" bitfld.long 0x0C 24. " CIDMSK ,Mask bits for chip IP bits" "0,1" bitfld.long 0x0C 16. " ODTMSK ,Mask bit for ODT bit" "0,1" bitfld.long 0x0C 8. " CKEMSK ,Mask bit for CKE bit" "0,1" newline bitfld.long 0x0C 7. " BAMSK[3] ,Mask bit for bank address bit 3" "0,1" bitfld.long 0x0C 6. " [2] ,Mask bit for bank address bit 2" "0,1" bitfld.long 0x0C 5. " [1] ,Mask bit for bank address bit 1" "0,1" bitfld.long 0x0C 4. " [0] ,Mask bit for bank address bit 0" "0,1" line.long 0x10 "BISTMSKR2,BIST Mask Register 2" newline line.long 0x14 "BISTLSR,BIST LFSR Seed Register" line.long 0x18 "BISTAR0,BIST Address Register 0" hexmask.long.byte 0x18 28.--31. 0x10 " BBANK ,BIST bank address" hexmask.long.word 0x18 0.--11. 0x01 " BCOL ,BIST column address" line.long 0x1C "BISTAR1,BIST Address Register 1" bitfld.long 0x1C 16.--19. " BMRANK ,BIST maximum rank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x1C 4.--15. 1. " BAINC ,BIST address increment" bitfld.long 0x1C 0.--3. " BRANK ,BIST rank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x20 "BISTAR2,BIST Address Register 2" hexmask.long.byte 0x20 28.--31. 0x10 " BMBANK ,BIST maximum bank address" hexmask.long.word 0x20 0.--11. 0x01 " BMCOL ,BIST maximum column address" line.long 0x24 "BISTAR3,BIST Address Register 3" hexmask.long.tbyte 0x24 0.--17. 0x01 " BROW ,BIST row address" line.long 0x28 "BISTAR4,BIST Address Register 4" hexmask.long.tbyte 0x28 0.--17. 0x01 " BMROW ,BIST maximum row address" line.long 0x2C "BISTUDPR,BIST User Data Pattern Register" hexmask.long.word 0x2C 16.--31. 1. " BUDP1 ,BIST user data pattern 1" hexmask.long.word 0x2C 0.--15. 1. " BUDP0 ,BIST user data pattern 0" rgroup.long 0x430++0x33 line.long 0x00 "BISTGSR,BIST General Status Register" bitfld.long 0x00 28.--29. " RASBER ,RAS_n/ACT_n bit error" "0,1,2,3" hexmask.long.byte 0x00 20.--27. 1. " DMBER ,DM bit error" hexmask.long.word 0x00 2.--10. 1. " BDXERR ,BIST data error" bitfld.long 0x00 1. " BACERR ,BIST address/command error" "No error,Error" newline bitfld.long 0x00 0. " BDONE ,BIST done" "Not done,Done" line.long 0x04 "BISTWER0,BIST Word Error Register 0" hexmask.long.tbyte 0x04 0.--17. 1. " ACWER ,Address/command word error" line.long 0x08 "BISTWER1,BIST Word Error Register 1" hexmask.long.word 0x08 0.--15. 1. " DXWER ,Byte word error" line.long 0x0C "BISTBER0,BIST Bit Error Register 0" line.long 0x10 "BISTBER1,BIST Bit Error Register 1" bitfld.long 0x10 8.--9. " CSBER ,CS_N bit error" "0,1,2,3" hexmask.long.byte 0x10 0.--7. 1. " BABER ,Bank address bit error" line.long 0x14 "BISTBER2,BIST Bit Error Register 2" line.long 0x18 "BISTBER3,BIST Bit Error Register 3" line.long 0x1C "BISTBER4,BIST Bit Error Register 4" bitfld.long 0x1C 8.--9. " CIDBER ,Chip ID bit error" "0,1,2,3" bitfld.long 0x1C 0.--3. " ABER ,Address bit error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x20 "BISTWCSR,BIST Word Count Status Register" hexmask.long.word 0x20 16.--31. 1. " DXWCNT ,Byte word count" hexmask.long.word 0x20 0.--15. 1. " ACWCNT ,Address/command word count" line.long 0x24 "BISTFWR0,BIST Fail Word Register 0" bitfld.long 0x24 20. " CSWEBS ,Bit status during a word error for CS# bits" "No error,Error" bitfld.long 0x24 18. " ACTWEBS ,Bit status during a word error for the RAS" "No error,Error" hexmask.long.tbyte 0x24 0.--17. 1. " AWEBS ,Bit status during a word error for address bits" line.long 0x28 "BISTFWR1,BIST Fail Word Register 1" bitfld.long 0x28 31. " DMWEBS[3] ,Bit status during a word error for the data mask DM bit 3" "No error,Error" bitfld.long 0x28 30. " [2] ,Bit status during a word error for the data mask DM bit 2" "No error,Error" bitfld.long 0x28 29. " [1] ,Bit status during a word error for the data mask DM bit 1" "No error,Error" bitfld.long 0x28 28. " [0] ,Bit status during a word error for the data mask DM bit 0" "No error,Error" newline bitfld.long 0x28 20. " CIDWEBS ,Bit status during a word error for chip ID bits" "No error,Error" bitfld.long 0x28 19. " BAWEBS[3] ,Bit status during a word error for the bank address bit 3" "No error,Error" bitfld.long 0x28 18. " [2] ,Bit status during a word error for the bank address bit 2" "No error,Error" bitfld.long 0x28 17. " [1] ,Bit status during a word error for the bank address bit 1" "No error,Error" newline bitfld.long 0x28 16. " [0] ,Bit status during a word error for the bank address bit 0" "No error,Error" bitfld.long 0x28 8. " ODTWEBS ,Bit status during a word error for the ODT bits" "No error,Error" bitfld.long 0x28 0. " CKEWEBS ,Bit status during a word error for the CKE bits" "No error,Error" line.long 0x2C "BISTFWR2,BIST Fail Word Register 2" line.long 0x30 "BISTBER5,BIST Bit Error Register 5" bitfld.long 0x30 16.--17. " ODTBER ,ODT bit error" "0,1,2,3" bitfld.long 0x30 0.--1. " CKEBER ,CKE bit error" "0,1,2,3" group.long 0x4DC++0x03 line.long 0x00 "RANKIDR,Rank ID Register" bitfld.long 0x00 16.--19. " RANKRID ,Rank read ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RANKWID ,Rank write ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4E8++0x03 line.long 0x00 "RIOCR2,Rank I/O Configuration Register 2" bitfld.long 0x00 24.--25. " COEMODE ,SDRAM C output enable (OE) mode selection" "0,1,2,3" bitfld.long 0x00 0.--1. " CSOEMODE ,SDRAM CS_n output enable (OE) mode selection" "0,1,2,3" group.long 0x4F0++0x07 line.long 0x00 "RIOCR4,Rank I/O Configuration Register 4" bitfld.long 0x00 0.--1. " CKEOEMODE ,SDRAM CKE output enable (OE) mode selection" "0,1,2,3" line.long 0x04 "RIOCR5,Rank I/O Configuration Register 5" bitfld.long 0x04 0.--1. " ODTOEMODE ,SDRAM On-die termination output enable (OE) mode selection" "0,1,2,3" newline group.long 0x500++0x17 line.long 0x00 "ACIOCR0,AC I/O Configuration Register 0" bitfld.long 0x00 30.--31. " ACSR ,Address/command slew rate (D3F I/O only)" "0,1,2,3" bitfld.long 0x00 29. " RSTIOM ,SDRAM reset I/O mode" "0,1" bitfld.long 0x00 28. " RSTPDR ,SDRAM reset power down receiver" "0,1" bitfld.long 0x00 26. " RSTODT ,SDRAM reset on-die termination" "0,1" newline hexmask.long.byte 0x00 16.--23. 1. " ESR ,Decoupling capacitance ESR control in D5M I/O ring" bitfld.long 0x00 10.--11. " ACPNUMSEL ,Address/command custom pin mapping configuration" "0,1,2,3" bitfld.long 0x00 6.--9. " CKDCC ,CK duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--5. " ACPDRMODE ,AC power down receiver mode" "0,1,2,3" newline bitfld.long 0x00 2.--3. " ACODTMODE ,AC on-die termination mode" "0,1,2,3" bitfld.long 0x00 0. " ACRANKCLKSEL ,Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices" "0,1" line.long 0x04 "ACIOCR1,AC I/O Configuration Register 1" line.long 0x08 "ACIOCR2,AC I/O Configuration Register 2" bitfld.long 0x08 31. " CLKGENCLKGATE ,Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL slice" "No gating,Gating" bitfld.long 0x08 30. " ACOECLKGATE0 ,Clock gating for output enable D slices [0]" "No gating,Gating" bitfld.long 0x08 29. " ACPDRCLKGATE0 ,Clock gating for power down receiver D slices [0]" "No gating,Gating" bitfld.long 0x08 28. " ACTECLKGATE0 ,Clock gating for termination enable D slices [0]" "No gating,Gating" newline bitfld.long 0x08 26.--27. " CKNCLKGATE0 ,Clock gating for CK# D slices [1:0]" "0,1,2,3" bitfld.long 0x08 24.--25. " CKCLKGATE0 ,Clock gating for CK D slices [1:0]" "0,1,2,3" hexmask.long.tbyte 0x08 0.--23. 1. " ACCLKGATE0 ,Clock gating for AC D slices [23:0]" line.long 0x0C "ACIOCR3,AC I/O Configuration Register 3" bitfld.long 0x0C 30.--31. " PAROEMODE ,SDRAM parity output enable (OE) mode selection" "0,1,2,3" bitfld.long 0x0C 26.--29. " BGOEMODE ,SDRAM bank group output enable (OE) mode selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 22.--25. " BAOEMODE ,SDRAM bank address output enable (OE) mode selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 20.--21. " A17OEMODE ,SDRAM A[17] output enable (OE) mode selection" "0,1,2,3" newline bitfld.long 0x0C 18.--19. " A16OEMODE ,SDRAM A[16] / RAS_N output enable (OE) mode selection" "0,1,2,3" bitfld.long 0x0C 16.--17. " ACTOEMODE ,SDRAM ACT_N output enable (OE) mode selection" "0,1,2,3" bitfld.long 0x0C 0.--3. " CKOEMODE ,SDRAM CK output enable (OE) mode selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "ACIOCR4,AC I/O Configuration Register 4" bitfld.long 0x10 31. " LBCLKGATE ,Clock gating for AC LB slices and loopback read valid slices" "No gating,Gating" bitfld.long 0x10 30. " ACOECLKGATE1 ,Clock gating for output enable D slices [1]" "No gating,Gating" bitfld.long 0x10 29. " ACPDRCLKGATE1 ,Clock gating for power down receiver D slices [1]" "No gating,Gating" bitfld.long 0x10 28. " ACTECLKGATE1 ,Clock gating for termination enable D slices [1]" "No gating,Gating" newline bitfld.long 0x10 26.--27. " CKNCLKGATE1 ,Clock gating for CK# D slices [3:2]" "0,1,2,3" bitfld.long 0x10 24.--25. " CKCLKGATE1 ,Clock gating for CK D slices [3:2]" "0,1,2,3" hexmask.long.tbyte 0x10 0.--23. 1. " ACCLKGATE1 ,Clock gating for AC D slices [47:24]" line.long 0x14 "ACIOCR5,AC I/O Configuration Register 5" bitfld.long 0x14 25.--27. " ACVREFIOM ,IOM bits for PVREF and PVREFE cells in AC IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x14 22.--24. " ACXIOM ,AC IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x14 11.--21. 1. " ACTXM ,AC IO transmitter mode" hexmask.long.word 0x14 0.--10. 1. " ACRXM ,AC IO receiver mode" group.long 0x520++0x03 line.long 0x00 "IOVCR0,IO VREF Control Register 0" bitfld.long 0x00 28. " ACREFPEN ,Address/command lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x00 26.--27. " ACREFEEN ,Address/command lane internal VREF enable" "0,1,2,3" bitfld.long 0x00 25. " ACREFSEN ,Address/command lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x00 24. " ACREFIEN ,Address/command lane internal VREF enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " ACREFESELRANGE ,External VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x00 16.--22. 1. " ACREFESEL ,Address/command lane external VREF select" bitfld.long 0x00 15. " ACREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x00 8.--14. 1. " ACREFSSEL ,Address/command lane single-end VREF select" newline bitfld.long 0x00 7. " ACVREFISELRANGE ,Internal VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x00 0.--6. 1. " ACVREFISEL ,REFSEL control for internal AC IOs" group.long 0x528++0x07 line.long 0x00 "VTCR0,VREF Training Control Register 0" bitfld.long 0x00 29.--31. " TVREF ,Number of CTL_CLK required to meet > 150ns timing requirements during DRAM DQ VREF training" "0,1,2,3,4,5,6,7" bitfld.long 0x00 28. " DVEN ,DRM DQ VREF training enable" "Disabled,Enabled" bitfld.long 0x00 27. " PDAEN ,Per device addressability enable" "Disabled,Enabled" bitfld.long 0x00 22.--25. " VWCR ,VREF word count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 18.--21. " DVSS ,DRAM DQ VREF step size used during DRAM VREF training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--17. " DVMAX ,Maximum VREF limit value used during DRAM VREF training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 6.--11. " DVMIN ,Minimum VREF limit value used during DRAM VREF training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DVINIT ,Initial DRAM DQ VREF value used during DRAM VREF training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "VTCR1,VREF Training Control Register 1" bitfld.long 0x04 28.--31. " HVSS ,Host VREF step size used during VREF training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x04 20.--26. 1. " HVMAX ,Maximum VREF limit value used during DRAM VREF training" hexmask.long.byte 0x04 12.--18. 1. " HVMIN ,Minimum VREF limit value used during DRAM VREF training" bitfld.long 0x04 9.--10. " SHRNK ,Static host VREF rank value" "0,1,2,3" newline bitfld.long 0x04 8. " SHREN ,Static host VREF rank enable" "Disabled,Enabled" bitfld.long 0x04 5.--7. " TVREFIO ,Number of CTL_CLK required to meet > 200ns VREF settling timing requirements during host IO VREF training" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3.--4. " EOFF ,Eye LCDL offset value for VREF training" "0,1,2,3" bitfld.long 0x04 2. " ENUM ,Number of LCDL eye points for which VREF training is repeated" "0,1" newline bitfld.long 0x04 1. " HVEN ,HOST IO internal VREF training enable" "Disabled,Enabled" bitfld.long 0x04 0. " HVIO ,Host IO type control" "0,1" newline group.long 0x540++0x47 line.long 0x00 "ACBDLR0,AC Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " CK3BD ,CK3 bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " CK2BD ,CK2 bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CK1BD ,CK1 bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CK0BD ,CK0 bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "ACBDLR1,AC Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " PARBD ,Delay select for the BDL on parity" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " A16BD ,Delay select for the BDL on address A[16]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " A17BD ,Delay select for the BDL on address A[17]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " ACTBD ,Delay select for the BDL on ACTN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "ACBDLR2,AC Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " BG1BD ,Delay select for the BDL on BG[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " BG0BD ,Delay select for the BDL on BG[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " BA1BD ,Delay select for the BDL on BA[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " BA0BD ,Delay select for the BDL on BA[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "ACBDLR3,AC Bit Delay Line Register 3" bitfld.long 0x0C 24.--29. " CS3BD ,Delay select for the BDL on CS[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " CS2BD ,Delay select for the BDL on CS[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 8.--13. " CS1BD ,Delay select for the BDL on CS[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " CS0BD ,Delay select for the BDL on CS[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "ACBDLR4,AC Bit Delay Line Register 4" bitfld.long 0x10 24.--29. " ODT3BD ,Delay select for the BDL on ODT[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 16.--21. " ODT2BD ,Delay select for the BDL on ODT[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 8.--13. " ODT1BD ,Delay select for the BDL on ODT[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 0.--5. " ODT0BD ,Delay select for the BDL on ODT[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x14 "ACBDLR5,AC Bit Delay Line Register 5" bitfld.long 0x14 24.--29. " CKE3BD ,Delay select for the BDL on CKE[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 16.--21. " CKE2BD ,Delay select for the BDL on CKE[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 8.--13. " CKE1BD ,Delay select for the BDL on CKE[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 0.--5. " CKE0BD ,Delay select for the BDL on CKE[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x18 "ACBDLR6,AC Bit Delay Line Register 6" bitfld.long 0x18 24.--29. " A03BD ,Delay select for the BDL on address A[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " A02BD ,Delay select for the BDL on address A[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " A01BD ,Delay select for the BDL on address A[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " A00BD ,Delay select for the BDL on address A[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "ACBDLR7,AC Bit Delay Line Register 7" bitfld.long 0x1C 24.--29. " A07BD ,Delay select for the BDL on address A[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1C 16.--21. " A06BD ,Delay select for the BDL on address A[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1C 8.--13. " A05BD ,Delay select for the BDL on address A[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1C 0.--5. " A04BD ,Delay select for the BDL on address A[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x20 "ACBDLR8,AC Bit Delay Line Register 8" bitfld.long 0x20 24.--29. " A11BD ,Delay select for the BDL on address A[11]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x20 16.--21. " A10BD ,Delay select for the BDL on address A[10]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x20 8.--13. " A09BD ,Delay select for the BDL on address A[9]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x20 0.--5. " A08BD ,Delay select for the BDL on address A[8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x24 "ACBDLR9,AC Bit Delay Line Register 9" bitfld.long 0x24 24.--29. " A15BD ,Delay select for the BDL on address A[15]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x24 16.--21. " A14BD ,Delay select for the BDL on address A[14]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x24 8.--13. " A13BD ,Delay select for the BDL on address A[13]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x24 0.--5. " A12BD ,Delay select for the BDL on address A[12]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x28 "ACBDLR10,AC Bit Delay Line Register 10" bitfld.long 0x28 24.--29. " CID2BD ,Delay select for the BDL on chip ID CID[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x28 16.--21. " CID1BD ,Delay select for the BDL on chip ID CID[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x28 8.--13. " CID0BD ,Delay select for the BDL on chip ID CID[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x2C "ACBDLR11,AC Bit Delay Line Register 11" bitfld.long 0x2C 24.--29. " CS7BD ,Delay select for the BDL on CS[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2C 16.--21. " CS6BD ,Delay select for the BDL on CS[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2C 8.--13. " CS5BD ,Delay select for the BDL on CS[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2C 0.--5. " CS4BD ,Delay select for the BDL on CS[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x30 "ACBDLR12,AC Bit Delay Line Register 12" bitfld.long 0x30 24.--29. " CS11BD ,Delay select for the BDL on CS[11]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x30 16.--21. " CS10BD ,Delay select for the BDL on CS[10]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x30 8.--13. " CS9BD ,Delay select for the BDL on CS[9]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x30 0.--5. " CS8BD ,Delay select for the BDL on CS[8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x34 "ACBDLR13,AC Bit Delay Line Register 13" bitfld.long 0x34 24.--29. " ODT7BD ,Delay select for the BDL on ODT[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x34 16.--21. " ODT6BD ,Delay select for the BDL on ODT[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x34 8.--13. " ODT5BD ,Delay select for the BDL on ODT[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x34 0.--5. " ODT4BD ,Delay select for the BDL on ODT[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x38 "ACBDLR14,AC Bit Delay Line Register 14" bitfld.long 0x38 24.--29. " CKE7BD ,Delay select for the BDL on CKE[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x38 16.--21. " CKE6BD ,Delay select for the BDL on CKE[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x38 8.--13. " CKE5BD ,Delay select for the BDL on CKE[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x38 0.--5. " CKE4BD ,Delay select for the BDL on CKE[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x3C "ACBDLR15,AC Bit Delay Line Register 15" bitfld.long 0x3C 16.--21. " OEBD ,Delay select for the BDL on OE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3C 8.--13. " TEBD ,Delay select for the BDL on TE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3C 0.--5. " PDRBD ,Delay select for the BDL on PDR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x40 "ACBDLR16,AC Bit Delay Line Register 16" bitfld.long 0x40 24.--29. " CKN3BD ,Delay select for the BDL on CKN[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x40 16.--21. " CKN2BD ,Delay select for the BDL on CKN[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x40 8.--13. " CKN1BD ,Delay select for the BDL on CKN[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x40 0.--5. " CKN0BD ,Delay select for the BDL on CKN[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x44 "ACLCDLR,AC Local Calibrated Delay Line Register" hexmask.long.word 0x44 16.--24. 1. " ACD1 ,Address/command delay for AC macro 1" hexmask.long.word 0x44 0.--8. 1. " ACD ,Address/command delay for AC macro 0" group.long 0x5A0++0x07 line.long 0x00 "ACMDLR0,AC Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "ACMDLR1,AC Master Delay Line Register 1" hexmask.long.word 0x04 16.--24. 1. " MDLD1 ,MDL delay for AC macro 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay for AC macro 0" newline group.long 0x680++0x03 line.long 0x00 "ZQCR,ZQ Impedance Control Register" bitfld.long 0x00 25. " ZQREFISELRANGE ,ZQ VREF range" "0,1" bitfld.long 0x00 19.--24. " PGWAIT_FRQB ,Programmable wait for frequency B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 13.--18. " PGWAIT_FRQA ,Programmable wait for frequency A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12. " ZQREFPEN ,ZQ VREF pad enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ZQREFIEN ,ZQ internal VREF enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " ODT_MODE ,Choice of termination mode" "0,1,2,3" bitfld.long 0x00 8. " FORCE_ZCAL_VT_UPDATE ,Force ZCAL VT update" "0,1" bitfld.long 0x00 5.--7. " IODLMT ,IO VT drift limit" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4. " AVGEN ,Averaging algorithm enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " AVGMAX ,Maximum number of averaging rounds to be used by averaging algorithm" "0,1,2,3" bitfld.long 0x00 1. " ZCALT ,ZQ calibration type" "0,1" bitfld.long 0x00 0. " ZQPD ,ZQ power down" "No,Yes" group.long 0x684++0x07 line.long 0x00 "ZQ0PR0,ZQ 0 Impedance Control Program Register 0" bitfld.long 0x00 31. " PD_DRV_ZDEN ,Pull-down drive strength ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 30. " PU_DRV_ZDEN ,Pull-up drive strength ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 29. " PD_ODT_ZDEN ,Pull-down termination ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 28. " PU_ODT_ZDEN ,Pull-up termination ZCTRL override enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " ZSEGBYP ,Calibration segment bypass" "Not bypassed,Bypassed" bitfld.long 0x00 25.--26. " ZLE_MODE ,VREF latch mode" "0,1,2,3" bitfld.long 0x00 22.--24. " ODT_ADJUST ,Termination adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19.--21. " PD_DRV_ADJUST ,Pull-down drive strength adjustment" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. " PU_DRV_ADJUST ,Pull-up drive strength adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--15. " ZPROG_DRAM_ODT ,DRAM impedance divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " ZPROG_HOST_ODT ,HOST impedance divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " ZPROG_ASYM_DRV_PD ,Impedance divide ratio pull-down drive calibration during asymmetric drive strength calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " ZPROG_ASYM_DRV_PU ,Impedance divide ratio (pull-up drive calibration during asymmetric drive strength calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ZQ0PR1,ZQ 0 Impedance Control Program Register 1" hexmask.long.byte 0x04 8.--14. 1. " PU_REFSEL ,Pull-up REFSEL for PZCTRL cell" hexmask.long.byte 0x04 0.--6. 1. " PD_REFSEL ,Pull-down REFSEL for PZCTRL cell" rgroup.long (0x684+0x08)++0x07 line.long 0x00 "ZQ0DR0,ZQ 0 Impedance Control Data Register 0" hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_RESULT ,Pull-up drive strength calibration code result" hexmask.long.word 0x00 0.--9. 1. " ZDATA_PD_DRV_RESULT ,Pull-down drive strength calibration code result" line.long 0x04 "ZQ0DR1,ZQ 0 Impedance Control Data Register 1" hexmask.long.word 0x04 16.--25. 1. " ZDATA_PU_ODT_RESULT ,Pull-up termination calibration code result" hexmask.long.word 0x04 0.--9. 1. " ZDATA_PD_ODT_RESULT ,Pull-down termination calibration code result" group.long (0x684+0x10)++0x07 line.long 0x00 "ZQ0OR0,ZQ 0 Impedance Control Override Data Register 0" hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_OVRD ,Override value for the pull-up output impedance" hexmask.long.word 0x00 0.--9. 1. " ZDATA_PD_DRV_OVRD ,Override value for the pull-down output impedance" line.long 0x04 "ZQ0OR1,ZQ 0 Impedance Control Override Data Register 1" hexmask.long.word 0x04 16.--25. 1. " ZDATA_PU_ODT_OVRD ,Override value for the pull-up termination" hexmask.long.word 0x04 0.--9. 1. " ZDATA_PD_ODT_OVRD ,Override value for the pull-down termination" rgroup.long (0x684+0x18)++0x03 line.long 0x00 "ZQ0SR,ZQ 0 Impedance Control Status Register" bitfld.long 0x00 13. " PD_ODT_SAT ,Pull-down drive strength code saturated due to termination strength adjustment setting in ZQ0PR" "Not saturated,Saturated" bitfld.long 0x00 12. " PU_ODT_SAT ,Pull-up drive strength code saturated due to termination strength adjustment setting in ZQ0PR" "Not saturated,Saturated" bitfld.long 0x00 11. " PD_DRV_SAT ,Pull-down drive strength code saturated due to drive strength adjustment setting in ZQ0PR" "Not saturated,Saturated" bitfld.long 0x00 10. " PU_DRV_SAT ,Pull-up drive strength code saturated due to drive strength adjustment setting in ZQ0PR" "Not saturated,Saturated" newline bitfld.long 0x00 9. " ZDONE ,Impedance calibration done" "Not done,Done" bitfld.long 0x00 8. " ZERR ,Impedance calibration error" "No error,Error" bitfld.long 0x00 6.--7. " OPU ,On-die termination ODT pull-up calibration status" "0,1,2,3" bitfld.long 0x00 4.--5. " OPD ,On-die termination ODT pull-down calibration status" "0,1,2,3" newline bitfld.long 0x00 2.--3. " ZPU ,Output impedance pull-up calibration status" "0,1,2,3" bitfld.long 0x00 0.--1. " ZPD ,Output impedance pull-down calibration status" "0,1,2,3" group.long 0x6A4++0x07 line.long 0x00 "ZQ1PR0,ZQ 1 Impedance Control Program Register 0" bitfld.long 0x00 31. " PD_DRV_ZDEN ,Pull-down drive strength ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 30. " PU_DRV_ZDEN ,Pull-up drive strength ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 29. " PD_ODT_ZDEN ,Pull-down termination ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 28. " PU_ODT_ZDEN ,Pull-up termination ZCTRL override enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " ZSEGBYP ,Calibration segment bypass" "Not bypassed,Bypassed" bitfld.long 0x00 25.--26. " ZLE_MODE ,VREF latch mode" "0,1,2,3" bitfld.long 0x00 22.--24. " ODT_ADJUST ,Termination adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19.--21. " PD_DRV_ADJUST ,Pull-down drive strength adjustment" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. " PU_DRV_ADJUST ,Pull-up drive strength adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--15. " ZPROG_DRAM_ODT ,DRAM impedance divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " ZPROG_HOST_ODT ,HOST impedance divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " ZPROG_ASYM_DRV_PD ,Impedance divide ratio pull-down drive calibration during asymmetric drive strength calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " ZPROG_ASYM_DRV_PU ,Impedance divide ratio (pull-up drive calibration during asymmetric drive strength calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ZQ1PR1,ZQ 1 Impedance Control Program Register 1" hexmask.long.byte 0x04 8.--14. 1. " PU_REFSEL ,Pull-up REFSEL for PZCTRL cell" hexmask.long.byte 0x04 0.--6. 1. " PD_REFSEL ,Pull-down REFSEL for PZCTRL cell" rgroup.long (0x6A4+0x08)++0x07 line.long 0x00 "ZQ1DR0,ZQ 1 Impedance Control Data Register 0" hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_RESULT ,Pull-up drive strength calibration code result" hexmask.long.word 0x00 0.--9. 1. " ZDATA_PD_DRV_RESULT ,Pull-down drive strength calibration code result" line.long 0x04 "ZQ1DR1,ZQ 1 Impedance Control Data Register 1" hexmask.long.word 0x04 16.--25. 1. " ZDATA_PU_ODT_RESULT ,Pull-up termination calibration code result" hexmask.long.word 0x04 0.--9. 1. " ZDATA_PD_ODT_RESULT ,Pull-down termination calibration code result" group.long (0x6A4+0x10)++0x07 line.long 0x00 "ZQ1OR0,ZQ 1 Impedance Control Override Data Register 0" hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_OVRD ,Override value for the pull-up output impedance" hexmask.long.word 0x00 0.--9. 1. " ZDATA_PD_DRV_OVRD ,Override value for the pull-down output impedance" line.long 0x04 "ZQ1OR1,ZQ 1 Impedance Control Override Data Register 1" hexmask.long.word 0x04 16.--25. 1. " ZDATA_PU_ODT_OVRD ,Override value for the pull-up termination" hexmask.long.word 0x04 0.--9. 1. " ZDATA_PD_ODT_OVRD ,Override value for the pull-down termination" rgroup.long (0x6A4+0x18)++0x03 line.long 0x00 "ZQ1SR,ZQ 1 Impedance Control Status Register" bitfld.long 0x00 13. " PD_ODT_SAT ,Pull-down drive strength code saturated due to termination strength adjustment setting in ZQ1PR" "Not saturated,Saturated" bitfld.long 0x00 12. " PU_ODT_SAT ,Pull-up drive strength code saturated due to termination strength adjustment setting in ZQ1PR" "Not saturated,Saturated" bitfld.long 0x00 11. " PD_DRV_SAT ,Pull-down drive strength code saturated due to drive strength adjustment setting in ZQ1PR" "Not saturated,Saturated" bitfld.long 0x00 10. " PU_DRV_SAT ,Pull-up drive strength code saturated due to drive strength adjustment setting in ZQ1PR" "Not saturated,Saturated" newline bitfld.long 0x00 9. " ZDONE ,Impedance calibration done" "Not done,Done" bitfld.long 0x00 8. " ZERR ,Impedance calibration error" "No error,Error" bitfld.long 0x00 6.--7. " OPU ,On-die termination ODT pull-up calibration status" "0,1,2,3" bitfld.long 0x00 4.--5. " OPD ,On-die termination ODT pull-down calibration status" "0,1,2,3" newline bitfld.long 0x00 2.--3. " ZPU ,Output impedance pull-up calibration status" "0,1,2,3" bitfld.long 0x00 0.--1. " ZPD ,Output impedance pull-down calibration status" "0,1,2,3" group.long 0x6C4++0x07 line.long 0x00 "ZQ2PR0,ZQ 2 Impedance Control Program Register 0" bitfld.long 0x00 31. " PD_DRV_ZDEN ,Pull-down drive strength ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 30. " PU_DRV_ZDEN ,Pull-up drive strength ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 29. " PD_ODT_ZDEN ,Pull-down termination ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 28. " PU_ODT_ZDEN ,Pull-up termination ZCTRL override enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " ZSEGBYP ,Calibration segment bypass" "Not bypassed,Bypassed" bitfld.long 0x00 25.--26. " ZLE_MODE ,VREF latch mode" "0,1,2,3" bitfld.long 0x00 22.--24. " ODT_ADJUST ,Termination adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19.--21. " PD_DRV_ADJUST ,Pull-down drive strength adjustment" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. " PU_DRV_ADJUST ,Pull-up drive strength adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--15. " ZPROG_DRAM_ODT ,DRAM impedance divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " ZPROG_HOST_ODT ,HOST impedance divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " ZPROG_ASYM_DRV_PD ,Impedance divide ratio pull-down drive calibration during asymmetric drive strength calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " ZPROG_ASYM_DRV_PU ,Impedance divide ratio (pull-up drive calibration during asymmetric drive strength calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ZQ2PR1,ZQ 2 Impedance Control Program Register 1" hexmask.long.byte 0x04 8.--14. 1. " PU_REFSEL ,Pull-up REFSEL for PZCTRL cell" hexmask.long.byte 0x04 0.--6. 1. " PD_REFSEL ,Pull-down REFSEL for PZCTRL cell" rgroup.long (0x6C4+0x08)++0x07 line.long 0x00 "ZQ2DR0,ZQ 2 Impedance Control Data Register 0" hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_RESULT ,Pull-up drive strength calibration code result" hexmask.long.word 0x00 0.--9. 1. " ZDATA_PD_DRV_RESULT ,Pull-down drive strength calibration code result" line.long 0x04 "ZQ2DR1,ZQ 2 Impedance Control Data Register 1" hexmask.long.word 0x04 16.--25. 1. " ZDATA_PU_ODT_RESULT ,Pull-up termination calibration code result" hexmask.long.word 0x04 0.--9. 1. " ZDATA_PD_ODT_RESULT ,Pull-down termination calibration code result" group.long (0x6C4+0x10)++0x07 line.long 0x00 "ZQ2OR0,ZQ 2 Impedance Control Override Data Register 0" hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_OVRD ,Override value for the pull-up output impedance" hexmask.long.word 0x00 0.--9. 1. " ZDATA_PD_DRV_OVRD ,Override value for the pull-down output impedance" line.long 0x04 "ZQ2OR1,ZQ 2 Impedance Control Override Data Register 1" hexmask.long.word 0x04 16.--25. 1. " ZDATA_PU_ODT_OVRD ,Override value for the pull-up termination" hexmask.long.word 0x04 0.--9. 1. " ZDATA_PD_ODT_OVRD ,Override value for the pull-down termination" rgroup.long (0x6C4+0x18)++0x03 line.long 0x00 "ZQ2SR,ZQ 2 Impedance Control Status Register" bitfld.long 0x00 13. " PD_ODT_SAT ,Pull-down drive strength code saturated due to termination strength adjustment setting in ZQ2PR" "Not saturated,Saturated" bitfld.long 0x00 12. " PU_ODT_SAT ,Pull-up drive strength code saturated due to termination strength adjustment setting in ZQ2PR" "Not saturated,Saturated" bitfld.long 0x00 11. " PD_DRV_SAT ,Pull-down drive strength code saturated due to drive strength adjustment setting in ZQ2PR" "Not saturated,Saturated" bitfld.long 0x00 10. " PU_DRV_SAT ,Pull-up drive strength code saturated due to drive strength adjustment setting in ZQ2PR" "Not saturated,Saturated" newline bitfld.long 0x00 9. " ZDONE ,Impedance calibration done" "Not done,Done" bitfld.long 0x00 8. " ZERR ,Impedance calibration error" "No error,Error" bitfld.long 0x00 6.--7. " OPU ,On-die termination ODT pull-up calibration status" "0,1,2,3" bitfld.long 0x00 4.--5. " OPD ,On-die termination ODT pull-down calibration status" "0,1,2,3" newline bitfld.long 0x00 2.--3. " ZPU ,Output impedance pull-up calibration status" "0,1,2,3" bitfld.long 0x00 0.--1. " ZPD ,Output impedance pull-down calibration status" "0,1,2,3" rgroup.long 0x6E4++0x07 line.long 0x00 "ZQ3PR0,ZQ 3 Impedance Control Program Register 0" bitfld.long 0x00 31. " PD_DRV_ZDEN ,Pull-down drive strength ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 30. " PU_DRV_ZDEN ,Pull-up drive strength ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 29. " PD_ODT_ZDEN ,Pull-down termination ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 28. " PU_ODT_ZDEN ,Pull-up termination ZCTRL override enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " ZSEGBYP ,Calibration segment bypass" "Not bypassed,Bypassed" bitfld.long 0x00 25.--26. " ZLE_MODE ,VREF latch mode" "0,1,2,3" bitfld.long 0x00 22.--24. " ODT_ADJUST ,Termination adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19.--21. " PD_DRV_ADJUST ,Pull-down drive strength adjustment" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. " PU_DRV_ADJUST ,Pull-up drive strength adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--15. " ZPROG_DRAM_ODT ,DRAM impedance divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " ZPROG_HOST_ODT ,HOST impedance divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " ZPROG_ASYM_DRV_PD ,Impedance divide ratio pull-down drive calibration during asymmetric drive strength calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " ZPROG_ASYM_DRV_PU ,Impedance divide ratio (pull-up drive calibration during asymmetric drive strength calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ZQ3PR1,ZQ 3 Impedance Control Program Register 1" hexmask.long.byte 0x04 8.--14. 1. " PU_REFSEL ,Pull-up REFSEL for PZCTRL cell" hexmask.long.byte 0x04 0.--6. 1. " PD_REFSEL ,Pull-down REFSEL for PZCTRL cell" rgroup.long (0x6E4+0x08)++0x07 line.long 0x00 "ZQ3DR0,ZQ 3 Impedance Control Data Register 0" hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_RESULT ,Pull-up drive strength calibration code result" hexmask.long.word 0x00 0.--9. 1. " ZDATA_PD_DRV_RESULT ,Pull-down drive strength calibration code result" line.long 0x04 "ZQ3DR1,ZQ 3 Impedance Control Data Register 1" hexmask.long.word 0x04 16.--25. 1. " ZDATA_PU_ODT_RESULT ,Pull-up termination calibration code result" hexmask.long.word 0x04 0.--9. 1. " ZDATA_PD_ODT_RESULT ,Pull-down termination calibration code result" rgroup.long (0x6E4+0x10)++0x07 line.long 0x00 "ZQ3OR0,ZQ 3 Impedance Control Override Data Register 0" hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_OVRD ,Override value for the pull-up output impedance" hexmask.long.word 0x00 0.--9. 1. " ZDATA_PD_DRV_OVRD ,Override value for the pull-down output impedance" line.long 0x04 "ZQ3OR1,ZQ 3 Impedance Control Override Data Register 1" hexmask.long.word 0x04 16.--25. 1. " ZDATA_PU_ODT_OVRD ,Override value for the pull-up termination" hexmask.long.word 0x04 0.--9. 1. " ZDATA_PD_ODT_OVRD ,Override value for the pull-down termination" rgroup.long (0x6E4+0x18)++0x03 line.long 0x00 "ZQ3SR,ZQ 3 Impedance Control Status Register" bitfld.long 0x00 13. " PD_ODT_SAT ,Pull-down drive strength code saturated due to termination strength adjustment setting in ZQ3PR" "Not saturated,Saturated" bitfld.long 0x00 12. " PU_ODT_SAT ,Pull-up drive strength code saturated due to termination strength adjustment setting in ZQ3PR" "Not saturated,Saturated" bitfld.long 0x00 11. " PD_DRV_SAT ,Pull-down drive strength code saturated due to drive strength adjustment setting in ZQ3PR" "Not saturated,Saturated" bitfld.long 0x00 10. " PU_DRV_SAT ,Pull-up drive strength code saturated due to drive strength adjustment setting in ZQ3PR" "Not saturated,Saturated" newline bitfld.long 0x00 9. " ZDONE ,Impedance calibration done" "Not done,Done" bitfld.long 0x00 8. " ZERR ,Impedance calibration error" "No error,Error" bitfld.long 0x00 6.--7. " OPU ,On-die termination ODT pull-up calibration status" "0,1,2,3" bitfld.long 0x00 4.--5. " OPD ,On-die termination ODT pull-down calibration status" "0,1,2,3" newline bitfld.long 0x00 2.--3. " ZPU ,Output impedance pull-up calibration status" "0,1,2,3" bitfld.long 0x00 0.--1. " ZPD ,Output impedance pull-down calibration status" "0,1,2,3" newline group.long 0x700++0x1F line.long 0x00 "DX0GCR0,DATX8 0 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX0GCR1,DATX8 0 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX0GCR2,DATX8 0 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX0GCR3,DATX8 0 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX0GCR4,DATX8 0 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX0GCR5,DATX8 0 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX0GCR6,DATX8 0 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX0GCR7,DATX8 0 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" group.long (0x700+0x28)++0x07 line.long 0x00 "DX0DQMAP0,DATX8 0 DQ/DM Mapping Register 0" rbitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW0DQMAP1,DATX8 0 DQ/DM Mapping Register 1" rbitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x700+0x40)++0x0B line.long 0x00 "DX0BDLR0,DATX8 0 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX0BDLR1,DATX8 0 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX0BDLR2,DATX8 0 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x700+0x50)++0x0B line.long 0x00 "DX0BDLR3,DATX8 0 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX0BDLR4,DATX8 0 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX0BDLR5,DATX8 0 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x700+0x60)++0x03 line.long 0x00 "DX0BDLR6,DATX8 0 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x700+0x80)++0x17 line.long 0x00 "DX0LCDLR0,DATX8 0 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX0LCDLR1,DATX8 0 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX0LCDLR2,DATX8 0 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX0LCDLR3,DATX8 0 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX0LCDLR4,DATX8 0 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX0LCDLR5,DATX8 0 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" group.long (0x700+0xA0)++0x07 line.long 0x00 "DX0MDLR0,DATX8 0 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX0MDLR1,DATX8 0 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" group.long (0x700+0xC0)++0x03 line.long 0x00 "DX0GTR0,DATX8 0 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0x700+0xD0)++0x1F line.long 0x00 "DX0RSR0,DATX8 0 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX0RSR1,DATX8 0 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX0RSR2,DATX8 0 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX0RSR3,DATX8 0 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX0GSR0,DATX8 0 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX0GSR1,DATX8 0 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX0GSR2,DATX8 0 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX0GSR3,DATX8 0 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" group.long 0x800++0x1F line.long 0x00 "DX1GCR0,DATX8 1 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX1GCR1,DATX8 1 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX1GCR2,DATX8 1 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX1GCR3,DATX8 1 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX1GCR4,DATX8 1 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX1GCR5,DATX8 1 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX1GCR6,DATX8 1 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX1GCR7,DATX8 1 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" group.long (0x800+0x28)++0x07 line.long 0x00 "DX1DQMAP0,DATX8 1 DQ/DM Mapping Register 0" rbitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW1DQMAP1,DATX8 1 DQ/DM Mapping Register 1" rbitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x800+0x40)++0x0B line.long 0x00 "DX1BDLR0,DATX8 1 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX1BDLR1,DATX8 1 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX1BDLR2,DATX8 1 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x800+0x50)++0x0B line.long 0x00 "DX1BDLR3,DATX8 1 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX1BDLR4,DATX8 1 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX1BDLR5,DATX8 1 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x800+0x60)++0x03 line.long 0x00 "DX1BDLR6,DATX8 1 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x800+0x80)++0x17 line.long 0x00 "DX1LCDLR0,DATX8 1 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX1LCDLR1,DATX8 1 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX1LCDLR2,DATX8 1 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX1LCDLR3,DATX8 1 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX1LCDLR4,DATX8 1 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX1LCDLR5,DATX8 1 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" group.long (0x800+0xA0)++0x07 line.long 0x00 "DX1MDLR0,DATX8 1 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX1MDLR1,DATX8 1 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" group.long (0x800+0xC0)++0x03 line.long 0x00 "DX1GTR0,DATX8 1 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0x800+0xD0)++0x1F line.long 0x00 "DX1RSR0,DATX8 1 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX1RSR1,DATX8 1 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX1RSR2,DATX8 1 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX1RSR3,DATX8 1 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX1GSR0,DATX8 1 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX1GSR1,DATX8 1 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX1GSR2,DATX8 1 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX1GSR3,DATX8 1 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" group.long 0x900++0x1F line.long 0x00 "DX2GCR0,DATX8 2 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX2GCR1,DATX8 2 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX2GCR2,DATX8 2 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX2GCR3,DATX8 2 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX2GCR4,DATX8 2 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX2GCR5,DATX8 2 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX2GCR6,DATX8 2 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX2GCR7,DATX8 2 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" group.long (0x900+0x28)++0x07 line.long 0x00 "DX2DQMAP0,DATX8 2 DQ/DM Mapping Register 0" rbitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW2DQMAP1,DATX8 2 DQ/DM Mapping Register 1" rbitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x900+0x40)++0x0B line.long 0x00 "DX2BDLR0,DATX8 2 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX2BDLR1,DATX8 2 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX2BDLR2,DATX8 2 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x900+0x50)++0x0B line.long 0x00 "DX2BDLR3,DATX8 2 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX2BDLR4,DATX8 2 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX2BDLR5,DATX8 2 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x900+0x60)++0x03 line.long 0x00 "DX2BDLR6,DATX8 2 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x900+0x80)++0x17 line.long 0x00 "DX2LCDLR0,DATX8 2 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX2LCDLR1,DATX8 2 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX2LCDLR2,DATX8 2 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX2LCDLR3,DATX8 2 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX2LCDLR4,DATX8 2 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX2LCDLR5,DATX8 2 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" group.long (0x900+0xA0)++0x07 line.long 0x00 "DX2MDLR0,DATX8 2 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX2MDLR1,DATX8 2 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" group.long (0x900+0xC0)++0x03 line.long 0x00 "DX2GTR0,DATX8 2 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0x900+0xD0)++0x1F line.long 0x00 "DX2RSR0,DATX8 2 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX2RSR1,DATX8 2 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX2RSR2,DATX8 2 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX2RSR3,DATX8 2 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX2GSR0,DATX8 2 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX2GSR1,DATX8 2 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX2GSR2,DATX8 2 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX2GSR3,DATX8 2 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" group.long 0xA00++0x1F line.long 0x00 "DX3GCR0,DATX8 3 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX3GCR1,DATX8 3 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX3GCR2,DATX8 3 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX3GCR3,DATX8 3 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX3GCR4,DATX8 3 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX3GCR5,DATX8 3 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX3GCR6,DATX8 3 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX3GCR7,DATX8 3 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" group.long (0xA00+0x28)++0x07 line.long 0x00 "DX3DQMAP0,DATX8 3 DQ/DM Mapping Register 0" rbitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW3DQMAP1,DATX8 3 DQ/DM Mapping Register 1" rbitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0xA00+0x40)++0x0B line.long 0x00 "DX3BDLR0,DATX8 3 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX3BDLR1,DATX8 3 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX3BDLR2,DATX8 3 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0xA00+0x50)++0x0B line.long 0x00 "DX3BDLR3,DATX8 3 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX3BDLR4,DATX8 3 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX3BDLR5,DATX8 3 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0xA00+0x60)++0x03 line.long 0x00 "DX3BDLR6,DATX8 3 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0xA00+0x80)++0x17 line.long 0x00 "DX3LCDLR0,DATX8 3 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX3LCDLR1,DATX8 3 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX3LCDLR2,DATX8 3 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX3LCDLR3,DATX8 3 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX3LCDLR4,DATX8 3 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX3LCDLR5,DATX8 3 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" group.long (0xA00+0xA0)++0x07 line.long 0x00 "DX3MDLR0,DATX8 3 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX3MDLR1,DATX8 3 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" group.long (0xA00+0xC0)++0x03 line.long 0x00 "DX3GTR0,DATX8 3 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0xA00+0xD0)++0x1F line.long 0x00 "DX3RSR0,DATX8 3 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX3RSR1,DATX8 3 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX3RSR2,DATX8 3 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX3RSR3,DATX8 3 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX3GSR0,DATX8 3 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX3GSR1,DATX8 3 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX3GSR2,DATX8 3 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX3GSR3,DATX8 3 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" rgroup.long 0xB00++0x1F line.long 0x00 "DX4GCR0,DATX8 4 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX4GCR1,DATX8 4 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX4GCR2,DATX8 4 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX4GCR3,DATX8 4 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX4GCR4,DATX8 4 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX4GCR5,DATX8 4 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX4GCR6,DATX8 4 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX4GCR7,DATX8 4 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" rgroup.long (0xB00+0x28)++0x07 line.long 0x00 "DX4DQMAP0,DATX8 4 DQ/DM Mapping Register 0" bitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW4DQMAP1,DATX8 4 DQ/DM Mapping Register 1" bitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0xB00+0x40)++0x0B line.long 0x00 "DX4BDLR0,DATX8 4 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX4BDLR1,DATX8 4 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX4BDLR2,DATX8 4 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xB00+0x50)++0x0B line.long 0x00 "DX4BDLR3,DATX8 4 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX4BDLR4,DATX8 4 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX4BDLR5,DATX8 4 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xB00+0x60)++0x03 line.long 0x00 "DX4BDLR6,DATX8 4 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xB00+0x80)++0x17 line.long 0x00 "DX4LCDLR0,DATX8 4 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX4LCDLR1,DATX8 4 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX4LCDLR2,DATX8 4 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX4LCDLR3,DATX8 4 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX4LCDLR4,DATX8 4 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX4LCDLR5,DATX8 4 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" rgroup.long (0xB00+0xA0)++0x07 line.long 0x00 "DX4MDLR0,DATX8 4 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX4MDLR1,DATX8 4 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" rgroup.long (0xB00+0xC0)++0x03 line.long 0x00 "DX4GTR0,DATX8 4 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0xB00+0xD0)++0x1F line.long 0x00 "DX4RSR0,DATX8 4 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX4RSR1,DATX8 4 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX4RSR2,DATX8 4 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX4RSR3,DATX8 4 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX4GSR0,DATX8 4 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX4GSR1,DATX8 4 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX4GSR2,DATX8 4 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX4GSR3,DATX8 4 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" rgroup.long 0xC00++0x1F line.long 0x00 "DX5GCR0,DATX8 5 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX5GCR1,DATX8 5 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX5GCR2,DATX8 5 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX5GCR3,DATX8 5 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX5GCR4,DATX8 5 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX5GCR5,DATX8 5 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX5GCR6,DATX8 5 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX5GCR7,DATX8 5 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" rgroup.long (0xC00+0x28)++0x07 line.long 0x00 "DX5DQMAP0,DATX8 5 DQ/DM Mapping Register 0" bitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW5DQMAP1,DATX8 5 DQ/DM Mapping Register 1" bitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0xC00+0x40)++0x0B line.long 0x00 "DX5BDLR0,DATX8 5 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX5BDLR1,DATX8 5 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX5BDLR2,DATX8 5 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xC00+0x50)++0x0B line.long 0x00 "DX5BDLR3,DATX8 5 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX5BDLR4,DATX8 5 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX5BDLR5,DATX8 5 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xC00+0x60)++0x03 line.long 0x00 "DX5BDLR6,DATX8 5 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xC00+0x80)++0x17 line.long 0x00 "DX5LCDLR0,DATX8 5 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX5LCDLR1,DATX8 5 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX5LCDLR2,DATX8 5 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX5LCDLR3,DATX8 5 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX5LCDLR4,DATX8 5 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX5LCDLR5,DATX8 5 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" rgroup.long (0xC00+0xA0)++0x07 line.long 0x00 "DX5MDLR0,DATX8 5 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX5MDLR1,DATX8 5 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" rgroup.long (0xC00+0xC0)++0x03 line.long 0x00 "DX5GTR0,DATX8 5 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0xC00+0xD0)++0x1F line.long 0x00 "DX5RSR0,DATX8 5 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX5RSR1,DATX8 5 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX5RSR2,DATX8 5 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX5RSR3,DATX8 5 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX5GSR0,DATX8 5 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX5GSR1,DATX8 5 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX5GSR2,DATX8 5 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX5GSR3,DATX8 5 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" rgroup.long 0xD00++0x1F line.long 0x00 "DX6GCR0,DATX8 6 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX6GCR1,DATX8 6 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX6GCR2,DATX8 6 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX6GCR3,DATX8 6 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX6GCR4,DATX8 6 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX6GCR5,DATX8 6 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX6GCR6,DATX8 6 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX6GCR7,DATX8 6 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" rgroup.long (0xD00+0x28)++0x07 line.long 0x00 "DX6DQMAP0,DATX8 6 DQ/DM Mapping Register 0" bitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW6DQMAP1,DATX8 6 DQ/DM Mapping Register 1" bitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0xD00+0x40)++0x0B line.long 0x00 "DX6BDLR0,DATX8 6 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX6BDLR1,DATX8 6 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX6BDLR2,DATX8 6 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xD00+0x50)++0x0B line.long 0x00 "DX6BDLR3,DATX8 6 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX6BDLR4,DATX8 6 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX6BDLR5,DATX8 6 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xD00+0x60)++0x03 line.long 0x00 "DX6BDLR6,DATX8 6 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xD00+0x80)++0x17 line.long 0x00 "DX6LCDLR0,DATX8 6 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX6LCDLR1,DATX8 6 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX6LCDLR2,DATX8 6 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX6LCDLR3,DATX8 6 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX6LCDLR4,DATX8 6 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX6LCDLR5,DATX8 6 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" rgroup.long (0xD00+0xA0)++0x07 line.long 0x00 "DX6MDLR0,DATX8 6 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX6MDLR1,DATX8 6 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" rgroup.long (0xD00+0xC0)++0x03 line.long 0x00 "DX6GTR0,DATX8 6 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0xD00+0xD0)++0x1F line.long 0x00 "DX6RSR0,DATX8 6 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX6RSR1,DATX8 6 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX6RSR2,DATX8 6 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX6RSR3,DATX8 6 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX6GSR0,DATX8 6 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX6GSR1,DATX8 6 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX6GSR2,DATX8 6 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX6GSR3,DATX8 6 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" rgroup.long 0xE00++0x1F line.long 0x00 "DX7GCR0,DATX8 7 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX7GCR1,DATX8 7 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX7GCR2,DATX8 7 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX7GCR3,DATX8 7 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX7GCR4,DATX8 7 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX7GCR5,DATX8 7 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX7GCR6,DATX8 7 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX7GCR7,DATX8 7 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" rgroup.long (0xE00+0x28)++0x07 line.long 0x00 "DX7DQMAP0,DATX8 7 DQ/DM Mapping Register 0" bitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW7DQMAP1,DATX8 7 DQ/DM Mapping Register 1" bitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0xE00+0x40)++0x0B line.long 0x00 "DX7BDLR0,DATX8 7 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX7BDLR1,DATX8 7 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX7BDLR2,DATX8 7 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xE00+0x50)++0x0B line.long 0x00 "DX7BDLR3,DATX8 7 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX7BDLR4,DATX8 7 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX7BDLR5,DATX8 7 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xE00+0x60)++0x03 line.long 0x00 "DX7BDLR6,DATX8 7 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xE00+0x80)++0x17 line.long 0x00 "DX7LCDLR0,DATX8 7 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX7LCDLR1,DATX8 7 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX7LCDLR2,DATX8 7 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX7LCDLR3,DATX8 7 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX7LCDLR4,DATX8 7 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX7LCDLR5,DATX8 7 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" rgroup.long (0xE00+0xA0)++0x07 line.long 0x00 "DX7MDLR0,DATX8 7 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX7MDLR1,DATX8 7 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" rgroup.long (0xE00+0xC0)++0x03 line.long 0x00 "DX7GTR0,DATX8 7 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0xE00+0xD0)++0x1F line.long 0x00 "DX7RSR0,DATX8 7 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX7RSR1,DATX8 7 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX7RSR2,DATX8 7 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX7RSR3,DATX8 7 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX7GSR0,DATX8 7 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX7GSR1,DATX8 7 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX7GSR2,DATX8 7 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX7GSR3,DATX8 7 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" rgroup.long 0xF00++0x1F line.long 0x00 "DX8GCR0,DATX8 8 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX8GCR1,DATX8 8 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX8GCR2,DATX8 8 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX8GCR3,DATX8 8 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX8GCR4,DATX8 8 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX8GCR5,DATX8 8 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX8GCR6,DATX8 8 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX8GCR7,DATX8 8 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" rgroup.long (0xF00+0x28)++0x07 line.long 0x00 "DX8DQMAP0,DATX8 8 DQ/DM Mapping Register 0" bitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW8DQMAP1,DATX8 8 DQ/DM Mapping Register 1" bitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0xF00+0x40)++0x0B line.long 0x00 "DX8BDLR0,DATX8 8 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX8BDLR1,DATX8 8 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX8BDLR2,DATX8 8 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xF00+0x50)++0x0B line.long 0x00 "DX8BDLR3,DATX8 8 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX8BDLR4,DATX8 8 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX8BDLR5,DATX8 8 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xF00+0x60)++0x03 line.long 0x00 "DX8BDLR6,DATX8 8 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xF00+0x80)++0x17 line.long 0x00 "DX8LCDLR0,DATX8 8 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX8LCDLR1,DATX8 8 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX8LCDLR2,DATX8 8 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX8LCDLR3,DATX8 8 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX8LCDLR4,DATX8 8 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX8LCDLR5,DATX8 8 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" rgroup.long (0xF00+0xA0)++0x07 line.long 0x00 "DX8MDLR0,DATX8 8 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX8MDLR1,DATX8 8 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" rgroup.long (0xF00+0xC0)++0x03 line.long 0x00 "DX8GTR0,DATX8 8 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0xF00+0xD0)++0x1F line.long 0x00 "DX8RSR0,DATX8 8 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX8RSR1,DATX8 8 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX8RSR2,DATX8 8 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX8RSR3,DATX8 8 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX8GSR0,DATX8 8 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX8GSR1,DATX8 8 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX8GSR2,DATX8 8 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX8GSR3,DATX8 8 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" newline group.long 0x1400++0x1F line.long 0x00 "DX8SL0OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode write-data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode write-leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL0PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL0PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL0PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL0PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL0PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL0PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL0DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path rise-to-rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path rise-to-rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x1400+0x24)++0x0F line.long 0x00 "DX8SL0DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL0DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL0DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during postamble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during preamble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL0IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" group.long 0x1440++0x1F line.long 0x00 "DX8SL1OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode write-data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode write-leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL1PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL1PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL1PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL1PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL1PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL1PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL1DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path rise-to-rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path rise-to-rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x1440+0x24)++0x0F line.long 0x00 "DX8SL1DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL1DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL1DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during postamble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during preamble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL1IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" group.long 0x1480++0x1F line.long 0x00 "DX8SL2OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode write-data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode write-leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL2PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL2PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL2PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL2PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL2PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL2PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL2DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path rise-to-rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path rise-to-rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x1480+0x24)++0x0F line.long 0x00 "DX8SL2DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL2DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL2DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during postamble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during preamble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL2IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" rgroup.long 0x14C0++0x1F line.long 0x00 "DX8SL3OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode Write-Data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode Write-Leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL3PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable ATOEN" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL3PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL3PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL3PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL3PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL3PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL3DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0x14C0+0x24)++0x0F line.long 0x00 "DX8SL3DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL3DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL3DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during Post-amble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during Pre-amble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL3IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" rgroup.long 0x1500++0x1F line.long 0x00 "DX8SL4OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode Write-Data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode Write-Leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL4PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable ATOEN" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL4PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL4PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL4PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL4PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL4PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL4DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0x1500+0x24)++0x0F line.long 0x00 "DX8SL4DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL4DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL4DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during Post-amble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during Pre-amble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL4IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" rgroup.long 0x1540++0x1F line.long 0x00 "DX8SL5OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode Write-Data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode Write-Leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL5PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable ATOEN" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL5PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL5PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL5PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL5PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL5PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL5DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0x1540+0x24)++0x0F line.long 0x00 "DX8SL5DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL5DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL5DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during Post-amble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during Pre-amble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL5IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" rgroup.long 0x1580++0x1F line.long 0x00 "DX8SL6OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode Write-Data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode Write-Leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL6PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable ATOEN" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL6PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL6PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL6PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL6PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL6PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL6DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0x1580+0x24)++0x0F line.long 0x00 "DX8SL6DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL6DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL6DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during Post-amble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during Pre-amble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL6IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" rgroup.long 0x15C0++0x1F line.long 0x00 "DX8SL7OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode Write-Data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode Write-Leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL7PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable ATOEN" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL7PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL7PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL7PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL7PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL7PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL7DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0x15C0+0x24)++0x0F line.long 0x00 "DX8SL7DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL7DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL7DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during Post-amble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during Pre-amble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL7IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" rgroup.long 0x1600++0x1F line.long 0x00 "DX8SL8OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode Write-Data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode Write-Leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL8PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable ATOEN" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL8PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL8PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL8PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL8PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL8PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL8DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0x1600+0x24)++0x0F line.long 0x00 "DX8SL8DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL8DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL8DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during Post-amble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during Pre-amble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL8IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" wgroup.long 0x17C0++0x1F line.long 0x00 "DX8SLBOSC,DATX8 0-8 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode write-data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode write-leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SLBPLLCR0,DAXT8 0-8 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable ATOEN" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SLBPLLCR1,DAXT8 0-8 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypassed,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SLBPLLCR2,DAXT8 0-8 PLL Control Register 2" line.long 0x10 "DX8SLBPLLCR3,DAXT8 0-8 PLL Control Register 3" line.long 0x14 "DX8SLBPLLCR4,DAXT8 0-8 PLL Control Register 4" line.long 0x18 "DX8SLBPLLCR5,DAXT8 0-8 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SLBDQSCTL,DATX8 0-8 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path rise-to-rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path rise-to-rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS# resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.long 0x17E4++0x0F line.long 0x00 "DX8SLBDDLCTL,DATX8 0-8 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SLBDXCTL1,DATX8 0-8 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SLBDXCTL2,DATX8 0-8 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during postamble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during preamble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "No bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No reset,Reset" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SLBIOCR,DATX8 0-8 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" width 0x0B tree.end tree "DDRC0_2 (DDR Controller)" base ad:0x5C100000 width 18. group.long 0x00++0x03 line.long 0x00 "MSTR,Master Register" bitfld.long 0x00 30.--31. " DEVICE_CONFIG ,Indicates the configuration of the device used in the system" "x4,x8,x16,x32" bitfld.long 0x00 29. " FREQUENCY_MODE ,Choose which registers are used" "Original,Shadow" newline bitfld.long 0x00 24.--25. " ACTIVE_RANKS ,Only present for multi-rank configurations" ",One rank,,Two rank" bitfld.long 0x00 22. " FREQUENCY_RATIO ,Selects the frequency ratio" "1:2 mode,1:1 mode" newline bitfld.long 0x00 16.--19. " BURST_RDWR ,Controls the burst size used to access the SDRAM" ",2,4,,8,,,,16,?..." bitfld.long 0x00 15. " DLL_OFF_MODE ,Indicates whether the DDRC and DRAM have to be put in DLL-off mode" "On mode,Off mode" newline bitfld.long 0x00 12.--13. " DATA_BUS_WIDTH ,Selects proportion of DQ bus width that is used by the SDRAM" "Full,Half,Quarter,?..." bitfld.long 0x00 11. " GEARDOWN_MODE ,DRAM mode" "Normal,Geardown" newline bitfld.long 0x00 10. " EN_2T_TIMING_MODE ,Enable 2T timing" "Disabled,Enabled" bitfld.long 0x00 9. " BURSTCHOP ,Burst-chop in DDR3/DDR4" "Disabled,Enabled" newline bitfld.long 0x00 5. " LPDDR4 ,Select LPDDR4 SDRAM" "Non-LPDDR4,LPDDR4" bitfld.long 0x00 3. " LPDDR3 ,Select LPDDR3 SDRAM" "Non-LPDDR3,LPDDR3" newline bitfld.long 0x00 2. " LPDDR2 ,Select LPDDR2 SDRAM" "Non-LPDDR2,LPDDR2" bitfld.long 0x00 0. " DDR3 ,Select DDR3 SDRAM" "Non-DDR3,DDR3" if (((per.l(ad:0x5C100000))&0x20)==0x20) rgroup.long 0x04++0x03 line.long 0x00 "STAT,Operating Mode Status Register" bitfld.long 0x00 8.--9. " SELFREF_STATE ,Self refresh state" "No self refresh,Self refresh 1,Self refresh power down,Self refresh" bitfld.long 0x00 4.--5. " SELFREF_TYPE ,SR-powerdown type" "Not in SR-powerdown,,Caused not only by automatic SR control,Caused only by automatic SR control" newline bitfld.long 0x00 0.--2. " OPERATING_MODE ,Operating mode" "Init,Normal,Power-down,Self refresh power-down,?..." elif (((per.l(ad:0x5C100000))&0x10)==0x10) rgroup.long 0x04++0x03 line.long 0x00 "STAT,Operating Mode Status Register" bitfld.long 0x00 8.--9. " SELFREF_STATE ,Self refresh state" "No self refresh,Self refresh 1,Self refresh power down,Self refresh" bitfld.long 0x00 4.--5. " SELFREF_TYPE ,Self refresh type" "Not in self refresh,,Caused not only by automatic SR control,Caused only by automatic SR control" newline bitfld.long 0x00 0.--2. " OPERATING_MODE ,Operating mode" "Init,Normal,Power-down,Self refresh,Deep power-down,Deep power-down,Deep power-down,Deep power-down" else rgroup.long 0x04++0x03 line.long 0x00 "STAT,Operating Mode Status Register" bitfld.long 0x00 8.--9. " SELFREF_STATE ,Self refresh state" "No self refresh,Self refresh 1,Self refresh power down,Self refresh" bitfld.long 0x00 4.--5. " SELFREF_TYPE ,Self refresh type" "Not in self refresh,,Caused not only by automatic SR control,Caused only by automatic SR control" newline bitfld.long 0x00 0.--1. " OPERATING_MODE ,Operating mode" "Init,Normal,Power-down,Self refresh" endif group.long 0x08++0x0F line.long 0x00 "MSTR1,Operating Mode Status Register 1" bitfld.long 0x00 16. " ALT_ADDRMAP_EN ,Enable alternative address map" "Disabled,Enabled" bitfld.long 0x00 1. " RANK_TMGREG_SEL[1] ,Indicates which register set is used for each rank" "Disabled,Enabled" newline bitfld.long 0x00 0. " [0] ,Indicates which register set is used for each rank" "Disabled,Enabled" line.long 0x04 "MRCTRL3,Operating Mode Status Register 3" bitfld.long 0x04 0.--1. " MR_RANK_SEL ,Controls which rank is accessed by MRCTRL0.mr_wr" "0,1,2,3" line.long 0x08 "MRCTRL0,Mode Register Read/Write Control Register 0" bitfld.long 0x08 31. " MR_WR ,Triggers a mode register read or write operation" "Not Triggered,Triggered" bitfld.long 0x08 30. " PBA_MODE ,Indicates whether PBA access is executed" "Not executed,Executed" newline bitfld.long 0x08 12.--15. " MR_ADDR ,Address of the mode register that is to be written to" "MR0,MR1,MR2,MR3,MR4,MR5,MR6,MR7,?..." bitfld.long 0x08 4.--5. " MR_RANK ,Controls which ranks are accessed by MRCTRL0.MR_WR" "0,1,2,3" newline bitfld.long 0x08 3. " SW_INIT_INT ,Indicates whether Software intervention is allowed" "Not allowed,Allowed" bitfld.long 0x08 2. " PDA_EN ,Indicates whether the mode register operation is MRS in PDA mode" "MRS,MRS in per DRAM addressability" newline bitfld.long 0x08 1. " MPR_EN ,Indicates whether the mode register operation is MRS or WR/RD for MPR" "MRS,WR/RD for MPR" bitfld.long 0x08 0. " MR_TYPE ,Indicates whether the mode register operation is read or write" "Write,Read" line.long 0x0C "MRCTRL1,Mode Register Read/Write Control Register 1" hexmask.long.tbyte 0x0C 0.--17. 1. " MR_DATA ,Mode register write data" rgroup.long 0x18++0x03 line.long 0x00 "MRSTAT,Mode Register Read/Write Status Register" bitfld.long 0x00 8. " PDA_DONE ,The SoC core may initiate a MR write operation in PDA/PBA mod" "In progress,Completed" bitfld.long 0x00 0. " MR_WR_BUSY ,The SoC core may initiate a MR write operation" "SoC core can initiate write operation,Write operation in progress" group.long 0x1C++0x03 line.long 0x00 "MRCTRL2,Mode Register Read/Write Control Register 2" if (((per.l(ad:0x5C100000))&0x20)==0x20) group.long 0x20++0x07 line.long 0x00 "DERATEEN,Temperature Derate Enable Register" bitfld.long 0x00 8.--9. " RC_DERATE_VALUE ,Derate value of tRC for LPDDR4" "+1,+2,+3,+4" bitfld.long 0x00 4.--7. " DERATE_BYTE ,Indicates which byte of the MRR data is used for derating" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1. " DERATE_VALUE ,Derate value" "+1,+2" bitfld.long 0x00 0. " DERATE_ENABLE ,Enables derating" "Disabled,Enabled" line.long 0x04 "DERATEINT,Temperature Derate Interval Register" else hgroup.long 0x20++0x03 hide.long 0x00 "DERATEEN,Temperature Derate Enable Register" hgroup.long 0x24++0x03 hide.long 0x00 "DERATEINT,Temperature Derate Interval Register" endif group.long 0x30++0x0B line.long 0x00 "PWRCTL,Low Power Control Register" bitfld.long 0x00 6. " STAY_IN_SELFREF ,Transition from Self refresh state" "Allow,Prohibit" bitfld.long 0x00 5. " SELFREF_SW ,Software entry transition to/from Self-refresh" "Exited,Entered" newline bitfld.long 0x00 4. " MPSM_EN ,DDRC maximum power saving mode" "Disabled,Enabled" bitfld.long 0x00 3. " EN_DFI_DRAM_CLK_DISABLE ,Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM" "No,Yes" newline bitfld.long 0x00 2. " DEEPPOWERDOWN_EN ,Enable for deep power-down" "Disabled,Enabled" bitfld.long 0x00 1. " POWERDOWN_EN ,Enable for power-down" "Disabled,Enabled" newline bitfld.long 0x00 0. " SELFREF_EN ,Enable for self refresh" "Disabled,Enabled" line.long 0x04 "PWRTMG,Low Power Timing Register" hexmask.long.byte 0x04 16.--23. 1. " SELFREF_TO_X32 ,SELFREF_TO_X32" hexmask.long.byte 0x04 8.--15. 1. " T_DPD_X4096 ,Minimum deep power-down time" newline bitfld.long 0x04 0.--4. " POWERDOWN_TO_X32 ,After this many clocks of NOP or deselect the DDRC automatically puts the SDRAM into power-down" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "HWLPCTL,Hardware Low Power Control Register" hexmask.long.word 0x08 16.--27. 1. " HW_LP_IDLE_X32 ,Hardware idle period" bitfld.long 0x08 1. " HW_LP_EXIT_IDLE_EN ,Enable for exit from the automatic clock stop automatic power down or automatic self-refresh modes" "Disabled,Enabled" newline bitfld.long 0x08 0. " HW_LP_EN ,Enable for hardware low power interface" "Disabled,Enabled" if (((per.l(ad:0x5C100000))&0x20)==0x20) group.long 0x50++0x03 line.long 0x00 "RFSHCTL0,Refresh Control Register 0" bitfld.long 0x00 20.--23. " REFRESH_MARGIN ,Threshold value in number of clock cycles before the critical refresh or page timer expires" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--16. " REFRESH_TO_X32 ,Speculative refreshes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4.--8. " REFRESH_BURST ,Number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute" "1 refresh,2 refresh,3 refresh,4 refresh,5 refresh,6 refresh,7 refresh,8 refresh,9 refresh,10 refresh,11 refresh,12 refresh,13 refresh,14 refresh,15 refresh,16 refresh,17 refresh,18 refresh,19 refresh,20 refresh,21 refresh,22 refresh,23 refresh,24 refresh,25 refresh,26 refresh,27 refresh,28 refresh,29 refresh,30 refresh,31 refresh,32 refresh" bitfld.long 0x00 2. " PER_BANK_REFRESH ,Allows traffic to flow to other banks" "All bank refresh,Per bank refresh" else group.long 0x50++0x03 line.long 0x00 "RFSHCTL0,Refresh Control Register 0" bitfld.long 0x00 20.--23. " REFRESH_MARGIN ,Threshold value in number of clock cycles before the critical refresh or page timer expires" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--16. " REFRESH_TO_X32 ,Speculative refreshes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4.--8. " REFRESH_BURST ,Number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute" "1 refresh,2 refresh,3 refresh,4 refresh,5 refresh,6 refresh,7 refresh,8 refresh,9 refresh,10 refresh,11 refresh,12 refresh,13 refresh,14 refresh,15 refresh,16 refresh,17 refresh,18 refresh,19 refresh,20 refresh,21 refresh,22 refresh,23 refresh,24 refresh,25 refresh,26 refresh,27 refresh,28 refresh,29 refresh,30 refresh,31 refresh,32 refresh" endif group.long 0x54++0x03 line.long 0x00 "RFSHCTL1,Refresh Control Register 1" hexmask.long.word 0x00 16.--27. 1. " REFRESH_TIMER1_START_VALUE_X32 ,Refresh timer start for rank 1" hexmask.long.word 0x00 0.--11. 1. " REFRESH_TIMER0_START_VALUE_X32 ,Refresh timer start for rank 0" group.long 0x60++0x07 line.long 0x00 "RFSHCTL3,Refresh Control Register 3" bitfld.long 0x00 4.--6. " REFRESH_MODE ,Fine granularity refresh mode" "Fixed,Fixed 2x,Fixed x4,,,Enabled on the fly x2,Enabled on the fly x4,?..." bitfld.long 0x00 1. " REFRESH_UPDATE_LEVEL ,Indicates that the refresh Register(S) have been updated" "0,1" newline bitfld.long 0x00 0. " DIS_AUTO_REFRESH ,Disables auto-refresh generated by the DDRC" "No,Yes" line.long 0x04 "RFSHTMG,Refresh Timing Register" hexmask.long.word 0x04 16.--27. 1. " T_RFC_NOM_X32 ,Average time interval between refreshes per rank" hexmask.long.word 0x04 0.--9. 1. " T_RFC_MIN ,Minimum time from refresh to refresh or activate" group.long 0xD0++0x03 line.long 0x00 "INIT0,SDRAM Initialization Register 0" bitfld.long 0x00 30.--31. " SKIP_DRAM_INIT ,If lower bit is enabled the SDRAM initialization routine is skipped" "Run after power-up,Skipped after power-up,Run after power-up,Skipped after power-up" hexmask.long.word 0x00 16.--25. 1. " POST_CKE_X1024 ,Cycles to wait after driving CKE high to start the SDRAM initialization sequence" newline hexmask.long.word 0x00 0.--11. 1. " PRE_CKE_X1024 ,Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence" if ((((per.l(ad:0x5C100000))&0x20)==0x20)||(((per.l(ad:0x5C100000))&0x01)==0x01)) group.long 0xD4++0x03 line.long 0x00 "INIT1,SDRAM Initialization Register 1" hexmask.long.word 0x00 16.--24. 1. " DRAM_RSTN_X1024 ,Number of cycles to assert SDRAM reset signal during init sequence" bitfld.long 0x00 0.--3. " PRE_OCD_X32 ,Wait period before driving the OCD complete command to SDRAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xD4++0x03 line.long 0x00 "INIT1,SDRAM Initialization Register 1" bitfld.long 0x00 0.--3. " PRE_OCD_X32 ,Wait period before driving the OCD complete command to SDRAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hgroup.long 0xD8++0x03 hide.long 0x00 "INIT2,SDRAM Initialization Register 2" group.long 0xDC++0x07 line.long 0x00 "INIT3,SDRAM Initialization Register 3" hexmask.long.word 0x00 16.--31. 1. " MR ,Value write to MR register" hexmask.long.word 0x00 0.--15. 1. " EMR ,Value write to EMR register" line.long 0x04 "INIT4,SDRAM Initialization Register 4" hexmask.long.word 0x04 16.--31. 1. " EMR2 ,Value write to EMR2 register" hexmask.long.word 0x04 0.--15. 1. " EMR3 ,Value write to EMR3 register" if (((per.l(ad:0x5C100000))&0x01)==0x01) group.long 0xE4++0x03 line.long 0x00 "INIT5,SDRAM Initialization Register 5" hexmask.long.byte 0x00 16.--23. 1. " DEV_ZQINIT_X32 ,ZQ initial calibration" hexmask.long.word 0x00 0.--9. 1. " MAX_AUTO_INIT_X_1024 ,Maximum duration of the auto initialization tINIT5" else hgroup.long 0xE4++0x03 hide.long 0x00 "INIT5,SDRAM Initialization Register 5" endif hgroup.long 0xE8++0x03 hide.long 0x00 "INIT6,SDRAM Initialization Register 6" hgroup.long 0xEC++0x03 hide.long 0x00 "INIT7,SDRAM Initialization Register 7" if (((per.l(ad:0x5C100000))&0x10)==0x10) group.long 0xF0++0x03 line.long 0x00 "DIMMCTL,DIMM Control Register" bitfld.long 0x00 6. " LRDIMM_BCOM_CMD_PROT ,Protects the timing restrictions" "0,1" bitfld.long 0x00 5. " DIMM_DIS_BG_MIRRORING ,Disabling address mirroring for BG bits" "Swapped,Not swapped" newline bitfld.long 0x00 4. " MRS_BG1_EN ,Enable for BG1 bit of MRS command" "Disabled,Enabled" bitfld.long 0x00 3. " MRS_A17_EN ,Enable for A17 bit of MRS command" "Disabled,Enabled" newline bitfld.long 0x00 2. " DIMM_OUTPUT_INV_EN ,Output inversion enable" "Disabled,Enabled" bitfld.long 0x00 1. " DIMM_ADDR_MIRR_EN ,Address mirroring enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DIMM_STAGGER_CS_EN ,Staggering enable for multi-rank accesses" "Disabled,Enabled" elif (((per.l(ad:0x5C100000))&0x20)==0x20) group.long 0xF0++0x03 line.long 0x00 "DIMMCTL,DIMM Control Register" bitfld.long 0x00 6. " LRDIMM_BCOM_CMD_PROT ,Protects the timing restrictions" "0,1" bitfld.long 0x00 5. " DIMM_DIS_BG_MIRRORING ,Disabling address mirroring for BG bits" "Swapped,Not swapped" newline bitfld.long 0x00 4. " MRS_BG1_EN ,Enable for BG1 bit of MRS command" "Disabled,Enabled" bitfld.long 0x00 3. " MRS_A17_EN ,Enable for A17 bit of MRS command" "Disabled,Enabled" newline bitfld.long 0x00 2. " DIMM_OUTPUT_INV_EN ,Output inversion enable" "Disabled,Enabled" else group.long 0xF0++0x03 line.long 0x00 "DIMMCTL,DIMM Control Register" bitfld.long 0x00 6. " LRDIMM_BCOM_CMD_PROT ,Protects the timing restrictions" "0,1" bitfld.long 0x00 5. " DIMM_DIS_BG_MIRRORING ,Disabling address mirroring for BG bits" "Swapped,Not swapped" newline bitfld.long 0x00 4. " MRS_BG1_EN ,Enable for BG1 bit of MRS command" "Disabled,Enabled" bitfld.long 0x00 3. " MRS_A17_EN ,Enable for A17 bit of MRS command" "Disabled,Enabled" endif group.long 0xF4++0x03 line.long 0x00 "RANKCTL,Rank Control Register" bitfld.long 0x00 8.--11. " DIFF_RANK_WR_GAP ,Only present for multi-rank configurations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DIFF_RANK_RD_GAP ,Only present for multi-rank configurations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " MAX_RANK_RD ,Only present for multi-rank configurations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x100++0x0B line.long 0x00 "DRAMTMG0,SDRAM Timing Register 0" hexmask.long.byte 0x00 24.--30. 1. " WR2PRE ,Minimum time between write and precharge to same bank" bitfld.long 0x00 16.--21. " T_FAW ,TFAW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x00 8.--14. 1. " T_RAS_MAX ,Maximum time between activate and precharge to the same bank" bitfld.long 0x00 0.--5. " T_RAS_MIN ,Minimum time between activate and precharge to the same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DRAMTMG1,SDRAM Timing Register 1" bitfld.long 0x04 16.--20. " T_XP ,Minimum time after power-down exit to any operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--13. " RD2PRE ,Minimum time from read to precharge of same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x04 0.--6. 1. " T_RC ,Minimum time between activates to same bank" line.long 0x08 "DRAMTMG2,SDRAM Timing Register 2" bitfld.long 0x08 24.--29. " WRITE_LATENCY ,Time from write command to write data on SDRAM interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " READ_LATENCY ,Time from read command to read data on SDRAM interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " RD2WR ,Minimum time from read command to write command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " WR2RD ,Minimum time from write command to read command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0x5C100000))&0x20)==0x20) group.long 0x10C++0x03 line.long 0x00 "DRAMTMG3,SDRAM Timing Register 3" hexmask.long.word 0x00 20.--29. 1. " T_MRW ,Time to wait after a mode register write or read" bitfld.long 0x00 12.--17. " T_MRD ,Cycles between loadmode commands" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.l(ad:0x5C100000))&0x01)==0x01) group.long 0x10C++0x03 line.long 0x00 "DRAMTMG3,SDRAM Timing Register 3" bitfld.long 0x00 12.--17. " T_MRD ,Cycles between loadmode commands" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 0.--9. 1. " T_MOD ,Cycles between loadmode command and following non-load mode command" else group.long 0x10C++0x03 line.long 0x00 "DRAMTMG3,SDRAM Timing Register 3" bitfld.long 0x00 12.--17. " T_MRD ,Cycles between loadmode commands" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x110++0x07 line.long 0x00 "DRAMTMG4,SDRAM Timing Register 4" bitfld.long 0x00 24.--28. " T_RCD ,Minimum time from activate to read or write command to same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--19. " T_CCD ,Minimum time between two reads or two writes for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " T_RRD ,Minimum time between activates from bank a to bank b for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " T_RP ,Minimum time from precharge to activate of same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DRAMTMG5,SDRAM Timing Register5" bitfld.long 0x04 24.--27. " T_CKSRX ,Time before self refresh exit that CK is maintained as a valid clock before issuing SRX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " T_CKSRE ,Time after self refresh down entry that CK is maintained as a valid clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--13. " T_CKESR ,Minimum CKE low width for self refresh entry to exit timing in memory clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--4. " T_CKE ,Minimum number of cycles of CKE HIGH / LOW during power-down and self refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x5C100000))&0x20)==0x20) group.long 0x118++0x07 line.long 0x00 "DRAMTMG6,SDRAM Timing Register 6" bitfld.long 0x00 0.--3. " T_CKCSX ,Time before clock stop exit that CK is maintained as a valid clock before issuing clock stop exit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DRAMTMG7,SDRAM Timing Register 7" bitfld.long 0x04 8.--11. " T_CKPDE ,Time after power down entry that CK is maintained as a valid clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " T_CKPDX ,Time before power down exit that CK is maintained as a valid clock before issuing PDX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else hgroup.long 0x118++0x03 hide.long 0x00 "DRAMTMG6,SDRAM Timing Register 6" hgroup.long 0x11C++0x03 hide.long 0x00 "DRAMTMG7,SDRAM Timing Register 7" endif if (((per.l(ad:0x5C100000))&0x01)==0x01) group.long 0x120++0x03 line.long 0x00 "DRAMTMG8,SDRAM Timing Register 8" hexmask.long.byte 0x00 24.--30. 1. " T_XS_FAST_X32 ,Exit Self refresh to ZQC ZQCS and MRS" hexmask.long.byte 0x00 16.--22. 1. " T_XS_ABORT_X32 ,Exit self refresh to commands not requiring a locked DLL in self refresh abort" newline hexmask.long.byte 0x00 8.--14. 1. " T_XS_DLL_X32 ,Exit self refresh to commands requiring a locked DLL" hexmask.long.byte 0x00 0.--6. 1. " T_XS_X32 ,Exit self refresh to commands not requiring a locked DLL" else group.long 0x120++0x03 line.long 0x00 "DRAMTMG8,SDRAM Timing Register 8" hexmask.long.byte 0x00 24.--30. 1. " T_XS_FAST_X32 ,Exit self refresh to ZQCL ZQCS and MRS" hexmask.long.byte 0x00 16.--22. 1. " T_XS_ABORT_X32 ,Exit Self Refresh to commands not requiring a locked DLL in self refresh abort" endif hgroup.long 0x124++0x03 hide.long 0x00 "DRAMTMG9,SDRAM Timing Register 9" group.long 0x128++0x03 line.long 0x00 "DRAMTMG10,SDRAM Timing Register 10" bitfld.long 0x00 16.--20. " T_SYNC_GEAR ,Indicates the time between MRS command and the sync pulse time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " T_CMD_GEAR ,Sync pulse to first valid command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 2.--3. " T_GEAR_SETUP ,Geardown setup time" ",1,2,3" bitfld.long 0x00 0.--1. " T_GEAR_HOLD ,Geardown hold time" ",1,2,3" hgroup.long 0x12C++0x03 hide.long 0x00 "DRAMTMG11,SDRAM Timing Register 11" group.long 0x130++0x07 line.long 0x00 "DRAMTMG12,SDRAM Timing Register 12" bitfld.long 0x00 16.--17. " T_CMDCKE ,Delay from valid command to CKE input LOW" "0,1,2,3" bitfld.long 0x00 8.--11. " T_CKEHCMD ,Valid command requirement after CKE input HIGH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--4. " T_MRD_PDA ,This is the mode register set command cycle time in PDA mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DRAMTMG13,SDRAM Timing Register 13" hexmask.long.byte 0x04 24.--30. 1. " ODTLOFF ,This is the latency from CAS-2 command to tODToff reference" bitfld.long 0x04 16.--21. " T_CCD_MW ,This is the minimum time from write or masked write to masked write command for same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 0.--2. " T_PPD ,This is the minimum time from precharge to precharge command" "0,1,2,3,4,5,6,7" if (((per.l(ad:0x5C100000))&0x20)==0x20) group.long 0x138++0x03 line.long 0x00 "DRAMTMG14,SDRAM Timing Register 14" hexmask.long.word 0x00 0.--11. 1. " T_XSR ,Exit self refresh to any command" else hgroup.long 0x138++0x03 hide.long 0x00 "DRAMTMG14,SDRAM Timing Register 14" endif group.long 0x13C++0x03 line.long 0x00 "DRAMTMG15,SDRAM Timing Register 15" bitfld.long 0x00 31. " EN_DFI_LP_T_STAB ,Enable DFI tSTAB" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " T_STAB_X32 ,Stabilization time" group.long 0x180++0x03 line.long 0x00 "ZQCTL0,ZQ Control Register 0" bitfld.long 0x00 31. " DIS_AUTO_ZQ ,Disable auto ZQCS/MPC" "No,Yes" bitfld.long 0x00 30. " DIS_SRX_ZQCL ,Disable ZQCL/MPC" "No,Yes" newline bitfld.long 0x00 29. " ZQ_RESISTOR_SHARED ,ZQ resistor sharing" "Not shared,Shared" newline hexmask.long.word 0x00 16.--26. 1. " T_ZQ_LONG_NOP ,Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to SDRAM" hexmask.long.word 0x00 0.--9. 1. " T_ZQ_SHORT_NOP ,Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to SDRAM" if (((per.l(ad:0x5C100000))&0x20)==0x20) group.long 0x184++0x03 line.long 0x00 "ZQCTL1,ZQ Control Register 1" hexmask.long.word 0x00 20.--29. 1. " T_ZQ_RESET_NOP ,Number of cycles of NOP required after a ZQReset (ZQ calibration reset) command is issued to SDRAM" hexmask.long.tbyte 0x00 0.--19. 1. " T_ZQ_SHORT_INTERVAL_X1024 ,Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands" elif ((((per.l(ad:0x5C100000))&0x01)==0x01)) group.long 0x184++0x03 line.long 0x00 "ZQCTL1,ZQ Control Register 1" hexmask.long.tbyte 0x00 0.--19. 1. " T_ZQ_SHORT_INTERVAL_X1024 ,Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands" else hgroup.long 0x184++0x03 hide.long 0x00 "ZQCTL1,ZQ Control Register 1" endif if (((per.l(ad:0x5C100000))&0x20)==0x20) group.long 0x188++0x03 line.long 0x00 "ZQCTL2,ZQ Control Register 2" bitfld.long 0x00 0. " ZQ_RESET ,Setting this register bit to 1 triggers a ZQ Reset operation" "Not triggered,Triggered" else hgroup.long 0x188++0x03 hide.long 0x00 "ZQCTL2,ZQ Control Register 2" endif rgroup.long 0x18C++0x03 line.long 0x00 "ZQSTAT,ZQ Status Register" bitfld.long 0x00 0. " ZQ_RESET_BUSY ,ZQ reset operation initialization by soc core" "Possibility of initialization,In progress" group.long 0x190++0x1B line.long 0x00 "DFITMG0,DFI Timing Register 0" bitfld.long 0x00 24.--28. " DFI_T_CTRL_DELAY ,Specifies the number of DFI clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 23. " DFI_RDDATA_USE_SDR ,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values" "HDR,SDR" newline hexmask.long.byte 0x00 16.--22. 1. " DFI_RDDATA_USE_SDR ,Time from the assertion of a read command on the DFI interface to the assertion of the DFI_RDDATA_EN signal" bitfld.long 0x00 15. " DFI_WRDATA_USE_SDR ,Selects whether value in DFITMG0.DFI_TPHY_WRLAT is in terms of SDR or HDR clock cycles" "HDR,SDR" newline bitfld.long 0x00 8.--13. " DFI_TPHY_WRDATA ,Specifies the number of clock cycles between when DFI_WRDATA_EN is asserted to when the associated write data is driven on the dfi_wrdata signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DFI_TPHY_WRLAT ,Number of clocks from the write command to write data enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DFITMG1,DFI Timing Register 1" bitfld.long 0x04 28.--31. " DFI_T_CMD_LAT ,Specifies the number of DFI PHY clock cycles" "0,,,3,4,5,6,,8,?..." bitfld.long 0x04 24.--25. " DFI_T_PARIN_LAT ,Number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven" "0,1,2,3" newline bitfld.long 0x04 16.--20. " DFI_T_WRDATA_DELAY ,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " DFI_T_DRAM_CLK_DISABLE ,Number of DFI clock cycles from the assertion of the DFI_DRAM_CLK_DISABLE signal on the DFI until the clock to the DRAM memory devices at the PHY-DRAM boundary maintains a low value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--4. " DFI_T_DRAM_CLK_ENABLE ,Specifies the number of DFI clock cycles from the de-assertion of the DFI_DRAM_CLK_DISABLE signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "DFILPCFG0,DFI Low Power Configuration Register 0" bitfld.long 0x08 24.--28. " DFI_TLP_RESP ,DFI_TLP_RESP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 20.--23. " DFI_LP_WAKEUP_DPD ,Value in DFI clock cycles to drive on dfi_lp_wakeup signal" "16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,262144,Unlimited" newline bitfld.long 0x08 16. " DFI_LP_EN_DPD ,Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit" "Disabled,Enabled" bitfld.long 0x08 12.--15. " DFI_LP_WAKEUP_SR ,Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered" "16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,262144,Unlimited" newline bitfld.long 0x08 8. " DFI_LP_EN_SR ,Enables DFI low power interface handshaking during self refresh entry/exit" "Disabled,Enabled" bitfld.long 0x08 4.--7. " DFI_LP_WAKEUP_PD ,Value to drive on dfi_lp_wakeup signal when Power Down mode is entered" "16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,262144,Unlimited" newline bitfld.long 0x08 0. " DFI_LP_EN_PD ,Enables DFI low power interface handshaking during power down entry/exit" "Disabled,Enabled" line.long 0x0C "DFILPCFG1,DFI Low Power Configuration Register 1" bitfld.long 0x0C 4.--7. " DFI_LP_WAKEUP_MPSM ,Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "DFIUPD0,DFI Update Register 0" bitfld.long 0x10 31. " DIS_AUTO_CTRLUPD ,Automatic dfi_ctrlupd_req generation by the DDRC" "No,Yes" bitfld.long 0x10 30. " DIS_AUTO_CTRLUPD_SRX ,Auto ctrlupd request generation" "No,Yes" newline bitfld.long 0x10 29. " CTRLUPD_PRE_SRX ,Selects dfi_ctrlupd_req requirements at SRX" "After SRX,Before SRX" hexmask.long.word 0x10 16.--25. 1. " DFI_T_CTRLUP_MAX ,Specifies the maximum number of clock cycles that the dfi_ctrlupd_req signal can assert" newline hexmask.long.word 0x10 0.--9. 1. " DFI_T_CTRLUP_MIN ,Specifies the minimum number of clock cycles that the dfi_ctrlupd_req signal must be asserted" line.long 0x14 "DFIUPD1,DFI Update Register 1" hexmask.long.byte 0x14 16.--23. 1. " DFI_T_CTRLUPD_INTERVAL_MIN_X1024 ,The minimum amount of time between DDRC initiated DFI update requests" hexmask.long.byte 0x14 0.--7. 1. " DFI_T_CTRLUPD_INTERVAL_MAX_X1024 ,The maximum amount of time between DDRC initiated DFI update requests" line.long 0x18 "DFIUPD2,DFI Update Register 2" bitfld.long 0x18 31. " DFI_PHYUPD_EN ,Enables the support for acknowledging PHY- initiated updates" "Disabled,Enabled" if (((per.l(ad:0x5C100000))&0x20)==0x20) group.long 0x1B0++0x03 line.long 0x00 "DFIMISC,DFI Miscellaneous Control Register" bitfld.long 0x00 8.--12. " DFI_FREQUENCY ,Indicates the operating frequency of the system" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " DFI_INIT_START ,PHY init start request signal" "Not started,Started" newline bitfld.long 0x00 4. " CTL_IDLE_EN ,Enables support of ctl_idle signal" "Disabled,Enabled" bitfld.long 0x00 2. " DFI_DATA_CS_POLARITY ,Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals" "Low,High" newline bitfld.long 0x00 1. " PHY_DBI_MODE ,DBI implemented in DDRC or PHY" "DDRC,PHY" bitfld.long 0x00 0. " DFI_INIT_COMPLETE_EN ,PHY initialization complete enable signal" "Disabled,Enabled" else group.long 0x1B0++0x03 line.long 0x00 "DFIMISC,DFI Miscellaneous Control Register" bitfld.long 0x00 8.--12. " DFI_FREQUENCY ,Indicates the operating frequency of the system" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " DFI_INIT_START ,PHY init start request signal" "Not started,Started" newline bitfld.long 0x00 4. " CTL_IDLE_EN ,Enables support of ctl_idle signal" "Disabled,Enabled" bitfld.long 0x00 2. " DFI_DATA_CS_POLARITY ,Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals" "Low,High" newline bitfld.long 0x00 0. " DFI_INIT_COMPLETE_EN ,PHY initialization complete enable signal" "Disabled,Enabled" endif group.long 0x1B4++0x07 line.long 0x00 "DFITMG2,DFI Timing Register 2" hexmask.long.byte 0x00 8.--14. 1. " DFI_TPHY_RDCSLAT ,Number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted" bitfld.long 0x00 0.--5. " DFI_TPHY_WRCSLAT ,Number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DFITMG3,DFI Timing Register 3" bitfld.long 0x04 0.--4. " DFI_T_GEARDOWN_DELAY ,Delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x1BC++0x03 line.long 0x00 "DFISTAT,DFI Status Register" bitfld.long 0x00 1. " DFI_LP_ACK ,Stores the value of the dfi_lp_ack input to the controller" "0,1" bitfld.long 0x00 0. " DFI_INIT_COMPLETE ,The status flag register which announces when the DFI initialization has been completed" "Not completed,Completed" group.long 0x1C0++0x03 line.long 0x00 "DBICTL,DM/DBI Control Register" bitfld.long 0x00 2. " RD_DBI_EN ,Read DBI enable signal in DDRC" "Disabled,Enabled" bitfld.long 0x00 1. " WR_DBI_EN ,Write DBI enable signal in DDRC" "Disabled,Enabled" newline bitfld.long 0x00 0. " DM_EN ,DM enable signal in DDRC" "Disabled,Enabled" group.long 0x200++0x23 line.long 0x00 "ADDRMAP0,Address Map Register 0" bitfld.long 0x00 0.--4. " ADDRMAP_CS_BIT0 ,Selects the HIF address bit used as rank address bit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,,,31" line.long 0x04 "ADDRMAP1,Address Map Register 1" bitfld.long 0x04 16.--20. " ADDRMAP_BANK_B2 ,Selects the HIF address bit used as bank address bit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " ADDRMAP_BANK_B1 ,Selects the HIF address bits used as bank address bit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--4. " ADDRMAP_BANK_B0 ,Selects the HIF address bits used as bank address bit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "ADDRMAP2,Address Map Register 2" bitfld.long 0x08 24.--27. " ADDRMAP_COL_B5 ,Selects the HIF address bit used as column address bit 5" "0,1,2,3,4,5,6,7,,,,,,,,15" bitfld.long 0x08 16.--19. " ADDRMAP_COL_B4 ,Selects the HIF address bit used as column address bit 4" "0,1,2,3,4,5,6,7,,,,,,,,15" newline bitfld.long 0x08 8.--11. " ADDRMAP_COL_B3 ,Selects the HIF address bit used as column address bit 3" "0,1,2,3,4,5,6,7,?..." bitfld.long 0x08 0.--3. " ADDRMAP_COL_B2 ,Selects the HIF address bit used as column address bit 2" "0,1,2,3,4,5,6,7,?..." line.long 0x0C "ADDRMAP3,Address Map Register 3" bitfld.long 0x0C 24.--27. " ADDRMAP_COL_B9 ,Selects the HIF address bit used as column address bit 9" "0,1,2,3,4,5,6,7,,,,,,,,15" bitfld.long 0x0C 16.--19. " ADDRMAP_COL_B8 ,Selects the HIF address bit used as column address bit 8" "0,1,2,3,4,5,6,7,,,,,,,,15" newline bitfld.long 0x0C 8.--11. " ADDRMAP_COL_B7 ,Selects the HIF address bit used as column address bit 7" "0,1,2,3,4,5,6,7,,,,,,,,15" bitfld.long 0x0C 0.--3. " ADDRMAP_COL_B6 ,Selects the HIF address bit used as column address bit 6" "0,1,2,3,4,5,6,7,,,,,,,,15" line.long 0x10 "ADDRMAP4,Address Map Register 4" bitfld.long 0x10 8.--11. " ADDRMAP_COL_B11 ,Selects the HIF address bit used as column address bit 13" "0,1,2,3,4,5,6,7,,,,,,,,15" bitfld.long 0x10 0.--3. " ADDRMAP_COL_B10 ,Selects the HIF address bit used as column address bit 11" "0,1,2,3,4,5,6,7,,,,,,,,15" line.long 0x14 "ADDRMAP5,Address Map Register 5" bitfld.long 0x14 24.--27. " ADDRMAP_ROW_B11 ,Selects the HIF address bit used as row address bit 11" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" bitfld.long 0x14 16.--19. " ADDRMAP_ROW_B2_10 ,Selects the HIF address bit used as row address bit 2 to 10" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" newline bitfld.long 0x14 8.--11. " ADDRMAP_ROW_B1 ,Selects the HIF address bits used as row address bit 1" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x14 0.--3. " ADDRMAP_ROW_B0 ,Selects the HIF address bits used as row address bit 0" "0,1,2,3,4,5,6,7,8,9,10,11,?..." line.long 0x18 "ADDRMAP6,Address Map Register 6" bitfld.long 0x18 24.--27. " ADDRMAP_ROW_B15 ,Selects the HIF address bit used as row address bit 15" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" bitfld.long 0x18 16.--19. " ADDRMAP_ROW_B14 ,Selects the HIF address bit used as row address bit 14" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" newline bitfld.long 0x18 8.--11. " ADDRMAP_ROW_B13 ,Selects the HIF address bit used as row address bit 13" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" bitfld.long 0x18 0.--3. " ADDRMAP_ROW_B12 ,Selects the HIF address bit used as row address bit 12" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" line.long 0x1C "ADDRMAP7,Address Map Register 7" bitfld.long 0x1C 8.--11. " ADDRMAP_ROW_B17 ,Selects the HIF address bit used as row address bit 17" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" bitfld.long 0x1C 0.--3. " ADDRMAP_ROW_B16 ,Selects the HIF address bit used as row address bit 16" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" line.long 0x20 "ADDRMAP8,Address Map Register 8" bitfld.long 0x20 8.--13. " ADDRMAP_BG_B1 ,Selects the HIF address bits used as bank group address bit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,63" bitfld.long 0x20 0.--4. " ADDRMAP_BG_B0 ,Selects the HIF address bits used as bank group address bit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x5C100000+0x214))&0xF0000)==0xF0000) group.long 0x224++0x0B line.long 0x00 "ADDRMAP9,Address Map Register 9" bitfld.long 0x00 24.--27. " ADDRMAP_ROW_B5 ,Selects the HIF address bits used as row address bit 5" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x00 16.--19. " ADDRMAP_ROW_B4 ,Selects the HIF address bits used as row address bit 4" "0,1,2,3,4,5,6,7,8,9,10,11,?..." newline bitfld.long 0x00 8.--11. " ADDRMAP_ROW_B3 ,Selects the HIF address bits used as row address bit 3" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x00 0.--3. " ADDRMAP_ROW_B2 ,Selects the HIF address bits used as row address bit 2" "0,1,2,3,4,5,6,7,8,9,10,11,?..." line.long 0x04 "ADDRMAP10,Address Map Register 10" bitfld.long 0x04 24.--27. " ADDRMAP_ROW_B9 ,Selects the HIF address bits used as row address bit 9" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" bitfld.long 0x04 16.--19. " ADDRMAP_ROW_B8 ,Selects the HIF address bits used as row address bit 8" "0,1,2,3,4,5,6,7,8,9,10,11,?..." newline bitfld.long 0x04 8.--11. " ADDRMAP_ROW_B7 ,Selects the HIF address bits used as row address bit 7" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x04 0.--3. " ADDRMAP_ROW_B6 ,Selects the HIF address bits used as row address bit 6" "0,1,2,3,4,5,6,7,8,9,10,11,?..." line.long 0x08 "ADDRMAP11,Address Map Register 11" bitfld.long 0x08 0.--3. " ADDRMAP_ROW_B10 ,Selects the HIF address bits used as row address bit 10" "0,1,2,3,4,5,6,7,8,9,10,11,?..." else hgroup.long 0x224++0x03 hide.long 0x00 "ADDRMAP9,Address Map Register 9" hgroup.long 0x228++0x03 hide.long 0x00 "ADDRMAP10,Address Map Register 10" hgroup.long 0x230++0x03 hide.long 0x00 "ADDRMAP11,Address Map Register 11" endif group.long 0x240++0x07 line.long 0x00 "ODTCFG,ODT configuration register" bitfld.long 0x00 24.--27. " WR_ODT_HOLD ,DFI PHY clock cycles to hold ODT for a write command" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " WR_ODT_DELAY ,Delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--11. " RD_ODT_HOLD ,DFI PHY clock cycles to hold ODT for a read command" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--6. " RD_ODT_DELAY ,Delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "ODTMAP,ODT/Rank Map Register" bitfld.long 0x04 13. " RANK1_RD_ODT[1] ,Indicates bit next to the LSB must be turned on during a read from rank 1" "Not occurred,Occurred" bitfld.long 0x04 12. " [0] ,Indicates LSB must be turned on during a read from rank 1" "Not occurred,Occurred" newline bitfld.long 0x04 9. " RANK1_WR_ODT[1] ,Indicates bit next to the LSB must be turned on during a write to rank 1" "Not occurred,Occurred" bitfld.long 0x04 8. " [0] ,Indicates LSB must be turned on during a write to rank 1" "Not occurred,Occurred" newline bitfld.long 0x04 5. " RANK0_RD_ODT[1] ,Indicates bit next to the LSB must be turned on during a read from rank 0" "0,1" bitfld.long 0x04 4. " [0] ,Indicates LSB must be turned on during a read from rank 0" "0,1" newline bitfld.long 0x04 1. " RANK0_WR_ODT[1] ,Indicates bit next to the LSB must be turned on during a write to rank 0" "0,1" bitfld.long 0x04 0. " [0] ,Indicates LSB must be turned on during a write to rank 0" "0,1" group.long 0x250++0x03 line.long 0x00 "SCHED,Scheduler Control Register" hexmask.long.byte 0x00 24.--30. 1. " RDWR_IDLE_GAP ,When the preferred transaction store is empty for these many clock cycles switch to the alternate transaction store if it is non-empty" bitfld.long 0x00 8.--12. " LPR_NUM_ENTRIES ,Number of entries in the low priority transaction store" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 2. " PAGECLOSE ,Provides a midway between open and close page policies" "Open page policy,Close page policy" bitfld.long 0x00 1. " PREFER_WRITE ,Bank selector prefers writes over reads" "Reads over writes,Writes over reads" newline bitfld.long 0x00 0. " FORCE_LOW_PRI_N ,Active low signal" "Not forced,Forced" if (((per.l(ad:0x5C100000+0x250))&0x04)==0x04) group.long 0x254++0x03 line.long 0x00 "SCHED1,Scheduler Control Register 1" hexmask.long.byte 0x00 0.--7. 1. " PAGECLOSE_TIMER ,Pageclose timer" else hgroup.long 0x254++0x03 hide.long 0x00 "SCHED1,Scheduler Control Register 1" endif group.long 0x25C++0x03 line.long 0x00 "PERFHPR1,High Priority Read CAM Register 1" hexmask.long.byte 0x00 24.--31. 1. " HPR_XACT_RUN_LENGTH ,Number of transactions that are serviced once the HPR queue goes critical" hexmask.long.word 0x00 0.--15. 1. " HPR_MAX_STARVE ,Number of DFI clocks that the HPR queue can be starved before it goes critical" group.long 0x264++0x03 line.long 0x00 "PERFLPR1,Low Priority Read CAM Register 1" hexmask.long.byte 0x00 24.--31. 1. " LPR_XACT_RUN_LENGTH ,Number of transactions that are serviced once the LPR queue goes critical" hexmask.long.word 0x00 0.--15. 1. " LPR_MAX_STARVE ,Number of DFI clocks that the LPR queue can be starved before it goes critical" group.long 0x26C++0x03 line.long 0x00 "PERFWR1,Write CAM Register 1" hexmask.long.byte 0x00 24.--31. 1. " W_XACT_RUN_LENGTH ,Number of transactions that are serviced once the WR queue goes critical" hexmask.long.word 0x00 0.--15. 1. " W_MAX_STARVE ,Number of DFI clocks that the WR queue can be starved before it goes critical" group.long 0x300++0x07 line.long 0x00 "DBG0,Debug Register 0" bitfld.long 0x00 4. " DIS_COLLISION_PAGE_OPT ,Auto-precharge enable" "Disabled,Enabled" bitfld.long 0x00 2. " DIS_ACT_BYPASS ,Disable bypass path for high priority read activates" "No,Yes" newline bitfld.long 0x00 1. " DIS_RD_BYPASS ,Disable bypass path for high priority read page hits" "No,Yes" bitfld.long 0x00 0. " DIS_WC ,Disable write combine" "No,Yes" line.long 0x04 "DBG1,Debug Register 1" bitfld.long 0x04 1. " DIS_HIF ,HIF disable" "No,Yes" bitfld.long 0x04 0. " DIS_DQ ,De-queue from the CAM disable" "No,Yes" rgroup.long 0x308++0x03 line.long 0x00 "DBGCAM,CAM Debug Register" bitfld.long 0x00 31. " DBG_STALL_RD ,Stall for read channel" "Not stalled,Stalled" bitfld.long 0x00 30. " DBG_STALL_WR ,Stall for write channel" "Not stalled,Stalled" newline bitfld.long 0x00 29. " WR_DATA_PIPELINE_EMPTY ,Indicates that the write data pipeline on the DFI interface is empty" "Not empty,Empty" bitfld.long 0x00 28. " RD_DATA_PIPELINE_EMPTY ,Indicates that the read data pipeline on the DFI interface is empty" "Not empty,Empty" newline bitfld.long 0x00 26. " DBG_WR_Q_EMPTY ,Indicates that all the write command queues and write data buffers inside DDRC are empty" "Not empty,Empty" bitfld.long 0x00 25. " DBG_RD_Q_EMPTY ,Indicates that all the read command queues and read data buffers inside DDRC are empty" "Not empty,Empty" newline bitfld.long 0x00 24. " DBG_STALL ,Stall" "Not stalled,Stalled" bitfld.long 0x00 16.--21. " DBG_W_Q_DEPTH ,Write queue depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " DBG_LPR_Q_DEPTH ,Low priority read queue depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DBG_HPR_Q_DEPTH ,High priority read queue depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x30C++0x03 line.long 0x00 "DBGCMD,Command Debug Register" bitfld.long 0x00 5. " CTRLUPD ,Indicates to the DDRC to issue a dfi_ctrlupd_req to the PHY" "Not issued,Issued" bitfld.long 0x00 4. " ZQ_CALIB_SHORT ,Indicates to the DDRC to issue a ZQCS command to the SDRAM" "No calibration,Calibration" newline bitfld.long 0x00 1. " RANK1_REFRESH ,Indicates to the DDRC to issue a refresh to rank 1" "No refresh,Refresh" bitfld.long 0x00 0. " RANK0_REFRESH ,Indicates to the DDRC to issue a refresh to rank 0" "No refresh,Refresh" rgroup.long 0x310++0x03 line.long 0x00 "DBGSTAT,Status Debug Register" bitfld.long 0x00 5. " CTRLUPD_BUSY ,Ctrlupd operation busy" "Not busy,Busy" bitfld.long 0x00 4. " ZQ_CALIB_SHORT_BUSY ,ZQCS operation busy" "Not busy,Busy" newline bitfld.long 0x00 1. " RANK1_REFRESH_BUSY ,Rank1_refresh operation busy" "Not busy,Busy" bitfld.long 0x00 0. " RANK0_REFRESH_BUSY ,Rank0_refresh operation busy" "Not busy,Busy" group.long 0x320++0x03 line.long 0x00 "SWCTL,Software Register Programming Control Enable" bitfld.long 0x00 0. " SW_DONE ,Enable quasi dynamic register programming outside reset" "Disabled,Enabled" rgroup.long 0x324++0x03 line.long 0x00 "SWSTAT,Software Register Programming Control Status" bitfld.long 0x00 0. " SW_DONE_ACK ,Register programming done" "Not done,Done" group.long 0x36C++0x03 line.long 0x00 "POISONCFG,AXI Poison Configuration Register" bitfld.long 0x00 24. " RD_POISON_INTR_CLR ,Interrupt clear for read transaction poisoning" "Not cleared,Cleared" bitfld.long 0x00 20. " RD_POISON_INTR_EN ,Enables interrupts for read transaction poisoning" "Disabled,Enabled" newline bitfld.long 0x00 16. " RD_POISON_SLVERR_EN ,Enables SLVERR response for read transaction poisoning" "Disabled,Enabled" bitfld.long 0x00 8. " WR_POISON_INTR_CLR ,Interrupt clear for write transaction poisoning" "Not cleared,Cleared" newline bitfld.long 0x00 4. " WR_POISON_INTR_EN ,Enables interrupts for write transaction poisoning" "Disabled,Enabled" bitfld.long 0x00 0. " WR_POISON_SLVERR_EN ,Enables SLVERR response for write transaction poisoning" "Disabled,Enabled" rgroup.long 0x370++0x03 line.long 0x00 "POISONSTAT,AXI Poison Status Register" bitfld.long 0x00 16. " RD_POISON_INTR_0 ,Read transaction poisoning error interrupt for port 0" "Not occurred,Occurred" bitfld.long 0x00 0. " WR_POISON_INTR_0 ,Write transaction poisoning error interrupt for port 0" "Not occurred,Occurred" rgroup.long 0x3FC++0x03 line.long 0x00 "PSTAT,Port Status Register" bitfld.long 0x00 16. " WR_PORT_BUSY_0 ,Indicates if there are outstanding writes for AXI port 0" "Not busy,Busy" bitfld.long 0x00 0. " RD_PORT_BUSY_0 ,Indicates if there are outstanding reads for AXI port 0" "Not busy,Busy" group.long 0x400++0x0B line.long 0x00 "PCCFG,Port Common Configuration Register" bitfld.long 0x00 8. " BL_EXP_MODE ,Burst length expansion mode" "0,1" bitfld.long 0x00 4. " PAGEMATCH_LIMIT ,Page match four limit" "No limit,Limit" newline bitfld.long 0x00 0. " GO2CRITICAL_EN ,Sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals" "Disabled,Enabled" line.long 0x04 "PCFGR_0,Port 0 Configuration Read Register" bitfld.long 0x04 16. " RDWR_ORDERED_EN ,Enable ordered read/writes" "Disabled,Enabled" bitfld.long 0x04 14. " RD_PORT_PAGEMATCH_EN ,Enables the Page Match feature" "Disabled,Enabled" newline bitfld.long 0x04 13. " RD_PORT_PAGEMATCH_EN ,Enables the AXI urgent sideband signal" "Disabled,Enabled" bitfld.long 0x04 12. " RD_PORT_AGING_EN ,Enables aging function for the read channel of the port" "Disabled,Enabled" newline hexmask.long.word 0x04 0.--9. 1. " RD_PORT_PRIORITY ,Determines the initial load value of read aging counters" line.long 0x08 "PCFGW_0,Port n Configuration Write Register" bitfld.long 0x08 14. " WR_PORT_PAGEMATCH_EN ,Enables the Page Match feature" "Disabled,Enabled" bitfld.long 0x08 13. " WR_PORT_URGENT_EN ,Enables the AXI urgent sideband signal" "Disabled,Enabled" newline bitfld.long 0x08 12. " WR_PORT_AGING_EN ,Enables aging function for the write channel of the port" "Disabled,Enabled" hexmask.long.word 0x08 0.--9. 1. " WR_PORT_PRIORITY ,Determines the initial load value of write aging counters" group.long 0x490++0x13 line.long 0x00 "PCTRL_0,Port 0 Control Register" bitfld.long 0x00 0. " PORT_EN ,Enables AXI port n" "Disabled,Enabled" line.long 0x04 "PCFGQOS0_0,Port 0 Read QoS Configuration Register 0" bitfld.long 0x04 20.--21. " RQOS_MAP_REGION1 ,Indicates the traffic class of region 1" "LPR,VPR,HPR,?..." bitfld.long 0x04 16.--17. " RQOS_MAP_REGION0 ,This bitfield indicates the traffic class of region 0" "LPR,VPR,HPR,?..." newline bitfld.long 0x04 0.--3. " RQOS_MAP_LEVEL1 ,Separation level1 indicating the end of region0 mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,?..." line.long 0x08 "PCFGQOS1_0,Port n Read QoS Configuration Register 1" hexmask.long.word 0x08 16.--26. 1. " RQOS_MAP_TIMEOUTR ,Specifies the timeout value for transactions mapped to the red address queue" hexmask.long.word 0x08 0.--10. 1. " RQOS_MAP_TIMEOUTB ,Specifies the timeout value for transactions mapped to the blue address queue" line.long 0x0C "PCFGWQOS0_0,Port n Write QoS Configuration Register 0" bitfld.long 0x0C 20.--21. " WQOS_MAP_REGION1 ,This bitfield indicates the traffic class of region 1" "NPW,VPW,?..." bitfld.long 0x0C 16.--17. " WQOS_MAP_REGION0 ,This bitfield indicates the traffic class of region 0" "NPW,VPW,?..." newline bitfld.long 0x0C 0.--3. " WQOS_MAP_LEVEL ,Separation level indicating the end of region0 mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,?..." line.long 0x10 "PCFGWQOS1_0,Port n Write QoS Configuration Register 1" hexmask.long.word 0x10 0.--10. 1. " WQOS_MAP_TIMEOUT ,Specifies the timeout value for write transactions" newline tree "SHADOW Registers" if (((per.l(ad:0x5C100000))&0x20)==0x20) group.long 0x2020++0x07 line.long 0x00 "DERATEEN_SHADOW,Temperature Derate Enable Register" bitfld.long 0x00 8.--9. " RC_DERATE_VALUE ,Derate value of tRC for LPDDR4" "+1,+2,+3,+4" bitfld.long 0x00 4.--7. " DERATE_BYTE ,Derate value of tRC for LPDDR4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1. " DERATE_VALUE ,Derate value" "+1,+2" bitfld.long 0x00 0. " DERATE_ENABLE ,Enables derating" "Disabled,Enabled" line.long 0x04 "DERATEINT_SHADOW,Temperature Derate Interval Register" elif ((((per.l(ad:0x5C100000))&0x08)==0x08)||(((per.l(ad:0x5C100000))&0x04)==0x04)) group.long 0x2020++0x07 line.long 0x00 "DERATEEN_SHADOW,Temperature Derate Enable Register" bitfld.long 0x00 4.--7. " DERATE_BYTE ,Derate value of tRC for LPDDR4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " DERATE_VALUE ,Derate value" "+1,+2" newline bitfld.long 0x00 0. " DERATE_ENABLE ,Enables derating" "Disabled,Enabled" line.long 0x04 "DERATEINT_SHADOW,Temperature Derate Interval Register" else hgroup.long 0x2020++0x03 hide.long 0x00 "DERATEEN_SHADOW,Temperature Derate Enable Register" hgroup.long 0x2024++0x03 hide.long 0x00 "DERATEINT_SHADOW,Temperature Derate Interval Register" endif if (((per.l(ad:0x5C100000))&0x20)==0x20) group.long 0x2050++0x03 line.long 0x00 "RFSHCTL0_SHADOW,Refresh Control Register 0" bitfld.long 0x00 20.--23. " REFRESH_MARGIN ,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--16. " REFRESH_TO_X32 ,Speculative refreshes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4.--8. " REFRESH_BURST ,Number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 2. " PER_BANK_REFRESH ,Per bank refresh" "Per bank,All bank" else group.long 0x2050++0x03 line.long 0x00 "RFSHCTL0_SHADOW,Refresh Control Register 0" bitfld.long 0x00 20.--23. " REFRESH_MARGIN ,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--16. " REFRESH_TO_X32 ,Speculative refreshes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4.--8. " REFRESH_BURST ,Number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif group.long 0x2064++0x03 line.long 0x00 "RFSHTMG_SHADOW,Refresh Timing Register" hexmask.long.word 0x00 16.--27. 1. " T_RFC_NOM_X32 ,Average time interval between refreshes per rank" bitfld.long 0x00 15. " LPDDR3_TREFBW_EN ,tREFBW parameter enabled" "Disabled,Enabled" newline hexmask.long.word 0x00 0.--9. 1. " T_RFC_MIN ,Minimum time from refresh to refresh or activate" group.long 0x20DC++0x07 line.long 0x00 "INIT3_SHADOW,SDRAM Initialization Register 3" hexmask.long.word 0x00 16.--31. 1. " MR ,Value to write to MR register" hexmask.long.word 0x00 0.--15. 1. " EMR ,Value to write to EMR register" line.long 0x04 "INIT4_SHADOW,SDRAM Initialization Register 4" hexmask.long.word 0x04 16.--31. 1. " EMR2 ,Value to write to EMR2 register" hexmask.long.word 0x04 0.--15. 1. " EMR3 ,Value to write to EMR3 register" hgroup.long 0x20E8++0x03 hide.long 0x00 "INIT6_SHADOW,SDRAM Initialization Register 6" hgroup.long 0x20EC++0x03 hide.long 0x00 "INIT7_SHADOW,SDRAM Initialization Register 7" group.long 0x2100++0x0B line.long 0x00 "DRAMTMG0_SHADOW,SDRAM Timing Register 0" hexmask.long.byte 0x00 24.--30. 1. " WR2PRE ,Minimum time between write and precharge to same bank" bitfld.long 0x00 16.--21. " T_FAW ,T_FAW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x00 8.--14. 1. " T_RAS_MAX ,Maximum time between activate and precharge to same bank" bitfld.long 0x00 0.--5. " T_RAS_MIN ,Minimum time between activate and precharge to the same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DRAMTMG1_SHADOW,SDRAM Timing Register 1" bitfld.long 0x04 16.--20. " T_XP ,Minimum time after power-down exit to any operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--13. " RD2PRE ,Minimum time from read to precharge of same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x04 0.--6. 1. " T_RC ,Minimum time between activates to same bank" line.long 0x08 "DRAMTMG2_SHADOW,SDRAM Timing Register 2" bitfld.long 0x08 24.--29. " WRITE_LATENCY ,Set to WL time from write command to write data on SDRAM interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " READ_LATENCY ,Set to RL time from read command to read data on SDRAM interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " RD2WR ,Minimum time from read command to write command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " WR2RD ,Minimum time from write command to read command for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if ((((per.l(ad:0x5C100000))&0x20)==0x20)||(((per.l(ad:0x5C100000))&0x08)==0x08)||(((per.l(ad:0x5C100000))&0x04)==0x04)) group.long 0x210C++0x03 line.long 0x00 "DRAMTMG3_SHADOW,SDRAM Timing Register 3" hexmask.long.word 0x00 20.--29. 1. " T_MRW ,Time to wait after a mode register write or read (MRW or MRR)" bitfld.long 0x00 12.--17. " T_MRD ,Cycles to wait after a mode register write or read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.l(ad:0x5C100000))&0x01)==0x01) group.long 0x210C++0x03 line.long 0x00 "DRAMTMG3_SHADOW,SDRAM Timing Register 3" textfld " " bitfld.long 0x00 12.--17. " T_MRD ,Cycles to wait after a mode register write or read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 0.--9. 1. " T_MOD ,Cycles between load mode command and following non-load mode command" else group.long 0x210C++0x03 line.long 0x00 "DRAMTMG3_SHADOW,SDRAM Timing Register 3" textfld " " bitfld.long 0x00 12.--17. " T_MRD ,Cycles to wait after a mode register write or read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x2110++0x07 line.long 0x00 "DRAMTMG4_SHADOW,SDRAM Timing Register 4" bitfld.long 0x00 24.--28. " T_RCD ,Minimum time from activate to read or write command to same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--19. " T_CCD ,This is the minimum time between two reads or two writes for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " T_RRD ,Minimum time between activates from bank a to bank b for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " T_RP ,Minimum time from precharge to activate of same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DRAMTMG5_SHADOW,SDRAM Timing Register 5" bitfld.long 0x04 24.--27. " T_CKSRX ,Time before self refresh exit that ck is maintained as a valid clock before issuing SRX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " T_CKSRE ,Time after self refresh down entry that CK is maintained as a valid clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--13. " T_CKESR ,Minimum CKE low width for self refresh or self refresh power down entry to exit timing in memory clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--4. " T_CKE ,Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x5C100000))&0x20)==0x20) group.long 0x2118++0x07 line.long 0x00 "DRAMTMG6_SHADOW,SDRAM Timing Register 6" bitfld.long 0x00 24.--27. " T_CKDPDE ,Time after deep power down entry that CK is maintained as a valid clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " T_CKDPDX ,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " T_CKCSX ,Time before clock stop exit that CK is maintained as a valid clock before issuing clock stop exit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DRAMTMG7_SHADOW,SDRAM Timing Register 7" bitfld.long 0x04 8.--11. " T_CKPDE ,This is the time after Power Down Entry that CK is maintained as a valid clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " T_CKPDX ,This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x2118++0x03 line.long 0x00 "DRAMTMG6_SHADOW,SDRAM Timing Register 6" bitfld.long 0x00 24.--27. " T_CKDPDE ,Time after deep power down entry that CK is maintained as a valid clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " T_CKDPDX ,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0x211C++0x03 hide.long 0x00 "DRAMTMG7_SHADOW,SDRAM Timing Register 7" endif if (((per.l(ad:0x5C100000))&0x01)==0x01) group.long 0x2120++0x03 line.long 0x00 "DRAMTMG8_SHADOW,SDRAM Timing Register 8" hexmask.long.byte 0x00 24.--30. 1. " T_XS_FAST_X32 ,Exit self refresh to ZQCL ZQCS and MRS" hexmask.long.byte 0x00 16.--22. 1. " T_XS_ABORT_X32 ,Exit Self Refresh to commands not requiring a locked DLL in self refresh abort" newline hexmask.long.byte 0x00 8.--14. 1. " T_XS_DLL_X32 ,Exit self refresh to commands requiring a locked DLL" hexmask.long.byte 0x00 0.--6. 1. " T_XS_X32 ,Exit self refresh to commands not requiring a locked DLL" else group.long 0x2120++0x03 line.long 0x00 "DRAMTMG8_SHADOW,SDRAM Timing Register 8" hexmask.long.byte 0x00 24.--30. 1. " T_XS_FAST_X32 ,Exit self refresh to ZQCL ZQCS and MRS" hexmask.long.byte 0x00 16.--22. 1. " T_XS_ABORT_X32 ,Exit Self Refresh to commands not requiring a locked DLL in self refresh abort" endif hgroup.long 0x2124++0x03 hide.long 0x00 "DRAMTMG9_SHADOW,SDRAM Timing Register 9" group.long 0x2128++0x03 line.long 0x00 "DRAMTMG10_SHADOW,SDRAM Timing Register 10" bitfld.long 0x00 16.--20. " T_SYNC_GEAR ,Indicates the time between MRS command and the sync pulse time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " T_CMD_GEAR ,Sync pulse to first valid command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 2.--3. " T_GEAR_SETUP ,Geardown setup time" "0,1,2,3" bitfld.long 0x00 0.--1. " T_GEAR_HOLD ,Geardown hold time" "0,1,2,3" hgroup.long 0x212C++0x03 hide.long 0x00 "DRAMTMG11_SHADOW,SDRAM Timing Register 11" group.long 0x2130++0x07 line.long 0x00 "DRAMTMG12_SHADOW,SDRAM Timing Register 12" bitfld.long 0x00 16.--17. " T_CMDCKE ,Delay from valid command to CKE input LOW" "0,1,2,3" bitfld.long 0x00 8.--11. " T_CKEHCMD ,Valid command requirement after CKE input HIGH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--4. " T_MRD_PDA ,This is the Mode Register Set command cycle time in PDA mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DRAMTMG13_SHADOW,SDRAM Timing Register 13" hexmask.long.byte 0x04 24.--30. 1. " ODTLOFF ,Latency from CAS-2 command to tODToff reference" bitfld.long 0x04 16.--21. " T_CCD_MW ,This is the minimum time from write or masked write to masked write command for same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 0.--2. " T_PPD ,Minimum time from precharge to precharge command" "0,1,2,3,4,5,6,7" if (((per.l(ad:0x5C100000))&0x20)==0x20) group.long 0x2138++0x03 line.long 0x00 "DRAMTMG14_SHADOW,SDRAM Timing Register 14" hexmask.long.word 0x00 0.--11. 1. " T_XSR ,Exit Self Refresh to any command" else hgroup.long 0x2138++0x03 hide.long 0x00 "DRAMTMG14_SHADOW,SDRAM Timing Register 14" endif group.long 0x213C++0x03 line.long 0x00 "DRAMTMG15_SHADOW,SDRAM Timing Register 15" bitfld.long 0x00 31. " EN_DFI_LP_T_STAB ,Enables using tSTAB" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " T_STAB_X32 ,Stabilization time" if ((((per.l(ad:0x5C100000))&0x01)==0x01)||(((per.l(ad:0x5C100000))&0x20)==0x20)) group.long 0x2180++0x03 line.long 0x00 "ZQCTL0_SHADOW,ZQ Control Register 0" bitfld.long 0x00 31. " DIS_AUTO_ZQ ,Disable DDRC generation of ZQCS/MPC command" "No,Yes" bitfld.long 0x00 30. " DIS_SRX_ZQCL ,Disable issuing of ZQCL/MPC(ZQ calibration) command at self-refresh/sr-powerdown exit" "No,Yes" newline bitfld.long 0x00 29. " ZQ_RESISTOR_SHARED ,ZQ resistor is shared between ranks" "Not shared,Shared" newline hexmask.long.word 0x00 16.--26. 1. " T_ZQ_LONG_NOP ,Number of DFI clock cycles of NOP required after a ZQCL/MPC command is issued to SDRAM" hexmask.long.word 0x00 0.--9. 1. " T_ZQ_SHORT_NOP ,Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM" else hgroup.long 0x2180++0x03 hide.long 0x00 "ZQCTL0_SHADOW,ZQ Control Register 0" endif group.long 0x2190++0x07 line.long 0x00 "DFITMG0_SHADOW,DFI Timing Register 0" bitfld.long 0x00 24.--28. " DFI_T_CTRL_DELAY ,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 23. " DFI_RDDATA_USE_SDR ,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR(DFI PHY clock) values" "HDR,SDR" newline hexmask.long.byte 0x00 16.--22. 1. " DFI_T_RDDATA_EN ,Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal" bitfld.long 0x00 15. " DFI_WRDATA_USE_SDR ,Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values" "HDR,SDR" newline bitfld.long 0x00 8.--13. " DFI_TPHY_WRDATA ,Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal" "0,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 0.--5. " DFI_TPHY_WRLAT ,Write latency number of clocks from the write command to write data enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DFITMG1_SHADOW,DFI Timing Register 1" bitfld.long 0x04 28.--31. " DFI_T_CMD_LAT ,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven" "0,,,3,4,5,6,,8,?..." bitfld.long 0x04 24.--25. " DFI_T_PARIN_LAT ,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven" "0,1,2,3" newline bitfld.long 0x04 16.--20. " DFI_T_WRDATA_DELAY ,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " DFI_T_DRAM_CLK_DISABLE ,Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--4. " DFI_T_DRAM_CLK_ENABLE ,Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x21B4++0x07 line.long 0x00 "DFITMG2_SHADOW,DFI Timing Register 2" hexmask.long.byte 0x00 8.--14. 1. " DFI_TPHY_RDCSLAT ,Number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted" bitfld.long 0x00 0.--5. " DFI_TPHY_WRCSLAT ,Number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DFITMG3_SHADOW,DFI Timing Register 3" bitfld.long 0x04 0.--4. " DFI_T_GEARDOWN_DELAY ,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x2240++0x03 line.long 0x00 "ODTCFG_SHADOW,ODT Configuration Register" bitfld.long 0x00 24.--27. " WR_ODT_HOLD ,DFI PHY clock cycles to hold ODT for a write command" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " WR_ODT_DELAY ,The delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--11. " RD_ODT_HOLD ,DFI PHY clock cycles to hold ODT for a read command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--6. " RD_ODT_DELAY ,The delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end width 0x0B tree.end tree "DDRP0_2 (DDR PHY)" base ad:0x5C110000 width 14. rgroup.long 0x00++0x03 line.long 0x00 "RIDR,Revision Identification Register" hexmask.long.byte 0x00 24.--31. 1. " UDRID ,User-Defined revision ID" hexmask.long.byte 0x00 20.--23. 1. " PHYMJR ,PHY major revision" hexmask.long.byte 0x00 16.--19. 1. " PHYMDR ,PHY moderate revision" hexmask.long.byte 0x00 12.--15. 1. " PHYMNR ,PHY minor revision" newline hexmask.long.byte 0x00 8.--11. 1. " PUBMJR ,PUB major revision" hexmask.long.byte 0x00 4.--7. 1. " PUBMDR ,PUB moderate revision" hexmask.long.byte 0x00 0.--3. 1. " PUBMNR ,PUB minor revision" group.long 0x04++0x03 line.long 0x00 "PIR,PHY Initialization Register" bitfld.long 0x00 30. " ZCALBYP ,Impedance calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 29. " DCALPSE ,Digital delay line calibration pause" "Not paused,Paused" bitfld.long 0x00 20. " DQS2DQ ,Write DQS2DQ training" "Disabled,Enabled" bitfld.long 0x00 19. " RDIMMINIT ,RDIMM initialization" "Disabled,Enabled" newline bitfld.long 0x00 18. " CTLDINIT ,Controller DRAM initialization" "Disabled,Enabled" bitfld.long 0x00 17. " VREF ,VREF training" "Disabled,Enabled" bitfld.long 0x00 16. " SRD ,Static read training" "Disabled,Enabled" bitfld.long 0x00 15. " WREYE ,Write data eye training" "Disabled,Enabled" newline bitfld.long 0x00 14. " RDEYE ,Read data eye training" "Disabled,Enabled" bitfld.long 0x00 13. " WRDSKW ,Write data bit deskew" "Disabled,Enabled" bitfld.long 0x00 12. " RDDSKW ,Read data bit deskew" "Disabled,Enabled" bitfld.long 0x00 11. " WLADJ ,Write leveling adjust" "Disabled,Enabled" newline bitfld.long 0x00 10. " QSGATE ,Read DQS gate training" "Disabled,Enabled" bitfld.long 0x00 9. " WL ,Write leveling" "Disabled,Enabled" bitfld.long 0x00 8. " DRAMINIT ,DRAM initialization" "Disabled,Enabled" bitfld.long 0x00 7. " DRAMRST ,DRAM reset" "No reset,Reset" newline bitfld.long 0x00 6. " PHYRST ,PHY reset" "No reset,Reset" bitfld.long 0x00 5. " DCAL ,Digital delay line calibration" "Disabled,Enabled" bitfld.long 0x00 4. " PLLINIT ,PLL initialization" "Disabled,Enabled" bitfld.long 0x00 2. " CA ,CA training" "Disabled,Enabled" newline bitfld.long 0x00 1. " ZCAL ,Impedance calibration" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization trigger" "Not triggered,Triggered" group.long 0x10++0x1F line.long 0x00 "PGCR0,PHY General Configuration Register 0" bitfld.long 0x00 31. " ADCP ,Address copy" "Disabled,Enabled" bitfld.long 0x00 26. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 24.--25. " OSCACDL ,Oscillator mode address/command delay line select" "0,1,2,3" bitfld.long 0x00 14.--18. " DTOSEL ,Digital test output select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 9.--12. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "PGCR1,PHY General Configuration Register 1" bitfld.long 0x04 31. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x04 28. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value (equivalent to one CK period)" "Not loaded,Loaded" bitfld.long 0x04 27. " DLTST ,Delay line test start" "Stopped,Started" bitfld.long 0x04 26. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x04 25. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x04 24. " ACVLDTRN ,AC loopback valid train" "0,1" bitfld.long 0x04 21.--23. " ACVLDDLY ,AC loopback valid delay" "0,1,2,3,4,5,6,7" bitfld.long 0x04 20. " LRDIMMST ,LRDIMM software training" "Disabled,Enabled" newline bitfld.long 0x04 18. " UPDMSTRC0 ,DFI update master channel 0" "Not updated,Updated" bitfld.long 0x04 17. " DISDIC ,Enable/disable control for DFI_INIT_COMPLETE" "Disabled,Enabled" bitfld.long 0x04 16. " ACPDDC ,AC power-down with dual channels" "Disabled,Enabled" bitfld.long 0x04 15. " DUALCHN ,Dual channel configuration" "Disabled,Enabled" newline bitfld.long 0x04 13.--14. " FDEPTH ,Filter depth" "0,1,2,3" bitfld.long 0x04 11.--12. " LPFDEPTH ,Low-pass filter depth" "0,1,2,3" bitfld.long 0x04 10. " LPFEN ,Low-pass filter enable" "Disabled,Enabled" bitfld.long 0x04 9. " MDLEN ,Master delay line enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " PUBMODE ,Enable the PUB to control the interface to the PHY and SDRAM" "Disabled,Enabled" bitfld.long 0x04 5. " CAST ,CA software training" "Disabled,Enabled" bitfld.long 0x04 4. " DX_DQSOUT_DIFF ,Select PDIFF cell for DQS generation" "0,1" bitfld.long 0x04 3. " AC_CKOUT_DIFF ,Select PDIFF cell for CK generation" "0,1" newline bitfld.long 0x04 2. " WLSTEP ,Write leveling step" "0,1" bitfld.long 0x04 1. " WLMODE ,Write leveling software mode" "Disabled,Enabled" bitfld.long 0x04 0. " DTOMODE ,Digital test output mode" "Disabled,Enabled" line.long 0x08 "PGCR2,PHY General Configuration Register 2" bitfld.long 0x08 31. " CLRTSTAT ,Clear training status registers" "No effect,Cleared" bitfld.long 0x08 30. " CLRZCAL ,Clear impedance calibration" "No effect,Cleared" bitfld.long 0x08 29. " CLRPERR ,Clear parity error" "No effect,Cleared" bitfld.long 0x08 28. " ICPC ,Initialization complete pin configuration" "0,1" newline hexmask.long.byte 0x08 20.--27. 1. " DTPMXTMR ,Data training PUB mode exit timer" bitfld.long 0x08 19. " INITFSMBYP ,Initialization bypass" "Not bypassed,Bypassed" bitfld.long 0x08 18. " PLLFSMBYP ,PLL FSM bypass" "Not bypassed,Bypassed" hexmask.long.tbyte 0x08 0.--17. 1. " TREFPRD ,Refresh period" line.long 0x0C "PGCR3,PHY General Configuration Register 3" hexmask.long.byte 0x0C 24.--31. 1. " CKNEN ,CKN enable" hexmask.long.byte 0x0C 16.--23. 1. " CKEN ,CK enable" bitfld.long 0x0C 13.--14. " GATEACRDCLK ,Enable clock gating for AC [0] CTL_RD_CLK" "0,1,2,3" bitfld.long 0x0C 11.--12. " GATEACDDRCLK ,Enable clock gating for AC [0] DDR_CLK" "0,1,2,3" newline bitfld.long 0x0C 9.--10. " GATEACCTLCLK ,Enable clock gating for AC [0] CTL_CLK" "0,1,2,3" bitfld.long 0x0C 6.--7. " DDLBYPMODE ,Controls DDL bypass modes" "0,1,2,3" bitfld.long 0x0C 5. " IOLB ,IO loopback select" "0,1" bitfld.long 0x0C 3.--4. " RDMODE ,AC receive FIFO read mode" "0,1,2,3" newline bitfld.long 0x0C 2. " DISRST ,Read FIFO reset disable" "No,Yes" bitfld.long 0x0C 0.--1. " CLKLEVEL ,Clock level when clock gating" "0,1,2,3" line.long 0x10 "PGCR4,PHY General Configuration Register 4" bitfld.long 0x10 29. " ACDDLLD ,AC DDL delay select dynamic load" "Disabled,Enabled" bitfld.long 0x10 24.--28. " ACDDLBYP ,AC DDL bypass" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 23. " OEDDLBYP ,AC OE DDL bypass" "Not bypassed,Bypassed" bitfld.long 0x10 22. " TEDDLBYP ,AC ODT DDL bypass" "Not bypassed,Bypassed" newline bitfld.long 0x10 21. " PDRDDLBYP ,AC PDR DDL bypass" "Not bypassed,Bypassed" bitfld.long 0x10 20. " RRRMODE ,AC macro read path rise-to-rise mode" "Disabled,Enabled" bitfld.long 0x10 19. " WRRMODE ,AC macro write path rise-to-rise mode" "Disabled,Enabled" bitfld.long 0x10 17. " DCALTYPE ,DDL calibration type" "0,1" newline hexmask.long.word 0x10 8.--16. 1. " DCALSVAL ,DDL calibration starting value" bitfld.long 0x10 4.--7. " LPWAKEUP_THRSH ,AC low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 1. " LPPLLPD ,AC low power PLL power down" "Disabled,Enabled" bitfld.long 0x10 0. " LPIOPD ,AC low power IO power down" "Disabled,Enabled" line.long 0x14 "PGCR5,PHY General Configuration Register 5" hexmask.long.byte 0x14 24.--31. 1. " FRQBT ,Frequency B ratio term" hexmask.long.byte 0x14 16.--23. 1. " FRQAT ,Frequency A ratio term" hexmask.long.byte 0x14 8.--15. 1. " DISCNPERIOD ,DFI disconnect time period" bitfld.long 0x14 4.--7. " VREF_RBCTRL ,Receiver bias core side control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 2. " DXREFISELRANGE ,Internal VREF generator REFSEL range select" "0,1" bitfld.long 0x14 1. " DDLPGACT ,DDL page read write select" "Read,Write" bitfld.long 0x14 0. " DDLPGRW ,DDL page read write select" "Read,Write" line.long 0x18 "PGCR6,PHY General Configuration Register 6" hexmask.long.byte 0x18 16.--23. 1. " DLDLMT ,Delay line VT drift limit" bitfld.long 0x18 13. " ACDLVT ,AC address/command delay LCDL VT compensation" "Disabled,Enabled" bitfld.long 0x18 12. " ACBVT ,Address/command bit delay VT compensation" "Disabled,Enabled" bitfld.long 0x18 11. " ODTBVT ,ODT bit delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x18 10. " CKEBVT ,CKE bit delay VT compensation" "Disabled,Enabled" bitfld.long 0x18 9. " CSNBVT ,CSN bit delay VT compensation" "Disabled,Enabled" bitfld.long 0x18 8. " CKBVT ,CK bit delay VT compensation" "Disabled,Enabled" bitfld.long 0x18 1. " FVT ,Forced VT compensation trigger" "Not triggered,Triggered" newline bitfld.long 0x18 0. " INHVT ,VT calculation inhibit" "Disabled,Enabled" line.long 0x1C "PGCR7,PHY General Configuration Register 7" bitfld.long 0x1C 5. " ACCALCLK ,AC calibration clock select" "0,1" bitfld.long 0x1C 4. " ACRCLKMD ,AC read clock mode" "Disabled,Enabled" bitfld.long 0x1C 3. " ACDLDT ,AC DDL load type" "0,1" bitfld.long 0x1C 1. " ACDTOSEL ,AC digital test output select" "0,1" newline bitfld.long 0x1C 0. " ACTMODE ,AC test mode" "Disabled,Enabled" rgroup.long 0x30++0x0B line.long 0x00 "PGSR0,PHY General Status Register 0" bitfld.long 0x00 31. " APLOCK ,AC PLL lock" "Not locked,Locked" bitfld.long 0x00 30. " SRDERR ,Static read error" "No error,Error" bitfld.long 0x00 29. " CAWRN ,CA training warning" "Not occurred,Occurred" bitfld.long 0x00 28. " CAERR ,CA training error" "No error,Error" newline bitfld.long 0x00 27. " WEERR ,Write eye training error" "No error,Error" bitfld.long 0x00 26. " REERR ,Read eye training error" "No error,Error" bitfld.long 0x00 25. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x00 24. " RDERR ,Read bit deskew error" "No error,Error" newline bitfld.long 0x00 23. " WLAERR ,Write leveling adjustment error" "No error,Error" bitfld.long 0x00 22. " QSGERR ,DQS gate training error" "No error,Error" bitfld.long 0x00 21. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x00 20. " ZCERR ,Impedance calibration error" "No error,Error" newline bitfld.long 0x00 19. " VERR ,VREF training error" "No error,Error" bitfld.long 0x00 18. " DQS2DQERR ,Write DQS2DQ training error" "No error,Error" bitfld.long 0x00 15. " DQS2DQDONE ,Write DQS2DQ training done" "Not done,Done" bitfld.long 0x00 14. " VDONE ,VREF training done" "Not done,Done" newline bitfld.long 0x00 13. " SRDDONE ,Static read done" "Not done,Done" bitfld.long 0x00 12. " CADONE ,CA training done" "Not done,Done" bitfld.long 0x00 11. " WEDONE ,Write eye training done" "Not done,Done" bitfld.long 0x00 10. " REDONE ,Read eye training done" "Not done,Done" newline bitfld.long 0x00 9. " WDDONE ,Write bit deskew done" "Not done,Done" bitfld.long 0x00 8. " RDDONE ,Read bit deskew done" "Not done,Done" bitfld.long 0x00 7. " WLADONE ,Write leveling adjustment done" "Not done,Done" bitfld.long 0x00 6. " QSGDONE ,DQS gate training done" "Not done,Done" newline bitfld.long 0x00 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x00 4. " DIDONE ,DRAM initialization done" "Not done,Done" bitfld.long 0x00 3. " ZCDONE ,Impedance calibration done" "Not done,Done" bitfld.long 0x00 2. " DCDONE ,Digital delay line calibration done" "Not done,Done" newline bitfld.long 0x00 1. " PLDONE ,PLL lock done" "Not done,Done" bitfld.long 0x00 0. " IDONE ,Initialization done" "Not done,Done" line.long 0x04 "PGSR1,PHY General Status Register 1" bitfld.long 0x04 31. " PARERR ,RDIMM parity error" "No error,Error" bitfld.long 0x04 30. " VTSTOP ,VT stop" "Not stopped,Stopped" hexmask.long.tbyte 0x04 1.--24. 1. " DLTCODE ,Delay line test code for AC macro 0" bitfld.long 0x04 0. " DLTDONE ,Delay line test done for AC macro 0" "Not done,Done" line.long 0x08 "PGSR2,PHY General Status Register 2" hexmask.long.tbyte 0x08 1.--24. 1. " DLTCODE ,Delay line test code for AC macro 1" bitfld.long 0x08 0. " DLTDONE ,Delay line test done for AC macro 1" "Not done,Done" newline group.long 0x40++0x1B line.long 0x00 "PTR0,PHY Timing Register 0" hexmask.long.word 0x00 21.--31. 1. " TPLLPD ,PLL power-down time" hexmask.long.tbyte 0x00 6.--20. 1. " TPLLGS ,PLL gear shift time" bitfld.long 0x00 0.--5. " TPHYRST ,PHY reset time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "PTR1,PHY Timing Register 1" hexmask.long.word 0x04 16.--31. 1. " TPLLLOCK ,PLL lock time" hexmask.long.word 0x04 0.--12. 1. " TPLLRST ,PLL reset time" line.long 0x08 "PTR2,PHY Timing Register 2" bitfld.long 0x08 15.--19. " TWLDLYS ,Write leveling delay settling time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 10.--14. " TCALH ,Calibration hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 5.--9. " TCALS ,Calibration setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 0.--4. " TCALON ,Calibration on time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "PTR3,PHY Timing Register 3" hexmask.long.tbyte 0x0C 0.--22. 1. " TDINIT0 ,DRAM initialization time 0" line.long 0x10 "PTR4,PHY Timing Register 4" hexmask.long.word 0x10 0.--12. 1. " TDINIT1 ,DRAM initialization time 1" line.long 0x14 "PTR5,PHY Timing Register 5" hexmask.long.tbyte 0x14 0.--18. 1. " TDINIT2 ,DRAM initialization time 2" line.long 0x18 "PTR6,PHY Timing Register 6" hexmask.long.byte 0x18 20.--26. 1. " TDINIT4 ,DRAM initialization time 4" hexmask.long.word 0x18 0.--11. 1. " TDINIT3 ,DRAM initialization time 3" group.long 0x68++0x17 line.long 0x00 "PLLCR0,PLL Control Register 0" bitfld.long 0x00 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x00 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x00 28. " RSTOPM ,Reference stop mode" "Disabled,Enabled" newline bitfld.long 0x00 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x00 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12. " GSHIFT ,Gear shift" "Disabled,Enabled" bitfld.long 0x00 8. " ATOEN ,Analog test enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "PLLCR1,PLL Control Register 1" hexmask.long.word 0x04 16.--31. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x04 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x04 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypassed,Bypassed" bitfld.long 0x04 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x04 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x04 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x04 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x08 "PLLCR2,PLL Control Register 2" line.long 0x0C "PLLCR3,PLL Control Register 3" line.long 0x10 "PLLCR4,PLL Control Register 4" line.long 0x14 "PLLCR5,PLL Control Register 5" hexmask.long.byte 0x14 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL generator control bus PLL_CTRL" group.long 0x88++0x03 line.long 0x00 "DXCCR,DATX8 Common Configuration Register" bitfld.long 0x00 29. " RKLOOP ,Rank looping (per-rank eye centering) enable" "Disabled,Enabled" bitfld.long 0x00 3.--6. " DQS2DQMPER ,Write DQS2DQ training measurement period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x90++0x03 line.long 0x00 "DSGCR,DDR System General Configuration Register" bitfld.long 0x00 27. " RDBICLSEL ,Select RDBI CL calculation" "Default,RDBICL" bitfld.long 0x00 24.--26. " RDBICL ,RDBI CL adjust value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " PHYZUEN ,PHY impedance update enable" "Disabled,Enabled" bitfld.long 0x00 21. " RSTOE ,SDRAM reset output enable" "Disabled,Enabled" newline bitfld.long 0x00 19.--20. " SDRMODE ,Single data rate mode" "0,1,2,3" bitfld.long 0x00 17. " ATOAE ,ATO analog test enable" "Disabled,Enabled" bitfld.long 0x00 16. " DTOOE ,DTO output enable" "Disabled,Enabled" bitfld.long 0x00 15. " DTOIOM ,DTO I/O mode" "Disabled,Enabled" newline bitfld.long 0x00 14. " DTOPDR ,DTO power down receiver" "Disabled,Enabled" bitfld.long 0x00 12. " DTOODT ,DTO on-die termination" "Disabled,Enabled" bitfld.long 0x00 6.--11. " PUAD ,PHY update acknowledge delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 5. " CUAEN ,Controller update acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " MSTRVER ,Controller impedance update enable" "Disabled,Enabled" bitfld.long 0x00 2. " CTLZUEN ,Controller impedance update enable" "Disabled,Enabled" bitfld.long 0x00 1. " MREN ,Master request enable" "Disabled,Enabled" bitfld.long 0x00 0. " PUREN ,PHY update request enable" "Disabled,Enabled" group.long 0x98++0x03 line.long 0x00 "ODTCR,ODT Configuration Register" bitfld.long 0x00 16. " WRODT ,Write ODT" "0,1" bitfld.long 0x00 0. " RDODT ,Read ODT" "0,1" group.long 0xA0++0x03 line.long 0x00 "AACR,Anti-Aging Control Register" bitfld.long 0x00 31. " AAOENC ,Anti-aging PAD output enable control" "Disabled,Enabled" bitfld.long 0x00 30. " AAENC ,Anti-aging enable control" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " AATR ,Anti-aging toggle rate" group.long 0xC0++0x07 line.long 0x00 "GPR0,General Purpose Register 0" line.long 0x04 "GPR1,General Purpose Register 1" group.long 0x100++0x03 line.long 0x00 "DCR,DRAM Configuration Register" bitfld.long 0x00 31. " GEARDN ,DDR4 gear down timing" "0,1" bitfld.long 0x00 30. " UBG ,Un-used bank group" "0,1" bitfld.long 0x00 29. " UDIMM ,Un-buffered DIMM address mirroring" "Disabled,Enabled" bitfld.long 0x00 28. " DDR2T ,DDR 2T timing" "0,1" newline bitfld.long 0x00 27. " NOSRA ,No simultaneous rank access" "No,Yes" hexmask.long.word 0x00 10.--17. 1. " BYTEMASK ,Byte mask" bitfld.long 0x00 8.--9. " DDRTYPE ,DDR type" "0,1,2,3" bitfld.long 0x00 7. " MPRDQ ,Multi-purpose register DQ" "0,1" newline bitfld.long 0x00 4.--6. " PDQ ,Primary DQ" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " DDR8BNK ,DDR 8-bank" "Disabled,Enabled" bitfld.long 0x00 0.--2. " DDRMD ,DDR mode" "0,1,2,3,4,5,6,7" group.long 0x110++0x1B line.long 0x00 "DTPR0,DRAM Timing Parameters Register 0" bitfld.long 0x00 24.--28. " TRRD ,Activate to activate command delay on different banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 16.--22. 1. " TRAS ,Activate to precharge command delay" hexmask.long.byte 0x00 8.--14. 1. " TRP ,Precharge command period" bitfld.long 0x00 0.--4. " TRTP ,Internal read to precharge command delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DTPR1,DRAM Timing Parameters Register 1" hexmask.long.byte 0x04 24.--30. 1. " TWLMRD ,Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge" hexmask.long.byte 0x04 16.--22. 1. " TFAW ,4-bank activate period" bitfld.long 0x04 8.--10. " TMOD ,Load mode update delay" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--4. " TMRD ,Load mode cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "DTPR2,DRAM Timing Parameters Register 2" bitfld.long 0x08 28. " TRTW ,Read to write command delay" "0,1" bitfld.long 0x08 24. " TRTODT ,Read to ODT delay" "0,1" bitfld.long 0x08 16.--19. " TCKE ,CKE minimum pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x08 0.--9. 1. " TXS ,Self refresh exit delay" line.long 0x0C "DTPR3,DRAM Timing Parameters Register 3" bitfld.long 0x0C 29.--31. " TOFDX ,ODT turn-off delay extension" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 26.--28. " TCCD ,Read to read and write to write command delay" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 16.--25. 1. " TDLLK ,DLL locking time" bitfld.long 0x0C 8.--11. " TDQSCKMAX ,Maximum DQS output access time from CK/CK#" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 0.--2. " TDQSCK ,DQS output access time from CK/CK#" "0,1,2,3,4,5,6,7" line.long 0x10 "DTPR4,DRAM Timing Parameters Register 4" bitfld.long 0x10 28.--29. " TAOND_TAOFD ,ODT turn-on/turn-off delays" "0,1,2,3" hexmask.long.word 0x10 16.--25. 1. " TRFC ,Refresh-to-refresh" bitfld.long 0x10 8.--13. " TWLO ,Write leveling output delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 0.--4. " TXP ,Power down exit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "DTPR5,DRAM Timing Parameters Register 5" hexmask.long.byte 0x14 16.--23. 1. " TRC ,Activate to activate command delay same bank" hexmask.long.byte 0x14 8.--14. 1. " TRCD ,Activate to read or write delay" bitfld.long 0x14 0.--4. " TWTR ,Internal write to read command delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "DTPR6,DRAM Timing Parameters Register 6" bitfld.long 0x18 31. " PUBWLEN ,PUB write latency enable" "Disabled,Enabled" bitfld.long 0x18 30. " PUBRLEN ,PUB read latency enable" "Disabled,Enabled" bitfld.long 0x18 8.--13. " PUBWL ,Write latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " PUBRL ,Read latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x140++0x0B line.long 0x00 "RDIMMGCR0,RDIMM General Configuration Register 0" bitfld.long 0x00 30. " QCSEN ,RDMIMM quad CS enable" "Disabled,Enabled" bitfld.long 0x00 27. " RDIMMIOM ,RDIMM outputs I/O mode" "Disabled,Enabled" bitfld.long 0x00 23. " ERROUTOE ,ERROUT# output enable" "Disabled,Enabled" bitfld.long 0x00 22. " ERROUTIOM ,ERROUT# I/O mode" "Disabled,Enabled" newline bitfld.long 0x00 21. " ERROUTPDR ,ERROUT# power down receiver" "No,Yes" bitfld.long 0x00 19. " ERROUTODT ,ERROUT# on-die termination" "Disabled,Enabled" bitfld.long 0x00 18. " LRDIMM ,Load reduced DIMM" "Disabled,Enabled" bitfld.long 0x00 17. " PARINIOM ,PAR_IN I/O mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " RNKMRREN ,Rank mirror enable" "Disabled,Enabled" bitfld.long 0x00 2. " SOPERR ,Stop on parity error" "Disabled,Enabled" bitfld.long 0x00 1. " ERRNOREG ,Parity error no registering" "No,Yes" bitfld.long 0x00 0. " RDIMM ,Registered DIMM" "Not registered,Registered" line.long 0x04 "RDIMMGCR1,RDIMM General Configuration Register 1" bitfld.long 0x04 28. " A17BID ,Address [17] B-side inversion disable" "No,Yes" bitfld.long 0x04 24.--26. " TBCMRD_L2 ,Command word to command word programming delay" "0,1,2,3,4,5,6,7" bitfld.long 0x04 20.--22. " TBCMRD_L ,Command word to command word programming delay" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " TBCMRD ,Command word to command word programming delay" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x04 0.--13. 1. " TBCSTAB ,Stabilization time" line.long 0x08 "RDIMMGCR2,RDIMM General Configuration Register 2" group.long 0x150++0x13 line.long 0x00 "RDIMMCR0,RDIMM Control Register 0" bitfld.long 0x00 28.--31. " RC7 ,DDR3 control word 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " RC5 ,DDR3 CK driver characteristics control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " RC4 ,DDR3 control signals driver characteristics control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " RC3 ,DDR3 control signals driver characteristics control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " RC2 ,DDR3 timing control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " RC1 ,DDR3 clock driver enable control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RC0 ,DDR3 global features control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "RDIMMCR1,RDIMM Control Register 1" bitfld.long 0x04 28.--31. " RC15 ,Control word 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 12.--15. " RC11 ,DDR3 operation voltage VDD control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " RC10 ,DDR3 RDIMM operating speed control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " RC9 ,DDR3 power saving settings control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " RC8 ,DDR3 additional input bus termination setting control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "RDIMMCR2,RDIMM Control Register 2" hexmask.long.byte 0x08 24.--31. 1. " RC4X ,Control word RC4X" hexmask.long.byte 0x08 16.--23. 1. " RC3X ,Control word RC3X" hexmask.long.byte 0x08 8.--15. 1. " RC2X ,Control word RC2X" hexmask.long.byte 0x08 0.--7. 1. " RC1X ,Control word RC1X" line.long 0x0C "RDIMMCR3,RDIMM Control Register 3" hexmask.long.byte 0x0C 24.--31. 1. " RC8X ,Control word RC8X" hexmask.long.byte 0x0C 16.--23. 1. " RC7X ,Control word RC7X" hexmask.long.byte 0x0C 8.--15. 1. " RC6X ,Control word RC6X" hexmask.long.byte 0x0C 0.--7. 1. " RC5X ,Control word RC5X" line.long 0x10 "RDIMMCR4,RDIMM Control Register 4" hexmask.long.byte 0x10 16.--23. 1. " RCBX ,Control word RC11X" hexmask.long.byte 0x10 8.--15. 1. " RCAX ,Control word RC10X" hexmask.long.byte 0x10 0.--7. 1. " RC9X ,Control word RC9X" group.long 0x168++0x07 line.long 0x00 "SCHCR0,Scheduler Command Register 0" hexmask.long.word 0x00 16.--24. 1. " SCHDQV ,Scheduler command DQ value" bitfld.long 0x00 8.--11. " SP_CMD ,Special command codes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CMD ,Specifies the command to be issued" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " SCHTRIG ,Mode register command trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SCHCR1,Scheduler Command Register 1" bitfld.long 0x04 28.--31. " SCRNK ,Scheduler rank address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x04 8.--27. 0x01 " SCADDR ,Scheduler command address specifies the value to be driven on the address bus" bitfld.long 0x04 6.--7. " SCBG ,Scheduler command bank group" "0,1,2,3" bitfld.long 0x04 4.--5. " SCBK ,Scheduler command bank address" "0,1,2,3" newline bitfld.long 0x04 2. " ALLRANK ,All ranks enabled" "Disabled,Enabled" group.long 0x180++0x0F line.long 0x00 "MR0,LPDDR4 Mode Register 0" bitfld.long 0x00 7. " CATR ,CA terminating rank" "0,1" bitfld.long 0x00 3.--4. " RZQI ,Built-in self-test for RZQ" "0,1,2,3" line.long 0x04 "MR1,LPDDR4 Mode Register 1" bitfld.long 0x04 7. " RDPST ,Read postamble length" "0,1" bitfld.long 0x04 4.--6. " NWR ,Write-recovery for auto-precharge command" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3. " RDPRE ,Read preamble length" "0,1" bitfld.long 0x04 2. " WRPRE ,Write preamble length" "0,1" newline bitfld.long 0x04 0.--1. " BL ,Burst length" "0,1,2,3" line.long 0x08 "MR2,LPDDR4 Mode Register 2" bitfld.long 0x08 7. " WRL ,Write leveling" "Disabled,Enabled" bitfld.long 0x08 6. " WLS ,Write latency set" "0,1" bitfld.long 0x08 3.--5. " WL ,Write latency" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0.--2. " RL ,Read latency" "0,1,2,3,4,5,6,7" line.long 0x0C "MR3,LPDDR4 Mode Register 3" bitfld.long 0x0C 7. " DBIWR ,DBI-write enable" "Disabled,Enabled" bitfld.long 0x0C 6. " DBIRD ,DBI-read enable" "Disabled,Enabled" bitfld.long 0x0C 3.--5. " PDDS ,Pull-down drive strength" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 1. " WRPST ,Write postamble length" "0,1" newline bitfld.long 0x0C 0. " PUCAL ,Pull-up calibration point" "0,1" group.long 0x1AC++0x0F line.long 0x00 "MR11,LPDDR4 Mode Register 11" bitfld.long 0x00 4.--6. " CAODT ,CA bus receiver on-die-termination" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " DQODT ,DQ bus receiver on-die-termination" "0,1,2,3,4,5,6,7" line.long 0x04 "MR12,LPDDR4 Mode Register 12" bitfld.long 0x04 6. " VR_CA ,VREF_CA range select" "0,1" bitfld.long 0x04 0.--5. " VREF_CA ,Controls the VREF_CA levels for frequency-set-point[1:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "MR13,LPDDR4 Mode Register 13" bitfld.long 0x08 7. " FSPOP ,Frequency set point operation mode" "0,1" bitfld.long 0x08 6. " FSPWR ,Frequency set point write enable" "Disabled,Enabled" bitfld.long 0x08 5. " DMD ,Data mask enable" "Disabled,Enabled" bitfld.long 0x08 4. " RRO ,Refresh rate option" "0,1" newline bitfld.long 0x08 3. " VRCG ,VREF current generator" "0,1" bitfld.long 0x08 2. " VRO ,VREF output" "0,1" bitfld.long 0x08 1. " RPT ,Read preamble training mode" "Disabled,Enabled" bitfld.long 0x08 0. " CBT ,Command bus training" "Disabled,Enabled" line.long 0x0C "MR14,LPDDR4 Mode Register 14" bitfld.long 0x0C 6. " VR_DQ ,VREFDQ range selects" "0,1" group.long 0x1D8++0x03 line.long 0x00 "MR22,LPDDR4 Mode Register 22" bitfld.long 0x00 5. " ODTD_CA ,CA ODT termination disable" "No,Yes" bitfld.long 0x00 4. " ODTE_CS ,ODT CS override" "No override,Override" bitfld.long 0x00 3. " ODTE_CK ,ODT CK override" "No override,Override" bitfld.long 0x00 0.--2. " CODT ,Controller ODT value for VOH calibration" "0,1,2,3,4,5,6,7" group.long 0x200++0x13 line.long 0x00 "DTCR0,Data Training Configuration Register 0" bitfld.long 0x00 28.--31. " RFSHDT ,Refresh during training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--25. " DTDRS ,Data training debug rank select" "0,1,2,3" bitfld.long 0x00 23. " DTEXG ,Data training with early/extended gate" "Disabled,Enabled" bitfld.long 0x00 22. " DTEXD ,Data training extended write DQS" "Disabled,Enabled" newline bitfld.long 0x00 21. " DTDSTP ,Data training debug step" "0,1" bitfld.long 0x00 20. " DTDEN ,Data training debug enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " DTDBS ,Data training debug byte select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " DTRDBITR ,Data training read DBI deskewing configuration" "0,1,2,3" newline bitfld.long 0x00 13. " DTBDC ,Data training bit deskew centering" "0,1" bitfld.long 0x00 12. " DTWBDDM ,Data training write bit deskew data mask" "Not masked,Masked" bitfld.long 0x00 8.--11. " RFSHEN ,Refreshes issued during entry to training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " DTCMPD ,Data training compare data" "0,1" newline bitfld.long 0x00 6. " DTMPR ,Data training using MPR" "Disabled,Enabled" bitfld.long 0x00 4. " INCWEYE ,WEYE training using MPC FIFO commands" "0,1" bitfld.long 0x00 0.--3. " DTRPTN ,Data training repeat number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DTCR1,Data Training Configuration Register 1" bitfld.long 0x04 16. " RANKEN ,Rank enable" "Disabled,Enabled" bitfld.long 0x04 12.--13. " DTRANK ,Data training rank" "0,1,2,3" bitfld.long 0x04 8.--10. " RDLVLGDIFF ,Read leveling gate sampling difference" "0,1,2,3,4,5,6,7" bitfld.long 0x04 4.--6. " RDLVLGS ,Read leveling gate shift" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 2. " RDPRMVL_TRN ,Read preamble training enable" "Disabled,Enabled" bitfld.long 0x04 1. " RDLVLEN ,Read leveling enable" "Disabled,Enabled" bitfld.long 0x04 0. " BSTEN ,Basic gate training enable" "Disabled,Enabled" line.long 0x08 "DTAR0,Data Training Address Register 0" bitfld.long 0x08 28.--29. " MPRLOC ,Multi-Purpose register MPR location" "0,1,2,3" hexmask.long.byte 0x08 24.--27. 0x01 " DTBGBK1 ,Data training bank group and bank address" hexmask.long.byte 0x08 20.--23. 0x10 " DTBGBK0 ,Data training bank group and bank address" hexmask.long.tbyte 0x08 0.--17. 0x01 " DTROW ,Data training row address" line.long 0x0C "DTAR1,Data Training Address Register 1" hexmask.long.word 0x0C 16.--24. 0x01 " DTCOL1 ,Data training column address" hexmask.long.word 0x0C 0.--8. 0x01 " DTCOL0 ,Data training column address" line.long 0x10 "DTAR2,Data Training Address Register 2" hexmask.long.word 0x10 16.--24. 0x01 " DTCOL3 ,Data training column address" hexmask.long.word 0x10 0.--8. 0x01 " DTCOL2 ,Data training column address" group.long 0x218++0x07 line.long 0x00 "DTDR0,Data Training Data Register 0" hexmask.long.byte 0x00 24.--31. 1. " DTBYTE3 ,Data training data" hexmask.long.byte 0x00 16.--23. 1. " DTBYTE2 ,Data training data" hexmask.long.byte 0x00 8.--15. 1. " DTBYTE1 ,Data training data" hexmask.long.byte 0x00 0.--7. 1. " DTBYTE0 ,Data training data" line.long 0x04 "DTDR1,Data Training Data Register 1" hexmask.long.byte 0x04 24.--31. 1. " DTBYTE7 ,Data training data" hexmask.long.byte 0x04 16.--23. 1. " DTBYTE6 ,Data training data" hexmask.long.byte 0x04 8.--15. 1. " DTBYTE5 ,Data training data" hexmask.long.byte 0x04 0.--7. 1. " DTBYTE4 ,Data training data" rgroup.long 0x230++0x0F line.long 0x00 "DTEDR0,Data Training Eye Data Register 0" hexmask.long.byte 0x00 24.--31. 1. " WDQMBX ,Data training write BDL shift maximum" bitfld.long 0x00 18.--23. " WDQBMN ,Data training write BDL shift minimum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 9.--17. 1. " WDQLMX ,Data training WDQ LCDL maximum" hexmask.long.word 0x00 0.--8. 1. " WDQLMN ,Data training WDQ LCDL minimum" line.long 0x04 "DTEDR1,Data Training Eye Data Register 1" hexmask.long.byte 0x04 24.--31. 1. " RDQSBMX ,Data training read BDL shift maximum" bitfld.long 0x04 18.--23. " RDQSBMN ,Data training read BDL shift minimum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x04 9.--17. 1. " RDQSLMX ,Data training RDQS LCDL maximum" hexmask.long.word 0x04 0.--8. 1. " RDQSLMN ,Data training RDQS LCDL minimum" line.long 0x08 "DTEDR2,Data Training Eye Data Register 2" hexmask.long.byte 0x08 24.--31. 1. " RDQSNBMX ,Data training read BDL shift maximum" bitfld.long 0x08 18.--23. " RDQSNBMN ,Data training read BDL shift minimum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x08 9.--17. 1. " RDQSNLMX ,Data training RDQSN LCDL maximum" hexmask.long.word 0x08 0.--8. 1. " RDQSNLMN ,Data training RDQSN LCDL minimum" line.long 0x0C "VTDR,VREF Training Data Register" hexmask.long.byte 0x0C 24.--30. 1. " HVREFMX ,DRAM DQ VREF maximum" hexmask.long.byte 0x0C 16.--22. 1. " HVREFMN ,DRAM DQ VREF minimum" bitfld.long 0x0C 8.--13. " DVREFMX ,DRAM DQ VREF maximum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " DVREFMN ,DRAM DQ VREF minimum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x240++0x0B line.long 0x00 "CATR0,CA Training Register 0" bitfld.long 0x00 16.--20. " CACD ,Minimum time between two consecutive CA calibration command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " CAADR ,Minimum wait time before sampling the CA response after calibration command has been sent to the memory" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " CA1BYTE1 ,CA_1 response byte lane 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CA1BYTE0 ,CA_1 response byte lane 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "CATR1,CA Training Register 1" bitfld.long 0x04 24.--27. " CA0BYTE1 ,CA_0 response byte lane 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 20.--23. " CA0BYTE0 ,CA_0 response byte lane 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " CAMRZ ,Minimum time for DRAM DQ going tristate after MRW CA exit calibration command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 12.--15. " CACKEH ,Minimum time for CKE high after last CA calibration response is driven by memory" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " CACKEL ,Minimum time for CKE going low after CA calibration mode is programmed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " CAEXT ,Minimum time for CA calibration exit command after CKE is high" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CAENT ,Minimum time for first CA calibration command after CKE is low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "PGCR8,PHY General Configuration Register 8" bitfld.long 0x08 28.--31. " CF ,Counter cycles factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x08 20.--27. 1. " CM ,Counter cycle multiplier" bitfld.long 0x08 16. " RANKEN ,Rank enable" "Disabled,Enabled" bitfld.long 0x08 15. " MODE ,Self incremental DQS2DQ training" "Disabled,Enabled" newline bitfld.long 0x08 14. " EN ,Incremental DQS2DQ training" "Disabled,Enabled" bitfld.long 0x08 8. " BSWAPMSB[8] ,PHY 8 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" bitfld.long 0x08 7. " [7] ,PHY 7 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" bitfld.long 0x08 6. " [6] ,PHY 6 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" newline bitfld.long 0x08 5. " [5] ,PHY 5 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" bitfld.long 0x08 4. " [4] ,PHY 4 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" bitfld.long 0x08 3. " [3] ,PHY 3 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" bitfld.long 0x08 2. " [2] ,PHY 2 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" newline bitfld.long 0x08 1. " [1] ,PHY 1 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" bitfld.long 0x08 0. " [0] ,PHY 0 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" group.long 0x250++0x0B line.long 0x00 "DQSDR0,DQS Drift Register 0" bitfld.long 0x00 28.--31. " DFTDLY ,Number of delay taps by which the DQS gate LCDL will be updated when DQS drift is detected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. " DFTZQUP ,Drift impedance update" "Not updated,Updated" bitfld.long 0x00 26. " DFTDDLUP ,Drift DDL update" "Not updated,Updated" bitfld.long 0x00 20.--21. " DFTRDSPC ,Drift read spacing" "0,1,2,3" newline bitfld.long 0x00 16.--19. " DFTB2BRD ,Drift back-to-back reads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DFTIDLRD ,Drift idle reads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DFTGPULSE ,Gate pulse enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--3. " DFTUPMODE ,DQS drift update mode" "0,1,2,3" newline bitfld.long 0x00 1. " DFTDTMODE ,DQS drift detection mode" "0,1" bitfld.long 0x00 0. " DFTDTEN ,DQS drift detection enable" "Disabled,Enabled" line.long 0x04 "DQSDR1,DQS Drift Register 1" bitfld.long 0x04 29.--31. " DFTUPDACKF ,Drift DFU update request ACK to DQS drift FSM issuing IDLE read cycles factor" "0,1,2,3,4,5,6,7" bitfld.long 0x04 24.--28. " DFTUPDACKC ,Drift DFI update request ACK to DQS drift FSM issuing IDLE read cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 20.--23. " DFTRDB2BF ,Drift Back-to-Back read cycles factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " DFTRDIDLF ,Drift idle read cycles factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x04 8.--15. 1. " DFTRDB2BC ,Drift Back-to-Back read cycles" hexmask.long.byte 0x04 0.--7. 1. " DFTRDIDLC ,Drift idle read cycles" line.long 0x08 "DQSDR2,DQS Drift Register 2" hexmask.long.byte 0x08 16.--23. 1. " DFTTHRSH ,Drift threshold" hexmask.long.word 0x08 0.--15. 1. " DFTMNTPRD ,Drift monitor period" group.long 0x300++0x17 line.long 0x00 "DCUAR,DCU Address Register" hexmask.long.byte 0x00 16.--19. 0x01 " CSADDR_R ,Cache slice address" hexmask.long.byte 0x00 12.--15. 0x10 " CWADDR_R ,Cache word address" bitfld.long 0x00 11. " ATYPE ,Access type" "0,1" bitfld.long 0x00 10. " INCA ,Increment address" "0,1" newline bitfld.long 0x00 8.--9. " CSEL ,Cache select" "0,1,2,3" hexmask.long.byte 0x00 4.--7. 0x10 " CSADDR_W ,Cache slice address" hexmask.long.byte 0x00 0.--3. 0x01 " CWADDR_W ,Cache word address" line.long 0x04 "DCUDR,DCU Data Register" line.long 0x08 "DCURR,DCU Run Register" bitfld.long 0x08 23. " XCEN ,Expected compare enable" "Disabled,Enabled" bitfld.long 0x08 22. " RCEN ,Read capture enable" "Disabled,Enabled" bitfld.long 0x08 21. " SCOF ,Stop capture on full" "0,1" bitfld.long 0x08 20. " SONF ,Stop on n-th fail" "0,1" newline hexmask.long.byte 0x08 12.--19. 1. " NFAIL ,Number of failures" hexmask.long.byte 0x08 8.--11. 0x01 " EADDR ,End address" hexmask.long.byte 0x08 4.--7. 0x10 " SADDR ,Start address" bitfld.long 0x08 0.--3. " DINST ,DCU instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "DCULR,DCU Loop Register" hexmask.long.byte 0x0C 28.--31. 0x10 " XLEADDR ,Expected data loop end address" bitfld.long 0x0C 17. " IDA ,Increment DRAM address" "0,1" bitfld.long 0x0C 16. " LINF ,Loop infinite" "0,1" hexmask.long.byte 0x0C 8.--15. 1. " LCNT ,Loop count" newline hexmask.long.byte 0x0C 4.--7. 0x10 " LEADDR ,Loop end address" hexmask.long.byte 0x0C 0.--3. 0x01 " LSADDR ,Loop start address" line.long 0x10 "DCUGCR,DCU General Configuration Register" hexmask.long.word 0x10 0.--15. 1. " RCSW ,Read capture start word" line.long 0x14 "DCUTPR,DCU Timing Parameters Register" hexmask.long.word 0x14 16.--31. 1. " TDCUT2 ,DCU generic timing parameter 2" hexmask.long.byte 0x14 8.--15. 1. " TDCUT1 ,DCU generic timing parameter 1" hexmask.long.byte 0x14 0.--7. 1. " TDCUT0 ,DCU generic timing parameter 0" rgroup.long 0x318++0x07 line.long 0x00 "DCUSR0,DCU Status Register 0" bitfld.long 0x00 2. " CFULL ,Capture full" "Not full,Full" bitfld.long 0x00 1. " CFAIL ,Capture fail" "Not failed,Failed" bitfld.long 0x00 0. " RDONE ,Run done" "Not done,Done" line.long 0x04 "DCUSR1,DCU Status Register 1" hexmask.long.byte 0x04 24.--31. 1. " LPCNT ,Loop count" hexmask.long.byte 0x04 16.--23. 1. " FLCNT ,Fail count" hexmask.long.word 0x04 0.--15. 1. " RDCNT ,Read count" group.long 0x400++0x2F line.long 0x00 "BISTRR,BIST Run Register" bitfld.long 0x00 29. " BPRBST ,BIST PRBS type" "0,1" bitfld.long 0x00 28. " BSOMA ,BIST stop on maximum address" "Disabled,Enabled" bitfld.long 0x00 26.--27. " BACDPAT ,BIST AC data pattern" "0,1,2,3" bitfld.long 0x00 25. " BCCSEL ,BIST clock cycle select" "0,1" newline bitfld.long 0x00 23.--24. " BCKSEL ,BIST CK select" "0,1,2,3" bitfld.long 0x00 19.--22. " BDXSEL ,BIST DATX8 select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 17.--18. " BDXDPAT ,BIST data pattern" "0,1,2,3" bitfld.long 0x00 16. " BDMEN ,BIST data mask enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " BACEN ,BIST AC enable" "Disabled,Enabled" bitfld.long 0x00 14. " BDXEN ,BIST DATX8 enable" "Disabled,Enabled" bitfld.long 0x00 13. " BSONF ,BIST stop on nth fail" "Disabled,Enabled" hexmask.long.word 0x00 5.--12. 1. " NFAIL ,Number of failures" newline bitfld.long 0x00 4. " BINF ,BIST infinite run" "0,1" bitfld.long 0x00 3. " BMODE ,BIST mode" "0,1" bitfld.long 0x00 0.--2. " BINST ,BIST instruction" "0,1,2,3,4,5,6,7" line.long 0x04 "BISTWCR,BIST Word Count Register" hexmask.long.word 0x04 16.--31. 1. " BACWCNT ,BIST AC word count" hexmask.long.word 0x04 0.--15. 1. " BDXWCNT ,BIST DX word count" newline line.long 0x08 "BISTMSKR0,BIST Mask Register 0" bitfld.long 0x08 20. " CSMSK ,Mask bit for CS_N bit 0" "0,1" bitfld.long 0x08 19. " ACTMSK ,Mask bit for the RAS" "0,1" newline bitfld.long 0x08 17. " AMSK[17:0] ,Mask bit for address bit 17" "0,1" bitfld.long 0x08 16. ",Mask bit for address bit 16" "0,1" bitfld.long 0x08 15. ",Mask bit for address bit 15" "0,1" bitfld.long 0x08 14. ",Mask bit for address bit 14" "0,1" bitfld.long 0x08 13. ",Mask bit for address bit 13" "0,1" bitfld.long 0x08 12. ",Mask bit for address bit 12" "0,1" bitfld.long 0x08 11. ",Mask bit for address bit 11" "0,1" bitfld.long 0x08 10. ",Mask bit for address bit 10" "0,1" bitfld.long 0x08 9. ",Mask bit for address bit 9" "0,1" bitfld.long 0x08 8. ",Mask bit for address bit 8" "0,1" bitfld.long 0x08 7. ",Mask bit for address bit 7" "0,1" bitfld.long 0x08 6. ",Mask bit for address bit 6" "0,1" bitfld.long 0x08 5. ",Mask bit for address bit 5" "0,1" bitfld.long 0x08 4. ",Mask bit for address bit 4" "0,1" bitfld.long 0x08 3. ",Mask bit for address bit 3" "0,1" bitfld.long 0x08 2. ",Mask bit for address bit 2" "0,1" bitfld.long 0x08 1. ",Mask bit for address bit 1" "0,1" bitfld.long 0x08 0. ",Mask bit for address bit 0" "0,1" line.long 0x0C "BISTMSKR1,BIST Mask Register 1" bitfld.long 0x0C 31. " DMMSK[3] ,Mask bit for the data mask DM bit 3" "0,1" bitfld.long 0x0C 30. " [2] ,Mask bit for the data mask DM bit 2" "0,1" bitfld.long 0x0C 29. " [1] ,Mask bit for the data mask DM bit 1" "0,1" bitfld.long 0x0C 28. " [0] ,Mask bit for the data mask DM bit 0" "0,1" newline bitfld.long 0x0C 27. " PARINMSK ,Mask bit for the PAR_IN" "0,1" bitfld.long 0x0C 24. " CIDMSK ,Mask bits for chip IP bits" "0,1" bitfld.long 0x0C 16. " ODTMSK ,Mask bit for ODT bit" "0,1" bitfld.long 0x0C 8. " CKEMSK ,Mask bit for CKE bit" "0,1" newline bitfld.long 0x0C 7. " BAMSK[3] ,Mask bit for bank address bit 3" "0,1" bitfld.long 0x0C 6. " [2] ,Mask bit for bank address bit 2" "0,1" bitfld.long 0x0C 5. " [1] ,Mask bit for bank address bit 1" "0,1" bitfld.long 0x0C 4. " [0] ,Mask bit for bank address bit 0" "0,1" line.long 0x10 "BISTMSKR2,BIST Mask Register 2" newline line.long 0x14 "BISTLSR,BIST LFSR Seed Register" line.long 0x18 "BISTAR0,BIST Address Register 0" hexmask.long.byte 0x18 28.--31. 0x10 " BBANK ,BIST bank address" hexmask.long.word 0x18 0.--11. 0x01 " BCOL ,BIST column address" line.long 0x1C "BISTAR1,BIST Address Register 1" bitfld.long 0x1C 16.--19. " BMRANK ,BIST maximum rank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x1C 4.--15. 1. " BAINC ,BIST address increment" bitfld.long 0x1C 0.--3. " BRANK ,BIST rank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x20 "BISTAR2,BIST Address Register 2" hexmask.long.byte 0x20 28.--31. 0x10 " BMBANK ,BIST maximum bank address" hexmask.long.word 0x20 0.--11. 0x01 " BMCOL ,BIST maximum column address" line.long 0x24 "BISTAR3,BIST Address Register 3" hexmask.long.tbyte 0x24 0.--17. 0x01 " BROW ,BIST row address" line.long 0x28 "BISTAR4,BIST Address Register 4" hexmask.long.tbyte 0x28 0.--17. 0x01 " BMROW ,BIST maximum row address" line.long 0x2C "BISTUDPR,BIST User Data Pattern Register" hexmask.long.word 0x2C 16.--31. 1. " BUDP1 ,BIST user data pattern 1" hexmask.long.word 0x2C 0.--15. 1. " BUDP0 ,BIST user data pattern 0" rgroup.long 0x430++0x33 line.long 0x00 "BISTGSR,BIST General Status Register" bitfld.long 0x00 28.--29. " RASBER ,RAS_n/ACT_n bit error" "0,1,2,3" hexmask.long.byte 0x00 20.--27. 1. " DMBER ,DM bit error" hexmask.long.word 0x00 2.--10. 1. " BDXERR ,BIST data error" bitfld.long 0x00 1. " BACERR ,BIST address/command error" "No error,Error" newline bitfld.long 0x00 0. " BDONE ,BIST done" "Not done,Done" line.long 0x04 "BISTWER0,BIST Word Error Register 0" hexmask.long.tbyte 0x04 0.--17. 1. " ACWER ,Address/command word error" line.long 0x08 "BISTWER1,BIST Word Error Register 1" hexmask.long.word 0x08 0.--15. 1. " DXWER ,Byte word error" line.long 0x0C "BISTBER0,BIST Bit Error Register 0" line.long 0x10 "BISTBER1,BIST Bit Error Register 1" bitfld.long 0x10 8.--9. " CSBER ,CS_N bit error" "0,1,2,3" hexmask.long.byte 0x10 0.--7. 1. " BABER ,Bank address bit error" line.long 0x14 "BISTBER2,BIST Bit Error Register 2" line.long 0x18 "BISTBER3,BIST Bit Error Register 3" line.long 0x1C "BISTBER4,BIST Bit Error Register 4" bitfld.long 0x1C 8.--9. " CIDBER ,Chip ID bit error" "0,1,2,3" bitfld.long 0x1C 0.--3. " ABER ,Address bit error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x20 "BISTWCSR,BIST Word Count Status Register" hexmask.long.word 0x20 16.--31. 1. " DXWCNT ,Byte word count" hexmask.long.word 0x20 0.--15. 1. " ACWCNT ,Address/command word count" line.long 0x24 "BISTFWR0,BIST Fail Word Register 0" bitfld.long 0x24 20. " CSWEBS ,Bit status during a word error for CS# bits" "No error,Error" bitfld.long 0x24 18. " ACTWEBS ,Bit status during a word error for the RAS" "No error,Error" hexmask.long.tbyte 0x24 0.--17. 1. " AWEBS ,Bit status during a word error for address bits" line.long 0x28 "BISTFWR1,BIST Fail Word Register 1" bitfld.long 0x28 31. " DMWEBS[3] ,Bit status during a word error for the data mask DM bit 3" "No error,Error" bitfld.long 0x28 30. " [2] ,Bit status during a word error for the data mask DM bit 2" "No error,Error" bitfld.long 0x28 29. " [1] ,Bit status during a word error for the data mask DM bit 1" "No error,Error" bitfld.long 0x28 28. " [0] ,Bit status during a word error for the data mask DM bit 0" "No error,Error" newline bitfld.long 0x28 20. " CIDWEBS ,Bit status during a word error for chip ID bits" "No error,Error" bitfld.long 0x28 19. " BAWEBS[3] ,Bit status during a word error for the bank address bit 3" "No error,Error" bitfld.long 0x28 18. " [2] ,Bit status during a word error for the bank address bit 2" "No error,Error" bitfld.long 0x28 17. " [1] ,Bit status during a word error for the bank address bit 1" "No error,Error" newline bitfld.long 0x28 16. " [0] ,Bit status during a word error for the bank address bit 0" "No error,Error" bitfld.long 0x28 8. " ODTWEBS ,Bit status during a word error for the ODT bits" "No error,Error" bitfld.long 0x28 0. " CKEWEBS ,Bit status during a word error for the CKE bits" "No error,Error" line.long 0x2C "BISTFWR2,BIST Fail Word Register 2" line.long 0x30 "BISTBER5,BIST Bit Error Register 5" bitfld.long 0x30 16.--17. " ODTBER ,ODT bit error" "0,1,2,3" bitfld.long 0x30 0.--1. " CKEBER ,CKE bit error" "0,1,2,3" group.long 0x4DC++0x03 line.long 0x00 "RANKIDR,Rank ID Register" bitfld.long 0x00 16.--19. " RANKRID ,Rank read ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RANKWID ,Rank write ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4E8++0x03 line.long 0x00 "RIOCR2,Rank I/O Configuration Register 2" bitfld.long 0x00 24.--25. " COEMODE ,SDRAM C output enable (OE) mode selection" "0,1,2,3" bitfld.long 0x00 0.--1. " CSOEMODE ,SDRAM CS_n output enable (OE) mode selection" "0,1,2,3" group.long 0x4F0++0x07 line.long 0x00 "RIOCR4,Rank I/O Configuration Register 4" bitfld.long 0x00 0.--1. " CKEOEMODE ,SDRAM CKE output enable (OE) mode selection" "0,1,2,3" line.long 0x04 "RIOCR5,Rank I/O Configuration Register 5" bitfld.long 0x04 0.--1. " ODTOEMODE ,SDRAM On-die termination output enable (OE) mode selection" "0,1,2,3" newline group.long 0x500++0x17 line.long 0x00 "ACIOCR0,AC I/O Configuration Register 0" bitfld.long 0x00 30.--31. " ACSR ,Address/command slew rate (D3F I/O only)" "0,1,2,3" bitfld.long 0x00 29. " RSTIOM ,SDRAM reset I/O mode" "0,1" bitfld.long 0x00 28. " RSTPDR ,SDRAM reset power down receiver" "0,1" bitfld.long 0x00 26. " RSTODT ,SDRAM reset on-die termination" "0,1" newline hexmask.long.byte 0x00 16.--23. 1. " ESR ,Decoupling capacitance ESR control in D5M I/O ring" bitfld.long 0x00 10.--11. " ACPNUMSEL ,Address/command custom pin mapping configuration" "0,1,2,3" bitfld.long 0x00 6.--9. " CKDCC ,CK duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--5. " ACPDRMODE ,AC power down receiver mode" "0,1,2,3" newline bitfld.long 0x00 2.--3. " ACODTMODE ,AC on-die termination mode" "0,1,2,3" bitfld.long 0x00 0. " ACRANKCLKSEL ,Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices" "0,1" line.long 0x04 "ACIOCR1,AC I/O Configuration Register 1" line.long 0x08 "ACIOCR2,AC I/O Configuration Register 2" bitfld.long 0x08 31. " CLKGENCLKGATE ,Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL slice" "No gating,Gating" bitfld.long 0x08 30. " ACOECLKGATE0 ,Clock gating for output enable D slices [0]" "No gating,Gating" bitfld.long 0x08 29. " ACPDRCLKGATE0 ,Clock gating for power down receiver D slices [0]" "No gating,Gating" bitfld.long 0x08 28. " ACTECLKGATE0 ,Clock gating for termination enable D slices [0]" "No gating,Gating" newline bitfld.long 0x08 26.--27. " CKNCLKGATE0 ,Clock gating for CK# D slices [1:0]" "0,1,2,3" bitfld.long 0x08 24.--25. " CKCLKGATE0 ,Clock gating for CK D slices [1:0]" "0,1,2,3" hexmask.long.tbyte 0x08 0.--23. 1. " ACCLKGATE0 ,Clock gating for AC D slices [23:0]" line.long 0x0C "ACIOCR3,AC I/O Configuration Register 3" bitfld.long 0x0C 30.--31. " PAROEMODE ,SDRAM parity output enable (OE) mode selection" "0,1,2,3" bitfld.long 0x0C 26.--29. " BGOEMODE ,SDRAM bank group output enable (OE) mode selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 22.--25. " BAOEMODE ,SDRAM bank address output enable (OE) mode selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 20.--21. " A17OEMODE ,SDRAM A[17] output enable (OE) mode selection" "0,1,2,3" newline bitfld.long 0x0C 18.--19. " A16OEMODE ,SDRAM A[16] / RAS_N output enable (OE) mode selection" "0,1,2,3" bitfld.long 0x0C 16.--17. " ACTOEMODE ,SDRAM ACT_N output enable (OE) mode selection" "0,1,2,3" bitfld.long 0x0C 0.--3. " CKOEMODE ,SDRAM CK output enable (OE) mode selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "ACIOCR4,AC I/O Configuration Register 4" bitfld.long 0x10 31. " LBCLKGATE ,Clock gating for AC LB slices and loopback read valid slices" "No gating,Gating" bitfld.long 0x10 30. " ACOECLKGATE1 ,Clock gating for output enable D slices [1]" "No gating,Gating" bitfld.long 0x10 29. " ACPDRCLKGATE1 ,Clock gating for power down receiver D slices [1]" "No gating,Gating" bitfld.long 0x10 28. " ACTECLKGATE1 ,Clock gating for termination enable D slices [1]" "No gating,Gating" newline bitfld.long 0x10 26.--27. " CKNCLKGATE1 ,Clock gating for CK# D slices [3:2]" "0,1,2,3" bitfld.long 0x10 24.--25. " CKCLKGATE1 ,Clock gating for CK D slices [3:2]" "0,1,2,3" hexmask.long.tbyte 0x10 0.--23. 1. " ACCLKGATE1 ,Clock gating for AC D slices [47:24]" line.long 0x14 "ACIOCR5,AC I/O Configuration Register 5" bitfld.long 0x14 25.--27. " ACVREFIOM ,IOM bits for PVREF and PVREFE cells in AC IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x14 22.--24. " ACXIOM ,AC IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x14 11.--21. 1. " ACTXM ,AC IO transmitter mode" hexmask.long.word 0x14 0.--10. 1. " ACRXM ,AC IO receiver mode" group.long 0x520++0x03 line.long 0x00 "IOVCR0,IO VREF Control Register 0" bitfld.long 0x00 28. " ACREFPEN ,Address/command lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x00 26.--27. " ACREFEEN ,Address/command lane internal VREF enable" "0,1,2,3" bitfld.long 0x00 25. " ACREFSEN ,Address/command lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x00 24. " ACREFIEN ,Address/command lane internal VREF enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " ACREFESELRANGE ,External VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x00 16.--22. 1. " ACREFESEL ,Address/command lane external VREF select" bitfld.long 0x00 15. " ACREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x00 8.--14. 1. " ACREFSSEL ,Address/command lane single-end VREF select" newline bitfld.long 0x00 7. " ACVREFISELRANGE ,Internal VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x00 0.--6. 1. " ACVREFISEL ,REFSEL control for internal AC IOs" group.long 0x528++0x07 line.long 0x00 "VTCR0,VREF Training Control Register 0" bitfld.long 0x00 29.--31. " TVREF ,Number of CTL_CLK required to meet > 150ns timing requirements during DRAM DQ VREF training" "0,1,2,3,4,5,6,7" bitfld.long 0x00 28. " DVEN ,DRM DQ VREF training enable" "Disabled,Enabled" bitfld.long 0x00 27. " PDAEN ,Per device addressability enable" "Disabled,Enabled" bitfld.long 0x00 22.--25. " VWCR ,VREF word count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 18.--21. " DVSS ,DRAM DQ VREF step size used during DRAM VREF training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--17. " DVMAX ,Maximum VREF limit value used during DRAM VREF training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 6.--11. " DVMIN ,Minimum VREF limit value used during DRAM VREF training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DVINIT ,Initial DRAM DQ VREF value used during DRAM VREF training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "VTCR1,VREF Training Control Register 1" bitfld.long 0x04 28.--31. " HVSS ,Host VREF step size used during VREF training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x04 20.--26. 1. " HVMAX ,Maximum VREF limit value used during DRAM VREF training" hexmask.long.byte 0x04 12.--18. 1. " HVMIN ,Minimum VREF limit value used during DRAM VREF training" bitfld.long 0x04 9.--10. " SHRNK ,Static host VREF rank value" "0,1,2,3" newline bitfld.long 0x04 8. " SHREN ,Static host VREF rank enable" "Disabled,Enabled" bitfld.long 0x04 5.--7. " TVREFIO ,Number of CTL_CLK required to meet > 200ns VREF settling timing requirements during host IO VREF training" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3.--4. " EOFF ,Eye LCDL offset value for VREF training" "0,1,2,3" bitfld.long 0x04 2. " ENUM ,Number of LCDL eye points for which VREF training is repeated" "0,1" newline bitfld.long 0x04 1. " HVEN ,HOST IO internal VREF training enable" "Disabled,Enabled" bitfld.long 0x04 0. " HVIO ,Host IO type control" "0,1" newline group.long 0x540++0x47 line.long 0x00 "ACBDLR0,AC Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " CK3BD ,CK3 bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " CK2BD ,CK2 bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CK1BD ,CK1 bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CK0BD ,CK0 bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "ACBDLR1,AC Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " PARBD ,Delay select for the BDL on parity" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " A16BD ,Delay select for the BDL on address A[16]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " A17BD ,Delay select for the BDL on address A[17]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " ACTBD ,Delay select for the BDL on ACTN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "ACBDLR2,AC Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " BG1BD ,Delay select for the BDL on BG[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " BG0BD ,Delay select for the BDL on BG[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " BA1BD ,Delay select for the BDL on BA[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " BA0BD ,Delay select for the BDL on BA[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "ACBDLR3,AC Bit Delay Line Register 3" bitfld.long 0x0C 24.--29. " CS3BD ,Delay select for the BDL on CS[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " CS2BD ,Delay select for the BDL on CS[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 8.--13. " CS1BD ,Delay select for the BDL on CS[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " CS0BD ,Delay select for the BDL on CS[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "ACBDLR4,AC Bit Delay Line Register 4" bitfld.long 0x10 24.--29. " ODT3BD ,Delay select for the BDL on ODT[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 16.--21. " ODT2BD ,Delay select for the BDL on ODT[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 8.--13. " ODT1BD ,Delay select for the BDL on ODT[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 0.--5. " ODT0BD ,Delay select for the BDL on ODT[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x14 "ACBDLR5,AC Bit Delay Line Register 5" bitfld.long 0x14 24.--29. " CKE3BD ,Delay select for the BDL on CKE[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 16.--21. " CKE2BD ,Delay select for the BDL on CKE[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 8.--13. " CKE1BD ,Delay select for the BDL on CKE[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 0.--5. " CKE0BD ,Delay select for the BDL on CKE[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x18 "ACBDLR6,AC Bit Delay Line Register 6" bitfld.long 0x18 24.--29. " A03BD ,Delay select for the BDL on address A[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " A02BD ,Delay select for the BDL on address A[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " A01BD ,Delay select for the BDL on address A[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " A00BD ,Delay select for the BDL on address A[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "ACBDLR7,AC Bit Delay Line Register 7" bitfld.long 0x1C 24.--29. " A07BD ,Delay select for the BDL on address A[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1C 16.--21. " A06BD ,Delay select for the BDL on address A[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1C 8.--13. " A05BD ,Delay select for the BDL on address A[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1C 0.--5. " A04BD ,Delay select for the BDL on address A[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x20 "ACBDLR8,AC Bit Delay Line Register 8" bitfld.long 0x20 24.--29. " A11BD ,Delay select for the BDL on address A[11]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x20 16.--21. " A10BD ,Delay select for the BDL on address A[10]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x20 8.--13. " A09BD ,Delay select for the BDL on address A[9]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x20 0.--5. " A08BD ,Delay select for the BDL on address A[8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x24 "ACBDLR9,AC Bit Delay Line Register 9" bitfld.long 0x24 24.--29. " A15BD ,Delay select for the BDL on address A[15]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x24 16.--21. " A14BD ,Delay select for the BDL on address A[14]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x24 8.--13. " A13BD ,Delay select for the BDL on address A[13]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x24 0.--5. " A12BD ,Delay select for the BDL on address A[12]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x28 "ACBDLR10,AC Bit Delay Line Register 10" bitfld.long 0x28 24.--29. " CID2BD ,Delay select for the BDL on chip ID CID[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x28 16.--21. " CID1BD ,Delay select for the BDL on chip ID CID[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x28 8.--13. " CID0BD ,Delay select for the BDL on chip ID CID[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x2C "ACBDLR11,AC Bit Delay Line Register 11" bitfld.long 0x2C 24.--29. " CS7BD ,Delay select for the BDL on CS[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2C 16.--21. " CS6BD ,Delay select for the BDL on CS[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2C 8.--13. " CS5BD ,Delay select for the BDL on CS[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2C 0.--5. " CS4BD ,Delay select for the BDL on CS[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x30 "ACBDLR12,AC Bit Delay Line Register 12" bitfld.long 0x30 24.--29. " CS11BD ,Delay select for the BDL on CS[11]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x30 16.--21. " CS10BD ,Delay select for the BDL on CS[10]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x30 8.--13. " CS9BD ,Delay select for the BDL on CS[9]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x30 0.--5. " CS8BD ,Delay select for the BDL on CS[8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x34 "ACBDLR13,AC Bit Delay Line Register 13" bitfld.long 0x34 24.--29. " ODT7BD ,Delay select for the BDL on ODT[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x34 16.--21. " ODT6BD ,Delay select for the BDL on ODT[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x34 8.--13. " ODT5BD ,Delay select for the BDL on ODT[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x34 0.--5. " ODT4BD ,Delay select for the BDL on ODT[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x38 "ACBDLR14,AC Bit Delay Line Register 14" bitfld.long 0x38 24.--29. " CKE7BD ,Delay select for the BDL on CKE[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x38 16.--21. " CKE6BD ,Delay select for the BDL on CKE[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x38 8.--13. " CKE5BD ,Delay select for the BDL on CKE[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x38 0.--5. " CKE4BD ,Delay select for the BDL on CKE[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x3C "ACBDLR15,AC Bit Delay Line Register 15" bitfld.long 0x3C 16.--21. " OEBD ,Delay select for the BDL on OE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3C 8.--13. " TEBD ,Delay select for the BDL on TE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3C 0.--5. " PDRBD ,Delay select for the BDL on PDR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x40 "ACBDLR16,AC Bit Delay Line Register 16" bitfld.long 0x40 24.--29. " CKN3BD ,Delay select for the BDL on CKN[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x40 16.--21. " CKN2BD ,Delay select for the BDL on CKN[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x40 8.--13. " CKN1BD ,Delay select for the BDL on CKN[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x40 0.--5. " CKN0BD ,Delay select for the BDL on CKN[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x44 "ACLCDLR,AC Local Calibrated Delay Line Register" hexmask.long.word 0x44 16.--24. 1. " ACD1 ,Address/command delay for AC macro 1" hexmask.long.word 0x44 0.--8. 1. " ACD ,Address/command delay for AC macro 0" group.long 0x5A0++0x07 line.long 0x00 "ACMDLR0,AC Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "ACMDLR1,AC Master Delay Line Register 1" hexmask.long.word 0x04 16.--24. 1. " MDLD1 ,MDL delay for AC macro 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay for AC macro 0" newline group.long 0x680++0x03 line.long 0x00 "ZQCR,ZQ Impedance Control Register" bitfld.long 0x00 25. " ZQREFISELRANGE ,ZQ VREF range" "0,1" bitfld.long 0x00 19.--24. " PGWAIT_FRQB ,Programmable wait for frequency B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 13.--18. " PGWAIT_FRQA ,Programmable wait for frequency A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12. " ZQREFPEN ,ZQ VREF pad enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ZQREFIEN ,ZQ internal VREF enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " ODT_MODE ,Choice of termination mode" "0,1,2,3" bitfld.long 0x00 8. " FORCE_ZCAL_VT_UPDATE ,Force ZCAL VT update" "0,1" bitfld.long 0x00 5.--7. " IODLMT ,IO VT drift limit" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4. " AVGEN ,Averaging algorithm enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " AVGMAX ,Maximum number of averaging rounds to be used by averaging algorithm" "0,1,2,3" bitfld.long 0x00 1. " ZCALT ,ZQ calibration type" "0,1" bitfld.long 0x00 0. " ZQPD ,ZQ power down" "No,Yes" group.long 0x684++0x07 line.long 0x00 "ZQ0PR0,ZQ 0 Impedance Control Program Register 0" bitfld.long 0x00 31. " PD_DRV_ZDEN ,Pull-down drive strength ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 30. " PU_DRV_ZDEN ,Pull-up drive strength ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 29. " PD_ODT_ZDEN ,Pull-down termination ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 28. " PU_ODT_ZDEN ,Pull-up termination ZCTRL override enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " ZSEGBYP ,Calibration segment bypass" "Not bypassed,Bypassed" bitfld.long 0x00 25.--26. " ZLE_MODE ,VREF latch mode" "0,1,2,3" bitfld.long 0x00 22.--24. " ODT_ADJUST ,Termination adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19.--21. " PD_DRV_ADJUST ,Pull-down drive strength adjustment" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. " PU_DRV_ADJUST ,Pull-up drive strength adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--15. " ZPROG_DRAM_ODT ,DRAM impedance divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " ZPROG_HOST_ODT ,HOST impedance divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " ZPROG_ASYM_DRV_PD ,Impedance divide ratio pull-down drive calibration during asymmetric drive strength calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " ZPROG_ASYM_DRV_PU ,Impedance divide ratio (pull-up drive calibration during asymmetric drive strength calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ZQ0PR1,ZQ 0 Impedance Control Program Register 1" hexmask.long.byte 0x04 8.--14. 1. " PU_REFSEL ,Pull-up REFSEL for PZCTRL cell" hexmask.long.byte 0x04 0.--6. 1. " PD_REFSEL ,Pull-down REFSEL for PZCTRL cell" rgroup.long (0x684+0x08)++0x07 line.long 0x00 "ZQ0DR0,ZQ 0 Impedance Control Data Register 0" hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_RESULT ,Pull-up drive strength calibration code result" hexmask.long.word 0x00 0.--9. 1. " ZDATA_PD_DRV_RESULT ,Pull-down drive strength calibration code result" line.long 0x04 "ZQ0DR1,ZQ 0 Impedance Control Data Register 1" hexmask.long.word 0x04 16.--25. 1. " ZDATA_PU_ODT_RESULT ,Pull-up termination calibration code result" hexmask.long.word 0x04 0.--9. 1. " ZDATA_PD_ODT_RESULT ,Pull-down termination calibration code result" group.long (0x684+0x10)++0x07 line.long 0x00 "ZQ0OR0,ZQ 0 Impedance Control Override Data Register 0" hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_OVRD ,Override value for the pull-up output impedance" hexmask.long.word 0x00 0.--9. 1. " ZDATA_PD_DRV_OVRD ,Override value for the pull-down output impedance" line.long 0x04 "ZQ0OR1,ZQ 0 Impedance Control Override Data Register 1" hexmask.long.word 0x04 16.--25. 1. " ZDATA_PU_ODT_OVRD ,Override value for the pull-up termination" hexmask.long.word 0x04 0.--9. 1. " ZDATA_PD_ODT_OVRD ,Override value for the pull-down termination" rgroup.long (0x684+0x18)++0x03 line.long 0x00 "ZQ0SR,ZQ 0 Impedance Control Status Register" bitfld.long 0x00 13. " PD_ODT_SAT ,Pull-down drive strength code saturated due to termination strength adjustment setting in ZQ0PR" "Not saturated,Saturated" bitfld.long 0x00 12. " PU_ODT_SAT ,Pull-up drive strength code saturated due to termination strength adjustment setting in ZQ0PR" "Not saturated,Saturated" bitfld.long 0x00 11. " PD_DRV_SAT ,Pull-down drive strength code saturated due to drive strength adjustment setting in ZQ0PR" "Not saturated,Saturated" bitfld.long 0x00 10. " PU_DRV_SAT ,Pull-up drive strength code saturated due to drive strength adjustment setting in ZQ0PR" "Not saturated,Saturated" newline bitfld.long 0x00 9. " ZDONE ,Impedance calibration done" "Not done,Done" bitfld.long 0x00 8. " ZERR ,Impedance calibration error" "No error,Error" bitfld.long 0x00 6.--7. " OPU ,On-die termination ODT pull-up calibration status" "0,1,2,3" bitfld.long 0x00 4.--5. " OPD ,On-die termination ODT pull-down calibration status" "0,1,2,3" newline bitfld.long 0x00 2.--3. " ZPU ,Output impedance pull-up calibration status" "0,1,2,3" bitfld.long 0x00 0.--1. " ZPD ,Output impedance pull-down calibration status" "0,1,2,3" group.long 0x6A4++0x07 line.long 0x00 "ZQ1PR0,ZQ 1 Impedance Control Program Register 0" bitfld.long 0x00 31. " PD_DRV_ZDEN ,Pull-down drive strength ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 30. " PU_DRV_ZDEN ,Pull-up drive strength ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 29. " PD_ODT_ZDEN ,Pull-down termination ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 28. " PU_ODT_ZDEN ,Pull-up termination ZCTRL override enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " ZSEGBYP ,Calibration segment bypass" "Not bypassed,Bypassed" bitfld.long 0x00 25.--26. " ZLE_MODE ,VREF latch mode" "0,1,2,3" bitfld.long 0x00 22.--24. " ODT_ADJUST ,Termination adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19.--21. " PD_DRV_ADJUST ,Pull-down drive strength adjustment" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. " PU_DRV_ADJUST ,Pull-up drive strength adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--15. " ZPROG_DRAM_ODT ,DRAM impedance divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " ZPROG_HOST_ODT ,HOST impedance divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " ZPROG_ASYM_DRV_PD ,Impedance divide ratio pull-down drive calibration during asymmetric drive strength calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " ZPROG_ASYM_DRV_PU ,Impedance divide ratio (pull-up drive calibration during asymmetric drive strength calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ZQ1PR1,ZQ 1 Impedance Control Program Register 1" hexmask.long.byte 0x04 8.--14. 1. " PU_REFSEL ,Pull-up REFSEL for PZCTRL cell" hexmask.long.byte 0x04 0.--6. 1. " PD_REFSEL ,Pull-down REFSEL for PZCTRL cell" rgroup.long (0x6A4+0x08)++0x07 line.long 0x00 "ZQ1DR0,ZQ 1 Impedance Control Data Register 0" hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_RESULT ,Pull-up drive strength calibration code result" hexmask.long.word 0x00 0.--9. 1. " ZDATA_PD_DRV_RESULT ,Pull-down drive strength calibration code result" line.long 0x04 "ZQ1DR1,ZQ 1 Impedance Control Data Register 1" hexmask.long.word 0x04 16.--25. 1. " ZDATA_PU_ODT_RESULT ,Pull-up termination calibration code result" hexmask.long.word 0x04 0.--9. 1. " ZDATA_PD_ODT_RESULT ,Pull-down termination calibration code result" group.long (0x6A4+0x10)++0x07 line.long 0x00 "ZQ1OR0,ZQ 1 Impedance Control Override Data Register 0" hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_OVRD ,Override value for the pull-up output impedance" hexmask.long.word 0x00 0.--9. 1. " ZDATA_PD_DRV_OVRD ,Override value for the pull-down output impedance" line.long 0x04 "ZQ1OR1,ZQ 1 Impedance Control Override Data Register 1" hexmask.long.word 0x04 16.--25. 1. " ZDATA_PU_ODT_OVRD ,Override value for the pull-up termination" hexmask.long.word 0x04 0.--9. 1. " ZDATA_PD_ODT_OVRD ,Override value for the pull-down termination" rgroup.long (0x6A4+0x18)++0x03 line.long 0x00 "ZQ1SR,ZQ 1 Impedance Control Status Register" bitfld.long 0x00 13. " PD_ODT_SAT ,Pull-down drive strength code saturated due to termination strength adjustment setting in ZQ1PR" "Not saturated,Saturated" bitfld.long 0x00 12. " PU_ODT_SAT ,Pull-up drive strength code saturated due to termination strength adjustment setting in ZQ1PR" "Not saturated,Saturated" bitfld.long 0x00 11. " PD_DRV_SAT ,Pull-down drive strength code saturated due to drive strength adjustment setting in ZQ1PR" "Not saturated,Saturated" bitfld.long 0x00 10. " PU_DRV_SAT ,Pull-up drive strength code saturated due to drive strength adjustment setting in ZQ1PR" "Not saturated,Saturated" newline bitfld.long 0x00 9. " ZDONE ,Impedance calibration done" "Not done,Done" bitfld.long 0x00 8. " ZERR ,Impedance calibration error" "No error,Error" bitfld.long 0x00 6.--7. " OPU ,On-die termination ODT pull-up calibration status" "0,1,2,3" bitfld.long 0x00 4.--5. " OPD ,On-die termination ODT pull-down calibration status" "0,1,2,3" newline bitfld.long 0x00 2.--3. " ZPU ,Output impedance pull-up calibration status" "0,1,2,3" bitfld.long 0x00 0.--1. " ZPD ,Output impedance pull-down calibration status" "0,1,2,3" group.long 0x6C4++0x07 line.long 0x00 "ZQ2PR0,ZQ 2 Impedance Control Program Register 0" bitfld.long 0x00 31. " PD_DRV_ZDEN ,Pull-down drive strength ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 30. " PU_DRV_ZDEN ,Pull-up drive strength ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 29. " PD_ODT_ZDEN ,Pull-down termination ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 28. " PU_ODT_ZDEN ,Pull-up termination ZCTRL override enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " ZSEGBYP ,Calibration segment bypass" "Not bypassed,Bypassed" bitfld.long 0x00 25.--26. " ZLE_MODE ,VREF latch mode" "0,1,2,3" bitfld.long 0x00 22.--24. " ODT_ADJUST ,Termination adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19.--21. " PD_DRV_ADJUST ,Pull-down drive strength adjustment" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. " PU_DRV_ADJUST ,Pull-up drive strength adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--15. " ZPROG_DRAM_ODT ,DRAM impedance divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " ZPROG_HOST_ODT ,HOST impedance divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " ZPROG_ASYM_DRV_PD ,Impedance divide ratio pull-down drive calibration during asymmetric drive strength calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " ZPROG_ASYM_DRV_PU ,Impedance divide ratio (pull-up drive calibration during asymmetric drive strength calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ZQ2PR1,ZQ 2 Impedance Control Program Register 1" hexmask.long.byte 0x04 8.--14. 1. " PU_REFSEL ,Pull-up REFSEL for PZCTRL cell" hexmask.long.byte 0x04 0.--6. 1. " PD_REFSEL ,Pull-down REFSEL for PZCTRL cell" rgroup.long (0x6C4+0x08)++0x07 line.long 0x00 "ZQ2DR0,ZQ 2 Impedance Control Data Register 0" hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_RESULT ,Pull-up drive strength calibration code result" hexmask.long.word 0x00 0.--9. 1. " ZDATA_PD_DRV_RESULT ,Pull-down drive strength calibration code result" line.long 0x04 "ZQ2DR1,ZQ 2 Impedance Control Data Register 1" hexmask.long.word 0x04 16.--25. 1. " ZDATA_PU_ODT_RESULT ,Pull-up termination calibration code result" hexmask.long.word 0x04 0.--9. 1. " ZDATA_PD_ODT_RESULT ,Pull-down termination calibration code result" group.long (0x6C4+0x10)++0x07 line.long 0x00 "ZQ2OR0,ZQ 2 Impedance Control Override Data Register 0" hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_OVRD ,Override value for the pull-up output impedance" hexmask.long.word 0x00 0.--9. 1. " ZDATA_PD_DRV_OVRD ,Override value for the pull-down output impedance" line.long 0x04 "ZQ2OR1,ZQ 2 Impedance Control Override Data Register 1" hexmask.long.word 0x04 16.--25. 1. " ZDATA_PU_ODT_OVRD ,Override value for the pull-up termination" hexmask.long.word 0x04 0.--9. 1. " ZDATA_PD_ODT_OVRD ,Override value for the pull-down termination" rgroup.long (0x6C4+0x18)++0x03 line.long 0x00 "ZQ2SR,ZQ 2 Impedance Control Status Register" bitfld.long 0x00 13. " PD_ODT_SAT ,Pull-down drive strength code saturated due to termination strength adjustment setting in ZQ2PR" "Not saturated,Saturated" bitfld.long 0x00 12. " PU_ODT_SAT ,Pull-up drive strength code saturated due to termination strength adjustment setting in ZQ2PR" "Not saturated,Saturated" bitfld.long 0x00 11. " PD_DRV_SAT ,Pull-down drive strength code saturated due to drive strength adjustment setting in ZQ2PR" "Not saturated,Saturated" bitfld.long 0x00 10. " PU_DRV_SAT ,Pull-up drive strength code saturated due to drive strength adjustment setting in ZQ2PR" "Not saturated,Saturated" newline bitfld.long 0x00 9. " ZDONE ,Impedance calibration done" "Not done,Done" bitfld.long 0x00 8. " ZERR ,Impedance calibration error" "No error,Error" bitfld.long 0x00 6.--7. " OPU ,On-die termination ODT pull-up calibration status" "0,1,2,3" bitfld.long 0x00 4.--5. " OPD ,On-die termination ODT pull-down calibration status" "0,1,2,3" newline bitfld.long 0x00 2.--3. " ZPU ,Output impedance pull-up calibration status" "0,1,2,3" bitfld.long 0x00 0.--1. " ZPD ,Output impedance pull-down calibration status" "0,1,2,3" rgroup.long 0x6E4++0x07 line.long 0x00 "ZQ3PR0,ZQ 3 Impedance Control Program Register 0" bitfld.long 0x00 31. " PD_DRV_ZDEN ,Pull-down drive strength ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 30. " PU_DRV_ZDEN ,Pull-up drive strength ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 29. " PD_ODT_ZDEN ,Pull-down termination ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 28. " PU_ODT_ZDEN ,Pull-up termination ZCTRL override enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " ZSEGBYP ,Calibration segment bypass" "Not bypassed,Bypassed" bitfld.long 0x00 25.--26. " ZLE_MODE ,VREF latch mode" "0,1,2,3" bitfld.long 0x00 22.--24. " ODT_ADJUST ,Termination adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19.--21. " PD_DRV_ADJUST ,Pull-down drive strength adjustment" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. " PU_DRV_ADJUST ,Pull-up drive strength adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--15. " ZPROG_DRAM_ODT ,DRAM impedance divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " ZPROG_HOST_ODT ,HOST impedance divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " ZPROG_ASYM_DRV_PD ,Impedance divide ratio pull-down drive calibration during asymmetric drive strength calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " ZPROG_ASYM_DRV_PU ,Impedance divide ratio (pull-up drive calibration during asymmetric drive strength calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ZQ3PR1,ZQ 3 Impedance Control Program Register 1" hexmask.long.byte 0x04 8.--14. 1. " PU_REFSEL ,Pull-up REFSEL for PZCTRL cell" hexmask.long.byte 0x04 0.--6. 1. " PD_REFSEL ,Pull-down REFSEL for PZCTRL cell" rgroup.long (0x6E4+0x08)++0x07 line.long 0x00 "ZQ3DR0,ZQ 3 Impedance Control Data Register 0" hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_RESULT ,Pull-up drive strength calibration code result" hexmask.long.word 0x00 0.--9. 1. " ZDATA_PD_DRV_RESULT ,Pull-down drive strength calibration code result" line.long 0x04 "ZQ3DR1,ZQ 3 Impedance Control Data Register 1" hexmask.long.word 0x04 16.--25. 1. " ZDATA_PU_ODT_RESULT ,Pull-up termination calibration code result" hexmask.long.word 0x04 0.--9. 1. " ZDATA_PD_ODT_RESULT ,Pull-down termination calibration code result" rgroup.long (0x6E4+0x10)++0x07 line.long 0x00 "ZQ3OR0,ZQ 3 Impedance Control Override Data Register 0" hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_OVRD ,Override value for the pull-up output impedance" hexmask.long.word 0x00 0.--9. 1. " ZDATA_PD_DRV_OVRD ,Override value for the pull-down output impedance" line.long 0x04 "ZQ3OR1,ZQ 3 Impedance Control Override Data Register 1" hexmask.long.word 0x04 16.--25. 1. " ZDATA_PU_ODT_OVRD ,Override value for the pull-up termination" hexmask.long.word 0x04 0.--9. 1. " ZDATA_PD_ODT_OVRD ,Override value for the pull-down termination" rgroup.long (0x6E4+0x18)++0x03 line.long 0x00 "ZQ3SR,ZQ 3 Impedance Control Status Register" bitfld.long 0x00 13. " PD_ODT_SAT ,Pull-down drive strength code saturated due to termination strength adjustment setting in ZQ3PR" "Not saturated,Saturated" bitfld.long 0x00 12. " PU_ODT_SAT ,Pull-up drive strength code saturated due to termination strength adjustment setting in ZQ3PR" "Not saturated,Saturated" bitfld.long 0x00 11. " PD_DRV_SAT ,Pull-down drive strength code saturated due to drive strength adjustment setting in ZQ3PR" "Not saturated,Saturated" bitfld.long 0x00 10. " PU_DRV_SAT ,Pull-up drive strength code saturated due to drive strength adjustment setting in ZQ3PR" "Not saturated,Saturated" newline bitfld.long 0x00 9. " ZDONE ,Impedance calibration done" "Not done,Done" bitfld.long 0x00 8. " ZERR ,Impedance calibration error" "No error,Error" bitfld.long 0x00 6.--7. " OPU ,On-die termination ODT pull-up calibration status" "0,1,2,3" bitfld.long 0x00 4.--5. " OPD ,On-die termination ODT pull-down calibration status" "0,1,2,3" newline bitfld.long 0x00 2.--3. " ZPU ,Output impedance pull-up calibration status" "0,1,2,3" bitfld.long 0x00 0.--1. " ZPD ,Output impedance pull-down calibration status" "0,1,2,3" newline group.long 0x700++0x1F line.long 0x00 "DX0GCR0,DATX8 0 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX0GCR1,DATX8 0 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX0GCR2,DATX8 0 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX0GCR3,DATX8 0 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX0GCR4,DATX8 0 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX0GCR5,DATX8 0 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX0GCR6,DATX8 0 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX0GCR7,DATX8 0 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" group.long (0x700+0x28)++0x07 line.long 0x00 "DX0DQMAP0,DATX8 0 DQ/DM Mapping Register 0" rbitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW0DQMAP1,DATX8 0 DQ/DM Mapping Register 1" rbitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x700+0x40)++0x0B line.long 0x00 "DX0BDLR0,DATX8 0 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX0BDLR1,DATX8 0 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX0BDLR2,DATX8 0 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x700+0x50)++0x0B line.long 0x00 "DX0BDLR3,DATX8 0 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX0BDLR4,DATX8 0 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX0BDLR5,DATX8 0 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x700+0x60)++0x03 line.long 0x00 "DX0BDLR6,DATX8 0 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x700+0x80)++0x17 line.long 0x00 "DX0LCDLR0,DATX8 0 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX0LCDLR1,DATX8 0 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX0LCDLR2,DATX8 0 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX0LCDLR3,DATX8 0 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX0LCDLR4,DATX8 0 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX0LCDLR5,DATX8 0 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" group.long (0x700+0xA0)++0x07 line.long 0x00 "DX0MDLR0,DATX8 0 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX0MDLR1,DATX8 0 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" group.long (0x700+0xC0)++0x03 line.long 0x00 "DX0GTR0,DATX8 0 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0x700+0xD0)++0x1F line.long 0x00 "DX0RSR0,DATX8 0 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX0RSR1,DATX8 0 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX0RSR2,DATX8 0 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX0RSR3,DATX8 0 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX0GSR0,DATX8 0 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX0GSR1,DATX8 0 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX0GSR2,DATX8 0 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX0GSR3,DATX8 0 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" group.long 0x800++0x1F line.long 0x00 "DX1GCR0,DATX8 1 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX1GCR1,DATX8 1 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX1GCR2,DATX8 1 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX1GCR3,DATX8 1 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX1GCR4,DATX8 1 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX1GCR5,DATX8 1 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX1GCR6,DATX8 1 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX1GCR7,DATX8 1 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" group.long (0x800+0x28)++0x07 line.long 0x00 "DX1DQMAP0,DATX8 1 DQ/DM Mapping Register 0" rbitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW1DQMAP1,DATX8 1 DQ/DM Mapping Register 1" rbitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x800+0x40)++0x0B line.long 0x00 "DX1BDLR0,DATX8 1 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX1BDLR1,DATX8 1 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX1BDLR2,DATX8 1 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x800+0x50)++0x0B line.long 0x00 "DX1BDLR3,DATX8 1 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX1BDLR4,DATX8 1 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX1BDLR5,DATX8 1 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x800+0x60)++0x03 line.long 0x00 "DX1BDLR6,DATX8 1 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x800+0x80)++0x17 line.long 0x00 "DX1LCDLR0,DATX8 1 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX1LCDLR1,DATX8 1 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX1LCDLR2,DATX8 1 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX1LCDLR3,DATX8 1 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX1LCDLR4,DATX8 1 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX1LCDLR5,DATX8 1 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" group.long (0x800+0xA0)++0x07 line.long 0x00 "DX1MDLR0,DATX8 1 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX1MDLR1,DATX8 1 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" group.long (0x800+0xC0)++0x03 line.long 0x00 "DX1GTR0,DATX8 1 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0x800+0xD0)++0x1F line.long 0x00 "DX1RSR0,DATX8 1 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX1RSR1,DATX8 1 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX1RSR2,DATX8 1 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX1RSR3,DATX8 1 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX1GSR0,DATX8 1 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX1GSR1,DATX8 1 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX1GSR2,DATX8 1 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX1GSR3,DATX8 1 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" group.long 0x900++0x1F line.long 0x00 "DX2GCR0,DATX8 2 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX2GCR1,DATX8 2 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX2GCR2,DATX8 2 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX2GCR3,DATX8 2 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX2GCR4,DATX8 2 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX2GCR5,DATX8 2 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX2GCR6,DATX8 2 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX2GCR7,DATX8 2 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" group.long (0x900+0x28)++0x07 line.long 0x00 "DX2DQMAP0,DATX8 2 DQ/DM Mapping Register 0" rbitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW2DQMAP1,DATX8 2 DQ/DM Mapping Register 1" rbitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x900+0x40)++0x0B line.long 0x00 "DX2BDLR0,DATX8 2 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX2BDLR1,DATX8 2 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX2BDLR2,DATX8 2 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x900+0x50)++0x0B line.long 0x00 "DX2BDLR3,DATX8 2 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX2BDLR4,DATX8 2 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX2BDLR5,DATX8 2 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x900+0x60)++0x03 line.long 0x00 "DX2BDLR6,DATX8 2 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x900+0x80)++0x17 line.long 0x00 "DX2LCDLR0,DATX8 2 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX2LCDLR1,DATX8 2 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX2LCDLR2,DATX8 2 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX2LCDLR3,DATX8 2 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX2LCDLR4,DATX8 2 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX2LCDLR5,DATX8 2 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" group.long (0x900+0xA0)++0x07 line.long 0x00 "DX2MDLR0,DATX8 2 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX2MDLR1,DATX8 2 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" group.long (0x900+0xC0)++0x03 line.long 0x00 "DX2GTR0,DATX8 2 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0x900+0xD0)++0x1F line.long 0x00 "DX2RSR0,DATX8 2 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX2RSR1,DATX8 2 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX2RSR2,DATX8 2 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX2RSR3,DATX8 2 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX2GSR0,DATX8 2 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX2GSR1,DATX8 2 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX2GSR2,DATX8 2 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX2GSR3,DATX8 2 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" group.long 0xA00++0x1F line.long 0x00 "DX3GCR0,DATX8 3 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX3GCR1,DATX8 3 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX3GCR2,DATX8 3 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX3GCR3,DATX8 3 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX3GCR4,DATX8 3 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX3GCR5,DATX8 3 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX3GCR6,DATX8 3 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX3GCR7,DATX8 3 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" group.long (0xA00+0x28)++0x07 line.long 0x00 "DX3DQMAP0,DATX8 3 DQ/DM Mapping Register 0" rbitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW3DQMAP1,DATX8 3 DQ/DM Mapping Register 1" rbitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0xA00+0x40)++0x0B line.long 0x00 "DX3BDLR0,DATX8 3 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX3BDLR1,DATX8 3 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX3BDLR2,DATX8 3 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0xA00+0x50)++0x0B line.long 0x00 "DX3BDLR3,DATX8 3 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX3BDLR4,DATX8 3 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX3BDLR5,DATX8 3 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0xA00+0x60)++0x03 line.long 0x00 "DX3BDLR6,DATX8 3 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0xA00+0x80)++0x17 line.long 0x00 "DX3LCDLR0,DATX8 3 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX3LCDLR1,DATX8 3 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX3LCDLR2,DATX8 3 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX3LCDLR3,DATX8 3 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX3LCDLR4,DATX8 3 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX3LCDLR5,DATX8 3 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" group.long (0xA00+0xA0)++0x07 line.long 0x00 "DX3MDLR0,DATX8 3 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX3MDLR1,DATX8 3 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" group.long (0xA00+0xC0)++0x03 line.long 0x00 "DX3GTR0,DATX8 3 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0xA00+0xD0)++0x1F line.long 0x00 "DX3RSR0,DATX8 3 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX3RSR1,DATX8 3 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX3RSR2,DATX8 3 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX3RSR3,DATX8 3 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX3GSR0,DATX8 3 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX3GSR1,DATX8 3 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX3GSR2,DATX8 3 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX3GSR3,DATX8 3 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" rgroup.long 0xB00++0x1F line.long 0x00 "DX4GCR0,DATX8 4 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX4GCR1,DATX8 4 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX4GCR2,DATX8 4 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX4GCR3,DATX8 4 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX4GCR4,DATX8 4 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX4GCR5,DATX8 4 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX4GCR6,DATX8 4 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX4GCR7,DATX8 4 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" rgroup.long (0xB00+0x28)++0x07 line.long 0x00 "DX4DQMAP0,DATX8 4 DQ/DM Mapping Register 0" bitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW4DQMAP1,DATX8 4 DQ/DM Mapping Register 1" bitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0xB00+0x40)++0x0B line.long 0x00 "DX4BDLR0,DATX8 4 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX4BDLR1,DATX8 4 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX4BDLR2,DATX8 4 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xB00+0x50)++0x0B line.long 0x00 "DX4BDLR3,DATX8 4 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX4BDLR4,DATX8 4 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX4BDLR5,DATX8 4 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xB00+0x60)++0x03 line.long 0x00 "DX4BDLR6,DATX8 4 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xB00+0x80)++0x17 line.long 0x00 "DX4LCDLR0,DATX8 4 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX4LCDLR1,DATX8 4 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX4LCDLR2,DATX8 4 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX4LCDLR3,DATX8 4 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX4LCDLR4,DATX8 4 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX4LCDLR5,DATX8 4 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" rgroup.long (0xB00+0xA0)++0x07 line.long 0x00 "DX4MDLR0,DATX8 4 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX4MDLR1,DATX8 4 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" rgroup.long (0xB00+0xC0)++0x03 line.long 0x00 "DX4GTR0,DATX8 4 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0xB00+0xD0)++0x1F line.long 0x00 "DX4RSR0,DATX8 4 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX4RSR1,DATX8 4 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX4RSR2,DATX8 4 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX4RSR3,DATX8 4 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX4GSR0,DATX8 4 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX4GSR1,DATX8 4 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX4GSR2,DATX8 4 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX4GSR3,DATX8 4 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" rgroup.long 0xC00++0x1F line.long 0x00 "DX5GCR0,DATX8 5 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX5GCR1,DATX8 5 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX5GCR2,DATX8 5 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX5GCR3,DATX8 5 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX5GCR4,DATX8 5 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX5GCR5,DATX8 5 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX5GCR6,DATX8 5 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX5GCR7,DATX8 5 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" rgroup.long (0xC00+0x28)++0x07 line.long 0x00 "DX5DQMAP0,DATX8 5 DQ/DM Mapping Register 0" bitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW5DQMAP1,DATX8 5 DQ/DM Mapping Register 1" bitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0xC00+0x40)++0x0B line.long 0x00 "DX5BDLR0,DATX8 5 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX5BDLR1,DATX8 5 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX5BDLR2,DATX8 5 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xC00+0x50)++0x0B line.long 0x00 "DX5BDLR3,DATX8 5 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX5BDLR4,DATX8 5 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX5BDLR5,DATX8 5 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xC00+0x60)++0x03 line.long 0x00 "DX5BDLR6,DATX8 5 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xC00+0x80)++0x17 line.long 0x00 "DX5LCDLR0,DATX8 5 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX5LCDLR1,DATX8 5 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX5LCDLR2,DATX8 5 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX5LCDLR3,DATX8 5 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX5LCDLR4,DATX8 5 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX5LCDLR5,DATX8 5 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" rgroup.long (0xC00+0xA0)++0x07 line.long 0x00 "DX5MDLR0,DATX8 5 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX5MDLR1,DATX8 5 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" rgroup.long (0xC00+0xC0)++0x03 line.long 0x00 "DX5GTR0,DATX8 5 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0xC00+0xD0)++0x1F line.long 0x00 "DX5RSR0,DATX8 5 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX5RSR1,DATX8 5 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX5RSR2,DATX8 5 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX5RSR3,DATX8 5 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX5GSR0,DATX8 5 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX5GSR1,DATX8 5 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX5GSR2,DATX8 5 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX5GSR3,DATX8 5 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" rgroup.long 0xD00++0x1F line.long 0x00 "DX6GCR0,DATX8 6 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX6GCR1,DATX8 6 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX6GCR2,DATX8 6 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX6GCR3,DATX8 6 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX6GCR4,DATX8 6 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX6GCR5,DATX8 6 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX6GCR6,DATX8 6 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX6GCR7,DATX8 6 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" rgroup.long (0xD00+0x28)++0x07 line.long 0x00 "DX6DQMAP0,DATX8 6 DQ/DM Mapping Register 0" bitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW6DQMAP1,DATX8 6 DQ/DM Mapping Register 1" bitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0xD00+0x40)++0x0B line.long 0x00 "DX6BDLR0,DATX8 6 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX6BDLR1,DATX8 6 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX6BDLR2,DATX8 6 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xD00+0x50)++0x0B line.long 0x00 "DX6BDLR3,DATX8 6 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX6BDLR4,DATX8 6 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX6BDLR5,DATX8 6 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xD00+0x60)++0x03 line.long 0x00 "DX6BDLR6,DATX8 6 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xD00+0x80)++0x17 line.long 0x00 "DX6LCDLR0,DATX8 6 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX6LCDLR1,DATX8 6 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX6LCDLR2,DATX8 6 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX6LCDLR3,DATX8 6 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX6LCDLR4,DATX8 6 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX6LCDLR5,DATX8 6 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" rgroup.long (0xD00+0xA0)++0x07 line.long 0x00 "DX6MDLR0,DATX8 6 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX6MDLR1,DATX8 6 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" rgroup.long (0xD00+0xC0)++0x03 line.long 0x00 "DX6GTR0,DATX8 6 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0xD00+0xD0)++0x1F line.long 0x00 "DX6RSR0,DATX8 6 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX6RSR1,DATX8 6 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX6RSR2,DATX8 6 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX6RSR3,DATX8 6 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX6GSR0,DATX8 6 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX6GSR1,DATX8 6 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX6GSR2,DATX8 6 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX6GSR3,DATX8 6 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" rgroup.long 0xE00++0x1F line.long 0x00 "DX7GCR0,DATX8 7 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX7GCR1,DATX8 7 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX7GCR2,DATX8 7 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX7GCR3,DATX8 7 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX7GCR4,DATX8 7 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX7GCR5,DATX8 7 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX7GCR6,DATX8 7 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX7GCR7,DATX8 7 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" rgroup.long (0xE00+0x28)++0x07 line.long 0x00 "DX7DQMAP0,DATX8 7 DQ/DM Mapping Register 0" bitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW7DQMAP1,DATX8 7 DQ/DM Mapping Register 1" bitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0xE00+0x40)++0x0B line.long 0x00 "DX7BDLR0,DATX8 7 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX7BDLR1,DATX8 7 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX7BDLR2,DATX8 7 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xE00+0x50)++0x0B line.long 0x00 "DX7BDLR3,DATX8 7 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX7BDLR4,DATX8 7 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX7BDLR5,DATX8 7 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xE00+0x60)++0x03 line.long 0x00 "DX7BDLR6,DATX8 7 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xE00+0x80)++0x17 line.long 0x00 "DX7LCDLR0,DATX8 7 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX7LCDLR1,DATX8 7 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX7LCDLR2,DATX8 7 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX7LCDLR3,DATX8 7 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX7LCDLR4,DATX8 7 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX7LCDLR5,DATX8 7 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" rgroup.long (0xE00+0xA0)++0x07 line.long 0x00 "DX7MDLR0,DATX8 7 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX7MDLR1,DATX8 7 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" rgroup.long (0xE00+0xC0)++0x03 line.long 0x00 "DX7GTR0,DATX8 7 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0xE00+0xD0)++0x1F line.long 0x00 "DX7RSR0,DATX8 7 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX7RSR1,DATX8 7 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX7RSR2,DATX8 7 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX7RSR3,DATX8 7 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX7GSR0,DATX8 7 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX7GSR1,DATX8 7 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX7GSR2,DATX8 7 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX7GSR3,DATX8 7 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" rgroup.long 0xF00++0x1F line.long 0x00 "DX8GCR0,DATX8 8 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX8GCR1,DATX8 8 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX8GCR2,DATX8 8 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX8GCR3,DATX8 8 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX8GCR4,DATX8 8 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX8GCR5,DATX8 8 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX8GCR6,DATX8 8 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX8GCR7,DATX8 8 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" rgroup.long (0xF00+0x28)++0x07 line.long 0x00 "DX8DQMAP0,DATX8 8 DQ/DM Mapping Register 0" bitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW8DQMAP1,DATX8 8 DQ/DM Mapping Register 1" bitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0xF00+0x40)++0x0B line.long 0x00 "DX8BDLR0,DATX8 8 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX8BDLR1,DATX8 8 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX8BDLR2,DATX8 8 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xF00+0x50)++0x0B line.long 0x00 "DX8BDLR3,DATX8 8 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX8BDLR4,DATX8 8 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX8BDLR5,DATX8 8 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xF00+0x60)++0x03 line.long 0x00 "DX8BDLR6,DATX8 8 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xF00+0x80)++0x17 line.long 0x00 "DX8LCDLR0,DATX8 8 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX8LCDLR1,DATX8 8 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX8LCDLR2,DATX8 8 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX8LCDLR3,DATX8 8 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX8LCDLR4,DATX8 8 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX8LCDLR5,DATX8 8 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" rgroup.long (0xF00+0xA0)++0x07 line.long 0x00 "DX8MDLR0,DATX8 8 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX8MDLR1,DATX8 8 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" rgroup.long (0xF00+0xC0)++0x03 line.long 0x00 "DX8GTR0,DATX8 8 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0xF00+0xD0)++0x1F line.long 0x00 "DX8RSR0,DATX8 8 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX8RSR1,DATX8 8 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX8RSR2,DATX8 8 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX8RSR3,DATX8 8 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX8GSR0,DATX8 8 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX8GSR1,DATX8 8 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX8GSR2,DATX8 8 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX8GSR3,DATX8 8 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" newline group.long 0x1400++0x1F line.long 0x00 "DX8SL0OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode write-data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode write-leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL0PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL0PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL0PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL0PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL0PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL0PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL0DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path rise-to-rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path rise-to-rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x1400+0x24)++0x0F line.long 0x00 "DX8SL0DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL0DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL0DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during postamble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during preamble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL0IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" group.long 0x1440++0x1F line.long 0x00 "DX8SL1OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode write-data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode write-leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL1PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL1PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL1PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL1PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL1PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL1PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL1DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path rise-to-rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path rise-to-rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x1440+0x24)++0x0F line.long 0x00 "DX8SL1DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL1DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL1DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during postamble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during preamble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL1IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" group.long 0x1480++0x1F line.long 0x00 "DX8SL2OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode write-data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode write-leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL2PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL2PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL2PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL2PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL2PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL2PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL2DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path rise-to-rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path rise-to-rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x1480+0x24)++0x0F line.long 0x00 "DX8SL2DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL2DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL2DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during postamble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during preamble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL2IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" rgroup.long 0x14C0++0x1F line.long 0x00 "DX8SL3OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode Write-Data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode Write-Leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL3PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable ATOEN" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL3PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL3PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL3PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL3PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL3PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL3DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0x14C0+0x24)++0x0F line.long 0x00 "DX8SL3DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL3DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL3DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during Post-amble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during Pre-amble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL3IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" rgroup.long 0x1500++0x1F line.long 0x00 "DX8SL4OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode Write-Data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode Write-Leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL4PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable ATOEN" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL4PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL4PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL4PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL4PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL4PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL4DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0x1500+0x24)++0x0F line.long 0x00 "DX8SL4DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL4DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL4DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during Post-amble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during Pre-amble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL4IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" rgroup.long 0x1540++0x1F line.long 0x00 "DX8SL5OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode Write-Data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode Write-Leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL5PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable ATOEN" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL5PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL5PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL5PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL5PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL5PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL5DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0x1540+0x24)++0x0F line.long 0x00 "DX8SL5DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL5DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL5DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during Post-amble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during Pre-amble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL5IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" rgroup.long 0x1580++0x1F line.long 0x00 "DX8SL6OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode Write-Data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode Write-Leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL6PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable ATOEN" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL6PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL6PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL6PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL6PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL6PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL6DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0x1580+0x24)++0x0F line.long 0x00 "DX8SL6DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL6DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL6DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during Post-amble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during Pre-amble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL6IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" rgroup.long 0x15C0++0x1F line.long 0x00 "DX8SL7OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode Write-Data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode Write-Leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL7PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable ATOEN" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL7PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL7PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL7PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL7PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL7PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL7DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0x15C0+0x24)++0x0F line.long 0x00 "DX8SL7DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL7DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL7DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during Post-amble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during Pre-amble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL7IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" rgroup.long 0x1600++0x1F line.long 0x00 "DX8SL8OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode Write-Data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode Write-Leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL8PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable ATOEN" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL8PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL8PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL8PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL8PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL8PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL8DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0x1600+0x24)++0x0F line.long 0x00 "DX8SL8DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL8DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL8DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during Post-amble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during Pre-amble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL8IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" wgroup.long 0x17C0++0x1F line.long 0x00 "DX8SLBOSC,DATX8 0-8 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode write-data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode write-leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SLBPLLCR0,DAXT8 0-8 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable ATOEN" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SLBPLLCR1,DAXT8 0-8 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypassed,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SLBPLLCR2,DAXT8 0-8 PLL Control Register 2" line.long 0x10 "DX8SLBPLLCR3,DAXT8 0-8 PLL Control Register 3" line.long 0x14 "DX8SLBPLLCR4,DAXT8 0-8 PLL Control Register 4" line.long 0x18 "DX8SLBPLLCR5,DAXT8 0-8 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SLBDQSCTL,DATX8 0-8 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path rise-to-rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path rise-to-rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS# resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.long 0x17E4++0x0F line.long 0x00 "DX8SLBDDLCTL,DATX8 0-8 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SLBDXCTL1,DATX8 0-8 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SLBDXCTL2,DATX8 0-8 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during postamble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during preamble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "No bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No reset,Reset" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SLBIOCR,DATX8 0-8 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" width 0x0B tree.end tree "DDRC0_3 (DDR Controller)" base ad:0x5C000000 width 18. group.long 0x00++0x03 line.long 0x00 "MSTR,Master Register" bitfld.long 0x00 30.--31. " DEVICE_CONFIG ,Indicates the configuration of the device used in the system" "x4,x8,x16,x32" bitfld.long 0x00 29. " FREQUENCY_MODE ,Choose which registers are used" "Original,Shadow" newline bitfld.long 0x00 24.--25. " ACTIVE_RANKS ,Only present for multi-rank configurations" ",One rank,,Two rank" bitfld.long 0x00 22. " FREQUENCY_RATIO ,Selects the frequency ratio" "1:2 mode,1:1 mode" newline bitfld.long 0x00 16.--19. " BURST_RDWR ,Controls the burst size used to access the SDRAM" ",2,4,,8,,,,16,?..." bitfld.long 0x00 15. " DLL_OFF_MODE ,Indicates whether the DDRC and DRAM have to be put in DLL-off mode" "On mode,Off mode" newline bitfld.long 0x00 12.--13. " DATA_BUS_WIDTH ,Selects proportion of DQ bus width that is used by the SDRAM" "Full,Half,Quarter,?..." bitfld.long 0x00 11. " GEARDOWN_MODE ,DRAM mode" "Normal,Geardown" newline bitfld.long 0x00 10. " EN_2T_TIMING_MODE ,Enable 2T timing" "Disabled,Enabled" bitfld.long 0x00 9. " BURSTCHOP ,Burst-chop in DDR3/DDR4" "Disabled,Enabled" newline bitfld.long 0x00 5. " LPDDR4 ,Select LPDDR4 SDRAM" "Non-LPDDR4,LPDDR4" bitfld.long 0x00 3. " LPDDR3 ,Select LPDDR3 SDRAM" "Non-LPDDR3,LPDDR3" newline bitfld.long 0x00 2. " LPDDR2 ,Select LPDDR2 SDRAM" "Non-LPDDR2,LPDDR2" bitfld.long 0x00 0. " DDR3 ,Select DDR3 SDRAM" "Non-DDR3,DDR3" if (((per.l(ad:0x5C000000))&0x20)==0x20) rgroup.long 0x04++0x03 line.long 0x00 "STAT,Operating Mode Status Register" bitfld.long 0x00 8.--9. " SELFREF_STATE ,Self refresh state" "No self refresh,Self refresh 1,Self refresh power down,Self refresh" bitfld.long 0x00 4.--5. " SELFREF_TYPE ,SR-powerdown type" "Not in SR-powerdown,,Caused not only by automatic SR control,Caused only by automatic SR control" newline bitfld.long 0x00 0.--2. " OPERATING_MODE ,Operating mode" "Init,Normal,Power-down,Self refresh power-down,?..." elif (((per.l(ad:0x5C000000))&0x10)==0x10) rgroup.long 0x04++0x03 line.long 0x00 "STAT,Operating Mode Status Register" bitfld.long 0x00 8.--9. " SELFREF_STATE ,Self refresh state" "No self refresh,Self refresh 1,Self refresh power down,Self refresh" bitfld.long 0x00 4.--5. " SELFREF_TYPE ,Self refresh type" "Not in self refresh,,Caused not only by automatic SR control,Caused only by automatic SR control" newline bitfld.long 0x00 0.--2. " OPERATING_MODE ,Operating mode" "Init,Normal,Power-down,Self refresh,Deep power-down,Deep power-down,Deep power-down,Deep power-down" else rgroup.long 0x04++0x03 line.long 0x00 "STAT,Operating Mode Status Register" bitfld.long 0x00 8.--9. " SELFREF_STATE ,Self refresh state" "No self refresh,Self refresh 1,Self refresh power down,Self refresh" bitfld.long 0x00 4.--5. " SELFREF_TYPE ,Self refresh type" "Not in self refresh,,Caused not only by automatic SR control,Caused only by automatic SR control" newline bitfld.long 0x00 0.--1. " OPERATING_MODE ,Operating mode" "Init,Normal,Power-down,Self refresh" endif group.long 0x08++0x0F line.long 0x00 "MSTR1,Operating Mode Status Register 1" bitfld.long 0x00 16. " ALT_ADDRMAP_EN ,Enable alternative address map" "Disabled,Enabled" bitfld.long 0x00 1. " RANK_TMGREG_SEL[1] ,Indicates which register set is used for each rank" "Disabled,Enabled" newline bitfld.long 0x00 0. " [0] ,Indicates which register set is used for each rank" "Disabled,Enabled" line.long 0x04 "MRCTRL3,Operating Mode Status Register 3" bitfld.long 0x04 0.--1. " MR_RANK_SEL ,Controls which rank is accessed by MRCTRL0.mr_wr" "0,1,2,3" line.long 0x08 "MRCTRL0,Mode Register Read/Write Control Register 0" bitfld.long 0x08 31. " MR_WR ,Triggers a mode register read or write operation" "Not Triggered,Triggered" bitfld.long 0x08 30. " PBA_MODE ,Indicates whether PBA access is executed" "Not executed,Executed" newline bitfld.long 0x08 12.--15. " MR_ADDR ,Address of the mode register that is to be written to" "MR0,MR1,MR2,MR3,MR4,MR5,MR6,MR7,?..." bitfld.long 0x08 4.--5. " MR_RANK ,Controls which ranks are accessed by MRCTRL0.MR_WR" "0,1,2,3" newline bitfld.long 0x08 3. " SW_INIT_INT ,Indicates whether Software intervention is allowed" "Not allowed,Allowed" bitfld.long 0x08 2. " PDA_EN ,Indicates whether the mode register operation is MRS in PDA mode" "MRS,MRS in per DRAM addressability" newline bitfld.long 0x08 1. " MPR_EN ,Indicates whether the mode register operation is MRS or WR/RD for MPR" "MRS,WR/RD for MPR" bitfld.long 0x08 0. " MR_TYPE ,Indicates whether the mode register operation is read or write" "Write,Read" line.long 0x0C "MRCTRL1,Mode Register Read/Write Control Register 1" hexmask.long.tbyte 0x0C 0.--17. 1. " MR_DATA ,Mode register write data" rgroup.long 0x18++0x03 line.long 0x00 "MRSTAT,Mode Register Read/Write Status Register" bitfld.long 0x00 8. " PDA_DONE ,The SoC core may initiate a MR write operation in PDA/PBA mod" "In progress,Completed" bitfld.long 0x00 0. " MR_WR_BUSY ,The SoC core may initiate a MR write operation" "SoC core can initiate write operation,Write operation in progress" group.long 0x1C++0x03 line.long 0x00 "MRCTRL2,Mode Register Read/Write Control Register 2" if (((per.l(ad:0x5C000000))&0x20)==0x20) group.long 0x20++0x07 line.long 0x00 "DERATEEN,Temperature Derate Enable Register" bitfld.long 0x00 8.--9. " RC_DERATE_VALUE ,Derate value of tRC for LPDDR4" "+1,+2,+3,+4" bitfld.long 0x00 4.--7. " DERATE_BYTE ,Indicates which byte of the MRR data is used for derating" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1. " DERATE_VALUE ,Derate value" "+1,+2" bitfld.long 0x00 0. " DERATE_ENABLE ,Enables derating" "Disabled,Enabled" line.long 0x04 "DERATEINT,Temperature Derate Interval Register" else hgroup.long 0x20++0x03 hide.long 0x00 "DERATEEN,Temperature Derate Enable Register" hgroup.long 0x24++0x03 hide.long 0x00 "DERATEINT,Temperature Derate Interval Register" endif group.long 0x30++0x0B line.long 0x00 "PWRCTL,Low Power Control Register" bitfld.long 0x00 6. " STAY_IN_SELFREF ,Transition from Self refresh state" "Allow,Prohibit" bitfld.long 0x00 5. " SELFREF_SW ,Software entry transition to/from Self-refresh" "Exited,Entered" newline bitfld.long 0x00 4. " MPSM_EN ,DDRC maximum power saving mode" "Disabled,Enabled" bitfld.long 0x00 3. " EN_DFI_DRAM_CLK_DISABLE ,Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM" "No,Yes" newline bitfld.long 0x00 2. " DEEPPOWERDOWN_EN ,Enable for deep power-down" "Disabled,Enabled" bitfld.long 0x00 1. " POWERDOWN_EN ,Enable for power-down" "Disabled,Enabled" newline bitfld.long 0x00 0. " SELFREF_EN ,Enable for self refresh" "Disabled,Enabled" line.long 0x04 "PWRTMG,Low Power Timing Register" hexmask.long.byte 0x04 16.--23. 1. " SELFREF_TO_X32 ,SELFREF_TO_X32" hexmask.long.byte 0x04 8.--15. 1. " T_DPD_X4096 ,Minimum deep power-down time" newline bitfld.long 0x04 0.--4. " POWERDOWN_TO_X32 ,After this many clocks of NOP or deselect the DDRC automatically puts the SDRAM into power-down" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "HWLPCTL,Hardware Low Power Control Register" hexmask.long.word 0x08 16.--27. 1. " HW_LP_IDLE_X32 ,Hardware idle period" bitfld.long 0x08 1. " HW_LP_EXIT_IDLE_EN ,Enable for exit from the automatic clock stop automatic power down or automatic self-refresh modes" "Disabled,Enabled" newline bitfld.long 0x08 0. " HW_LP_EN ,Enable for hardware low power interface" "Disabled,Enabled" if (((per.l(ad:0x5C000000))&0x20)==0x20) group.long 0x50++0x03 line.long 0x00 "RFSHCTL0,Refresh Control Register 0" bitfld.long 0x00 20.--23. " REFRESH_MARGIN ,Threshold value in number of clock cycles before the critical refresh or page timer expires" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--16. " REFRESH_TO_X32 ,Speculative refreshes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4.--8. " REFRESH_BURST ,Number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute" "1 refresh,2 refresh,3 refresh,4 refresh,5 refresh,6 refresh,7 refresh,8 refresh,9 refresh,10 refresh,11 refresh,12 refresh,13 refresh,14 refresh,15 refresh,16 refresh,17 refresh,18 refresh,19 refresh,20 refresh,21 refresh,22 refresh,23 refresh,24 refresh,25 refresh,26 refresh,27 refresh,28 refresh,29 refresh,30 refresh,31 refresh,32 refresh" bitfld.long 0x00 2. " PER_BANK_REFRESH ,Allows traffic to flow to other banks" "All bank refresh,Per bank refresh" else group.long 0x50++0x03 line.long 0x00 "RFSHCTL0,Refresh Control Register 0" bitfld.long 0x00 20.--23. " REFRESH_MARGIN ,Threshold value in number of clock cycles before the critical refresh or page timer expires" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--16. " REFRESH_TO_X32 ,Speculative refreshes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4.--8. " REFRESH_BURST ,Number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute" "1 refresh,2 refresh,3 refresh,4 refresh,5 refresh,6 refresh,7 refresh,8 refresh,9 refresh,10 refresh,11 refresh,12 refresh,13 refresh,14 refresh,15 refresh,16 refresh,17 refresh,18 refresh,19 refresh,20 refresh,21 refresh,22 refresh,23 refresh,24 refresh,25 refresh,26 refresh,27 refresh,28 refresh,29 refresh,30 refresh,31 refresh,32 refresh" endif group.long 0x54++0x03 line.long 0x00 "RFSHCTL1,Refresh Control Register 1" hexmask.long.word 0x00 16.--27. 1. " REFRESH_TIMER1_START_VALUE_X32 ,Refresh timer start for rank 1" hexmask.long.word 0x00 0.--11. 1. " REFRESH_TIMER0_START_VALUE_X32 ,Refresh timer start for rank 0" group.long 0x60++0x07 line.long 0x00 "RFSHCTL3,Refresh Control Register 3" bitfld.long 0x00 4.--6. " REFRESH_MODE ,Fine granularity refresh mode" "Fixed,Fixed 2x,Fixed x4,,,Enabled on the fly x2,Enabled on the fly x4,?..." bitfld.long 0x00 1. " REFRESH_UPDATE_LEVEL ,Indicates that the refresh Register(S) have been updated" "0,1" newline bitfld.long 0x00 0. " DIS_AUTO_REFRESH ,Disables auto-refresh generated by the DDRC" "No,Yes" line.long 0x04 "RFSHTMG,Refresh Timing Register" hexmask.long.word 0x04 16.--27. 1. " T_RFC_NOM_X32 ,Average time interval between refreshes per rank" hexmask.long.word 0x04 0.--9. 1. " T_RFC_MIN ,Minimum time from refresh to refresh or activate" group.long 0xD0++0x03 line.long 0x00 "INIT0,SDRAM Initialization Register 0" bitfld.long 0x00 30.--31. " SKIP_DRAM_INIT ,If lower bit is enabled the SDRAM initialization routine is skipped" "Run after power-up,Skipped after power-up,Run after power-up,Skipped after power-up" hexmask.long.word 0x00 16.--25. 1. " POST_CKE_X1024 ,Cycles to wait after driving CKE high to start the SDRAM initialization sequence" newline hexmask.long.word 0x00 0.--11. 1. " PRE_CKE_X1024 ,Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence" if ((((per.l(ad:0x5C000000))&0x20)==0x20)||(((per.l(ad:0x5C000000))&0x01)==0x01)) group.long 0xD4++0x03 line.long 0x00 "INIT1,SDRAM Initialization Register 1" hexmask.long.word 0x00 16.--24. 1. " DRAM_RSTN_X1024 ,Number of cycles to assert SDRAM reset signal during init sequence" bitfld.long 0x00 0.--3. " PRE_OCD_X32 ,Wait period before driving the OCD complete command to SDRAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0xD4++0x03 line.long 0x00 "INIT1,SDRAM Initialization Register 1" bitfld.long 0x00 0.--3. " PRE_OCD_X32 ,Wait period before driving the OCD complete command to SDRAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hgroup.long 0xD8++0x03 hide.long 0x00 "INIT2,SDRAM Initialization Register 2" group.long 0xDC++0x07 line.long 0x00 "INIT3,SDRAM Initialization Register 3" hexmask.long.word 0x00 16.--31. 1. " MR ,Value write to MR register" hexmask.long.word 0x00 0.--15. 1. " EMR ,Value write to EMR register" line.long 0x04 "INIT4,SDRAM Initialization Register 4" hexmask.long.word 0x04 16.--31. 1. " EMR2 ,Value write to EMR2 register" hexmask.long.word 0x04 0.--15. 1. " EMR3 ,Value write to EMR3 register" if (((per.l(ad:0x5C000000))&0x01)==0x01) group.long 0xE4++0x03 line.long 0x00 "INIT5,SDRAM Initialization Register 5" hexmask.long.byte 0x00 16.--23. 1. " DEV_ZQINIT_X32 ,ZQ initial calibration" hexmask.long.word 0x00 0.--9. 1. " MAX_AUTO_INIT_X_1024 ,Maximum duration of the auto initialization tINIT5" else hgroup.long 0xE4++0x03 hide.long 0x00 "INIT5,SDRAM Initialization Register 5" endif hgroup.long 0xE8++0x03 hide.long 0x00 "INIT6,SDRAM Initialization Register 6" hgroup.long 0xEC++0x03 hide.long 0x00 "INIT7,SDRAM Initialization Register 7" if (((per.l(ad:0x5C000000))&0x10)==0x10) group.long 0xF0++0x03 line.long 0x00 "DIMMCTL,DIMM Control Register" bitfld.long 0x00 6. " LRDIMM_BCOM_CMD_PROT ,Protects the timing restrictions" "0,1" bitfld.long 0x00 5. " DIMM_DIS_BG_MIRRORING ,Disabling address mirroring for BG bits" "Swapped,Not swapped" newline bitfld.long 0x00 4. " MRS_BG1_EN ,Enable for BG1 bit of MRS command" "Disabled,Enabled" bitfld.long 0x00 3. " MRS_A17_EN ,Enable for A17 bit of MRS command" "Disabled,Enabled" newline bitfld.long 0x00 2. " DIMM_OUTPUT_INV_EN ,Output inversion enable" "Disabled,Enabled" bitfld.long 0x00 1. " DIMM_ADDR_MIRR_EN ,Address mirroring enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DIMM_STAGGER_CS_EN ,Staggering enable for multi-rank accesses" "Disabled,Enabled" elif (((per.l(ad:0x5C000000))&0x20)==0x20) group.long 0xF0++0x03 line.long 0x00 "DIMMCTL,DIMM Control Register" bitfld.long 0x00 6. " LRDIMM_BCOM_CMD_PROT ,Protects the timing restrictions" "0,1" bitfld.long 0x00 5. " DIMM_DIS_BG_MIRRORING ,Disabling address mirroring for BG bits" "Swapped,Not swapped" newline bitfld.long 0x00 4. " MRS_BG1_EN ,Enable for BG1 bit of MRS command" "Disabled,Enabled" bitfld.long 0x00 3. " MRS_A17_EN ,Enable for A17 bit of MRS command" "Disabled,Enabled" newline bitfld.long 0x00 2. " DIMM_OUTPUT_INV_EN ,Output inversion enable" "Disabled,Enabled" else group.long 0xF0++0x03 line.long 0x00 "DIMMCTL,DIMM Control Register" bitfld.long 0x00 6. " LRDIMM_BCOM_CMD_PROT ,Protects the timing restrictions" "0,1" bitfld.long 0x00 5. " DIMM_DIS_BG_MIRRORING ,Disabling address mirroring for BG bits" "Swapped,Not swapped" newline bitfld.long 0x00 4. " MRS_BG1_EN ,Enable for BG1 bit of MRS command" "Disabled,Enabled" bitfld.long 0x00 3. " MRS_A17_EN ,Enable for A17 bit of MRS command" "Disabled,Enabled" endif group.long 0xF4++0x03 line.long 0x00 "RANKCTL,Rank Control Register" bitfld.long 0x00 8.--11. " DIFF_RANK_WR_GAP ,Only present for multi-rank configurations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DIFF_RANK_RD_GAP ,Only present for multi-rank configurations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " MAX_RANK_RD ,Only present for multi-rank configurations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x100++0x0B line.long 0x00 "DRAMTMG0,SDRAM Timing Register 0" hexmask.long.byte 0x00 24.--30. 1. " WR2PRE ,Minimum time between write and precharge to same bank" bitfld.long 0x00 16.--21. " T_FAW ,TFAW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x00 8.--14. 1. " T_RAS_MAX ,Maximum time between activate and precharge to the same bank" bitfld.long 0x00 0.--5. " T_RAS_MIN ,Minimum time between activate and precharge to the same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DRAMTMG1,SDRAM Timing Register 1" bitfld.long 0x04 16.--20. " T_XP ,Minimum time after power-down exit to any operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--13. " RD2PRE ,Minimum time from read to precharge of same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x04 0.--6. 1. " T_RC ,Minimum time between activates to same bank" line.long 0x08 "DRAMTMG2,SDRAM Timing Register 2" bitfld.long 0x08 24.--29. " WRITE_LATENCY ,Time from write command to write data on SDRAM interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " READ_LATENCY ,Time from read command to read data on SDRAM interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " RD2WR ,Minimum time from read command to write command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " WR2RD ,Minimum time from write command to read command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0x5C000000))&0x20)==0x20) group.long 0x10C++0x03 line.long 0x00 "DRAMTMG3,SDRAM Timing Register 3" hexmask.long.word 0x00 20.--29. 1. " T_MRW ,Time to wait after a mode register write or read" bitfld.long 0x00 12.--17. " T_MRD ,Cycles between loadmode commands" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.l(ad:0x5C000000))&0x01)==0x01) group.long 0x10C++0x03 line.long 0x00 "DRAMTMG3,SDRAM Timing Register 3" bitfld.long 0x00 12.--17. " T_MRD ,Cycles between loadmode commands" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 0.--9. 1. " T_MOD ,Cycles between loadmode command and following non-load mode command" else group.long 0x10C++0x03 line.long 0x00 "DRAMTMG3,SDRAM Timing Register 3" bitfld.long 0x00 12.--17. " T_MRD ,Cycles between loadmode commands" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x110++0x07 line.long 0x00 "DRAMTMG4,SDRAM Timing Register 4" bitfld.long 0x00 24.--28. " T_RCD ,Minimum time from activate to read or write command to same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--19. " T_CCD ,Minimum time between two reads or two writes for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " T_RRD ,Minimum time between activates from bank a to bank b for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " T_RP ,Minimum time from precharge to activate of same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DRAMTMG5,SDRAM Timing Register5" bitfld.long 0x04 24.--27. " T_CKSRX ,Time before self refresh exit that CK is maintained as a valid clock before issuing SRX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " T_CKSRE ,Time after self refresh down entry that CK is maintained as a valid clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--13. " T_CKESR ,Minimum CKE low width for self refresh entry to exit timing in memory clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--4. " T_CKE ,Minimum number of cycles of CKE HIGH / LOW during power-down and self refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x5C000000))&0x20)==0x20) group.long 0x118++0x07 line.long 0x00 "DRAMTMG6,SDRAM Timing Register 6" bitfld.long 0x00 0.--3. " T_CKCSX ,Time before clock stop exit that CK is maintained as a valid clock before issuing clock stop exit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DRAMTMG7,SDRAM Timing Register 7" bitfld.long 0x04 8.--11. " T_CKPDE ,Time after power down entry that CK is maintained as a valid clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " T_CKPDX ,Time before power down exit that CK is maintained as a valid clock before issuing PDX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else hgroup.long 0x118++0x03 hide.long 0x00 "DRAMTMG6,SDRAM Timing Register 6" hgroup.long 0x11C++0x03 hide.long 0x00 "DRAMTMG7,SDRAM Timing Register 7" endif if (((per.l(ad:0x5C000000))&0x01)==0x01) group.long 0x120++0x03 line.long 0x00 "DRAMTMG8,SDRAM Timing Register 8" hexmask.long.byte 0x00 24.--30. 1. " T_XS_FAST_X32 ,Exit Self refresh to ZQC ZQCS and MRS" hexmask.long.byte 0x00 16.--22. 1. " T_XS_ABORT_X32 ,Exit self refresh to commands not requiring a locked DLL in self refresh abort" newline hexmask.long.byte 0x00 8.--14. 1. " T_XS_DLL_X32 ,Exit self refresh to commands requiring a locked DLL" hexmask.long.byte 0x00 0.--6. 1. " T_XS_X32 ,Exit self refresh to commands not requiring a locked DLL" else group.long 0x120++0x03 line.long 0x00 "DRAMTMG8,SDRAM Timing Register 8" hexmask.long.byte 0x00 24.--30. 1. " T_XS_FAST_X32 ,Exit self refresh to ZQCL ZQCS and MRS" hexmask.long.byte 0x00 16.--22. 1. " T_XS_ABORT_X32 ,Exit Self Refresh to commands not requiring a locked DLL in self refresh abort" endif hgroup.long 0x124++0x03 hide.long 0x00 "DRAMTMG9,SDRAM Timing Register 9" group.long 0x128++0x03 line.long 0x00 "DRAMTMG10,SDRAM Timing Register 10" bitfld.long 0x00 16.--20. " T_SYNC_GEAR ,Indicates the time between MRS command and the sync pulse time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " T_CMD_GEAR ,Sync pulse to first valid command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 2.--3. " T_GEAR_SETUP ,Geardown setup time" ",1,2,3" bitfld.long 0x00 0.--1. " T_GEAR_HOLD ,Geardown hold time" ",1,2,3" hgroup.long 0x12C++0x03 hide.long 0x00 "DRAMTMG11,SDRAM Timing Register 11" group.long 0x130++0x07 line.long 0x00 "DRAMTMG12,SDRAM Timing Register 12" bitfld.long 0x00 16.--17. " T_CMDCKE ,Delay from valid command to CKE input LOW" "0,1,2,3" bitfld.long 0x00 8.--11. " T_CKEHCMD ,Valid command requirement after CKE input HIGH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--4. " T_MRD_PDA ,This is the mode register set command cycle time in PDA mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DRAMTMG13,SDRAM Timing Register 13" hexmask.long.byte 0x04 24.--30. 1. " ODTLOFF ,This is the latency from CAS-2 command to tODToff reference" bitfld.long 0x04 16.--21. " T_CCD_MW ,This is the minimum time from write or masked write to masked write command for same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 0.--2. " T_PPD ,This is the minimum time from precharge to precharge command" "0,1,2,3,4,5,6,7" if (((per.l(ad:0x5C000000))&0x20)==0x20) group.long 0x138++0x03 line.long 0x00 "DRAMTMG14,SDRAM Timing Register 14" hexmask.long.word 0x00 0.--11. 1. " T_XSR ,Exit self refresh to any command" else hgroup.long 0x138++0x03 hide.long 0x00 "DRAMTMG14,SDRAM Timing Register 14" endif group.long 0x13C++0x03 line.long 0x00 "DRAMTMG15,SDRAM Timing Register 15" bitfld.long 0x00 31. " EN_DFI_LP_T_STAB ,Enable DFI tSTAB" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " T_STAB_X32 ,Stabilization time" group.long 0x180++0x03 line.long 0x00 "ZQCTL0,ZQ Control Register 0" bitfld.long 0x00 31. " DIS_AUTO_ZQ ,Disable auto ZQCS/MPC" "No,Yes" bitfld.long 0x00 30. " DIS_SRX_ZQCL ,Disable ZQCL/MPC" "No,Yes" newline bitfld.long 0x00 29. " ZQ_RESISTOR_SHARED ,ZQ resistor sharing" "Not shared,Shared" newline hexmask.long.word 0x00 16.--26. 1. " T_ZQ_LONG_NOP ,Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to SDRAM" hexmask.long.word 0x00 0.--9. 1. " T_ZQ_SHORT_NOP ,Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to SDRAM" if (((per.l(ad:0x5C000000))&0x20)==0x20) group.long 0x184++0x03 line.long 0x00 "ZQCTL1,ZQ Control Register 1" hexmask.long.word 0x00 20.--29. 1. " T_ZQ_RESET_NOP ,Number of cycles of NOP required after a ZQReset (ZQ calibration reset) command is issued to SDRAM" hexmask.long.tbyte 0x00 0.--19. 1. " T_ZQ_SHORT_INTERVAL_X1024 ,Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands" elif ((((per.l(ad:0x5C000000))&0x01)==0x01)) group.long 0x184++0x03 line.long 0x00 "ZQCTL1,ZQ Control Register 1" hexmask.long.tbyte 0x00 0.--19. 1. " T_ZQ_SHORT_INTERVAL_X1024 ,Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands" else hgroup.long 0x184++0x03 hide.long 0x00 "ZQCTL1,ZQ Control Register 1" endif if (((per.l(ad:0x5C000000))&0x20)==0x20) group.long 0x188++0x03 line.long 0x00 "ZQCTL2,ZQ Control Register 2" bitfld.long 0x00 0. " ZQ_RESET ,Setting this register bit to 1 triggers a ZQ Reset operation" "Not triggered,Triggered" else hgroup.long 0x188++0x03 hide.long 0x00 "ZQCTL2,ZQ Control Register 2" endif rgroup.long 0x18C++0x03 line.long 0x00 "ZQSTAT,ZQ Status Register" bitfld.long 0x00 0. " ZQ_RESET_BUSY ,ZQ reset operation initialization by soc core" "Possibility of initialization,In progress" group.long 0x190++0x1B line.long 0x00 "DFITMG0,DFI Timing Register 0" bitfld.long 0x00 24.--28. " DFI_T_CTRL_DELAY ,Specifies the number of DFI clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 23. " DFI_RDDATA_USE_SDR ,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values" "HDR,SDR" newline hexmask.long.byte 0x00 16.--22. 1. " DFI_RDDATA_USE_SDR ,Time from the assertion of a read command on the DFI interface to the assertion of the DFI_RDDATA_EN signal" bitfld.long 0x00 15. " DFI_WRDATA_USE_SDR ,Selects whether value in DFITMG0.DFI_TPHY_WRLAT is in terms of SDR or HDR clock cycles" "HDR,SDR" newline bitfld.long 0x00 8.--13. " DFI_TPHY_WRDATA ,Specifies the number of clock cycles between when DFI_WRDATA_EN is asserted to when the associated write data is driven on the dfi_wrdata signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DFI_TPHY_WRLAT ,Number of clocks from the write command to write data enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DFITMG1,DFI Timing Register 1" bitfld.long 0x04 28.--31. " DFI_T_CMD_LAT ,Specifies the number of DFI PHY clock cycles" "0,,,3,4,5,6,,8,?..." bitfld.long 0x04 24.--25. " DFI_T_PARIN_LAT ,Number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven" "0,1,2,3" newline bitfld.long 0x04 16.--20. " DFI_T_WRDATA_DELAY ,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " DFI_T_DRAM_CLK_DISABLE ,Number of DFI clock cycles from the assertion of the DFI_DRAM_CLK_DISABLE signal on the DFI until the clock to the DRAM memory devices at the PHY-DRAM boundary maintains a low value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--4. " DFI_T_DRAM_CLK_ENABLE ,Specifies the number of DFI clock cycles from the de-assertion of the DFI_DRAM_CLK_DISABLE signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "DFILPCFG0,DFI Low Power Configuration Register 0" bitfld.long 0x08 24.--28. " DFI_TLP_RESP ,DFI_TLP_RESP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 20.--23. " DFI_LP_WAKEUP_DPD ,Value in DFI clock cycles to drive on dfi_lp_wakeup signal" "16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,262144,Unlimited" newline bitfld.long 0x08 16. " DFI_LP_EN_DPD ,Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit" "Disabled,Enabled" bitfld.long 0x08 12.--15. " DFI_LP_WAKEUP_SR ,Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered" "16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,262144,Unlimited" newline bitfld.long 0x08 8. " DFI_LP_EN_SR ,Enables DFI low power interface handshaking during self refresh entry/exit" "Disabled,Enabled" bitfld.long 0x08 4.--7. " DFI_LP_WAKEUP_PD ,Value to drive on dfi_lp_wakeup signal when Power Down mode is entered" "16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,262144,Unlimited" newline bitfld.long 0x08 0. " DFI_LP_EN_PD ,Enables DFI low power interface handshaking during power down entry/exit" "Disabled,Enabled" line.long 0x0C "DFILPCFG1,DFI Low Power Configuration Register 1" bitfld.long 0x0C 4.--7. " DFI_LP_WAKEUP_MPSM ,Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "DFIUPD0,DFI Update Register 0" bitfld.long 0x10 31. " DIS_AUTO_CTRLUPD ,Automatic dfi_ctrlupd_req generation by the DDRC" "No,Yes" bitfld.long 0x10 30. " DIS_AUTO_CTRLUPD_SRX ,Auto ctrlupd request generation" "No,Yes" newline bitfld.long 0x10 29. " CTRLUPD_PRE_SRX ,Selects dfi_ctrlupd_req requirements at SRX" "After SRX,Before SRX" hexmask.long.word 0x10 16.--25. 1. " DFI_T_CTRLUP_MAX ,Specifies the maximum number of clock cycles that the dfi_ctrlupd_req signal can assert" newline hexmask.long.word 0x10 0.--9. 1. " DFI_T_CTRLUP_MIN ,Specifies the minimum number of clock cycles that the dfi_ctrlupd_req signal must be asserted" line.long 0x14 "DFIUPD1,DFI Update Register 1" hexmask.long.byte 0x14 16.--23. 1. " DFI_T_CTRLUPD_INTERVAL_MIN_X1024 ,The minimum amount of time between DDRC initiated DFI update requests" hexmask.long.byte 0x14 0.--7. 1. " DFI_T_CTRLUPD_INTERVAL_MAX_X1024 ,The maximum amount of time between DDRC initiated DFI update requests" line.long 0x18 "DFIUPD2,DFI Update Register 2" bitfld.long 0x18 31. " DFI_PHYUPD_EN ,Enables the support for acknowledging PHY- initiated updates" "Disabled,Enabled" if (((per.l(ad:0x5C000000))&0x20)==0x20) group.long 0x1B0++0x03 line.long 0x00 "DFIMISC,DFI Miscellaneous Control Register" bitfld.long 0x00 8.--12. " DFI_FREQUENCY ,Indicates the operating frequency of the system" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " DFI_INIT_START ,PHY init start request signal" "Not started,Started" newline bitfld.long 0x00 4. " CTL_IDLE_EN ,Enables support of ctl_idle signal" "Disabled,Enabled" bitfld.long 0x00 2. " DFI_DATA_CS_POLARITY ,Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals" "Low,High" newline bitfld.long 0x00 1. " PHY_DBI_MODE ,DBI implemented in DDRC or PHY" "DDRC,PHY" bitfld.long 0x00 0. " DFI_INIT_COMPLETE_EN ,PHY initialization complete enable signal" "Disabled,Enabled" else group.long 0x1B0++0x03 line.long 0x00 "DFIMISC,DFI Miscellaneous Control Register" bitfld.long 0x00 8.--12. " DFI_FREQUENCY ,Indicates the operating frequency of the system" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " DFI_INIT_START ,PHY init start request signal" "Not started,Started" newline bitfld.long 0x00 4. " CTL_IDLE_EN ,Enables support of ctl_idle signal" "Disabled,Enabled" bitfld.long 0x00 2. " DFI_DATA_CS_POLARITY ,Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals" "Low,High" newline bitfld.long 0x00 0. " DFI_INIT_COMPLETE_EN ,PHY initialization complete enable signal" "Disabled,Enabled" endif group.long 0x1B4++0x07 line.long 0x00 "DFITMG2,DFI Timing Register 2" hexmask.long.byte 0x00 8.--14. 1. " DFI_TPHY_RDCSLAT ,Number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted" bitfld.long 0x00 0.--5. " DFI_TPHY_WRCSLAT ,Number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DFITMG3,DFI Timing Register 3" bitfld.long 0x04 0.--4. " DFI_T_GEARDOWN_DELAY ,Delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x1BC++0x03 line.long 0x00 "DFISTAT,DFI Status Register" bitfld.long 0x00 1. " DFI_LP_ACK ,Stores the value of the dfi_lp_ack input to the controller" "0,1" bitfld.long 0x00 0. " DFI_INIT_COMPLETE ,The status flag register which announces when the DFI initialization has been completed" "Not completed,Completed" group.long 0x1C0++0x03 line.long 0x00 "DBICTL,DM/DBI Control Register" bitfld.long 0x00 2. " RD_DBI_EN ,Read DBI enable signal in DDRC" "Disabled,Enabled" bitfld.long 0x00 1. " WR_DBI_EN ,Write DBI enable signal in DDRC" "Disabled,Enabled" newline bitfld.long 0x00 0. " DM_EN ,DM enable signal in DDRC" "Disabled,Enabled" group.long 0x200++0x23 line.long 0x00 "ADDRMAP0,Address Map Register 0" bitfld.long 0x00 0.--4. " ADDRMAP_CS_BIT0 ,Selects the HIF address bit used as rank address bit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,,,31" line.long 0x04 "ADDRMAP1,Address Map Register 1" bitfld.long 0x04 16.--20. " ADDRMAP_BANK_B2 ,Selects the HIF address bit used as bank address bit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " ADDRMAP_BANK_B1 ,Selects the HIF address bits used as bank address bit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--4. " ADDRMAP_BANK_B0 ,Selects the HIF address bits used as bank address bit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "ADDRMAP2,Address Map Register 2" bitfld.long 0x08 24.--27. " ADDRMAP_COL_B5 ,Selects the HIF address bit used as column address bit 5" "0,1,2,3,4,5,6,7,,,,,,,,15" bitfld.long 0x08 16.--19. " ADDRMAP_COL_B4 ,Selects the HIF address bit used as column address bit 4" "0,1,2,3,4,5,6,7,,,,,,,,15" newline bitfld.long 0x08 8.--11. " ADDRMAP_COL_B3 ,Selects the HIF address bit used as column address bit 3" "0,1,2,3,4,5,6,7,?..." bitfld.long 0x08 0.--3. " ADDRMAP_COL_B2 ,Selects the HIF address bit used as column address bit 2" "0,1,2,3,4,5,6,7,?..." line.long 0x0C "ADDRMAP3,Address Map Register 3" bitfld.long 0x0C 24.--27. " ADDRMAP_COL_B9 ,Selects the HIF address bit used as column address bit 9" "0,1,2,3,4,5,6,7,,,,,,,,15" bitfld.long 0x0C 16.--19. " ADDRMAP_COL_B8 ,Selects the HIF address bit used as column address bit 8" "0,1,2,3,4,5,6,7,,,,,,,,15" newline bitfld.long 0x0C 8.--11. " ADDRMAP_COL_B7 ,Selects the HIF address bit used as column address bit 7" "0,1,2,3,4,5,6,7,,,,,,,,15" bitfld.long 0x0C 0.--3. " ADDRMAP_COL_B6 ,Selects the HIF address bit used as column address bit 6" "0,1,2,3,4,5,6,7,,,,,,,,15" line.long 0x10 "ADDRMAP4,Address Map Register 4" bitfld.long 0x10 8.--11. " ADDRMAP_COL_B11 ,Selects the HIF address bit used as column address bit 13" "0,1,2,3,4,5,6,7,,,,,,,,15" bitfld.long 0x10 0.--3. " ADDRMAP_COL_B10 ,Selects the HIF address bit used as column address bit 11" "0,1,2,3,4,5,6,7,,,,,,,,15" line.long 0x14 "ADDRMAP5,Address Map Register 5" bitfld.long 0x14 24.--27. " ADDRMAP_ROW_B11 ,Selects the HIF address bit used as row address bit 11" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" bitfld.long 0x14 16.--19. " ADDRMAP_ROW_B2_10 ,Selects the HIF address bit used as row address bit 2 to 10" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" newline bitfld.long 0x14 8.--11. " ADDRMAP_ROW_B1 ,Selects the HIF address bits used as row address bit 1" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x14 0.--3. " ADDRMAP_ROW_B0 ,Selects the HIF address bits used as row address bit 0" "0,1,2,3,4,5,6,7,8,9,10,11,?..." line.long 0x18 "ADDRMAP6,Address Map Register 6" bitfld.long 0x18 24.--27. " ADDRMAP_ROW_B15 ,Selects the HIF address bit used as row address bit 15" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" bitfld.long 0x18 16.--19. " ADDRMAP_ROW_B14 ,Selects the HIF address bit used as row address bit 14" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" newline bitfld.long 0x18 8.--11. " ADDRMAP_ROW_B13 ,Selects the HIF address bit used as row address bit 13" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" bitfld.long 0x18 0.--3. " ADDRMAP_ROW_B12 ,Selects the HIF address bit used as row address bit 12" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" line.long 0x1C "ADDRMAP7,Address Map Register 7" bitfld.long 0x1C 8.--11. " ADDRMAP_ROW_B17 ,Selects the HIF address bit used as row address bit 17" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" bitfld.long 0x1C 0.--3. " ADDRMAP_ROW_B16 ,Selects the HIF address bit used as row address bit 16" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" line.long 0x20 "ADDRMAP8,Address Map Register 8" bitfld.long 0x20 8.--13. " ADDRMAP_BG_B1 ,Selects the HIF address bits used as bank group address bit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,63" bitfld.long 0x20 0.--4. " ADDRMAP_BG_B0 ,Selects the HIF address bits used as bank group address bit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x5C000000+0x214))&0xF0000)==0xF0000) group.long 0x224++0x0B line.long 0x00 "ADDRMAP9,Address Map Register 9" bitfld.long 0x00 24.--27. " ADDRMAP_ROW_B5 ,Selects the HIF address bits used as row address bit 5" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x00 16.--19. " ADDRMAP_ROW_B4 ,Selects the HIF address bits used as row address bit 4" "0,1,2,3,4,5,6,7,8,9,10,11,?..." newline bitfld.long 0x00 8.--11. " ADDRMAP_ROW_B3 ,Selects the HIF address bits used as row address bit 3" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x00 0.--3. " ADDRMAP_ROW_B2 ,Selects the HIF address bits used as row address bit 2" "0,1,2,3,4,5,6,7,8,9,10,11,?..." line.long 0x04 "ADDRMAP10,Address Map Register 10" bitfld.long 0x04 24.--27. " ADDRMAP_ROW_B9 ,Selects the HIF address bits used as row address bit 9" "0,1,2,3,4,5,6,7,8,9,10,11,,,,15" bitfld.long 0x04 16.--19. " ADDRMAP_ROW_B8 ,Selects the HIF address bits used as row address bit 8" "0,1,2,3,4,5,6,7,8,9,10,11,?..." newline bitfld.long 0x04 8.--11. " ADDRMAP_ROW_B7 ,Selects the HIF address bits used as row address bit 7" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x04 0.--3. " ADDRMAP_ROW_B6 ,Selects the HIF address bits used as row address bit 6" "0,1,2,3,4,5,6,7,8,9,10,11,?..." line.long 0x08 "ADDRMAP11,Address Map Register 11" bitfld.long 0x08 0.--3. " ADDRMAP_ROW_B10 ,Selects the HIF address bits used as row address bit 10" "0,1,2,3,4,5,6,7,8,9,10,11,?..." else hgroup.long 0x224++0x03 hide.long 0x00 "ADDRMAP9,Address Map Register 9" hgroup.long 0x228++0x03 hide.long 0x00 "ADDRMAP10,Address Map Register 10" hgroup.long 0x230++0x03 hide.long 0x00 "ADDRMAP11,Address Map Register 11" endif group.long 0x240++0x07 line.long 0x00 "ODTCFG,ODT configuration register" bitfld.long 0x00 24.--27. " WR_ODT_HOLD ,DFI PHY clock cycles to hold ODT for a write command" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " WR_ODT_DELAY ,Delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--11. " RD_ODT_HOLD ,DFI PHY clock cycles to hold ODT for a read command" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--6. " RD_ODT_DELAY ,Delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "ODTMAP,ODT/Rank Map Register" bitfld.long 0x04 13. " RANK1_RD_ODT[1] ,Indicates bit next to the LSB must be turned on during a read from rank 1" "Not occurred,Occurred" bitfld.long 0x04 12. " [0] ,Indicates LSB must be turned on during a read from rank 1" "Not occurred,Occurred" newline bitfld.long 0x04 9. " RANK1_WR_ODT[1] ,Indicates bit next to the LSB must be turned on during a write to rank 1" "Not occurred,Occurred" bitfld.long 0x04 8. " [0] ,Indicates LSB must be turned on during a write to rank 1" "Not occurred,Occurred" newline bitfld.long 0x04 5. " RANK0_RD_ODT[1] ,Indicates bit next to the LSB must be turned on during a read from rank 0" "0,1" bitfld.long 0x04 4. " [0] ,Indicates LSB must be turned on during a read from rank 0" "0,1" newline bitfld.long 0x04 1. " RANK0_WR_ODT[1] ,Indicates bit next to the LSB must be turned on during a write to rank 0" "0,1" bitfld.long 0x04 0. " [0] ,Indicates LSB must be turned on during a write to rank 0" "0,1" group.long 0x250++0x03 line.long 0x00 "SCHED,Scheduler Control Register" hexmask.long.byte 0x00 24.--30. 1. " RDWR_IDLE_GAP ,When the preferred transaction store is empty for these many clock cycles switch to the alternate transaction store if it is non-empty" bitfld.long 0x00 8.--12. " LPR_NUM_ENTRIES ,Number of entries in the low priority transaction store" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 2. " PAGECLOSE ,Provides a midway between open and close page policies" "Open page policy,Close page policy" bitfld.long 0x00 1. " PREFER_WRITE ,Bank selector prefers writes over reads" "Reads over writes,Writes over reads" newline bitfld.long 0x00 0. " FORCE_LOW_PRI_N ,Active low signal" "Not forced,Forced" if (((per.l(ad:0x5C000000+0x250))&0x04)==0x04) group.long 0x254++0x03 line.long 0x00 "SCHED1,Scheduler Control Register 1" hexmask.long.byte 0x00 0.--7. 1. " PAGECLOSE_TIMER ,Pageclose timer" else hgroup.long 0x254++0x03 hide.long 0x00 "SCHED1,Scheduler Control Register 1" endif group.long 0x25C++0x03 line.long 0x00 "PERFHPR1,High Priority Read CAM Register 1" hexmask.long.byte 0x00 24.--31. 1. " HPR_XACT_RUN_LENGTH ,Number of transactions that are serviced once the HPR queue goes critical" hexmask.long.word 0x00 0.--15. 1. " HPR_MAX_STARVE ,Number of DFI clocks that the HPR queue can be starved before it goes critical" group.long 0x264++0x03 line.long 0x00 "PERFLPR1,Low Priority Read CAM Register 1" hexmask.long.byte 0x00 24.--31. 1. " LPR_XACT_RUN_LENGTH ,Number of transactions that are serviced once the LPR queue goes critical" hexmask.long.word 0x00 0.--15. 1. " LPR_MAX_STARVE ,Number of DFI clocks that the LPR queue can be starved before it goes critical" group.long 0x26C++0x03 line.long 0x00 "PERFWR1,Write CAM Register 1" hexmask.long.byte 0x00 24.--31. 1. " W_XACT_RUN_LENGTH ,Number of transactions that are serviced once the WR queue goes critical" hexmask.long.word 0x00 0.--15. 1. " W_MAX_STARVE ,Number of DFI clocks that the WR queue can be starved before it goes critical" group.long 0x300++0x07 line.long 0x00 "DBG0,Debug Register 0" bitfld.long 0x00 4. " DIS_COLLISION_PAGE_OPT ,Auto-precharge enable" "Disabled,Enabled" bitfld.long 0x00 2. " DIS_ACT_BYPASS ,Disable bypass path for high priority read activates" "No,Yes" newline bitfld.long 0x00 1. " DIS_RD_BYPASS ,Disable bypass path for high priority read page hits" "No,Yes" bitfld.long 0x00 0. " DIS_WC ,Disable write combine" "No,Yes" line.long 0x04 "DBG1,Debug Register 1" bitfld.long 0x04 1. " DIS_HIF ,HIF disable" "No,Yes" bitfld.long 0x04 0. " DIS_DQ ,De-queue from the CAM disable" "No,Yes" rgroup.long 0x308++0x03 line.long 0x00 "DBGCAM,CAM Debug Register" bitfld.long 0x00 31. " DBG_STALL_RD ,Stall for read channel" "Not stalled,Stalled" bitfld.long 0x00 30. " DBG_STALL_WR ,Stall for write channel" "Not stalled,Stalled" newline bitfld.long 0x00 29. " WR_DATA_PIPELINE_EMPTY ,Indicates that the write data pipeline on the DFI interface is empty" "Not empty,Empty" bitfld.long 0x00 28. " RD_DATA_PIPELINE_EMPTY ,Indicates that the read data pipeline on the DFI interface is empty" "Not empty,Empty" newline bitfld.long 0x00 26. " DBG_WR_Q_EMPTY ,Indicates that all the write command queues and write data buffers inside DDRC are empty" "Not empty,Empty" bitfld.long 0x00 25. " DBG_RD_Q_EMPTY ,Indicates that all the read command queues and read data buffers inside DDRC are empty" "Not empty,Empty" newline bitfld.long 0x00 24. " DBG_STALL ,Stall" "Not stalled,Stalled" bitfld.long 0x00 16.--21. " DBG_W_Q_DEPTH ,Write queue depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " DBG_LPR_Q_DEPTH ,Low priority read queue depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DBG_HPR_Q_DEPTH ,High priority read queue depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x30C++0x03 line.long 0x00 "DBGCMD,Command Debug Register" bitfld.long 0x00 5. " CTRLUPD ,Indicates to the DDRC to issue a dfi_ctrlupd_req to the PHY" "Not issued,Issued" bitfld.long 0x00 4. " ZQ_CALIB_SHORT ,Indicates to the DDRC to issue a ZQCS command to the SDRAM" "No calibration,Calibration" newline bitfld.long 0x00 1. " RANK1_REFRESH ,Indicates to the DDRC to issue a refresh to rank 1" "No refresh,Refresh" bitfld.long 0x00 0. " RANK0_REFRESH ,Indicates to the DDRC to issue a refresh to rank 0" "No refresh,Refresh" rgroup.long 0x310++0x03 line.long 0x00 "DBGSTAT,Status Debug Register" bitfld.long 0x00 5. " CTRLUPD_BUSY ,Ctrlupd operation busy" "Not busy,Busy" bitfld.long 0x00 4. " ZQ_CALIB_SHORT_BUSY ,ZQCS operation busy" "Not busy,Busy" newline bitfld.long 0x00 1. " RANK1_REFRESH_BUSY ,Rank1_refresh operation busy" "Not busy,Busy" bitfld.long 0x00 0. " RANK0_REFRESH_BUSY ,Rank0_refresh operation busy" "Not busy,Busy" group.long 0x320++0x03 line.long 0x00 "SWCTL,Software Register Programming Control Enable" bitfld.long 0x00 0. " SW_DONE ,Enable quasi dynamic register programming outside reset" "Disabled,Enabled" rgroup.long 0x324++0x03 line.long 0x00 "SWSTAT,Software Register Programming Control Status" bitfld.long 0x00 0. " SW_DONE_ACK ,Register programming done" "Not done,Done" group.long 0x36C++0x03 line.long 0x00 "POISONCFG,AXI Poison Configuration Register" bitfld.long 0x00 24. " RD_POISON_INTR_CLR ,Interrupt clear for read transaction poisoning" "Not cleared,Cleared" bitfld.long 0x00 20. " RD_POISON_INTR_EN ,Enables interrupts for read transaction poisoning" "Disabled,Enabled" newline bitfld.long 0x00 16. " RD_POISON_SLVERR_EN ,Enables SLVERR response for read transaction poisoning" "Disabled,Enabled" bitfld.long 0x00 8. " WR_POISON_INTR_CLR ,Interrupt clear for write transaction poisoning" "Not cleared,Cleared" newline bitfld.long 0x00 4. " WR_POISON_INTR_EN ,Enables interrupts for write transaction poisoning" "Disabled,Enabled" bitfld.long 0x00 0. " WR_POISON_SLVERR_EN ,Enables SLVERR response for write transaction poisoning" "Disabled,Enabled" rgroup.long 0x370++0x03 line.long 0x00 "POISONSTAT,AXI Poison Status Register" bitfld.long 0x00 16. " RD_POISON_INTR_0 ,Read transaction poisoning error interrupt for port 0" "Not occurred,Occurred" bitfld.long 0x00 0. " WR_POISON_INTR_0 ,Write transaction poisoning error interrupt for port 0" "Not occurred,Occurred" rgroup.long 0x3FC++0x03 line.long 0x00 "PSTAT,Port Status Register" bitfld.long 0x00 16. " WR_PORT_BUSY_0 ,Indicates if there are outstanding writes for AXI port 0" "Not busy,Busy" bitfld.long 0x00 0. " RD_PORT_BUSY_0 ,Indicates if there are outstanding reads for AXI port 0" "Not busy,Busy" group.long 0x400++0x0B line.long 0x00 "PCCFG,Port Common Configuration Register" bitfld.long 0x00 8. " BL_EXP_MODE ,Burst length expansion mode" "0,1" bitfld.long 0x00 4. " PAGEMATCH_LIMIT ,Page match four limit" "No limit,Limit" newline bitfld.long 0x00 0. " GO2CRITICAL_EN ,Sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals" "Disabled,Enabled" line.long 0x04 "PCFGR_0,Port 0 Configuration Read Register" bitfld.long 0x04 16. " RDWR_ORDERED_EN ,Enable ordered read/writes" "Disabled,Enabled" bitfld.long 0x04 14. " RD_PORT_PAGEMATCH_EN ,Enables the Page Match feature" "Disabled,Enabled" newline bitfld.long 0x04 13. " RD_PORT_PAGEMATCH_EN ,Enables the AXI urgent sideband signal" "Disabled,Enabled" bitfld.long 0x04 12. " RD_PORT_AGING_EN ,Enables aging function for the read channel of the port" "Disabled,Enabled" newline hexmask.long.word 0x04 0.--9. 1. " RD_PORT_PRIORITY ,Determines the initial load value of read aging counters" line.long 0x08 "PCFGW_0,Port n Configuration Write Register" bitfld.long 0x08 14. " WR_PORT_PAGEMATCH_EN ,Enables the Page Match feature" "Disabled,Enabled" bitfld.long 0x08 13. " WR_PORT_URGENT_EN ,Enables the AXI urgent sideband signal" "Disabled,Enabled" newline bitfld.long 0x08 12. " WR_PORT_AGING_EN ,Enables aging function for the write channel of the port" "Disabled,Enabled" hexmask.long.word 0x08 0.--9. 1. " WR_PORT_PRIORITY ,Determines the initial load value of write aging counters" group.long 0x490++0x13 line.long 0x00 "PCTRL_0,Port 0 Control Register" bitfld.long 0x00 0. " PORT_EN ,Enables AXI port n" "Disabled,Enabled" line.long 0x04 "PCFGQOS0_0,Port 0 Read QoS Configuration Register 0" bitfld.long 0x04 20.--21. " RQOS_MAP_REGION1 ,Indicates the traffic class of region 1" "LPR,VPR,HPR,?..." bitfld.long 0x04 16.--17. " RQOS_MAP_REGION0 ,This bitfield indicates the traffic class of region 0" "LPR,VPR,HPR,?..." newline bitfld.long 0x04 0.--3. " RQOS_MAP_LEVEL1 ,Separation level1 indicating the end of region0 mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,?..." line.long 0x08 "PCFGQOS1_0,Port n Read QoS Configuration Register 1" hexmask.long.word 0x08 16.--26. 1. " RQOS_MAP_TIMEOUTR ,Specifies the timeout value for transactions mapped to the red address queue" hexmask.long.word 0x08 0.--10. 1. " RQOS_MAP_TIMEOUTB ,Specifies the timeout value for transactions mapped to the blue address queue" line.long 0x0C "PCFGWQOS0_0,Port n Write QoS Configuration Register 0" bitfld.long 0x0C 20.--21. " WQOS_MAP_REGION1 ,This bitfield indicates the traffic class of region 1" "NPW,VPW,?..." bitfld.long 0x0C 16.--17. " WQOS_MAP_REGION0 ,This bitfield indicates the traffic class of region 0" "NPW,VPW,?..." newline bitfld.long 0x0C 0.--3. " WQOS_MAP_LEVEL ,Separation level indicating the end of region0 mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,?..." line.long 0x10 "PCFGWQOS1_0,Port n Write QoS Configuration Register 1" hexmask.long.word 0x10 0.--10. 1. " WQOS_MAP_TIMEOUT ,Specifies the timeout value for write transactions" newline tree "SHADOW Registers" if (((per.l(ad:0x5C000000))&0x20)==0x20) group.long 0x2020++0x07 line.long 0x00 "DERATEEN_SHADOW,Temperature Derate Enable Register" bitfld.long 0x00 8.--9. " RC_DERATE_VALUE ,Derate value of tRC for LPDDR4" "+1,+2,+3,+4" bitfld.long 0x00 4.--7. " DERATE_BYTE ,Derate value of tRC for LPDDR4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1. " DERATE_VALUE ,Derate value" "+1,+2" bitfld.long 0x00 0. " DERATE_ENABLE ,Enables derating" "Disabled,Enabled" line.long 0x04 "DERATEINT_SHADOW,Temperature Derate Interval Register" elif ((((per.l(ad:0x5C000000))&0x08)==0x08)||(((per.l(ad:0x5C000000))&0x04)==0x04)) group.long 0x2020++0x07 line.long 0x00 "DERATEEN_SHADOW,Temperature Derate Enable Register" bitfld.long 0x00 4.--7. " DERATE_BYTE ,Derate value of tRC for LPDDR4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " DERATE_VALUE ,Derate value" "+1,+2" newline bitfld.long 0x00 0. " DERATE_ENABLE ,Enables derating" "Disabled,Enabled" line.long 0x04 "DERATEINT_SHADOW,Temperature Derate Interval Register" else hgroup.long 0x2020++0x03 hide.long 0x00 "DERATEEN_SHADOW,Temperature Derate Enable Register" hgroup.long 0x2024++0x03 hide.long 0x00 "DERATEINT_SHADOW,Temperature Derate Interval Register" endif if (((per.l(ad:0x5C000000))&0x20)==0x20) group.long 0x2050++0x03 line.long 0x00 "RFSHCTL0_SHADOW,Refresh Control Register 0" bitfld.long 0x00 20.--23. " REFRESH_MARGIN ,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--16. " REFRESH_TO_X32 ,Speculative refreshes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4.--8. " REFRESH_BURST ,Number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 2. " PER_BANK_REFRESH ,Per bank refresh" "Per bank,All bank" else group.long 0x2050++0x03 line.long 0x00 "RFSHCTL0_SHADOW,Refresh Control Register 0" bitfld.long 0x00 20.--23. " REFRESH_MARGIN ,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--16. " REFRESH_TO_X32 ,Speculative refreshes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4.--8. " REFRESH_BURST ,Number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif group.long 0x2064++0x03 line.long 0x00 "RFSHTMG_SHADOW,Refresh Timing Register" hexmask.long.word 0x00 16.--27. 1. " T_RFC_NOM_X32 ,Average time interval between refreshes per rank" bitfld.long 0x00 15. " LPDDR3_TREFBW_EN ,tREFBW parameter enabled" "Disabled,Enabled" newline hexmask.long.word 0x00 0.--9. 1. " T_RFC_MIN ,Minimum time from refresh to refresh or activate" group.long 0x20DC++0x07 line.long 0x00 "INIT3_SHADOW,SDRAM Initialization Register 3" hexmask.long.word 0x00 16.--31. 1. " MR ,Value to write to MR register" hexmask.long.word 0x00 0.--15. 1. " EMR ,Value to write to EMR register" line.long 0x04 "INIT4_SHADOW,SDRAM Initialization Register 4" hexmask.long.word 0x04 16.--31. 1. " EMR2 ,Value to write to EMR2 register" hexmask.long.word 0x04 0.--15. 1. " EMR3 ,Value to write to EMR3 register" hgroup.long 0x20E8++0x03 hide.long 0x00 "INIT6_SHADOW,SDRAM Initialization Register 6" hgroup.long 0x20EC++0x03 hide.long 0x00 "INIT7_SHADOW,SDRAM Initialization Register 7" group.long 0x2100++0x0B line.long 0x00 "DRAMTMG0_SHADOW,SDRAM Timing Register 0" hexmask.long.byte 0x00 24.--30. 1. " WR2PRE ,Minimum time between write and precharge to same bank" bitfld.long 0x00 16.--21. " T_FAW ,T_FAW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x00 8.--14. 1. " T_RAS_MAX ,Maximum time between activate and precharge to same bank" bitfld.long 0x00 0.--5. " T_RAS_MIN ,Minimum time between activate and precharge to the same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DRAMTMG1_SHADOW,SDRAM Timing Register 1" bitfld.long 0x04 16.--20. " T_XP ,Minimum time after power-down exit to any operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--13. " RD2PRE ,Minimum time from read to precharge of same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x04 0.--6. 1. " T_RC ,Minimum time between activates to same bank" line.long 0x08 "DRAMTMG2_SHADOW,SDRAM Timing Register 2" bitfld.long 0x08 24.--29. " WRITE_LATENCY ,Set to WL time from write command to write data on SDRAM interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " READ_LATENCY ,Set to RL time from read command to read data on SDRAM interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 8.--13. " RD2WR ,Minimum time from read command to write command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " WR2RD ,Minimum time from write command to read command for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if ((((per.l(ad:0x5C000000))&0x20)==0x20)||(((per.l(ad:0x5C000000))&0x08)==0x08)||(((per.l(ad:0x5C000000))&0x04)==0x04)) group.long 0x210C++0x03 line.long 0x00 "DRAMTMG3_SHADOW,SDRAM Timing Register 3" hexmask.long.word 0x00 20.--29. 1. " T_MRW ,Time to wait after a mode register write or read (MRW or MRR)" bitfld.long 0x00 12.--17. " T_MRD ,Cycles to wait after a mode register write or read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.l(ad:0x5C000000))&0x01)==0x01) group.long 0x210C++0x03 line.long 0x00 "DRAMTMG3_SHADOW,SDRAM Timing Register 3" textfld " " bitfld.long 0x00 12.--17. " T_MRD ,Cycles to wait after a mode register write or read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 0.--9. 1. " T_MOD ,Cycles between load mode command and following non-load mode command" else group.long 0x210C++0x03 line.long 0x00 "DRAMTMG3_SHADOW,SDRAM Timing Register 3" textfld " " bitfld.long 0x00 12.--17. " T_MRD ,Cycles to wait after a mode register write or read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x2110++0x07 line.long 0x00 "DRAMTMG4_SHADOW,SDRAM Timing Register 4" bitfld.long 0x00 24.--28. " T_RCD ,Minimum time from activate to read or write command to same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--19. " T_CCD ,This is the minimum time between two reads or two writes for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " T_RRD ,Minimum time between activates from bank a to bank b for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " T_RP ,Minimum time from precharge to activate of same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DRAMTMG5_SHADOW,SDRAM Timing Register 5" bitfld.long 0x04 24.--27. " T_CKSRX ,Time before self refresh exit that ck is maintained as a valid clock before issuing SRX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " T_CKSRE ,Time after self refresh down entry that CK is maintained as a valid clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--13. " T_CKESR ,Minimum CKE low width for self refresh or self refresh power down entry to exit timing in memory clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--4. " T_CKE ,Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x5C000000))&0x20)==0x20) group.long 0x2118++0x07 line.long 0x00 "DRAMTMG6_SHADOW,SDRAM Timing Register 6" bitfld.long 0x00 24.--27. " T_CKDPDE ,Time after deep power down entry that CK is maintained as a valid clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " T_CKDPDX ,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " T_CKCSX ,Time before clock stop exit that CK is maintained as a valid clock before issuing clock stop exit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DRAMTMG7_SHADOW,SDRAM Timing Register 7" bitfld.long 0x04 8.--11. " T_CKPDE ,This is the time after Power Down Entry that CK is maintained as a valid clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " T_CKPDX ,This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x2118++0x03 line.long 0x00 "DRAMTMG6_SHADOW,SDRAM Timing Register 6" bitfld.long 0x00 24.--27. " T_CKDPDE ,Time after deep power down entry that CK is maintained as a valid clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " T_CKDPDX ,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0x211C++0x03 hide.long 0x00 "DRAMTMG7_SHADOW,SDRAM Timing Register 7" endif if (((per.l(ad:0x5C000000))&0x01)==0x01) group.long 0x2120++0x03 line.long 0x00 "DRAMTMG8_SHADOW,SDRAM Timing Register 8" hexmask.long.byte 0x00 24.--30. 1. " T_XS_FAST_X32 ,Exit self refresh to ZQCL ZQCS and MRS" hexmask.long.byte 0x00 16.--22. 1. " T_XS_ABORT_X32 ,Exit Self Refresh to commands not requiring a locked DLL in self refresh abort" newline hexmask.long.byte 0x00 8.--14. 1. " T_XS_DLL_X32 ,Exit self refresh to commands requiring a locked DLL" hexmask.long.byte 0x00 0.--6. 1. " T_XS_X32 ,Exit self refresh to commands not requiring a locked DLL" else group.long 0x2120++0x03 line.long 0x00 "DRAMTMG8_SHADOW,SDRAM Timing Register 8" hexmask.long.byte 0x00 24.--30. 1. " T_XS_FAST_X32 ,Exit self refresh to ZQCL ZQCS and MRS" hexmask.long.byte 0x00 16.--22. 1. " T_XS_ABORT_X32 ,Exit Self Refresh to commands not requiring a locked DLL in self refresh abort" endif hgroup.long 0x2124++0x03 hide.long 0x00 "DRAMTMG9_SHADOW,SDRAM Timing Register 9" group.long 0x2128++0x03 line.long 0x00 "DRAMTMG10_SHADOW,SDRAM Timing Register 10" bitfld.long 0x00 16.--20. " T_SYNC_GEAR ,Indicates the time between MRS command and the sync pulse time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " T_CMD_GEAR ,Sync pulse to first valid command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 2.--3. " T_GEAR_SETUP ,Geardown setup time" "0,1,2,3" bitfld.long 0x00 0.--1. " T_GEAR_HOLD ,Geardown hold time" "0,1,2,3" hgroup.long 0x212C++0x03 hide.long 0x00 "DRAMTMG11_SHADOW,SDRAM Timing Register 11" group.long 0x2130++0x07 line.long 0x00 "DRAMTMG12_SHADOW,SDRAM Timing Register 12" bitfld.long 0x00 16.--17. " T_CMDCKE ,Delay from valid command to CKE input LOW" "0,1,2,3" bitfld.long 0x00 8.--11. " T_CKEHCMD ,Valid command requirement after CKE input HIGH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--4. " T_MRD_PDA ,This is the Mode Register Set command cycle time in PDA mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DRAMTMG13_SHADOW,SDRAM Timing Register 13" hexmask.long.byte 0x04 24.--30. 1. " ODTLOFF ,Latency from CAS-2 command to tODToff reference" bitfld.long 0x04 16.--21. " T_CCD_MW ,This is the minimum time from write or masked write to masked write command for same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 0.--2. " T_PPD ,Minimum time from precharge to precharge command" "0,1,2,3,4,5,6,7" if (((per.l(ad:0x5C000000))&0x20)==0x20) group.long 0x2138++0x03 line.long 0x00 "DRAMTMG14_SHADOW,SDRAM Timing Register 14" hexmask.long.word 0x00 0.--11. 1. " T_XSR ,Exit Self Refresh to any command" else hgroup.long 0x2138++0x03 hide.long 0x00 "DRAMTMG14_SHADOW,SDRAM Timing Register 14" endif group.long 0x213C++0x03 line.long 0x00 "DRAMTMG15_SHADOW,SDRAM Timing Register 15" bitfld.long 0x00 31. " EN_DFI_LP_T_STAB ,Enables using tSTAB" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " T_STAB_X32 ,Stabilization time" if ((((per.l(ad:0x5C000000))&0x01)==0x01)||(((per.l(ad:0x5C000000))&0x20)==0x20)) group.long 0x2180++0x03 line.long 0x00 "ZQCTL0_SHADOW,ZQ Control Register 0" bitfld.long 0x00 31. " DIS_AUTO_ZQ ,Disable DDRC generation of ZQCS/MPC command" "No,Yes" bitfld.long 0x00 30. " DIS_SRX_ZQCL ,Disable issuing of ZQCL/MPC(ZQ calibration) command at self-refresh/sr-powerdown exit" "No,Yes" newline bitfld.long 0x00 29. " ZQ_RESISTOR_SHARED ,ZQ resistor is shared between ranks" "Not shared,Shared" newline hexmask.long.word 0x00 16.--26. 1. " T_ZQ_LONG_NOP ,Number of DFI clock cycles of NOP required after a ZQCL/MPC command is issued to SDRAM" hexmask.long.word 0x00 0.--9. 1. " T_ZQ_SHORT_NOP ,Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM" else hgroup.long 0x2180++0x03 hide.long 0x00 "ZQCTL0_SHADOW,ZQ Control Register 0" endif group.long 0x2190++0x07 line.long 0x00 "DFITMG0_SHADOW,DFI Timing Register 0" bitfld.long 0x00 24.--28. " DFI_T_CTRL_DELAY ,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 23. " DFI_RDDATA_USE_SDR ,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR(DFI PHY clock) values" "HDR,SDR" newline hexmask.long.byte 0x00 16.--22. 1. " DFI_T_RDDATA_EN ,Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal" bitfld.long 0x00 15. " DFI_WRDATA_USE_SDR ,Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values" "HDR,SDR" newline bitfld.long 0x00 8.--13. " DFI_TPHY_WRDATA ,Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal" "0,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 0.--5. " DFI_TPHY_WRLAT ,Write latency number of clocks from the write command to write data enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DFITMG1_SHADOW,DFI Timing Register 1" bitfld.long 0x04 28.--31. " DFI_T_CMD_LAT ,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven" "0,,,3,4,5,6,,8,?..." bitfld.long 0x04 24.--25. " DFI_T_PARIN_LAT ,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven" "0,1,2,3" newline bitfld.long 0x04 16.--20. " DFI_T_WRDATA_DELAY ,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " DFI_T_DRAM_CLK_DISABLE ,Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--4. " DFI_T_DRAM_CLK_ENABLE ,Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x21B4++0x07 line.long 0x00 "DFITMG2_SHADOW,DFI Timing Register 2" hexmask.long.byte 0x00 8.--14. 1. " DFI_TPHY_RDCSLAT ,Number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted" bitfld.long 0x00 0.--5. " DFI_TPHY_WRCSLAT ,Number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DFITMG3_SHADOW,DFI Timing Register 3" bitfld.long 0x04 0.--4. " DFI_T_GEARDOWN_DELAY ,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x2240++0x03 line.long 0x00 "ODTCFG_SHADOW,ODT Configuration Register" bitfld.long 0x00 24.--27. " WR_ODT_HOLD ,DFI PHY clock cycles to hold ODT for a write command" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " WR_ODT_DELAY ,The delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--11. " RD_ODT_HOLD ,DFI PHY clock cycles to hold ODT for a read command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--6. " RD_ODT_DELAY ,The delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end width 0x0B tree.end tree "DDRP0_3 (DDR PHY)" base ad:0x5C010000 width 14. rgroup.long 0x00++0x03 line.long 0x00 "RIDR,Revision Identification Register" hexmask.long.byte 0x00 24.--31. 1. " UDRID ,User-Defined revision ID" hexmask.long.byte 0x00 20.--23. 1. " PHYMJR ,PHY major revision" hexmask.long.byte 0x00 16.--19. 1. " PHYMDR ,PHY moderate revision" hexmask.long.byte 0x00 12.--15. 1. " PHYMNR ,PHY minor revision" newline hexmask.long.byte 0x00 8.--11. 1. " PUBMJR ,PUB major revision" hexmask.long.byte 0x00 4.--7. 1. " PUBMDR ,PUB moderate revision" hexmask.long.byte 0x00 0.--3. 1. " PUBMNR ,PUB minor revision" group.long 0x04++0x03 line.long 0x00 "PIR,PHY Initialization Register" bitfld.long 0x00 30. " ZCALBYP ,Impedance calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 29. " DCALPSE ,Digital delay line calibration pause" "Not paused,Paused" bitfld.long 0x00 20. " DQS2DQ ,Write DQS2DQ training" "Disabled,Enabled" bitfld.long 0x00 19. " RDIMMINIT ,RDIMM initialization" "Disabled,Enabled" newline bitfld.long 0x00 18. " CTLDINIT ,Controller DRAM initialization" "Disabled,Enabled" bitfld.long 0x00 17. " VREF ,VREF training" "Disabled,Enabled" bitfld.long 0x00 16. " SRD ,Static read training" "Disabled,Enabled" bitfld.long 0x00 15. " WREYE ,Write data eye training" "Disabled,Enabled" newline bitfld.long 0x00 14. " RDEYE ,Read data eye training" "Disabled,Enabled" bitfld.long 0x00 13. " WRDSKW ,Write data bit deskew" "Disabled,Enabled" bitfld.long 0x00 12. " RDDSKW ,Read data bit deskew" "Disabled,Enabled" bitfld.long 0x00 11. " WLADJ ,Write leveling adjust" "Disabled,Enabled" newline bitfld.long 0x00 10. " QSGATE ,Read DQS gate training" "Disabled,Enabled" bitfld.long 0x00 9. " WL ,Write leveling" "Disabled,Enabled" bitfld.long 0x00 8. " DRAMINIT ,DRAM initialization" "Disabled,Enabled" bitfld.long 0x00 7. " DRAMRST ,DRAM reset" "No reset,Reset" newline bitfld.long 0x00 6. " PHYRST ,PHY reset" "No reset,Reset" bitfld.long 0x00 5. " DCAL ,Digital delay line calibration" "Disabled,Enabled" bitfld.long 0x00 4. " PLLINIT ,PLL initialization" "Disabled,Enabled" bitfld.long 0x00 2. " CA ,CA training" "Disabled,Enabled" newline bitfld.long 0x00 1. " ZCAL ,Impedance calibration" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization trigger" "Not triggered,Triggered" group.long 0x10++0x1F line.long 0x00 "PGCR0,PHY General Configuration Register 0" bitfld.long 0x00 31. " ADCP ,Address copy" "Disabled,Enabled" bitfld.long 0x00 26. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 24.--25. " OSCACDL ,Oscillator mode address/command delay line select" "0,1,2,3" bitfld.long 0x00 14.--18. " DTOSEL ,Digital test output select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 9.--12. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "PGCR1,PHY General Configuration Register 1" bitfld.long 0x04 31. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x04 28. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value (equivalent to one CK period)" "Not loaded,Loaded" bitfld.long 0x04 27. " DLTST ,Delay line test start" "Stopped,Started" bitfld.long 0x04 26. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x04 25. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x04 24. " ACVLDTRN ,AC loopback valid train" "0,1" bitfld.long 0x04 21.--23. " ACVLDDLY ,AC loopback valid delay" "0,1,2,3,4,5,6,7" bitfld.long 0x04 20. " LRDIMMST ,LRDIMM software training" "Disabled,Enabled" newline bitfld.long 0x04 18. " UPDMSTRC0 ,DFI update master channel 0" "Not updated,Updated" bitfld.long 0x04 17. " DISDIC ,Enable/disable control for DFI_INIT_COMPLETE" "Disabled,Enabled" bitfld.long 0x04 16. " ACPDDC ,AC power-down with dual channels" "Disabled,Enabled" bitfld.long 0x04 15. " DUALCHN ,Dual channel configuration" "Disabled,Enabled" newline bitfld.long 0x04 13.--14. " FDEPTH ,Filter depth" "0,1,2,3" bitfld.long 0x04 11.--12. " LPFDEPTH ,Low-pass filter depth" "0,1,2,3" bitfld.long 0x04 10. " LPFEN ,Low-pass filter enable" "Disabled,Enabled" bitfld.long 0x04 9. " MDLEN ,Master delay line enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " PUBMODE ,Enable the PUB to control the interface to the PHY and SDRAM" "Disabled,Enabled" bitfld.long 0x04 5. " CAST ,CA software training" "Disabled,Enabled" bitfld.long 0x04 4. " DX_DQSOUT_DIFF ,Select PDIFF cell for DQS generation" "0,1" bitfld.long 0x04 3. " AC_CKOUT_DIFF ,Select PDIFF cell for CK generation" "0,1" newline bitfld.long 0x04 2. " WLSTEP ,Write leveling step" "0,1" bitfld.long 0x04 1. " WLMODE ,Write leveling software mode" "Disabled,Enabled" bitfld.long 0x04 0. " DTOMODE ,Digital test output mode" "Disabled,Enabled" line.long 0x08 "PGCR2,PHY General Configuration Register 2" bitfld.long 0x08 31. " CLRTSTAT ,Clear training status registers" "No effect,Cleared" bitfld.long 0x08 30. " CLRZCAL ,Clear impedance calibration" "No effect,Cleared" bitfld.long 0x08 29. " CLRPERR ,Clear parity error" "No effect,Cleared" bitfld.long 0x08 28. " ICPC ,Initialization complete pin configuration" "0,1" newline hexmask.long.byte 0x08 20.--27. 1. " DTPMXTMR ,Data training PUB mode exit timer" bitfld.long 0x08 19. " INITFSMBYP ,Initialization bypass" "Not bypassed,Bypassed" bitfld.long 0x08 18. " PLLFSMBYP ,PLL FSM bypass" "Not bypassed,Bypassed" hexmask.long.tbyte 0x08 0.--17. 1. " TREFPRD ,Refresh period" line.long 0x0C "PGCR3,PHY General Configuration Register 3" hexmask.long.byte 0x0C 24.--31. 1. " CKNEN ,CKN enable" hexmask.long.byte 0x0C 16.--23. 1. " CKEN ,CK enable" bitfld.long 0x0C 13.--14. " GATEACRDCLK ,Enable clock gating for AC [0] CTL_RD_CLK" "0,1,2,3" bitfld.long 0x0C 11.--12. " GATEACDDRCLK ,Enable clock gating for AC [0] DDR_CLK" "0,1,2,3" newline bitfld.long 0x0C 9.--10. " GATEACCTLCLK ,Enable clock gating for AC [0] CTL_CLK" "0,1,2,3" bitfld.long 0x0C 6.--7. " DDLBYPMODE ,Controls DDL bypass modes" "0,1,2,3" bitfld.long 0x0C 5. " IOLB ,IO loopback select" "0,1" bitfld.long 0x0C 3.--4. " RDMODE ,AC receive FIFO read mode" "0,1,2,3" newline bitfld.long 0x0C 2. " DISRST ,Read FIFO reset disable" "No,Yes" bitfld.long 0x0C 0.--1. " CLKLEVEL ,Clock level when clock gating" "0,1,2,3" line.long 0x10 "PGCR4,PHY General Configuration Register 4" bitfld.long 0x10 29. " ACDDLLD ,AC DDL delay select dynamic load" "Disabled,Enabled" bitfld.long 0x10 24.--28. " ACDDLBYP ,AC DDL bypass" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 23. " OEDDLBYP ,AC OE DDL bypass" "Not bypassed,Bypassed" bitfld.long 0x10 22. " TEDDLBYP ,AC ODT DDL bypass" "Not bypassed,Bypassed" newline bitfld.long 0x10 21. " PDRDDLBYP ,AC PDR DDL bypass" "Not bypassed,Bypassed" bitfld.long 0x10 20. " RRRMODE ,AC macro read path rise-to-rise mode" "Disabled,Enabled" bitfld.long 0x10 19. " WRRMODE ,AC macro write path rise-to-rise mode" "Disabled,Enabled" bitfld.long 0x10 17. " DCALTYPE ,DDL calibration type" "0,1" newline hexmask.long.word 0x10 8.--16. 1. " DCALSVAL ,DDL calibration starting value" bitfld.long 0x10 4.--7. " LPWAKEUP_THRSH ,AC low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 1. " LPPLLPD ,AC low power PLL power down" "Disabled,Enabled" bitfld.long 0x10 0. " LPIOPD ,AC low power IO power down" "Disabled,Enabled" line.long 0x14 "PGCR5,PHY General Configuration Register 5" hexmask.long.byte 0x14 24.--31. 1. " FRQBT ,Frequency B ratio term" hexmask.long.byte 0x14 16.--23. 1. " FRQAT ,Frequency A ratio term" hexmask.long.byte 0x14 8.--15. 1. " DISCNPERIOD ,DFI disconnect time period" bitfld.long 0x14 4.--7. " VREF_RBCTRL ,Receiver bias core side control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 2. " DXREFISELRANGE ,Internal VREF generator REFSEL range select" "0,1" bitfld.long 0x14 1. " DDLPGACT ,DDL page read write select" "Read,Write" bitfld.long 0x14 0. " DDLPGRW ,DDL page read write select" "Read,Write" line.long 0x18 "PGCR6,PHY General Configuration Register 6" hexmask.long.byte 0x18 16.--23. 1. " DLDLMT ,Delay line VT drift limit" bitfld.long 0x18 13. " ACDLVT ,AC address/command delay LCDL VT compensation" "Disabled,Enabled" bitfld.long 0x18 12. " ACBVT ,Address/command bit delay VT compensation" "Disabled,Enabled" bitfld.long 0x18 11. " ODTBVT ,ODT bit delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x18 10. " CKEBVT ,CKE bit delay VT compensation" "Disabled,Enabled" bitfld.long 0x18 9. " CSNBVT ,CSN bit delay VT compensation" "Disabled,Enabled" bitfld.long 0x18 8. " CKBVT ,CK bit delay VT compensation" "Disabled,Enabled" bitfld.long 0x18 1. " FVT ,Forced VT compensation trigger" "Not triggered,Triggered" newline bitfld.long 0x18 0. " INHVT ,VT calculation inhibit" "Disabled,Enabled" line.long 0x1C "PGCR7,PHY General Configuration Register 7" bitfld.long 0x1C 5. " ACCALCLK ,AC calibration clock select" "0,1" bitfld.long 0x1C 4. " ACRCLKMD ,AC read clock mode" "Disabled,Enabled" bitfld.long 0x1C 3. " ACDLDT ,AC DDL load type" "0,1" bitfld.long 0x1C 1. " ACDTOSEL ,AC digital test output select" "0,1" newline bitfld.long 0x1C 0. " ACTMODE ,AC test mode" "Disabled,Enabled" rgroup.long 0x30++0x0B line.long 0x00 "PGSR0,PHY General Status Register 0" bitfld.long 0x00 31. " APLOCK ,AC PLL lock" "Not locked,Locked" bitfld.long 0x00 30. " SRDERR ,Static read error" "No error,Error" bitfld.long 0x00 29. " CAWRN ,CA training warning" "Not occurred,Occurred" bitfld.long 0x00 28. " CAERR ,CA training error" "No error,Error" newline bitfld.long 0x00 27. " WEERR ,Write eye training error" "No error,Error" bitfld.long 0x00 26. " REERR ,Read eye training error" "No error,Error" bitfld.long 0x00 25. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x00 24. " RDERR ,Read bit deskew error" "No error,Error" newline bitfld.long 0x00 23. " WLAERR ,Write leveling adjustment error" "No error,Error" bitfld.long 0x00 22. " QSGERR ,DQS gate training error" "No error,Error" bitfld.long 0x00 21. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x00 20. " ZCERR ,Impedance calibration error" "No error,Error" newline bitfld.long 0x00 19. " VERR ,VREF training error" "No error,Error" bitfld.long 0x00 18. " DQS2DQERR ,Write DQS2DQ training error" "No error,Error" bitfld.long 0x00 15. " DQS2DQDONE ,Write DQS2DQ training done" "Not done,Done" bitfld.long 0x00 14. " VDONE ,VREF training done" "Not done,Done" newline bitfld.long 0x00 13. " SRDDONE ,Static read done" "Not done,Done" bitfld.long 0x00 12. " CADONE ,CA training done" "Not done,Done" bitfld.long 0x00 11. " WEDONE ,Write eye training done" "Not done,Done" bitfld.long 0x00 10. " REDONE ,Read eye training done" "Not done,Done" newline bitfld.long 0x00 9. " WDDONE ,Write bit deskew done" "Not done,Done" bitfld.long 0x00 8. " RDDONE ,Read bit deskew done" "Not done,Done" bitfld.long 0x00 7. " WLADONE ,Write leveling adjustment done" "Not done,Done" bitfld.long 0x00 6. " QSGDONE ,DQS gate training done" "Not done,Done" newline bitfld.long 0x00 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x00 4. " DIDONE ,DRAM initialization done" "Not done,Done" bitfld.long 0x00 3. " ZCDONE ,Impedance calibration done" "Not done,Done" bitfld.long 0x00 2. " DCDONE ,Digital delay line calibration done" "Not done,Done" newline bitfld.long 0x00 1. " PLDONE ,PLL lock done" "Not done,Done" bitfld.long 0x00 0. " IDONE ,Initialization done" "Not done,Done" line.long 0x04 "PGSR1,PHY General Status Register 1" bitfld.long 0x04 31. " PARERR ,RDIMM parity error" "No error,Error" bitfld.long 0x04 30. " VTSTOP ,VT stop" "Not stopped,Stopped" hexmask.long.tbyte 0x04 1.--24. 1. " DLTCODE ,Delay line test code for AC macro 0" bitfld.long 0x04 0. " DLTDONE ,Delay line test done for AC macro 0" "Not done,Done" line.long 0x08 "PGSR2,PHY General Status Register 2" hexmask.long.tbyte 0x08 1.--24. 1. " DLTCODE ,Delay line test code for AC macro 1" bitfld.long 0x08 0. " DLTDONE ,Delay line test done for AC macro 1" "Not done,Done" newline group.long 0x40++0x1B line.long 0x00 "PTR0,PHY Timing Register 0" hexmask.long.word 0x00 21.--31. 1. " TPLLPD ,PLL power-down time" hexmask.long.tbyte 0x00 6.--20. 1. " TPLLGS ,PLL gear shift time" bitfld.long 0x00 0.--5. " TPHYRST ,PHY reset time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "PTR1,PHY Timing Register 1" hexmask.long.word 0x04 16.--31. 1. " TPLLLOCK ,PLL lock time" hexmask.long.word 0x04 0.--12. 1. " TPLLRST ,PLL reset time" line.long 0x08 "PTR2,PHY Timing Register 2" bitfld.long 0x08 15.--19. " TWLDLYS ,Write leveling delay settling time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 10.--14. " TCALH ,Calibration hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 5.--9. " TCALS ,Calibration setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 0.--4. " TCALON ,Calibration on time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "PTR3,PHY Timing Register 3" hexmask.long.tbyte 0x0C 0.--22. 1. " TDINIT0 ,DRAM initialization time 0" line.long 0x10 "PTR4,PHY Timing Register 4" hexmask.long.word 0x10 0.--12. 1. " TDINIT1 ,DRAM initialization time 1" line.long 0x14 "PTR5,PHY Timing Register 5" hexmask.long.tbyte 0x14 0.--18. 1. " TDINIT2 ,DRAM initialization time 2" line.long 0x18 "PTR6,PHY Timing Register 6" hexmask.long.byte 0x18 20.--26. 1. " TDINIT4 ,DRAM initialization time 4" hexmask.long.word 0x18 0.--11. 1. " TDINIT3 ,DRAM initialization time 3" group.long 0x68++0x17 line.long 0x00 "PLLCR0,PLL Control Register 0" bitfld.long 0x00 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x00 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x00 28. " RSTOPM ,Reference stop mode" "Disabled,Enabled" newline bitfld.long 0x00 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x00 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12. " GSHIFT ,Gear shift" "Disabled,Enabled" bitfld.long 0x00 8. " ATOEN ,Analog test enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "PLLCR1,PLL Control Register 1" hexmask.long.word 0x04 16.--31. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x04 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x04 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypassed,Bypassed" bitfld.long 0x04 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x04 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x04 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x04 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x08 "PLLCR2,PLL Control Register 2" line.long 0x0C "PLLCR3,PLL Control Register 3" line.long 0x10 "PLLCR4,PLL Control Register 4" line.long 0x14 "PLLCR5,PLL Control Register 5" hexmask.long.byte 0x14 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL generator control bus PLL_CTRL" group.long 0x88++0x03 line.long 0x00 "DXCCR,DATX8 Common Configuration Register" bitfld.long 0x00 29. " RKLOOP ,Rank looping (per-rank eye centering) enable" "Disabled,Enabled" bitfld.long 0x00 3.--6. " DQS2DQMPER ,Write DQS2DQ training measurement period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x90++0x03 line.long 0x00 "DSGCR,DDR System General Configuration Register" bitfld.long 0x00 27. " RDBICLSEL ,Select RDBI CL calculation" "Default,RDBICL" bitfld.long 0x00 24.--26. " RDBICL ,RDBI CL adjust value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. " PHYZUEN ,PHY impedance update enable" "Disabled,Enabled" bitfld.long 0x00 21. " RSTOE ,SDRAM reset output enable" "Disabled,Enabled" newline bitfld.long 0x00 19.--20. " SDRMODE ,Single data rate mode" "0,1,2,3" bitfld.long 0x00 17. " ATOAE ,ATO analog test enable" "Disabled,Enabled" bitfld.long 0x00 16. " DTOOE ,DTO output enable" "Disabled,Enabled" bitfld.long 0x00 15. " DTOIOM ,DTO I/O mode" "Disabled,Enabled" newline bitfld.long 0x00 14. " DTOPDR ,DTO power down receiver" "Disabled,Enabled" bitfld.long 0x00 12. " DTOODT ,DTO on-die termination" "Disabled,Enabled" bitfld.long 0x00 6.--11. " PUAD ,PHY update acknowledge delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 5. " CUAEN ,Controller update acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " MSTRVER ,Controller impedance update enable" "Disabled,Enabled" bitfld.long 0x00 2. " CTLZUEN ,Controller impedance update enable" "Disabled,Enabled" bitfld.long 0x00 1. " MREN ,Master request enable" "Disabled,Enabled" bitfld.long 0x00 0. " PUREN ,PHY update request enable" "Disabled,Enabled" group.long 0x98++0x03 line.long 0x00 "ODTCR,ODT Configuration Register" bitfld.long 0x00 16. " WRODT ,Write ODT" "0,1" bitfld.long 0x00 0. " RDODT ,Read ODT" "0,1" group.long 0xA0++0x03 line.long 0x00 "AACR,Anti-Aging Control Register" bitfld.long 0x00 31. " AAOENC ,Anti-aging PAD output enable control" "Disabled,Enabled" bitfld.long 0x00 30. " AAENC ,Anti-aging enable control" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " AATR ,Anti-aging toggle rate" group.long 0xC0++0x07 line.long 0x00 "GPR0,General Purpose Register 0" line.long 0x04 "GPR1,General Purpose Register 1" group.long 0x100++0x03 line.long 0x00 "DCR,DRAM Configuration Register" bitfld.long 0x00 31. " GEARDN ,DDR4 gear down timing" "0,1" bitfld.long 0x00 30. " UBG ,Un-used bank group" "0,1" bitfld.long 0x00 29. " UDIMM ,Un-buffered DIMM address mirroring" "Disabled,Enabled" bitfld.long 0x00 28. " DDR2T ,DDR 2T timing" "0,1" newline bitfld.long 0x00 27. " NOSRA ,No simultaneous rank access" "No,Yes" hexmask.long.word 0x00 10.--17. 1. " BYTEMASK ,Byte mask" bitfld.long 0x00 8.--9. " DDRTYPE ,DDR type" "0,1,2,3" bitfld.long 0x00 7. " MPRDQ ,Multi-purpose register DQ" "0,1" newline bitfld.long 0x00 4.--6. " PDQ ,Primary DQ" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " DDR8BNK ,DDR 8-bank" "Disabled,Enabled" bitfld.long 0x00 0.--2. " DDRMD ,DDR mode" "0,1,2,3,4,5,6,7" group.long 0x110++0x1B line.long 0x00 "DTPR0,DRAM Timing Parameters Register 0" bitfld.long 0x00 24.--28. " TRRD ,Activate to activate command delay on different banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 16.--22. 1. " TRAS ,Activate to precharge command delay" hexmask.long.byte 0x00 8.--14. 1. " TRP ,Precharge command period" bitfld.long 0x00 0.--4. " TRTP ,Internal read to precharge command delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DTPR1,DRAM Timing Parameters Register 1" hexmask.long.byte 0x04 24.--30. 1. " TWLMRD ,Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge" hexmask.long.byte 0x04 16.--22. 1. " TFAW ,4-bank activate period" bitfld.long 0x04 8.--10. " TMOD ,Load mode update delay" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--4. " TMRD ,Load mode cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "DTPR2,DRAM Timing Parameters Register 2" bitfld.long 0x08 28. " TRTW ,Read to write command delay" "0,1" bitfld.long 0x08 24. " TRTODT ,Read to ODT delay" "0,1" bitfld.long 0x08 16.--19. " TCKE ,CKE minimum pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x08 0.--9. 1. " TXS ,Self refresh exit delay" line.long 0x0C "DTPR3,DRAM Timing Parameters Register 3" bitfld.long 0x0C 29.--31. " TOFDX ,ODT turn-off delay extension" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 26.--28. " TCCD ,Read to read and write to write command delay" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 16.--25. 1. " TDLLK ,DLL locking time" bitfld.long 0x0C 8.--11. " TDQSCKMAX ,Maximum DQS output access time from CK/CK#" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 0.--2. " TDQSCK ,DQS output access time from CK/CK#" "0,1,2,3,4,5,6,7" line.long 0x10 "DTPR4,DRAM Timing Parameters Register 4" bitfld.long 0x10 28.--29. " TAOND_TAOFD ,ODT turn-on/turn-off delays" "0,1,2,3" hexmask.long.word 0x10 16.--25. 1. " TRFC ,Refresh-to-refresh" bitfld.long 0x10 8.--13. " TWLO ,Write leveling output delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 0.--4. " TXP ,Power down exit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "DTPR5,DRAM Timing Parameters Register 5" hexmask.long.byte 0x14 16.--23. 1. " TRC ,Activate to activate command delay same bank" hexmask.long.byte 0x14 8.--14. 1. " TRCD ,Activate to read or write delay" bitfld.long 0x14 0.--4. " TWTR ,Internal write to read command delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "DTPR6,DRAM Timing Parameters Register 6" bitfld.long 0x18 31. " PUBWLEN ,PUB write latency enable" "Disabled,Enabled" bitfld.long 0x18 30. " PUBRLEN ,PUB read latency enable" "Disabled,Enabled" bitfld.long 0x18 8.--13. " PUBWL ,Write latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " PUBRL ,Read latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x140++0x0B line.long 0x00 "RDIMMGCR0,RDIMM General Configuration Register 0" bitfld.long 0x00 30. " QCSEN ,RDMIMM quad CS enable" "Disabled,Enabled" bitfld.long 0x00 27. " RDIMMIOM ,RDIMM outputs I/O mode" "Disabled,Enabled" bitfld.long 0x00 23. " ERROUTOE ,ERROUT# output enable" "Disabled,Enabled" bitfld.long 0x00 22. " ERROUTIOM ,ERROUT# I/O mode" "Disabled,Enabled" newline bitfld.long 0x00 21. " ERROUTPDR ,ERROUT# power down receiver" "No,Yes" bitfld.long 0x00 19. " ERROUTODT ,ERROUT# on-die termination" "Disabled,Enabled" bitfld.long 0x00 18. " LRDIMM ,Load reduced DIMM" "Disabled,Enabled" bitfld.long 0x00 17. " PARINIOM ,PAR_IN I/O mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " RNKMRREN ,Rank mirror enable" "Disabled,Enabled" bitfld.long 0x00 2. " SOPERR ,Stop on parity error" "Disabled,Enabled" bitfld.long 0x00 1. " ERRNOREG ,Parity error no registering" "No,Yes" bitfld.long 0x00 0. " RDIMM ,Registered DIMM" "Not registered,Registered" line.long 0x04 "RDIMMGCR1,RDIMM General Configuration Register 1" bitfld.long 0x04 28. " A17BID ,Address [17] B-side inversion disable" "No,Yes" bitfld.long 0x04 24.--26. " TBCMRD_L2 ,Command word to command word programming delay" "0,1,2,3,4,5,6,7" bitfld.long 0x04 20.--22. " TBCMRD_L ,Command word to command word programming delay" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " TBCMRD ,Command word to command word programming delay" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x04 0.--13. 1. " TBCSTAB ,Stabilization time" line.long 0x08 "RDIMMGCR2,RDIMM General Configuration Register 2" group.long 0x150++0x13 line.long 0x00 "RDIMMCR0,RDIMM Control Register 0" bitfld.long 0x00 28.--31. " RC7 ,DDR3 control word 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " RC5 ,DDR3 CK driver characteristics control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " RC4 ,DDR3 control signals driver characteristics control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " RC3 ,DDR3 control signals driver characteristics control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " RC2 ,DDR3 timing control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " RC1 ,DDR3 clock driver enable control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RC0 ,DDR3 global features control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "RDIMMCR1,RDIMM Control Register 1" bitfld.long 0x04 28.--31. " RC15 ,Control word 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 12.--15. " RC11 ,DDR3 operation voltage VDD control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " RC10 ,DDR3 RDIMM operating speed control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " RC9 ,DDR3 power saving settings control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " RC8 ,DDR3 additional input bus termination setting control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "RDIMMCR2,RDIMM Control Register 2" hexmask.long.byte 0x08 24.--31. 1. " RC4X ,Control word RC4X" hexmask.long.byte 0x08 16.--23. 1. " RC3X ,Control word RC3X" hexmask.long.byte 0x08 8.--15. 1. " RC2X ,Control word RC2X" hexmask.long.byte 0x08 0.--7. 1. " RC1X ,Control word RC1X" line.long 0x0C "RDIMMCR3,RDIMM Control Register 3" hexmask.long.byte 0x0C 24.--31. 1. " RC8X ,Control word RC8X" hexmask.long.byte 0x0C 16.--23. 1. " RC7X ,Control word RC7X" hexmask.long.byte 0x0C 8.--15. 1. " RC6X ,Control word RC6X" hexmask.long.byte 0x0C 0.--7. 1. " RC5X ,Control word RC5X" line.long 0x10 "RDIMMCR4,RDIMM Control Register 4" hexmask.long.byte 0x10 16.--23. 1. " RCBX ,Control word RC11X" hexmask.long.byte 0x10 8.--15. 1. " RCAX ,Control word RC10X" hexmask.long.byte 0x10 0.--7. 1. " RC9X ,Control word RC9X" group.long 0x168++0x07 line.long 0x00 "SCHCR0,Scheduler Command Register 0" hexmask.long.word 0x00 16.--24. 1. " SCHDQV ,Scheduler command DQ value" bitfld.long 0x00 8.--11. " SP_CMD ,Special command codes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CMD ,Specifies the command to be issued" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " SCHTRIG ,Mode register command trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SCHCR1,Scheduler Command Register 1" bitfld.long 0x04 28.--31. " SCRNK ,Scheduler rank address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x04 8.--27. 0x01 " SCADDR ,Scheduler command address specifies the value to be driven on the address bus" bitfld.long 0x04 6.--7. " SCBG ,Scheduler command bank group" "0,1,2,3" bitfld.long 0x04 4.--5. " SCBK ,Scheduler command bank address" "0,1,2,3" newline bitfld.long 0x04 2. " ALLRANK ,All ranks enabled" "Disabled,Enabled" group.long 0x180++0x0F line.long 0x00 "MR0,LPDDR4 Mode Register 0" bitfld.long 0x00 7. " CATR ,CA terminating rank" "0,1" bitfld.long 0x00 3.--4. " RZQI ,Built-in self-test for RZQ" "0,1,2,3" line.long 0x04 "MR1,LPDDR4 Mode Register 1" bitfld.long 0x04 7. " RDPST ,Read postamble length" "0,1" bitfld.long 0x04 4.--6. " NWR ,Write-recovery for auto-precharge command" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3. " RDPRE ,Read preamble length" "0,1" bitfld.long 0x04 2. " WRPRE ,Write preamble length" "0,1" newline bitfld.long 0x04 0.--1. " BL ,Burst length" "0,1,2,3" line.long 0x08 "MR2,LPDDR4 Mode Register 2" bitfld.long 0x08 7. " WRL ,Write leveling" "Disabled,Enabled" bitfld.long 0x08 6. " WLS ,Write latency set" "0,1" bitfld.long 0x08 3.--5. " WL ,Write latency" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0.--2. " RL ,Read latency" "0,1,2,3,4,5,6,7" line.long 0x0C "MR3,LPDDR4 Mode Register 3" bitfld.long 0x0C 7. " DBIWR ,DBI-write enable" "Disabled,Enabled" bitfld.long 0x0C 6. " DBIRD ,DBI-read enable" "Disabled,Enabled" bitfld.long 0x0C 3.--5. " PDDS ,Pull-down drive strength" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 1. " WRPST ,Write postamble length" "0,1" newline bitfld.long 0x0C 0. " PUCAL ,Pull-up calibration point" "0,1" group.long 0x1AC++0x0F line.long 0x00 "MR11,LPDDR4 Mode Register 11" bitfld.long 0x00 4.--6. " CAODT ,CA bus receiver on-die-termination" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " DQODT ,DQ bus receiver on-die-termination" "0,1,2,3,4,5,6,7" line.long 0x04 "MR12,LPDDR4 Mode Register 12" bitfld.long 0x04 6. " VR_CA ,VREF_CA range select" "0,1" bitfld.long 0x04 0.--5. " VREF_CA ,Controls the VREF_CA levels for frequency-set-point[1:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "MR13,LPDDR4 Mode Register 13" bitfld.long 0x08 7. " FSPOP ,Frequency set point operation mode" "0,1" bitfld.long 0x08 6. " FSPWR ,Frequency set point write enable" "Disabled,Enabled" bitfld.long 0x08 5. " DMD ,Data mask enable" "Disabled,Enabled" bitfld.long 0x08 4. " RRO ,Refresh rate option" "0,1" newline bitfld.long 0x08 3. " VRCG ,VREF current generator" "0,1" bitfld.long 0x08 2. " VRO ,VREF output" "0,1" bitfld.long 0x08 1. " RPT ,Read preamble training mode" "Disabled,Enabled" bitfld.long 0x08 0. " CBT ,Command bus training" "Disabled,Enabled" line.long 0x0C "MR14,LPDDR4 Mode Register 14" bitfld.long 0x0C 6. " VR_DQ ,VREFDQ range selects" "0,1" group.long 0x1D8++0x03 line.long 0x00 "MR22,LPDDR4 Mode Register 22" bitfld.long 0x00 5. " ODTD_CA ,CA ODT termination disable" "No,Yes" bitfld.long 0x00 4. " ODTE_CS ,ODT CS override" "No override,Override" bitfld.long 0x00 3. " ODTE_CK ,ODT CK override" "No override,Override" bitfld.long 0x00 0.--2. " CODT ,Controller ODT value for VOH calibration" "0,1,2,3,4,5,6,7" group.long 0x200++0x13 line.long 0x00 "DTCR0,Data Training Configuration Register 0" bitfld.long 0x00 28.--31. " RFSHDT ,Refresh during training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--25. " DTDRS ,Data training debug rank select" "0,1,2,3" bitfld.long 0x00 23. " DTEXG ,Data training with early/extended gate" "Disabled,Enabled" bitfld.long 0x00 22. " DTEXD ,Data training extended write DQS" "Disabled,Enabled" newline bitfld.long 0x00 21. " DTDSTP ,Data training debug step" "0,1" bitfld.long 0x00 20. " DTDEN ,Data training debug enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " DTDBS ,Data training debug byte select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " DTRDBITR ,Data training read DBI deskewing configuration" "0,1,2,3" newline bitfld.long 0x00 13. " DTBDC ,Data training bit deskew centering" "0,1" bitfld.long 0x00 12. " DTWBDDM ,Data training write bit deskew data mask" "Not masked,Masked" bitfld.long 0x00 8.--11. " RFSHEN ,Refreshes issued during entry to training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " DTCMPD ,Data training compare data" "0,1" newline bitfld.long 0x00 6. " DTMPR ,Data training using MPR" "Disabled,Enabled" bitfld.long 0x00 4. " INCWEYE ,WEYE training using MPC FIFO commands" "0,1" bitfld.long 0x00 0.--3. " DTRPTN ,Data training repeat number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DTCR1,Data Training Configuration Register 1" bitfld.long 0x04 16. " RANKEN ,Rank enable" "Disabled,Enabled" bitfld.long 0x04 12.--13. " DTRANK ,Data training rank" "0,1,2,3" bitfld.long 0x04 8.--10. " RDLVLGDIFF ,Read leveling gate sampling difference" "0,1,2,3,4,5,6,7" bitfld.long 0x04 4.--6. " RDLVLGS ,Read leveling gate shift" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 2. " RDPRMVL_TRN ,Read preamble training enable" "Disabled,Enabled" bitfld.long 0x04 1. " RDLVLEN ,Read leveling enable" "Disabled,Enabled" bitfld.long 0x04 0. " BSTEN ,Basic gate training enable" "Disabled,Enabled" line.long 0x08 "DTAR0,Data Training Address Register 0" bitfld.long 0x08 28.--29. " MPRLOC ,Multi-Purpose register MPR location" "0,1,2,3" hexmask.long.byte 0x08 24.--27. 0x01 " DTBGBK1 ,Data training bank group and bank address" hexmask.long.byte 0x08 20.--23. 0x10 " DTBGBK0 ,Data training bank group and bank address" hexmask.long.tbyte 0x08 0.--17. 0x01 " DTROW ,Data training row address" line.long 0x0C "DTAR1,Data Training Address Register 1" hexmask.long.word 0x0C 16.--24. 0x01 " DTCOL1 ,Data training column address" hexmask.long.word 0x0C 0.--8. 0x01 " DTCOL0 ,Data training column address" line.long 0x10 "DTAR2,Data Training Address Register 2" hexmask.long.word 0x10 16.--24. 0x01 " DTCOL3 ,Data training column address" hexmask.long.word 0x10 0.--8. 0x01 " DTCOL2 ,Data training column address" group.long 0x218++0x07 line.long 0x00 "DTDR0,Data Training Data Register 0" hexmask.long.byte 0x00 24.--31. 1. " DTBYTE3 ,Data training data" hexmask.long.byte 0x00 16.--23. 1. " DTBYTE2 ,Data training data" hexmask.long.byte 0x00 8.--15. 1. " DTBYTE1 ,Data training data" hexmask.long.byte 0x00 0.--7. 1. " DTBYTE0 ,Data training data" line.long 0x04 "DTDR1,Data Training Data Register 1" hexmask.long.byte 0x04 24.--31. 1. " DTBYTE7 ,Data training data" hexmask.long.byte 0x04 16.--23. 1. " DTBYTE6 ,Data training data" hexmask.long.byte 0x04 8.--15. 1. " DTBYTE5 ,Data training data" hexmask.long.byte 0x04 0.--7. 1. " DTBYTE4 ,Data training data" rgroup.long 0x230++0x0F line.long 0x00 "DTEDR0,Data Training Eye Data Register 0" hexmask.long.byte 0x00 24.--31. 1. " WDQMBX ,Data training write BDL shift maximum" bitfld.long 0x00 18.--23. " WDQBMN ,Data training write BDL shift minimum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 9.--17. 1. " WDQLMX ,Data training WDQ LCDL maximum" hexmask.long.word 0x00 0.--8. 1. " WDQLMN ,Data training WDQ LCDL minimum" line.long 0x04 "DTEDR1,Data Training Eye Data Register 1" hexmask.long.byte 0x04 24.--31. 1. " RDQSBMX ,Data training read BDL shift maximum" bitfld.long 0x04 18.--23. " RDQSBMN ,Data training read BDL shift minimum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x04 9.--17. 1. " RDQSLMX ,Data training RDQS LCDL maximum" hexmask.long.word 0x04 0.--8. 1. " RDQSLMN ,Data training RDQS LCDL minimum" line.long 0x08 "DTEDR2,Data Training Eye Data Register 2" hexmask.long.byte 0x08 24.--31. 1. " RDQSNBMX ,Data training read BDL shift maximum" bitfld.long 0x08 18.--23. " RDQSNBMN ,Data training read BDL shift minimum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x08 9.--17. 1. " RDQSNLMX ,Data training RDQSN LCDL maximum" hexmask.long.word 0x08 0.--8. 1. " RDQSNLMN ,Data training RDQSN LCDL minimum" line.long 0x0C "VTDR,VREF Training Data Register" hexmask.long.byte 0x0C 24.--30. 1. " HVREFMX ,DRAM DQ VREF maximum" hexmask.long.byte 0x0C 16.--22. 1. " HVREFMN ,DRAM DQ VREF minimum" bitfld.long 0x0C 8.--13. " DVREFMX ,DRAM DQ VREF maximum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " DVREFMN ,DRAM DQ VREF minimum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x240++0x0B line.long 0x00 "CATR0,CA Training Register 0" bitfld.long 0x00 16.--20. " CACD ,Minimum time between two consecutive CA calibration command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " CAADR ,Minimum wait time before sampling the CA response after calibration command has been sent to the memory" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " CA1BYTE1 ,CA_1 response byte lane 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CA1BYTE0 ,CA_1 response byte lane 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "CATR1,CA Training Register 1" bitfld.long 0x04 24.--27. " CA0BYTE1 ,CA_0 response byte lane 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 20.--23. " CA0BYTE0 ,CA_0 response byte lane 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " CAMRZ ,Minimum time for DRAM DQ going tristate after MRW CA exit calibration command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 12.--15. " CACKEH ,Minimum time for CKE high after last CA calibration response is driven by memory" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " CACKEL ,Minimum time for CKE going low after CA calibration mode is programmed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " CAEXT ,Minimum time for CA calibration exit command after CKE is high" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CAENT ,Minimum time for first CA calibration command after CKE is low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "PGCR8,PHY General Configuration Register 8" bitfld.long 0x08 28.--31. " CF ,Counter cycles factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x08 20.--27. 1. " CM ,Counter cycle multiplier" bitfld.long 0x08 16. " RANKEN ,Rank enable" "Disabled,Enabled" bitfld.long 0x08 15. " MODE ,Self incremental DQS2DQ training" "Disabled,Enabled" newline bitfld.long 0x08 14. " EN ,Incremental DQS2DQ training" "Disabled,Enabled" bitfld.long 0x08 8. " BSWAPMSB[8] ,PHY 8 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" bitfld.long 0x08 7. " [7] ,PHY 7 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" bitfld.long 0x08 6. " [6] ,PHY 6 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" newline bitfld.long 0x08 5. " [5] ,PHY 5 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" bitfld.long 0x08 4. " [4] ,PHY 4 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" bitfld.long 0x08 3. " [3] ,PHY 3 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" bitfld.long 0x08 2. " [2] ,PHY 2 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" newline bitfld.long 0x08 1. " [1] ,PHY 1 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" bitfld.long 0x08 0. " [0] ,PHY 0 byte lane connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to" "Not connected,Connected" group.long 0x250++0x0B line.long 0x00 "DQSDR0,DQS Drift Register 0" bitfld.long 0x00 28.--31. " DFTDLY ,Number of delay taps by which the DQS gate LCDL will be updated when DQS drift is detected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. " DFTZQUP ,Drift impedance update" "Not updated,Updated" bitfld.long 0x00 26. " DFTDDLUP ,Drift DDL update" "Not updated,Updated" bitfld.long 0x00 20.--21. " DFTRDSPC ,Drift read spacing" "0,1,2,3" newline bitfld.long 0x00 16.--19. " DFTB2BRD ,Drift back-to-back reads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DFTIDLRD ,Drift idle reads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DFTGPULSE ,Gate pulse enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--3. " DFTUPMODE ,DQS drift update mode" "0,1,2,3" newline bitfld.long 0x00 1. " DFTDTMODE ,DQS drift detection mode" "0,1" bitfld.long 0x00 0. " DFTDTEN ,DQS drift detection enable" "Disabled,Enabled" line.long 0x04 "DQSDR1,DQS Drift Register 1" bitfld.long 0x04 29.--31. " DFTUPDACKF ,Drift DFU update request ACK to DQS drift FSM issuing IDLE read cycles factor" "0,1,2,3,4,5,6,7" bitfld.long 0x04 24.--28. " DFTUPDACKC ,Drift DFI update request ACK to DQS drift FSM issuing IDLE read cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 20.--23. " DFTRDB2BF ,Drift Back-to-Back read cycles factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " DFTRDIDLF ,Drift idle read cycles factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x04 8.--15. 1. " DFTRDB2BC ,Drift Back-to-Back read cycles" hexmask.long.byte 0x04 0.--7. 1. " DFTRDIDLC ,Drift idle read cycles" line.long 0x08 "DQSDR2,DQS Drift Register 2" hexmask.long.byte 0x08 16.--23. 1. " DFTTHRSH ,Drift threshold" hexmask.long.word 0x08 0.--15. 1. " DFTMNTPRD ,Drift monitor period" group.long 0x300++0x17 line.long 0x00 "DCUAR,DCU Address Register" hexmask.long.byte 0x00 16.--19. 0x01 " CSADDR_R ,Cache slice address" hexmask.long.byte 0x00 12.--15. 0x10 " CWADDR_R ,Cache word address" bitfld.long 0x00 11. " ATYPE ,Access type" "0,1" bitfld.long 0x00 10. " INCA ,Increment address" "0,1" newline bitfld.long 0x00 8.--9. " CSEL ,Cache select" "0,1,2,3" hexmask.long.byte 0x00 4.--7. 0x10 " CSADDR_W ,Cache slice address" hexmask.long.byte 0x00 0.--3. 0x01 " CWADDR_W ,Cache word address" line.long 0x04 "DCUDR,DCU Data Register" line.long 0x08 "DCURR,DCU Run Register" bitfld.long 0x08 23. " XCEN ,Expected compare enable" "Disabled,Enabled" bitfld.long 0x08 22. " RCEN ,Read capture enable" "Disabled,Enabled" bitfld.long 0x08 21. " SCOF ,Stop capture on full" "0,1" bitfld.long 0x08 20. " SONF ,Stop on n-th fail" "0,1" newline hexmask.long.byte 0x08 12.--19. 1. " NFAIL ,Number of failures" hexmask.long.byte 0x08 8.--11. 0x01 " EADDR ,End address" hexmask.long.byte 0x08 4.--7. 0x10 " SADDR ,Start address" bitfld.long 0x08 0.--3. " DINST ,DCU instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "DCULR,DCU Loop Register" hexmask.long.byte 0x0C 28.--31. 0x10 " XLEADDR ,Expected data loop end address" bitfld.long 0x0C 17. " IDA ,Increment DRAM address" "0,1" bitfld.long 0x0C 16. " LINF ,Loop infinite" "0,1" hexmask.long.byte 0x0C 8.--15. 1. " LCNT ,Loop count" newline hexmask.long.byte 0x0C 4.--7. 0x10 " LEADDR ,Loop end address" hexmask.long.byte 0x0C 0.--3. 0x01 " LSADDR ,Loop start address" line.long 0x10 "DCUGCR,DCU General Configuration Register" hexmask.long.word 0x10 0.--15. 1. " RCSW ,Read capture start word" line.long 0x14 "DCUTPR,DCU Timing Parameters Register" hexmask.long.word 0x14 16.--31. 1. " TDCUT2 ,DCU generic timing parameter 2" hexmask.long.byte 0x14 8.--15. 1. " TDCUT1 ,DCU generic timing parameter 1" hexmask.long.byte 0x14 0.--7. 1. " TDCUT0 ,DCU generic timing parameter 0" rgroup.long 0x318++0x07 line.long 0x00 "DCUSR0,DCU Status Register 0" bitfld.long 0x00 2. " CFULL ,Capture full" "Not full,Full" bitfld.long 0x00 1. " CFAIL ,Capture fail" "Not failed,Failed" bitfld.long 0x00 0. " RDONE ,Run done" "Not done,Done" line.long 0x04 "DCUSR1,DCU Status Register 1" hexmask.long.byte 0x04 24.--31. 1. " LPCNT ,Loop count" hexmask.long.byte 0x04 16.--23. 1. " FLCNT ,Fail count" hexmask.long.word 0x04 0.--15. 1. " RDCNT ,Read count" group.long 0x400++0x2F line.long 0x00 "BISTRR,BIST Run Register" bitfld.long 0x00 29. " BPRBST ,BIST PRBS type" "0,1" bitfld.long 0x00 28. " BSOMA ,BIST stop on maximum address" "Disabled,Enabled" bitfld.long 0x00 26.--27. " BACDPAT ,BIST AC data pattern" "0,1,2,3" bitfld.long 0x00 25. " BCCSEL ,BIST clock cycle select" "0,1" newline bitfld.long 0x00 23.--24. " BCKSEL ,BIST CK select" "0,1,2,3" bitfld.long 0x00 19.--22. " BDXSEL ,BIST DATX8 select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 17.--18. " BDXDPAT ,BIST data pattern" "0,1,2,3" bitfld.long 0x00 16. " BDMEN ,BIST data mask enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " BACEN ,BIST AC enable" "Disabled,Enabled" bitfld.long 0x00 14. " BDXEN ,BIST DATX8 enable" "Disabled,Enabled" bitfld.long 0x00 13. " BSONF ,BIST stop on nth fail" "Disabled,Enabled" hexmask.long.word 0x00 5.--12. 1. " NFAIL ,Number of failures" newline bitfld.long 0x00 4. " BINF ,BIST infinite run" "0,1" bitfld.long 0x00 3. " BMODE ,BIST mode" "0,1" bitfld.long 0x00 0.--2. " BINST ,BIST instruction" "0,1,2,3,4,5,6,7" line.long 0x04 "BISTWCR,BIST Word Count Register" hexmask.long.word 0x04 16.--31. 1. " BACWCNT ,BIST AC word count" hexmask.long.word 0x04 0.--15. 1. " BDXWCNT ,BIST DX word count" newline line.long 0x08 "BISTMSKR0,BIST Mask Register 0" bitfld.long 0x08 20. " CSMSK ,Mask bit for CS_N bit 0" "0,1" bitfld.long 0x08 19. " ACTMSK ,Mask bit for the RAS" "0,1" newline bitfld.long 0x08 17. " AMSK[17:0] ,Mask bit for address bit 17" "0,1" bitfld.long 0x08 16. ",Mask bit for address bit 16" "0,1" bitfld.long 0x08 15. ",Mask bit for address bit 15" "0,1" bitfld.long 0x08 14. ",Mask bit for address bit 14" "0,1" bitfld.long 0x08 13. ",Mask bit for address bit 13" "0,1" bitfld.long 0x08 12. ",Mask bit for address bit 12" "0,1" bitfld.long 0x08 11. ",Mask bit for address bit 11" "0,1" bitfld.long 0x08 10. ",Mask bit for address bit 10" "0,1" bitfld.long 0x08 9. ",Mask bit for address bit 9" "0,1" bitfld.long 0x08 8. ",Mask bit for address bit 8" "0,1" bitfld.long 0x08 7. ",Mask bit for address bit 7" "0,1" bitfld.long 0x08 6. ",Mask bit for address bit 6" "0,1" bitfld.long 0x08 5. ",Mask bit for address bit 5" "0,1" bitfld.long 0x08 4. ",Mask bit for address bit 4" "0,1" bitfld.long 0x08 3. ",Mask bit for address bit 3" "0,1" bitfld.long 0x08 2. ",Mask bit for address bit 2" "0,1" bitfld.long 0x08 1. ",Mask bit for address bit 1" "0,1" bitfld.long 0x08 0. ",Mask bit for address bit 0" "0,1" line.long 0x0C "BISTMSKR1,BIST Mask Register 1" bitfld.long 0x0C 31. " DMMSK[3] ,Mask bit for the data mask DM bit 3" "0,1" bitfld.long 0x0C 30. " [2] ,Mask bit for the data mask DM bit 2" "0,1" bitfld.long 0x0C 29. " [1] ,Mask bit for the data mask DM bit 1" "0,1" bitfld.long 0x0C 28. " [0] ,Mask bit for the data mask DM bit 0" "0,1" newline bitfld.long 0x0C 27. " PARINMSK ,Mask bit for the PAR_IN" "0,1" bitfld.long 0x0C 24. " CIDMSK ,Mask bits for chip IP bits" "0,1" bitfld.long 0x0C 16. " ODTMSK ,Mask bit for ODT bit" "0,1" bitfld.long 0x0C 8. " CKEMSK ,Mask bit for CKE bit" "0,1" newline bitfld.long 0x0C 7. " BAMSK[3] ,Mask bit for bank address bit 3" "0,1" bitfld.long 0x0C 6. " [2] ,Mask bit for bank address bit 2" "0,1" bitfld.long 0x0C 5. " [1] ,Mask bit for bank address bit 1" "0,1" bitfld.long 0x0C 4. " [0] ,Mask bit for bank address bit 0" "0,1" line.long 0x10 "BISTMSKR2,BIST Mask Register 2" newline line.long 0x14 "BISTLSR,BIST LFSR Seed Register" line.long 0x18 "BISTAR0,BIST Address Register 0" hexmask.long.byte 0x18 28.--31. 0x10 " BBANK ,BIST bank address" hexmask.long.word 0x18 0.--11. 0x01 " BCOL ,BIST column address" line.long 0x1C "BISTAR1,BIST Address Register 1" bitfld.long 0x1C 16.--19. " BMRANK ,BIST maximum rank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x1C 4.--15. 1. " BAINC ,BIST address increment" bitfld.long 0x1C 0.--3. " BRANK ,BIST rank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x20 "BISTAR2,BIST Address Register 2" hexmask.long.byte 0x20 28.--31. 0x10 " BMBANK ,BIST maximum bank address" hexmask.long.word 0x20 0.--11. 0x01 " BMCOL ,BIST maximum column address" line.long 0x24 "BISTAR3,BIST Address Register 3" hexmask.long.tbyte 0x24 0.--17. 0x01 " BROW ,BIST row address" line.long 0x28 "BISTAR4,BIST Address Register 4" hexmask.long.tbyte 0x28 0.--17. 0x01 " BMROW ,BIST maximum row address" line.long 0x2C "BISTUDPR,BIST User Data Pattern Register" hexmask.long.word 0x2C 16.--31. 1. " BUDP1 ,BIST user data pattern 1" hexmask.long.word 0x2C 0.--15. 1. " BUDP0 ,BIST user data pattern 0" rgroup.long 0x430++0x33 line.long 0x00 "BISTGSR,BIST General Status Register" bitfld.long 0x00 28.--29. " RASBER ,RAS_n/ACT_n bit error" "0,1,2,3" hexmask.long.byte 0x00 20.--27. 1. " DMBER ,DM bit error" hexmask.long.word 0x00 2.--10. 1. " BDXERR ,BIST data error" bitfld.long 0x00 1. " BACERR ,BIST address/command error" "No error,Error" newline bitfld.long 0x00 0. " BDONE ,BIST done" "Not done,Done" line.long 0x04 "BISTWER0,BIST Word Error Register 0" hexmask.long.tbyte 0x04 0.--17. 1. " ACWER ,Address/command word error" line.long 0x08 "BISTWER1,BIST Word Error Register 1" hexmask.long.word 0x08 0.--15. 1. " DXWER ,Byte word error" line.long 0x0C "BISTBER0,BIST Bit Error Register 0" line.long 0x10 "BISTBER1,BIST Bit Error Register 1" bitfld.long 0x10 8.--9. " CSBER ,CS_N bit error" "0,1,2,3" hexmask.long.byte 0x10 0.--7. 1. " BABER ,Bank address bit error" line.long 0x14 "BISTBER2,BIST Bit Error Register 2" line.long 0x18 "BISTBER3,BIST Bit Error Register 3" line.long 0x1C "BISTBER4,BIST Bit Error Register 4" bitfld.long 0x1C 8.--9. " CIDBER ,Chip ID bit error" "0,1,2,3" bitfld.long 0x1C 0.--3. " ABER ,Address bit error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x20 "BISTWCSR,BIST Word Count Status Register" hexmask.long.word 0x20 16.--31. 1. " DXWCNT ,Byte word count" hexmask.long.word 0x20 0.--15. 1. " ACWCNT ,Address/command word count" line.long 0x24 "BISTFWR0,BIST Fail Word Register 0" bitfld.long 0x24 20. " CSWEBS ,Bit status during a word error for CS# bits" "No error,Error" bitfld.long 0x24 18. " ACTWEBS ,Bit status during a word error for the RAS" "No error,Error" hexmask.long.tbyte 0x24 0.--17. 1. " AWEBS ,Bit status during a word error for address bits" line.long 0x28 "BISTFWR1,BIST Fail Word Register 1" bitfld.long 0x28 31. " DMWEBS[3] ,Bit status during a word error for the data mask DM bit 3" "No error,Error" bitfld.long 0x28 30. " [2] ,Bit status during a word error for the data mask DM bit 2" "No error,Error" bitfld.long 0x28 29. " [1] ,Bit status during a word error for the data mask DM bit 1" "No error,Error" bitfld.long 0x28 28. " [0] ,Bit status during a word error for the data mask DM bit 0" "No error,Error" newline bitfld.long 0x28 20. " CIDWEBS ,Bit status during a word error for chip ID bits" "No error,Error" bitfld.long 0x28 19. " BAWEBS[3] ,Bit status during a word error for the bank address bit 3" "No error,Error" bitfld.long 0x28 18. " [2] ,Bit status during a word error for the bank address bit 2" "No error,Error" bitfld.long 0x28 17. " [1] ,Bit status during a word error for the bank address bit 1" "No error,Error" newline bitfld.long 0x28 16. " [0] ,Bit status during a word error for the bank address bit 0" "No error,Error" bitfld.long 0x28 8. " ODTWEBS ,Bit status during a word error for the ODT bits" "No error,Error" bitfld.long 0x28 0. " CKEWEBS ,Bit status during a word error for the CKE bits" "No error,Error" line.long 0x2C "BISTFWR2,BIST Fail Word Register 2" line.long 0x30 "BISTBER5,BIST Bit Error Register 5" bitfld.long 0x30 16.--17. " ODTBER ,ODT bit error" "0,1,2,3" bitfld.long 0x30 0.--1. " CKEBER ,CKE bit error" "0,1,2,3" group.long 0x4DC++0x03 line.long 0x00 "RANKIDR,Rank ID Register" bitfld.long 0x00 16.--19. " RANKRID ,Rank read ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RANKWID ,Rank write ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4E8++0x03 line.long 0x00 "RIOCR2,Rank I/O Configuration Register 2" bitfld.long 0x00 24.--25. " COEMODE ,SDRAM C output enable (OE) mode selection" "0,1,2,3" bitfld.long 0x00 0.--1. " CSOEMODE ,SDRAM CS_n output enable (OE) mode selection" "0,1,2,3" group.long 0x4F0++0x07 line.long 0x00 "RIOCR4,Rank I/O Configuration Register 4" bitfld.long 0x00 0.--1. " CKEOEMODE ,SDRAM CKE output enable (OE) mode selection" "0,1,2,3" line.long 0x04 "RIOCR5,Rank I/O Configuration Register 5" bitfld.long 0x04 0.--1. " ODTOEMODE ,SDRAM On-die termination output enable (OE) mode selection" "0,1,2,3" newline group.long 0x500++0x17 line.long 0x00 "ACIOCR0,AC I/O Configuration Register 0" bitfld.long 0x00 30.--31. " ACSR ,Address/command slew rate (D3F I/O only)" "0,1,2,3" bitfld.long 0x00 29. " RSTIOM ,SDRAM reset I/O mode" "0,1" bitfld.long 0x00 28. " RSTPDR ,SDRAM reset power down receiver" "0,1" bitfld.long 0x00 26. " RSTODT ,SDRAM reset on-die termination" "0,1" newline hexmask.long.byte 0x00 16.--23. 1. " ESR ,Decoupling capacitance ESR control in D5M I/O ring" bitfld.long 0x00 10.--11. " ACPNUMSEL ,Address/command custom pin mapping configuration" "0,1,2,3" bitfld.long 0x00 6.--9. " CKDCC ,CK duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--5. " ACPDRMODE ,AC power down receiver mode" "0,1,2,3" newline bitfld.long 0x00 2.--3. " ACODTMODE ,AC on-die termination mode" "0,1,2,3" bitfld.long 0x00 0. " ACRANKCLKSEL ,Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices" "0,1" line.long 0x04 "ACIOCR1,AC I/O Configuration Register 1" line.long 0x08 "ACIOCR2,AC I/O Configuration Register 2" bitfld.long 0x08 31. " CLKGENCLKGATE ,Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL slice" "No gating,Gating" bitfld.long 0x08 30. " ACOECLKGATE0 ,Clock gating for output enable D slices [0]" "No gating,Gating" bitfld.long 0x08 29. " ACPDRCLKGATE0 ,Clock gating for power down receiver D slices [0]" "No gating,Gating" bitfld.long 0x08 28. " ACTECLKGATE0 ,Clock gating for termination enable D slices [0]" "No gating,Gating" newline bitfld.long 0x08 26.--27. " CKNCLKGATE0 ,Clock gating for CK# D slices [1:0]" "0,1,2,3" bitfld.long 0x08 24.--25. " CKCLKGATE0 ,Clock gating for CK D slices [1:0]" "0,1,2,3" hexmask.long.tbyte 0x08 0.--23. 1. " ACCLKGATE0 ,Clock gating for AC D slices [23:0]" line.long 0x0C "ACIOCR3,AC I/O Configuration Register 3" bitfld.long 0x0C 30.--31. " PAROEMODE ,SDRAM parity output enable (OE) mode selection" "0,1,2,3" bitfld.long 0x0C 26.--29. " BGOEMODE ,SDRAM bank group output enable (OE) mode selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 22.--25. " BAOEMODE ,SDRAM bank address output enable (OE) mode selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 20.--21. " A17OEMODE ,SDRAM A[17] output enable (OE) mode selection" "0,1,2,3" newline bitfld.long 0x0C 18.--19. " A16OEMODE ,SDRAM A[16] / RAS_N output enable (OE) mode selection" "0,1,2,3" bitfld.long 0x0C 16.--17. " ACTOEMODE ,SDRAM ACT_N output enable (OE) mode selection" "0,1,2,3" bitfld.long 0x0C 0.--3. " CKOEMODE ,SDRAM CK output enable (OE) mode selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "ACIOCR4,AC I/O Configuration Register 4" bitfld.long 0x10 31. " LBCLKGATE ,Clock gating for AC LB slices and loopback read valid slices" "No gating,Gating" bitfld.long 0x10 30. " ACOECLKGATE1 ,Clock gating for output enable D slices [1]" "No gating,Gating" bitfld.long 0x10 29. " ACPDRCLKGATE1 ,Clock gating for power down receiver D slices [1]" "No gating,Gating" bitfld.long 0x10 28. " ACTECLKGATE1 ,Clock gating for termination enable D slices [1]" "No gating,Gating" newline bitfld.long 0x10 26.--27. " CKNCLKGATE1 ,Clock gating for CK# D slices [3:2]" "0,1,2,3" bitfld.long 0x10 24.--25. " CKCLKGATE1 ,Clock gating for CK D slices [3:2]" "0,1,2,3" hexmask.long.tbyte 0x10 0.--23. 1. " ACCLKGATE1 ,Clock gating for AC D slices [47:24]" line.long 0x14 "ACIOCR5,AC I/O Configuration Register 5" bitfld.long 0x14 25.--27. " ACVREFIOM ,IOM bits for PVREF and PVREFE cells in AC IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x14 22.--24. " ACXIOM ,AC IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x14 11.--21. 1. " ACTXM ,AC IO transmitter mode" hexmask.long.word 0x14 0.--10. 1. " ACRXM ,AC IO receiver mode" group.long 0x520++0x03 line.long 0x00 "IOVCR0,IO VREF Control Register 0" bitfld.long 0x00 28. " ACREFPEN ,Address/command lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x00 26.--27. " ACREFEEN ,Address/command lane internal VREF enable" "0,1,2,3" bitfld.long 0x00 25. " ACREFSEN ,Address/command lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x00 24. " ACREFIEN ,Address/command lane internal VREF enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " ACREFESELRANGE ,External VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x00 16.--22. 1. " ACREFESEL ,Address/command lane external VREF select" bitfld.long 0x00 15. " ACREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x00 8.--14. 1. " ACREFSSEL ,Address/command lane single-end VREF select" newline bitfld.long 0x00 7. " ACVREFISELRANGE ,Internal VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x00 0.--6. 1. " ACVREFISEL ,REFSEL control for internal AC IOs" group.long 0x528++0x07 line.long 0x00 "VTCR0,VREF Training Control Register 0" bitfld.long 0x00 29.--31. " TVREF ,Number of CTL_CLK required to meet > 150ns timing requirements during DRAM DQ VREF training" "0,1,2,3,4,5,6,7" bitfld.long 0x00 28. " DVEN ,DRM DQ VREF training enable" "Disabled,Enabled" bitfld.long 0x00 27. " PDAEN ,Per device addressability enable" "Disabled,Enabled" bitfld.long 0x00 22.--25. " VWCR ,VREF word count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 18.--21. " DVSS ,DRAM DQ VREF step size used during DRAM VREF training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--17. " DVMAX ,Maximum VREF limit value used during DRAM VREF training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 6.--11. " DVMIN ,Minimum VREF limit value used during DRAM VREF training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DVINIT ,Initial DRAM DQ VREF value used during DRAM VREF training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "VTCR1,VREF Training Control Register 1" bitfld.long 0x04 28.--31. " HVSS ,Host VREF step size used during VREF training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x04 20.--26. 1. " HVMAX ,Maximum VREF limit value used during DRAM VREF training" hexmask.long.byte 0x04 12.--18. 1. " HVMIN ,Minimum VREF limit value used during DRAM VREF training" bitfld.long 0x04 9.--10. " SHRNK ,Static host VREF rank value" "0,1,2,3" newline bitfld.long 0x04 8. " SHREN ,Static host VREF rank enable" "Disabled,Enabled" bitfld.long 0x04 5.--7. " TVREFIO ,Number of CTL_CLK required to meet > 200ns VREF settling timing requirements during host IO VREF training" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3.--4. " EOFF ,Eye LCDL offset value for VREF training" "0,1,2,3" bitfld.long 0x04 2. " ENUM ,Number of LCDL eye points for which VREF training is repeated" "0,1" newline bitfld.long 0x04 1. " HVEN ,HOST IO internal VREF training enable" "Disabled,Enabled" bitfld.long 0x04 0. " HVIO ,Host IO type control" "0,1" newline group.long 0x540++0x47 line.long 0x00 "ACBDLR0,AC Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " CK3BD ,CK3 bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " CK2BD ,CK2 bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CK1BD ,CK1 bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CK0BD ,CK0 bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "ACBDLR1,AC Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " PARBD ,Delay select for the BDL on parity" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " A16BD ,Delay select for the BDL on address A[16]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " A17BD ,Delay select for the BDL on address A[17]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " ACTBD ,Delay select for the BDL on ACTN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "ACBDLR2,AC Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " BG1BD ,Delay select for the BDL on BG[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " BG0BD ,Delay select for the BDL on BG[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " BA1BD ,Delay select for the BDL on BA[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " BA0BD ,Delay select for the BDL on BA[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "ACBDLR3,AC Bit Delay Line Register 3" bitfld.long 0x0C 24.--29. " CS3BD ,Delay select for the BDL on CS[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 16.--21. " CS2BD ,Delay select for the BDL on CS[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 8.--13. " CS1BD ,Delay select for the BDL on CS[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--5. " CS0BD ,Delay select for the BDL on CS[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "ACBDLR4,AC Bit Delay Line Register 4" bitfld.long 0x10 24.--29. " ODT3BD ,Delay select for the BDL on ODT[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 16.--21. " ODT2BD ,Delay select for the BDL on ODT[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 8.--13. " ODT1BD ,Delay select for the BDL on ODT[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 0.--5. " ODT0BD ,Delay select for the BDL on ODT[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x14 "ACBDLR5,AC Bit Delay Line Register 5" bitfld.long 0x14 24.--29. " CKE3BD ,Delay select for the BDL on CKE[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 16.--21. " CKE2BD ,Delay select for the BDL on CKE[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 8.--13. " CKE1BD ,Delay select for the BDL on CKE[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 0.--5. " CKE0BD ,Delay select for the BDL on CKE[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x18 "ACBDLR6,AC Bit Delay Line Register 6" bitfld.long 0x18 24.--29. " A03BD ,Delay select for the BDL on address A[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " A02BD ,Delay select for the BDL on address A[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " A01BD ,Delay select for the BDL on address A[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " A00BD ,Delay select for the BDL on address A[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "ACBDLR7,AC Bit Delay Line Register 7" bitfld.long 0x1C 24.--29. " A07BD ,Delay select for the BDL on address A[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1C 16.--21. " A06BD ,Delay select for the BDL on address A[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1C 8.--13. " A05BD ,Delay select for the BDL on address A[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1C 0.--5. " A04BD ,Delay select for the BDL on address A[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x20 "ACBDLR8,AC Bit Delay Line Register 8" bitfld.long 0x20 24.--29. " A11BD ,Delay select for the BDL on address A[11]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x20 16.--21. " A10BD ,Delay select for the BDL on address A[10]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x20 8.--13. " A09BD ,Delay select for the BDL on address A[9]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x20 0.--5. " A08BD ,Delay select for the BDL on address A[8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x24 "ACBDLR9,AC Bit Delay Line Register 9" bitfld.long 0x24 24.--29. " A15BD ,Delay select for the BDL on address A[15]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x24 16.--21. " A14BD ,Delay select for the BDL on address A[14]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x24 8.--13. " A13BD ,Delay select for the BDL on address A[13]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x24 0.--5. " A12BD ,Delay select for the BDL on address A[12]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x28 "ACBDLR10,AC Bit Delay Line Register 10" bitfld.long 0x28 24.--29. " CID2BD ,Delay select for the BDL on chip ID CID[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x28 16.--21. " CID1BD ,Delay select for the BDL on chip ID CID[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x28 8.--13. " CID0BD ,Delay select for the BDL on chip ID CID[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x2C "ACBDLR11,AC Bit Delay Line Register 11" bitfld.long 0x2C 24.--29. " CS7BD ,Delay select for the BDL on CS[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2C 16.--21. " CS6BD ,Delay select for the BDL on CS[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2C 8.--13. " CS5BD ,Delay select for the BDL on CS[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2C 0.--5. " CS4BD ,Delay select for the BDL on CS[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x30 "ACBDLR12,AC Bit Delay Line Register 12" bitfld.long 0x30 24.--29. " CS11BD ,Delay select for the BDL on CS[11]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x30 16.--21. " CS10BD ,Delay select for the BDL on CS[10]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x30 8.--13. " CS9BD ,Delay select for the BDL on CS[9]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x30 0.--5. " CS8BD ,Delay select for the BDL on CS[8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x34 "ACBDLR13,AC Bit Delay Line Register 13" bitfld.long 0x34 24.--29. " ODT7BD ,Delay select for the BDL on ODT[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x34 16.--21. " ODT6BD ,Delay select for the BDL on ODT[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x34 8.--13. " ODT5BD ,Delay select for the BDL on ODT[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x34 0.--5. " ODT4BD ,Delay select for the BDL on ODT[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x38 "ACBDLR14,AC Bit Delay Line Register 14" bitfld.long 0x38 24.--29. " CKE7BD ,Delay select for the BDL on CKE[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x38 16.--21. " CKE6BD ,Delay select for the BDL on CKE[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x38 8.--13. " CKE5BD ,Delay select for the BDL on CKE[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x38 0.--5. " CKE4BD ,Delay select for the BDL on CKE[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x3C "ACBDLR15,AC Bit Delay Line Register 15" bitfld.long 0x3C 16.--21. " OEBD ,Delay select for the BDL on OE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3C 8.--13. " TEBD ,Delay select for the BDL on TE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3C 0.--5. " PDRBD ,Delay select for the BDL on PDR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x40 "ACBDLR16,AC Bit Delay Line Register 16" bitfld.long 0x40 24.--29. " CKN3BD ,Delay select for the BDL on CKN[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x40 16.--21. " CKN2BD ,Delay select for the BDL on CKN[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x40 8.--13. " CKN1BD ,Delay select for the BDL on CKN[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x40 0.--5. " CKN0BD ,Delay select for the BDL on CKN[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x44 "ACLCDLR,AC Local Calibrated Delay Line Register" hexmask.long.word 0x44 16.--24. 1. " ACD1 ,Address/command delay for AC macro 1" hexmask.long.word 0x44 0.--8. 1. " ACD ,Address/command delay for AC macro 0" group.long 0x5A0++0x07 line.long 0x00 "ACMDLR0,AC Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "ACMDLR1,AC Master Delay Line Register 1" hexmask.long.word 0x04 16.--24. 1. " MDLD1 ,MDL delay for AC macro 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay for AC macro 0" newline group.long 0x680++0x03 line.long 0x00 "ZQCR,ZQ Impedance Control Register" bitfld.long 0x00 25. " ZQREFISELRANGE ,ZQ VREF range" "0,1" bitfld.long 0x00 19.--24. " PGWAIT_FRQB ,Programmable wait for frequency B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 13.--18. " PGWAIT_FRQA ,Programmable wait for frequency A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12. " ZQREFPEN ,ZQ VREF pad enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ZQREFIEN ,ZQ internal VREF enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " ODT_MODE ,Choice of termination mode" "0,1,2,3" bitfld.long 0x00 8. " FORCE_ZCAL_VT_UPDATE ,Force ZCAL VT update" "0,1" bitfld.long 0x00 5.--7. " IODLMT ,IO VT drift limit" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4. " AVGEN ,Averaging algorithm enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " AVGMAX ,Maximum number of averaging rounds to be used by averaging algorithm" "0,1,2,3" bitfld.long 0x00 1. " ZCALT ,ZQ calibration type" "0,1" bitfld.long 0x00 0. " ZQPD ,ZQ power down" "No,Yes" group.long 0x684++0x07 line.long 0x00 "ZQ0PR0,ZQ 0 Impedance Control Program Register 0" bitfld.long 0x00 31. " PD_DRV_ZDEN ,Pull-down drive strength ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 30. " PU_DRV_ZDEN ,Pull-up drive strength ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 29. " PD_ODT_ZDEN ,Pull-down termination ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 28. " PU_ODT_ZDEN ,Pull-up termination ZCTRL override enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " ZSEGBYP ,Calibration segment bypass" "Not bypassed,Bypassed" bitfld.long 0x00 25.--26. " ZLE_MODE ,VREF latch mode" "0,1,2,3" bitfld.long 0x00 22.--24. " ODT_ADJUST ,Termination adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19.--21. " PD_DRV_ADJUST ,Pull-down drive strength adjustment" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. " PU_DRV_ADJUST ,Pull-up drive strength adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--15. " ZPROG_DRAM_ODT ,DRAM impedance divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " ZPROG_HOST_ODT ,HOST impedance divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " ZPROG_ASYM_DRV_PD ,Impedance divide ratio pull-down drive calibration during asymmetric drive strength calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " ZPROG_ASYM_DRV_PU ,Impedance divide ratio (pull-up drive calibration during asymmetric drive strength calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ZQ0PR1,ZQ 0 Impedance Control Program Register 1" hexmask.long.byte 0x04 8.--14. 1. " PU_REFSEL ,Pull-up REFSEL for PZCTRL cell" hexmask.long.byte 0x04 0.--6. 1. " PD_REFSEL ,Pull-down REFSEL for PZCTRL cell" rgroup.long (0x684+0x08)++0x07 line.long 0x00 "ZQ0DR0,ZQ 0 Impedance Control Data Register 0" hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_RESULT ,Pull-up drive strength calibration code result" hexmask.long.word 0x00 0.--9. 1. " ZDATA_PD_DRV_RESULT ,Pull-down drive strength calibration code result" line.long 0x04 "ZQ0DR1,ZQ 0 Impedance Control Data Register 1" hexmask.long.word 0x04 16.--25. 1. " ZDATA_PU_ODT_RESULT ,Pull-up termination calibration code result" hexmask.long.word 0x04 0.--9. 1. " ZDATA_PD_ODT_RESULT ,Pull-down termination calibration code result" group.long (0x684+0x10)++0x07 line.long 0x00 "ZQ0OR0,ZQ 0 Impedance Control Override Data Register 0" hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_OVRD ,Override value for the pull-up output impedance" hexmask.long.word 0x00 0.--9. 1. " ZDATA_PD_DRV_OVRD ,Override value for the pull-down output impedance" line.long 0x04 "ZQ0OR1,ZQ 0 Impedance Control Override Data Register 1" hexmask.long.word 0x04 16.--25. 1. " ZDATA_PU_ODT_OVRD ,Override value for the pull-up termination" hexmask.long.word 0x04 0.--9. 1. " ZDATA_PD_ODT_OVRD ,Override value for the pull-down termination" rgroup.long (0x684+0x18)++0x03 line.long 0x00 "ZQ0SR,ZQ 0 Impedance Control Status Register" bitfld.long 0x00 13. " PD_ODT_SAT ,Pull-down drive strength code saturated due to termination strength adjustment setting in ZQ0PR" "Not saturated,Saturated" bitfld.long 0x00 12. " PU_ODT_SAT ,Pull-up drive strength code saturated due to termination strength adjustment setting in ZQ0PR" "Not saturated,Saturated" bitfld.long 0x00 11. " PD_DRV_SAT ,Pull-down drive strength code saturated due to drive strength adjustment setting in ZQ0PR" "Not saturated,Saturated" bitfld.long 0x00 10. " PU_DRV_SAT ,Pull-up drive strength code saturated due to drive strength adjustment setting in ZQ0PR" "Not saturated,Saturated" newline bitfld.long 0x00 9. " ZDONE ,Impedance calibration done" "Not done,Done" bitfld.long 0x00 8. " ZERR ,Impedance calibration error" "No error,Error" bitfld.long 0x00 6.--7. " OPU ,On-die termination ODT pull-up calibration status" "0,1,2,3" bitfld.long 0x00 4.--5. " OPD ,On-die termination ODT pull-down calibration status" "0,1,2,3" newline bitfld.long 0x00 2.--3. " ZPU ,Output impedance pull-up calibration status" "0,1,2,3" bitfld.long 0x00 0.--1. " ZPD ,Output impedance pull-down calibration status" "0,1,2,3" group.long 0x6A4++0x07 line.long 0x00 "ZQ1PR0,ZQ 1 Impedance Control Program Register 0" bitfld.long 0x00 31. " PD_DRV_ZDEN ,Pull-down drive strength ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 30. " PU_DRV_ZDEN ,Pull-up drive strength ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 29. " PD_ODT_ZDEN ,Pull-down termination ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 28. " PU_ODT_ZDEN ,Pull-up termination ZCTRL override enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " ZSEGBYP ,Calibration segment bypass" "Not bypassed,Bypassed" bitfld.long 0x00 25.--26. " ZLE_MODE ,VREF latch mode" "0,1,2,3" bitfld.long 0x00 22.--24. " ODT_ADJUST ,Termination adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19.--21. " PD_DRV_ADJUST ,Pull-down drive strength adjustment" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. " PU_DRV_ADJUST ,Pull-up drive strength adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--15. " ZPROG_DRAM_ODT ,DRAM impedance divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " ZPROG_HOST_ODT ,HOST impedance divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " ZPROG_ASYM_DRV_PD ,Impedance divide ratio pull-down drive calibration during asymmetric drive strength calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " ZPROG_ASYM_DRV_PU ,Impedance divide ratio (pull-up drive calibration during asymmetric drive strength calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ZQ1PR1,ZQ 1 Impedance Control Program Register 1" hexmask.long.byte 0x04 8.--14. 1. " PU_REFSEL ,Pull-up REFSEL for PZCTRL cell" hexmask.long.byte 0x04 0.--6. 1. " PD_REFSEL ,Pull-down REFSEL for PZCTRL cell" rgroup.long (0x6A4+0x08)++0x07 line.long 0x00 "ZQ1DR0,ZQ 1 Impedance Control Data Register 0" hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_RESULT ,Pull-up drive strength calibration code result" hexmask.long.word 0x00 0.--9. 1. " ZDATA_PD_DRV_RESULT ,Pull-down drive strength calibration code result" line.long 0x04 "ZQ1DR1,ZQ 1 Impedance Control Data Register 1" hexmask.long.word 0x04 16.--25. 1. " ZDATA_PU_ODT_RESULT ,Pull-up termination calibration code result" hexmask.long.word 0x04 0.--9. 1. " ZDATA_PD_ODT_RESULT ,Pull-down termination calibration code result" group.long (0x6A4+0x10)++0x07 line.long 0x00 "ZQ1OR0,ZQ 1 Impedance Control Override Data Register 0" hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_OVRD ,Override value for the pull-up output impedance" hexmask.long.word 0x00 0.--9. 1. " ZDATA_PD_DRV_OVRD ,Override value for the pull-down output impedance" line.long 0x04 "ZQ1OR1,ZQ 1 Impedance Control Override Data Register 1" hexmask.long.word 0x04 16.--25. 1. " ZDATA_PU_ODT_OVRD ,Override value for the pull-up termination" hexmask.long.word 0x04 0.--9. 1. " ZDATA_PD_ODT_OVRD ,Override value for the pull-down termination" rgroup.long (0x6A4+0x18)++0x03 line.long 0x00 "ZQ1SR,ZQ 1 Impedance Control Status Register" bitfld.long 0x00 13. " PD_ODT_SAT ,Pull-down drive strength code saturated due to termination strength adjustment setting in ZQ1PR" "Not saturated,Saturated" bitfld.long 0x00 12. " PU_ODT_SAT ,Pull-up drive strength code saturated due to termination strength adjustment setting in ZQ1PR" "Not saturated,Saturated" bitfld.long 0x00 11. " PD_DRV_SAT ,Pull-down drive strength code saturated due to drive strength adjustment setting in ZQ1PR" "Not saturated,Saturated" bitfld.long 0x00 10. " PU_DRV_SAT ,Pull-up drive strength code saturated due to drive strength adjustment setting in ZQ1PR" "Not saturated,Saturated" newline bitfld.long 0x00 9. " ZDONE ,Impedance calibration done" "Not done,Done" bitfld.long 0x00 8. " ZERR ,Impedance calibration error" "No error,Error" bitfld.long 0x00 6.--7. " OPU ,On-die termination ODT pull-up calibration status" "0,1,2,3" bitfld.long 0x00 4.--5. " OPD ,On-die termination ODT pull-down calibration status" "0,1,2,3" newline bitfld.long 0x00 2.--3. " ZPU ,Output impedance pull-up calibration status" "0,1,2,3" bitfld.long 0x00 0.--1. " ZPD ,Output impedance pull-down calibration status" "0,1,2,3" group.long 0x6C4++0x07 line.long 0x00 "ZQ2PR0,ZQ 2 Impedance Control Program Register 0" bitfld.long 0x00 31. " PD_DRV_ZDEN ,Pull-down drive strength ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 30. " PU_DRV_ZDEN ,Pull-up drive strength ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 29. " PD_ODT_ZDEN ,Pull-down termination ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 28. " PU_ODT_ZDEN ,Pull-up termination ZCTRL override enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " ZSEGBYP ,Calibration segment bypass" "Not bypassed,Bypassed" bitfld.long 0x00 25.--26. " ZLE_MODE ,VREF latch mode" "0,1,2,3" bitfld.long 0x00 22.--24. " ODT_ADJUST ,Termination adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19.--21. " PD_DRV_ADJUST ,Pull-down drive strength adjustment" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. " PU_DRV_ADJUST ,Pull-up drive strength adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--15. " ZPROG_DRAM_ODT ,DRAM impedance divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " ZPROG_HOST_ODT ,HOST impedance divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " ZPROG_ASYM_DRV_PD ,Impedance divide ratio pull-down drive calibration during asymmetric drive strength calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " ZPROG_ASYM_DRV_PU ,Impedance divide ratio (pull-up drive calibration during asymmetric drive strength calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ZQ2PR1,ZQ 2 Impedance Control Program Register 1" hexmask.long.byte 0x04 8.--14. 1. " PU_REFSEL ,Pull-up REFSEL for PZCTRL cell" hexmask.long.byte 0x04 0.--6. 1. " PD_REFSEL ,Pull-down REFSEL for PZCTRL cell" rgroup.long (0x6C4+0x08)++0x07 line.long 0x00 "ZQ2DR0,ZQ 2 Impedance Control Data Register 0" hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_RESULT ,Pull-up drive strength calibration code result" hexmask.long.word 0x00 0.--9. 1. " ZDATA_PD_DRV_RESULT ,Pull-down drive strength calibration code result" line.long 0x04 "ZQ2DR1,ZQ 2 Impedance Control Data Register 1" hexmask.long.word 0x04 16.--25. 1. " ZDATA_PU_ODT_RESULT ,Pull-up termination calibration code result" hexmask.long.word 0x04 0.--9. 1. " ZDATA_PD_ODT_RESULT ,Pull-down termination calibration code result" group.long (0x6C4+0x10)++0x07 line.long 0x00 "ZQ2OR0,ZQ 2 Impedance Control Override Data Register 0" hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_OVRD ,Override value for the pull-up output impedance" hexmask.long.word 0x00 0.--9. 1. " ZDATA_PD_DRV_OVRD ,Override value for the pull-down output impedance" line.long 0x04 "ZQ2OR1,ZQ 2 Impedance Control Override Data Register 1" hexmask.long.word 0x04 16.--25. 1. " ZDATA_PU_ODT_OVRD ,Override value for the pull-up termination" hexmask.long.word 0x04 0.--9. 1. " ZDATA_PD_ODT_OVRD ,Override value for the pull-down termination" rgroup.long (0x6C4+0x18)++0x03 line.long 0x00 "ZQ2SR,ZQ 2 Impedance Control Status Register" bitfld.long 0x00 13. " PD_ODT_SAT ,Pull-down drive strength code saturated due to termination strength adjustment setting in ZQ2PR" "Not saturated,Saturated" bitfld.long 0x00 12. " PU_ODT_SAT ,Pull-up drive strength code saturated due to termination strength adjustment setting in ZQ2PR" "Not saturated,Saturated" bitfld.long 0x00 11. " PD_DRV_SAT ,Pull-down drive strength code saturated due to drive strength adjustment setting in ZQ2PR" "Not saturated,Saturated" bitfld.long 0x00 10. " PU_DRV_SAT ,Pull-up drive strength code saturated due to drive strength adjustment setting in ZQ2PR" "Not saturated,Saturated" newline bitfld.long 0x00 9. " ZDONE ,Impedance calibration done" "Not done,Done" bitfld.long 0x00 8. " ZERR ,Impedance calibration error" "No error,Error" bitfld.long 0x00 6.--7. " OPU ,On-die termination ODT pull-up calibration status" "0,1,2,3" bitfld.long 0x00 4.--5. " OPD ,On-die termination ODT pull-down calibration status" "0,1,2,3" newline bitfld.long 0x00 2.--3. " ZPU ,Output impedance pull-up calibration status" "0,1,2,3" bitfld.long 0x00 0.--1. " ZPD ,Output impedance pull-down calibration status" "0,1,2,3" rgroup.long 0x6E4++0x07 line.long 0x00 "ZQ3PR0,ZQ 3 Impedance Control Program Register 0" bitfld.long 0x00 31. " PD_DRV_ZDEN ,Pull-down drive strength ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 30. " PU_DRV_ZDEN ,Pull-up drive strength ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 29. " PD_ODT_ZDEN ,Pull-down termination ZCTRL override enable" "Disabled,Enabled" bitfld.long 0x00 28. " PU_ODT_ZDEN ,Pull-up termination ZCTRL override enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " ZSEGBYP ,Calibration segment bypass" "Not bypassed,Bypassed" bitfld.long 0x00 25.--26. " ZLE_MODE ,VREF latch mode" "0,1,2,3" bitfld.long 0x00 22.--24. " ODT_ADJUST ,Termination adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19.--21. " PD_DRV_ADJUST ,Pull-down drive strength adjustment" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. " PU_DRV_ADJUST ,Pull-up drive strength adjustment" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--15. " ZPROG_DRAM_ODT ,DRAM impedance divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " ZPROG_HOST_ODT ,HOST impedance divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " ZPROG_ASYM_DRV_PD ,Impedance divide ratio pull-down drive calibration during asymmetric drive strength calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " ZPROG_ASYM_DRV_PU ,Impedance divide ratio (pull-up drive calibration during asymmetric drive strength calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "ZQ3PR1,ZQ 3 Impedance Control Program Register 1" hexmask.long.byte 0x04 8.--14. 1. " PU_REFSEL ,Pull-up REFSEL for PZCTRL cell" hexmask.long.byte 0x04 0.--6. 1. " PD_REFSEL ,Pull-down REFSEL for PZCTRL cell" rgroup.long (0x6E4+0x08)++0x07 line.long 0x00 "ZQ3DR0,ZQ 3 Impedance Control Data Register 0" hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_RESULT ,Pull-up drive strength calibration code result" hexmask.long.word 0x00 0.--9. 1. " ZDATA_PD_DRV_RESULT ,Pull-down drive strength calibration code result" line.long 0x04 "ZQ3DR1,ZQ 3 Impedance Control Data Register 1" hexmask.long.word 0x04 16.--25. 1. " ZDATA_PU_ODT_RESULT ,Pull-up termination calibration code result" hexmask.long.word 0x04 0.--9. 1. " ZDATA_PD_ODT_RESULT ,Pull-down termination calibration code result" rgroup.long (0x6E4+0x10)++0x07 line.long 0x00 "ZQ3OR0,ZQ 3 Impedance Control Override Data Register 0" hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_OVRD ,Override value for the pull-up output impedance" hexmask.long.word 0x00 0.--9. 1. " ZDATA_PD_DRV_OVRD ,Override value for the pull-down output impedance" line.long 0x04 "ZQ3OR1,ZQ 3 Impedance Control Override Data Register 1" hexmask.long.word 0x04 16.--25. 1. " ZDATA_PU_ODT_OVRD ,Override value for the pull-up termination" hexmask.long.word 0x04 0.--9. 1. " ZDATA_PD_ODT_OVRD ,Override value for the pull-down termination" rgroup.long (0x6E4+0x18)++0x03 line.long 0x00 "ZQ3SR,ZQ 3 Impedance Control Status Register" bitfld.long 0x00 13. " PD_ODT_SAT ,Pull-down drive strength code saturated due to termination strength adjustment setting in ZQ3PR" "Not saturated,Saturated" bitfld.long 0x00 12. " PU_ODT_SAT ,Pull-up drive strength code saturated due to termination strength adjustment setting in ZQ3PR" "Not saturated,Saturated" bitfld.long 0x00 11. " PD_DRV_SAT ,Pull-down drive strength code saturated due to drive strength adjustment setting in ZQ3PR" "Not saturated,Saturated" bitfld.long 0x00 10. " PU_DRV_SAT ,Pull-up drive strength code saturated due to drive strength adjustment setting in ZQ3PR" "Not saturated,Saturated" newline bitfld.long 0x00 9. " ZDONE ,Impedance calibration done" "Not done,Done" bitfld.long 0x00 8. " ZERR ,Impedance calibration error" "No error,Error" bitfld.long 0x00 6.--7. " OPU ,On-die termination ODT pull-up calibration status" "0,1,2,3" bitfld.long 0x00 4.--5. " OPD ,On-die termination ODT pull-down calibration status" "0,1,2,3" newline bitfld.long 0x00 2.--3. " ZPU ,Output impedance pull-up calibration status" "0,1,2,3" bitfld.long 0x00 0.--1. " ZPD ,Output impedance pull-down calibration status" "0,1,2,3" newline group.long 0x700++0x1F line.long 0x00 "DX0GCR0,DATX8 0 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX0GCR1,DATX8 0 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX0GCR2,DATX8 0 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX0GCR3,DATX8 0 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX0GCR4,DATX8 0 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX0GCR5,DATX8 0 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX0GCR6,DATX8 0 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX0GCR7,DATX8 0 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" group.long (0x700+0x28)++0x07 line.long 0x00 "DX0DQMAP0,DATX8 0 DQ/DM Mapping Register 0" rbitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW0DQMAP1,DATX8 0 DQ/DM Mapping Register 1" rbitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x700+0x40)++0x0B line.long 0x00 "DX0BDLR0,DATX8 0 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX0BDLR1,DATX8 0 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX0BDLR2,DATX8 0 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x700+0x50)++0x0B line.long 0x00 "DX0BDLR3,DATX8 0 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX0BDLR4,DATX8 0 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX0BDLR5,DATX8 0 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x700+0x60)++0x03 line.long 0x00 "DX0BDLR6,DATX8 0 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x700+0x80)++0x17 line.long 0x00 "DX0LCDLR0,DATX8 0 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX0LCDLR1,DATX8 0 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX0LCDLR2,DATX8 0 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX0LCDLR3,DATX8 0 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX0LCDLR4,DATX8 0 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX0LCDLR5,DATX8 0 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" group.long (0x700+0xA0)++0x07 line.long 0x00 "DX0MDLR0,DATX8 0 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX0MDLR1,DATX8 0 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" group.long (0x700+0xC0)++0x03 line.long 0x00 "DX0GTR0,DATX8 0 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0x700+0xD0)++0x1F line.long 0x00 "DX0RSR0,DATX8 0 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX0RSR1,DATX8 0 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX0RSR2,DATX8 0 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX0RSR3,DATX8 0 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX0GSR0,DATX8 0 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX0GSR1,DATX8 0 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX0GSR2,DATX8 0 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX0GSR3,DATX8 0 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" group.long 0x800++0x1F line.long 0x00 "DX1GCR0,DATX8 1 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX1GCR1,DATX8 1 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX1GCR2,DATX8 1 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX1GCR3,DATX8 1 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX1GCR4,DATX8 1 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX1GCR5,DATX8 1 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX1GCR6,DATX8 1 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX1GCR7,DATX8 1 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" group.long (0x800+0x28)++0x07 line.long 0x00 "DX1DQMAP0,DATX8 1 DQ/DM Mapping Register 0" rbitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW1DQMAP1,DATX8 1 DQ/DM Mapping Register 1" rbitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x800+0x40)++0x0B line.long 0x00 "DX1BDLR0,DATX8 1 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX1BDLR1,DATX8 1 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX1BDLR2,DATX8 1 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x800+0x50)++0x0B line.long 0x00 "DX1BDLR3,DATX8 1 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX1BDLR4,DATX8 1 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX1BDLR5,DATX8 1 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x800+0x60)++0x03 line.long 0x00 "DX1BDLR6,DATX8 1 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x800+0x80)++0x17 line.long 0x00 "DX1LCDLR0,DATX8 1 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX1LCDLR1,DATX8 1 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX1LCDLR2,DATX8 1 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX1LCDLR3,DATX8 1 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX1LCDLR4,DATX8 1 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX1LCDLR5,DATX8 1 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" group.long (0x800+0xA0)++0x07 line.long 0x00 "DX1MDLR0,DATX8 1 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX1MDLR1,DATX8 1 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" group.long (0x800+0xC0)++0x03 line.long 0x00 "DX1GTR0,DATX8 1 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0x800+0xD0)++0x1F line.long 0x00 "DX1RSR0,DATX8 1 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX1RSR1,DATX8 1 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX1RSR2,DATX8 1 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX1RSR3,DATX8 1 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX1GSR0,DATX8 1 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX1GSR1,DATX8 1 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX1GSR2,DATX8 1 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX1GSR3,DATX8 1 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" group.long 0x900++0x1F line.long 0x00 "DX2GCR0,DATX8 2 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX2GCR1,DATX8 2 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX2GCR2,DATX8 2 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX2GCR3,DATX8 2 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX2GCR4,DATX8 2 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX2GCR5,DATX8 2 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX2GCR6,DATX8 2 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX2GCR7,DATX8 2 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" group.long (0x900+0x28)++0x07 line.long 0x00 "DX2DQMAP0,DATX8 2 DQ/DM Mapping Register 0" rbitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW2DQMAP1,DATX8 2 DQ/DM Mapping Register 1" rbitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x900+0x40)++0x0B line.long 0x00 "DX2BDLR0,DATX8 2 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX2BDLR1,DATX8 2 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX2BDLR2,DATX8 2 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x900+0x50)++0x0B line.long 0x00 "DX2BDLR3,DATX8 2 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX2BDLR4,DATX8 2 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX2BDLR5,DATX8 2 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x900+0x60)++0x03 line.long 0x00 "DX2BDLR6,DATX8 2 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x900+0x80)++0x17 line.long 0x00 "DX2LCDLR0,DATX8 2 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX2LCDLR1,DATX8 2 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX2LCDLR2,DATX8 2 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX2LCDLR3,DATX8 2 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX2LCDLR4,DATX8 2 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX2LCDLR5,DATX8 2 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" group.long (0x900+0xA0)++0x07 line.long 0x00 "DX2MDLR0,DATX8 2 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX2MDLR1,DATX8 2 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" group.long (0x900+0xC0)++0x03 line.long 0x00 "DX2GTR0,DATX8 2 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0x900+0xD0)++0x1F line.long 0x00 "DX2RSR0,DATX8 2 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX2RSR1,DATX8 2 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX2RSR2,DATX8 2 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX2RSR3,DATX8 2 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX2GSR0,DATX8 2 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX2GSR1,DATX8 2 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX2GSR2,DATX8 2 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX2GSR3,DATX8 2 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" group.long 0xA00++0x1F line.long 0x00 "DX3GCR0,DATX8 3 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX3GCR1,DATX8 3 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX3GCR2,DATX8 3 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX3GCR3,DATX8 3 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX3GCR4,DATX8 3 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX3GCR5,DATX8 3 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX3GCR6,DATX8 3 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX3GCR7,DATX8 3 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" group.long (0xA00+0x28)++0x07 line.long 0x00 "DX3DQMAP0,DATX8 3 DQ/DM Mapping Register 0" rbitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW3DQMAP1,DATX8 3 DQ/DM Mapping Register 1" rbitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0xA00+0x40)++0x0B line.long 0x00 "DX3BDLR0,DATX8 3 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX3BDLR1,DATX8 3 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX3BDLR2,DATX8 3 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0xA00+0x50)++0x0B line.long 0x00 "DX3BDLR3,DATX8 3 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX3BDLR4,DATX8 3 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX3BDLR5,DATX8 3 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0xA00+0x60)++0x03 line.long 0x00 "DX3BDLR6,DATX8 3 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0xA00+0x80)++0x17 line.long 0x00 "DX3LCDLR0,DATX8 3 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX3LCDLR1,DATX8 3 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX3LCDLR2,DATX8 3 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX3LCDLR3,DATX8 3 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX3LCDLR4,DATX8 3 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX3LCDLR5,DATX8 3 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" group.long (0xA00+0xA0)++0x07 line.long 0x00 "DX3MDLR0,DATX8 3 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX3MDLR1,DATX8 3 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" group.long (0xA00+0xC0)++0x03 line.long 0x00 "DX3GTR0,DATX8 3 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0xA00+0xD0)++0x1F line.long 0x00 "DX3RSR0,DATX8 3 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX3RSR1,DATX8 3 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX3RSR2,DATX8 3 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX3RSR3,DATX8 3 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX3GSR0,DATX8 3 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX3GSR1,DATX8 3 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX3GSR2,DATX8 3 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX3GSR3,DATX8 3 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" rgroup.long 0xB00++0x1F line.long 0x00 "DX4GCR0,DATX8 4 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX4GCR1,DATX8 4 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX4GCR2,DATX8 4 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX4GCR3,DATX8 4 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX4GCR4,DATX8 4 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX4GCR5,DATX8 4 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX4GCR6,DATX8 4 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX4GCR7,DATX8 4 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" rgroup.long (0xB00+0x28)++0x07 line.long 0x00 "DX4DQMAP0,DATX8 4 DQ/DM Mapping Register 0" bitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW4DQMAP1,DATX8 4 DQ/DM Mapping Register 1" bitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0xB00+0x40)++0x0B line.long 0x00 "DX4BDLR0,DATX8 4 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX4BDLR1,DATX8 4 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX4BDLR2,DATX8 4 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xB00+0x50)++0x0B line.long 0x00 "DX4BDLR3,DATX8 4 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX4BDLR4,DATX8 4 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX4BDLR5,DATX8 4 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xB00+0x60)++0x03 line.long 0x00 "DX4BDLR6,DATX8 4 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xB00+0x80)++0x17 line.long 0x00 "DX4LCDLR0,DATX8 4 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX4LCDLR1,DATX8 4 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX4LCDLR2,DATX8 4 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX4LCDLR3,DATX8 4 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX4LCDLR4,DATX8 4 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX4LCDLR5,DATX8 4 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" rgroup.long (0xB00+0xA0)++0x07 line.long 0x00 "DX4MDLR0,DATX8 4 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX4MDLR1,DATX8 4 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" rgroup.long (0xB00+0xC0)++0x03 line.long 0x00 "DX4GTR0,DATX8 4 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0xB00+0xD0)++0x1F line.long 0x00 "DX4RSR0,DATX8 4 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX4RSR1,DATX8 4 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX4RSR2,DATX8 4 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX4RSR3,DATX8 4 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX4GSR0,DATX8 4 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX4GSR1,DATX8 4 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX4GSR2,DATX8 4 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX4GSR3,DATX8 4 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" rgroup.long 0xC00++0x1F line.long 0x00 "DX5GCR0,DATX8 5 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX5GCR1,DATX8 5 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX5GCR2,DATX8 5 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX5GCR3,DATX8 5 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX5GCR4,DATX8 5 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX5GCR5,DATX8 5 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX5GCR6,DATX8 5 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX5GCR7,DATX8 5 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" rgroup.long (0xC00+0x28)++0x07 line.long 0x00 "DX5DQMAP0,DATX8 5 DQ/DM Mapping Register 0" bitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW5DQMAP1,DATX8 5 DQ/DM Mapping Register 1" bitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0xC00+0x40)++0x0B line.long 0x00 "DX5BDLR0,DATX8 5 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX5BDLR1,DATX8 5 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX5BDLR2,DATX8 5 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xC00+0x50)++0x0B line.long 0x00 "DX5BDLR3,DATX8 5 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX5BDLR4,DATX8 5 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX5BDLR5,DATX8 5 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xC00+0x60)++0x03 line.long 0x00 "DX5BDLR6,DATX8 5 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xC00+0x80)++0x17 line.long 0x00 "DX5LCDLR0,DATX8 5 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX5LCDLR1,DATX8 5 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX5LCDLR2,DATX8 5 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX5LCDLR3,DATX8 5 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX5LCDLR4,DATX8 5 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX5LCDLR5,DATX8 5 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" rgroup.long (0xC00+0xA0)++0x07 line.long 0x00 "DX5MDLR0,DATX8 5 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX5MDLR1,DATX8 5 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" rgroup.long (0xC00+0xC0)++0x03 line.long 0x00 "DX5GTR0,DATX8 5 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0xC00+0xD0)++0x1F line.long 0x00 "DX5RSR0,DATX8 5 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX5RSR1,DATX8 5 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX5RSR2,DATX8 5 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX5RSR3,DATX8 5 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX5GSR0,DATX8 5 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX5GSR1,DATX8 5 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX5GSR2,DATX8 5 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX5GSR3,DATX8 5 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" rgroup.long 0xD00++0x1F line.long 0x00 "DX6GCR0,DATX8 6 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX6GCR1,DATX8 6 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX6GCR2,DATX8 6 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX6GCR3,DATX8 6 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX6GCR4,DATX8 6 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX6GCR5,DATX8 6 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX6GCR6,DATX8 6 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX6GCR7,DATX8 6 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" rgroup.long (0xD00+0x28)++0x07 line.long 0x00 "DX6DQMAP0,DATX8 6 DQ/DM Mapping Register 0" bitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW6DQMAP1,DATX8 6 DQ/DM Mapping Register 1" bitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0xD00+0x40)++0x0B line.long 0x00 "DX6BDLR0,DATX8 6 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX6BDLR1,DATX8 6 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX6BDLR2,DATX8 6 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xD00+0x50)++0x0B line.long 0x00 "DX6BDLR3,DATX8 6 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX6BDLR4,DATX8 6 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX6BDLR5,DATX8 6 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xD00+0x60)++0x03 line.long 0x00 "DX6BDLR6,DATX8 6 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xD00+0x80)++0x17 line.long 0x00 "DX6LCDLR0,DATX8 6 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX6LCDLR1,DATX8 6 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX6LCDLR2,DATX8 6 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX6LCDLR3,DATX8 6 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX6LCDLR4,DATX8 6 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX6LCDLR5,DATX8 6 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" rgroup.long (0xD00+0xA0)++0x07 line.long 0x00 "DX6MDLR0,DATX8 6 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX6MDLR1,DATX8 6 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" rgroup.long (0xD00+0xC0)++0x03 line.long 0x00 "DX6GTR0,DATX8 6 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0xD00+0xD0)++0x1F line.long 0x00 "DX6RSR0,DATX8 6 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX6RSR1,DATX8 6 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX6RSR2,DATX8 6 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX6RSR3,DATX8 6 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX6GSR0,DATX8 6 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX6GSR1,DATX8 6 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX6GSR2,DATX8 6 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX6GSR3,DATX8 6 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" rgroup.long 0xE00++0x1F line.long 0x00 "DX7GCR0,DATX8 7 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX7GCR1,DATX8 7 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX7GCR2,DATX8 7 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX7GCR3,DATX8 7 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX7GCR4,DATX8 7 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX7GCR5,DATX8 7 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX7GCR6,DATX8 7 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX7GCR7,DATX8 7 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" rgroup.long (0xE00+0x28)++0x07 line.long 0x00 "DX7DQMAP0,DATX8 7 DQ/DM Mapping Register 0" bitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW7DQMAP1,DATX8 7 DQ/DM Mapping Register 1" bitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0xE00+0x40)++0x0B line.long 0x00 "DX7BDLR0,DATX8 7 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX7BDLR1,DATX8 7 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX7BDLR2,DATX8 7 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xE00+0x50)++0x0B line.long 0x00 "DX7BDLR3,DATX8 7 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX7BDLR4,DATX8 7 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX7BDLR5,DATX8 7 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xE00+0x60)++0x03 line.long 0x00 "DX7BDLR6,DATX8 7 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xE00+0x80)++0x17 line.long 0x00 "DX7LCDLR0,DATX8 7 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX7LCDLR1,DATX8 7 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX7LCDLR2,DATX8 7 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX7LCDLR3,DATX8 7 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX7LCDLR4,DATX8 7 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX7LCDLR5,DATX8 7 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" rgroup.long (0xE00+0xA0)++0x07 line.long 0x00 "DX7MDLR0,DATX8 7 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX7MDLR1,DATX8 7 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" rgroup.long (0xE00+0xC0)++0x03 line.long 0x00 "DX7GTR0,DATX8 7 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0xE00+0xD0)++0x1F line.long 0x00 "DX7RSR0,DATX8 7 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX7RSR1,DATX8 7 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX7RSR2,DATX8 7 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX7RSR3,DATX8 7 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX7GSR0,DATX8 7 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX7GSR1,DATX8 7 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX7GSR2,DATX8 7 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX7GSR3,DATX8 7 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" rgroup.long 0xF00++0x1F line.long 0x00 "DX8GCR0,DATX8 8 General Configuration Register 0" bitfld.long 0x00 31. " CALBYP ,Calibration bypass" "Not bypassed,Bypassed" bitfld.long 0x00 30. " MDLEN ,Master delay line enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " CODTSHFT ,Configurable ODTTE phase shift" "0,1,2,3" bitfld.long 0x00 24.--27. " DQSDCC ,DQS duty cycle correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " RDDLY ,Number of cycles to generate CTL_DX_GET_STATIC_RD input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DQSNSEPDR ,DQSNSE power down receiver" "No,Yes" bitfld.long 0x00 12. " DQSSEPDR ,DQSSE power down receiver" "No,Yes" bitfld.long 0x00 11. " RTTOAL ,RTT on additive latency" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " RTTOH ,RTT output hold" "0,1,2,3" bitfld.long 0x00 7.--8. " CPDRSHFT ,Configurable PDR phase shift" "0,1,2,3" bitfld.long 0x00 6. " DQSRPD ,DQSR power down" "No,Yes" bitfld.long 0x00 5. " DQSGPDR ,DQSG power down receiver" "No,Yes" newline bitfld.long 0x00 3. " DQSGODT ,DQSG on-die termination" "Disabled,Enabled" bitfld.long 0x00 2. " DQSGOE ,DQSG output enable" "Disabled,Enabled" line.long 0x04 "DX8GCR1,DATX8 8 General Configuration Register 1" bitfld.long 0x04 30.--31. " DXPDRMODE[15:14] ,Enable the PDR mode for DQ7" "0,1,2,3" bitfld.long 0x04 28.--29. " [13:12] ,Enable the PDR mode for DQ6" "0,1,2,3" bitfld.long 0x04 26.--27. " [11:10] ,Enable the PDR mode for DQ5" "0,1,2,3" bitfld.long 0x04 24.--25. " [9:8] ,Enable the PDR mode for DQ4" "0,1,2,3" newline bitfld.long 0x04 22.--23. " [7:6] ,Enable the PDR mode for DQ3" "0,1,2,3" bitfld.long 0x04 20.--21. " [5:4] ,Enable the PDR mode for DQ2" "0,1,2,3" bitfld.long 0x04 18.--19. " [3:2] ,Enable the PDR mode for DQ1" "0,1,2,3" bitfld.long 0x04 16.--17. " [1:0] ,Enable the PDR mode for DQ0" "0,1,2,3" newline bitfld.long 0x04 14. " QSNSEL ,Select the delayed or non-delayed read data strobe #" "Disabled,Enabled" bitfld.long 0x04 13. " QSSEL ,Select the delayed or non-delayed read data strobe" "Disabled,Enabled" bitfld.long 0x04 12. " OEEN ,Enables read data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 11. " PDREN ,Enables PDR in a byte lane" "Disabled,Enabled" newline bitfld.long 0x04 10. " TEEN ,Enables ODT/TE in a byte lane" "Disabled,Enabled" bitfld.long 0x04 9. " DSEN ,Enables write data strobe in a byte lane" "Disabled,Enabled" bitfld.long 0x04 8. " DMEN ,Enables DM pin in a byte lane" "Disabled,Enabled" bitfld.long 0x04 7. " DQEN[7] ,DQ7 enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,DQ6 enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,DQ5 enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,DQ4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,DQ3 enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " [2] ,DQ2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,DQ1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,DQ0 enable" "Disabled,Enabled" line.long 0x08 "DX8GCR2,DATX8 8 General Configuration Register 2" bitfld.long 0x08 30.--31. " DXOEMODE[15:14] ,Enable the OE mode for DQ7" "0,1,2,3" bitfld.long 0x08 28.--29. " [13:12] ,Enable the OE mode for DQ6" "0,1,2,3" bitfld.long 0x08 26.--27. " [11:10] ,Enable the OE mode for DQ5" "0,1,2,3" bitfld.long 0x08 24.--25. " [9:8] ,Enable the OE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 22.--23. " [7:6] ,Enable the OE mode for DQ3" "0,1,2,3" bitfld.long 0x08 20.--21. " [5:4] ,Enable the OE mode for DQ2" "0,1,2,3" bitfld.long 0x08 18.--19. " [3:2] ,Enable the OE mode for DQ1" "0,1,2,3" bitfld.long 0x08 16.--17. " [1:0] ,Enable the OE mode for DQ0" "0,1,2,3" newline bitfld.long 0x08 14.--15. " DXTEMODE[15:14] ,Enable the TE mode for DQ7" "0,1,2,3" bitfld.long 0x08 12.--13. " [13:12] ,Enable the TE mode for DQ6" "0,1,2,3" bitfld.long 0x08 10.--11. " [11:10] ,Enable the TE mode for DQ5" "0,1,2,3" bitfld.long 0x08 8.--9. " [9:8] ,Enable the TE mode for DQ4" "0,1,2,3" newline bitfld.long 0x08 6.--7. " [7:6] ,Enable the TE mode for DQ3" "0,1,2,3" bitfld.long 0x08 4.--5. " [5:4] ,Enable the TE mode for DQ2" "0,1,2,3" bitfld.long 0x08 2.--3. " [3:2] ,Enable the TE mode for DQ1" "0,1,2,3" bitfld.long 0x08 0.--1. " [1:0] ,Enable the TE mode for DQ0" "0,1,2,3" line.long 0x0C "DX8GCR3,DATX8 8 General Configuration Register 3" bitfld.long 0x0C 31. " OEBVT ,Output enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 30. " TEBVT ,Termination enable BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 29. " RDBVT ,Read data BDL VT compensation" "Disabled,Enabled" bitfld.long 0x0C 28. " WDBVT ,Write data BDL VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 27. " RGLVT ,Read DQS gating LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 26. " RDLVT ,Read DQS LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 25. " WDLVT ,Write DQ LCDL delay VT compensation" "Disabled,Enabled" bitfld.long 0x0C 24. " WLLVT ,Write leveling LCDL delay VT compensation" "Disabled,Enabled" newline bitfld.long 0x0C 23. " RGSLVT ,Read DQS gating status LCDL delay VT compensation" "0,1" bitfld.long 0x0C 22. " PDRBVT ,Power down receiver BDL VT compensation" "No,Yes" bitfld.long 0x0C 20.--21. " DSNOEMODE ,Enables the OE mode for DQS" "0,1,2,3" bitfld.long 0x0C 18.--19. " DSNTEMODE ,Enables the TE mode for DQS" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " DSNPDRMODE ,Enables the PDR mode for DQS" "0,1,2,3" bitfld.long 0x0C 14.--15. " DMOEMODE ,Enables the OE mode values for DM" "0,1,2,3" bitfld.long 0x0C 12.--13. " DMTEMODE ,Enables the TE mode values for DM" "0,1,2,3" bitfld.long 0x0C 10.--11. " DMPDRMODE ,Enables the PDR mode values for DM" "0,1,2,3" newline bitfld.long 0x0C 8. " WDSBVT ,Write data strobe BDL VT compensation" "0,1" bitfld.long 0x0C 6.--7. " DSOEMODE ,Enables the OE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 4.--5. " DSTEMODE ,Enables the TE mode values for DQS" "0,1,2,3" bitfld.long 0x0C 2.--3. " DSPDRMODE ,Enables the PDR mode values for DQS" "0,1,2,3" newline bitfld.long 0x0C 1. " RDMBVT ,Read data mask BDL VT compensation" "Not masked,Masked" bitfld.long 0x0C 0. " WDMBVT ,Write data mask BDL VT compensation" "Not masked,Masked" line.long 0x10 "DX8GCR4,DATX8 8 General Configuration Register 4" bitfld.long 0x10 28. " DXREFPEN ,Byte lane VREF pad enable" "Disabled,Enabled" bitfld.long 0x10 26.--27. " DXREFEEN ,Byte lane internal VREF enable" "0,1,2,3" bitfld.long 0x10 25. " DXREFSEN ,Byte lane single-end VREF enable" "Disabled,Enabled" bitfld.long 0x10 23. " DXREFESELRANGE ,External VREF generator REFSEL range select" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. " DXREFESEL ,Byte lane external VREF select" bitfld.long 0x10 15. " DXREFSSELRANGE ,Single ended VREF generator REFSEL range select" "0,1" hexmask.long.byte 0x10 8.--14. 1. " DXREFSSEL ,Byte lane single-end VREF select" bitfld.long 0x10 2.--5. " DXREFIEN ,VREF enable control for DQ IO single ended buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--1. " DXREFIMON ,VRMON control for DQ IO single ended buffers of a byte lane" "0,1,2,3" line.long 0x14 "DX8GCR5,DATX8 8 General Configuration Register 5" hexmask.long.byte 0x14 24.--30. 1. " DXREFISELR3 ,Byte lane internal VREF select for rank 3" hexmask.long.byte 0x14 16.--22. 1. " DXREFISELR2 ,Byte lane internal VREF select for rank 2" hexmask.long.byte 0x14 8.--14. 1. " DXREFISELR1 ,Byte lane internal VREF select for rank 1" hexmask.long.byte 0x14 0.--6. 1. " DXREFISELR0 ,Byte lane internal VREF select for rank 0" line.long 0x18 "DX8GCR6,DATX8 8 General Configuration Register 6" bitfld.long 0x18 24.--29. " DXDQVREFR3 ,DRAM DQ VREF select for rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 16.--21. " DXDQVREFR2 ,DRAM DQ VREF select for rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 8.--13. " DXDQVREFR1 ,DRAM DQ VREF select for rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 0.--5. " DXDQVREFR0 ,DRAM DQ VREF select for rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "DX8GCR7,DATX8 8 General Configuration Register 7" bitfld.long 0x1C 9. " DCALTYPE ,DDL calibration type" "0,1" hexmask.long.word 0x1C 0.--8. 1. " DCALSVAL ,DDL calibration starting value" rgroup.long (0xF00+0x28)++0x07 line.long 0x00 "DX8DQMAP0,DATX8 8 DQ/DM Mapping Register 0" bitfld.long 0x00 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x00 16.--19. " DQ4MAP ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DQ3MAP ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DQ2MAP ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " DQ1MAP ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DQ0MAP ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DW8DQMAP1,DATX8 8 DQ/DM Mapping Register 1" bitfld.long 0x04 31. " MAPOK ,Checksum bit" "0,1" bitfld.long 0x04 12.--15. " DMMAP ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " DQ7MAP ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DQ6MAP ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " DQ5MAP ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0xF00+0x40)++0x0B line.long 0x00 "DX8BDLR0,DATX8 8 Bit Delay Line Register 0" bitfld.long 0x00 24.--29. " DQ3WBD ,DQ3 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2WBD ,DQ2 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1WBD ,DQ1 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0WBD ,DQ0 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX8BDLR1,DATX8 8 Bit Delay Line Register 1" bitfld.long 0x04 24.--29. " DQ7WBD ,DQ7 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6WBD ,DQ6 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5WBD ,DQ5 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4WBD ,DQ4 write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX8BDLR2,DATX8 8 Bit Delay Line Register 2" bitfld.long 0x08 24.--29. " DSNWBD ,DQSN write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 16.--21. " DSOEBD ,DQS/DM/DQ output enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 8.--13. " DSWBD ,DQS write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. " DMWBD ,DM write bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xF00+0x50)++0x0B line.long 0x00 "DX8BDLR3,DATX8 8 Bit Delay Line Register 3" bitfld.long 0x00 24.--29. " DQ3RBD ,DQ3 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " DQ2RBD ,DQ2 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " DQ1RBD ,DQ1 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DQ0RBD ,DQ0 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DX8BDLR4,DATX8 8 Bit Delay Line Register 4" bitfld.long 0x04 24.--29. " DQ7RBD ,DQ7 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " DQ6RBD ,DQ6 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " DQ5RBD ,DQ5 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " DQ4RBD ,DQ4 read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "DX8BDLR5,DATX8 8 Bit Delay Line Register 5" bitfld.long 0x08 0.--5. " DMRBD ,DM read bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xF00+0x60)++0x03 line.long 0x00 "DX8BDLR6,DATX8 8 Bit Delay Line Register 6" bitfld.long 0x00 16.--21. " TERBD ,Termination enable bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " PDRBD ,Power down receiver bit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xF00+0x80)++0x17 line.long 0x00 "DX8LCDLR0,DATX8 8 Local Calibrated Delay Line Register 0" hexmask.long.word 0x00 0.--8. 1. " WLD ,Write leveling delay" line.long 0x04 "DX8LCDLR1,DATX8 8 Local Calibrated Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " WDQD ,Write data delay" line.long 0x08 "DX8LCDLR2,DATX8 8 Local Calibrated Delay Line Register 2" hexmask.long.word 0x08 0.--8. 1. " DQSGD ,Read DQS gating delay" line.long 0x0C "DX8LCDLR3,DATX8 8 Local Calibrated Delay Line Register 3" hexmask.long.word 0x0C 0.--8. 1. " RDQSD ,Read DQS delay" line.long 0x10 "DX8LCDLR4,DATX8 8 Local Calibrated Delay Line Register 4" hexmask.long.word 0x10 0.--8. 1. " RDQSND ,Read DQSN delay" line.long 0x14 "DX8LCDLR5,DATX8 8 Local Calibrated Delay Line Register 5" hexmask.long.word 0x14 0.--8. 1. " DQSGSD ,DQS gating status delay" rgroup.long (0xF00+0xA0)++0x07 line.long 0x00 "DX8MDLR0,DATX8 8 Master Delay Line Register 0" hexmask.long.word 0x00 16.--24. 1. " TPRD ,Target period" hexmask.long.word 0x00 0.--8. 1. " IPRD ,Initial period" line.long 0x04 "DX8MDLR1,DATX8 8 Master Delay Line Register 1" hexmask.long.word 0x04 0.--8. 1. " MDLD ,MDL delay" rgroup.long (0xF00+0xC0)++0x03 line.long 0x00 "DX8GTR0,DATX8 8 General Timing Register 0" bitfld.long 0x00 24.--26. " WDQSL ,DQ write path latency pipeline" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " WLSL ,Write leveling system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " DGSL ,DQS gating system latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0xF00+0xD0)++0x1F line.long 0x00 "DX8RSR0,DATX8 8 Rank Status Register 0" hexmask.long.word 0x00 0.--15. 1. " QSGERR ,DQS gate training error" line.long 0x04 "DX8RSR1,DATX8 8 Rank Status Register 1" hexmask.long.word 0x04 0.--15. 1. " RDLVLERR ,Read leveling error" line.long 0x08 "DX8RSR2,DATX8 8 Rank Status Register 2" hexmask.long.word 0x08 0.--15. 1. " WLAWN ,Write latency adjustment warning" line.long 0x0C "DX8RSR3,DATX8 8 Rank Status Register 3" hexmask.long.word 0x0C 0.--15. 1. " WLAERR ,Write leveling adjustment error" line.long 0x10 "DX8GSR0,DATX8 8 General Status Register 0" bitfld.long 0x10 30. " WLDQ ,Write leveling DQ status" "0,1" hexmask.long.word 0x10 17.--25. 1. " GDQSPRD ,Read DQS gating period" bitfld.long 0x10 16. " DPLOCK ,DATX8 PLL lock" "Not locked,Locked" hexmask.long.word 0x10 7.--15. 1. " WLPRD ,Write leveling period" newline bitfld.long 0x10 6. " WLERR ,Write leveling error" "No error,Error" bitfld.long 0x10 5. " WLDONE ,Write leveling done" "Not done,Done" bitfld.long 0x10 4. " WLCAL ,Write leveling calibration" "Not done,Done" bitfld.long 0x10 3. " GDQSCAL ,Read DQS gating calibration" "Not done,Done" newline bitfld.long 0x10 2. " RDQSNCAL ,Read DQS# calibration" "Not done,Done" bitfld.long 0x10 1. " RDQSCAL ,Read DQS calibration" "Not done,Done" bitfld.long 0x10 0. " WDQCAL ,Write DQ calibration" "Not done,Done" line.long 0x14 "DX8GSR1,DATX8 8 General Status Register 1" hexmask.long.tbyte 0x14 1.--24. 1. " DLTCODE ,Delay line test code" bitfld.long 0x14 0. " DLTDONE ,Delay line test done" "Not done,Done" line.long 0x18 "DX8GSR2,DATX8 8 General Status Register 2" hexmask.long.word 0x18 23.--31. 1. " GSDQSPRD ,Read DQS gating status period" bitfld.long 0x18 22. " GSDQSCAL ,Read DQS gating status calibration" "Not done,Done" bitfld.long 0x18 20. " SRDERR ,Static read error" "No error,Error" hexmask.long.byte 0x18 12.--19. 1. " DQS2DQERR ,Write DQS2DQ training error" newline bitfld.long 0x18 8.--11. " ESTAT ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 7. " WEWN ,Write eye centering warning" "Not occurred,Occurred" bitfld.long 0x18 6. " WEERR ,Write eye centering error" "No error,Error" bitfld.long 0x18 5. " REWN ,Read eye centering warning" "Not occurred,Occurred" newline bitfld.long 0x18 4. " REERR ,Read eye centering error" "No error,Error" bitfld.long 0x18 3. " WDWN ,Write bit deskew warning" "Not occurred,Occurred" bitfld.long 0x18 2. " WDERR ,Write bit deskew error" "No error,Error" bitfld.long 0x18 1. " RDWN ,Read bit deskew warning" "Not occurred,Occurred" newline bitfld.long 0x18 0. " RDERR ,Read bit deskew error" "No error,Error" line.long 0x1C "DX8GSR3,DATX8 8 General Status Register 3" bitfld.long 0x1C 24.--26. " ESTAT ,VREF training error status code" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--23. " DVWRN ,DRAM VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " DVERR ,DRAM VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " HVWRN ,Host VREF training warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 8.--11. " HVERR ,Host VREF training error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--1. " SRDPC ,Static read delay pass count" "0,1,2,3" newline group.long 0x1400++0x1F line.long 0x00 "DX8SL0OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode write-data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode write-leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL0PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL0PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL0PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL0PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL0PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL0PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL0DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path rise-to-rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path rise-to-rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x1400+0x24)++0x0F line.long 0x00 "DX8SL0DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL0DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL0DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during postamble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during preamble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL0IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" group.long 0x1440++0x1F line.long 0x00 "DX8SL1OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode write-data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode write-leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL1PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL1PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL1PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL1PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL1PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL1PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL1DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path rise-to-rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path rise-to-rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x1440+0x24)++0x0F line.long 0x00 "DX8SL1DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL1DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL1DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during postamble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during preamble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL1IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" group.long 0x1480++0x1F line.long 0x00 "DX8SL2OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode write-data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode write-leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL2PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL2PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL2PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL2PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL2PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL2PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL2DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path rise-to-rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path rise-to-rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x1480+0x24)++0x0F line.long 0x00 "DX8SL2DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL2DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL2DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during postamble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during preamble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL2IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" rgroup.long 0x14C0++0x1F line.long 0x00 "DX8SL3OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode Write-Data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode Write-Leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL3PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable ATOEN" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL3PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL3PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL3PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL3PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL3PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL3DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0x14C0+0x24)++0x0F line.long 0x00 "DX8SL3DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL3DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL3DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during Post-amble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during Pre-amble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL3IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" rgroup.long 0x1500++0x1F line.long 0x00 "DX8SL4OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode Write-Data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode Write-Leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL4PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable ATOEN" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL4PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL4PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL4PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL4PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL4PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL4DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0x1500+0x24)++0x0F line.long 0x00 "DX8SL4DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL4DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL4DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during Post-amble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during Pre-amble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL4IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" rgroup.long 0x1540++0x1F line.long 0x00 "DX8SL5OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode Write-Data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode Write-Leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL5PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable ATOEN" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL5PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL5PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL5PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL5PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL5PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL5DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0x1540+0x24)++0x0F line.long 0x00 "DX8SL5DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL5DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL5DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during Post-amble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during Pre-amble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL5IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" rgroup.long 0x1580++0x1F line.long 0x00 "DX8SL6OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode Write-Data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode Write-Leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL6PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable ATOEN" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL6PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL6PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL6PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL6PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL6PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL6DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0x1580+0x24)++0x0F line.long 0x00 "DX8SL6DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL6DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL6DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during Post-amble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during Pre-amble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL6IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" rgroup.long 0x15C0++0x1F line.long 0x00 "DX8SL7OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode Write-Data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode Write-Leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL7PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable ATOEN" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL7PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL7PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL7PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL7PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL7PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL7DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0x15C0+0x24)++0x0F line.long 0x00 "DX8SL7DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL7DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL7DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during Post-amble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during Pre-amble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL7IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" rgroup.long 0x1600++0x1F line.long 0x00 "DX8SL8OSC,DATX8 0-1 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode Write-Data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode Write-Leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SL8PLLCR0,DAXT8 0-1 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable ATOEN" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SL8PLLCR1,DAXT8 0-1 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypass,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SL8PLLCR2,DAXT8 0-1 PLL Control Register 2" line.long 0x10 "DX8SL8PLLCR3,DAXT8 0-1 PLL Control Register 3" line.long 0x14 "DX8SL8PLLCR4,DAXT8 0-1 PLL Control Register 4" line.long 0x18 "DX8SL8PLLCR5,DAXT8 0-1 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SL8DQSCTL,DATX8 0-1 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path Rise-to-Rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS_N resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0x1600+0x24)++0x0F line.long 0x00 "DX8SL8DDLCTL,DATX8 0-1 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SL8DXCTL1,DATX8 0-1 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SL8DXCTL2,DATX8 0-1 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during Post-amble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during Pre-amble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "Not bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No,Yes" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SL8IOCR,DATX8 0-1 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" wgroup.long 0x17C0++0x1F line.long 0x00 "DX8SLBOSC,DATX8 0-8 Oscillator Register" bitfld.long 0x00 28.--29. " GATEDXRDCLK ,Enable clock gating for DX DDR_CLK" "0,1,2,3" bitfld.long 0x00 26.--27. " GATEDXDDRCLK ,Enable clock gating for DX CTL_RD_CLK" "0,1,2,3" bitfld.long 0x00 24.--25. " GATEDXCTLCLK ,Enable clock gating for DX CTL_CLK" "0,1,2,3" bitfld.long 0x00 22.--23. " CLKLEVEL ,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3" newline bitfld.long 0x00 21. " LBMODE ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 20. " LBGSDQS ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "Not loaded,Loaded" bitfld.long 0x00 18.--19. " LBGDQS ,Loopback DQS gating" "0,1,2,3" bitfld.long 0x00 17. " LBDQSS ,Loopback DQS shift" "Not shifted,Shifted" newline bitfld.long 0x00 16. " PHYHRST ,PHY high-speed reset" "No reset,Reset" bitfld.long 0x00 15. " PHYFRST ,PHY FIFO reset" "No reset,Reset" bitfld.long 0x00 14. " DLTST ,Delay line test start" "Not started,Started" bitfld.long 0x00 13. " DLTMODE ,Delay line test mode" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " OSCWDDL ,Oscillator mode write-data delay line select" "0,1,2,3" bitfld.long 0x00 5.--6. " OSCWDL ,Oscillator mode write-leveling delay line select" "0,1,2,3" bitfld.long 0x00 1.--4. " OSCDIV ,Oscillator mode division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " OSCEN ,Oscillator enable" "Disabled,Enabled" line.long 0x04 "DX8SLBPLLCR0,DAXT8 0-8 PLL Control Register 0" bitfld.long 0x04 31. " PLLBYP ,PLL bypass" "Not bypassed,Bypassed" bitfld.long 0x04 30. " PLLRST ,PLL reset" "No reset,Reset" bitfld.long 0x04 29. " PLLPD ,PLL power down" "No,Yes" bitfld.long 0x04 28. " RSTOPM ,Reference stop mode" "0,1" newline bitfld.long 0x04 24.--27. " FRQSEL ,PLL frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 23. " RLOCKM ,Relock mode" "Disabled,Enabled" bitfld.long 0x04 17.--22. " CPPC ,Charge pump proportional current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 13.--16. " CPIC ,Charge pump integrating current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12. " GSHIFT ,Gear shift" "0,1" bitfld.long 0x04 8. " ATOEN ,Analog test enable ATOEN" "Disabled,Enabled" bitfld.long 0x04 4.--7. " ATC ,Analog test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DTC ,Digital test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DX8SLBPLLCR1,DAXT8 0-8 PLL Control Register 1" hexmask.long.tbyte 0x08 6.--21. 1. " PLLPROG ,Connects to the PLL PLL_PROG bus" bitfld.long 0x08 5. " BYPVREGCP ,Bypass PLL VREG_CP" "Not bypassed,Bypassed" bitfld.long 0x08 4. " BYPVREGDIG ,Bypass PLL VREG_DIG" "Not bypassed,Bypassed" bitfld.long 0x08 3. " BYPVDD ,PLL VDD voltage level control" "0,1" newline bitfld.long 0x08 2. " LOCKPS ,Lock detector phase select" "0,1" bitfld.long 0x08 1. " LOCKCS ,Lock detector counter select" "0,1" bitfld.long 0x08 0. " LOCKDS ,Lock detector select" "0,1" line.long 0x0C "DX8SLBPLLCR2,DAXT8 0-8 PLL Control Register 2" line.long 0x10 "DX8SLBPLLCR3,DAXT8 0-8 PLL Control Register 3" line.long 0x14 "DX8SLBPLLCR4,DAXT8 0-8 PLL Control Register 4" line.long 0x18 "DX8SLBPLLCR5,DAXT8 0-8 PLL Control Register 5" hexmask.long.byte 0x18 0.--7. 1. " PLLCTRL_103_96 ,Connects to bits [103:96] of the PLL general control bus PLL_CTRL" line.long 0x1C "DX8SLBDQSCTL,DATX8 0-8 DQS Control Register" bitfld.long 0x1C 24. " RRRMODE ,Read path rise-to-rise mode" "0,1" bitfld.long 0x1C 21. " WRRMODE ,Write path rise-to-rise mode" "0,1" bitfld.long 0x1C 19.--20. " DQSGX ,DQS gate extension" "0,1,2,3" bitfld.long 0x1C 18. " LPPLLPD ,Low power PLL power down" "No,Yes" newline bitfld.long 0x1C 17. " LPIOPD ,Low power I/O power down" "No,Yes" bitfld.long 0x1C 14. " QSCNTEN ,QS counter enable" "Disabled,Enabled" bitfld.long 0x1C 13. " UDQIOM ,Unused DQ I/O mode" "0,1" bitfld.long 0x1C 8.--9. " DXSR ,Data slew rate" "0,1,2,3" newline bitfld.long 0x1C 4.--7. " DQSNRES ,DQS# resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " DQSRES ,DQS resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.long 0x17E4++0x0F line.long 0x00 "DX8SLBDDLCTL,DATX8 0-8 DDL Control Register" bitfld.long 0x00 26. " DLYLDTM ,Delay load timing" "0,1" bitfld.long 0x00 25. " DXDDLLDT ,DX DDL load type" "0,1" bitfld.long 0x00 18.--22. " DXDDLLD ,DATX8 DDL delay select dynamic load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 2.--17. 1. " DXDDLBYP ,DATX8 DDL bypass" newline bitfld.long 0x00 0.--1. " DDLBYPMODE ,Controls DDL bypass mode" "0,1,2,3" line.long 0x04 "DX8SLBDXCTL1,DATX8 0-8 DX Control Register 1" bitfld.long 0x04 24. " DXCALCLK ,DATX calibration clock select" "0,1" bitfld.long 0x04 23. " DXRCLKMD ,DATX8 read clock mode" "0,1" bitfld.long 0x04 20.--21. " DXDTOSEL ,DATX8 digital test output select" "0,1,2,3" bitfld.long 0x04 19. " DXGSMD ,Read DQS gating status mode" "0,1" newline bitfld.long 0x04 18. " DXQSDBYP ,Read DQS/DQS_N delay load bypass mode" "0,1" bitfld.long 0x04 17. " DXGDBYP ,Read DQS gate delay load bypass mode" "0,1" bitfld.long 0x04 16. " DXTMODE ,DATX8 test mode" "0,1" line.long 0x08 "DX8SLBDXCTL2,DATX8 0-8 DX Control Register 2" bitfld.long 0x08 23. " CRDEN ,Configurable read data enable" "Disabled,Enabled" bitfld.long 0x08 20.--22. " POSOEX ,OX extension during postamble" "0,1,2,3,4,5,6,7" bitfld.long 0x08 18.--19. " PREOEX ,OE extension during preamble" "0,1,2,3" bitfld.long 0x08 16. " IOAG ,I/O assisted gate select" "0,1" newline bitfld.long 0x08 15. " IOLB ,I/O loopback select" "0,1" bitfld.long 0x08 9.--12. " LPWAKEUP_THRSH ,Low power wakeup threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8. " RDBI ,Read data bus inversion enable" "Disabled,Enabled" bitfld.long 0x08 7. " WDBI ,Write data bus inversion enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " PRFBYP ,PUB read FIFO bypass" "No bypassed,Bypassed" bitfld.long 0x08 4.--5. " RDMODE ,DATX8 receive FIFO read mode" "0,1,2,3" bitfld.long 0x08 3. " DISRST ,Disables the read FIFO reset" "No reset,Reset" bitfld.long 0x08 1.--2. " DQSGLB ,Read DQS gate I/O loopback" "0,1,2,3" line.long 0x0C "DX8SLBIOCR,DATX8 0-8 I/O Configuration Register" bitfld.long 0x0C 28.--30. " DXDACRANGE ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " DXVREFIOM ,IOM bits for PVREF/PVREF_DAC/PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 22.--24. " DXIOM ,DX IO mode" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 11.--21. 1. " DXTXM ,DX IO transmitter mode" newline hexmask.long.word 0x0C 0.--10. 1. " DXRXM ,DX IO receiver mode" width 0x0B tree.end tree.end sif (cpuis("IMX8*-CM4")) tree.open "CM4 (ARM Cortex-M4 Subsystem)" ; tree "LMEM (Local Memory Controller)" ; base ad:0x00 ; %include imx8x/lmem.ph ad:0x00 ; tree.end tree "MCM (Miscellaneous Control Module)" base ad:0xE0080000 width 7. rgroup.word 0x08++0x03 line.word 0x00 "PLASC,Crossbar Switch Slave Configuration" bitfld.word 0x00 7. " ASC[7] ,Bus slave connection to AXBS input port 7" "Absent,Present" bitfld.word 0x00 6. " [6] ,Bus slave connection to AXBS input port 6" "Absent,Present" bitfld.word 0x00 5. " [5] ,Bus slave connection to AXBS input port 5" "Absent,Present" bitfld.word 0x00 4. " [4] ,Bus slave connection to AXBS input port 4" "Absent,Present" newline bitfld.word 0x00 3. " [3] ,Bus slave connection to AXBS input port 3" "Absent,Present" bitfld.word 0x00 2. " [2] ,Bus slave connection to AXBS input port 2" "Absent,Present" bitfld.word 0x00 1. " [1] ,Bus slave connection to AXBS input port 1" "Absent,Present" bitfld.word 0x00 0. " [0] ,Bus slave connection to AXBS input port 0" "Absent,Present" line.word 0x02 "PLAMC,Crossbar Switch Master Configuration" bitfld.word 0x02 7. " AMC[7] ,Bus master connection to AXBS input port 7" "Absent,Present" bitfld.word 0x02 6. " [6] ,Bus master connection to AXBS input port 6" "Absent,Present" bitfld.word 0x02 5. " [5] ,Bus master connection to AXBS input port 5" "Absent,Present" bitfld.word 0x02 4. " [4] ,Bus master connection to AXBS input port 4" "Absent,Present" newline bitfld.word 0x02 3. " [3] ,Bus master connection to AXBS input port 3" "Absent,Present" bitfld.word 0x02 2. " [2] ,Bus master connection to AXBS input port 2" "Absent,Present" bitfld.word 0x02 1. " [1] ,Bus master connection to AXBS input port 1" "Absent,Present" bitfld.word 0x02 0. " [0] ,Bus master connection to AXBS input port 0" "Absent,Present" rgroup.long 0x20++0x0B line.long 0x00 "FADR,Fault Address Register" line.long 0x04 "FATR,Fault Attributes Register" bitfld.long 0x04 31. " BEOVR ,Bus error overrun" "No error,Error" bitfld.long 0x04 8.--11. " BEMN ,Bus error master number" ",1,?..." bitfld.long 0x04 7. " BEWT ,Bus error write" "Read,Write" newline bitfld.long 0x04 4.--5. " BESZ ,Bus error size" "8-bit,16-bit,32-bit,?..." bitfld.long 0x04 1. " BEMD ,Bus error privilege level" "User mode,Supervisor/privileged mode" bitfld.long 0x04 0. " BEDA ,Bus error access type" "Instruction,Data" line.long 0x08 "FDR,Fault Data Register" width 0x0B tree.end tree "LPI2C (Low-Power I2C Controller)" base ad:0x41230000 width 8. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number" line.long 0x04 "PARAM,Parameter Register" bitfld.long 0x04 8.--11. " MRXFIFO ,Master receive FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x04 0.--3. " MTXFIFO ,Master transmit FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" group.long 0x10++0x13 line.long 0x00 "MCR,Master Control Register" bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset" bitfld.long 0x00 3. " DBGEN ,Debug enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " MEN ,Master enable" "Disabled,Enabled" line.long 0x04 "MSR,Master Status Register" rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x04 24. " MBF ,Master busy flag" "Idle,Busy" eventfld.long 0x04 14. " DMF ,Data match flag" "Not received,Received" eventfld.long 0x04 13. " PLTF ,Pin low timeout flag" "Not occurred/disabled,Occurred" newline eventfld.long 0x04 12. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x04 11. " ALF ,Arbitration lost flag" "Not lost,Lost" eventfld.long 0x04 10. " NDF ,NACK detect flag" "Not detected,Detected" eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected" newline eventfld.long 0x04 8. " EPF ,End packet flag" "Not generated/Repeated,Generated/Repeated" rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "MIER,Master Interrupt Enable Register" bitfld.long 0x08 14. " DMIE ,Data match interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " PLTIE ,Pin low timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " FEIE ,FIFO error interrupt disable" "No,Yes" newline bitfld.long 0x08 11. " ALIE ,Arbitration lost interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " NDIE ,NACK detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " EPIE ,End packet interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "MDER,Master DMA Enable Register" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" line.long 0x10 "MCFGR0,Master Configuration Register 0" bitfld.long 0x10 9. " RDMO ,Receive data match only" "Stored,Discarded" bitfld.long 0x10 8. " CIRFIFO ,Circular FIFO enable" "Disabled,Enabled" bitfld.long 0x10 2. " HRSEL ,Host request select" "HREQ pin,Input trigger" newline bitfld.long 0x10 1. " HRPOL ,Host request polarity" "Active low,Active high" bitfld.long 0x10 0. " HREN ,Host request enable" "Disabled,Enabled" newline if (((per.l(ad:0x41230000+0x10))&0x01)==0x01) rgroup.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Disabled,,1st word = MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "SCL,SCL or SDA" newline bitfld.long 0x00 9. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "No effect,Enabled" bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" else group.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Disabled,,1st word = MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "On SCL low too long,On SCL or SDA low too long" newline bitfld.long 0x00 9. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "No effect,Enabled" bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" endif newline if ((((per.l(ad:0x41230000+0x10))&0x01)==0x00)||(((per.l(ad:0x41230000+0x14))&0x1000000)==0x00)) group.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" else rgroup.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" endif if (((per.l(ad:0x41230000+0x10))&0x01)==0x01) rgroup.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x58++0x03 line.long 0x00 "MFCR,Master FIFO Control Register" bitfld.long 0x00 16.--17. " RXWATER ,Receive FIFO watermark" "0,1,2,3" bitfld.long 0x00 0.--1. " TXWATER ,Transmit FIFO watermark" "0,1,2,3" rgroup.long 0x5C++0x03 line.long 0x00 "MFSR,Master FIFO Status Register" bitfld.long 0x00 16.--18. " RXCOUNT ,Receive FIFO count" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " TXCOUNT ,Transmit FIFO count" "0,1,2,3,4,5,6,7" newline wgroup.long 0x60++0x03 line.long 0x00 "MTDR,Master Transmit Data Register" bitfld.long 0x00 8.--10. " CMD ,Command data" "Transmit,Receive,Generate STOP,Receive and discard,START and transmit,START and transmit (NACK returned),START and transmit (high speed mode),START and transmit high speed mode (NACK returned)" newline hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data" newline hgroup.long 0x70++0x03 hide.long 0x00 "MRDR,Master Receive Data Register" in newline group.long 0x110++0x0F line.long 0x00 "SCR,Slave Control Register" bitfld.long 0x00 9. " RRF ,Receive FIFO reset" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Transmit FIFO reset" "No effect,Reset" bitfld.long 0x00 5. " FILTDZ ,Filter doze enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " FILTEN ,Filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " SEN ,Slave enable" "Disabled,Enabled" line.long 0x04 "SSR,Slave Status Register" rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x04 24. " SBF ,Slave busy flag" "Idle,Busy" rbitfld.long 0x04 15. " SARF ,SMBus alert response flag" "Not detected,Detected" rbitfld.long 0x04 14. " GCF ,General call flag" "Not detected,Detected" newline rbitfld.long 0x04 13. " AM1F ,Address match 1 flag" "Not matched,Matched" rbitfld.long 0x04 12. " AM0F ,Address match 0 flag" "Not matched,Matched" eventfld.long 0x04 11. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x04 10. " BEF ,Bit error flag" "No error,Error" newline eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected" eventfld.long 0x04 8. " RSF ,Repeated start flag" "Not detected,Detected" rbitfld.long 0x04 3. " TAF ,Transmit ACK flag" "Not required,Required" rbitfld.long 0x04 2. " AVF ,Address valid flag" "Invalid,Valid" newline rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "SIER,Slave Interrupt Enable Register" bitfld.long 0x08 15. " SARIE ,SMBus alert response interrupt enable" "Disabled,Enabled" bitfld.long 0x08 14. " GCIE ,General call interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " AM1F ,Address match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " AM0IE ,Address match 0 interrupt disable" "No,Yes" newline bitfld.long 0x08 11. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " BEIE ,Bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 8. " RSIE ,Repeated start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " TAIE ,Transmit ACK interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " AVIE ,Address valid interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "SDER,Slave DMA Enable Register" bitfld.long 0x0C 2. " AVDE ,Address valid DMA enable" "Disabled,Enabled" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" newline if (((per.l(ad:0x41230000+0x110))&0x01)==0x01) rgroup.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration match" "0 (7-bit),0 (10-bit),0 (7-bit) / 1 (7-bit),0 (10-bit) / 1 (10-bit),0 (7-bit) / 1 (10-bit),0 (10-bit) / 1 (7-bit),From 0 (7-bit) to 1 (7-bit),From 0 (10-bit) to 1 (10-bit)" bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" bitfld.long 0x00 12. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return data / clear RDF,Return address / clear AVF" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer,On TDR empty" bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration match" "0 (7-bit),0 (10-bit),0 (7-bit) / 1 (7-bit),0 (10-bit) / 1 (10-bit),0 (7-bit) / 1 (10-bit),0 (10-bit) / 1 (7-bit),From 0 (7-bit) to 1 (7-bit),From 0 (10-bit) to 1 (10-bit)" bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" bitfld.long 0x00 12. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return data / clear RDF,Return address / clear AVF" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer,On TDR empty" bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline if (((per.l(ad:0x41230000+0x110))&0x01)==0x01) rgroup.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" else group.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" endif rgroup.long 0x150++0x03 line.long 0x00 "SASR,Slave Address Status Register" bitfld.long 0x00 14. " ANV ,Address invalid" "No,Yes" hexmask.long.word 0x00 0.--10. 0x01 " RADDR ,Received address" if (((per.l(ad:0x41230000+0x124))&0x08)==0x08) group.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,NACK transmit" "ACK,NACK" else rgroup.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,NACK transmit" "ACK,NACK" endif wgroup.long 0x160++0x03 line.long 0x00 "STDR,Slave Transmit Data Register" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data" rgroup.long 0x170++0x03 line.long 0x00 "SRDR,Slave Receive Data Register" bitfld.long 0x00 15. " SOF ,Start of frame" "Not the first data word,First data word" bitfld.long 0x00 14. " RXEMPTY ,RX empty" "Not empty,Empty" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data receive" width 0x0B tree.end tree "LPIT" base ad:0x41210000 endian.be width 13. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.word 0x00 16.--31. 1. " FEATURE ,Feature number" hexmask.long.byte 0x00 8.--15. 1. " MINOR ,Minor version number" hexmask.long.byte 0x00 0.--7. 1. " MAJOR ,Major version number" line.long 0x04 "PARAM,Parameter Register" hexmask.long.byte 0x04 24.--31. 1. " CHANNEL ,Number of timer channels" hexmask.long.byte 0x04 16.--23. 1. " EXT_TRIG ,Number of external trigger inputs" group.long 0x08++0x03 line.long 0x00 "MCR,Module Control Register" bitfld.long 0x00 31. " M_CEN ,Module clock enable" "Disabled,Enabled" bitfld.long 0x00 30. " SW_RST ,Software reset bit" "No reset,Reset" bitfld.long 0x00 29. " DOZE_EN ,DOZE mode enable bit" "Disabled,Enabled" bitfld.long 0x00 28. " DBG_EN ,Debug enable bit" "Disabled,Enabled" if (((per.l.be(ad:0x41210000+0x08))&0x01)==0x01) group.long 0x0C++0x03 line.long 0x00 "MSR,Module Status Register" eventfld.long 0x00 31. " TIF0 ,Channel 0 timer interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 30. " TIF1 ,Channel 1 timer interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 29. " TIF2 ,Channel 2 timer interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 28. " TIF3 ,Channel 3 timer interrupt flag" "No interrupt,Interrupt" else rgroup.long 0x0C++0x03 line.long 0x00 "MSR,Module Status Register" bitfld.long 0x00 31. " TIF0 ,Channel 0 timer interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 30. " TIF1 ,Channel 1 timer interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 29. " TIF2 ,Channel 2 timer interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 28. " TIF3 ,Channel 3 timer interrupt flag" "No interrupt,Interrupt" endif group.long 0x10++0x03 line.long 0x00 "MIER,Module Interrupt Enable Register" bitfld.long 0x00 31. " TIE0 ,Channel 0 timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 30. " TIE1 ,Channel 1 timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 29. " TIE2 ,Channel 2 timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " TIE3 ,Channel 3 timer interrupt enable" "Disabled,Enabled" if (((per.l.be(ad:0x41210000+0x08))&0x01)==0x01) group.long 0x14++0x03 line.long 0x00 "TEN_SET/CLR,Set/Clear Timer Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " T_EN_0 ,Timer 0 enable" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " T_EN_1 ,Timer 1 enable" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x04 29. " T_EN_2 ,Timer 2 enable" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " T_EN_3 ,Timer 3 enable" "Disabled,Enabled" else rgroup.long 0x14++0x07 line.long 0x00 "SETTEN,Set Timer Enable Register" bitfld.long 0x00 31. " SET_T_EN_0 ,Set timer 0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " SET_T_EN_1 ,Set timer 1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " SET_T_EN_2 ,Set timer 2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " SET_T_EN_3 ,Set timer 3 enable" "Disabled,Enabled" line.long 0x04 "CLRTEN,Clear Timer Enable Register" bitfld.long 0x04 31. " CLR_T_EN_0 ,Clear timer 0 enable" "Disabled,Enabled" bitfld.long 0x04 30. " CLR_T_EN_1 ,Clear timer 1 enable" "Disabled,Enabled" bitfld.long 0x04 29. " CLR_T_EN_2 ,Clear timer 2 enable" "Disabled,Enabled" bitfld.long 0x04 28. " CLR_T_EN_3 ,Clear timer 3 enable" "Disabled,Enabled" endif if (((per.l.be(ad:0x41210000+0x08))&0x01)==0x01) group.long 0x20++0x03 line.long 0x00 "TVAL0,Timer Value Register" else rgroup.long 0x20++0x03 line.long 0x00 "TVAL0,Timer Value Register" endif rgroup.long (0x20+0x04)++0x03 line.long 0x00 "CVAL0,Current Timer Value Register" if (((per.l.be(ad:0x41210000+0x08))&0x01)==0x01) if (((per.l.be(ad:0x41210000+0x20+0x08))&0x01)==0x00) group.long (0x20+0x08)++0x03 line.long 0x00 "TCTRL0,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Immediately,Rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." else group.long (0x20+0x08)++0x03 line.long 0x00 "TCTRL0,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" rbitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." endif else rgroup.long (0x20+0x08)++0x03 line.long 0x00 "TCTRL0,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." endif if (((per.l.be(ad:0x41210000+0x08))&0x01)==0x01) group.long 0x30++0x03 line.long 0x00 "TVAL1,Timer Value Register" else rgroup.long 0x30++0x03 line.long 0x00 "TVAL1,Timer Value Register" endif rgroup.long (0x30+0x04)++0x03 line.long 0x00 "CVAL1,Current Timer Value Register" if (((per.l.be(ad:0x41210000+0x08))&0x01)==0x01) if (((per.l.be(ad:0x41210000+0x30+0x08))&0x01)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "TCTRL1,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Immediately,Rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." else group.long (0x30+0x08)++0x03 line.long 0x00 "TCTRL1,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" rbitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." endif else rgroup.long (0x30+0x08)++0x03 line.long 0x00 "TCTRL1,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." endif if (((per.l.be(ad:0x41210000+0x08))&0x01)==0x01) group.long 0x40++0x03 line.long 0x00 "TVAL2,Timer Value Register" else rgroup.long 0x40++0x03 line.long 0x00 "TVAL2,Timer Value Register" endif rgroup.long (0x40+0x04)++0x03 line.long 0x00 "CVAL2,Current Timer Value Register" if (((per.l.be(ad:0x41210000+0x08))&0x01)==0x01) if (((per.l.be(ad:0x41210000+0x40+0x08))&0x01)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "TCTRL2,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Immediately,Rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." else group.long (0x40+0x08)++0x03 line.long 0x00 "TCTRL2,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" rbitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." endif else rgroup.long (0x40+0x08)++0x03 line.long 0x00 "TCTRL2,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." endif if (((per.l.be(ad:0x41210000+0x08))&0x01)==0x01) group.long 0x50++0x03 line.long 0x00 "TVAL3,Timer Value Register" else rgroup.long 0x50++0x03 line.long 0x00 "TVAL3,Timer Value Register" endif rgroup.long (0x50+0x04)++0x03 line.long 0x00 "CVAL3,Current Timer Value Register" if (((per.l.be(ad:0x41210000+0x08))&0x01)==0x01) if (((per.l.be(ad:0x41210000+0x50+0x08))&0x01)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "TCTRL3,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Immediately,Rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." else group.long (0x50+0x08)++0x03 line.long 0x00 "TCTRL3,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" rbitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." endif else rgroup.long (0x50+0x08)++0x03 line.long 0x00 "TCTRL3,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." endif endian.le width 0x0B tree.end tree "LPUART (Low Power Universal Asynchronous Receiver/Transmitter)" base ad:0x41220000 width 8. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature identification number" line.long 0x04 "PARAM,Parameter Register" hexmask.long.byte 0x04 8.--15. 1. " RXFIFO ,Receive FIFO size" hexmask.long.byte 0x04 0.--7. 1. " TXFIFO ,Transmit FIFO size" group.long 0x08++0x03 line.long 0x00 "GLOBAL,Global Register" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" if (((per.l(ad:0x41220000+0x18))&0xC0000)==0x00) group.long 0x0C++0x03 line.long 0x00 "PINCFG,Pin Configuration Register" bitfld.long 0x00 0.--1. " TRGSEL ,Trigger select" "Disabled,Instead RX in,Instead CTS in,TX out modulation" else rgroup.long 0x0C++0x03 line.long 0x00 "PINCFG,Pin Configuration Register" bitfld.long 0x00 0.--1. " TRGSEL ,Trigger select" "Disabled,Instead RX in,Instead CTS in,TX out modulation" endif group.long 0x10++0x07 line.long 0x00 "BAUD,Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" bitfld.long 0x00 29. " M10 ,10-bit mode select" "7/8/9 bit,10 bit" newline bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" "16x,,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 20. " RIDMAE ,Receiver idle DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " SBNS ,Stop bit number select" "One,Two" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" bitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" bitfld.long 0x04 26. " BRK13 ,Break character generation length" "9-13 bit,12-15 bit" newline bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" newline eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" newline if (((per.l(ad:0x41220000+0x18))&0xC0000)==0x00) if ((per.b(ad:0x41220000+0x18)&0x08)==0x08) group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" newline bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,LPUART in Doze mode enabled" "LPUART enabled,LPUART disabled" newline bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" else group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" newline bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,LPUART in Doze mode enabled" "LPUART enabled,LPUART disabled" newline bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif else group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" rbitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" rbitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" rbitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline rbitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" rbitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline rbitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" rbitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" newline rbitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" rbitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" rbitfld.long 0x00 6. " DOZEEN ,LPUART in Doze mode enabled" "LPUART enabled,LPUART disabled" newline rbitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" rbitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" rbitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline rbitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" rbitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" rbitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif group.long 0x1C++0x07 line.long 0x00 "DATA,Data Register" rbitfld.long 0x00 15. " NOISY ,Current received dataword noise" "Not noisy,Noisy" rbitfld.long 0x00 14. " PARITYE ,Current received dataword parity error" "No error,Error" bitfld.long 0x00 13. " FRETSC ,Current received dataword frame error/Transmit special character" "No error/Normal character,Error/Special character" newline rbitfld.long 0x00 12. " RXEMPT ,Receive buffer empty" "Not empty,Empty" rbitfld.long 0x00 11. " IDLINE ,Receiver line idle status before receiving current character" "Not idle,Idle" newline bitfld.long 0x00 9. " R9T9 ,Read receive data buffer 9 or write transmit data buffer 9" "Low,High" bitfld.long 0x00 8. " R8T8 ,Read receive data buffer 8 or write transmit data buffer 8" "Low,High" bitfld.long 0x00 7. " R7T7 ,Read receive data buffer 7 or write transmit data buffer 7" "Low,High" newline bitfld.long 0x00 6. " R6T6 ,Read receive data buffer 6 or write transmit data buffer 6" "Low,High" bitfld.long 0x00 5. " R5T5 ,Read receive data buffer 5 or write transmit data buffer 5" "Low,High" bitfld.long 0x00 4. " R4T4 ,Read receive data buffer 4 or write transmit data buffer 4" "Low,High" newline bitfld.long 0x00 3. " R3T3 ,Read receive data buffer 3 or write transmit data buffer 3" "Low,High" bitfld.long 0x00 2. " R2T2 ,Read receive data buffer 2 or write transmit data buffer 2" "Low,High" bitfld.long 0x00 1. " R1T1 ,Read receive data buffer 1 or write transmit data buffer 1" "Low,High" newline bitfld.long 0x00 0. " R0T0 ,Read receive data buffer 0 or write transmit data buffer 0" "Low,High" line.long 0x04 "MATCH,Match Address Register" hexmask.long.word 0x04 16.--25. 0x01 " MA2 ,Match address 2" hexmask.long.word 0x04 0.--9. 0x01 " MA1 ,Match address 1" if (((per.l(ad:0x41220000+0x18))&0xC0000)==0x00) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" bitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" newline bitfld.long 0x00 8.--12. " RTSWATER ,Receive RTS configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" elif (((per.l(ad:0x41220000+0x18))&0xC0000)==0x40000) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" newline rbitfld.long 0x00 8.--12. " RTSWATER ,Receive RTS configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" rbitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" elif (((per.l(ad:0x41220000+0x18))&0xC0000)==0x80000) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" newline bitfld.long 0x00 8.--12. " RTSWATER ,Receive RTS configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" rbitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline rbitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" newline rbitfld.long 0x00 8.--12. " RTSWATER ,Receive RTS configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" rbitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" rbitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline rbitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" endif if ((((per.l(ad:0x41220000+0x18))&0xC0000)==0x00)&&(((per.l(ad:0x41220000+0x28))&0xC00000)==0xC00000)) group.long 0x28++0x03 line.long 0x00 "FIFO,FIFO Register" rbitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO empty" "Not empty,Empty" rbitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO empty" "Not empty,Empty" eventfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" eventfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" newline rbitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" else rgroup.long 0x28++0x03 line.long 0x00 "FIFO,FIFO Register" bitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" bitfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" endif if (((per.l(ad:0x41220000+0x18))&0x80000)==0x80000) rgroup.long 0x2C++0x03 line.long 0x00 "WATER,Watermark Register" bitfld.long 0x00 24.--29. " RXCOUNT ,Receive counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--20. " RXWATER ,Receive watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " TXCOUNT ,Transmit counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--4. " TXWATER ,Transmit watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x2C++0x03 line.long 0x00 "WATER,Watermark Register" rbitfld.long 0x00 24.--29. " RXCOUNT ,Receive counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--20. " RXWATER ,Receive watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " TXCOUNT ,Transmit counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--4. " TXWATER ,Transmit watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif width 0x0B tree.end tree "RGPIO (Rapid General-Purpose Input and Output)" base ad:0x410F0000 width 6. group.long 0x00++0x03 line.long 0x00 "PDOR,Port Data Output Register" bitfld.long 0x00 31. " PDO[31] ,Port data output pin 31" "Low,High" bitfld.long 0x00 30. " [30] ,Port data output pin 30" "Low,High" bitfld.long 0x00 29. " [29] ,Port data output pin 29" "Low,High" bitfld.long 0x00 28. " [28] ,Port data output pin 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,Port data output pin 27" "Low,High" bitfld.long 0x00 26. " [26] ,Port data output pin 26" "Low,High" bitfld.long 0x00 25. " [25] ,Port data output pin 25" "Low,High" bitfld.long 0x00 24. " [24] ,Port data output pin 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,Port data output pin 23" "Low,High" bitfld.long 0x00 22. " [22] ,Port data output pin 22" "Low,High" bitfld.long 0x00 21. " [21] ,Port data output pin 21" "Low,High" bitfld.long 0x00 20. " [20] ,Port data output pin 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,Port data output pin 19" "Low,High" bitfld.long 0x00 18. " [18] ,Port data output pin 18" "Low,High" bitfld.long 0x00 17. " [17] ,Port data output pin 17" "Low,High" bitfld.long 0x00 16. " [16] ,Port data output pin 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,Port data output pin 15" "Low,High" bitfld.long 0x00 14. " [14] ,Port data output pin 14" "Low,High" bitfld.long 0x00 13. " [13] ,Port data output pin 13" "Low,High" bitfld.long 0x00 12. " [12] ,Port data output pin 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,Port data output pin 11" "Low,High" bitfld.long 0x00 10. " [10] ,Port data output pin 10" "Low,High" bitfld.long 0x00 9. " [9] ,Port data output pin 9" "Low,High" bitfld.long 0x00 8. " [8] ,Port data output pin 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,Port data output pin 7" "Low,High" bitfld.long 0x00 6. " [6] ,Port data output pin 6" "Low,High" bitfld.long 0x00 5. " [5] ,Port data output pin 5" "Low,High" bitfld.long 0x00 4. " [4] ,Port data output pin 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,Port data output pin 3" "Low,High" bitfld.long 0x00 2. " [2] ,Port data output pin 2" "Low,High" bitfld.long 0x00 1. " [1] ,Port data output pin 1" "Low,High" bitfld.long 0x00 0. " [0] ,Port data output pin 0" "Low,High" wgroup.long 0x04++0x0B line.long 0x00 "PSOR,Port Set Output Register" bitfld.long 0x00 31. " PTSO[31] ,Port set output pin 31" "No effect,Set" bitfld.long 0x00 30. " [30] ,Port set output pin 30" "No effect,Set" bitfld.long 0x00 29. " [29] ,Port set output pin 29" "No effect,Set" bitfld.long 0x00 28. " [28] ,Port set output pin 28" "No effect,Set" newline bitfld.long 0x00 27. " [27] ,Port set output pin 27" "No effect,Set" bitfld.long 0x00 26. " [26] ,Port set output pin 26" "No effect,Set" bitfld.long 0x00 25. " [25] ,Port set output pin 25" "No effect,Set" bitfld.long 0x00 24. " [24] ,Port set output pin 24" "No effect,Set" newline bitfld.long 0x00 23. " [23] ,Port set output pin 23" "No effect,Set" bitfld.long 0x00 22. " [22] ,Port set output pin 22" "No effect,Set" bitfld.long 0x00 21. " [21] ,Port set output pin 21" "No effect,Set" bitfld.long 0x00 20. " [20] ,Port set output pin 20" "No effect,Set" newline bitfld.long 0x00 19. " [19] ,Port set output pin 19" "No effect,Set" bitfld.long 0x00 18. " [18] ,Port set output pin 18" "No effect,Set" bitfld.long 0x00 17. " [17] ,Port set output pin 17" "No effect,Set" bitfld.long 0x00 16. " [16] ,Port set output pin 16" "No effect,Set" newline bitfld.long 0x00 15. " [15] ,Port set output pin 15" "No effect,Set" bitfld.long 0x00 14. " [14] ,Port set output pin 14" "No effect,Set" bitfld.long 0x00 13. " [13] ,Port set output pin 13" "No effect,Set" bitfld.long 0x00 12. " [12] ,Port set output pin 12" "No effect,Set" newline bitfld.long 0x00 11. " [11] ,Port set output pin 11" "No effect,Set" bitfld.long 0x00 10. " [10] ,Port set output pin 10" "No effect,Set" bitfld.long 0x00 9. " [9] ,Port set output pin 9" "No effect,Set" bitfld.long 0x00 8. " [8] ,Port set output pin 8" "No effect,Set" newline bitfld.long 0x00 7. " [7] ,Port set output pin 7" "No effect,Set" bitfld.long 0x00 6. " [6] ,Port set output pin 6" "No effect,Set" bitfld.long 0x00 5. " [5] ,Port set output pin 5" "No effect,Set" bitfld.long 0x00 4. " [4] ,Port set output pin 4" "No effect,Set" newline bitfld.long 0x00 3. " [3] ,Port set output pin 3" "No effect,Set" bitfld.long 0x00 2. " [2] ,Port set output pin 2" "No effect,Set" bitfld.long 0x00 1. " [1] ,Port set output pin 1" "No effect,Set" bitfld.long 0x00 0. " [0] ,Port set output pin 0" "No effect,Set" line.long 0x04 "PCOR,Port Clear Output Register" bitfld.long 0x04 31. " PTCO[31] ,Port clear output pin 31" "No effect,Clear" bitfld.long 0x04 30. " [30] ,Port clear output pin 30" "No effect,Clear" bitfld.long 0x04 29. " [29] ,Port clear output pin 29" "No effect,Clear" bitfld.long 0x04 28. " [28] ,Port clear output pin 28" "No effect,Clear" newline bitfld.long 0x04 27. " [27] ,Port clear output pin 27" "No effect,Clear" bitfld.long 0x04 26. " [26] ,Port clear output pin 26" "No effect,Clear" bitfld.long 0x04 25. " [25] ,Port clear output pin 25" "No effect,Clear" bitfld.long 0x04 24. " [24] ,Port clear output pin 24" "No effect,Clear" newline bitfld.long 0x04 23. " [23] ,Port clear output pin 23" "No effect,Clear" bitfld.long 0x04 22. " [22] ,Port clear output pin 22" "No effect,Clear" bitfld.long 0x04 21. " [21] ,Port clear output pin 21" "No effect,Clear" bitfld.long 0x04 20. " [20] ,Port clear output pin 20" "No effect,Clear" newline bitfld.long 0x04 19. " [19] ,Port clear output pin 19" "No effect,Clear" bitfld.long 0x04 18. " [18] ,Port clear output pin 18" "No effect,Clear" bitfld.long 0x04 17. " [17] ,Port clear output pin 17" "No effect,Clear" bitfld.long 0x04 16. " [16] ,Port clear output pin 16" "No effect,Clear" newline bitfld.long 0x04 15. " [15] ,Port clear output pin 15" "No effect,Clear" bitfld.long 0x04 14. " [14] ,Port clear output pin 14" "No effect,Clear" bitfld.long 0x04 13. " [13] ,Port clear output pin 13" "No effect,Clear" bitfld.long 0x04 12. " [12] ,Port clear output pin 12" "No effect,Clear" newline bitfld.long 0x04 11. " [11] ,Port clear output pin 11" "No effect,Clear" bitfld.long 0x04 10. " [10] ,Port clear output pin 10" "No effect,Clear" bitfld.long 0x04 9. " [9] ,Port clear output pin 9" "No effect,Clear" bitfld.long 0x04 8. " [8] ,Port clear output pin 8" "No effect,Clear" newline bitfld.long 0x04 7. " [7] ,Port clear output pin 7" "No effect,Clear" bitfld.long 0x04 6. " [6] ,Port clear output pin 6" "No effect,Clear" bitfld.long 0x04 5. " [5] ,Port clear output pin 5" "No effect,Clear" bitfld.long 0x04 4. " [4] ,Port clear output pin 4" "No effect,Clear" newline bitfld.long 0x04 3. " [3] ,Port clear output pin 3" "No effect,Clear" bitfld.long 0x04 2. " [2] ,Port clear output pin 2" "No effect,Clear" bitfld.long 0x04 1. " [1] ,Port clear output pin 1" "No effect,Clear" bitfld.long 0x04 0. " [0] ,Port clear output pin 0" "No effect,Clear" line.long 0x08 "PTOR,Port Toggle Output Register" bitfld.long 0x08 31. " PTTO[31] ,Port toggle output pin 31" "No effect,Toggled" bitfld.long 0x08 30. " [30] ,Port toggle output pin 30" "No effect,Toggled" bitfld.long 0x08 29. " [29] ,Port toggle output pin 29" "No effect,Toggled" bitfld.long 0x08 28. " [28] ,Port toggle output pin 28" "No effect,Toggled" newline bitfld.long 0x08 27. " [27] ,Port toggle output pin 27" "No effect,Toggled" bitfld.long 0x08 26. " [26] ,Port toggle output pin 26" "No effect,Toggled" bitfld.long 0x08 25. " [25] ,Port toggle output pin 25" "No effect,Toggled" bitfld.long 0x08 24. " [24] ,Port toggle output pin 24" "No effect,Toggled" newline bitfld.long 0x08 23. " [23] ,Port toggle output pin 23" "No effect,Toggled" bitfld.long 0x08 22. " [22] ,Port toggle output pin 22" "No effect,Toggled" bitfld.long 0x08 21. " [21] ,Port toggle output pin 21" "No effect,Toggled" bitfld.long 0x08 20. " [20] ,Port toggle output pin 20" "No effect,Toggled" newline bitfld.long 0x08 19. " [19] ,Port toggle output pin 19" "No effect,Toggled" bitfld.long 0x08 18. " [18] ,Port toggle output pin 18" "No effect,Toggled" bitfld.long 0x08 17. " [17] ,Port toggle output pin 17" "No effect,Toggled" bitfld.long 0x08 16. " [16] ,Port toggle output pin 16" "No effect,Toggled" newline bitfld.long 0x08 15. " [15] ,Port toggle output pin 15" "No effect,Toggled" bitfld.long 0x08 14. " [14] ,Port toggle output pin 14" "No effect,Toggled" bitfld.long 0x08 13. " [13] ,Port toggle output pin 13" "No effect,Toggled" bitfld.long 0x08 12. " [12] ,Port toggle output pin 12" "No effect,Toggled" newline bitfld.long 0x08 11. " [11] ,Port toggle output pin 11" "No effect,Toggled" bitfld.long 0x08 10. " [10] ,Port toggle output pin 10" "No effect,Toggled" bitfld.long 0x08 9. " [9] ,Port toggle output pin 9" "No effect,Toggled" bitfld.long 0x08 8. " [8] ,Port toggle output pin 8" "No effect,Toggled" newline bitfld.long 0x08 7. " [7] ,Port toggle output pin 7" "No effect,Toggled" bitfld.long 0x08 6. " [6] ,Port toggle output pin 6" "No effect,Toggled" bitfld.long 0x08 5. " [5] ,Port toggle output pin 5" "No effect,Toggled" bitfld.long 0x08 4. " [4] ,Port toggle output pin 4" "No effect,Toggled" newline bitfld.long 0x08 3. " [3] ,Port toggle output pin 3" "No effect,Toggled" bitfld.long 0x08 2. " [2] ,Port toggle output pin 2" "No effect,Toggled" bitfld.long 0x08 1. " [1] ,Port toggle output pin 1" "No effect,Toggled" bitfld.long 0x08 0. " [0] ,Port toggle output pin 0" "No effect,Toggled" rgroup.long 0x10++0x03 line.long 0x00 "PDIR,Port Data Input Register" bitfld.long 0x00 31. " PDI[31] ,Port data input pin 31" "Low/Not configured,High" bitfld.long 0x00 30. " [30] ,Port data input pin 30" "Low/Not configured,High" bitfld.long 0x00 29. " [29] ,Port data input pin 29" "Low/Not configured,High" bitfld.long 0x00 28. " [28] ,Port data input pin 28" "Low/Not configured,High" newline bitfld.long 0x00 27. " [27] ,Port data input pin 27" "Low/Not configured,High" bitfld.long 0x00 26. " [26] ,Port data input pin 26" "Low/Not configured,High" bitfld.long 0x00 25. " [25] ,Port data input pin 25" "Low/Not configured,High" bitfld.long 0x00 24. " [24] ,Port data input pin 24" "Low/Not configured,High" newline bitfld.long 0x00 23. " [23] ,Port data input pin 23" "Low/Not configured,High" bitfld.long 0x00 22. " [22] ,Port data input pin 22" "Low/Not configured,High" bitfld.long 0x00 21. " [21] ,Port data input pin 21" "Low/Not configured,High" bitfld.long 0x00 20. " [20] ,Port data input pin 20" "Low/Not configured,High" newline bitfld.long 0x00 19. " [19] ,Port data input pin 19" "Low/Not configured,High" bitfld.long 0x00 18. " [18] ,Port data input pin 18" "Low/Not configured,High" bitfld.long 0x00 17. " [17] ,Port data input pin 17" "Low/Not configured,High" bitfld.long 0x00 16. " [16] ,Port data input pin 16" "Low/Not configured,High" newline bitfld.long 0x00 15. " [15] ,Port data input pin 15" "Low/Not configured,High" bitfld.long 0x00 14. " [14] ,Port data input pin 14" "Low/Not configured,High" bitfld.long 0x00 13. " [13] ,Port data input pin 13" "Low/Not configured,High" bitfld.long 0x00 12. " [12] ,Port data input pin 12" "Low/Not configured,High" newline bitfld.long 0x00 11. " [11] ,Port data input pin 11" "Low/Not configured,High" bitfld.long 0x00 10. " [10] ,Port data input pin 10" "Low/Not configured,High" bitfld.long 0x00 9. " [9] ,Port data input pin 9" "Low/Not configured,High" bitfld.long 0x00 8. " [8] ,Port data input pin 8" "Low/Not configured,High" newline bitfld.long 0x00 7. " [7] ,Port data input pin 7" "Low/Not configured,High" bitfld.long 0x00 6. " [6] ,Port data input pin 6" "Low/Not configured,High" bitfld.long 0x00 5. " [5] ,Port data input pin 5" "Low/Not configured,High" bitfld.long 0x00 4. " [4] ,Port data input pin 4" "Low/Not configured,High" newline bitfld.long 0x00 3. " [3] ,Port data input pin 3" "Low/Not configured,High" bitfld.long 0x00 2. " [2] ,Port data input pin 2" "Low/Not configured,High" bitfld.long 0x00 1. " [1] ,Port data input pin 1" "Low/Not configured,High" bitfld.long 0x00 0. " [0] ,Port data input pin 0" "Low/Not configured,High" group.long 0x14++0x03 line.long 0x00 "PDDR,Port Data Direction Register" bitfld.long 0x00 31. " PDD[31] ,Port data direction" "Input,Output" bitfld.long 0x00 30. " [30] ,Port data direction pin 30" "Input,Output" bitfld.long 0x00 29. " [29] ,Port data direction pin 29" "Input,Output" bitfld.long 0x00 28. " [28] ,Port data direction pin 28" "Input,Output" newline bitfld.long 0x00 27. " [27] ,Port data direction pin 27" "Input,Output" bitfld.long 0x00 26. " [26] ,Port data direction pin 26" "Input,Output" bitfld.long 0x00 25. " [25] ,Port data direction pin 25" "Input,Output" bitfld.long 0x00 24. " [24] ,Port data direction pin 24" "Input,Output" newline bitfld.long 0x00 23. " [23] ,Port data direction pin 23" "Input,Output" bitfld.long 0x00 22. " [22] ,Port data direction pin 22" "Input,Output" bitfld.long 0x00 21. " [21] ,Port data direction pin 21" "Input,Output" bitfld.long 0x00 20. " [20] ,Port data direction pin 20" "Input,Output" newline bitfld.long 0x00 19. " [19] ,Port data direction pin 19" "Input,Output" bitfld.long 0x00 18. " [18] ,Port data direction pin 18" "Input,Output" bitfld.long 0x00 17. " [17] ,Port data direction pin 17" "Input,Output" bitfld.long 0x00 16. " [16] ,Port data direction pin 16" "Input,Output" newline bitfld.long 0x00 15. " [15] ,Port data direction pin 15" "Input,Output" bitfld.long 0x00 14. " [14] ,Port data direction pin 14" "Input,Output" bitfld.long 0x00 13. " [13] ,Port data direction pin 13" "Input,Output" bitfld.long 0x00 12. " [12] ,Port data direction pin 12" "Input,Output" newline bitfld.long 0x00 11. " [11] ,Port data direction pin 11" "Input,Output" bitfld.long 0x00 10. " [10] ,Port data direction pin 10" "Input,Output" bitfld.long 0x00 9. " [9] ,Port data direction pin 9" "Input,Output" bitfld.long 0x00 8. " [8] ,Port data direction pin 8" "Input,Output" newline bitfld.long 0x00 7. " [7] ,Port data direction pin 7" "Input,Output" bitfld.long 0x00 6. " [6] ,Port data direction pin 6" "Input,Output" bitfld.long 0x00 5. " [5] ,Port data direction pin 5" "Input,Output" bitfld.long 0x00 4. " [4] ,Port data direction pin 4" "Input,Output" newline bitfld.long 0x00 3. " [3] ,Port data direction pin 3" "Input,Output" bitfld.long 0x00 2. " [2] ,Port data direction pin 2" "Input,Output" bitfld.long 0x00 1. " [1] ,Port data direction pin 1" "Input,Output" bitfld.long 0x00 0. " [0] ,Port data direction pin 0" "Input,Output" width 0x0B tree.end tree "TPM" base ad:0x41200000 endian.be width 9. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature identification number" line.long 0x04 "PARAM,Parameter Register" hexmask.long.byte 0x04 16.--23. 1. " WIDTH ,Counter width" hexmask.long.byte 0x04 8.--15. 1. " TRIG ,Trigger count" hexmask.long.byte 0x04 0.--7. 1. " CHAN ,Channel count" group.long 0x08++0x03 line.long 0x00 "GLOBAL,TPM Global Register" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" if (((per.l.be(ad:0x41200000+0x10))&0x18)==0x00) group.long 0x10++0x03 line.long 0x00 "SC,Status And Control Register" bitfld.long 0x00 8. " DMA ,DMA enable" "Disabled,Enabled" eventfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-down counting" bitfld.long 0x00 3.--4. " CMOD ,Clock mode select" "Disabled,Counter clock,Clock rising edge,Input rising edge" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x10++0x03 line.long 0x00 "SC,Status And Control Register" bitfld.long 0x00 8. " DMA ,DMA enable" "Disabled,Enabled" eventfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-down counting" bitfld.long 0x00 3.--4. " CMOD ,Clock mode select" "Disabled,Counter clock,Clock rising edge,Input rising edge" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif group.long 0x14++0x0B line.long 0x00 "CNT,Counter Register" line.long 0x04 "MOD,Modulo Register" line.long 0x08 "STATUS,Capture And Compare Status Register" eventfld.long 0x08 8. " TOF ,Timer overflow flag" "No overflow,Overflow" eventfld.long 0x08 5. " CH5F ,Channel 5 flag" "Not occurred,Occurred" eventfld.long 0x08 4. " CH4F ,Channel 4 flag" "Not occurred,Occurred" newline eventfld.long 0x08 3. " CH3F ,Channel 3 flag" "Not occurred,Occurred" eventfld.long 0x08 2. " CH2F ,Channel 2 flag" "Not occurred,Occurred" eventfld.long 0x08 1. " CH1F ,Channel 1 flag" "Not occurred,Occurred" newline eventfld.long 0x08 0. " CH0F ,Channel 0 flag" "Not occurred,Occurred" if (((per.l.be(ad:0x41200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x41200000+0x20)&0x30)==0x00)) group.long 0x20++0x03 line.long 0x00 "C0SC,Channel 0 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x41200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x41200000+0x20)&0x30)==0x10)) group.long 0x20++0x03 line.long 0x00 "C0SC,Channel 0 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Not used,Toggle output,Clear output,Set output" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x41200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x41200000+0x20)&0x30)==0x20)) group.long 0x20++0x03 line.long 0x00 "C0SC,Channel 0 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x41200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x41200000+0x20)&0x30)==0x30)) group.long 0x20++0x03 line.long 0x00 "C0SC,Channel 0 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Pulse output high,Pulse output low,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x41200000+0x10)&0x20)==0x20)&&((per.l.be(ad:0x41200000+0x20)&0x30)==0x20)) group.long 0x20++0x03 line.long 0x00 "C0SC,Channel 0 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x20++0x03 hide.long 0x00 "C0SC,Channel 0 Status And Control Register" newline endif group.long (0x20+0x04)++0x03 line.long 0x00 "C0V,Channel 0 Value Register" if (((per.l.be(ad:0x41200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x41200000+0x28)&0x30)==0x00)) group.long 0x28++0x03 line.long 0x00 "C1SC,Channel 1 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x41200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x41200000+0x28)&0x30)==0x10)) group.long 0x28++0x03 line.long 0x00 "C1SC,Channel 1 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Not used,Toggle output,Clear output,Set output" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x41200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x41200000+0x28)&0x30)==0x20)) group.long 0x28++0x03 line.long 0x00 "C1SC,Channel 1 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x41200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x41200000+0x28)&0x30)==0x30)) group.long 0x28++0x03 line.long 0x00 "C1SC,Channel 1 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Pulse output high,Pulse output low,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x41200000+0x10)&0x20)==0x20)&&((per.l.be(ad:0x41200000+0x28)&0x30)==0x20)) group.long 0x28++0x03 line.long 0x00 "C1SC,Channel 1 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x28++0x03 hide.long 0x00 "C1SC,Channel 1 Status And Control Register" newline endif group.long (0x28+0x04)++0x03 line.long 0x00 "C1V,Channel 1 Value Register" if (((per.l.be(ad:0x41200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x41200000+0x30)&0x30)==0x00)) group.long 0x30++0x03 line.long 0x00 "C2SC,Channel 2 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 2 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x41200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x41200000+0x30)&0x30)==0x10)) group.long 0x30++0x03 line.long 0x00 "C2SC,Channel 2 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 2 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Not used,Toggle output,Clear output,Set output" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x41200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x41200000+0x30)&0x30)==0x20)) group.long 0x30++0x03 line.long 0x00 "C2SC,Channel 2 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 2 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x41200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x41200000+0x30)&0x30)==0x30)) group.long 0x30++0x03 line.long 0x00 "C2SC,Channel 2 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 2 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Pulse output high,Pulse output low,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x41200000+0x10)&0x20)==0x20)&&((per.l.be(ad:0x41200000+0x30)&0x30)==0x20)) group.long 0x30++0x03 line.long 0x00 "C2SC,Channel 2 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 2 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x30++0x03 hide.long 0x00 "C2SC,Channel 2 Status And Control Register" newline endif group.long (0x30+0x04)++0x03 line.long 0x00 "C2V,Channel 2 Value Register" if (((per.l.be(ad:0x41200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x41200000+0x38)&0x30)==0x00)) group.long 0x38++0x03 line.long 0x00 "C3SC,Channel 3 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 3 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x41200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x41200000+0x38)&0x30)==0x10)) group.long 0x38++0x03 line.long 0x00 "C3SC,Channel 3 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 3 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Not used,Toggle output,Clear output,Set output" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x41200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x41200000+0x38)&0x30)==0x20)) group.long 0x38++0x03 line.long 0x00 "C3SC,Channel 3 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 3 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x41200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x41200000+0x38)&0x30)==0x30)) group.long 0x38++0x03 line.long 0x00 "C3SC,Channel 3 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 3 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Pulse output high,Pulse output low,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x41200000+0x10)&0x20)==0x20)&&((per.l.be(ad:0x41200000+0x38)&0x30)==0x20)) group.long 0x38++0x03 line.long 0x00 "C3SC,Channel 3 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 3 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x38++0x03 hide.long 0x00 "C3SC,Channel 3 Status And Control Register" newline endif group.long (0x38+0x04)++0x03 line.long 0x00 "C3V,Channel 3 Value Register" if (((per.l.be(ad:0x41200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x41200000+0x40)&0x30)==0x00)) group.long 0x40++0x03 line.long 0x00 "C4SC,Channel 4 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x41200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x41200000+0x40)&0x30)==0x10)) group.long 0x40++0x03 line.long 0x00 "C4SC,Channel 4 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Not used,Toggle output,Clear output,Set output" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x41200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x41200000+0x40)&0x30)==0x20)) group.long 0x40++0x03 line.long 0x00 "C4SC,Channel 4 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x41200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x41200000+0x40)&0x30)==0x30)) group.long 0x40++0x03 line.long 0x00 "C4SC,Channel 4 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Pulse output high,Pulse output low,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x41200000+0x10)&0x20)==0x20)&&((per.l.be(ad:0x41200000+0x40)&0x30)==0x20)) group.long 0x40++0x03 line.long 0x00 "C4SC,Channel 4 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x40++0x03 hide.long 0x00 "C4SC,Channel 4 Status And Control Register" newline endif group.long (0x40+0x04)++0x03 line.long 0x00 "C4V,Channel 4 Value Register" if (((per.l.be(ad:0x41200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x41200000+0x48)&0x30)==0x00)) group.long 0x48++0x03 line.long 0x00 "C5SC,Channel 5 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 5 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x41200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x41200000+0x48)&0x30)==0x10)) group.long 0x48++0x03 line.long 0x00 "C5SC,Channel 5 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 5 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Not used,Toggle output,Clear output,Set output" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x41200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x41200000+0x48)&0x30)==0x20)) group.long 0x48++0x03 line.long 0x00 "C5SC,Channel 5 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 5 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x41200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x41200000+0x48)&0x30)==0x30)) group.long 0x48++0x03 line.long 0x00 "C5SC,Channel 5 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 5 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Pulse output high,Pulse output low,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x41200000+0x10)&0x20)==0x20)&&((per.l.be(ad:0x41200000+0x48)&0x30)==0x20)) group.long 0x48++0x03 line.long 0x00 "C5SC,Channel 5 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 5 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x48++0x03 hide.long 0x00 "C5SC,Channel 5 Status And Control Register" newline endif group.long (0x48+0x04)++0x03 line.long 0x00 "C5V,Channel 5 Value Register" group.long 0x64++0x03 line.long 0x00 "COMBINE,Combine Channel Register" bitfld.long 0x00 17. " COMSWAP2 ,Combine channels 4 and 5 swap" "Even,Odd" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" bitfld.long 0x00 9. " COMSWAP1 ,Combine channels 2 and 3 swap" "Even,Odd" newline bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" bitfld.long 0x00 1. " COMSWAP0 ,Combine channels 0 and 1 swap" "Even,Odd" bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" group.long 0x6C++0x07 line.long 0x00 "TRIG,Channel Trigger Register" bitfld.long 0x00 5. " TRIG5 ,Channel 5 trigger" "No effect,Used" bitfld.long 0x00 4. " TRIG4 ,Channel 4 trigger" "No effect,Used" bitfld.long 0x00 3. " TRIG3 ,Channel 3 trigger" "No effect,Used" newline bitfld.long 0x00 2. " TRIG2 ,Channel 2 trigger" "No effect,Used" bitfld.long 0x00 1. " TRIG1 ,Channel 1 trigger" "No effect,Used" bitfld.long 0x00 0. " TRIG0 ,Channel 0 trigger" "No effect,Used" line.long 0x04 "POL,Channel Polarity Register" bitfld.long 0x04 5. " POL5 ,Channel 5 polarity" "High,Low" bitfld.long 0x04 4. " POL4 ,Channel 4 polarity" "High,Low" bitfld.long 0x04 3. " POL3 ,Channel 3 polarity" "High,Low" newline bitfld.long 0x04 2. " POL2 ,Channel 2 polarity" "High,Low" bitfld.long 0x04 1. " POL1 ,Channel 1 polarity" "High,Low" bitfld.long 0x04 0. " POL0 ,Channel 0 polarity" "High,Low" group.long 0x78++0x03 line.long 0x00 "FILTER,Filter Control Register" bitfld.long 0x00 20.--23. " CH5FVAL ,Channel 5 filter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CH4FVAL ,Channel 4 filter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 filter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 filter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 filter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 filter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status Register" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase,Count and direction" rbitfld.long 0x00 2. " QUADIR ,Counter direction in quadrature decode mode" "Decreased,Increased" rbitfld.long 0x00 1. " TOFDIR ,TOF bit set status" "Bottom,Top" newline bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" if (((per.l.be(ad:0x41200000+0x10))&0x18)==0x00) group.long 0x84++0x03 line.long 0x00 "CONF,Configuration Register" bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" ",CH0,CH1,CH0/CH1,CH2,CH0/CH2,CH1/CH2,CH0/CH1/CH2,CH3,CH0/CH3,CH1/CH3,CH0/CH1/CH3,CH2/CH3,CH0/CH2/CH3,CH1/CH2/CH3,CH0/CH1/CH2/CH3" bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "High,Low" newline bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled" bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Disabled,Enabled" newline bitfld.long 0x00 16. " CSOT ,Counter start trigger" "Immediately,Rising edge" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "Paused,,,Continued" bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled" else group.long 0x84++0x03 line.long 0x00 "CONF,Configuration Register" rbitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" ",CH0,CH1,CH0/CH1,CH2,CH0/CH2,CH1/CH2,CH0/CH1/CH2,CH3,CH0/CH3,CH1/CH3,CH0/CH1/CH3,CH2/CH3,CH0/CH2/CH3,CH1/CH2/CH3,CH0/CH1/CH2/CH3" rbitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal" rbitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "High,Low" newline rbitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled" rbitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded" rbitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Disabled,Enabled" newline rbitfld.long 0x00 16. " CSOT ,Counter start trigger" "Immediately,Rising edge" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "Paused,,,Continued" bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled" endif endian.le width 0x0B tree.end tree "SEMA42 (Semaphores2)" base ad:0x411B0000 width 9. group.byte 0x0++0x03 line.byte 0x00 "GATE3,Gate Register 3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x01 "GATE2,Gate Register 2" bitfld.byte 0x01 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x02 "GATE1,Gate Register 1" bitfld.byte 0x02 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x03 "GATE0,Gate Register 0" bitfld.byte 0x03 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" group.byte 0x4++0x03 line.byte 0x00 "GATE7,Gate Register 7" bitfld.byte 0x00 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x01 "GATE6,Gate Register 6" bitfld.byte 0x01 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x02 "GATE5,Gate Register 5" bitfld.byte 0x02 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x03 "GATE4,Gate Register 4" bitfld.byte 0x03 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" group.byte 0x8++0x03 line.byte 0x00 "GATE11,Gate Register 11" bitfld.byte 0x00 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x01 "GATE10,Gate Register 10" bitfld.byte 0x01 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x02 "GATE9,Gate Register 9" bitfld.byte 0x02 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x03 "GATE8,Gate Register 8" bitfld.byte 0x03 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" group.byte 0xC++0x03 line.byte 0x00 "GATE15,Gate Register 15" bitfld.byte 0x00 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x01 "GATE14,Gate Register 14" bitfld.byte 0x01 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x02 "GATE13,Gate Register 13" bitfld.byte 0x02 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x03 "GATE12,Gate Register 12" bitfld.byte 0x03 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" rgroup.word 0x42++0x01 line.word 0x00 "RSTGT_R,Reset Gate Read Register" bitfld.word 0x00 14.--15. " ROZ ,ROZ" "0,1,2,3" bitfld.word 0x00 12.--13. " RSTGSM ,Reset gate finite state machine" "Idle,Waiting,Completed,?..." bitfld.word 0x00 8.--11. " RSTGMS ,Reset gate bus master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word.byte 0x00 0.--7. 1. " RSTGTN ,Reset gate number" wgroup.word 0x42++0x01 line.word 0x00 "RSTGT_W,Reset Gate Write Register" hexmask.word.byte 0x00 8.--15. 1. " RSTGDP ,Reset gate data pattern" hexmask.word.byte 0x00 0.--7. 1. " RSTGTN ,Reset gate number" width 0x0B tree.end tree.open "MU (Messaging Unit)" tree "MU0-A0" base ad:0x41440000 width 9. if (((per.l(ad:0x41440000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x41440000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x41440000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x41440000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x41440000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x41440000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x41440000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x41440000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree "MU0-A1" base ad:0x41450000 width 9. if (((per.l(ad:0x41450000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x41450000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x41450000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x41450000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x41450000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x41450000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x41450000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x41450000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree "MU0-A2" base ad:0x41460000 width 9. if (((per.l(ad:0x41460000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x41460000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x41460000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x41460000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x41460000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x41460000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x41460000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x41460000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree "MU0-A3" base ad:0x41470000 width 9. if (((per.l(ad:0x41470000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x41470000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x41470000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x41470000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x41470000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x41470000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x41470000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x41470000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree "MU0-B" base ad:0x41430000 width 9. if (((per.l(ad:0x41430000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "BTR0,Processor B Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "BTR0,Processor B Transmit Register 0" endif if (((per.l(ad:0x41430000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "BTR1,Processor B Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "BTR1,Processor B Transmit Register 1" endif if (((per.l(ad:0x41430000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "BTR2,Processor B Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "BTR2,Processor B Transmit Register 2" endif if (((per.l(ad:0x41430000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "BTR3,Processor B Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "BTR3,Processor B Transmit Register 3" endif newline if (((per.l(ad:0x41430000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "BRR0,Processor B Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "BRR0,Processor B Receive Register 0" in newline endif if (((per.l(ad:0x41430000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "BRR1,Processor B Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "BRR1,Processor B Receive Register 1" in newline endif if (((per.l(ad:0x41430000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "BRR2,Processor B Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "BRR2,Processor B Receive Register 2" in newline endif if (((per.l(ad:0x41430000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "BRR3,Processor B Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "BRR3,Processor B Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "BSR,Processor B Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor B general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor B general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor B general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor B general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor B receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor B receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor B receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor B receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor B transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor B transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor B transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor B transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 8. " FUP ,Processor B flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " ARS ,Processor A reset state" "No reset,Reset" bitfld.long 0x00 4. " EP ,Processor B-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor B-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor B-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor B-side flag 0" "0,1" line.long 0x04 "BCR,Processor B Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor B general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor B general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor B general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor B general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor B receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor B receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor B receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor B receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor B transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor B transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor B transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor B transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor B general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor B general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor B general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor B general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 4. " HRM ,Processor B hardware reset mask" "Not masked,Masked" newline bitfld.long 0x04 2. " BAF[2] ,Processor B to processor A flag 2" "Clear,Set" bitfld.long 0x04 1. " [1] ,Processor B to processor A flag 1" "Clear,Set" bitfld.long 0x04 0. " [0] ,Processor B to processor A flag 0" "Clear,Set" width 0x0B tree.end tree "MU1-A" base ad:0x41480000 width 9. if (((per.l(ad:0x41480000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x41480000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x41480000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x41480000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x41480000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x41480000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x41480000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x41480000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree.end tree "WDOG (Watchdog Timer)" base ad:0x41420000 width 7. group.long 0x00++0x0F line.long 0x00 "CS,Watchdog Control and Status Register" bitfld.long 0x00 15. " WIN ,Window mode enable" "Disabled,Enabled" eventfld.long 0x00 14. " FLG ,Watchdog interrupt flag" "Not occurred,Occurred" bitfld.long 0x00 13. " CMD32EN ,WDOG support for 32-bit enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " PRES ,Watchdog 256 prescaler enable" "Disabled,Enabled" rbitfld.long 0x00 11. " ULK ,Unlock status" "Locked,Unlocked" rbitfld.long 0x00 10. " RCS ,Reconfiguration success" "In progress,Succeeded" newline bitfld.long 0x00 8.--9. " CLK ,Watchdog counter clock source" "Bus clock,LPO clock,INTCLK,ERCLK" bitfld.long 0x00 7. " EN ,Watchdog counter enable" "Disabled,Enabled" bitfld.long 0x00 6. " INT ,Watchdog interrupt" "Disabled,Enabled" newline bitfld.long 0x00 5. " UPDATE ,Watchdog software reconfiguration without a reset allowance" "Not allowed,Allowed" bitfld.long 0x00 3.--4. " TST ,Fast test mode enable" "Disabled,User mode,Test mode/low byte,Test mode/high byte" bitfld.long 0x00 2. " DBG ,Debug mode enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " WAIT ,Wait mode enable" "Disabled,Enabled" bitfld.long 0x00 0. " STOP ,Stop mode enable" "Disabled,Enabled" line.long 0x04 "CNT,Watchdog Counter Register" hexmask.long.byte 0x04 8.--15. 1. " CNTHIGH ,High byte of the watchdog counter" hexmask.long.byte 0x04 0.--7. 1. " CNTLOW ,Low byte of the watchdog counter" line.long 0x08 "TOVAL,Watchdog Timeout Value Register" hexmask.long.byte 0x08 8.--15. 1. " TOVALHIGH ,High byte of the timeout value" hexmask.long.byte 0x08 0.--7. 1. " TOVALLOW ,Low byte of the timeout value" line.long 0x0C "WIN,Watchdog Window Register" hexmask.long.byte 0x0C 8.--15. 1. " WINHIGH ,High byte of watchdog window" hexmask.long.byte 0x0C 0.--7. 1. " WINLOW ,Low byte of watchdog window" width 0x0B tree.end tree "ASMC (Auxiliary System Mode Control)" base ad:0x41410000 width 10. rgroup.long 0x00++0x03 line.long 0x00 "SRS,System Reset Status Register" bitfld.long 0x00 12. " SACKERR ,Reset caused by peripheral failure to acknowledge attempt to enter stop mode" "Not occurred,Occurred" bitfld.long 0x00 10. " SW ,Reset caused by software setting of SYSRESETREQ bit" "Not occurred,Occurred" bitfld.long 0x00 9. " LOCKUP ,Reset caused by core LOCKUP event" "Not occurred,Occurred" bitfld.long 0x00 7. " POR ,Reset caused by power-on detection logic" "Not occurred,Occurred" newline bitfld.long 0x00 6. " RES ,Chip Reset caused by a source other than power-on detection logic" "Not occurred,Occurred" bitfld.long 0x00 5. " WDOG1 ,Reset caused by watchdog timer 1 timeout" "Not occurred,Occurred" bitfld.long 0x00 0. " WAKEUP ,Reset caused by LLWU module wakeup source" "Not occurred,Occurred" group.long 0x08++0x0B line.long 0x00 "PMPROT,Power Mode Protection Register" bitfld.long 0x00 7. " AHSRUN ,Allow high speed run mode" "Not allowed,Allowed" bitfld.long 0x00 5. " AVLP ,Allow very low power modes" "Not allowed,Allowed" bitfld.long 0x00 3. " ALLS ,Allow low-leakage stop mode" "Not allowed,Allowed" bitfld.long 0x00 1. " AVLLS ,Allow very-low-leakage stop mode" "Not allowed,Allowed" line.long 0x04 "PMCTRL,Power Mode Control Register" bitfld.long 0x04 5.--6. " RUNM ,Run mode control" "Normal,,Very-low-power,High speed" bitfld.long 0x04 0.--2. " STOPM ,Stop mode control" "Normal,,Very-low-power,Low-leakage,Very-low-leakage,?..." line.long 0x08 "STOPCTRL,Stop Control Register" bitfld.long 0x08 6.--7. " PSTOPO ,Partial stop option" "Normal,PSTOP1,PSTOP2,?..." rgroup.long 0x14++0x03 line.long 0x00 "PMSTAT,Power Mode Status Register" hexmask.long.byte 0x00 0.--7. 1. " PMSTAT ,Power mode status" rgroup.long 0xF0++0x07 "Time Stamp Timer Module (TSTMR)" line.long 0x00 "LOW,Time Stamp Timer Register Low" line.long 0x04 "HIGH,Time Stamp Timer Register High" width 0x0B tree.end tree "INTMUX (Interrupt Multiplexer)" base ad:0x41400000 width 14. group.long 0x0++0x03 "Channel 0" line.long 0x00 "CH0_CSR,Channel 0 Control Status Register" rbitfld.long 0x00 31. " IRQP ,Channel interrupt request pending" "Not pending,Pending" rbitfld.long 0x00 8.--11. " CHIN ,Channel instance number" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 4.--5. " IRQN ,Channel input number" "32 interrupt inputs,?..." newline bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND" bitfld.long 0x00 0. " RST ,Software reset" "No reset,Reset" rgroup.long (0x0+0x04)++0x03 line.long 0x00 "CH0_VEC,Channel 0 Vector Number Register" hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector number" newline group.long (0x0+0x10)++0x03 line.long 0x00 "CH0_IER_31_0,Channel 0 Interrupt Enable Register" bitfld.long 0x00 31. " INTE[31] ,Interrupt MU0_A0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Interrupt LPUART enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Interrupt LPIT enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Interrupt TPM enable" "Disabled,Enabled" rgroup.long (0x0+0x20)++0x03 line.long 0x00 "CH0_IPR_31_0,Channel 0 Interrupt Pending Register" bitfld.long 0x00 31. " INTP[31] ,Interrupt MU0_A0 pending" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 pending" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 pending" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 pending" "Not pending,Pending" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C pending" "Not pending,Pending" bitfld.long 0x00 7. " [7] ,Interrupt LPUART pending" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Interrupt LPIT pending" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Interrupt TPM pending" "Not pending,Pending" group.long 0x40++0x03 "Channel 1" line.long 0x00 "CH1_CSR,Channel 1 Control Status Register" rbitfld.long 0x00 31. " IRQP ,Channel interrupt request pending" "Not pending,Pending" rbitfld.long 0x00 8.--11. " CHIN ,Channel instance number" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 4.--5. " IRQN ,Channel input number" "32 interrupt inputs,?..." newline bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND" bitfld.long 0x00 0. " RST ,Software reset" "No reset,Reset" rgroup.long (0x40+0x04)++0x03 line.long 0x00 "CH1_VEC,Channel 1 Vector Number Register" hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector number" newline group.long (0x40+0x10)++0x03 line.long 0x00 "CH1_IER_31_0,Channel 1 Interrupt Enable Register" bitfld.long 0x00 31. " INTE[31] ,Interrupt MU0_A0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Interrupt LPUART enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Interrupt LPIT enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Interrupt TPM enable" "Disabled,Enabled" rgroup.long (0x40+0x20)++0x03 line.long 0x00 "CH1_IPR_31_0,Channel 1 Interrupt Pending Register" bitfld.long 0x00 31. " INTP[31] ,Interrupt MU0_A0 pending" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 pending" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 pending" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 pending" "Not pending,Pending" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C pending" "Not pending,Pending" bitfld.long 0x00 7. " [7] ,Interrupt LPUART pending" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Interrupt LPIT pending" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Interrupt TPM pending" "Not pending,Pending" group.long 0x80++0x03 "Channel 2" line.long 0x00 "CH2_CSR,Channel 2 Control Status Register" rbitfld.long 0x00 31. " IRQP ,Channel interrupt request pending" "Not pending,Pending" rbitfld.long 0x00 8.--11. " CHIN ,Channel instance number" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 4.--5. " IRQN ,Channel input number" "32 interrupt inputs,?..." newline bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND" bitfld.long 0x00 0. " RST ,Software reset" "No reset,Reset" rgroup.long (0x80+0x04)++0x03 line.long 0x00 "CH2_VEC,Channel 2 Vector Number Register" hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector number" newline group.long (0x80+0x10)++0x03 line.long 0x00 "CH2_IER_31_0,Channel 2 Interrupt Enable Register" bitfld.long 0x00 31. " INTE[31] ,Interrupt MU0_A0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Interrupt LPUART enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Interrupt LPIT enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Interrupt TPM enable" "Disabled,Enabled" rgroup.long (0x80+0x20)++0x03 line.long 0x00 "CH2_IPR_31_0,Channel 2 Interrupt Pending Register" bitfld.long 0x00 31. " INTP[31] ,Interrupt MU0_A0 pending" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 pending" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 pending" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 pending" "Not pending,Pending" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C pending" "Not pending,Pending" bitfld.long 0x00 7. " [7] ,Interrupt LPUART pending" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Interrupt LPIT pending" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Interrupt TPM pending" "Not pending,Pending" group.long 0xC0++0x03 "Channel 3" line.long 0x00 "CH3_CSR,Channel 3 Control Status Register" rbitfld.long 0x00 31. " IRQP ,Channel interrupt request pending" "Not pending,Pending" rbitfld.long 0x00 8.--11. " CHIN ,Channel instance number" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 4.--5. " IRQN ,Channel input number" "32 interrupt inputs,?..." newline bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND" bitfld.long 0x00 0. " RST ,Software reset" "No reset,Reset" rgroup.long (0xC0+0x04)++0x03 line.long 0x00 "CH3_VEC,Channel 3 Vector Number Register" hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector number" newline group.long (0xC0+0x10)++0x03 line.long 0x00 "CH3_IER_31_0,Channel 3 Interrupt Enable Register" bitfld.long 0x00 31. " INTE[31] ,Interrupt MU0_A0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Interrupt LPUART enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Interrupt LPIT enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Interrupt TPM enable" "Disabled,Enabled" rgroup.long (0xC0+0x20)++0x03 line.long 0x00 "CH3_IPR_31_0,Channel 3 Interrupt Pending Register" bitfld.long 0x00 31. " INTP[31] ,Interrupt MU0_A0 pending" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 pending" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 pending" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 pending" "Not pending,Pending" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C pending" "Not pending,Pending" bitfld.long 0x00 7. " [7] ,Interrupt LPUART pending" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Interrupt LPIT pending" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Interrupt TPM pending" "Not pending,Pending" group.long 0x100++0x03 "Channel 4" line.long 0x00 "CH4_CSR,Channel 4 Control Status Register" rbitfld.long 0x00 31. " IRQP ,Channel interrupt request pending" "Not pending,Pending" rbitfld.long 0x00 8.--11. " CHIN ,Channel instance number" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 4.--5. " IRQN ,Channel input number" "32 interrupt inputs,?..." newline bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND" bitfld.long 0x00 0. " RST ,Software reset" "No reset,Reset" rgroup.long (0x100+0x04)++0x03 line.long 0x00 "CH4_VEC,Channel 4 Vector Number Register" hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector number" newline group.long (0x100+0x10)++0x03 line.long 0x00 "CH4_IER_31_0,Channel 4 Interrupt Enable Register" bitfld.long 0x00 31. " INTE[31] ,Interrupt MU0_A0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Interrupt LPUART enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Interrupt LPIT enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Interrupt TPM enable" "Disabled,Enabled" rgroup.long (0x100+0x20)++0x03 line.long 0x00 "CH4_IPR_31_0,Channel 4 Interrupt Pending Register" bitfld.long 0x00 31. " INTP[31] ,Interrupt MU0_A0 pending" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 pending" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 pending" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 pending" "Not pending,Pending" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C pending" "Not pending,Pending" bitfld.long 0x00 7. " [7] ,Interrupt LPUART pending" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Interrupt LPIT pending" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Interrupt TPM pending" "Not pending,Pending" group.long 0x140++0x03 "Channel 5" line.long 0x00 "CH5_CSR,Channel 5 Control Status Register" rbitfld.long 0x00 31. " IRQP ,Channel interrupt request pending" "Not pending,Pending" rbitfld.long 0x00 8.--11. " CHIN ,Channel instance number" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 4.--5. " IRQN ,Channel input number" "32 interrupt inputs,?..." newline bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND" bitfld.long 0x00 0. " RST ,Software reset" "No reset,Reset" rgroup.long (0x140+0x04)++0x03 line.long 0x00 "CH5_VEC,Channel 5 Vector Number Register" hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector number" newline group.long (0x140+0x10)++0x03 line.long 0x00 "CH5_IER_31_0,Channel 5 Interrupt Enable Register" bitfld.long 0x00 31. " INTE[31] ,Interrupt MU0_A0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Interrupt LPUART enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Interrupt LPIT enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Interrupt TPM enable" "Disabled,Enabled" rgroup.long (0x140+0x20)++0x03 line.long 0x00 "CH5_IPR_31_0,Channel 5 Interrupt Pending Register" bitfld.long 0x00 31. " INTP[31] ,Interrupt MU0_A0 pending" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 pending" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 pending" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 pending" "Not pending,Pending" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C pending" "Not pending,Pending" bitfld.long 0x00 7. " [7] ,Interrupt LPUART pending" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Interrupt LPIT pending" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Interrupt TPM pending" "Not pending,Pending" group.long 0x180++0x03 "Channel 6" line.long 0x00 "CH6_CSR,Channel 6 Control Status Register" rbitfld.long 0x00 31. " IRQP ,Channel interrupt request pending" "Not pending,Pending" rbitfld.long 0x00 8.--11. " CHIN ,Channel instance number" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 4.--5. " IRQN ,Channel input number" "32 interrupt inputs,?..." newline bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND" bitfld.long 0x00 0. " RST ,Software reset" "No reset,Reset" rgroup.long (0x180+0x04)++0x03 line.long 0x00 "CH6_VEC,Channel 6 Vector Number Register" hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector number" newline group.long (0x180+0x10)++0x03 line.long 0x00 "CH6_IER_31_0,Channel 6 Interrupt Enable Register" bitfld.long 0x00 31. " INTE[31] ,Interrupt MU0_A0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Interrupt LPUART enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Interrupt LPIT enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Interrupt TPM enable" "Disabled,Enabled" rgroup.long (0x180+0x20)++0x03 line.long 0x00 "CH6_IPR_31_0,Channel 6 Interrupt Pending Register" bitfld.long 0x00 31. " INTP[31] ,Interrupt MU0_A0 pending" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 pending" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 pending" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 pending" "Not pending,Pending" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C pending" "Not pending,Pending" bitfld.long 0x00 7. " [7] ,Interrupt LPUART pending" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Interrupt LPIT pending" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Interrupt TPM pending" "Not pending,Pending" group.long 0x1C0++0x03 "Channel 7" line.long 0x00 "CH7_CSR,Channel 7 Control Status Register" rbitfld.long 0x00 31. " IRQP ,Channel interrupt request pending" "Not pending,Pending" rbitfld.long 0x00 8.--11. " CHIN ,Channel instance number" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 4.--5. " IRQN ,Channel input number" "32 interrupt inputs,?..." newline bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND" bitfld.long 0x00 0. " RST ,Software reset" "No reset,Reset" rgroup.long (0x1C0+0x04)++0x03 line.long 0x00 "CH7_VEC,Channel 7 Vector Number Register" hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector number" newline group.long (0x1C0+0x10)++0x03 line.long 0x00 "CH7_IER_31_0,Channel 7 Interrupt Enable Register" bitfld.long 0x00 31. " INTE[31] ,Interrupt MU0_A0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Interrupt LPUART enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Interrupt LPIT enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Interrupt TPM enable" "Disabled,Enabled" rgroup.long (0x1C0+0x20)++0x03 line.long 0x00 "CH7_IPR_31_0,Channel 7 Interrupt Pending Register" bitfld.long 0x00 31. " INTP[31] ,Interrupt MU0_A0 pending" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 pending" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 pending" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 pending" "Not pending,Pending" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C pending" "Not pending,Pending" bitfld.long 0x00 7. " [7] ,Interrupt LPUART pending" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Interrupt LPIT pending" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Interrupt TPM pending" "Not pending,Pending" width 0x0B tree.end tree.end elif (cpuis("IMX8DX")||cpuis("IMX8DXP")||cpuis("IMX8QXP")) tree.open "CM4 (ARM Cortex-M4 Subsystem)" ; tree "LMEM (Local Memory Controller)" ; base ad:0x00 ; %include imx8x/lmem.ph ad:0x00 ; tree.end tree "MCM (Miscellaneous Control Module)" base ad:0xE0080000 width 7. rgroup.word 0x08++0x03 line.word 0x00 "PLASC,Crossbar Switch Slave Configuration" bitfld.word 0x00 7. " ASC[7] ,Bus slave connection to AXBS input port 7" "Absent,Present" bitfld.word 0x00 6. " [6] ,Bus slave connection to AXBS input port 6" "Absent,Present" bitfld.word 0x00 5. " [5] ,Bus slave connection to AXBS input port 5" "Absent,Present" bitfld.word 0x00 4. " [4] ,Bus slave connection to AXBS input port 4" "Absent,Present" newline bitfld.word 0x00 3. " [3] ,Bus slave connection to AXBS input port 3" "Absent,Present" bitfld.word 0x00 2. " [2] ,Bus slave connection to AXBS input port 2" "Absent,Present" bitfld.word 0x00 1. " [1] ,Bus slave connection to AXBS input port 1" "Absent,Present" bitfld.word 0x00 0. " [0] ,Bus slave connection to AXBS input port 0" "Absent,Present" line.word 0x02 "PLAMC,Crossbar Switch Master Configuration" bitfld.word 0x02 7. " AMC[7] ,Bus master connection to AXBS input port 7" "Absent,Present" bitfld.word 0x02 6. " [6] ,Bus master connection to AXBS input port 6" "Absent,Present" bitfld.word 0x02 5. " [5] ,Bus master connection to AXBS input port 5" "Absent,Present" bitfld.word 0x02 4. " [4] ,Bus master connection to AXBS input port 4" "Absent,Present" newline bitfld.word 0x02 3. " [3] ,Bus master connection to AXBS input port 3" "Absent,Present" bitfld.word 0x02 2. " [2] ,Bus master connection to AXBS input port 2" "Absent,Present" bitfld.word 0x02 1. " [1] ,Bus master connection to AXBS input port 1" "Absent,Present" bitfld.word 0x02 0. " [0] ,Bus master connection to AXBS input port 0" "Absent,Present" rgroup.long 0x20++0x0B line.long 0x00 "FADR,Fault Address Register" line.long 0x04 "FATR,Fault Attributes Register" bitfld.long 0x04 31. " BEOVR ,Bus error overrun" "No error,Error" bitfld.long 0x04 8.--11. " BEMN ,Bus error master number" ",1,?..." bitfld.long 0x04 7. " BEWT ,Bus error write" "Read,Write" newline bitfld.long 0x04 4.--5. " BESZ ,Bus error size" "8-bit,16-bit,32-bit,?..." bitfld.long 0x04 1. " BEMD ,Bus error privilege level" "User mode,Supervisor/privileged mode" bitfld.long 0x04 0. " BEDA ,Bus error access type" "Instruction,Data" line.long 0x08 "FDR,Fault Data Register" width 0x0B tree.end tree "LPI2C (Low-Power I2C Controller)" base ad:0x37230000 width 8. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number" line.long 0x04 "PARAM,Parameter Register" bitfld.long 0x04 8.--11. " MRXFIFO ,Master receive FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x04 0.--3. " MTXFIFO ,Master transmit FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" group.long 0x10++0x13 line.long 0x00 "MCR,Master Control Register" bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset" bitfld.long 0x00 3. " DBGEN ,Debug enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " MEN ,Master enable" "Disabled,Enabled" line.long 0x04 "MSR,Master Status Register" rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x04 24. " MBF ,Master busy flag" "Idle,Busy" eventfld.long 0x04 14. " DMF ,Data match flag" "Not received,Received" eventfld.long 0x04 13. " PLTF ,Pin low timeout flag" "Not occurred/disabled,Occurred" newline eventfld.long 0x04 12. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x04 11. " ALF ,Arbitration lost flag" "Not lost,Lost" eventfld.long 0x04 10. " NDF ,NACK detect flag" "Not detected,Detected" eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected" newline eventfld.long 0x04 8. " EPF ,End packet flag" "Not generated/Repeated,Generated/Repeated" rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "MIER,Master Interrupt Enable Register" bitfld.long 0x08 14. " DMIE ,Data match interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " PLTIE ,Pin low timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " FEIE ,FIFO error interrupt disable" "No,Yes" newline bitfld.long 0x08 11. " ALIE ,Arbitration lost interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " NDIE ,NACK detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " EPIE ,End packet interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "MDER,Master DMA Enable Register" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" line.long 0x10 "MCFGR0,Master Configuration Register 0" bitfld.long 0x10 9. " RDMO ,Receive data match only" "Stored,Discarded" bitfld.long 0x10 8. " CIRFIFO ,Circular FIFO enable" "Disabled,Enabled" bitfld.long 0x10 2. " HRSEL ,Host request select" "HREQ pin,Input trigger" newline bitfld.long 0x10 1. " HRPOL ,Host request polarity" "Active low,Active high" bitfld.long 0x10 0. " HREN ,Host request enable" "Disabled,Enabled" newline if (((per.l(ad:0x37230000+0x10))&0x01)==0x01) rgroup.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Disabled,,1st word = MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "SCL,SCL or SDA" newline bitfld.long 0x00 9. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "No effect,Enabled" bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" else group.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Disabled,,1st word = MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "On SCL low too long,On SCL or SDA low too long" newline bitfld.long 0x00 9. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "No effect,Enabled" bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" endif newline if ((((per.l(ad:0x37230000+0x10))&0x01)==0x00)||(((per.l(ad:0x37230000+0x14))&0x1000000)==0x00)) group.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" else rgroup.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" endif if (((per.l(ad:0x37230000+0x10))&0x01)==0x01) rgroup.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x58++0x03 line.long 0x00 "MFCR,Master FIFO Control Register" bitfld.long 0x00 16.--17. " RXWATER ,Receive FIFO watermark" "0,1,2,3" bitfld.long 0x00 0.--1. " TXWATER ,Transmit FIFO watermark" "0,1,2,3" rgroup.long 0x5C++0x03 line.long 0x00 "MFSR,Master FIFO Status Register" bitfld.long 0x00 16.--18. " RXCOUNT ,Receive FIFO count" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " TXCOUNT ,Transmit FIFO count" "0,1,2,3,4,5,6,7" newline wgroup.long 0x60++0x03 line.long 0x00 "MTDR,Master Transmit Data Register" bitfld.long 0x00 8.--10. " CMD ,Command data" "Transmit,Receive,Generate STOP,Receive and discard,START and transmit,START and transmit (NACK returned),START and transmit (high speed mode),START and transmit high speed mode (NACK returned)" newline hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data" newline hgroup.long 0x70++0x03 hide.long 0x00 "MRDR,Master Receive Data Register" in newline group.long 0x110++0x0F line.long 0x00 "SCR,Slave Control Register" bitfld.long 0x00 9. " RRF ,Receive FIFO reset" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Transmit FIFO reset" "No effect,Reset" bitfld.long 0x00 5. " FILTDZ ,Filter doze enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " FILTEN ,Filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " SEN ,Slave enable" "Disabled,Enabled" line.long 0x04 "SSR,Slave Status Register" rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x04 24. " SBF ,Slave busy flag" "Idle,Busy" rbitfld.long 0x04 15. " SARF ,SMBus alert response flag" "Not detected,Detected" rbitfld.long 0x04 14. " GCF ,General call flag" "Not detected,Detected" newline rbitfld.long 0x04 13. " AM1F ,Address match 1 flag" "Not matched,Matched" rbitfld.long 0x04 12. " AM0F ,Address match 0 flag" "Not matched,Matched" eventfld.long 0x04 11. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x04 10. " BEF ,Bit error flag" "No error,Error" newline eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected" eventfld.long 0x04 8. " RSF ,Repeated start flag" "Not detected,Detected" rbitfld.long 0x04 3. " TAF ,Transmit ACK flag" "Not required,Required" rbitfld.long 0x04 2. " AVF ,Address valid flag" "Invalid,Valid" newline rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "SIER,Slave Interrupt Enable Register" bitfld.long 0x08 15. " SARIE ,SMBus alert response interrupt enable" "Disabled,Enabled" bitfld.long 0x08 14. " GCIE ,General call interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " AM1F ,Address match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " AM0IE ,Address match 0 interrupt disable" "No,Yes" newline bitfld.long 0x08 11. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " BEIE ,Bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 8. " RSIE ,Repeated start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " TAIE ,Transmit ACK interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " AVIE ,Address valid interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "SDER,Slave DMA Enable Register" bitfld.long 0x0C 2. " AVDE ,Address valid DMA enable" "Disabled,Enabled" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" newline if (((per.l(ad:0x37230000+0x110))&0x01)==0x01) rgroup.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration match" "0 (7-bit),0 (10-bit),0 (7-bit) / 1 (7-bit),0 (10-bit) / 1 (10-bit),0 (7-bit) / 1 (10-bit),0 (10-bit) / 1 (7-bit),From 0 (7-bit) to 1 (7-bit),From 0 (10-bit) to 1 (10-bit)" bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" bitfld.long 0x00 12. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return data / clear RDF,Return address / clear AVF" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer,On TDR empty" bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration match" "0 (7-bit),0 (10-bit),0 (7-bit) / 1 (7-bit),0 (10-bit) / 1 (10-bit),0 (7-bit) / 1 (10-bit),0 (10-bit) / 1 (7-bit),From 0 (7-bit) to 1 (7-bit),From 0 (10-bit) to 1 (10-bit)" bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" bitfld.long 0x00 12. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return data / clear RDF,Return address / clear AVF" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer,On TDR empty" bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline if (((per.l(ad:0x37230000+0x110))&0x01)==0x01) rgroup.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" else group.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" endif rgroup.long 0x150++0x03 line.long 0x00 "SASR,Slave Address Status Register" bitfld.long 0x00 14. " ANV ,Address invalid" "No,Yes" hexmask.long.word 0x00 0.--10. 0x01 " RADDR ,Received address" if (((per.l(ad:0x37230000+0x124))&0x08)==0x08) group.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,NACK transmit" "ACK,NACK" else rgroup.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,NACK transmit" "ACK,NACK" endif wgroup.long 0x160++0x03 line.long 0x00 "STDR,Slave Transmit Data Register" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data" rgroup.long 0x170++0x03 line.long 0x00 "SRDR,Slave Receive Data Register" bitfld.long 0x00 15. " SOF ,Start of frame" "Not the first data word,First data word" bitfld.long 0x00 14. " RXEMPTY ,RX empty" "Not empty,Empty" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data receive" width 0x0B tree.end tree "LPIT" base ad:0x37210000 endian.be width 13. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.word 0x00 16.--31. 1. " FEATURE ,Feature number" hexmask.long.byte 0x00 8.--15. 1. " MINOR ,Minor version number" hexmask.long.byte 0x00 0.--7. 1. " MAJOR ,Major version number" line.long 0x04 "PARAM,Parameter Register" hexmask.long.byte 0x04 24.--31. 1. " CHANNEL ,Number of timer channels" hexmask.long.byte 0x04 16.--23. 1. " EXT_TRIG ,Number of external trigger inputs" group.long 0x08++0x03 line.long 0x00 "MCR,Module Control Register" bitfld.long 0x00 31. " M_CEN ,Module clock enable" "Disabled,Enabled" bitfld.long 0x00 30. " SW_RST ,Software reset bit" "No reset,Reset" bitfld.long 0x00 29. " DOZE_EN ,DOZE mode enable bit" "Disabled,Enabled" bitfld.long 0x00 28. " DBG_EN ,Debug enable bit" "Disabled,Enabled" if (((per.l.be(ad:0x37210000+0x08))&0x01)==0x01) group.long 0x0C++0x03 line.long 0x00 "MSR,Module Status Register" eventfld.long 0x00 31. " TIF0 ,Channel 0 timer interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 30. " TIF1 ,Channel 1 timer interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 29. " TIF2 ,Channel 2 timer interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 28. " TIF3 ,Channel 3 timer interrupt flag" "No interrupt,Interrupt" else rgroup.long 0x0C++0x03 line.long 0x00 "MSR,Module Status Register" bitfld.long 0x00 31. " TIF0 ,Channel 0 timer interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 30. " TIF1 ,Channel 1 timer interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 29. " TIF2 ,Channel 2 timer interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 28. " TIF3 ,Channel 3 timer interrupt flag" "No interrupt,Interrupt" endif group.long 0x10++0x03 line.long 0x00 "MIER,Module Interrupt Enable Register" bitfld.long 0x00 31. " TIE0 ,Channel 0 timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 30. " TIE1 ,Channel 1 timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 29. " TIE2 ,Channel 2 timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " TIE3 ,Channel 3 timer interrupt enable" "Disabled,Enabled" if (((per.l.be(ad:0x37210000+0x08))&0x01)==0x01) group.long 0x14++0x03 line.long 0x00 "TEN_SET/CLR,Set/Clear Timer Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " T_EN_0 ,Timer 0 enable" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " T_EN_1 ,Timer 1 enable" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x04 29. " T_EN_2 ,Timer 2 enable" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " T_EN_3 ,Timer 3 enable" "Disabled,Enabled" else rgroup.long 0x14++0x07 line.long 0x00 "SETTEN,Set Timer Enable Register" bitfld.long 0x00 31. " SET_T_EN_0 ,Set timer 0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " SET_T_EN_1 ,Set timer 1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " SET_T_EN_2 ,Set timer 2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " SET_T_EN_3 ,Set timer 3 enable" "Disabled,Enabled" line.long 0x04 "CLRTEN,Clear Timer Enable Register" bitfld.long 0x04 31. " CLR_T_EN_0 ,Clear timer 0 enable" "Disabled,Enabled" bitfld.long 0x04 30. " CLR_T_EN_1 ,Clear timer 1 enable" "Disabled,Enabled" bitfld.long 0x04 29. " CLR_T_EN_2 ,Clear timer 2 enable" "Disabled,Enabled" bitfld.long 0x04 28. " CLR_T_EN_3 ,Clear timer 3 enable" "Disabled,Enabled" endif if (((per.l.be(ad:0x37210000+0x08))&0x01)==0x01) group.long 0x20++0x03 line.long 0x00 "TVAL0,Timer Value Register" else rgroup.long 0x20++0x03 line.long 0x00 "TVAL0,Timer Value Register" endif rgroup.long (0x20+0x04)++0x03 line.long 0x00 "CVAL0,Current Timer Value Register" if (((per.l.be(ad:0x37210000+0x08))&0x01)==0x01) if (((per.l.be(ad:0x37210000+0x20+0x08))&0x01)==0x00) group.long (0x20+0x08)++0x03 line.long 0x00 "TCTRL0,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Immediately,Rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." else group.long (0x20+0x08)++0x03 line.long 0x00 "TCTRL0,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" rbitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." endif else rgroup.long (0x20+0x08)++0x03 line.long 0x00 "TCTRL0,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." endif if (((per.l.be(ad:0x37210000+0x08))&0x01)==0x01) group.long 0x30++0x03 line.long 0x00 "TVAL1,Timer Value Register" else rgroup.long 0x30++0x03 line.long 0x00 "TVAL1,Timer Value Register" endif rgroup.long (0x30+0x04)++0x03 line.long 0x00 "CVAL1,Current Timer Value Register" if (((per.l.be(ad:0x37210000+0x08))&0x01)==0x01) if (((per.l.be(ad:0x37210000+0x30+0x08))&0x01)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "TCTRL1,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Immediately,Rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." else group.long (0x30+0x08)++0x03 line.long 0x00 "TCTRL1,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" rbitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." endif else rgroup.long (0x30+0x08)++0x03 line.long 0x00 "TCTRL1,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." endif if (((per.l.be(ad:0x37210000+0x08))&0x01)==0x01) group.long 0x40++0x03 line.long 0x00 "TVAL2,Timer Value Register" else rgroup.long 0x40++0x03 line.long 0x00 "TVAL2,Timer Value Register" endif rgroup.long (0x40+0x04)++0x03 line.long 0x00 "CVAL2,Current Timer Value Register" if (((per.l.be(ad:0x37210000+0x08))&0x01)==0x01) if (((per.l.be(ad:0x37210000+0x40+0x08))&0x01)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "TCTRL2,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Immediately,Rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." else group.long (0x40+0x08)++0x03 line.long 0x00 "TCTRL2,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" rbitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." endif else rgroup.long (0x40+0x08)++0x03 line.long 0x00 "TCTRL2,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." endif if (((per.l.be(ad:0x37210000+0x08))&0x01)==0x01) group.long 0x50++0x03 line.long 0x00 "TVAL3,Timer Value Register" else rgroup.long 0x50++0x03 line.long 0x00 "TVAL3,Timer Value Register" endif rgroup.long (0x50+0x04)++0x03 line.long 0x00 "CVAL3,Current Timer Value Register" if (((per.l.be(ad:0x37210000+0x08))&0x01)==0x01) if (((per.l.be(ad:0x37210000+0x50+0x08))&0x01)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "TCTRL3,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Immediately,Rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." else group.long (0x50+0x08)++0x03 line.long 0x00 "TCTRL3,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" rbitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." endif else rgroup.long (0x50+0x08)++0x03 line.long 0x00 "TCTRL3,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." endif endian.le width 0x0B tree.end tree "LPUART (Low Power Universal Asynchronous Receiver/Transmitter)" base ad:0x37220000 width 8. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature identification number" line.long 0x04 "PARAM,Parameter Register" hexmask.long.byte 0x04 8.--15. 1. " RXFIFO ,Receive FIFO size" hexmask.long.byte 0x04 0.--7. 1. " TXFIFO ,Transmit FIFO size" group.long 0x08++0x03 line.long 0x00 "GLOBAL,Global Register" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" if (((per.l(ad:0x37220000+0x18))&0xC0000)==0x00) group.long 0x0C++0x03 line.long 0x00 "PINCFG,Pin Configuration Register" bitfld.long 0x00 0.--1. " TRGSEL ,Trigger select" "Disabled,Instead RX in,Instead CTS in,TX out modulation" else rgroup.long 0x0C++0x03 line.long 0x00 "PINCFG,Pin Configuration Register" bitfld.long 0x00 0.--1. " TRGSEL ,Trigger select" "Disabled,Instead RX in,Instead CTS in,TX out modulation" endif group.long 0x10++0x07 line.long 0x00 "BAUD,Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" bitfld.long 0x00 29. " M10 ,10-bit mode select" "7/8/9 bit,10 bit" newline bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" "16x,,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 20. " RIDMAE ,Receiver idle DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " SBNS ,Stop bit number select" "One,Two" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" bitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" bitfld.long 0x04 26. " BRK13 ,Break character generation length" "9-13 bit,12-15 bit" newline bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" newline eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" newline if (((per.l(ad:0x37220000+0x18))&0xC0000)==0x00) if ((per.b(ad:0x37220000+0x18)&0x08)==0x08) group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" newline bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,LPUART in Doze mode enabled" "LPUART enabled,LPUART disabled" newline bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" else group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" newline bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,LPUART in Doze mode enabled" "LPUART enabled,LPUART disabled" newline bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif else group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" rbitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" rbitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" rbitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline rbitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" rbitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline rbitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" rbitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" newline rbitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" rbitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" rbitfld.long 0x00 6. " DOZEEN ,LPUART in Doze mode enabled" "LPUART enabled,LPUART disabled" newline rbitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" rbitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" rbitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline rbitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" rbitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" rbitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif group.long 0x1C++0x07 line.long 0x00 "DATA,Data Register" rbitfld.long 0x00 15. " NOISY ,Current received dataword noise" "Not noisy,Noisy" rbitfld.long 0x00 14. " PARITYE ,Current received dataword parity error" "No error,Error" bitfld.long 0x00 13. " FRETSC ,Current received dataword frame error/Transmit special character" "No error/Normal character,Error/Special character" newline rbitfld.long 0x00 12. " RXEMPT ,Receive buffer empty" "Not empty,Empty" rbitfld.long 0x00 11. " IDLINE ,Receiver line idle status before receiving current character" "Not idle,Idle" newline bitfld.long 0x00 9. " R9T9 ,Read receive data buffer 9 or write transmit data buffer 9" "Low,High" bitfld.long 0x00 8. " R8T8 ,Read receive data buffer 8 or write transmit data buffer 8" "Low,High" bitfld.long 0x00 7. " R7T7 ,Read receive data buffer 7 or write transmit data buffer 7" "Low,High" newline bitfld.long 0x00 6. " R6T6 ,Read receive data buffer 6 or write transmit data buffer 6" "Low,High" bitfld.long 0x00 5. " R5T5 ,Read receive data buffer 5 or write transmit data buffer 5" "Low,High" bitfld.long 0x00 4. " R4T4 ,Read receive data buffer 4 or write transmit data buffer 4" "Low,High" newline bitfld.long 0x00 3. " R3T3 ,Read receive data buffer 3 or write transmit data buffer 3" "Low,High" bitfld.long 0x00 2. " R2T2 ,Read receive data buffer 2 or write transmit data buffer 2" "Low,High" bitfld.long 0x00 1. " R1T1 ,Read receive data buffer 1 or write transmit data buffer 1" "Low,High" newline bitfld.long 0x00 0. " R0T0 ,Read receive data buffer 0 or write transmit data buffer 0" "Low,High" line.long 0x04 "MATCH,Match Address Register" hexmask.long.word 0x04 16.--25. 0x01 " MA2 ,Match address 2" hexmask.long.word 0x04 0.--9. 0x01 " MA1 ,Match address 1" if (((per.l(ad:0x37220000+0x18))&0xC0000)==0x00) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" bitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" newline bitfld.long 0x00 8.--12. " RTSWATER ,Receive RTS configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" elif (((per.l(ad:0x37220000+0x18))&0xC0000)==0x40000) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" newline rbitfld.long 0x00 8.--12. " RTSWATER ,Receive RTS configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" rbitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" elif (((per.l(ad:0x37220000+0x18))&0xC0000)==0x80000) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" newline bitfld.long 0x00 8.--12. " RTSWATER ,Receive RTS configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" rbitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline rbitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" newline rbitfld.long 0x00 8.--12. " RTSWATER ,Receive RTS configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" rbitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" rbitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline rbitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" endif if ((((per.l(ad:0x37220000+0x18))&0xC0000)==0x00)&&(((per.l(ad:0x37220000+0x28))&0xC00000)==0xC00000)) group.long 0x28++0x03 line.long 0x00 "FIFO,FIFO Register" rbitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO empty" "Not empty,Empty" rbitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO empty" "Not empty,Empty" eventfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" eventfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" newline rbitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" else rgroup.long 0x28++0x03 line.long 0x00 "FIFO,FIFO Register" bitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" bitfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" endif if (((per.l(ad:0x37220000+0x18))&0x80000)==0x80000) rgroup.long 0x2C++0x03 line.long 0x00 "WATER,Watermark Register" bitfld.long 0x00 24.--29. " RXCOUNT ,Receive counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--20. " RXWATER ,Receive watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " TXCOUNT ,Transmit counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--4. " TXWATER ,Transmit watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x2C++0x03 line.long 0x00 "WATER,Watermark Register" rbitfld.long 0x00 24.--29. " RXCOUNT ,Receive counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--20. " RXWATER ,Receive watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " TXCOUNT ,Transmit counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--4. " TXWATER ,Transmit watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif width 0x0B tree.end tree "RGPIO (Rapid General-Purpose Input and Output)" base ad:0x370F0000 width 6. group.long 0x00++0x03 line.long 0x00 "PDOR,Port Data Output Register" bitfld.long 0x00 31. " PDO[31] ,Port data output pin 31" "Low,High" bitfld.long 0x00 30. " [30] ,Port data output pin 30" "Low,High" bitfld.long 0x00 29. " [29] ,Port data output pin 29" "Low,High" bitfld.long 0x00 28. " [28] ,Port data output pin 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,Port data output pin 27" "Low,High" bitfld.long 0x00 26. " [26] ,Port data output pin 26" "Low,High" bitfld.long 0x00 25. " [25] ,Port data output pin 25" "Low,High" bitfld.long 0x00 24. " [24] ,Port data output pin 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,Port data output pin 23" "Low,High" bitfld.long 0x00 22. " [22] ,Port data output pin 22" "Low,High" bitfld.long 0x00 21. " [21] ,Port data output pin 21" "Low,High" bitfld.long 0x00 20. " [20] ,Port data output pin 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,Port data output pin 19" "Low,High" bitfld.long 0x00 18. " [18] ,Port data output pin 18" "Low,High" bitfld.long 0x00 17. " [17] ,Port data output pin 17" "Low,High" bitfld.long 0x00 16. " [16] ,Port data output pin 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,Port data output pin 15" "Low,High" bitfld.long 0x00 14. " [14] ,Port data output pin 14" "Low,High" bitfld.long 0x00 13. " [13] ,Port data output pin 13" "Low,High" bitfld.long 0x00 12. " [12] ,Port data output pin 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,Port data output pin 11" "Low,High" bitfld.long 0x00 10. " [10] ,Port data output pin 10" "Low,High" bitfld.long 0x00 9. " [9] ,Port data output pin 9" "Low,High" bitfld.long 0x00 8. " [8] ,Port data output pin 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,Port data output pin 7" "Low,High" bitfld.long 0x00 6. " [6] ,Port data output pin 6" "Low,High" bitfld.long 0x00 5. " [5] ,Port data output pin 5" "Low,High" bitfld.long 0x00 4. " [4] ,Port data output pin 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,Port data output pin 3" "Low,High" bitfld.long 0x00 2. " [2] ,Port data output pin 2" "Low,High" bitfld.long 0x00 1. " [1] ,Port data output pin 1" "Low,High" bitfld.long 0x00 0. " [0] ,Port data output pin 0" "Low,High" wgroup.long 0x04++0x0B line.long 0x00 "PSOR,Port Set Output Register" bitfld.long 0x00 31. " PTSO[31] ,Port set output pin 31" "No effect,Set" bitfld.long 0x00 30. " [30] ,Port set output pin 30" "No effect,Set" bitfld.long 0x00 29. " [29] ,Port set output pin 29" "No effect,Set" bitfld.long 0x00 28. " [28] ,Port set output pin 28" "No effect,Set" newline bitfld.long 0x00 27. " [27] ,Port set output pin 27" "No effect,Set" bitfld.long 0x00 26. " [26] ,Port set output pin 26" "No effect,Set" bitfld.long 0x00 25. " [25] ,Port set output pin 25" "No effect,Set" bitfld.long 0x00 24. " [24] ,Port set output pin 24" "No effect,Set" newline bitfld.long 0x00 23. " [23] ,Port set output pin 23" "No effect,Set" bitfld.long 0x00 22. " [22] ,Port set output pin 22" "No effect,Set" bitfld.long 0x00 21. " [21] ,Port set output pin 21" "No effect,Set" bitfld.long 0x00 20. " [20] ,Port set output pin 20" "No effect,Set" newline bitfld.long 0x00 19. " [19] ,Port set output pin 19" "No effect,Set" bitfld.long 0x00 18. " [18] ,Port set output pin 18" "No effect,Set" bitfld.long 0x00 17. " [17] ,Port set output pin 17" "No effect,Set" bitfld.long 0x00 16. " [16] ,Port set output pin 16" "No effect,Set" newline bitfld.long 0x00 15. " [15] ,Port set output pin 15" "No effect,Set" bitfld.long 0x00 14. " [14] ,Port set output pin 14" "No effect,Set" bitfld.long 0x00 13. " [13] ,Port set output pin 13" "No effect,Set" bitfld.long 0x00 12. " [12] ,Port set output pin 12" "No effect,Set" newline bitfld.long 0x00 11. " [11] ,Port set output pin 11" "No effect,Set" bitfld.long 0x00 10. " [10] ,Port set output pin 10" "No effect,Set" bitfld.long 0x00 9. " [9] ,Port set output pin 9" "No effect,Set" bitfld.long 0x00 8. " [8] ,Port set output pin 8" "No effect,Set" newline bitfld.long 0x00 7. " [7] ,Port set output pin 7" "No effect,Set" bitfld.long 0x00 6. " [6] ,Port set output pin 6" "No effect,Set" bitfld.long 0x00 5. " [5] ,Port set output pin 5" "No effect,Set" bitfld.long 0x00 4. " [4] ,Port set output pin 4" "No effect,Set" newline bitfld.long 0x00 3. " [3] ,Port set output pin 3" "No effect,Set" bitfld.long 0x00 2. " [2] ,Port set output pin 2" "No effect,Set" bitfld.long 0x00 1. " [1] ,Port set output pin 1" "No effect,Set" bitfld.long 0x00 0. " [0] ,Port set output pin 0" "No effect,Set" line.long 0x04 "PCOR,Port Clear Output Register" bitfld.long 0x04 31. " PTCO[31] ,Port clear output pin 31" "No effect,Clear" bitfld.long 0x04 30. " [30] ,Port clear output pin 30" "No effect,Clear" bitfld.long 0x04 29. " [29] ,Port clear output pin 29" "No effect,Clear" bitfld.long 0x04 28. " [28] ,Port clear output pin 28" "No effect,Clear" newline bitfld.long 0x04 27. " [27] ,Port clear output pin 27" "No effect,Clear" bitfld.long 0x04 26. " [26] ,Port clear output pin 26" "No effect,Clear" bitfld.long 0x04 25. " [25] ,Port clear output pin 25" "No effect,Clear" bitfld.long 0x04 24. " [24] ,Port clear output pin 24" "No effect,Clear" newline bitfld.long 0x04 23. " [23] ,Port clear output pin 23" "No effect,Clear" bitfld.long 0x04 22. " [22] ,Port clear output pin 22" "No effect,Clear" bitfld.long 0x04 21. " [21] ,Port clear output pin 21" "No effect,Clear" bitfld.long 0x04 20. " [20] ,Port clear output pin 20" "No effect,Clear" newline bitfld.long 0x04 19. " [19] ,Port clear output pin 19" "No effect,Clear" bitfld.long 0x04 18. " [18] ,Port clear output pin 18" "No effect,Clear" bitfld.long 0x04 17. " [17] ,Port clear output pin 17" "No effect,Clear" bitfld.long 0x04 16. " [16] ,Port clear output pin 16" "No effect,Clear" newline bitfld.long 0x04 15. " [15] ,Port clear output pin 15" "No effect,Clear" bitfld.long 0x04 14. " [14] ,Port clear output pin 14" "No effect,Clear" bitfld.long 0x04 13. " [13] ,Port clear output pin 13" "No effect,Clear" bitfld.long 0x04 12. " [12] ,Port clear output pin 12" "No effect,Clear" newline bitfld.long 0x04 11. " [11] ,Port clear output pin 11" "No effect,Clear" bitfld.long 0x04 10. " [10] ,Port clear output pin 10" "No effect,Clear" bitfld.long 0x04 9. " [9] ,Port clear output pin 9" "No effect,Clear" bitfld.long 0x04 8. " [8] ,Port clear output pin 8" "No effect,Clear" newline bitfld.long 0x04 7. " [7] ,Port clear output pin 7" "No effect,Clear" bitfld.long 0x04 6. " [6] ,Port clear output pin 6" "No effect,Clear" bitfld.long 0x04 5. " [5] ,Port clear output pin 5" "No effect,Clear" bitfld.long 0x04 4. " [4] ,Port clear output pin 4" "No effect,Clear" newline bitfld.long 0x04 3. " [3] ,Port clear output pin 3" "No effect,Clear" bitfld.long 0x04 2. " [2] ,Port clear output pin 2" "No effect,Clear" bitfld.long 0x04 1. " [1] ,Port clear output pin 1" "No effect,Clear" bitfld.long 0x04 0. " [0] ,Port clear output pin 0" "No effect,Clear" line.long 0x08 "PTOR,Port Toggle Output Register" bitfld.long 0x08 31. " PTTO[31] ,Port toggle output pin 31" "No effect,Toggled" bitfld.long 0x08 30. " [30] ,Port toggle output pin 30" "No effect,Toggled" bitfld.long 0x08 29. " [29] ,Port toggle output pin 29" "No effect,Toggled" bitfld.long 0x08 28. " [28] ,Port toggle output pin 28" "No effect,Toggled" newline bitfld.long 0x08 27. " [27] ,Port toggle output pin 27" "No effect,Toggled" bitfld.long 0x08 26. " [26] ,Port toggle output pin 26" "No effect,Toggled" bitfld.long 0x08 25. " [25] ,Port toggle output pin 25" "No effect,Toggled" bitfld.long 0x08 24. " [24] ,Port toggle output pin 24" "No effect,Toggled" newline bitfld.long 0x08 23. " [23] ,Port toggle output pin 23" "No effect,Toggled" bitfld.long 0x08 22. " [22] ,Port toggle output pin 22" "No effect,Toggled" bitfld.long 0x08 21. " [21] ,Port toggle output pin 21" "No effect,Toggled" bitfld.long 0x08 20. " [20] ,Port toggle output pin 20" "No effect,Toggled" newline bitfld.long 0x08 19. " [19] ,Port toggle output pin 19" "No effect,Toggled" bitfld.long 0x08 18. " [18] ,Port toggle output pin 18" "No effect,Toggled" bitfld.long 0x08 17. " [17] ,Port toggle output pin 17" "No effect,Toggled" bitfld.long 0x08 16. " [16] ,Port toggle output pin 16" "No effect,Toggled" newline bitfld.long 0x08 15. " [15] ,Port toggle output pin 15" "No effect,Toggled" bitfld.long 0x08 14. " [14] ,Port toggle output pin 14" "No effect,Toggled" bitfld.long 0x08 13. " [13] ,Port toggle output pin 13" "No effect,Toggled" bitfld.long 0x08 12. " [12] ,Port toggle output pin 12" "No effect,Toggled" newline bitfld.long 0x08 11. " [11] ,Port toggle output pin 11" "No effect,Toggled" bitfld.long 0x08 10. " [10] ,Port toggle output pin 10" "No effect,Toggled" bitfld.long 0x08 9. " [9] ,Port toggle output pin 9" "No effect,Toggled" bitfld.long 0x08 8. " [8] ,Port toggle output pin 8" "No effect,Toggled" newline bitfld.long 0x08 7. " [7] ,Port toggle output pin 7" "No effect,Toggled" bitfld.long 0x08 6. " [6] ,Port toggle output pin 6" "No effect,Toggled" bitfld.long 0x08 5. " [5] ,Port toggle output pin 5" "No effect,Toggled" bitfld.long 0x08 4. " [4] ,Port toggle output pin 4" "No effect,Toggled" newline bitfld.long 0x08 3. " [3] ,Port toggle output pin 3" "No effect,Toggled" bitfld.long 0x08 2. " [2] ,Port toggle output pin 2" "No effect,Toggled" bitfld.long 0x08 1. " [1] ,Port toggle output pin 1" "No effect,Toggled" bitfld.long 0x08 0. " [0] ,Port toggle output pin 0" "No effect,Toggled" rgroup.long 0x10++0x03 line.long 0x00 "PDIR,Port Data Input Register" bitfld.long 0x00 31. " PDI[31] ,Port data input pin 31" "Low/Not configured,High" bitfld.long 0x00 30. " [30] ,Port data input pin 30" "Low/Not configured,High" bitfld.long 0x00 29. " [29] ,Port data input pin 29" "Low/Not configured,High" bitfld.long 0x00 28. " [28] ,Port data input pin 28" "Low/Not configured,High" newline bitfld.long 0x00 27. " [27] ,Port data input pin 27" "Low/Not configured,High" bitfld.long 0x00 26. " [26] ,Port data input pin 26" "Low/Not configured,High" bitfld.long 0x00 25. " [25] ,Port data input pin 25" "Low/Not configured,High" bitfld.long 0x00 24. " [24] ,Port data input pin 24" "Low/Not configured,High" newline bitfld.long 0x00 23. " [23] ,Port data input pin 23" "Low/Not configured,High" bitfld.long 0x00 22. " [22] ,Port data input pin 22" "Low/Not configured,High" bitfld.long 0x00 21. " [21] ,Port data input pin 21" "Low/Not configured,High" bitfld.long 0x00 20. " [20] ,Port data input pin 20" "Low/Not configured,High" newline bitfld.long 0x00 19. " [19] ,Port data input pin 19" "Low/Not configured,High" bitfld.long 0x00 18. " [18] ,Port data input pin 18" "Low/Not configured,High" bitfld.long 0x00 17. " [17] ,Port data input pin 17" "Low/Not configured,High" bitfld.long 0x00 16. " [16] ,Port data input pin 16" "Low/Not configured,High" newline bitfld.long 0x00 15. " [15] ,Port data input pin 15" "Low/Not configured,High" bitfld.long 0x00 14. " [14] ,Port data input pin 14" "Low/Not configured,High" bitfld.long 0x00 13. " [13] ,Port data input pin 13" "Low/Not configured,High" bitfld.long 0x00 12. " [12] ,Port data input pin 12" "Low/Not configured,High" newline bitfld.long 0x00 11. " [11] ,Port data input pin 11" "Low/Not configured,High" bitfld.long 0x00 10. " [10] ,Port data input pin 10" "Low/Not configured,High" bitfld.long 0x00 9. " [9] ,Port data input pin 9" "Low/Not configured,High" bitfld.long 0x00 8. " [8] ,Port data input pin 8" "Low/Not configured,High" newline bitfld.long 0x00 7. " [7] ,Port data input pin 7" "Low/Not configured,High" bitfld.long 0x00 6. " [6] ,Port data input pin 6" "Low/Not configured,High" bitfld.long 0x00 5. " [5] ,Port data input pin 5" "Low/Not configured,High" bitfld.long 0x00 4. " [4] ,Port data input pin 4" "Low/Not configured,High" newline bitfld.long 0x00 3. " [3] ,Port data input pin 3" "Low/Not configured,High" bitfld.long 0x00 2. " [2] ,Port data input pin 2" "Low/Not configured,High" bitfld.long 0x00 1. " [1] ,Port data input pin 1" "Low/Not configured,High" bitfld.long 0x00 0. " [0] ,Port data input pin 0" "Low/Not configured,High" group.long 0x14++0x03 line.long 0x00 "PDDR,Port Data Direction Register" bitfld.long 0x00 31. " PDD[31] ,Port data direction" "Input,Output" bitfld.long 0x00 30. " [30] ,Port data direction pin 30" "Input,Output" bitfld.long 0x00 29. " [29] ,Port data direction pin 29" "Input,Output" bitfld.long 0x00 28. " [28] ,Port data direction pin 28" "Input,Output" newline bitfld.long 0x00 27. " [27] ,Port data direction pin 27" "Input,Output" bitfld.long 0x00 26. " [26] ,Port data direction pin 26" "Input,Output" bitfld.long 0x00 25. " [25] ,Port data direction pin 25" "Input,Output" bitfld.long 0x00 24. " [24] ,Port data direction pin 24" "Input,Output" newline bitfld.long 0x00 23. " [23] ,Port data direction pin 23" "Input,Output" bitfld.long 0x00 22. " [22] ,Port data direction pin 22" "Input,Output" bitfld.long 0x00 21. " [21] ,Port data direction pin 21" "Input,Output" bitfld.long 0x00 20. " [20] ,Port data direction pin 20" "Input,Output" newline bitfld.long 0x00 19. " [19] ,Port data direction pin 19" "Input,Output" bitfld.long 0x00 18. " [18] ,Port data direction pin 18" "Input,Output" bitfld.long 0x00 17. " [17] ,Port data direction pin 17" "Input,Output" bitfld.long 0x00 16. " [16] ,Port data direction pin 16" "Input,Output" newline bitfld.long 0x00 15. " [15] ,Port data direction pin 15" "Input,Output" bitfld.long 0x00 14. " [14] ,Port data direction pin 14" "Input,Output" bitfld.long 0x00 13. " [13] ,Port data direction pin 13" "Input,Output" bitfld.long 0x00 12. " [12] ,Port data direction pin 12" "Input,Output" newline bitfld.long 0x00 11. " [11] ,Port data direction pin 11" "Input,Output" bitfld.long 0x00 10. " [10] ,Port data direction pin 10" "Input,Output" bitfld.long 0x00 9. " [9] ,Port data direction pin 9" "Input,Output" bitfld.long 0x00 8. " [8] ,Port data direction pin 8" "Input,Output" newline bitfld.long 0x00 7. " [7] ,Port data direction pin 7" "Input,Output" bitfld.long 0x00 6. " [6] ,Port data direction pin 6" "Input,Output" bitfld.long 0x00 5. " [5] ,Port data direction pin 5" "Input,Output" bitfld.long 0x00 4. " [4] ,Port data direction pin 4" "Input,Output" newline bitfld.long 0x00 3. " [3] ,Port data direction pin 3" "Input,Output" bitfld.long 0x00 2. " [2] ,Port data direction pin 2" "Input,Output" bitfld.long 0x00 1. " [1] ,Port data direction pin 1" "Input,Output" bitfld.long 0x00 0. " [0] ,Port data direction pin 0" "Input,Output" width 0x0B tree.end tree "TPM" base ad:0x37200000 endian.be width 9. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature identification number" line.long 0x04 "PARAM,Parameter Register" hexmask.long.byte 0x04 16.--23. 1. " WIDTH ,Counter width" hexmask.long.byte 0x04 8.--15. 1. " TRIG ,Trigger count" hexmask.long.byte 0x04 0.--7. 1. " CHAN ,Channel count" group.long 0x08++0x03 line.long 0x00 "GLOBAL,TPM Global Register" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" if (((per.l.be(ad:0x37200000+0x10))&0x18)==0x00) group.long 0x10++0x03 line.long 0x00 "SC,Status And Control Register" bitfld.long 0x00 8. " DMA ,DMA enable" "Disabled,Enabled" eventfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-down counting" bitfld.long 0x00 3.--4. " CMOD ,Clock mode select" "Disabled,Counter clock,Clock rising edge,Input rising edge" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x10++0x03 line.long 0x00 "SC,Status And Control Register" bitfld.long 0x00 8. " DMA ,DMA enable" "Disabled,Enabled" eventfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-down counting" bitfld.long 0x00 3.--4. " CMOD ,Clock mode select" "Disabled,Counter clock,Clock rising edge,Input rising edge" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif group.long 0x14++0x0B line.long 0x00 "CNT,Counter Register" line.long 0x04 "MOD,Modulo Register" line.long 0x08 "STATUS,Capture And Compare Status Register" eventfld.long 0x08 8. " TOF ,Timer overflow flag" "No overflow,Overflow" eventfld.long 0x08 5. " CH5F ,Channel 5 flag" "Not occurred,Occurred" eventfld.long 0x08 4. " CH4F ,Channel 4 flag" "Not occurred,Occurred" newline eventfld.long 0x08 3. " CH3F ,Channel 3 flag" "Not occurred,Occurred" eventfld.long 0x08 2. " CH2F ,Channel 2 flag" "Not occurred,Occurred" eventfld.long 0x08 1. " CH1F ,Channel 1 flag" "Not occurred,Occurred" newline eventfld.long 0x08 0. " CH0F ,Channel 0 flag" "Not occurred,Occurred" if (((per.l.be(ad:0x37200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x37200000+0x20)&0x30)==0x00)) group.long 0x20++0x03 line.long 0x00 "C0SC,Channel 0 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x37200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x37200000+0x20)&0x30)==0x10)) group.long 0x20++0x03 line.long 0x00 "C0SC,Channel 0 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Not used,Toggle output,Clear output,Set output" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x37200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x37200000+0x20)&0x30)==0x20)) group.long 0x20++0x03 line.long 0x00 "C0SC,Channel 0 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x37200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x37200000+0x20)&0x30)==0x30)) group.long 0x20++0x03 line.long 0x00 "C0SC,Channel 0 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Pulse output high,Pulse output low,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x37200000+0x10)&0x20)==0x20)&&((per.l.be(ad:0x37200000+0x20)&0x30)==0x20)) group.long 0x20++0x03 line.long 0x00 "C0SC,Channel 0 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x20++0x03 hide.long 0x00 "C0SC,Channel 0 Status And Control Register" newline endif group.long (0x20+0x04)++0x03 line.long 0x00 "C0V,Channel 0 Value Register" if (((per.l.be(ad:0x37200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x37200000+0x28)&0x30)==0x00)) group.long 0x28++0x03 line.long 0x00 "C1SC,Channel 1 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x37200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x37200000+0x28)&0x30)==0x10)) group.long 0x28++0x03 line.long 0x00 "C1SC,Channel 1 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Not used,Toggle output,Clear output,Set output" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x37200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x37200000+0x28)&0x30)==0x20)) group.long 0x28++0x03 line.long 0x00 "C1SC,Channel 1 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x37200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x37200000+0x28)&0x30)==0x30)) group.long 0x28++0x03 line.long 0x00 "C1SC,Channel 1 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Pulse output high,Pulse output low,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x37200000+0x10)&0x20)==0x20)&&((per.l.be(ad:0x37200000+0x28)&0x30)==0x20)) group.long 0x28++0x03 line.long 0x00 "C1SC,Channel 1 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x28++0x03 hide.long 0x00 "C1SC,Channel 1 Status And Control Register" newline endif group.long (0x28+0x04)++0x03 line.long 0x00 "C1V,Channel 1 Value Register" if (((per.l.be(ad:0x37200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x37200000+0x30)&0x30)==0x00)) group.long 0x30++0x03 line.long 0x00 "C2SC,Channel 2 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 2 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x37200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x37200000+0x30)&0x30)==0x10)) group.long 0x30++0x03 line.long 0x00 "C2SC,Channel 2 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 2 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Not used,Toggle output,Clear output,Set output" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x37200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x37200000+0x30)&0x30)==0x20)) group.long 0x30++0x03 line.long 0x00 "C2SC,Channel 2 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 2 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x37200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x37200000+0x30)&0x30)==0x30)) group.long 0x30++0x03 line.long 0x00 "C2SC,Channel 2 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 2 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Pulse output high,Pulse output low,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x37200000+0x10)&0x20)==0x20)&&((per.l.be(ad:0x37200000+0x30)&0x30)==0x20)) group.long 0x30++0x03 line.long 0x00 "C2SC,Channel 2 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 2 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x30++0x03 hide.long 0x00 "C2SC,Channel 2 Status And Control Register" newline endif group.long (0x30+0x04)++0x03 line.long 0x00 "C2V,Channel 2 Value Register" if (((per.l.be(ad:0x37200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x37200000+0x38)&0x30)==0x00)) group.long 0x38++0x03 line.long 0x00 "C3SC,Channel 3 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 3 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x37200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x37200000+0x38)&0x30)==0x10)) group.long 0x38++0x03 line.long 0x00 "C3SC,Channel 3 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 3 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Not used,Toggle output,Clear output,Set output" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x37200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x37200000+0x38)&0x30)==0x20)) group.long 0x38++0x03 line.long 0x00 "C3SC,Channel 3 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 3 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x37200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x37200000+0x38)&0x30)==0x30)) group.long 0x38++0x03 line.long 0x00 "C3SC,Channel 3 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 3 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Pulse output high,Pulse output low,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x37200000+0x10)&0x20)==0x20)&&((per.l.be(ad:0x37200000+0x38)&0x30)==0x20)) group.long 0x38++0x03 line.long 0x00 "C3SC,Channel 3 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 3 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x38++0x03 hide.long 0x00 "C3SC,Channel 3 Status And Control Register" newline endif group.long (0x38+0x04)++0x03 line.long 0x00 "C3V,Channel 3 Value Register" if (((per.l.be(ad:0x37200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x37200000+0x40)&0x30)==0x00)) group.long 0x40++0x03 line.long 0x00 "C4SC,Channel 4 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x37200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x37200000+0x40)&0x30)==0x10)) group.long 0x40++0x03 line.long 0x00 "C4SC,Channel 4 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Not used,Toggle output,Clear output,Set output" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x37200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x37200000+0x40)&0x30)==0x20)) group.long 0x40++0x03 line.long 0x00 "C4SC,Channel 4 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x37200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x37200000+0x40)&0x30)==0x30)) group.long 0x40++0x03 line.long 0x00 "C4SC,Channel 4 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Pulse output high,Pulse output low,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x37200000+0x10)&0x20)==0x20)&&((per.l.be(ad:0x37200000+0x40)&0x30)==0x20)) group.long 0x40++0x03 line.long 0x00 "C4SC,Channel 4 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x40++0x03 hide.long 0x00 "C4SC,Channel 4 Status And Control Register" newline endif group.long (0x40+0x04)++0x03 line.long 0x00 "C4V,Channel 4 Value Register" if (((per.l.be(ad:0x37200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x37200000+0x48)&0x30)==0x00)) group.long 0x48++0x03 line.long 0x00 "C5SC,Channel 5 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 5 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x37200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x37200000+0x48)&0x30)==0x10)) group.long 0x48++0x03 line.long 0x00 "C5SC,Channel 5 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 5 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Not used,Toggle output,Clear output,Set output" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x37200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x37200000+0x48)&0x30)==0x20)) group.long 0x48++0x03 line.long 0x00 "C5SC,Channel 5 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 5 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x37200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x37200000+0x48)&0x30)==0x30)) group.long 0x48++0x03 line.long 0x00 "C5SC,Channel 5 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 5 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Pulse output high,Pulse output low,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x37200000+0x10)&0x20)==0x20)&&((per.l.be(ad:0x37200000+0x48)&0x30)==0x20)) group.long 0x48++0x03 line.long 0x00 "C5SC,Channel 5 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 5 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x48++0x03 hide.long 0x00 "C5SC,Channel 5 Status And Control Register" newline endif group.long (0x48+0x04)++0x03 line.long 0x00 "C5V,Channel 5 Value Register" group.long 0x64++0x03 line.long 0x00 "COMBINE,Combine Channel Register" bitfld.long 0x00 17. " COMSWAP2 ,Combine channels 4 and 5 swap" "Even,Odd" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" bitfld.long 0x00 9. " COMSWAP1 ,Combine channels 2 and 3 swap" "Even,Odd" newline bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" bitfld.long 0x00 1. " COMSWAP0 ,Combine channels 0 and 1 swap" "Even,Odd" bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" group.long 0x6C++0x07 line.long 0x00 "TRIG,Channel Trigger Register" bitfld.long 0x00 5. " TRIG5 ,Channel 5 trigger" "No effect,Used" bitfld.long 0x00 4. " TRIG4 ,Channel 4 trigger" "No effect,Used" bitfld.long 0x00 3. " TRIG3 ,Channel 3 trigger" "No effect,Used" newline bitfld.long 0x00 2. " TRIG2 ,Channel 2 trigger" "No effect,Used" bitfld.long 0x00 1. " TRIG1 ,Channel 1 trigger" "No effect,Used" bitfld.long 0x00 0. " TRIG0 ,Channel 0 trigger" "No effect,Used" line.long 0x04 "POL,Channel Polarity Register" bitfld.long 0x04 5. " POL5 ,Channel 5 polarity" "High,Low" bitfld.long 0x04 4. " POL4 ,Channel 4 polarity" "High,Low" bitfld.long 0x04 3. " POL3 ,Channel 3 polarity" "High,Low" newline bitfld.long 0x04 2. " POL2 ,Channel 2 polarity" "High,Low" bitfld.long 0x04 1. " POL1 ,Channel 1 polarity" "High,Low" bitfld.long 0x04 0. " POL0 ,Channel 0 polarity" "High,Low" group.long 0x78++0x03 line.long 0x00 "FILTER,Filter Control Register" bitfld.long 0x00 20.--23. " CH5FVAL ,Channel 5 filter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CH4FVAL ,Channel 4 filter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 filter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 filter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 filter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 filter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status Register" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase,Count and direction" rbitfld.long 0x00 2. " QUADIR ,Counter direction in quadrature decode mode" "Decreased,Increased" rbitfld.long 0x00 1. " TOFDIR ,TOF bit set status" "Bottom,Top" newline bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" if (((per.l.be(ad:0x37200000+0x10))&0x18)==0x00) group.long 0x84++0x03 line.long 0x00 "CONF,Configuration Register" bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" ",CH0,CH1,CH0/CH1,CH2,CH0/CH2,CH1/CH2,CH0/CH1/CH2,CH3,CH0/CH3,CH1/CH3,CH0/CH1/CH3,CH2/CH3,CH0/CH2/CH3,CH1/CH2/CH3,CH0/CH1/CH2/CH3" bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "High,Low" newline bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled" bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Disabled,Enabled" newline bitfld.long 0x00 16. " CSOT ,Counter start trigger" "Immediately,Rising edge" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "Paused,,,Continued" bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled" else group.long 0x84++0x03 line.long 0x00 "CONF,Configuration Register" rbitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" ",CH0,CH1,CH0/CH1,CH2,CH0/CH2,CH1/CH2,CH0/CH1/CH2,CH3,CH0/CH3,CH1/CH3,CH0/CH1/CH3,CH2/CH3,CH0/CH2/CH3,CH1/CH2/CH3,CH0/CH1/CH2/CH3" rbitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal" rbitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "High,Low" newline rbitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled" rbitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded" rbitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Disabled,Enabled" newline rbitfld.long 0x00 16. " CSOT ,Counter start trigger" "Immediately,Rising edge" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "Paused,,,Continued" bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled" endif endian.le width 0x0B tree.end tree "SEMA42 (Semaphores2)" base ad:0x371B0000 width 9. group.byte 0x0++0x03 line.byte 0x00 "GATE3,Gate Register 3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x01 "GATE2,Gate Register 2" bitfld.byte 0x01 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x02 "GATE1,Gate Register 1" bitfld.byte 0x02 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x03 "GATE0,Gate Register 0" bitfld.byte 0x03 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" group.byte 0x4++0x03 line.byte 0x00 "GATE7,Gate Register 7" bitfld.byte 0x00 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x01 "GATE6,Gate Register 6" bitfld.byte 0x01 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x02 "GATE5,Gate Register 5" bitfld.byte 0x02 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x03 "GATE4,Gate Register 4" bitfld.byte 0x03 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" group.byte 0x8++0x03 line.byte 0x00 "GATE11,Gate Register 11" bitfld.byte 0x00 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x01 "GATE10,Gate Register 10" bitfld.byte 0x01 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x02 "GATE9,Gate Register 9" bitfld.byte 0x02 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x03 "GATE8,Gate Register 8" bitfld.byte 0x03 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" group.byte 0xC++0x03 line.byte 0x00 "GATE15,Gate Register 15" bitfld.byte 0x00 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x01 "GATE14,Gate Register 14" bitfld.byte 0x01 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x02 "GATE13,Gate Register 13" bitfld.byte 0x02 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x03 "GATE12,Gate Register 12" bitfld.byte 0x03 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" rgroup.word 0x42++0x01 line.word 0x00 "RSTGT_R,Reset Gate Read Register" bitfld.word 0x00 14.--15. " ROZ ,ROZ" "0,1,2,3" bitfld.word 0x00 12.--13. " RSTGSM ,Reset gate finite state machine" "Idle,Waiting,Completed,?..." bitfld.word 0x00 8.--11. " RSTGMS ,Reset gate bus master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word.byte 0x00 0.--7. 1. " RSTGTN ,Reset gate number" wgroup.word 0x42++0x01 line.word 0x00 "RSTGT_W,Reset Gate Write Register" hexmask.word.byte 0x00 8.--15. 1. " RSTGDP ,Reset gate data pattern" hexmask.word.byte 0x00 0.--7. 1. " RSTGTN ,Reset gate number" width 0x0B tree.end tree.open "MU (Messaging Unit)" tree "MU0-A0" base ad:0x37440000 width 9. if (((per.l(ad:0x37440000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x37440000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x37440000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x37440000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x37440000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x37440000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x37440000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x37440000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree "MU0-A1" base ad:0x37450000 width 9. if (((per.l(ad:0x37450000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x37450000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x37450000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x37450000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x37450000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x37450000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x37450000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x37450000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree "MU0-A2" base ad:0x37460000 width 9. if (((per.l(ad:0x37460000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x37460000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x37460000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x37460000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x37460000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x37460000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x37460000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x37460000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree "MU0-A3" base ad:0x37470000 width 9. if (((per.l(ad:0x37470000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x37470000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x37470000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x37470000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x37470000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x37470000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x37470000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x37470000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree "MU0-B" base ad:0x37430000 width 9. if (((per.l(ad:0x37430000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "BTR0,Processor B Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "BTR0,Processor B Transmit Register 0" endif if (((per.l(ad:0x37430000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "BTR1,Processor B Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "BTR1,Processor B Transmit Register 1" endif if (((per.l(ad:0x37430000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "BTR2,Processor B Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "BTR2,Processor B Transmit Register 2" endif if (((per.l(ad:0x37430000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "BTR3,Processor B Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "BTR3,Processor B Transmit Register 3" endif newline if (((per.l(ad:0x37430000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "BRR0,Processor B Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "BRR0,Processor B Receive Register 0" in newline endif if (((per.l(ad:0x37430000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "BRR1,Processor B Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "BRR1,Processor B Receive Register 1" in newline endif if (((per.l(ad:0x37430000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "BRR2,Processor B Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "BRR2,Processor B Receive Register 2" in newline endif if (((per.l(ad:0x37430000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "BRR3,Processor B Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "BRR3,Processor B Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "BSR,Processor B Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor B general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor B general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor B general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor B general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor B receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor B receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor B receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor B receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor B transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor B transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor B transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor B transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 8. " FUP ,Processor B flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " ARS ,Processor A reset state" "No reset,Reset" bitfld.long 0x00 4. " EP ,Processor B-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor B-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor B-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor B-side flag 0" "0,1" line.long 0x04 "BCR,Processor B Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor B general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor B general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor B general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor B general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor B receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor B receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor B receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor B receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor B transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor B transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor B transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor B transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor B general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor B general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor B general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor B general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 4. " HRM ,Processor B hardware reset mask" "Not masked,Masked" newline bitfld.long 0x04 2. " BAF[2] ,Processor B to processor A flag 2" "Clear,Set" bitfld.long 0x04 1. " [1] ,Processor B to processor A flag 1" "Clear,Set" bitfld.long 0x04 0. " [0] ,Processor B to processor A flag 0" "Clear,Set" width 0x0B tree.end tree "MU1-A" base ad:0x37480000 width 9. if (((per.l(ad:0x37480000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x37480000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x37480000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x37480000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x37480000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x37480000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x37480000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x37480000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree.end tree "WDOG (Watchdog Timer)" base ad:0x37420000 width 7. group.long 0x00++0x0F line.long 0x00 "CS,Watchdog Control and Status Register" bitfld.long 0x00 15. " WIN ,Window mode enable" "Disabled,Enabled" eventfld.long 0x00 14. " FLG ,Watchdog interrupt flag" "Not occurred,Occurred" bitfld.long 0x00 13. " CMD32EN ,WDOG support for 32-bit enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " PRES ,Watchdog 256 prescaler enable" "Disabled,Enabled" rbitfld.long 0x00 11. " ULK ,Unlock status" "Locked,Unlocked" rbitfld.long 0x00 10. " RCS ,Reconfiguration success" "In progress,Succeeded" newline bitfld.long 0x00 8.--9. " CLK ,Watchdog counter clock source" "Bus clock,LPO clock,INTCLK,ERCLK" bitfld.long 0x00 7. " EN ,Watchdog counter enable" "Disabled,Enabled" bitfld.long 0x00 6. " INT ,Watchdog interrupt" "Disabled,Enabled" newline bitfld.long 0x00 5. " UPDATE ,Watchdog software reconfiguration without a reset allowance" "Not allowed,Allowed" bitfld.long 0x00 3.--4. " TST ,Fast test mode enable" "Disabled,User mode,Test mode/low byte,Test mode/high byte" bitfld.long 0x00 2. " DBG ,Debug mode enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " WAIT ,Wait mode enable" "Disabled,Enabled" bitfld.long 0x00 0. " STOP ,Stop mode enable" "Disabled,Enabled" line.long 0x04 "CNT,Watchdog Counter Register" hexmask.long.byte 0x04 8.--15. 1. " CNTHIGH ,High byte of the watchdog counter" hexmask.long.byte 0x04 0.--7. 1. " CNTLOW ,Low byte of the watchdog counter" line.long 0x08 "TOVAL,Watchdog Timeout Value Register" hexmask.long.byte 0x08 8.--15. 1. " TOVALHIGH ,High byte of the timeout value" hexmask.long.byte 0x08 0.--7. 1. " TOVALLOW ,Low byte of the timeout value" line.long 0x0C "WIN,Watchdog Window Register" hexmask.long.byte 0x0C 8.--15. 1. " WINHIGH ,High byte of watchdog window" hexmask.long.byte 0x0C 0.--7. 1. " WINLOW ,Low byte of watchdog window" width 0x0B tree.end tree "ASMC (Auxiliary System Mode Control)" base ad:0x37410000 width 10. rgroup.long 0x00++0x03 line.long 0x00 "SRS,System Reset Status Register" bitfld.long 0x00 12. " SACKERR ,Reset caused by peripheral failure to acknowledge attempt to enter stop mode" "Not occurred,Occurred" bitfld.long 0x00 10. " SW ,Reset caused by software setting of SYSRESETREQ bit" "Not occurred,Occurred" bitfld.long 0x00 9. " LOCKUP ,Reset caused by core LOCKUP event" "Not occurred,Occurred" bitfld.long 0x00 7. " POR ,Reset caused by power-on detection logic" "Not occurred,Occurred" newline bitfld.long 0x00 6. " RES ,Chip Reset caused by a source other than power-on detection logic" "Not occurred,Occurred" bitfld.long 0x00 5. " WDOG1 ,Reset caused by watchdog timer 1 timeout" "Not occurred,Occurred" bitfld.long 0x00 0. " WAKEUP ,Reset caused by LLWU module wakeup source" "Not occurred,Occurred" group.long 0x08++0x0B line.long 0x00 "PMPROT,Power Mode Protection Register" bitfld.long 0x00 7. " AHSRUN ,Allow high speed run mode" "Not allowed,Allowed" bitfld.long 0x00 5. " AVLP ,Allow very low power modes" "Not allowed,Allowed" bitfld.long 0x00 3. " ALLS ,Allow low-leakage stop mode" "Not allowed,Allowed" bitfld.long 0x00 1. " AVLLS ,Allow very-low-leakage stop mode" "Not allowed,Allowed" line.long 0x04 "PMCTRL,Power Mode Control Register" bitfld.long 0x04 5.--6. " RUNM ,Run mode control" "Normal,,Very-low-power,High speed" bitfld.long 0x04 0.--2. " STOPM ,Stop mode control" "Normal,,Very-low-power,Low-leakage,Very-low-leakage,?..." line.long 0x08 "STOPCTRL,Stop Control Register" bitfld.long 0x08 6.--7. " PSTOPO ,Partial stop option" "Normal,PSTOP1,PSTOP2,?..." rgroup.long 0x14++0x03 line.long 0x00 "PMSTAT,Power Mode Status Register" hexmask.long.byte 0x00 0.--7. 1. " PMSTAT ,Power mode status" rgroup.long 0xF0++0x07 "Time Stamp Timer Module (TSTMR)" line.long 0x00 "LOW,Time Stamp Timer Register Low" line.long 0x04 "HIGH,Time Stamp Timer Register High" width 0x0B tree.end tree "INTMUX (Interrupt Multiplexer)" base ad:0x37400000 width 14. group.long 0x0++0x03 "Channel 0" line.long 0x00 "CH0_CSR,Channel 0 Control Status Register" rbitfld.long 0x00 31. " IRQP ,Channel interrupt request pending" "Not pending,Pending" rbitfld.long 0x00 8.--11. " CHIN ,Channel instance number" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 4.--5. " IRQN ,Channel input number" "32 interrupt inputs,?..." newline bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND" bitfld.long 0x00 0. " RST ,Software reset" "No reset,Reset" rgroup.long (0x0+0x04)++0x03 line.long 0x00 "CH0_VEC,Channel 0 Vector Number Register" hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector number" newline group.long (0x0+0x10)++0x03 line.long 0x00 "CH0_IER_31_0,Channel 0 Interrupt Enable Register" bitfld.long 0x00 31. " INTE[31] ,Interrupt MU0_A0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Interrupt LPUART enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Interrupt LPIT enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Interrupt TPM enable" "Disabled,Enabled" rgroup.long (0x0+0x20)++0x03 line.long 0x00 "CH0_IPR_31_0,Channel 0 Interrupt Pending Register" bitfld.long 0x00 31. " INTP[31] ,Interrupt MU0_A0 pending" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 pending" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 pending" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 pending" "Not pending,Pending" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C pending" "Not pending,Pending" bitfld.long 0x00 7. " [7] ,Interrupt LPUART pending" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Interrupt LPIT pending" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Interrupt TPM pending" "Not pending,Pending" group.long 0x40++0x03 "Channel 1" line.long 0x00 "CH1_CSR,Channel 1 Control Status Register" rbitfld.long 0x00 31. " IRQP ,Channel interrupt request pending" "Not pending,Pending" rbitfld.long 0x00 8.--11. " CHIN ,Channel instance number" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 4.--5. " IRQN ,Channel input number" "32 interrupt inputs,?..." newline bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND" bitfld.long 0x00 0. " RST ,Software reset" "No reset,Reset" rgroup.long (0x40+0x04)++0x03 line.long 0x00 "CH1_VEC,Channel 1 Vector Number Register" hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector number" newline group.long (0x40+0x10)++0x03 line.long 0x00 "CH1_IER_31_0,Channel 1 Interrupt Enable Register" bitfld.long 0x00 31. " INTE[31] ,Interrupt MU0_A0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Interrupt LPUART enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Interrupt LPIT enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Interrupt TPM enable" "Disabled,Enabled" rgroup.long (0x40+0x20)++0x03 line.long 0x00 "CH1_IPR_31_0,Channel 1 Interrupt Pending Register" bitfld.long 0x00 31. " INTP[31] ,Interrupt MU0_A0 pending" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 pending" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 pending" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 pending" "Not pending,Pending" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C pending" "Not pending,Pending" bitfld.long 0x00 7. " [7] ,Interrupt LPUART pending" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Interrupt LPIT pending" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Interrupt TPM pending" "Not pending,Pending" group.long 0x80++0x03 "Channel 2" line.long 0x00 "CH2_CSR,Channel 2 Control Status Register" rbitfld.long 0x00 31. " IRQP ,Channel interrupt request pending" "Not pending,Pending" rbitfld.long 0x00 8.--11. " CHIN ,Channel instance number" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 4.--5. " IRQN ,Channel input number" "32 interrupt inputs,?..." newline bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND" bitfld.long 0x00 0. " RST ,Software reset" "No reset,Reset" rgroup.long (0x80+0x04)++0x03 line.long 0x00 "CH2_VEC,Channel 2 Vector Number Register" hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector number" newline group.long (0x80+0x10)++0x03 line.long 0x00 "CH2_IER_31_0,Channel 2 Interrupt Enable Register" bitfld.long 0x00 31. " INTE[31] ,Interrupt MU0_A0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Interrupt LPUART enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Interrupt LPIT enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Interrupt TPM enable" "Disabled,Enabled" rgroup.long (0x80+0x20)++0x03 line.long 0x00 "CH2_IPR_31_0,Channel 2 Interrupt Pending Register" bitfld.long 0x00 31. " INTP[31] ,Interrupt MU0_A0 pending" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 pending" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 pending" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 pending" "Not pending,Pending" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C pending" "Not pending,Pending" bitfld.long 0x00 7. " [7] ,Interrupt LPUART pending" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Interrupt LPIT pending" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Interrupt TPM pending" "Not pending,Pending" group.long 0xC0++0x03 "Channel 3" line.long 0x00 "CH3_CSR,Channel 3 Control Status Register" rbitfld.long 0x00 31. " IRQP ,Channel interrupt request pending" "Not pending,Pending" rbitfld.long 0x00 8.--11. " CHIN ,Channel instance number" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 4.--5. " IRQN ,Channel input number" "32 interrupt inputs,?..." newline bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND" bitfld.long 0x00 0. " RST ,Software reset" "No reset,Reset" rgroup.long (0xC0+0x04)++0x03 line.long 0x00 "CH3_VEC,Channel 3 Vector Number Register" hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector number" newline group.long (0xC0+0x10)++0x03 line.long 0x00 "CH3_IER_31_0,Channel 3 Interrupt Enable Register" bitfld.long 0x00 31. " INTE[31] ,Interrupt MU0_A0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Interrupt LPUART enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Interrupt LPIT enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Interrupt TPM enable" "Disabled,Enabled" rgroup.long (0xC0+0x20)++0x03 line.long 0x00 "CH3_IPR_31_0,Channel 3 Interrupt Pending Register" bitfld.long 0x00 31. " INTP[31] ,Interrupt MU0_A0 pending" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 pending" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 pending" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 pending" "Not pending,Pending" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C pending" "Not pending,Pending" bitfld.long 0x00 7. " [7] ,Interrupt LPUART pending" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Interrupt LPIT pending" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Interrupt TPM pending" "Not pending,Pending" group.long 0x100++0x03 "Channel 4" line.long 0x00 "CH4_CSR,Channel 4 Control Status Register" rbitfld.long 0x00 31. " IRQP ,Channel interrupt request pending" "Not pending,Pending" rbitfld.long 0x00 8.--11. " CHIN ,Channel instance number" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 4.--5. " IRQN ,Channel input number" "32 interrupt inputs,?..." newline bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND" bitfld.long 0x00 0. " RST ,Software reset" "No reset,Reset" rgroup.long (0x100+0x04)++0x03 line.long 0x00 "CH4_VEC,Channel 4 Vector Number Register" hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector number" newline group.long (0x100+0x10)++0x03 line.long 0x00 "CH4_IER_31_0,Channel 4 Interrupt Enable Register" bitfld.long 0x00 31. " INTE[31] ,Interrupt MU0_A0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Interrupt LPUART enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Interrupt LPIT enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Interrupt TPM enable" "Disabled,Enabled" rgroup.long (0x100+0x20)++0x03 line.long 0x00 "CH4_IPR_31_0,Channel 4 Interrupt Pending Register" bitfld.long 0x00 31. " INTP[31] ,Interrupt MU0_A0 pending" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 pending" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 pending" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 pending" "Not pending,Pending" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C pending" "Not pending,Pending" bitfld.long 0x00 7. " [7] ,Interrupt LPUART pending" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Interrupt LPIT pending" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Interrupt TPM pending" "Not pending,Pending" group.long 0x140++0x03 "Channel 5" line.long 0x00 "CH5_CSR,Channel 5 Control Status Register" rbitfld.long 0x00 31. " IRQP ,Channel interrupt request pending" "Not pending,Pending" rbitfld.long 0x00 8.--11. " CHIN ,Channel instance number" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 4.--5. " IRQN ,Channel input number" "32 interrupt inputs,?..." newline bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND" bitfld.long 0x00 0. " RST ,Software reset" "No reset,Reset" rgroup.long (0x140+0x04)++0x03 line.long 0x00 "CH5_VEC,Channel 5 Vector Number Register" hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector number" newline group.long (0x140+0x10)++0x03 line.long 0x00 "CH5_IER_31_0,Channel 5 Interrupt Enable Register" bitfld.long 0x00 31. " INTE[31] ,Interrupt MU0_A0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Interrupt LPUART enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Interrupt LPIT enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Interrupt TPM enable" "Disabled,Enabled" rgroup.long (0x140+0x20)++0x03 line.long 0x00 "CH5_IPR_31_0,Channel 5 Interrupt Pending Register" bitfld.long 0x00 31. " INTP[31] ,Interrupt MU0_A0 pending" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 pending" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 pending" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 pending" "Not pending,Pending" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C pending" "Not pending,Pending" bitfld.long 0x00 7. " [7] ,Interrupt LPUART pending" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Interrupt LPIT pending" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Interrupt TPM pending" "Not pending,Pending" group.long 0x180++0x03 "Channel 6" line.long 0x00 "CH6_CSR,Channel 6 Control Status Register" rbitfld.long 0x00 31. " IRQP ,Channel interrupt request pending" "Not pending,Pending" rbitfld.long 0x00 8.--11. " CHIN ,Channel instance number" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 4.--5. " IRQN ,Channel input number" "32 interrupt inputs,?..." newline bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND" bitfld.long 0x00 0. " RST ,Software reset" "No reset,Reset" rgroup.long (0x180+0x04)++0x03 line.long 0x00 "CH6_VEC,Channel 6 Vector Number Register" hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector number" newline group.long (0x180+0x10)++0x03 line.long 0x00 "CH6_IER_31_0,Channel 6 Interrupt Enable Register" bitfld.long 0x00 31. " INTE[31] ,Interrupt MU0_A0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Interrupt LPUART enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Interrupt LPIT enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Interrupt TPM enable" "Disabled,Enabled" rgroup.long (0x180+0x20)++0x03 line.long 0x00 "CH6_IPR_31_0,Channel 6 Interrupt Pending Register" bitfld.long 0x00 31. " INTP[31] ,Interrupt MU0_A0 pending" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 pending" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 pending" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 pending" "Not pending,Pending" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C pending" "Not pending,Pending" bitfld.long 0x00 7. " [7] ,Interrupt LPUART pending" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Interrupt LPIT pending" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Interrupt TPM pending" "Not pending,Pending" group.long 0x1C0++0x03 "Channel 7" line.long 0x00 "CH7_CSR,Channel 7 Control Status Register" rbitfld.long 0x00 31. " IRQP ,Channel interrupt request pending" "Not pending,Pending" rbitfld.long 0x00 8.--11. " CHIN ,Channel instance number" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 4.--5. " IRQN ,Channel input number" "32 interrupt inputs,?..." newline bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND" bitfld.long 0x00 0. " RST ,Software reset" "No reset,Reset" rgroup.long (0x1C0+0x04)++0x03 line.long 0x00 "CH7_VEC,Channel 7 Vector Number Register" hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector number" newline group.long (0x1C0+0x10)++0x03 line.long 0x00 "CH7_IER_31_0,Channel 7 Interrupt Enable Register" bitfld.long 0x00 31. " INTE[31] ,Interrupt MU0_A0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Interrupt LPUART enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Interrupt LPIT enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Interrupt TPM enable" "Disabled,Enabled" rgroup.long (0x1C0+0x20)++0x03 line.long 0x00 "CH7_IPR_31_0,Channel 7 Interrupt Pending Register" bitfld.long 0x00 31. " INTP[31] ,Interrupt MU0_A0 pending" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 pending" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 pending" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 pending" "Not pending,Pending" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C pending" "Not pending,Pending" bitfld.long 0x00 7. " [7] ,Interrupt LPUART pending" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Interrupt LPIT pending" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Interrupt TPM pending" "Not pending,Pending" width 0x0B tree.end tree.end endif sif (cpuis("IMX8*-SCU")) tree.open "SCU (System Controller Unit)" tree "LPI2C (Low-Power I2C Controller)" base ad:0x41230000 width 8. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number" line.long 0x04 "PARAM,Parameter Register" bitfld.long 0x04 8.--11. " MRXFIFO ,Master receive FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x04 0.--3. " MTXFIFO ,Master transmit FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" group.long 0x10++0x13 line.long 0x00 "MCR,Master Control Register" bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset" bitfld.long 0x00 3. " DBGEN ,Debug enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " MEN ,Master enable" "Disabled,Enabled" line.long 0x04 "MSR,Master Status Register" rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x04 24. " MBF ,Master busy flag" "Idle,Busy" eventfld.long 0x04 14. " DMF ,Data match flag" "Not received,Received" eventfld.long 0x04 13. " PLTF ,Pin low timeout flag" "Not occurred/disabled,Occurred" newline eventfld.long 0x04 12. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x04 11. " ALF ,Arbitration lost flag" "Not lost,Lost" eventfld.long 0x04 10. " NDF ,NACK detect flag" "Not detected,Detected" eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected" newline eventfld.long 0x04 8. " EPF ,End packet flag" "Not generated/Repeated,Generated/Repeated" rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "MIER,Master Interrupt Enable Register" bitfld.long 0x08 14. " DMIE ,Data match interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " PLTIE ,Pin low timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " FEIE ,FIFO error interrupt disable" "No,Yes" newline bitfld.long 0x08 11. " ALIE ,Arbitration lost interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " NDIE ,NACK detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " EPIE ,End packet interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "MDER,Master DMA Enable Register" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" line.long 0x10 "MCFGR0,Master Configuration Register 0" bitfld.long 0x10 9. " RDMO ,Receive data match only" "Stored,Discarded" bitfld.long 0x10 8. " CIRFIFO ,Circular FIFO enable" "Disabled,Enabled" bitfld.long 0x10 2. " HRSEL ,Host request select" "HREQ pin,Input trigger" newline bitfld.long 0x10 1. " HRPOL ,Host request polarity" "Active low,Active high" bitfld.long 0x10 0. " HREN ,Host request enable" "Disabled,Enabled" newline if (((per.l(ad:0x41230000+0x10))&0x01)==0x01) rgroup.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Disabled,,1st word = MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "SCL,SCL or SDA" newline bitfld.long 0x00 9. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "No effect,Enabled" bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" else group.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Disabled,,1st word = MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "On SCL low too long,On SCL or SDA low too long" newline bitfld.long 0x00 9. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "No effect,Enabled" bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" endif newline if ((((per.l(ad:0x41230000+0x10))&0x01)==0x00)||(((per.l(ad:0x41230000+0x14))&0x1000000)==0x00)) group.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" else rgroup.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" endif if (((per.l(ad:0x41230000+0x10))&0x01)==0x01) rgroup.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x58++0x03 line.long 0x00 "MFCR,Master FIFO Control Register" bitfld.long 0x00 16.--17. " RXWATER ,Receive FIFO watermark" "0,1,2,3" bitfld.long 0x00 0.--1. " TXWATER ,Transmit FIFO watermark" "0,1,2,3" rgroup.long 0x5C++0x03 line.long 0x00 "MFSR,Master FIFO Status Register" bitfld.long 0x00 16.--18. " RXCOUNT ,Receive FIFO count" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " TXCOUNT ,Transmit FIFO count" "0,1,2,3,4,5,6,7" newline wgroup.long 0x60++0x03 line.long 0x00 "MTDR,Master Transmit Data Register" bitfld.long 0x00 8.--10. " CMD ,Command data" "Transmit,Receive,Generate STOP,Receive and discard,START and transmit,START and transmit (NACK returned),START and transmit (high speed mode),START and transmit high speed mode (NACK returned)" newline hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data" newline hgroup.long 0x70++0x03 hide.long 0x00 "MRDR,Master Receive Data Register" in newline group.long 0x110++0x0F line.long 0x00 "SCR,Slave Control Register" bitfld.long 0x00 9. " RRF ,Receive FIFO reset" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Transmit FIFO reset" "No effect,Reset" bitfld.long 0x00 5. " FILTDZ ,Filter doze enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " FILTEN ,Filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " SEN ,Slave enable" "Disabled,Enabled" line.long 0x04 "SSR,Slave Status Register" rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x04 24. " SBF ,Slave busy flag" "Idle,Busy" rbitfld.long 0x04 15. " SARF ,SMBus alert response flag" "Not detected,Detected" rbitfld.long 0x04 14. " GCF ,General call flag" "Not detected,Detected" newline rbitfld.long 0x04 13. " AM1F ,Address match 1 flag" "Not matched,Matched" rbitfld.long 0x04 12. " AM0F ,Address match 0 flag" "Not matched,Matched" eventfld.long 0x04 11. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x04 10. " BEF ,Bit error flag" "No error,Error" newline eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected" eventfld.long 0x04 8. " RSF ,Repeated start flag" "Not detected,Detected" rbitfld.long 0x04 3. " TAF ,Transmit ACK flag" "Not required,Required" rbitfld.long 0x04 2. " AVF ,Address valid flag" "Invalid,Valid" newline rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "SIER,Slave Interrupt Enable Register" bitfld.long 0x08 15. " SARIE ,SMBus alert response interrupt enable" "Disabled,Enabled" bitfld.long 0x08 14. " GCIE ,General call interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " AM1F ,Address match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " AM0IE ,Address match 0 interrupt disable" "No,Yes" newline bitfld.long 0x08 11. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " BEIE ,Bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 8. " RSIE ,Repeated start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " TAIE ,Transmit ACK interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " AVIE ,Address valid interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "SDER,Slave DMA Enable Register" bitfld.long 0x0C 2. " AVDE ,Address valid DMA enable" "Disabled,Enabled" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" newline if (((per.l(ad:0x41230000+0x110))&0x01)==0x01) rgroup.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration match" "0 (7-bit),0 (10-bit),0 (7-bit) / 1 (7-bit),0 (10-bit) / 1 (10-bit),0 (7-bit) / 1 (10-bit),0 (10-bit) / 1 (7-bit),From 0 (7-bit) to 1 (7-bit),From 0 (10-bit) to 1 (10-bit)" bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" bitfld.long 0x00 12. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return data / clear RDF,Return address / clear AVF" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer,On TDR empty" bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration match" "0 (7-bit),0 (10-bit),0 (7-bit) / 1 (7-bit),0 (10-bit) / 1 (10-bit),0 (7-bit) / 1 (10-bit),0 (10-bit) / 1 (7-bit),From 0 (7-bit) to 1 (7-bit),From 0 (10-bit) to 1 (10-bit)" bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" bitfld.long 0x00 12. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return data / clear RDF,Return address / clear AVF" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer,On TDR empty" bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline if (((per.l(ad:0x41230000+0x110))&0x01)==0x01) rgroup.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" else group.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" endif rgroup.long 0x150++0x03 line.long 0x00 "SASR,Slave Address Status Register" bitfld.long 0x00 14. " ANV ,Address invalid" "No,Yes" hexmask.long.word 0x00 0.--10. 0x01 " RADDR ,Received address" if (((per.l(ad:0x41230000+0x124))&0x08)==0x08) group.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,NACK transmit" "ACK,NACK" else rgroup.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,NACK transmit" "ACK,NACK" endif wgroup.long 0x160++0x03 line.long 0x00 "STDR,Slave Transmit Data Register" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data" rgroup.long 0x170++0x03 line.long 0x00 "SRDR,Slave Receive Data Register" bitfld.long 0x00 15. " SOF ,Start of frame" "Not the first data word,First data word" bitfld.long 0x00 14. " RXEMPTY ,RX empty" "Not empty,Empty" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data receive" width 0x0B tree.end tree "LPIT" base ad:0x41210000 endian.be width 13. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.word 0x00 16.--31. 1. " FEATURE ,Feature number" hexmask.long.byte 0x00 8.--15. 1. " MINOR ,Minor version number" hexmask.long.byte 0x00 0.--7. 1. " MAJOR ,Major version number" line.long 0x04 "PARAM,Parameter Register" hexmask.long.byte 0x04 24.--31. 1. " CHANNEL ,Number of timer channels" hexmask.long.byte 0x04 16.--23. 1. " EXT_TRIG ,Number of external trigger inputs" group.long 0x08++0x03 line.long 0x00 "MCR,Module Control Register" bitfld.long 0x00 31. " M_CEN ,Module clock enable" "Disabled,Enabled" bitfld.long 0x00 30. " SW_RST ,Software reset bit" "No reset,Reset" bitfld.long 0x00 29. " DOZE_EN ,DOZE mode enable bit" "Disabled,Enabled" bitfld.long 0x00 28. " DBG_EN ,Debug enable bit" "Disabled,Enabled" if (((per.l.be(ad:0x41210000+0x08))&0x01)==0x01) group.long 0x0C++0x03 line.long 0x00 "MSR,Module Status Register" eventfld.long 0x00 31. " TIF0 ,Channel 0 timer interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 30. " TIF1 ,Channel 1 timer interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 29. " TIF2 ,Channel 2 timer interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 28. " TIF3 ,Channel 3 timer interrupt flag" "No interrupt,Interrupt" else rgroup.long 0x0C++0x03 line.long 0x00 "MSR,Module Status Register" bitfld.long 0x00 31. " TIF0 ,Channel 0 timer interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 30. " TIF1 ,Channel 1 timer interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 29. " TIF2 ,Channel 2 timer interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 28. " TIF3 ,Channel 3 timer interrupt flag" "No interrupt,Interrupt" endif group.long 0x10++0x03 line.long 0x00 "MIER,Module Interrupt Enable Register" bitfld.long 0x00 31. " TIE0 ,Channel 0 timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 30. " TIE1 ,Channel 1 timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 29. " TIE2 ,Channel 2 timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " TIE3 ,Channel 3 timer interrupt enable" "Disabled,Enabled" if (((per.l.be(ad:0x41210000+0x08))&0x01)==0x01) group.long 0x14++0x03 line.long 0x00 "TEN_SET/CLR,Set/Clear Timer Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " T_EN_0 ,Timer 0 enable" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " T_EN_1 ,Timer 1 enable" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x04 29. " T_EN_2 ,Timer 2 enable" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " T_EN_3 ,Timer 3 enable" "Disabled,Enabled" else rgroup.long 0x14++0x07 line.long 0x00 "SETTEN,Set Timer Enable Register" bitfld.long 0x00 31. " SET_T_EN_0 ,Set timer 0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " SET_T_EN_1 ,Set timer 1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " SET_T_EN_2 ,Set timer 2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " SET_T_EN_3 ,Set timer 3 enable" "Disabled,Enabled" line.long 0x04 "CLRTEN,Clear Timer Enable Register" bitfld.long 0x04 31. " CLR_T_EN_0 ,Clear timer 0 enable" "Disabled,Enabled" bitfld.long 0x04 30. " CLR_T_EN_1 ,Clear timer 1 enable" "Disabled,Enabled" bitfld.long 0x04 29. " CLR_T_EN_2 ,Clear timer 2 enable" "Disabled,Enabled" bitfld.long 0x04 28. " CLR_T_EN_3 ,Clear timer 3 enable" "Disabled,Enabled" endif if (((per.l.be(ad:0x41210000+0x08))&0x01)==0x01) group.long 0x20++0x03 line.long 0x00 "TVAL0,Timer Value Register" else rgroup.long 0x20++0x03 line.long 0x00 "TVAL0,Timer Value Register" endif rgroup.long (0x20+0x04)++0x03 line.long 0x00 "CVAL0,Current Timer Value Register" if (((per.l.be(ad:0x41210000+0x08))&0x01)==0x01) if (((per.l.be(ad:0x41210000+0x20+0x08))&0x01)==0x00) group.long (0x20+0x08)++0x03 line.long 0x00 "TCTRL0,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Immediately,Rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." else group.long (0x20+0x08)++0x03 line.long 0x00 "TCTRL0,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" rbitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." endif else rgroup.long (0x20+0x08)++0x03 line.long 0x00 "TCTRL0,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." endif if (((per.l.be(ad:0x41210000+0x08))&0x01)==0x01) group.long 0x30++0x03 line.long 0x00 "TVAL1,Timer Value Register" else rgroup.long 0x30++0x03 line.long 0x00 "TVAL1,Timer Value Register" endif rgroup.long (0x30+0x04)++0x03 line.long 0x00 "CVAL1,Current Timer Value Register" if (((per.l.be(ad:0x41210000+0x08))&0x01)==0x01) if (((per.l.be(ad:0x41210000+0x30+0x08))&0x01)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "TCTRL1,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Immediately,Rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." else group.long (0x30+0x08)++0x03 line.long 0x00 "TCTRL1,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" rbitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." endif else rgroup.long (0x30+0x08)++0x03 line.long 0x00 "TCTRL1,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." endif if (((per.l.be(ad:0x41210000+0x08))&0x01)==0x01) group.long 0x40++0x03 line.long 0x00 "TVAL2,Timer Value Register" else rgroup.long 0x40++0x03 line.long 0x00 "TVAL2,Timer Value Register" endif rgroup.long (0x40+0x04)++0x03 line.long 0x00 "CVAL2,Current Timer Value Register" if (((per.l.be(ad:0x41210000+0x08))&0x01)==0x01) if (((per.l.be(ad:0x41210000+0x40+0x08))&0x01)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "TCTRL2,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Immediately,Rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." else group.long (0x40+0x08)++0x03 line.long 0x00 "TCTRL2,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" rbitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." endif else rgroup.long (0x40+0x08)++0x03 line.long 0x00 "TCTRL2,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." endif if (((per.l.be(ad:0x41210000+0x08))&0x01)==0x01) group.long 0x50++0x03 line.long 0x00 "TVAL3,Timer Value Register" else rgroup.long 0x50++0x03 line.long 0x00 "TVAL3,Timer Value Register" endif rgroup.long (0x50+0x04)++0x03 line.long 0x00 "CVAL3,Current Timer Value Register" if (((per.l.be(ad:0x41210000+0x08))&0x01)==0x01) if (((per.l.be(ad:0x41210000+0x50+0x08))&0x01)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "TCTRL3,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Immediately,Rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." else group.long (0x50+0x08)++0x03 line.long 0x00 "TCTRL3,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" rbitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." endif else rgroup.long (0x50+0x08)++0x03 line.long 0x00 "TCTRL3,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." endif endian.le width 0x0B tree.end tree "TPM" base ad:0x41200000 endian.be width 9. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature identification number" line.long 0x04 "PARAM,Parameter Register" hexmask.long.byte 0x04 16.--23. 1. " WIDTH ,Counter width" hexmask.long.byte 0x04 8.--15. 1. " TRIG ,Trigger count" hexmask.long.byte 0x04 0.--7. 1. " CHAN ,Channel count" group.long 0x08++0x03 line.long 0x00 "GLOBAL,TPM Global Register" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" if (((per.l.be(ad:0x33200000+0x10))&0x18)==0x00) group.long 0x10++0x03 line.long 0x00 "SC,Status And Control Register" bitfld.long 0x00 8. " DMA ,DMA enable" "Disabled,Enabled" eventfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-down counting" bitfld.long 0x00 3.--4. " CMOD ,Clock mode select" "Disabled,Counter clock,Clock rising edge,Input rising edge" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x10++0x03 line.long 0x00 "SC,Status And Control Register" bitfld.long 0x00 8. " DMA ,DMA enable" "Disabled,Enabled" eventfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-down counting" bitfld.long 0x00 3.--4. " CMOD ,Clock mode select" "Disabled,Counter clock,Clock rising edge,Input rising edge" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif group.long 0x14++0x0B line.long 0x00 "CNT,Counter Register" line.long 0x04 "MOD,Modulo Register" line.long 0x08 "STATUS,Capture And Compare Status Register" eventfld.long 0x08 8. " TOF ,Timer overflow flag" "No overflow,Overflow" eventfld.long 0x08 5. " CH5F ,Channel 5 flag" "Not occurred,Occurred" eventfld.long 0x08 4. " CH4F ,Channel 4 flag" "Not occurred,Occurred" newline eventfld.long 0x08 3. " CH3F ,Channel 3 flag" "Not occurred,Occurred" eventfld.long 0x08 2. " CH2F ,Channel 2 flag" "Not occurred,Occurred" eventfld.long 0x08 1. " CH1F ,Channel 1 flag" "Not occurred,Occurred" newline eventfld.long 0x08 0. " CH0F ,Channel 0 flag" "Not occurred,Occurred" if (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x20)&0x30)==0x00)) group.long 0x20++0x03 line.long 0x00 "C0SC,Channel 0 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x20)&0x30)==0x10)) group.long 0x20++0x03 line.long 0x00 "C0SC,Channel 0 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Not used,Toggle output,Clear output,Set output" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x20)&0x30)==0x20)) group.long 0x20++0x03 line.long 0x00 "C0SC,Channel 0 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x20)&0x30)==0x30)) group.long 0x20++0x03 line.long 0x00 "C0SC,Channel 0 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Pulse output high,Pulse output low,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x20)&&((per.l.be(ad:0x33200000+0x20)&0x30)==0x20)) group.long 0x20++0x03 line.long 0x00 "C0SC,Channel 0 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x20++0x03 hide.long 0x00 "C0SC,Channel 0 Status And Control Register" newline endif group.long (0x20+0x04)++0x03 line.long 0x00 "C0V,Channel 0 Value Register" if (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x28)&0x30)==0x00)) group.long 0x28++0x03 line.long 0x00 "C1SC,Channel 1 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x28)&0x30)==0x10)) group.long 0x28++0x03 line.long 0x00 "C1SC,Channel 1 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Not used,Toggle output,Clear output,Set output" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x28)&0x30)==0x20)) group.long 0x28++0x03 line.long 0x00 "C1SC,Channel 1 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x28)&0x30)==0x30)) group.long 0x28++0x03 line.long 0x00 "C1SC,Channel 1 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Pulse output high,Pulse output low,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x20)&&((per.l.be(ad:0x33200000+0x28)&0x30)==0x20)) group.long 0x28++0x03 line.long 0x00 "C1SC,Channel 1 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x28++0x03 hide.long 0x00 "C1SC,Channel 1 Status And Control Register" newline endif group.long (0x28+0x04)++0x03 line.long 0x00 "C1V,Channel 1 Value Register" if (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x30)&0x30)==0x00)) group.long 0x30++0x03 line.long 0x00 "C2SC,Channel 2 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 2 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x30)&0x30)==0x10)) group.long 0x30++0x03 line.long 0x00 "C2SC,Channel 2 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 2 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Not used,Toggle output,Clear output,Set output" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x30)&0x30)==0x20)) group.long 0x30++0x03 line.long 0x00 "C2SC,Channel 2 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 2 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x30)&0x30)==0x30)) group.long 0x30++0x03 line.long 0x00 "C2SC,Channel 2 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 2 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Pulse output high,Pulse output low,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x20)&&((per.l.be(ad:0x33200000+0x30)&0x30)==0x20)) group.long 0x30++0x03 line.long 0x00 "C2SC,Channel 2 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 2 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x30++0x03 hide.long 0x00 "C2SC,Channel 2 Status And Control Register" newline endif group.long (0x30+0x04)++0x03 line.long 0x00 "C2V,Channel 2 Value Register" if (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x38)&0x30)==0x00)) group.long 0x38++0x03 line.long 0x00 "C3SC,Channel 3 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 3 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x38)&0x30)==0x10)) group.long 0x38++0x03 line.long 0x00 "C3SC,Channel 3 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 3 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Not used,Toggle output,Clear output,Set output" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x38)&0x30)==0x20)) group.long 0x38++0x03 line.long 0x00 "C3SC,Channel 3 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 3 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x38)&0x30)==0x30)) group.long 0x38++0x03 line.long 0x00 "C3SC,Channel 3 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 3 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Pulse output high,Pulse output low,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x20)&&((per.l.be(ad:0x33200000+0x38)&0x30)==0x20)) group.long 0x38++0x03 line.long 0x00 "C3SC,Channel 3 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 3 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x38++0x03 hide.long 0x00 "C3SC,Channel 3 Status And Control Register" newline endif group.long (0x38+0x04)++0x03 line.long 0x00 "C3V,Channel 3 Value Register" if (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x40)&0x30)==0x00)) group.long 0x40++0x03 line.long 0x00 "C4SC,Channel 4 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x40)&0x30)==0x10)) group.long 0x40++0x03 line.long 0x00 "C4SC,Channel 4 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Not used,Toggle output,Clear output,Set output" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x40)&0x30)==0x20)) group.long 0x40++0x03 line.long 0x00 "C4SC,Channel 4 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x40)&0x30)==0x30)) group.long 0x40++0x03 line.long 0x00 "C4SC,Channel 4 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Pulse output high,Pulse output low,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x20)&&((per.l.be(ad:0x33200000+0x40)&0x30)==0x20)) group.long 0x40++0x03 line.long 0x00 "C4SC,Channel 4 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x40++0x03 hide.long 0x00 "C4SC,Channel 4 Status And Control Register" newline endif group.long (0x40+0x04)++0x03 line.long 0x00 "C4V,Channel 4 Value Register" if (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x48)&0x30)==0x00)) group.long 0x48++0x03 line.long 0x00 "C5SC,Channel 5 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 5 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x48)&0x30)==0x10)) group.long 0x48++0x03 line.long 0x00 "C5SC,Channel 5 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 5 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Not used,Toggle output,Clear output,Set output" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x48)&0x30)==0x20)) group.long 0x48++0x03 line.long 0x00 "C5SC,Channel 5 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 5 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x48)&0x30)==0x30)) group.long 0x48++0x03 line.long 0x00 "C5SC,Channel 5 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 5 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Pulse output high,Pulse output low,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x20)&&((per.l.be(ad:0x33200000+0x48)&0x30)==0x20)) group.long 0x48++0x03 line.long 0x00 "C5SC,Channel 5 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 5 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x48++0x03 hide.long 0x00 "C5SC,Channel 5 Status And Control Register" newline endif group.long (0x48+0x04)++0x03 line.long 0x00 "C5V,Channel 5 Value Register" group.long 0x64++0x03 line.long 0x00 "COMBINE,Combine Channel Register" bitfld.long 0x00 17. " COMSWAP2 ,Combine channels 4 and 5 swap" "Even,Odd" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" bitfld.long 0x00 9. " COMSWAP1 ,Combine channels 2 and 3 swap" "Even,Odd" newline bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" bitfld.long 0x00 1. " COMSWAP0 ,Combine channels 0 and 1 swap" "Even,Odd" bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" group.long 0x6C++0x07 line.long 0x00 "TRIG,Channel Trigger Register" bitfld.long 0x00 5. " TRIG5 ,Channel 5 trigger" "No effect,Used" bitfld.long 0x00 4. " TRIG4 ,Channel 4 trigger" "No effect,Used" bitfld.long 0x00 3. " TRIG3 ,Channel 3 trigger" "No effect,Used" newline bitfld.long 0x00 2. " TRIG2 ,Channel 2 trigger" "No effect,Used" bitfld.long 0x00 1. " TRIG1 ,Channel 1 trigger" "No effect,Used" bitfld.long 0x00 0. " TRIG0 ,Channel 0 trigger" "No effect,Used" line.long 0x04 "POL,Channel Polarity Register" bitfld.long 0x04 5. " POL5 ,Channel 5 polarity" "High,Low" bitfld.long 0x04 4. " POL4 ,Channel 4 polarity" "High,Low" bitfld.long 0x04 3. " POL3 ,Channel 3 polarity" "High,Low" newline bitfld.long 0x04 2. " POL2 ,Channel 2 polarity" "High,Low" bitfld.long 0x04 1. " POL1 ,Channel 1 polarity" "High,Low" bitfld.long 0x04 0. " POL0 ,Channel 0 polarity" "High,Low" group.long 0x78++0x03 line.long 0x00 "FILTER,Filter Control Register" bitfld.long 0x00 20.--23. " CH5FVAL ,Channel 5 filter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CH4FVAL ,Channel 4 filter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 filter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 filter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 filter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 filter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status Register" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase,Count and direction" rbitfld.long 0x00 2. " QUADIR ,Counter direction in quadrature decode mode" "Decreased,Increased" rbitfld.long 0x00 1. " TOFDIR ,TOF bit set status" "Bottom,Top" newline bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" if (((per.l.be(ad:0x33200000+0x10))&0x18)==0x00) group.long 0x84++0x03 line.long 0x00 "CONF,Configuration Register" bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" ",CH0,CH1,CH0/CH1,CH2,CH0/CH2,CH1/CH2,CH0/CH1/CH2,CH3,CH0/CH3,CH1/CH3,CH0/CH1/CH3,CH2/CH3,CH0/CH2/CH3,CH1/CH2/CH3,CH0/CH1/CH2/CH3" bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "High,Low" newline bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled" bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Disabled,Enabled" newline bitfld.long 0x00 16. " CSOT ,Counter start trigger" "Immediately,Rising edge" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "Paused,,,Continued" bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled" else group.long 0x84++0x03 line.long 0x00 "CONF,Configuration Register" rbitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" ",CH0,CH1,CH0/CH1,CH2,CH0/CH2,CH1/CH2,CH0/CH1/CH2,CH3,CH0/CH3,CH1/CH3,CH0/CH1/CH3,CH2/CH3,CH0/CH2/CH3,CH1/CH2/CH3,CH0/CH1/CH2/CH3" rbitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal" rbitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "High,Low" newline rbitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled" rbitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded" rbitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Disabled,Enabled" newline rbitfld.long 0x00 16. " CSOT ,Counter start trigger" "Immediately,Rising edge" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "Paused,,,Continued" bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled" endif endian.le width 0x0B tree.end tree "LPUART (Low Power Universal Asynchronous Receiver/Transmitter)" base ad:0x41220000 width 8. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature identification number" line.long 0x04 "PARAM,Parameter Register" hexmask.long.byte 0x04 8.--15. 1. " RXFIFO ,Receive FIFO size" hexmask.long.byte 0x04 0.--7. 1. " TXFIFO ,Transmit FIFO size" group.long 0x08++0x03 line.long 0x00 "GLOBAL,Global Register" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" if (((per.l(ad:0x41220000+0x18))&0xC0000)==0x00) group.long 0x0C++0x03 line.long 0x00 "PINCFG,Pin Configuration Register" bitfld.long 0x00 0.--1. " TRGSEL ,Trigger select" "Disabled,Instead RX in,Instead CTS in,TX out modulation" else rgroup.long 0x0C++0x03 line.long 0x00 "PINCFG,Pin Configuration Register" bitfld.long 0x00 0.--1. " TRGSEL ,Trigger select" "Disabled,Instead RX in,Instead CTS in,TX out modulation" endif group.long 0x10++0x07 line.long 0x00 "BAUD,Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" bitfld.long 0x00 29. " M10 ,10-bit mode select" "7/8/9 bit,10 bit" newline bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" "16x,,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 20. " RIDMAE ,Receiver idle DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " SBNS ,Stop bit number select" "One,Two" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" bitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" bitfld.long 0x04 26. " BRK13 ,Break character generation length" "9-13 bit,12-15 bit" newline bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" newline eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" newline if (((per.l(ad:0x41220000+0x18))&0xC0000)==0x00) if ((per.b(ad:0x41220000+0x18)&0x08)==0x08) group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" newline bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,LPUART in Doze mode enabled" "LPUART enabled,LPUART disabled" newline bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" else group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" newline bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,LPUART in Doze mode enabled" "LPUART enabled,LPUART disabled" newline bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif else group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" rbitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" rbitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" rbitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline rbitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" rbitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline rbitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" rbitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" newline rbitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" rbitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" rbitfld.long 0x00 6. " DOZEEN ,LPUART in Doze mode enabled" "LPUART enabled,LPUART disabled" newline rbitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" rbitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" rbitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline rbitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" rbitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" rbitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif group.long 0x1C++0x07 line.long 0x00 "DATA,Data Register" rbitfld.long 0x00 15. " NOISY ,Current received dataword noise" "Not noisy,Noisy" rbitfld.long 0x00 14. " PARITYE ,Current received dataword parity error" "No error,Error" bitfld.long 0x00 13. " FRETSC ,Current received dataword frame error/Transmit special character" "No error/Normal character,Error/Special character" newline rbitfld.long 0x00 12. " RXEMPT ,Receive buffer empty" "Not empty,Empty" rbitfld.long 0x00 11. " IDLINE ,Receiver line idle status before receiving current character" "Not idle,Idle" newline bitfld.long 0x00 9. " R9T9 ,Read receive data buffer 9 or write transmit data buffer 9" "Low,High" bitfld.long 0x00 8. " R8T8 ,Read receive data buffer 8 or write transmit data buffer 8" "Low,High" bitfld.long 0x00 7. " R7T7 ,Read receive data buffer 7 or write transmit data buffer 7" "Low,High" newline bitfld.long 0x00 6. " R6T6 ,Read receive data buffer 6 or write transmit data buffer 6" "Low,High" bitfld.long 0x00 5. " R5T5 ,Read receive data buffer 5 or write transmit data buffer 5" "Low,High" bitfld.long 0x00 4. " R4T4 ,Read receive data buffer 4 or write transmit data buffer 4" "Low,High" newline bitfld.long 0x00 3. " R3T3 ,Read receive data buffer 3 or write transmit data buffer 3" "Low,High" bitfld.long 0x00 2. " R2T2 ,Read receive data buffer 2 or write transmit data buffer 2" "Low,High" bitfld.long 0x00 1. " R1T1 ,Read receive data buffer 1 or write transmit data buffer 1" "Low,High" newline bitfld.long 0x00 0. " R0T0 ,Read receive data buffer 0 or write transmit data buffer 0" "Low,High" line.long 0x04 "MATCH,Match Address Register" hexmask.long.word 0x04 16.--25. 0x01 " MA2 ,Match address 2" hexmask.long.word 0x04 0.--9. 0x01 " MA1 ,Match address 1" if (((per.l(ad:0x41220000+0x18))&0xC0000)==0x00) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" bitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" newline bitfld.long 0x00 8.--12. " RTSWATER ,Receive RTS configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" elif (((per.l(ad:0x41220000+0x18))&0xC0000)==0x40000) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" newline rbitfld.long 0x00 8.--12. " RTSWATER ,Receive RTS configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" rbitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" elif (((per.l(ad:0x41220000+0x18))&0xC0000)==0x80000) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" newline bitfld.long 0x00 8.--12. " RTSWATER ,Receive RTS configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" rbitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline rbitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" newline rbitfld.long 0x00 8.--12. " RTSWATER ,Receive RTS configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" rbitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" rbitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline rbitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" endif if ((((per.l(ad:0x41220000+0x18))&0xC0000)==0x00)&&(((per.l(ad:0x41220000+0x28))&0xC00000)==0xC00000)) group.long 0x28++0x03 line.long 0x00 "FIFO,FIFO Register" rbitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO empty" "Not empty,Empty" rbitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO empty" "Not empty,Empty" eventfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" eventfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" newline rbitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" else rgroup.long 0x28++0x03 line.long 0x00 "FIFO,FIFO Register" bitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" bitfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" endif if (((per.l(ad:0x41220000+0x18))&0x80000)==0x80000) rgroup.long 0x2C++0x03 line.long 0x00 "WATER,Watermark Register" bitfld.long 0x00 24.--29. " RXCOUNT ,Receive counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--20. " RXWATER ,Receive watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " TXCOUNT ,Transmit counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--4. " TXWATER ,Transmit watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x2C++0x03 line.long 0x00 "WATER,Watermark Register" rbitfld.long 0x00 24.--29. " RXCOUNT ,Receive counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--20. " RXWATER ,Receive watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " TXCOUNT ,Transmit counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--4. " TXWATER ,Transmit watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif width 0x0B tree.end tree "RGPIO (Rapid General-Purpose Input and Output)" base ad:0x410F0000 width 6. group.long 0x00++0x03 line.long 0x00 "PDOR,Port Data Output Register" bitfld.long 0x00 31. " PDO[31] ,Port data output pin 31" "Low,High" bitfld.long 0x00 30. " [30] ,Port data output pin 30" "Low,High" bitfld.long 0x00 29. " [29] ,Port data output pin 29" "Low,High" bitfld.long 0x00 28. " [28] ,Port data output pin 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,Port data output pin 27" "Low,High" bitfld.long 0x00 26. " [26] ,Port data output pin 26" "Low,High" bitfld.long 0x00 25. " [25] ,Port data output pin 25" "Low,High" bitfld.long 0x00 24. " [24] ,Port data output pin 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,Port data output pin 23" "Low,High" bitfld.long 0x00 22. " [22] ,Port data output pin 22" "Low,High" bitfld.long 0x00 21. " [21] ,Port data output pin 21" "Low,High" bitfld.long 0x00 20. " [20] ,Port data output pin 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,Port data output pin 19" "Low,High" bitfld.long 0x00 18. " [18] ,Port data output pin 18" "Low,High" bitfld.long 0x00 17. " [17] ,Port data output pin 17" "Low,High" bitfld.long 0x00 16. " [16] ,Port data output pin 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,Port data output pin 15" "Low,High" bitfld.long 0x00 14. " [14] ,Port data output pin 14" "Low,High" bitfld.long 0x00 13. " [13] ,Port data output pin 13" "Low,High" bitfld.long 0x00 12. " [12] ,Port data output pin 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,Port data output pin 11" "Low,High" bitfld.long 0x00 10. " [10] ,Port data output pin 10" "Low,High" bitfld.long 0x00 9. " [9] ,Port data output pin 9" "Low,High" bitfld.long 0x00 8. " [8] ,Port data output pin 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,Port data output pin 7" "Low,High" bitfld.long 0x00 6. " [6] ,Port data output pin 6" "Low,High" bitfld.long 0x00 5. " [5] ,Port data output pin 5" "Low,High" bitfld.long 0x00 4. " [4] ,Port data output pin 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,Port data output pin 3" "Low,High" bitfld.long 0x00 2. " [2] ,Port data output pin 2" "Low,High" bitfld.long 0x00 1. " [1] ,Port data output pin 1" "Low,High" bitfld.long 0x00 0. " [0] ,Port data output pin 0" "Low,High" wgroup.long 0x04++0x0B line.long 0x00 "PSOR,Port Set Output Register" bitfld.long 0x00 31. " PTSO[31] ,Port set output pin 31" "No effect,Set" bitfld.long 0x00 30. " [30] ,Port set output pin 30" "No effect,Set" bitfld.long 0x00 29. " [29] ,Port set output pin 29" "No effect,Set" bitfld.long 0x00 28. " [28] ,Port set output pin 28" "No effect,Set" newline bitfld.long 0x00 27. " [27] ,Port set output pin 27" "No effect,Set" bitfld.long 0x00 26. " [26] ,Port set output pin 26" "No effect,Set" bitfld.long 0x00 25. " [25] ,Port set output pin 25" "No effect,Set" bitfld.long 0x00 24. " [24] ,Port set output pin 24" "No effect,Set" newline bitfld.long 0x00 23. " [23] ,Port set output pin 23" "No effect,Set" bitfld.long 0x00 22. " [22] ,Port set output pin 22" "No effect,Set" bitfld.long 0x00 21. " [21] ,Port set output pin 21" "No effect,Set" bitfld.long 0x00 20. " [20] ,Port set output pin 20" "No effect,Set" newline bitfld.long 0x00 19. " [19] ,Port set output pin 19" "No effect,Set" bitfld.long 0x00 18. " [18] ,Port set output pin 18" "No effect,Set" bitfld.long 0x00 17. " [17] ,Port set output pin 17" "No effect,Set" bitfld.long 0x00 16. " [16] ,Port set output pin 16" "No effect,Set" newline bitfld.long 0x00 15. " [15] ,Port set output pin 15" "No effect,Set" bitfld.long 0x00 14. " [14] ,Port set output pin 14" "No effect,Set" bitfld.long 0x00 13. " [13] ,Port set output pin 13" "No effect,Set" bitfld.long 0x00 12. " [12] ,Port set output pin 12" "No effect,Set" newline bitfld.long 0x00 11. " [11] ,Port set output pin 11" "No effect,Set" bitfld.long 0x00 10. " [10] ,Port set output pin 10" "No effect,Set" bitfld.long 0x00 9. " [9] ,Port set output pin 9" "No effect,Set" bitfld.long 0x00 8. " [8] ,Port set output pin 8" "No effect,Set" newline bitfld.long 0x00 7. " [7] ,Port set output pin 7" "No effect,Set" bitfld.long 0x00 6. " [6] ,Port set output pin 6" "No effect,Set" bitfld.long 0x00 5. " [5] ,Port set output pin 5" "No effect,Set" bitfld.long 0x00 4. " [4] ,Port set output pin 4" "No effect,Set" newline bitfld.long 0x00 3. " [3] ,Port set output pin 3" "No effect,Set" bitfld.long 0x00 2. " [2] ,Port set output pin 2" "No effect,Set" bitfld.long 0x00 1. " [1] ,Port set output pin 1" "No effect,Set" bitfld.long 0x00 0. " [0] ,Port set output pin 0" "No effect,Set" line.long 0x04 "PCOR,Port Clear Output Register" bitfld.long 0x04 31. " PTCO[31] ,Port clear output pin 31" "No effect,Clear" bitfld.long 0x04 30. " [30] ,Port clear output pin 30" "No effect,Clear" bitfld.long 0x04 29. " [29] ,Port clear output pin 29" "No effect,Clear" bitfld.long 0x04 28. " [28] ,Port clear output pin 28" "No effect,Clear" newline bitfld.long 0x04 27. " [27] ,Port clear output pin 27" "No effect,Clear" bitfld.long 0x04 26. " [26] ,Port clear output pin 26" "No effect,Clear" bitfld.long 0x04 25. " [25] ,Port clear output pin 25" "No effect,Clear" bitfld.long 0x04 24. " [24] ,Port clear output pin 24" "No effect,Clear" newline bitfld.long 0x04 23. " [23] ,Port clear output pin 23" "No effect,Clear" bitfld.long 0x04 22. " [22] ,Port clear output pin 22" "No effect,Clear" bitfld.long 0x04 21. " [21] ,Port clear output pin 21" "No effect,Clear" bitfld.long 0x04 20. " [20] ,Port clear output pin 20" "No effect,Clear" newline bitfld.long 0x04 19. " [19] ,Port clear output pin 19" "No effect,Clear" bitfld.long 0x04 18. " [18] ,Port clear output pin 18" "No effect,Clear" bitfld.long 0x04 17. " [17] ,Port clear output pin 17" "No effect,Clear" bitfld.long 0x04 16. " [16] ,Port clear output pin 16" "No effect,Clear" newline bitfld.long 0x04 15. " [15] ,Port clear output pin 15" "No effect,Clear" bitfld.long 0x04 14. " [14] ,Port clear output pin 14" "No effect,Clear" bitfld.long 0x04 13. " [13] ,Port clear output pin 13" "No effect,Clear" bitfld.long 0x04 12. " [12] ,Port clear output pin 12" "No effect,Clear" newline bitfld.long 0x04 11. " [11] ,Port clear output pin 11" "No effect,Clear" bitfld.long 0x04 10. " [10] ,Port clear output pin 10" "No effect,Clear" bitfld.long 0x04 9. " [9] ,Port clear output pin 9" "No effect,Clear" bitfld.long 0x04 8. " [8] ,Port clear output pin 8" "No effect,Clear" newline bitfld.long 0x04 7. " [7] ,Port clear output pin 7" "No effect,Clear" bitfld.long 0x04 6. " [6] ,Port clear output pin 6" "No effect,Clear" bitfld.long 0x04 5. " [5] ,Port clear output pin 5" "No effect,Clear" bitfld.long 0x04 4. " [4] ,Port clear output pin 4" "No effect,Clear" newline bitfld.long 0x04 3. " [3] ,Port clear output pin 3" "No effect,Clear" bitfld.long 0x04 2. " [2] ,Port clear output pin 2" "No effect,Clear" bitfld.long 0x04 1. " [1] ,Port clear output pin 1" "No effect,Clear" bitfld.long 0x04 0. " [0] ,Port clear output pin 0" "No effect,Clear" line.long 0x08 "PTOR,Port Toggle Output Register" bitfld.long 0x08 31. " PTTO[31] ,Port toggle output pin 31" "No effect,Toggled" bitfld.long 0x08 30. " [30] ,Port toggle output pin 30" "No effect,Toggled" bitfld.long 0x08 29. " [29] ,Port toggle output pin 29" "No effect,Toggled" bitfld.long 0x08 28. " [28] ,Port toggle output pin 28" "No effect,Toggled" newline bitfld.long 0x08 27. " [27] ,Port toggle output pin 27" "No effect,Toggled" bitfld.long 0x08 26. " [26] ,Port toggle output pin 26" "No effect,Toggled" bitfld.long 0x08 25. " [25] ,Port toggle output pin 25" "No effect,Toggled" bitfld.long 0x08 24. " [24] ,Port toggle output pin 24" "No effect,Toggled" newline bitfld.long 0x08 23. " [23] ,Port toggle output pin 23" "No effect,Toggled" bitfld.long 0x08 22. " [22] ,Port toggle output pin 22" "No effect,Toggled" bitfld.long 0x08 21. " [21] ,Port toggle output pin 21" "No effect,Toggled" bitfld.long 0x08 20. " [20] ,Port toggle output pin 20" "No effect,Toggled" newline bitfld.long 0x08 19. " [19] ,Port toggle output pin 19" "No effect,Toggled" bitfld.long 0x08 18. " [18] ,Port toggle output pin 18" "No effect,Toggled" bitfld.long 0x08 17. " [17] ,Port toggle output pin 17" "No effect,Toggled" bitfld.long 0x08 16. " [16] ,Port toggle output pin 16" "No effect,Toggled" newline bitfld.long 0x08 15. " [15] ,Port toggle output pin 15" "No effect,Toggled" bitfld.long 0x08 14. " [14] ,Port toggle output pin 14" "No effect,Toggled" bitfld.long 0x08 13. " [13] ,Port toggle output pin 13" "No effect,Toggled" bitfld.long 0x08 12. " [12] ,Port toggle output pin 12" "No effect,Toggled" newline bitfld.long 0x08 11. " [11] ,Port toggle output pin 11" "No effect,Toggled" bitfld.long 0x08 10. " [10] ,Port toggle output pin 10" "No effect,Toggled" bitfld.long 0x08 9. " [9] ,Port toggle output pin 9" "No effect,Toggled" bitfld.long 0x08 8. " [8] ,Port toggle output pin 8" "No effect,Toggled" newline bitfld.long 0x08 7. " [7] ,Port toggle output pin 7" "No effect,Toggled" bitfld.long 0x08 6. " [6] ,Port toggle output pin 6" "No effect,Toggled" bitfld.long 0x08 5. " [5] ,Port toggle output pin 5" "No effect,Toggled" bitfld.long 0x08 4. " [4] ,Port toggle output pin 4" "No effect,Toggled" newline bitfld.long 0x08 3. " [3] ,Port toggle output pin 3" "No effect,Toggled" bitfld.long 0x08 2. " [2] ,Port toggle output pin 2" "No effect,Toggled" bitfld.long 0x08 1. " [1] ,Port toggle output pin 1" "No effect,Toggled" bitfld.long 0x08 0. " [0] ,Port toggle output pin 0" "No effect,Toggled" rgroup.long 0x10++0x03 line.long 0x00 "PDIR,Port Data Input Register" bitfld.long 0x00 31. " PDI[31] ,Port data input pin 31" "Low/Not configured,High" bitfld.long 0x00 30. " [30] ,Port data input pin 30" "Low/Not configured,High" bitfld.long 0x00 29. " [29] ,Port data input pin 29" "Low/Not configured,High" bitfld.long 0x00 28. " [28] ,Port data input pin 28" "Low/Not configured,High" newline bitfld.long 0x00 27. " [27] ,Port data input pin 27" "Low/Not configured,High" bitfld.long 0x00 26. " [26] ,Port data input pin 26" "Low/Not configured,High" bitfld.long 0x00 25. " [25] ,Port data input pin 25" "Low/Not configured,High" bitfld.long 0x00 24. " [24] ,Port data input pin 24" "Low/Not configured,High" newline bitfld.long 0x00 23. " [23] ,Port data input pin 23" "Low/Not configured,High" bitfld.long 0x00 22. " [22] ,Port data input pin 22" "Low/Not configured,High" bitfld.long 0x00 21. " [21] ,Port data input pin 21" "Low/Not configured,High" bitfld.long 0x00 20. " [20] ,Port data input pin 20" "Low/Not configured,High" newline bitfld.long 0x00 19. " [19] ,Port data input pin 19" "Low/Not configured,High" bitfld.long 0x00 18. " [18] ,Port data input pin 18" "Low/Not configured,High" bitfld.long 0x00 17. " [17] ,Port data input pin 17" "Low/Not configured,High" bitfld.long 0x00 16. " [16] ,Port data input pin 16" "Low/Not configured,High" newline bitfld.long 0x00 15. " [15] ,Port data input pin 15" "Low/Not configured,High" bitfld.long 0x00 14. " [14] ,Port data input pin 14" "Low/Not configured,High" bitfld.long 0x00 13. " [13] ,Port data input pin 13" "Low/Not configured,High" bitfld.long 0x00 12. " [12] ,Port data input pin 12" "Low/Not configured,High" newline bitfld.long 0x00 11. " [11] ,Port data input pin 11" "Low/Not configured,High" bitfld.long 0x00 10. " [10] ,Port data input pin 10" "Low/Not configured,High" bitfld.long 0x00 9. " [9] ,Port data input pin 9" "Low/Not configured,High" bitfld.long 0x00 8. " [8] ,Port data input pin 8" "Low/Not configured,High" newline bitfld.long 0x00 7. " [7] ,Port data input pin 7" "Low/Not configured,High" bitfld.long 0x00 6. " [6] ,Port data input pin 6" "Low/Not configured,High" bitfld.long 0x00 5. " [5] ,Port data input pin 5" "Low/Not configured,High" bitfld.long 0x00 4. " [4] ,Port data input pin 4" "Low/Not configured,High" newline bitfld.long 0x00 3. " [3] ,Port data input pin 3" "Low/Not configured,High" bitfld.long 0x00 2. " [2] ,Port data input pin 2" "Low/Not configured,High" bitfld.long 0x00 1. " [1] ,Port data input pin 1" "Low/Not configured,High" bitfld.long 0x00 0. " [0] ,Port data input pin 0" "Low/Not configured,High" group.long 0x14++0x03 line.long 0x00 "PDDR,Port Data Direction Register" bitfld.long 0x00 31. " PDD[31] ,Port data direction" "Input,Output" bitfld.long 0x00 30. " [30] ,Port data direction pin 30" "Input,Output" bitfld.long 0x00 29. " [29] ,Port data direction pin 29" "Input,Output" bitfld.long 0x00 28. " [28] ,Port data direction pin 28" "Input,Output" newline bitfld.long 0x00 27. " [27] ,Port data direction pin 27" "Input,Output" bitfld.long 0x00 26. " [26] ,Port data direction pin 26" "Input,Output" bitfld.long 0x00 25. " [25] ,Port data direction pin 25" "Input,Output" bitfld.long 0x00 24. " [24] ,Port data direction pin 24" "Input,Output" newline bitfld.long 0x00 23. " [23] ,Port data direction pin 23" "Input,Output" bitfld.long 0x00 22. " [22] ,Port data direction pin 22" "Input,Output" bitfld.long 0x00 21. " [21] ,Port data direction pin 21" "Input,Output" bitfld.long 0x00 20. " [20] ,Port data direction pin 20" "Input,Output" newline bitfld.long 0x00 19. " [19] ,Port data direction pin 19" "Input,Output" bitfld.long 0x00 18. " [18] ,Port data direction pin 18" "Input,Output" bitfld.long 0x00 17. " [17] ,Port data direction pin 17" "Input,Output" bitfld.long 0x00 16. " [16] ,Port data direction pin 16" "Input,Output" newline bitfld.long 0x00 15. " [15] ,Port data direction pin 15" "Input,Output" bitfld.long 0x00 14. " [14] ,Port data direction pin 14" "Input,Output" bitfld.long 0x00 13. " [13] ,Port data direction pin 13" "Input,Output" bitfld.long 0x00 12. " [12] ,Port data direction pin 12" "Input,Output" newline bitfld.long 0x00 11. " [11] ,Port data direction pin 11" "Input,Output" bitfld.long 0x00 10. " [10] ,Port data direction pin 10" "Input,Output" bitfld.long 0x00 9. " [9] ,Port data direction pin 9" "Input,Output" bitfld.long 0x00 8. " [8] ,Port data direction pin 8" "Input,Output" newline bitfld.long 0x00 7. " [7] ,Port data direction pin 7" "Input,Output" bitfld.long 0x00 6. " [6] ,Port data direction pin 6" "Input,Output" bitfld.long 0x00 5. " [5] ,Port data direction pin 5" "Input,Output" bitfld.long 0x00 4. " [4] ,Port data direction pin 4" "Input,Output" newline bitfld.long 0x00 3. " [3] ,Port data direction pin 3" "Input,Output" bitfld.long 0x00 2. " [2] ,Port data direction pin 2" "Input,Output" bitfld.long 0x00 1. " [1] ,Port data direction pin 1" "Input,Output" bitfld.long 0x00 0. " [0] ,Port data direction pin 0" "Input,Output" width 0x0B tree.end tree "SEMA42 (Semaphores2)" base ad:0x411B0000 width 9. group.byte 0x0++0x03 line.byte 0x00 "GATE3,Gate Register 3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x01 "GATE2,Gate Register 2" bitfld.byte 0x01 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x02 "GATE1,Gate Register 1" bitfld.byte 0x02 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x03 "GATE0,Gate Register 0" bitfld.byte 0x03 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" group.byte 0x4++0x03 line.byte 0x00 "GATE7,Gate Register 7" bitfld.byte 0x00 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x01 "GATE6,Gate Register 6" bitfld.byte 0x01 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x02 "GATE5,Gate Register 5" bitfld.byte 0x02 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x03 "GATE4,Gate Register 4" bitfld.byte 0x03 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" group.byte 0x8++0x03 line.byte 0x00 "GATE11,Gate Register 11" bitfld.byte 0x00 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x01 "GATE10,Gate Register 10" bitfld.byte 0x01 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x02 "GATE9,Gate Register 9" bitfld.byte 0x02 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x03 "GATE8,Gate Register 8" bitfld.byte 0x03 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" group.byte 0xC++0x03 line.byte 0x00 "GATE15,Gate Register 15" bitfld.byte 0x00 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x01 "GATE14,Gate Register 14" bitfld.byte 0x01 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x02 "GATE13,Gate Register 13" bitfld.byte 0x02 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x03 "GATE12,Gate Register 12" bitfld.byte 0x03 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" rgroup.word 0x42++0x01 line.word 0x00 "RSTGT_R,Reset Gate Read Register" bitfld.word 0x00 14.--15. " ROZ ,ROZ" "0,1,2,3" bitfld.word 0x00 12.--13. " RSTGSM ,Reset gate finite state machine" "Idle,Waiting,Completed,?..." bitfld.word 0x00 8.--11. " RSTGMS ,Reset gate bus master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word.byte 0x00 0.--7. 1. " RSTGTN ,Reset gate number" wgroup.word 0x42++0x01 line.word 0x00 "RSTGT_W,Reset Gate Write Register" hexmask.word.byte 0x00 8.--15. 1. " RSTGDP ,Reset gate data pattern" hexmask.word.byte 0x00 0.--7. 1. " RSTGTN ,Reset gate number" width 0x0B tree.end tree.open "MU (Messaging Unit)" tree "MU0-A0" base ad:0x41440000 width 9. if (((per.l(ad:0x41440000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x41440000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x41440000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x41440000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x41440000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x41440000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x41440000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x41440000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree "MU0-A1" base ad:0x41450000 width 9. if (((per.l(ad:0x41450000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x41450000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x41450000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x41450000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x41450000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x41450000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x41450000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x41450000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree "MU0-A2" base ad:0x41460000 width 9. if (((per.l(ad:0x41460000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x41460000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x41460000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x41460000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x41460000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x41460000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x41460000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x41460000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree "MU0-A3" base ad:0x41470000 width 9. if (((per.l(ad:0x41470000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x41470000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x41470000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x41470000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x41470000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x41470000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x41470000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x41470000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree "MU0-B" base ad:0x41430000 width 9. if (((per.l(ad:0x41430000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "BTR0,Processor B Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "BTR0,Processor B Transmit Register 0" endif if (((per.l(ad:0x41430000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "BTR1,Processor B Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "BTR1,Processor B Transmit Register 1" endif if (((per.l(ad:0x41430000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "BTR2,Processor B Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "BTR2,Processor B Transmit Register 2" endif if (((per.l(ad:0x41430000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "BTR3,Processor B Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "BTR3,Processor B Transmit Register 3" endif newline if (((per.l(ad:0x41430000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "BRR0,Processor B Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "BRR0,Processor B Receive Register 0" in newline endif if (((per.l(ad:0x41430000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "BRR1,Processor B Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "BRR1,Processor B Receive Register 1" in newline endif if (((per.l(ad:0x41430000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "BRR2,Processor B Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "BRR2,Processor B Receive Register 2" in newline endif if (((per.l(ad:0x41430000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "BRR3,Processor B Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "BRR3,Processor B Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "BSR,Processor B Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor B general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor B general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor B general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor B general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor B receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor B receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor B receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor B receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor B transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor B transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor B transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor B transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 8. " FUP ,Processor B flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " ARS ,Processor A reset state" "No reset,Reset" bitfld.long 0x00 4. " EP ,Processor B-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor B-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor B-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor B-side flag 0" "0,1" line.long 0x04 "BCR,Processor B Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor B general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor B general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor B general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor B general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor B receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor B receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor B receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor B receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor B transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor B transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor B transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor B transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor B general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor B general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor B general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor B general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 4. " HRM ,Processor B hardware reset mask" "Not masked,Masked" newline bitfld.long 0x04 2. " BAF[2] ,Processor B to processor A flag 2" "Clear,Set" bitfld.long 0x04 1. " [1] ,Processor B to processor A flag 1" "Clear,Set" bitfld.long 0x04 0. " [0] ,Processor B to processor A flag 0" "Clear,Set" width 0x0B tree.end tree "MU1-A" base ad:0x41480000 width 9. if (((per.l(ad:0x41480000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x41480000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x41480000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x41480000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x41480000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x41480000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x41480000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x41480000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree.end tree "WDOG (Watchdog Timer)" base ad:0x41420000 width 7. group.long 0x00++0x0F line.long 0x00 "CS,Watchdog Control and Status Register" bitfld.long 0x00 15. " WIN ,Window mode enable" "Disabled,Enabled" eventfld.long 0x00 14. " FLG ,Watchdog interrupt flag" "Not occurred,Occurred" bitfld.long 0x00 13. " CMD32EN ,WDOG support for 32-bit enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " PRES ,Watchdog 256 prescaler enable" "Disabled,Enabled" rbitfld.long 0x00 11. " ULK ,Unlock status" "Locked,Unlocked" rbitfld.long 0x00 10. " RCS ,Reconfiguration success" "In progress,Succeeded" newline bitfld.long 0x00 8.--9. " CLK ,Watchdog counter clock source" "Bus clock,LPO clock,INTCLK,ERCLK" bitfld.long 0x00 7. " EN ,Watchdog counter enable" "Disabled,Enabled" bitfld.long 0x00 6. " INT ,Watchdog interrupt" "Disabled,Enabled" newline bitfld.long 0x00 5. " UPDATE ,Watchdog software reconfiguration without a reset allowance" "Not allowed,Allowed" bitfld.long 0x00 3.--4. " TST ,Fast test mode enable" "Disabled,User mode,Test mode/low byte,Test mode/high byte" bitfld.long 0x00 2. " DBG ,Debug mode enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " WAIT ,Wait mode enable" "Disabled,Enabled" bitfld.long 0x00 0. " STOP ,Stop mode enable" "Disabled,Enabled" line.long 0x04 "CNT,Watchdog Counter Register" hexmask.long.byte 0x04 8.--15. 1. " CNTHIGH ,High byte of the watchdog counter" hexmask.long.byte 0x04 0.--7. 1. " CNTLOW ,Low byte of the watchdog counter" line.long 0x08 "TOVAL,Watchdog Timeout Value Register" hexmask.long.byte 0x08 8.--15. 1. " TOVALHIGH ,High byte of the timeout value" hexmask.long.byte 0x08 0.--7. 1. " TOVALLOW ,Low byte of the timeout value" line.long 0x0C "WIN,Watchdog Window Register" hexmask.long.byte 0x0C 8.--15. 1. " WINHIGH ,High byte of watchdog window" hexmask.long.byte 0x0C 0.--7. 1. " WINLOW ,Low byte of watchdog window" width 0x0B tree.end tree "SCU_LPC (SCU Low Power Controller)" base ad:0x40070000 width 5. group.long 0x0++0x03 line.long 0x00 "PC0,Power Control Register 0" hexmask.long.tbyte 0x00 0.--23. 1. " PC ,Power control bus" group.long 0x4++0x03 line.long 0x00 "PC1,Power Control Register 1" hexmask.long.tbyte 0x00 0.--23. 1. " PC ,Power control bus" group.long 0x8++0x03 line.long 0x00 "PC2,Power Control Register 2" hexmask.long.tbyte 0x00 0.--23. 1. " PC ,Power control bus" group.long 0xC++0x03 line.long 0x00 "PC3,Power Control Register 3" hexmask.long.tbyte 0x00 0.--23. 1. " PC ,Power control bus" group.long 0x10++0x03 line.long 0x00 "PC4,Power Control Register 4" hexmask.long.tbyte 0x00 0.--23. 1. " PC ,Power control bus" group.long 0x14++0x03 line.long 0x00 "PC5,Power Control Register 5" hexmask.long.tbyte 0x00 0.--23. 1. " PC ,Power control bus" group.long 0x18++0x03 line.long 0x00 "PC6,Power Control Register 6" hexmask.long.tbyte 0x00 0.--23. 1. " PC ,Power control bus" group.long 0x1C++0x03 line.long 0x00 "CR,Configuration Register" bitfld.long 0x00 7. " CLKG ,LPC clock gate request" "Not requested,Requested" rbitfld.long 0x00 6. " CLKS ,LPC clock status" "Not gated,Gated" bitfld.long 0x00 4.--5. " CLKSEL ,LPC clock select" "25 MHz,1 MHz,32 kHz,?..." bitfld.long 0x00 2. " PCSEL ,LPC/DSC power control select" "DSC,LPC" bitfld.long 0x00 1. " PMICSTDBY ,PMIC standby request asserted during low power mode" "Not asserted,Asserted" bitfld.long 0x00 0. " ROSCDIS ,ROSC disable" "No,Yes" group.long 0x20++0x03 line.long 0x00 "ED0,Entry Delay Stage N 0" bitfld.long 0x00 0.--4. " ED ,Entry delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long (0x20+0x20)++0x03 line.long 0x00 "XD0,Exit Delay Stage N 0" bitfld.long 0x00 0.--4. " XD ,Exit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x24++0x03 line.long 0x00 "ED1,Entry Delay Stage N 1" bitfld.long 0x00 0.--4. " ED ,Entry delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long (0x24+0x20)++0x03 line.long 0x00 "XD1,Exit Delay Stage N 1" bitfld.long 0x00 0.--4. " XD ,Exit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x28++0x03 line.long 0x00 "ED2,Entry Delay Stage N 2" bitfld.long 0x00 0.--4. " ED ,Entry delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long (0x28+0x20)++0x03 line.long 0x00 "XD2,Exit Delay Stage N 2" bitfld.long 0x00 0.--4. " XD ,Exit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x2C++0x03 line.long 0x00 "ED3,Entry Delay Stage N 3" bitfld.long 0x00 0.--4. " ED ,Entry delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long (0x2C+0x20)++0x03 line.long 0x00 "XD3,Exit Delay Stage N 3" bitfld.long 0x00 0.--4. " XD ,Exit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x30++0x03 line.long 0x00 "ED4,Entry Delay Stage N 4" bitfld.long 0x00 0.--4. " ED ,Entry delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long (0x30+0x20)++0x03 line.long 0x00 "XD4,Exit Delay Stage N 4" bitfld.long 0x00 0.--4. " XD ,Exit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x34++0x03 line.long 0x00 "ED5,Entry Delay Stage N 5" bitfld.long 0x00 0.--4. " ED ,Entry delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long (0x34+0x20)++0x03 line.long 0x00 "XD5,Exit Delay Stage N 5" bitfld.long 0x00 0.--4. " XD ,Exit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x38++0x03 line.long 0x00 "ED6,Entry Delay Stage N 6" bitfld.long 0x00 0.--4. " ED ,Entry delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long (0x38+0x20)++0x03 line.long 0x00 "XD6,Exit Delay Stage N 6" hexmask.long.word 0x00 0.--15. 1. " XD ,Exit delay" width 0x0B tree.end ; tree "OCOTP_CTRL (On-Chip OTP Controller)" ; base ad:0x00 ; %include imx8x/ocotp.ph ad:0x00 ; tree.end tree "ASMC (Auxiliary System Mode Control)" base ad:0x41410000 width 10. rgroup.long 0x00++0x03 line.long 0x00 "SRS,System Reset Status Register" bitfld.long 0x00 12. " SACKERR ,Reset caused by peripheral failure to acknowledge attempt to enter stop mode" "Not occurred,Occurred" bitfld.long 0x00 10. " SW ,Reset caused by software setting of SYSRESETREQ bit" "Not occurred,Occurred" bitfld.long 0x00 9. " LOCKUP ,Reset caused by core LOCKUP event" "Not occurred,Occurred" bitfld.long 0x00 7. " POR ,Reset caused by power-on detection logic" "Not occurred,Occurred" newline bitfld.long 0x00 6. " RES ,Chip Reset caused by a source other than power-on detection logic" "Not occurred,Occurred" bitfld.long 0x00 5. " WDOG1 ,Reset caused by watchdog timer 1 timeout" "Not occurred,Occurred" bitfld.long 0x00 0. " WAKEUP ,Reset caused by LLWU module wakeup source" "Not occurred,Occurred" group.long 0x08++0x0B line.long 0x00 "PMPROT,Power Mode Protection Register" bitfld.long 0x00 7. " AHSRUN ,Allow high speed run mode" "Not allowed,Allowed" bitfld.long 0x00 5. " AVLP ,Allow very low power modes" "Not allowed,Allowed" bitfld.long 0x00 3. " ALLS ,Allow low-leakage stop mode" "Not allowed,Allowed" bitfld.long 0x00 1. " AVLLS ,Allow very-low-leakage stop mode" "Not allowed,Allowed" line.long 0x04 "PMCTRL,Power Mode Control Register" bitfld.long 0x04 5.--6. " RUNM ,Run mode control" "Normal,,Very-low-power,High speed" bitfld.long 0x04 0.--2. " STOPM ,Stop mode control" "Normal,,Very-low-power,Low-leakage,Very-low-leakage,?..." line.long 0x08 "STOPCTRL,Stop Control Register" bitfld.long 0x08 6.--7. " PSTOPO ,Partial stop option" "Normal,PSTOP1,PSTOP2,?..." rgroup.long 0x14++0x03 line.long 0x00 "PMSTAT,Power Mode Status Register" hexmask.long.byte 0x00 0.--7. 1. " PMSTAT ,Power mode status" rgroup.long 0xF0++0x07 "Time Stamp Timer Module (TSTMR)" line.long 0x00 "LOW,Time Stamp Timer Register Low" line.long 0x04 "HIGH,Time Stamp Timer Register High" width 0x0B tree.end tree "INTMUX (Interrupt Multiplexer)" base ad:0x41400000 width 14. group.long 0x0++0x03 "Channel 0" line.long 0x00 "CH0_CSR,Channel 0 Control Status Register" rbitfld.long 0x00 31. " IRQP ,Channel interrupt request pending" "Not pending,Pending" rbitfld.long 0x00 8.--11. " CHIN ,Channel instance number" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 4.--5. " IRQN ,Channel input number" "32 interrupt inputs,?..." newline bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND" bitfld.long 0x00 0. " RST ,Software reset" "No reset,Reset" rgroup.long (0x0+0x04)++0x03 line.long 0x00 "CH0_VEC,Channel 0 Vector Number Register" hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector number" newline group.long (0x0+0x10)++0x03 line.long 0x00 "CH0_IER_31_0,Channel 0 Interrupt Enable Register" bitfld.long 0x00 31. " INTE[31] ,Interrupt MU0_A0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Interrupt LPUART enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Interrupt LPIT enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Interrupt TPM enable" "Disabled,Enabled" rgroup.long (0x0+0x20)++0x03 line.long 0x00 "CH0_IPR_31_0,Channel 0 Interrupt Pending Register" bitfld.long 0x00 31. " INTP[31] ,Interrupt MU0_A0 pending" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 pending" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 pending" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 pending" "Not pending,Pending" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C pending" "Not pending,Pending" bitfld.long 0x00 7. " [7] ,Interrupt LPUART pending" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Interrupt LPIT pending" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Interrupt TPM pending" "Not pending,Pending" group.long 0x40++0x03 "Channel 1" line.long 0x00 "CH1_CSR,Channel 1 Control Status Register" rbitfld.long 0x00 31. " IRQP ,Channel interrupt request pending" "Not pending,Pending" rbitfld.long 0x00 8.--11. " CHIN ,Channel instance number" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 4.--5. " IRQN ,Channel input number" "32 interrupt inputs,?..." newline bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND" bitfld.long 0x00 0. " RST ,Software reset" "No reset,Reset" rgroup.long (0x40+0x04)++0x03 line.long 0x00 "CH1_VEC,Channel 1 Vector Number Register" hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector number" newline group.long (0x40+0x10)++0x03 line.long 0x00 "CH1_IER_31_0,Channel 1 Interrupt Enable Register" bitfld.long 0x00 31. " INTE[31] ,Interrupt MU0_A0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Interrupt LPUART enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Interrupt LPIT enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Interrupt TPM enable" "Disabled,Enabled" rgroup.long (0x40+0x20)++0x03 line.long 0x00 "CH1_IPR_31_0,Channel 1 Interrupt Pending Register" bitfld.long 0x00 31. " INTP[31] ,Interrupt MU0_A0 pending" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 pending" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 pending" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 pending" "Not pending,Pending" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C pending" "Not pending,Pending" bitfld.long 0x00 7. " [7] ,Interrupt LPUART pending" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Interrupt LPIT pending" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Interrupt TPM pending" "Not pending,Pending" group.long 0x80++0x03 "Channel 2" line.long 0x00 "CH2_CSR,Channel 2 Control Status Register" rbitfld.long 0x00 31. " IRQP ,Channel interrupt request pending" "Not pending,Pending" rbitfld.long 0x00 8.--11. " CHIN ,Channel instance number" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 4.--5. " IRQN ,Channel input number" "32 interrupt inputs,?..." newline bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND" bitfld.long 0x00 0. " RST ,Software reset" "No reset,Reset" rgroup.long (0x80+0x04)++0x03 line.long 0x00 "CH2_VEC,Channel 2 Vector Number Register" hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector number" newline group.long (0x80+0x10)++0x03 line.long 0x00 "CH2_IER_31_0,Channel 2 Interrupt Enable Register" bitfld.long 0x00 31. " INTE[31] ,Interrupt MU0_A0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Interrupt LPUART enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Interrupt LPIT enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Interrupt TPM enable" "Disabled,Enabled" rgroup.long (0x80+0x20)++0x03 line.long 0x00 "CH2_IPR_31_0,Channel 2 Interrupt Pending Register" bitfld.long 0x00 31. " INTP[31] ,Interrupt MU0_A0 pending" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 pending" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 pending" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 pending" "Not pending,Pending" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C pending" "Not pending,Pending" bitfld.long 0x00 7. " [7] ,Interrupt LPUART pending" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Interrupt LPIT pending" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Interrupt TPM pending" "Not pending,Pending" group.long 0xC0++0x03 "Channel 3" line.long 0x00 "CH3_CSR,Channel 3 Control Status Register" rbitfld.long 0x00 31. " IRQP ,Channel interrupt request pending" "Not pending,Pending" rbitfld.long 0x00 8.--11. " CHIN ,Channel instance number" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 4.--5. " IRQN ,Channel input number" "32 interrupt inputs,?..." newline bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND" bitfld.long 0x00 0. " RST ,Software reset" "No reset,Reset" rgroup.long (0xC0+0x04)++0x03 line.long 0x00 "CH3_VEC,Channel 3 Vector Number Register" hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector number" newline group.long (0xC0+0x10)++0x03 line.long 0x00 "CH3_IER_31_0,Channel 3 Interrupt Enable Register" bitfld.long 0x00 31. " INTE[31] ,Interrupt MU0_A0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Interrupt LPUART enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Interrupt LPIT enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Interrupt TPM enable" "Disabled,Enabled" rgroup.long (0xC0+0x20)++0x03 line.long 0x00 "CH3_IPR_31_0,Channel 3 Interrupt Pending Register" bitfld.long 0x00 31. " INTP[31] ,Interrupt MU0_A0 pending" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 pending" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 pending" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 pending" "Not pending,Pending" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C pending" "Not pending,Pending" bitfld.long 0x00 7. " [7] ,Interrupt LPUART pending" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Interrupt LPIT pending" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Interrupt TPM pending" "Not pending,Pending" group.long 0x100++0x03 "Channel 4" line.long 0x00 "CH4_CSR,Channel 4 Control Status Register" rbitfld.long 0x00 31. " IRQP ,Channel interrupt request pending" "Not pending,Pending" rbitfld.long 0x00 8.--11. " CHIN ,Channel instance number" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 4.--5. " IRQN ,Channel input number" "32 interrupt inputs,?..." newline bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND" bitfld.long 0x00 0. " RST ,Software reset" "No reset,Reset" rgroup.long (0x100+0x04)++0x03 line.long 0x00 "CH4_VEC,Channel 4 Vector Number Register" hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector number" newline group.long (0x100+0x10)++0x03 line.long 0x00 "CH4_IER_31_0,Channel 4 Interrupt Enable Register" bitfld.long 0x00 31. " INTE[31] ,Interrupt MU0_A0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Interrupt LPUART enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Interrupt LPIT enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Interrupt TPM enable" "Disabled,Enabled" rgroup.long (0x100+0x20)++0x03 line.long 0x00 "CH4_IPR_31_0,Channel 4 Interrupt Pending Register" bitfld.long 0x00 31. " INTP[31] ,Interrupt MU0_A0 pending" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 pending" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 pending" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 pending" "Not pending,Pending" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C pending" "Not pending,Pending" bitfld.long 0x00 7. " [7] ,Interrupt LPUART pending" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Interrupt LPIT pending" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Interrupt TPM pending" "Not pending,Pending" group.long 0x140++0x03 "Channel 5" line.long 0x00 "CH5_CSR,Channel 5 Control Status Register" rbitfld.long 0x00 31. " IRQP ,Channel interrupt request pending" "Not pending,Pending" rbitfld.long 0x00 8.--11. " CHIN ,Channel instance number" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 4.--5. " IRQN ,Channel input number" "32 interrupt inputs,?..." newline bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND" bitfld.long 0x00 0. " RST ,Software reset" "No reset,Reset" rgroup.long (0x140+0x04)++0x03 line.long 0x00 "CH5_VEC,Channel 5 Vector Number Register" hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector number" newline group.long (0x140+0x10)++0x03 line.long 0x00 "CH5_IER_31_0,Channel 5 Interrupt Enable Register" bitfld.long 0x00 31. " INTE[31] ,Interrupt MU0_A0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Interrupt LPUART enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Interrupt LPIT enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Interrupt TPM enable" "Disabled,Enabled" rgroup.long (0x140+0x20)++0x03 line.long 0x00 "CH5_IPR_31_0,Channel 5 Interrupt Pending Register" bitfld.long 0x00 31. " INTP[31] ,Interrupt MU0_A0 pending" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 pending" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 pending" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 pending" "Not pending,Pending" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C pending" "Not pending,Pending" bitfld.long 0x00 7. " [7] ,Interrupt LPUART pending" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Interrupt LPIT pending" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Interrupt TPM pending" "Not pending,Pending" group.long 0x180++0x03 "Channel 6" line.long 0x00 "CH6_CSR,Channel 6 Control Status Register" rbitfld.long 0x00 31. " IRQP ,Channel interrupt request pending" "Not pending,Pending" rbitfld.long 0x00 8.--11. " CHIN ,Channel instance number" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 4.--5. " IRQN ,Channel input number" "32 interrupt inputs,?..." newline bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND" bitfld.long 0x00 0. " RST ,Software reset" "No reset,Reset" rgroup.long (0x180+0x04)++0x03 line.long 0x00 "CH6_VEC,Channel 6 Vector Number Register" hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector number" newline group.long (0x180+0x10)++0x03 line.long 0x00 "CH6_IER_31_0,Channel 6 Interrupt Enable Register" bitfld.long 0x00 31. " INTE[31] ,Interrupt MU0_A0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Interrupt LPUART enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Interrupt LPIT enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Interrupt TPM enable" "Disabled,Enabled" rgroup.long (0x180+0x20)++0x03 line.long 0x00 "CH6_IPR_31_0,Channel 6 Interrupt Pending Register" bitfld.long 0x00 31. " INTP[31] ,Interrupt MU0_A0 pending" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 pending" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 pending" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 pending" "Not pending,Pending" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C pending" "Not pending,Pending" bitfld.long 0x00 7. " [7] ,Interrupt LPUART pending" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Interrupt LPIT pending" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Interrupt TPM pending" "Not pending,Pending" group.long 0x1C0++0x03 "Channel 7" line.long 0x00 "CH7_CSR,Channel 7 Control Status Register" rbitfld.long 0x00 31. " IRQP ,Channel interrupt request pending" "Not pending,Pending" rbitfld.long 0x00 8.--11. " CHIN ,Channel instance number" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 4.--5. " IRQN ,Channel input number" "32 interrupt inputs,?..." newline bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND" bitfld.long 0x00 0. " RST ,Software reset" "No reset,Reset" rgroup.long (0x1C0+0x04)++0x03 line.long 0x00 "CH7_VEC,Channel 7 Vector Number Register" hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector number" newline group.long (0x1C0+0x10)++0x03 line.long 0x00 "CH7_IER_31_0,Channel 7 Interrupt Enable Register" bitfld.long 0x00 31. " INTE[31] ,Interrupt MU0_A0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Interrupt LPUART enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Interrupt LPIT enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Interrupt TPM enable" "Disabled,Enabled" rgroup.long (0x1C0+0x20)++0x03 line.long 0x00 "CH7_IPR_31_0,Channel 7 Interrupt Pending Register" bitfld.long 0x00 31. " INTP[31] ,Interrupt MU0_A0 pending" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 pending" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 pending" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 pending" "Not pending,Pending" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C pending" "Not pending,Pending" bitfld.long 0x00 7. " [7] ,Interrupt LPUART pending" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Interrupt LPIT pending" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Interrupt TPM pending" "Not pending,Pending" width 0x0B tree.end tree.end elif (cpuis("IMX8DX")||cpuis("IMX8DXP")||cpuis("IMX8QXP")) tree.open "SCU (System Controller Unit)" tree "LPI2C (Low-Power I2C Controller)" base ad:0x33230000 width 8. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number" line.long 0x04 "PARAM,Parameter Register" bitfld.long 0x04 8.--11. " MRXFIFO ,Master receive FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x04 0.--3. " MTXFIFO ,Master transmit FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" group.long 0x10++0x13 line.long 0x00 "MCR,Master Control Register" bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset" bitfld.long 0x00 3. " DBGEN ,Debug enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " MEN ,Master enable" "Disabled,Enabled" line.long 0x04 "MSR,Master Status Register" rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x04 24. " MBF ,Master busy flag" "Idle,Busy" eventfld.long 0x04 14. " DMF ,Data match flag" "Not received,Received" eventfld.long 0x04 13. " PLTF ,Pin low timeout flag" "Not occurred/disabled,Occurred" newline eventfld.long 0x04 12. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x04 11. " ALF ,Arbitration lost flag" "Not lost,Lost" eventfld.long 0x04 10. " NDF ,NACK detect flag" "Not detected,Detected" eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected" newline eventfld.long 0x04 8. " EPF ,End packet flag" "Not generated/Repeated,Generated/Repeated" rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "MIER,Master Interrupt Enable Register" bitfld.long 0x08 14. " DMIE ,Data match interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " PLTIE ,Pin low timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " FEIE ,FIFO error interrupt disable" "No,Yes" newline bitfld.long 0x08 11. " ALIE ,Arbitration lost interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " NDIE ,NACK detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " EPIE ,End packet interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "MDER,Master DMA Enable Register" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" line.long 0x10 "MCFGR0,Master Configuration Register 0" bitfld.long 0x10 9. " RDMO ,Receive data match only" "Stored,Discarded" bitfld.long 0x10 8. " CIRFIFO ,Circular FIFO enable" "Disabled,Enabled" bitfld.long 0x10 2. " HRSEL ,Host request select" "HREQ pin,Input trigger" newline bitfld.long 0x10 1. " HRPOL ,Host request polarity" "Active low,Active high" bitfld.long 0x10 0. " HREN ,Host request enable" "Disabled,Enabled" newline if (((per.l(ad:0x33230000+0x10))&0x01)==0x01) rgroup.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Disabled,,1st word = MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "SCL,SCL or SDA" newline bitfld.long 0x00 9. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "No effect,Enabled" bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" else group.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Disabled,,1st word = MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "On SCL low too long,On SCL or SDA low too long" newline bitfld.long 0x00 9. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "No effect,Enabled" bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" endif newline if ((((per.l(ad:0x33230000+0x10))&0x01)==0x00)||(((per.l(ad:0x33230000+0x14))&0x1000000)==0x00)) group.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" else rgroup.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" endif if (((per.l(ad:0x33230000+0x10))&0x01)==0x01) rgroup.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x58++0x03 line.long 0x00 "MFCR,Master FIFO Control Register" bitfld.long 0x00 16.--17. " RXWATER ,Receive FIFO watermark" "0,1,2,3" bitfld.long 0x00 0.--1. " TXWATER ,Transmit FIFO watermark" "0,1,2,3" rgroup.long 0x5C++0x03 line.long 0x00 "MFSR,Master FIFO Status Register" bitfld.long 0x00 16.--18. " RXCOUNT ,Receive FIFO count" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " TXCOUNT ,Transmit FIFO count" "0,1,2,3,4,5,6,7" newline wgroup.long 0x60++0x03 line.long 0x00 "MTDR,Master Transmit Data Register" bitfld.long 0x00 8.--10. " CMD ,Command data" "Transmit,Receive,Generate STOP,Receive and discard,START and transmit,START and transmit (NACK returned),START and transmit (high speed mode),START and transmit high speed mode (NACK returned)" newline hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data" newline hgroup.long 0x70++0x03 hide.long 0x00 "MRDR,Master Receive Data Register" in newline group.long 0x110++0x0F line.long 0x00 "SCR,Slave Control Register" bitfld.long 0x00 9. " RRF ,Receive FIFO reset" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Transmit FIFO reset" "No effect,Reset" bitfld.long 0x00 5. " FILTDZ ,Filter doze enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " FILTEN ,Filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " SEN ,Slave enable" "Disabled,Enabled" line.long 0x04 "SSR,Slave Status Register" rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x04 24. " SBF ,Slave busy flag" "Idle,Busy" rbitfld.long 0x04 15. " SARF ,SMBus alert response flag" "Not detected,Detected" rbitfld.long 0x04 14. " GCF ,General call flag" "Not detected,Detected" newline rbitfld.long 0x04 13. " AM1F ,Address match 1 flag" "Not matched,Matched" rbitfld.long 0x04 12. " AM0F ,Address match 0 flag" "Not matched,Matched" eventfld.long 0x04 11. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x04 10. " BEF ,Bit error flag" "No error,Error" newline eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected" eventfld.long 0x04 8. " RSF ,Repeated start flag" "Not detected,Detected" rbitfld.long 0x04 3. " TAF ,Transmit ACK flag" "Not required,Required" rbitfld.long 0x04 2. " AVF ,Address valid flag" "Invalid,Valid" newline rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "SIER,Slave Interrupt Enable Register" bitfld.long 0x08 15. " SARIE ,SMBus alert response interrupt enable" "Disabled,Enabled" bitfld.long 0x08 14. " GCIE ,General call interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " AM1F ,Address match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " AM0IE ,Address match 0 interrupt disable" "No,Yes" newline bitfld.long 0x08 11. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " BEIE ,Bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 8. " RSIE ,Repeated start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " TAIE ,Transmit ACK interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " AVIE ,Address valid interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "SDER,Slave DMA Enable Register" bitfld.long 0x0C 2. " AVDE ,Address valid DMA enable" "Disabled,Enabled" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" newline if (((per.l(ad:0x33230000+0x110))&0x01)==0x01) rgroup.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration match" "0 (7-bit),0 (10-bit),0 (7-bit) / 1 (7-bit),0 (10-bit) / 1 (10-bit),0 (7-bit) / 1 (10-bit),0 (10-bit) / 1 (7-bit),From 0 (7-bit) to 1 (7-bit),From 0 (10-bit) to 1 (10-bit)" bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" bitfld.long 0x00 12. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return data / clear RDF,Return address / clear AVF" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer,On TDR empty" bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration match" "0 (7-bit),0 (10-bit),0 (7-bit) / 1 (7-bit),0 (10-bit) / 1 (10-bit),0 (7-bit) / 1 (10-bit),0 (10-bit) / 1 (7-bit),From 0 (7-bit) to 1 (7-bit),From 0 (10-bit) to 1 (10-bit)" bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" bitfld.long 0x00 12. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return data / clear RDF,Return address / clear AVF" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer,On TDR empty" bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline if (((per.l(ad:0x33230000+0x110))&0x01)==0x01) rgroup.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" else group.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" endif rgroup.long 0x150++0x03 line.long 0x00 "SASR,Slave Address Status Register" bitfld.long 0x00 14. " ANV ,Address invalid" "No,Yes" hexmask.long.word 0x00 0.--10. 0x01 " RADDR ,Received address" if (((per.l(ad:0x33230000+0x124))&0x08)==0x08) group.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,NACK transmit" "ACK,NACK" else rgroup.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,NACK transmit" "ACK,NACK" endif wgroup.long 0x160++0x03 line.long 0x00 "STDR,Slave Transmit Data Register" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data" rgroup.long 0x170++0x03 line.long 0x00 "SRDR,Slave Receive Data Register" bitfld.long 0x00 15. " SOF ,Start of frame" "Not the first data word,First data word" bitfld.long 0x00 14. " RXEMPTY ,RX empty" "Not empty,Empty" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data receive" width 0x0B tree.end tree "LPIT" base ad:0x33210000 endian.be width 13. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.word 0x00 16.--31. 1. " FEATURE ,Feature number" hexmask.long.byte 0x00 8.--15. 1. " MINOR ,Minor version number" hexmask.long.byte 0x00 0.--7. 1. " MAJOR ,Major version number" line.long 0x04 "PARAM,Parameter Register" hexmask.long.byte 0x04 24.--31. 1. " CHANNEL ,Number of timer channels" hexmask.long.byte 0x04 16.--23. 1. " EXT_TRIG ,Number of external trigger inputs" group.long 0x08++0x03 line.long 0x00 "MCR,Module Control Register" bitfld.long 0x00 31. " M_CEN ,Module clock enable" "Disabled,Enabled" bitfld.long 0x00 30. " SW_RST ,Software reset bit" "No reset,Reset" bitfld.long 0x00 29. " DOZE_EN ,DOZE mode enable bit" "Disabled,Enabled" bitfld.long 0x00 28. " DBG_EN ,Debug enable bit" "Disabled,Enabled" if (((per.l.be(ad:0x33210000+0x08))&0x01)==0x01) group.long 0x0C++0x03 line.long 0x00 "MSR,Module Status Register" eventfld.long 0x00 31. " TIF0 ,Channel 0 timer interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 30. " TIF1 ,Channel 1 timer interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 29. " TIF2 ,Channel 2 timer interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 28. " TIF3 ,Channel 3 timer interrupt flag" "No interrupt,Interrupt" else rgroup.long 0x0C++0x03 line.long 0x00 "MSR,Module Status Register" bitfld.long 0x00 31. " TIF0 ,Channel 0 timer interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 30. " TIF1 ,Channel 1 timer interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 29. " TIF2 ,Channel 2 timer interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 28. " TIF3 ,Channel 3 timer interrupt flag" "No interrupt,Interrupt" endif group.long 0x10++0x03 line.long 0x00 "MIER,Module Interrupt Enable Register" bitfld.long 0x00 31. " TIE0 ,Channel 0 timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 30. " TIE1 ,Channel 1 timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 29. " TIE2 ,Channel 2 timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " TIE3 ,Channel 3 timer interrupt enable" "Disabled,Enabled" if (((per.l.be(ad:0x33210000+0x08))&0x01)==0x01) group.long 0x14++0x03 line.long 0x00 "TEN_SET/CLR,Set/Clear Timer Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " T_EN_0 ,Timer 0 enable" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " T_EN_1 ,Timer 1 enable" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x04 29. " T_EN_2 ,Timer 2 enable" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " T_EN_3 ,Timer 3 enable" "Disabled,Enabled" else rgroup.long 0x14++0x07 line.long 0x00 "SETTEN,Set Timer Enable Register" bitfld.long 0x00 31. " SET_T_EN_0 ,Set timer 0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " SET_T_EN_1 ,Set timer 1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " SET_T_EN_2 ,Set timer 2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " SET_T_EN_3 ,Set timer 3 enable" "Disabled,Enabled" line.long 0x04 "CLRTEN,Clear Timer Enable Register" bitfld.long 0x04 31. " CLR_T_EN_0 ,Clear timer 0 enable" "Disabled,Enabled" bitfld.long 0x04 30. " CLR_T_EN_1 ,Clear timer 1 enable" "Disabled,Enabled" bitfld.long 0x04 29. " CLR_T_EN_2 ,Clear timer 2 enable" "Disabled,Enabled" bitfld.long 0x04 28. " CLR_T_EN_3 ,Clear timer 3 enable" "Disabled,Enabled" endif if (((per.l.be(ad:0x33210000+0x08))&0x01)==0x01) group.long 0x20++0x03 line.long 0x00 "TVAL0,Timer Value Register" else rgroup.long 0x20++0x03 line.long 0x00 "TVAL0,Timer Value Register" endif rgroup.long (0x20+0x04)++0x03 line.long 0x00 "CVAL0,Current Timer Value Register" if (((per.l.be(ad:0x33210000+0x08))&0x01)==0x01) if (((per.l.be(ad:0x33210000+0x20+0x08))&0x01)==0x00) group.long (0x20+0x08)++0x03 line.long 0x00 "TCTRL0,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Immediately,Rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." else group.long (0x20+0x08)++0x03 line.long 0x00 "TCTRL0,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" rbitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." endif else rgroup.long (0x20+0x08)++0x03 line.long 0x00 "TCTRL0,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." endif if (((per.l.be(ad:0x33210000+0x08))&0x01)==0x01) group.long 0x30++0x03 line.long 0x00 "TVAL1,Timer Value Register" else rgroup.long 0x30++0x03 line.long 0x00 "TVAL1,Timer Value Register" endif rgroup.long (0x30+0x04)++0x03 line.long 0x00 "CVAL1,Current Timer Value Register" if (((per.l.be(ad:0x33210000+0x08))&0x01)==0x01) if (((per.l.be(ad:0x33210000+0x30+0x08))&0x01)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "TCTRL1,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Immediately,Rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." else group.long (0x30+0x08)++0x03 line.long 0x00 "TCTRL1,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" rbitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." endif else rgroup.long (0x30+0x08)++0x03 line.long 0x00 "TCTRL1,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." endif if (((per.l.be(ad:0x33210000+0x08))&0x01)==0x01) group.long 0x40++0x03 line.long 0x00 "TVAL2,Timer Value Register" else rgroup.long 0x40++0x03 line.long 0x00 "TVAL2,Timer Value Register" endif rgroup.long (0x40+0x04)++0x03 line.long 0x00 "CVAL2,Current Timer Value Register" if (((per.l.be(ad:0x33210000+0x08))&0x01)==0x01) if (((per.l.be(ad:0x33210000+0x40+0x08))&0x01)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "TCTRL2,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Immediately,Rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." else group.long (0x40+0x08)++0x03 line.long 0x00 "TCTRL2,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" rbitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." endif else rgroup.long (0x40+0x08)++0x03 line.long 0x00 "TCTRL2,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." endif if (((per.l.be(ad:0x33210000+0x08))&0x01)==0x01) group.long 0x50++0x03 line.long 0x00 "TVAL3,Timer Value Register" else rgroup.long 0x50++0x03 line.long 0x00 "TVAL3,Timer Value Register" endif rgroup.long (0x50+0x04)++0x03 line.long 0x00 "CVAL3,Current Timer Value Register" if (((per.l.be(ad:0x33210000+0x08))&0x01)==0x01) if (((per.l.be(ad:0x33210000+0x50+0x08))&0x01)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "TCTRL3,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Immediately,Rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." else group.long (0x50+0x08)++0x03 line.long 0x00 "TCTRL3,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" rbitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." endif else rgroup.long (0x50+0x08)++0x03 line.long 0x00 "TCTRL3,Timer Control Register" bitfld.long 0x00 31. " T_EN ,Timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHAIN ,Chain channel" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture" bitfld.long 0x00 15. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge" newline bitfld.long 0x00 14. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped" bitfld.long 0x00 13. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 8. " TRG_SRC ,Trigger source" "External,Internal" bitfld.long 0x00 4.--7. " TRG_SEL ,Trigger select" "Timer CH0,Timer CH1,Timer CH2,Timer CH3,?..." endif endian.le width 0x0B tree.end tree "TPM" base ad:0x33200000 endian.be width 9. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature identification number" line.long 0x04 "PARAM,Parameter Register" hexmask.long.byte 0x04 16.--23. 1. " WIDTH ,Counter width" hexmask.long.byte 0x04 8.--15. 1. " TRIG ,Trigger count" hexmask.long.byte 0x04 0.--7. 1. " CHAN ,Channel count" group.long 0x08++0x03 line.long 0x00 "GLOBAL,TPM Global Register" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" if (((per.l.be(ad:0x33200000+0x10))&0x18)==0x00) group.long 0x10++0x03 line.long 0x00 "SC,Status And Control Register" bitfld.long 0x00 8. " DMA ,DMA enable" "Disabled,Enabled" eventfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-down counting" bitfld.long 0x00 3.--4. " CMOD ,Clock mode select" "Disabled,Counter clock,Clock rising edge,Input rising edge" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x10++0x03 line.long 0x00 "SC,Status And Control Register" bitfld.long 0x00 8. " DMA ,DMA enable" "Disabled,Enabled" eventfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-down counting" bitfld.long 0x00 3.--4. " CMOD ,Clock mode select" "Disabled,Counter clock,Clock rising edge,Input rising edge" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif group.long 0x14++0x0B line.long 0x00 "CNT,Counter Register" line.long 0x04 "MOD,Modulo Register" line.long 0x08 "STATUS,Capture And Compare Status Register" eventfld.long 0x08 8. " TOF ,Timer overflow flag" "No overflow,Overflow" eventfld.long 0x08 5. " CH5F ,Channel 5 flag" "Not occurred,Occurred" eventfld.long 0x08 4. " CH4F ,Channel 4 flag" "Not occurred,Occurred" newline eventfld.long 0x08 3. " CH3F ,Channel 3 flag" "Not occurred,Occurred" eventfld.long 0x08 2. " CH2F ,Channel 2 flag" "Not occurred,Occurred" eventfld.long 0x08 1. " CH1F ,Channel 1 flag" "Not occurred,Occurred" newline eventfld.long 0x08 0. " CH0F ,Channel 0 flag" "Not occurred,Occurred" if (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x20)&0x30)==0x00)) group.long 0x20++0x03 line.long 0x00 "C0SC,Channel 0 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x20)&0x30)==0x10)) group.long 0x20++0x03 line.long 0x00 "C0SC,Channel 0 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Not used,Toggle output,Clear output,Set output" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x20)&0x30)==0x20)) group.long 0x20++0x03 line.long 0x00 "C0SC,Channel 0 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x20)&0x30)==0x30)) group.long 0x20++0x03 line.long 0x00 "C0SC,Channel 0 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Pulse output high,Pulse output low,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x20)&&((per.l.be(ad:0x33200000+0x20)&0x30)==0x20)) group.long 0x20++0x03 line.long 0x00 "C0SC,Channel 0 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x20++0x03 hide.long 0x00 "C0SC,Channel 0 Status And Control Register" newline endif group.long (0x20+0x04)++0x03 line.long 0x00 "C0V,Channel 0 Value Register" if (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x28)&0x30)==0x00)) group.long 0x28++0x03 line.long 0x00 "C1SC,Channel 1 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x28)&0x30)==0x10)) group.long 0x28++0x03 line.long 0x00 "C1SC,Channel 1 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Not used,Toggle output,Clear output,Set output" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x28)&0x30)==0x20)) group.long 0x28++0x03 line.long 0x00 "C1SC,Channel 1 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x28)&0x30)==0x30)) group.long 0x28++0x03 line.long 0x00 "C1SC,Channel 1 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Pulse output high,Pulse output low,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x20)&&((per.l.be(ad:0x33200000+0x28)&0x30)==0x20)) group.long 0x28++0x03 line.long 0x00 "C1SC,Channel 1 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x28++0x03 hide.long 0x00 "C1SC,Channel 1 Status And Control Register" newline endif group.long (0x28+0x04)++0x03 line.long 0x00 "C1V,Channel 1 Value Register" if (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x30)&0x30)==0x00)) group.long 0x30++0x03 line.long 0x00 "C2SC,Channel 2 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 2 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x30)&0x30)==0x10)) group.long 0x30++0x03 line.long 0x00 "C2SC,Channel 2 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 2 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Not used,Toggle output,Clear output,Set output" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x30)&0x30)==0x20)) group.long 0x30++0x03 line.long 0x00 "C2SC,Channel 2 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 2 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x30)&0x30)==0x30)) group.long 0x30++0x03 line.long 0x00 "C2SC,Channel 2 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 2 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Pulse output high,Pulse output low,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x20)&&((per.l.be(ad:0x33200000+0x30)&0x30)==0x20)) group.long 0x30++0x03 line.long 0x00 "C2SC,Channel 2 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 2 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x30++0x03 hide.long 0x00 "C2SC,Channel 2 Status And Control Register" newline endif group.long (0x30+0x04)++0x03 line.long 0x00 "C2V,Channel 2 Value Register" if (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x38)&0x30)==0x00)) group.long 0x38++0x03 line.long 0x00 "C3SC,Channel 3 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 3 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x38)&0x30)==0x10)) group.long 0x38++0x03 line.long 0x00 "C3SC,Channel 3 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 3 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Not used,Toggle output,Clear output,Set output" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x38)&0x30)==0x20)) group.long 0x38++0x03 line.long 0x00 "C3SC,Channel 3 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 3 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x38)&0x30)==0x30)) group.long 0x38++0x03 line.long 0x00 "C3SC,Channel 3 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 3 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Pulse output high,Pulse output low,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x20)&&((per.l.be(ad:0x33200000+0x38)&0x30)==0x20)) group.long 0x38++0x03 line.long 0x00 "C3SC,Channel 3 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 3 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x38++0x03 hide.long 0x00 "C3SC,Channel 3 Status And Control Register" newline endif group.long (0x38+0x04)++0x03 line.long 0x00 "C3V,Channel 3 Value Register" if (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x40)&0x30)==0x00)) group.long 0x40++0x03 line.long 0x00 "C4SC,Channel 4 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x40)&0x30)==0x10)) group.long 0x40++0x03 line.long 0x00 "C4SC,Channel 4 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Not used,Toggle output,Clear output,Set output" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x40)&0x30)==0x20)) group.long 0x40++0x03 line.long 0x00 "C4SC,Channel 4 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x40)&0x30)==0x30)) group.long 0x40++0x03 line.long 0x00 "C4SC,Channel 4 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Pulse output high,Pulse output low,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x20)&&((per.l.be(ad:0x33200000+0x40)&0x30)==0x20)) group.long 0x40++0x03 line.long 0x00 "C4SC,Channel 4 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x40++0x03 hide.long 0x00 "C4SC,Channel 4 Status And Control Register" newline endif group.long (0x40+0x04)++0x03 line.long 0x00 "C4V,Channel 4 Value Register" if (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x48)&0x30)==0x00)) group.long 0x48++0x03 line.long 0x00 "C5SC,Channel 5 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 5 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x48)&0x30)==0x10)) group.long 0x48++0x03 line.long 0x00 "C5SC,Channel 5 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 5 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Not used,Toggle output,Clear output,Set output" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x48)&0x30)==0x20)) group.long 0x48++0x03 line.long 0x00 "C5SC,Channel 5 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 5 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x00)&&((per.l.be(ad:0x33200000+0x48)&0x30)==0x30)) group.long 0x48++0x03 line.long 0x00 "C5SC,Channel 5 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 5 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Pulse output high,Pulse output low,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x33200000+0x10)&0x20)==0x20)&&((per.l.be(ad:0x33200000+0x48)&0x30)==0x20)) group.long 0x48++0x03 line.long 0x00 "C5SC,Channel 5 Status And Control Register" eventfld.long 0x00 7. " CHF ,Channel 5 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "High-true pulses,Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x48++0x03 hide.long 0x00 "C5SC,Channel 5 Status And Control Register" newline endif group.long (0x48+0x04)++0x03 line.long 0x00 "C5V,Channel 5 Value Register" group.long 0x64++0x03 line.long 0x00 "COMBINE,Combine Channel Register" bitfld.long 0x00 17. " COMSWAP2 ,Combine channels 4 and 5 swap" "Even,Odd" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" bitfld.long 0x00 9. " COMSWAP1 ,Combine channels 2 and 3 swap" "Even,Odd" newline bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" bitfld.long 0x00 1. " COMSWAP0 ,Combine channels 0 and 1 swap" "Even,Odd" bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" group.long 0x6C++0x07 line.long 0x00 "TRIG,Channel Trigger Register" bitfld.long 0x00 5. " TRIG5 ,Channel 5 trigger" "No effect,Used" bitfld.long 0x00 4. " TRIG4 ,Channel 4 trigger" "No effect,Used" bitfld.long 0x00 3. " TRIG3 ,Channel 3 trigger" "No effect,Used" newline bitfld.long 0x00 2. " TRIG2 ,Channel 2 trigger" "No effect,Used" bitfld.long 0x00 1. " TRIG1 ,Channel 1 trigger" "No effect,Used" bitfld.long 0x00 0. " TRIG0 ,Channel 0 trigger" "No effect,Used" line.long 0x04 "POL,Channel Polarity Register" bitfld.long 0x04 5. " POL5 ,Channel 5 polarity" "High,Low" bitfld.long 0x04 4. " POL4 ,Channel 4 polarity" "High,Low" bitfld.long 0x04 3. " POL3 ,Channel 3 polarity" "High,Low" newline bitfld.long 0x04 2. " POL2 ,Channel 2 polarity" "High,Low" bitfld.long 0x04 1. " POL1 ,Channel 1 polarity" "High,Low" bitfld.long 0x04 0. " POL0 ,Channel 0 polarity" "High,Low" group.long 0x78++0x03 line.long 0x00 "FILTER,Filter Control Register" bitfld.long 0x00 20.--23. " CH5FVAL ,Channel 5 filter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CH4FVAL ,Channel 4 filter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 filter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 filter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 filter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 filter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status Register" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase,Count and direction" rbitfld.long 0x00 2. " QUADIR ,Counter direction in quadrature decode mode" "Decreased,Increased" rbitfld.long 0x00 1. " TOFDIR ,TOF bit set status" "Bottom,Top" newline bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" if (((per.l.be(ad:0x33200000+0x10))&0x18)==0x00) group.long 0x84++0x03 line.long 0x00 "CONF,Configuration Register" bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" ",CH0,CH1,CH0/CH1,CH2,CH0/CH2,CH1/CH2,CH0/CH1/CH2,CH3,CH0/CH3,CH1/CH3,CH0/CH1/CH3,CH2/CH3,CH0/CH2/CH3,CH1/CH2/CH3,CH0/CH1/CH2/CH3" bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "High,Low" newline bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled" bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Disabled,Enabled" newline bitfld.long 0x00 16. " CSOT ,Counter start trigger" "Immediately,Rising edge" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "Paused,,,Continued" bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled" else group.long 0x84++0x03 line.long 0x00 "CONF,Configuration Register" rbitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" ",CH0,CH1,CH0/CH1,CH2,CH0/CH2,CH1/CH2,CH0/CH1/CH2,CH3,CH0/CH3,CH1/CH3,CH0/CH1/CH3,CH2/CH3,CH0/CH2/CH3,CH1/CH2/CH3,CH0/CH1/CH2/CH3" rbitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal" rbitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "High,Low" newline rbitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled" rbitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded" rbitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Disabled,Enabled" newline rbitfld.long 0x00 16. " CSOT ,Counter start trigger" "Immediately,Rising edge" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "Paused,,,Continued" bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled" endif endian.le width 0x0B tree.end tree "LPUART (Low Power Universal Asynchronous Receiver/Transmitter)" base ad:0x33220000 width 8. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature identification number" line.long 0x04 "PARAM,Parameter Register" hexmask.long.byte 0x04 8.--15. 1. " RXFIFO ,Receive FIFO size" hexmask.long.byte 0x04 0.--7. 1. " TXFIFO ,Transmit FIFO size" group.long 0x08++0x03 line.long 0x00 "GLOBAL,Global Register" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" if (((per.l(ad:0x33220000+0x18))&0xC0000)==0x00) group.long 0x0C++0x03 line.long 0x00 "PINCFG,Pin Configuration Register" bitfld.long 0x00 0.--1. " TRGSEL ,Trigger select" "Disabled,Instead RX in,Instead CTS in,TX out modulation" else rgroup.long 0x0C++0x03 line.long 0x00 "PINCFG,Pin Configuration Register" bitfld.long 0x00 0.--1. " TRGSEL ,Trigger select" "Disabled,Instead RX in,Instead CTS in,TX out modulation" endif group.long 0x10++0x07 line.long 0x00 "BAUD,Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" bitfld.long 0x00 29. " M10 ,10-bit mode select" "7/8/9 bit,10 bit" newline bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" "16x,,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 20. " RIDMAE ,Receiver idle DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " SBNS ,Stop bit number select" "One,Two" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" bitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" bitfld.long 0x04 26. " BRK13 ,Break character generation length" "9-13 bit,12-15 bit" newline bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" newline eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" newline if (((per.l(ad:0x33220000+0x18))&0xC0000)==0x00) if ((per.b(ad:0x33220000+0x18)&0x08)==0x08) group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" newline bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,LPUART in Doze mode enabled" "LPUART enabled,LPUART disabled" newline bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" else group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" newline bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,LPUART in Doze mode enabled" "LPUART enabled,LPUART disabled" newline bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif else group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" rbitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" rbitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" rbitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline rbitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" rbitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline rbitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" rbitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" newline rbitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" rbitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" rbitfld.long 0x00 6. " DOZEEN ,LPUART in Doze mode enabled" "LPUART enabled,LPUART disabled" newline rbitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" rbitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" rbitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline rbitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" rbitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" rbitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif group.long 0x1C++0x07 line.long 0x00 "DATA,Data Register" rbitfld.long 0x00 15. " NOISY ,Current received dataword noise" "Not noisy,Noisy" rbitfld.long 0x00 14. " PARITYE ,Current received dataword parity error" "No error,Error" bitfld.long 0x00 13. " FRETSC ,Current received dataword frame error/Transmit special character" "No error/Normal character,Error/Special character" newline rbitfld.long 0x00 12. " RXEMPT ,Receive buffer empty" "Not empty,Empty" rbitfld.long 0x00 11. " IDLINE ,Receiver line idle status before receiving current character" "Not idle,Idle" newline bitfld.long 0x00 9. " R9T9 ,Read receive data buffer 9 or write transmit data buffer 9" "Low,High" bitfld.long 0x00 8. " R8T8 ,Read receive data buffer 8 or write transmit data buffer 8" "Low,High" bitfld.long 0x00 7. " R7T7 ,Read receive data buffer 7 or write transmit data buffer 7" "Low,High" newline bitfld.long 0x00 6. " R6T6 ,Read receive data buffer 6 or write transmit data buffer 6" "Low,High" bitfld.long 0x00 5. " R5T5 ,Read receive data buffer 5 or write transmit data buffer 5" "Low,High" bitfld.long 0x00 4. " R4T4 ,Read receive data buffer 4 or write transmit data buffer 4" "Low,High" newline bitfld.long 0x00 3. " R3T3 ,Read receive data buffer 3 or write transmit data buffer 3" "Low,High" bitfld.long 0x00 2. " R2T2 ,Read receive data buffer 2 or write transmit data buffer 2" "Low,High" bitfld.long 0x00 1. " R1T1 ,Read receive data buffer 1 or write transmit data buffer 1" "Low,High" newline bitfld.long 0x00 0. " R0T0 ,Read receive data buffer 0 or write transmit data buffer 0" "Low,High" line.long 0x04 "MATCH,Match Address Register" hexmask.long.word 0x04 16.--25. 0x01 " MA2 ,Match address 2" hexmask.long.word 0x04 0.--9. 0x01 " MA1 ,Match address 1" if (((per.l(ad:0x33220000+0x18))&0xC0000)==0x00) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" bitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" newline bitfld.long 0x00 8.--12. " RTSWATER ,Receive RTS configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" elif (((per.l(ad:0x33220000+0x18))&0xC0000)==0x40000) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" newline rbitfld.long 0x00 8.--12. " RTSWATER ,Receive RTS configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" rbitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" elif (((per.l(ad:0x33220000+0x18))&0xC0000)==0x80000) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" newline bitfld.long 0x00 8.--12. " RTSWATER ,Receive RTS configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" rbitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline rbitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" newline rbitfld.long 0x00 8.--12. " RTSWATER ,Receive RTS configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" rbitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" rbitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline rbitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" endif if ((((per.l(ad:0x33220000+0x18))&0xC0000)==0x00)&&(((per.l(ad:0x33220000+0x28))&0xC00000)==0xC00000)) group.long 0x28++0x03 line.long 0x00 "FIFO,FIFO Register" rbitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO empty" "Not empty,Empty" rbitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO empty" "Not empty,Empty" eventfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" eventfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" newline rbitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" else rgroup.long 0x28++0x03 line.long 0x00 "FIFO,FIFO Register" bitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" bitfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" endif if (((per.l(ad:0x33220000+0x18))&0x80000)==0x80000) rgroup.long 0x2C++0x03 line.long 0x00 "WATER,Watermark Register" bitfld.long 0x00 24.--29. " RXCOUNT ,Receive counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--20. " RXWATER ,Receive watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " TXCOUNT ,Transmit counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--4. " TXWATER ,Transmit watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x2C++0x03 line.long 0x00 "WATER,Watermark Register" rbitfld.long 0x00 24.--29. " RXCOUNT ,Receive counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--20. " RXWATER ,Receive watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " TXCOUNT ,Transmit counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--4. " TXWATER ,Transmit watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif width 0x0B tree.end tree "RGPIO (Rapid General-Purpose Input and Output)" base ad:0x330F0000 width 6. group.long 0x00++0x03 line.long 0x00 "PDOR,Port Data Output Register" bitfld.long 0x00 31. " PDO[31] ,Port data output pin 31" "Low,High" bitfld.long 0x00 30. " [30] ,Port data output pin 30" "Low,High" bitfld.long 0x00 29. " [29] ,Port data output pin 29" "Low,High" bitfld.long 0x00 28. " [28] ,Port data output pin 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,Port data output pin 27" "Low,High" bitfld.long 0x00 26. " [26] ,Port data output pin 26" "Low,High" bitfld.long 0x00 25. " [25] ,Port data output pin 25" "Low,High" bitfld.long 0x00 24. " [24] ,Port data output pin 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,Port data output pin 23" "Low,High" bitfld.long 0x00 22. " [22] ,Port data output pin 22" "Low,High" bitfld.long 0x00 21. " [21] ,Port data output pin 21" "Low,High" bitfld.long 0x00 20. " [20] ,Port data output pin 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,Port data output pin 19" "Low,High" bitfld.long 0x00 18. " [18] ,Port data output pin 18" "Low,High" bitfld.long 0x00 17. " [17] ,Port data output pin 17" "Low,High" bitfld.long 0x00 16. " [16] ,Port data output pin 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,Port data output pin 15" "Low,High" bitfld.long 0x00 14. " [14] ,Port data output pin 14" "Low,High" bitfld.long 0x00 13. " [13] ,Port data output pin 13" "Low,High" bitfld.long 0x00 12. " [12] ,Port data output pin 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,Port data output pin 11" "Low,High" bitfld.long 0x00 10. " [10] ,Port data output pin 10" "Low,High" bitfld.long 0x00 9. " [9] ,Port data output pin 9" "Low,High" bitfld.long 0x00 8. " [8] ,Port data output pin 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,Port data output pin 7" "Low,High" bitfld.long 0x00 6. " [6] ,Port data output pin 6" "Low,High" bitfld.long 0x00 5. " [5] ,Port data output pin 5" "Low,High" bitfld.long 0x00 4. " [4] ,Port data output pin 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,Port data output pin 3" "Low,High" bitfld.long 0x00 2. " [2] ,Port data output pin 2" "Low,High" bitfld.long 0x00 1. " [1] ,Port data output pin 1" "Low,High" bitfld.long 0x00 0. " [0] ,Port data output pin 0" "Low,High" wgroup.long 0x04++0x0B line.long 0x00 "PSOR,Port Set Output Register" bitfld.long 0x00 31. " PTSO[31] ,Port set output pin 31" "No effect,Set" bitfld.long 0x00 30. " [30] ,Port set output pin 30" "No effect,Set" bitfld.long 0x00 29. " [29] ,Port set output pin 29" "No effect,Set" bitfld.long 0x00 28. " [28] ,Port set output pin 28" "No effect,Set" newline bitfld.long 0x00 27. " [27] ,Port set output pin 27" "No effect,Set" bitfld.long 0x00 26. " [26] ,Port set output pin 26" "No effect,Set" bitfld.long 0x00 25. " [25] ,Port set output pin 25" "No effect,Set" bitfld.long 0x00 24. " [24] ,Port set output pin 24" "No effect,Set" newline bitfld.long 0x00 23. " [23] ,Port set output pin 23" "No effect,Set" bitfld.long 0x00 22. " [22] ,Port set output pin 22" "No effect,Set" bitfld.long 0x00 21. " [21] ,Port set output pin 21" "No effect,Set" bitfld.long 0x00 20. " [20] ,Port set output pin 20" "No effect,Set" newline bitfld.long 0x00 19. " [19] ,Port set output pin 19" "No effect,Set" bitfld.long 0x00 18. " [18] ,Port set output pin 18" "No effect,Set" bitfld.long 0x00 17. " [17] ,Port set output pin 17" "No effect,Set" bitfld.long 0x00 16. " [16] ,Port set output pin 16" "No effect,Set" newline bitfld.long 0x00 15. " [15] ,Port set output pin 15" "No effect,Set" bitfld.long 0x00 14. " [14] ,Port set output pin 14" "No effect,Set" bitfld.long 0x00 13. " [13] ,Port set output pin 13" "No effect,Set" bitfld.long 0x00 12. " [12] ,Port set output pin 12" "No effect,Set" newline bitfld.long 0x00 11. " [11] ,Port set output pin 11" "No effect,Set" bitfld.long 0x00 10. " [10] ,Port set output pin 10" "No effect,Set" bitfld.long 0x00 9. " [9] ,Port set output pin 9" "No effect,Set" bitfld.long 0x00 8. " [8] ,Port set output pin 8" "No effect,Set" newline bitfld.long 0x00 7. " [7] ,Port set output pin 7" "No effect,Set" bitfld.long 0x00 6. " [6] ,Port set output pin 6" "No effect,Set" bitfld.long 0x00 5. " [5] ,Port set output pin 5" "No effect,Set" bitfld.long 0x00 4. " [4] ,Port set output pin 4" "No effect,Set" newline bitfld.long 0x00 3. " [3] ,Port set output pin 3" "No effect,Set" bitfld.long 0x00 2. " [2] ,Port set output pin 2" "No effect,Set" bitfld.long 0x00 1. " [1] ,Port set output pin 1" "No effect,Set" bitfld.long 0x00 0. " [0] ,Port set output pin 0" "No effect,Set" line.long 0x04 "PCOR,Port Clear Output Register" bitfld.long 0x04 31. " PTCO[31] ,Port clear output pin 31" "No effect,Clear" bitfld.long 0x04 30. " [30] ,Port clear output pin 30" "No effect,Clear" bitfld.long 0x04 29. " [29] ,Port clear output pin 29" "No effect,Clear" bitfld.long 0x04 28. " [28] ,Port clear output pin 28" "No effect,Clear" newline bitfld.long 0x04 27. " [27] ,Port clear output pin 27" "No effect,Clear" bitfld.long 0x04 26. " [26] ,Port clear output pin 26" "No effect,Clear" bitfld.long 0x04 25. " [25] ,Port clear output pin 25" "No effect,Clear" bitfld.long 0x04 24. " [24] ,Port clear output pin 24" "No effect,Clear" newline bitfld.long 0x04 23. " [23] ,Port clear output pin 23" "No effect,Clear" bitfld.long 0x04 22. " [22] ,Port clear output pin 22" "No effect,Clear" bitfld.long 0x04 21. " [21] ,Port clear output pin 21" "No effect,Clear" bitfld.long 0x04 20. " [20] ,Port clear output pin 20" "No effect,Clear" newline bitfld.long 0x04 19. " [19] ,Port clear output pin 19" "No effect,Clear" bitfld.long 0x04 18. " [18] ,Port clear output pin 18" "No effect,Clear" bitfld.long 0x04 17. " [17] ,Port clear output pin 17" "No effect,Clear" bitfld.long 0x04 16. " [16] ,Port clear output pin 16" "No effect,Clear" newline bitfld.long 0x04 15. " [15] ,Port clear output pin 15" "No effect,Clear" bitfld.long 0x04 14. " [14] ,Port clear output pin 14" "No effect,Clear" bitfld.long 0x04 13. " [13] ,Port clear output pin 13" "No effect,Clear" bitfld.long 0x04 12. " [12] ,Port clear output pin 12" "No effect,Clear" newline bitfld.long 0x04 11. " [11] ,Port clear output pin 11" "No effect,Clear" bitfld.long 0x04 10. " [10] ,Port clear output pin 10" "No effect,Clear" bitfld.long 0x04 9. " [9] ,Port clear output pin 9" "No effect,Clear" bitfld.long 0x04 8. " [8] ,Port clear output pin 8" "No effect,Clear" newline bitfld.long 0x04 7. " [7] ,Port clear output pin 7" "No effect,Clear" bitfld.long 0x04 6. " [6] ,Port clear output pin 6" "No effect,Clear" bitfld.long 0x04 5. " [5] ,Port clear output pin 5" "No effect,Clear" bitfld.long 0x04 4. " [4] ,Port clear output pin 4" "No effect,Clear" newline bitfld.long 0x04 3. " [3] ,Port clear output pin 3" "No effect,Clear" bitfld.long 0x04 2. " [2] ,Port clear output pin 2" "No effect,Clear" bitfld.long 0x04 1. " [1] ,Port clear output pin 1" "No effect,Clear" bitfld.long 0x04 0. " [0] ,Port clear output pin 0" "No effect,Clear" line.long 0x08 "PTOR,Port Toggle Output Register" bitfld.long 0x08 31. " PTTO[31] ,Port toggle output pin 31" "No effect,Toggled" bitfld.long 0x08 30. " [30] ,Port toggle output pin 30" "No effect,Toggled" bitfld.long 0x08 29. " [29] ,Port toggle output pin 29" "No effect,Toggled" bitfld.long 0x08 28. " [28] ,Port toggle output pin 28" "No effect,Toggled" newline bitfld.long 0x08 27. " [27] ,Port toggle output pin 27" "No effect,Toggled" bitfld.long 0x08 26. " [26] ,Port toggle output pin 26" "No effect,Toggled" bitfld.long 0x08 25. " [25] ,Port toggle output pin 25" "No effect,Toggled" bitfld.long 0x08 24. " [24] ,Port toggle output pin 24" "No effect,Toggled" newline bitfld.long 0x08 23. " [23] ,Port toggle output pin 23" "No effect,Toggled" bitfld.long 0x08 22. " [22] ,Port toggle output pin 22" "No effect,Toggled" bitfld.long 0x08 21. " [21] ,Port toggle output pin 21" "No effect,Toggled" bitfld.long 0x08 20. " [20] ,Port toggle output pin 20" "No effect,Toggled" newline bitfld.long 0x08 19. " [19] ,Port toggle output pin 19" "No effect,Toggled" bitfld.long 0x08 18. " [18] ,Port toggle output pin 18" "No effect,Toggled" bitfld.long 0x08 17. " [17] ,Port toggle output pin 17" "No effect,Toggled" bitfld.long 0x08 16. " [16] ,Port toggle output pin 16" "No effect,Toggled" newline bitfld.long 0x08 15. " [15] ,Port toggle output pin 15" "No effect,Toggled" bitfld.long 0x08 14. " [14] ,Port toggle output pin 14" "No effect,Toggled" bitfld.long 0x08 13. " [13] ,Port toggle output pin 13" "No effect,Toggled" bitfld.long 0x08 12. " [12] ,Port toggle output pin 12" "No effect,Toggled" newline bitfld.long 0x08 11. " [11] ,Port toggle output pin 11" "No effect,Toggled" bitfld.long 0x08 10. " [10] ,Port toggle output pin 10" "No effect,Toggled" bitfld.long 0x08 9. " [9] ,Port toggle output pin 9" "No effect,Toggled" bitfld.long 0x08 8. " [8] ,Port toggle output pin 8" "No effect,Toggled" newline bitfld.long 0x08 7. " [7] ,Port toggle output pin 7" "No effect,Toggled" bitfld.long 0x08 6. " [6] ,Port toggle output pin 6" "No effect,Toggled" bitfld.long 0x08 5. " [5] ,Port toggle output pin 5" "No effect,Toggled" bitfld.long 0x08 4. " [4] ,Port toggle output pin 4" "No effect,Toggled" newline bitfld.long 0x08 3. " [3] ,Port toggle output pin 3" "No effect,Toggled" bitfld.long 0x08 2. " [2] ,Port toggle output pin 2" "No effect,Toggled" bitfld.long 0x08 1. " [1] ,Port toggle output pin 1" "No effect,Toggled" bitfld.long 0x08 0. " [0] ,Port toggle output pin 0" "No effect,Toggled" rgroup.long 0x10++0x03 line.long 0x00 "PDIR,Port Data Input Register" bitfld.long 0x00 31. " PDI[31] ,Port data input pin 31" "Low/Not configured,High" bitfld.long 0x00 30. " [30] ,Port data input pin 30" "Low/Not configured,High" bitfld.long 0x00 29. " [29] ,Port data input pin 29" "Low/Not configured,High" bitfld.long 0x00 28. " [28] ,Port data input pin 28" "Low/Not configured,High" newline bitfld.long 0x00 27. " [27] ,Port data input pin 27" "Low/Not configured,High" bitfld.long 0x00 26. " [26] ,Port data input pin 26" "Low/Not configured,High" bitfld.long 0x00 25. " [25] ,Port data input pin 25" "Low/Not configured,High" bitfld.long 0x00 24. " [24] ,Port data input pin 24" "Low/Not configured,High" newline bitfld.long 0x00 23. " [23] ,Port data input pin 23" "Low/Not configured,High" bitfld.long 0x00 22. " [22] ,Port data input pin 22" "Low/Not configured,High" bitfld.long 0x00 21. " [21] ,Port data input pin 21" "Low/Not configured,High" bitfld.long 0x00 20. " [20] ,Port data input pin 20" "Low/Not configured,High" newline bitfld.long 0x00 19. " [19] ,Port data input pin 19" "Low/Not configured,High" bitfld.long 0x00 18. " [18] ,Port data input pin 18" "Low/Not configured,High" bitfld.long 0x00 17. " [17] ,Port data input pin 17" "Low/Not configured,High" bitfld.long 0x00 16. " [16] ,Port data input pin 16" "Low/Not configured,High" newline bitfld.long 0x00 15. " [15] ,Port data input pin 15" "Low/Not configured,High" bitfld.long 0x00 14. " [14] ,Port data input pin 14" "Low/Not configured,High" bitfld.long 0x00 13. " [13] ,Port data input pin 13" "Low/Not configured,High" bitfld.long 0x00 12. " [12] ,Port data input pin 12" "Low/Not configured,High" newline bitfld.long 0x00 11. " [11] ,Port data input pin 11" "Low/Not configured,High" bitfld.long 0x00 10. " [10] ,Port data input pin 10" "Low/Not configured,High" bitfld.long 0x00 9. " [9] ,Port data input pin 9" "Low/Not configured,High" bitfld.long 0x00 8. " [8] ,Port data input pin 8" "Low/Not configured,High" newline bitfld.long 0x00 7. " [7] ,Port data input pin 7" "Low/Not configured,High" bitfld.long 0x00 6. " [6] ,Port data input pin 6" "Low/Not configured,High" bitfld.long 0x00 5. " [5] ,Port data input pin 5" "Low/Not configured,High" bitfld.long 0x00 4. " [4] ,Port data input pin 4" "Low/Not configured,High" newline bitfld.long 0x00 3. " [3] ,Port data input pin 3" "Low/Not configured,High" bitfld.long 0x00 2. " [2] ,Port data input pin 2" "Low/Not configured,High" bitfld.long 0x00 1. " [1] ,Port data input pin 1" "Low/Not configured,High" bitfld.long 0x00 0. " [0] ,Port data input pin 0" "Low/Not configured,High" group.long 0x14++0x03 line.long 0x00 "PDDR,Port Data Direction Register" bitfld.long 0x00 31. " PDD[31] ,Port data direction" "Input,Output" bitfld.long 0x00 30. " [30] ,Port data direction pin 30" "Input,Output" bitfld.long 0x00 29. " [29] ,Port data direction pin 29" "Input,Output" bitfld.long 0x00 28. " [28] ,Port data direction pin 28" "Input,Output" newline bitfld.long 0x00 27. " [27] ,Port data direction pin 27" "Input,Output" bitfld.long 0x00 26. " [26] ,Port data direction pin 26" "Input,Output" bitfld.long 0x00 25. " [25] ,Port data direction pin 25" "Input,Output" bitfld.long 0x00 24. " [24] ,Port data direction pin 24" "Input,Output" newline bitfld.long 0x00 23. " [23] ,Port data direction pin 23" "Input,Output" bitfld.long 0x00 22. " [22] ,Port data direction pin 22" "Input,Output" bitfld.long 0x00 21. " [21] ,Port data direction pin 21" "Input,Output" bitfld.long 0x00 20. " [20] ,Port data direction pin 20" "Input,Output" newline bitfld.long 0x00 19. " [19] ,Port data direction pin 19" "Input,Output" bitfld.long 0x00 18. " [18] ,Port data direction pin 18" "Input,Output" bitfld.long 0x00 17. " [17] ,Port data direction pin 17" "Input,Output" bitfld.long 0x00 16. " [16] ,Port data direction pin 16" "Input,Output" newline bitfld.long 0x00 15. " [15] ,Port data direction pin 15" "Input,Output" bitfld.long 0x00 14. " [14] ,Port data direction pin 14" "Input,Output" bitfld.long 0x00 13. " [13] ,Port data direction pin 13" "Input,Output" bitfld.long 0x00 12. " [12] ,Port data direction pin 12" "Input,Output" newline bitfld.long 0x00 11. " [11] ,Port data direction pin 11" "Input,Output" bitfld.long 0x00 10. " [10] ,Port data direction pin 10" "Input,Output" bitfld.long 0x00 9. " [9] ,Port data direction pin 9" "Input,Output" bitfld.long 0x00 8. " [8] ,Port data direction pin 8" "Input,Output" newline bitfld.long 0x00 7. " [7] ,Port data direction pin 7" "Input,Output" bitfld.long 0x00 6. " [6] ,Port data direction pin 6" "Input,Output" bitfld.long 0x00 5. " [5] ,Port data direction pin 5" "Input,Output" bitfld.long 0x00 4. " [4] ,Port data direction pin 4" "Input,Output" newline bitfld.long 0x00 3. " [3] ,Port data direction pin 3" "Input,Output" bitfld.long 0x00 2. " [2] ,Port data direction pin 2" "Input,Output" bitfld.long 0x00 1. " [1] ,Port data direction pin 1" "Input,Output" bitfld.long 0x00 0. " [0] ,Port data direction pin 0" "Input,Output" width 0x0B tree.end tree "SEMA42 (Semaphores2)" base ad:0x331B0000 width 9. group.byte 0x0++0x03 line.byte 0x00 "GATE3,Gate Register 3" bitfld.byte 0x00 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x01 "GATE2,Gate Register 2" bitfld.byte 0x01 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x02 "GATE1,Gate Register 1" bitfld.byte 0x02 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x03 "GATE0,Gate Register 0" bitfld.byte 0x03 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" group.byte 0x4++0x03 line.byte 0x00 "GATE7,Gate Register 7" bitfld.byte 0x00 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x01 "GATE6,Gate Register 6" bitfld.byte 0x01 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x02 "GATE5,Gate Register 5" bitfld.byte 0x02 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x03 "GATE4,Gate Register 4" bitfld.byte 0x03 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" group.byte 0x8++0x03 line.byte 0x00 "GATE11,Gate Register 11" bitfld.byte 0x00 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x01 "GATE10,Gate Register 10" bitfld.byte 0x01 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x02 "GATE9,Gate Register 9" bitfld.byte 0x02 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x03 "GATE8,Gate Register 8" bitfld.byte 0x03 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" group.byte 0xC++0x03 line.byte 0x00 "GATE15,Gate Register 15" bitfld.byte 0x00 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x01 "GATE14,Gate Register 14" bitfld.byte 0x01 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x02 "GATE13,Gate Register 13" bitfld.byte 0x02 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" line.byte 0x03 "GATE12,Gate Register 12" bitfld.byte 0x03 0.--3. " GTFSM ,Gate finite state machine" "Unlocked,Locked by processor 0,Locked by processor 1,Locked by processor 2,Locked by processor 3,Locked by processor 4,Locked by processor 5,Locked by processor 6,Locked by processor 7,Locked by processor 8,Locked by processor 9,Locked by processor 10,Locked by processor 11,Locked by processor 12,Locked by processor 13,Locked by processor 14" rgroup.word 0x42++0x01 line.word 0x00 "RSTGT_R,Reset Gate Read Register" bitfld.word 0x00 14.--15. " ROZ ,ROZ" "0,1,2,3" bitfld.word 0x00 12.--13. " RSTGSM ,Reset gate finite state machine" "Idle,Waiting,Completed,?..." bitfld.word 0x00 8.--11. " RSTGMS ,Reset gate bus master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word.byte 0x00 0.--7. 1. " RSTGTN ,Reset gate number" wgroup.word 0x42++0x01 line.word 0x00 "RSTGT_W,Reset Gate Write Register" hexmask.word.byte 0x00 8.--15. 1. " RSTGDP ,Reset gate data pattern" hexmask.word.byte 0x00 0.--7. 1. " RSTGTN ,Reset gate number" width 0x0B tree.end tree.open "MU (Messaging Unit)" tree "MU0-A0" base ad:0x33440000 width 9. if (((per.l(ad:0x33440000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x33440000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x33440000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x33440000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x33440000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x33440000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x33440000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x33440000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree "MU0-A1" base ad:0x33450000 width 9. if (((per.l(ad:0x33450000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x33450000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x33450000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x33450000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x33450000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x33450000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x33450000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x33450000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree "MU0-A2" base ad:0x33460000 width 9. if (((per.l(ad:0x33460000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x33460000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x33460000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x33460000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x33460000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x33460000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x33460000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x33460000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree "MU0-A3" base ad:0x33470000 width 9. if (((per.l(ad:0x33470000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x33470000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x33470000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x33470000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x33470000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x33470000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x33470000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x33470000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree "MU0-B" base ad:0x33430000 width 9. if (((per.l(ad:0x33430000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "BTR0,Processor B Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "BTR0,Processor B Transmit Register 0" endif if (((per.l(ad:0x33430000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "BTR1,Processor B Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "BTR1,Processor B Transmit Register 1" endif if (((per.l(ad:0x33430000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "BTR2,Processor B Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "BTR2,Processor B Transmit Register 2" endif if (((per.l(ad:0x33430000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "BTR3,Processor B Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "BTR3,Processor B Transmit Register 3" endif newline if (((per.l(ad:0x33430000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "BRR0,Processor B Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "BRR0,Processor B Receive Register 0" in newline endif if (((per.l(ad:0x33430000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "BRR1,Processor B Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "BRR1,Processor B Receive Register 1" in newline endif if (((per.l(ad:0x33430000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "BRR2,Processor B Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "BRR2,Processor B Receive Register 2" in newline endif if (((per.l(ad:0x33430000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "BRR3,Processor B Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "BRR3,Processor B Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "BSR,Processor B Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor B general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor B general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor B general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor B general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor B receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor B receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor B receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor B receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor B transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor B transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor B transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor B transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 8. " FUP ,Processor B flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " ARS ,Processor A reset state" "No reset,Reset" bitfld.long 0x00 4. " EP ,Processor B-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor B-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor B-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor B-side flag 0" "0,1" line.long 0x04 "BCR,Processor B Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor B general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor B general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor B general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor B general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor B receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor B receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor B receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor B receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor B transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor B transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor B transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor B transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor B general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor B general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor B general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor B general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 4. " HRM ,Processor B hardware reset mask" "Not masked,Masked" newline bitfld.long 0x04 2. " BAF[2] ,Processor B to processor A flag 2" "Clear,Set" bitfld.long 0x04 1. " [1] ,Processor B to processor A flag 1" "Clear,Set" bitfld.long 0x04 0. " [0] ,Processor B to processor A flag 0" "Clear,Set" width 0x0B tree.end tree "MU1-A" base ad:0x33480000 width 9. if (((per.l(ad:0x33480000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x33480000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x33480000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x33480000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x33480000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x33480000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x33480000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x33480000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree.end tree "WDOG (Watchdog Timer)" base ad:0x33420000 width 7. group.long 0x00++0x0F line.long 0x00 "CS,Watchdog Control and Status Register" bitfld.long 0x00 15. " WIN ,Window mode enable" "Disabled,Enabled" eventfld.long 0x00 14. " FLG ,Watchdog interrupt flag" "Not occurred,Occurred" bitfld.long 0x00 13. " CMD32EN ,WDOG support for 32-bit enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " PRES ,Watchdog 256 prescaler enable" "Disabled,Enabled" rbitfld.long 0x00 11. " ULK ,Unlock status" "Locked,Unlocked" rbitfld.long 0x00 10. " RCS ,Reconfiguration success" "In progress,Succeeded" newline bitfld.long 0x00 8.--9. " CLK ,Watchdog counter clock source" "Bus clock,LPO clock,INTCLK,ERCLK" bitfld.long 0x00 7. " EN ,Watchdog counter enable" "Disabled,Enabled" bitfld.long 0x00 6. " INT ,Watchdog interrupt" "Disabled,Enabled" newline bitfld.long 0x00 5. " UPDATE ,Watchdog software reconfiguration without a reset allowance" "Not allowed,Allowed" bitfld.long 0x00 3.--4. " TST ,Fast test mode enable" "Disabled,User mode,Test mode/low byte,Test mode/high byte" bitfld.long 0x00 2. " DBG ,Debug mode enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " WAIT ,Wait mode enable" "Disabled,Enabled" bitfld.long 0x00 0. " STOP ,Stop mode enable" "Disabled,Enabled" line.long 0x04 "CNT,Watchdog Counter Register" hexmask.long.byte 0x04 8.--15. 1. " CNTHIGH ,High byte of the watchdog counter" hexmask.long.byte 0x04 0.--7. 1. " CNTLOW ,Low byte of the watchdog counter" line.long 0x08 "TOVAL,Watchdog Timeout Value Register" hexmask.long.byte 0x08 8.--15. 1. " TOVALHIGH ,High byte of the timeout value" hexmask.long.byte 0x08 0.--7. 1. " TOVALLOW ,Low byte of the timeout value" line.long 0x0C "WIN,Watchdog Window Register" hexmask.long.byte 0x0C 8.--15. 1. " WINHIGH ,High byte of watchdog window" hexmask.long.byte 0x0C 0.--7. 1. " WINLOW ,Low byte of watchdog window" width 0x0B tree.end tree "SCU_LPC (SCU Low Power Controller)" base ad:0x40070000 width 5. group.long 0x0++0x03 line.long 0x00 "PC0,Power Control Register 0" hexmask.long.tbyte 0x00 0.--23. 1. " PC ,Power control bus" group.long 0x4++0x03 line.long 0x00 "PC1,Power Control Register 1" hexmask.long.tbyte 0x00 0.--23. 1. " PC ,Power control bus" group.long 0x8++0x03 line.long 0x00 "PC2,Power Control Register 2" hexmask.long.tbyte 0x00 0.--23. 1. " PC ,Power control bus" group.long 0xC++0x03 line.long 0x00 "PC3,Power Control Register 3" hexmask.long.tbyte 0x00 0.--23. 1. " PC ,Power control bus" group.long 0x10++0x03 line.long 0x00 "PC4,Power Control Register 4" hexmask.long.tbyte 0x00 0.--23. 1. " PC ,Power control bus" group.long 0x14++0x03 line.long 0x00 "PC5,Power Control Register 5" hexmask.long.tbyte 0x00 0.--23. 1. " PC ,Power control bus" group.long 0x18++0x03 line.long 0x00 "PC6,Power Control Register 6" hexmask.long.tbyte 0x00 0.--23. 1. " PC ,Power control bus" group.long 0x1C++0x03 line.long 0x00 "CR,Configuration Register" bitfld.long 0x00 7. " CLKG ,LPC clock gate request" "Not requested,Requested" rbitfld.long 0x00 6. " CLKS ,LPC clock status" "Not gated,Gated" bitfld.long 0x00 4.--5. " CLKSEL ,LPC clock select" "25 MHz,1 MHz,32 kHz,?..." bitfld.long 0x00 2. " PCSEL ,LPC/DSC power control select" "DSC,LPC" bitfld.long 0x00 1. " PMICSTDBY ,PMIC standby request asserted during low power mode" "Not asserted,Asserted" bitfld.long 0x00 0. " ROSCDIS ,ROSC disable" "No,Yes" group.long 0x20++0x03 line.long 0x00 "ED0,Entry Delay Stage N 0" bitfld.long 0x00 0.--4. " ED ,Entry delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long (0x20+0x20)++0x03 line.long 0x00 "XD0,Exit Delay Stage N 0" bitfld.long 0x00 0.--4. " XD ,Exit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x24++0x03 line.long 0x00 "ED1,Entry Delay Stage N 1" bitfld.long 0x00 0.--4. " ED ,Entry delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long (0x24+0x20)++0x03 line.long 0x00 "XD1,Exit Delay Stage N 1" bitfld.long 0x00 0.--4. " XD ,Exit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x28++0x03 line.long 0x00 "ED2,Entry Delay Stage N 2" bitfld.long 0x00 0.--4. " ED ,Entry delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long (0x28+0x20)++0x03 line.long 0x00 "XD2,Exit Delay Stage N 2" bitfld.long 0x00 0.--4. " XD ,Exit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x2C++0x03 line.long 0x00 "ED3,Entry Delay Stage N 3" bitfld.long 0x00 0.--4. " ED ,Entry delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long (0x2C+0x20)++0x03 line.long 0x00 "XD3,Exit Delay Stage N 3" bitfld.long 0x00 0.--4. " XD ,Exit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x30++0x03 line.long 0x00 "ED4,Entry Delay Stage N 4" bitfld.long 0x00 0.--4. " ED ,Entry delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long (0x30+0x20)++0x03 line.long 0x00 "XD4,Exit Delay Stage N 4" bitfld.long 0x00 0.--4. " XD ,Exit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x34++0x03 line.long 0x00 "ED5,Entry Delay Stage N 5" bitfld.long 0x00 0.--4. " ED ,Entry delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long (0x34+0x20)++0x03 line.long 0x00 "XD5,Exit Delay Stage N 5" bitfld.long 0x00 0.--4. " XD ,Exit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x38++0x03 line.long 0x00 "ED6,Entry Delay Stage N 6" bitfld.long 0x00 0.--4. " ED ,Entry delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long (0x38+0x20)++0x03 line.long 0x00 "XD6,Exit Delay Stage N 6" hexmask.long.word 0x00 0.--15. 1. " XD ,Exit delay" width 0x0B tree.end ; tree "OCOTP_CTRL (On-Chip OTP Controller)" ; base ad:0x00 ; %include imx8x/ocotp.ph ad:0x00 ; tree.end tree "ASMC (Auxiliary System Mode Control)" base ad:0x33410000 width 10. rgroup.long 0x00++0x03 line.long 0x00 "SRS,System Reset Status Register" bitfld.long 0x00 12. " SACKERR ,Reset caused by peripheral failure to acknowledge attempt to enter stop mode" "Not occurred,Occurred" bitfld.long 0x00 10. " SW ,Reset caused by software setting of SYSRESETREQ bit" "Not occurred,Occurred" bitfld.long 0x00 9. " LOCKUP ,Reset caused by core LOCKUP event" "Not occurred,Occurred" bitfld.long 0x00 7. " POR ,Reset caused by power-on detection logic" "Not occurred,Occurred" newline bitfld.long 0x00 6. " RES ,Chip Reset caused by a source other than power-on detection logic" "Not occurred,Occurred" bitfld.long 0x00 5. " WDOG1 ,Reset caused by watchdog timer 1 timeout" "Not occurred,Occurred" bitfld.long 0x00 0. " WAKEUP ,Reset caused by LLWU module wakeup source" "Not occurred,Occurred" group.long 0x08++0x0B line.long 0x00 "PMPROT,Power Mode Protection Register" bitfld.long 0x00 7. " AHSRUN ,Allow high speed run mode" "Not allowed,Allowed" bitfld.long 0x00 5. " AVLP ,Allow very low power modes" "Not allowed,Allowed" bitfld.long 0x00 3. " ALLS ,Allow low-leakage stop mode" "Not allowed,Allowed" bitfld.long 0x00 1. " AVLLS ,Allow very-low-leakage stop mode" "Not allowed,Allowed" line.long 0x04 "PMCTRL,Power Mode Control Register" bitfld.long 0x04 5.--6. " RUNM ,Run mode control" "Normal,,Very-low-power,High speed" bitfld.long 0x04 0.--2. " STOPM ,Stop mode control" "Normal,,Very-low-power,Low-leakage,Very-low-leakage,?..." line.long 0x08 "STOPCTRL,Stop Control Register" bitfld.long 0x08 6.--7. " PSTOPO ,Partial stop option" "Normal,PSTOP1,PSTOP2,?..." rgroup.long 0x14++0x03 line.long 0x00 "PMSTAT,Power Mode Status Register" hexmask.long.byte 0x00 0.--7. 1. " PMSTAT ,Power mode status" rgroup.long 0xF0++0x07 "Time Stamp Timer Module (TSTMR)" line.long 0x00 "LOW,Time Stamp Timer Register Low" line.long 0x04 "HIGH,Time Stamp Timer Register High" width 0x0B tree.end tree "INTMUX (Interrupt Multiplexer)" base ad:0x33400000 width 14. group.long 0x0++0x03 "Channel 0" line.long 0x00 "CH0_CSR,Channel 0 Control Status Register" rbitfld.long 0x00 31. " IRQP ,Channel interrupt request pending" "Not pending,Pending" rbitfld.long 0x00 8.--11. " CHIN ,Channel instance number" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 4.--5. " IRQN ,Channel input number" "32 interrupt inputs,?..." newline bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND" bitfld.long 0x00 0. " RST ,Software reset" "No reset,Reset" rgroup.long (0x0+0x04)++0x03 line.long 0x00 "CH0_VEC,Channel 0 Vector Number Register" hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector number" newline group.long (0x0+0x10)++0x03 line.long 0x00 "CH0_IER_31_0,Channel 0 Interrupt Enable Register" bitfld.long 0x00 31. " INTE[31] ,Interrupt MU0_A0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Interrupt LPUART enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Interrupt LPIT enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Interrupt TPM enable" "Disabled,Enabled" rgroup.long (0x0+0x20)++0x03 line.long 0x00 "CH0_IPR_31_0,Channel 0 Interrupt Pending Register" bitfld.long 0x00 31. " INTP[31] ,Interrupt MU0_A0 pending" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 pending" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 pending" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 pending" "Not pending,Pending" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C pending" "Not pending,Pending" bitfld.long 0x00 7. " [7] ,Interrupt LPUART pending" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Interrupt LPIT pending" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Interrupt TPM pending" "Not pending,Pending" group.long 0x40++0x03 "Channel 1" line.long 0x00 "CH1_CSR,Channel 1 Control Status Register" rbitfld.long 0x00 31. " IRQP ,Channel interrupt request pending" "Not pending,Pending" rbitfld.long 0x00 8.--11. " CHIN ,Channel instance number" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 4.--5. " IRQN ,Channel input number" "32 interrupt inputs,?..." newline bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND" bitfld.long 0x00 0. " RST ,Software reset" "No reset,Reset" rgroup.long (0x40+0x04)++0x03 line.long 0x00 "CH1_VEC,Channel 1 Vector Number Register" hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector number" newline group.long (0x40+0x10)++0x03 line.long 0x00 "CH1_IER_31_0,Channel 1 Interrupt Enable Register" bitfld.long 0x00 31. " INTE[31] ,Interrupt MU0_A0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Interrupt LPUART enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Interrupt LPIT enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Interrupt TPM enable" "Disabled,Enabled" rgroup.long (0x40+0x20)++0x03 line.long 0x00 "CH1_IPR_31_0,Channel 1 Interrupt Pending Register" bitfld.long 0x00 31. " INTP[31] ,Interrupt MU0_A0 pending" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 pending" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 pending" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 pending" "Not pending,Pending" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C pending" "Not pending,Pending" bitfld.long 0x00 7. " [7] ,Interrupt LPUART pending" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Interrupt LPIT pending" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Interrupt TPM pending" "Not pending,Pending" group.long 0x80++0x03 "Channel 2" line.long 0x00 "CH2_CSR,Channel 2 Control Status Register" rbitfld.long 0x00 31. " IRQP ,Channel interrupt request pending" "Not pending,Pending" rbitfld.long 0x00 8.--11. " CHIN ,Channel instance number" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 4.--5. " IRQN ,Channel input number" "32 interrupt inputs,?..." newline bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND" bitfld.long 0x00 0. " RST ,Software reset" "No reset,Reset" rgroup.long (0x80+0x04)++0x03 line.long 0x00 "CH2_VEC,Channel 2 Vector Number Register" hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector number" newline group.long (0x80+0x10)++0x03 line.long 0x00 "CH2_IER_31_0,Channel 2 Interrupt Enable Register" bitfld.long 0x00 31. " INTE[31] ,Interrupt MU0_A0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Interrupt LPUART enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Interrupt LPIT enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Interrupt TPM enable" "Disabled,Enabled" rgroup.long (0x80+0x20)++0x03 line.long 0x00 "CH2_IPR_31_0,Channel 2 Interrupt Pending Register" bitfld.long 0x00 31. " INTP[31] ,Interrupt MU0_A0 pending" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 pending" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 pending" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 pending" "Not pending,Pending" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C pending" "Not pending,Pending" bitfld.long 0x00 7. " [7] ,Interrupt LPUART pending" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Interrupt LPIT pending" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Interrupt TPM pending" "Not pending,Pending" group.long 0xC0++0x03 "Channel 3" line.long 0x00 "CH3_CSR,Channel 3 Control Status Register" rbitfld.long 0x00 31. " IRQP ,Channel interrupt request pending" "Not pending,Pending" rbitfld.long 0x00 8.--11. " CHIN ,Channel instance number" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 4.--5. " IRQN ,Channel input number" "32 interrupt inputs,?..." newline bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND" bitfld.long 0x00 0. " RST ,Software reset" "No reset,Reset" rgroup.long (0xC0+0x04)++0x03 line.long 0x00 "CH3_VEC,Channel 3 Vector Number Register" hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector number" newline group.long (0xC0+0x10)++0x03 line.long 0x00 "CH3_IER_31_0,Channel 3 Interrupt Enable Register" bitfld.long 0x00 31. " INTE[31] ,Interrupt MU0_A0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Interrupt LPUART enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Interrupt LPIT enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Interrupt TPM enable" "Disabled,Enabled" rgroup.long (0xC0+0x20)++0x03 line.long 0x00 "CH3_IPR_31_0,Channel 3 Interrupt Pending Register" bitfld.long 0x00 31. " INTP[31] ,Interrupt MU0_A0 pending" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 pending" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 pending" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 pending" "Not pending,Pending" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C pending" "Not pending,Pending" bitfld.long 0x00 7. " [7] ,Interrupt LPUART pending" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Interrupt LPIT pending" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Interrupt TPM pending" "Not pending,Pending" group.long 0x100++0x03 "Channel 4" line.long 0x00 "CH4_CSR,Channel 4 Control Status Register" rbitfld.long 0x00 31. " IRQP ,Channel interrupt request pending" "Not pending,Pending" rbitfld.long 0x00 8.--11. " CHIN ,Channel instance number" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 4.--5. " IRQN ,Channel input number" "32 interrupt inputs,?..." newline bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND" bitfld.long 0x00 0. " RST ,Software reset" "No reset,Reset" rgroup.long (0x100+0x04)++0x03 line.long 0x00 "CH4_VEC,Channel 4 Vector Number Register" hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector number" newline group.long (0x100+0x10)++0x03 line.long 0x00 "CH4_IER_31_0,Channel 4 Interrupt Enable Register" bitfld.long 0x00 31. " INTE[31] ,Interrupt MU0_A0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Interrupt LPUART enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Interrupt LPIT enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Interrupt TPM enable" "Disabled,Enabled" rgroup.long (0x100+0x20)++0x03 line.long 0x00 "CH4_IPR_31_0,Channel 4 Interrupt Pending Register" bitfld.long 0x00 31. " INTP[31] ,Interrupt MU0_A0 pending" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 pending" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 pending" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 pending" "Not pending,Pending" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C pending" "Not pending,Pending" bitfld.long 0x00 7. " [7] ,Interrupt LPUART pending" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Interrupt LPIT pending" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Interrupt TPM pending" "Not pending,Pending" group.long 0x140++0x03 "Channel 5" line.long 0x00 "CH5_CSR,Channel 5 Control Status Register" rbitfld.long 0x00 31. " IRQP ,Channel interrupt request pending" "Not pending,Pending" rbitfld.long 0x00 8.--11. " CHIN ,Channel instance number" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 4.--5. " IRQN ,Channel input number" "32 interrupt inputs,?..." newline bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND" bitfld.long 0x00 0. " RST ,Software reset" "No reset,Reset" rgroup.long (0x140+0x04)++0x03 line.long 0x00 "CH5_VEC,Channel 5 Vector Number Register" hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector number" newline group.long (0x140+0x10)++0x03 line.long 0x00 "CH5_IER_31_0,Channel 5 Interrupt Enable Register" bitfld.long 0x00 31. " INTE[31] ,Interrupt MU0_A0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Interrupt LPUART enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Interrupt LPIT enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Interrupt TPM enable" "Disabled,Enabled" rgroup.long (0x140+0x20)++0x03 line.long 0x00 "CH5_IPR_31_0,Channel 5 Interrupt Pending Register" bitfld.long 0x00 31. " INTP[31] ,Interrupt MU0_A0 pending" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 pending" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 pending" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 pending" "Not pending,Pending" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C pending" "Not pending,Pending" bitfld.long 0x00 7. " [7] ,Interrupt LPUART pending" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Interrupt LPIT pending" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Interrupt TPM pending" "Not pending,Pending" group.long 0x180++0x03 "Channel 6" line.long 0x00 "CH6_CSR,Channel 6 Control Status Register" rbitfld.long 0x00 31. " IRQP ,Channel interrupt request pending" "Not pending,Pending" rbitfld.long 0x00 8.--11. " CHIN ,Channel instance number" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 4.--5. " IRQN ,Channel input number" "32 interrupt inputs,?..." newline bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND" bitfld.long 0x00 0. " RST ,Software reset" "No reset,Reset" rgroup.long (0x180+0x04)++0x03 line.long 0x00 "CH6_VEC,Channel 6 Vector Number Register" hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector number" newline group.long (0x180+0x10)++0x03 line.long 0x00 "CH6_IER_31_0,Channel 6 Interrupt Enable Register" bitfld.long 0x00 31. " INTE[31] ,Interrupt MU0_A0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Interrupt LPUART enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Interrupt LPIT enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Interrupt TPM enable" "Disabled,Enabled" rgroup.long (0x180+0x20)++0x03 line.long 0x00 "CH6_IPR_31_0,Channel 6 Interrupt Pending Register" bitfld.long 0x00 31. " INTP[31] ,Interrupt MU0_A0 pending" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 pending" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 pending" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 pending" "Not pending,Pending" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C pending" "Not pending,Pending" bitfld.long 0x00 7. " [7] ,Interrupt LPUART pending" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Interrupt LPIT pending" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Interrupt TPM pending" "Not pending,Pending" group.long 0x1C0++0x03 "Channel 7" line.long 0x00 "CH7_CSR,Channel 7 Control Status Register" rbitfld.long 0x00 31. " IRQP ,Channel interrupt request pending" "Not pending,Pending" rbitfld.long 0x00 8.--11. " CHIN ,Channel instance number" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 4.--5. " IRQN ,Channel input number" "32 interrupt inputs,?..." newline bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND" bitfld.long 0x00 0. " RST ,Software reset" "No reset,Reset" rgroup.long (0x1C0+0x04)++0x03 line.long 0x00 "CH7_VEC,Channel 7 Vector Number Register" hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector number" newline group.long (0x1C0+0x10)++0x03 line.long 0x00 "CH7_IER_31_0,Channel 7 Interrupt Enable Register" bitfld.long 0x00 31. " INTE[31] ,Interrupt MU0_A0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Interrupt LPUART enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Interrupt LPIT enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Interrupt TPM enable" "Disabled,Enabled" rgroup.long (0x1C0+0x20)++0x03 line.long 0x00 "CH7_IPR_31_0,Channel 7 Interrupt Pending Register" bitfld.long 0x00 31. " INTP[31] ,Interrupt MU0_A0 pending" "Not pending,Pending" bitfld.long 0x00 30. " [30] ,Interrupt MU0_A1 pending" "Not pending,Pending" bitfld.long 0x00 29. " [29] ,Interrupt MU0_A2 pending" "Not pending,Pending" bitfld.long 0x00 28. " [28] ,Interrupt MU0_A3 pending" "Not pending,Pending" newline bitfld.long 0x00 9. " [9] ,Interrupt LPI2C pending" "Not pending,Pending" bitfld.long 0x00 7. " [7] ,Interrupt LPUART pending" "Not pending,Pending" bitfld.long 0x00 4. " [4] ,Interrupt LPIT pending" "Not pending,Pending" bitfld.long 0x00 1. " [1] ,Interrupt TPM pending" "Not pending,Pending" width 0x0B tree.end tree.end endif tree.open "Connectivity" tree "APBHDMA (AHB-to-APBH Bridge with DMA)" base ad:0x5B810000 width 22. group.long 0x00++0x03 line.long 0x00 "CTRL0_SET/CLR,AHB To APBH Bridge Control And Status Set/Clear Register 0" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " SFTRST ,APBH DMA clocking disable" "No,Yes" setclrfld.long 0x00 30. 0x04 30. 0x08 31. " CLKGATE ,Clock gate operation" "Normal,Gated off" setclrfld.long 0x00 29. 0x04 29. 0x08 29. " AHB_BURST8_EN ,AHB 8-beat burst enable" "Disabled,Enabled" newline setclrfld.long 0x00 28. 0x04 28. 0x08 28. " APB_BURST_EN ,Burst DMA request enable" "Disabled,Enabled" newline setclrfld.long 0x00 15. 0x04 15. 0x08 15. " CLKGATE_CHANNEL[15] ,Clock gate operation channel 15" "Normal,Gated off" newline setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,Clock gate operation channel 14" "Normal,Gated off" setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,Clock gate operation channel 13" "Normal,Gated off" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,Clock gate operation channel 12" "Normal,Gated off" newline setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,Clock gate operation channel 11" "Normal,Gated off" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,Clock gate operation channel 10" "Normal,Gated off" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,Clock gate operation channel 9" "Normal,Gated off" newline setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,Clock gate operation channel 8" "Normal,Gated off" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,Clock gate operation channel 7" "Normal,Gated off" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,Clock gate operation channel 6" "Normal,Gated off" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,Clock gate operation channel 5" "Normal,Gated off" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,Clock gate operation channel 4" "Normal,Gated off" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Clock gate operation channel 3" "Normal,Gated off" newline setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Clock gate operation channel 2" "Normal,Gated off" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Clock gate operation channel 1" "Normal,Gated off" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Clock gate operation channel 0" "Normal,Gated off" group.long 0x0C++0x03 line.long 0x00 "CTRL0_TOG,AHB To APBH Bridge Control And Status Toggle Register 0" bitfld.long 0x00 31. " SFTRST ,APBH DMA clocking disable" "No effect,Toggle" bitfld.long 0x00 30. " CLKGATE ,Clock gate operation" "No effect,Toggle" bitfld.long 0x00 29. " AHB_BURST8_EN ,AHB 8-beat burst enable" "No effect,Toggle" newline bitfld.long 0x00 28. " APB_BURST_EN ,Burst DMA request enable" "No effect,Toggle" newline bitfld.long 0x00 15. " CLKGATE_CHANNEL[15] ,Clock gate operation channel 15" "No effect,Toggle" newline bitfld.long 0x00 14. " [14] ,Clock gate operation channel 14" "No effect,Toggle" bitfld.long 0x00 13. " [13] ,Clock gate operation channel 13" "No effect,Toggle" bitfld.long 0x00 12. " [12] ,Clock gate operation channel 12" "No effect,Toggle" newline bitfld.long 0x00 11. " [11] ,Clock gate operation channel 11" "No effect,Toggle" bitfld.long 0x00 10. " [10] ,Clock gate operation channel 10" "No effect,Toggle" bitfld.long 0x00 9. " [9] ,Clock gate operation channel 9" "No effect,Toggle" newline bitfld.long 0x00 8. " [8] ,Clock gate operation channel 8" "No effect,Toggle" bitfld.long 0x00 7. " [7] ,Clock gate operation channel 7" "No effect,Toggle" bitfld.long 0x00 6. " [6] ,Clock gate operation channel 6" "No effect,Toggle" newline bitfld.long 0x00 5. " [5] ,Clock gate operation channel 5" "No effect,Toggle" bitfld.long 0x00 4. " [4] ,Clock gate operation channel 4" "No effect,Toggle" bitfld.long 0x00 3. " [3] ,Clock gate operation channel 3" "No effect,Toggle" newline bitfld.long 0x00 2. " [2] ,Clock gate operation channel 2" "No effect,Toggle" bitfld.long 0x00 1. " [1] ,Clock gate operation channel 1" "No effect,Toggle" bitfld.long 0x00 0. " [0] ,Clock gate operation channel 0" "No effect,Toggle" group.long 0x10++0x03 line.long 0x00 "CTRL1_SET/CLR,AHB To APBH Bridge Control And Status Set/Clear Register 1" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " CH[15]_CMDCMPLT_IRQ_EN ,Interrupt request for APBH DMA channel 15 enable" "Disabled,Enabled" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [14] ,Interrupt request for APBH DMA channel 14 enable" "Disabled,Enabled" setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [13] ,Interrupt request for APBH DMA channel 13 enable" "Disabled,Enabled" newline setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [12] ,Interrupt request for APBH DMA channel 12 enable" "Disabled,Enabled" setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [11] ,Interrupt request for APBH DMA channel 11 enable" "Disabled,Enabled" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [10] ,Interrupt request for APBH DMA channel 10 enable" "Disabled,Enabled" newline setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [9] ,Interrupt request for APBH DMA channel 9 enable" "Disabled,Enabled" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [8] ,Interrupt request for APBH DMA channel 8 enable" "Disabled,Enabled" setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [7] ,Interrupt request for APBH DMA channel 7 enable" "Disabled,Enabled" newline setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [6] ,Interrupt request for APBH DMA channel 6 enable" "Disabled,Enabled" setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [5] ,Interrupt request for APBH DMA channel 5 enable" "Disabled,Enabled" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [4] ,Interrupt request for APBH DMA channel 4 enable" "Disabled,Enabled" newline setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [3] ,Interrupt request for APBH DMA channel 3 enable" "Disabled,Enabled" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [2] ,Interrupt request for APBH DMA channel 2 enable" "Disabled,Enabled" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [1] ,Interrupt request for APBH DMA channel 1 enable" "Disabled,Enabled" newline setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [0] ,Interrupt request for APBH DMA channel 0 enable" "Disabled,Enabled" newline setclrfld.long 0x00 15. 0x04 15. 0x08 15. " CH[15]_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 15" "No interrupt,Interrupt" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,Interrupt request status bit for APBH DMA channel 14" "No interrupt,Interrupt" setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,Interrupt request status bit for APBH DMA channel 13" "No interrupt,Interrupt" newline setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,Interrupt request status bit for APBH DMA channel 12" "No interrupt,Interrupt" setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,Interrupt request status bit for APBH DMA channel 11" "No interrupt,Interrupt" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,Interrupt request status bit for APBH DMA channel 10" "No interrupt,Interrupt" newline setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,Interrupt request status bit for APBH DMA channel 9" "No interrupt,Interrupt" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,Interrupt request status bit for APBH DMA channel 8" "No interrupt,Interrupt" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,Interrupt request status bit for APBH DMA channel 7" "No interrupt,Interrupt" newline setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,Interrupt request status bit for APBH DMA channel 6" "No interrupt,Interrupt" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,Interrupt request status bit for APBH DMA channel 5" "No interrupt,Interrupt" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,Interrupt request status bit for APBH DMA channel 4" "No interrupt,Interrupt" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Interrupt request status bit for APBH DMA channel 3" "No interrupt,Interrupt" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Interrupt request status bit for APBH DMA channel 2" "No interrupt,Interrupt" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Interrupt request status bit for APBH DMA channel 1" "No interrupt,Interrupt" newline setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Interrupt request status bit for APBH DMA channel 0" "No interrupt,Interrupt" group.long 0x1C++0x03 line.long 0x00 "CTRL1_TOG,AHB To APBH Bridge Control And Status Toggle Register 1" bitfld.long 0x00 31. " CH[15]_CMDCMPLT_IRQ_EN ,Interrupt request for APBH DMA channel 15 enable" "No effect,Toggle" bitfld.long 0x00 30. " [14] ,Interrupt request for APBH DMA channel 14 enable" "No effect,Toggle" bitfld.long 0x00 29. " [13] ,Interrupt request for APBH DMA channel 13 enable" "No effect,Toggle" newline bitfld.long 0x00 28. " [12] ,Interrupt request for APBH DMA channel 12 enable" "No effect,Toggle" bitfld.long 0x00 27. " [11] ,Interrupt request for APBH DMA channel 11 enable" "No effect,Toggle" bitfld.long 0x00 26. " [10] ,Interrupt request for APBH DMA channel 10 enable" "No effect,Toggle" newline bitfld.long 0x00 25. " [9] ,Interrupt request for APBH DMA channel 9 enable" "No effect,Toggle" bitfld.long 0x00 24. " [8] ,Interrupt request for APBH DMA channel 8 enable" "No effect,Toggle" bitfld.long 0x00 23. " [7] ,Interrupt request for APBH DMA channel 7 enable" "No effect,Toggle" newline bitfld.long 0x00 22. " [6] ,Interrupt request for APBH DMA channel 6 enable" "No effect,Toggle" bitfld.long 0x00 21. " [5] ,Interrupt request for APBH DMA channel 5 enable" "No effect,Toggle" bitfld.long 0x00 20. " [4] ,Interrupt request for APBH DMA channel 4 enable" "No effect,Toggle" newline bitfld.long 0x00 19. " [3] ,Interrupt request for APBH DMA channel 3 enable" "No effect,Toggle" bitfld.long 0x00 18. " [2] ,Interrupt request for APBH DMA channel 2 enable" "No effect,Toggle" bitfld.long 0x00 17. " [1] ,Interrupt request for APBH DMA channel 1 enable" "No effect,Toggle" newline bitfld.long 0x00 16. " [0] ,Interrupt request for APBH DMA channel 0 enable" "No effect,Toggle" newline bitfld.long 0x00 15. " CH[15]_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 15" "No effect,Toggle" bitfld.long 0x00 14. " [14] ,Interrupt request status bit for APBH DMA channel 14" "No effect,Toggle" bitfld.long 0x00 13. " [13] ,Interrupt request status bit for APBH DMA channel 13" "No effect,Toggle" newline bitfld.long 0x00 12. " [12] ,Interrupt request status bit for APBH DMA channel 12" "No effect,Toggle" bitfld.long 0x00 11. " [11] ,Interrupt request status bit for APBH DMA channel 11" "No effect,Toggle" bitfld.long 0x00 10. " [10] ,Interrupt request status bit for APBH DMA channel 10" "No effect,Toggle" newline bitfld.long 0x00 9. " [9] ,Interrupt request status bit for APBH DMA channel 9" "No effect,Toggle" bitfld.long 0x00 8. " [8] ,Interrupt request status bit for APBH DMA channel 8" "No effect,Toggle" bitfld.long 0x00 7. " [7] ,Interrupt request status bit for APBH DMA channel 7" "No effect,Toggle" newline bitfld.long 0x00 6. " [6] ,Interrupt request status bit for APBH DMA channel 6" "No effect,Toggle" bitfld.long 0x00 5. " [5] ,Interrupt request status bit for APBH DMA channel 5" "No effect,Toggle" bitfld.long 0x00 4. " [4] ,Interrupt request status bit for APBH DMA channel 4" "No effect,Toggle" newline bitfld.long 0x00 3. " [3] ,Interrupt request status bit for APBH DMA channel 3" "No effect,Toggle" bitfld.long 0x00 2. " [2] ,Interrupt request status bit for APBH DMA channel 2" "No effect,Toggle" bitfld.long 0x00 1. " [1] ,Interrupt request status bit for APBH DMA channel 1" "No effect,Toggle" newline bitfld.long 0x00 0. " [0] ,Interrupt request status bit for APBH DMA channel 0" "No effect,Toggle" group.long 0x20++0x0F line.long 0x00 "CTRL2,AHB To APBH Bridge Control And Status Register 2" rbitfld.long 0x00 31. " CH[15]_ERROR_STATUS ,Error status bit for APBH DMA channel 15" "No error,Error" rbitfld.long 0x00 30. " [14] ,Error status bit for APBH DMA channel 14" "No error,Error" rbitfld.long 0x00 29. " [13] ,Error status bit for APBH DMA channel 13" "No error,Error" newline rbitfld.long 0x00 28. " [12] ,Error status bit for APBH DMA channel 12" "No error,Error" rbitfld.long 0x00 27. " [11] ,Error status bit for APBH DMA channel 11" "No error,Error" rbitfld.long 0x00 26. " [10] ,Error status bit for APBH DMA channel 10" "No error,Error" newline rbitfld.long 0x00 25. " [9] ,Error status bit for APBH DMA channel 9" "No error,Error" rbitfld.long 0x00 24. " [8] ,Error status bit for APBH DMA channel 8" "No error,Error" rbitfld.long 0x00 23. " [7] ,Error status bit for APBH DMA channel 7" "No error,Error" newline rbitfld.long 0x00 22. " [6] ,Error status bit for APBH DMA channel 6" "No error,Error" rbitfld.long 0x00 21. " [5] ,Error status bit for APBH DMA channel 5" "No error,Error" rbitfld.long 0x00 20. " [4] ,Error status bit for APBH DMA channel 4" "No error,Error" newline rbitfld.long 0x00 19. " [3] ,Error status bit for APBH DMA channel 3" "No error,Error" rbitfld.long 0x00 18. " [2] ,Error status bit for APBH DMA channel 2" "No error,Error" rbitfld.long 0x00 17. " [1] ,Error status bit for APBH DMA channel 1" "No error,Error" newline rbitfld.long 0x00 16. " [0] ,Error status bit for APBH DMA channel 0" "No error,Error" newline setclrfld.long 0x00 15. 0x04 15. 0x08 15. " CH[15]_ERROR_IRQ_SET/CLR ,Error interrupt status bit for APBH DMA channel 15" "No interrupt,Interrupt" setclrfld.long 0x00 14. 0x04 14. 0x08 15. " [14] ,Error interrupt status bit for APBH DMA channel 14" "No interrupt,Interrupt" setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,Error interrupt status bit for APBH DMA channel 13" "No interrupt,Interrupt" newline setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,Error interrupt status bit for APBH DMA channel 12" "No interrupt,Interrupt" setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,Error interrupt status bit for APBH DMA channel 11" "No interrupt,Interrupt" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,Error interrupt status bit for APBH DMA channel 10" "No interrupt,Interrupt" newline setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,Error interrupt status bit for APBH DMA channel 9" "No interrupt,Interrupt" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,Error interrupt status bit for APBH DMA channel 8" "No interrupt,Interrupt" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,Error interrupt status bit for APBH DMA channel 7" "No interrupt,Interrupt" newline setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,Error interrupt status bit for APBH DMA channel 6" "No interrupt,Interrupt" setclrfld.long 0x00 5. 0x04 5. 0x08 6. " [5] ,Error interrupt status bit for APBH DMA channel 5" "No interrupt,Interrupt" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,Error interrupt status bit for APBH DMA channel 4" "No interrupt,Interrupt" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Error interrupt status bit for APBH DMA channel 3" "No interrupt,Interrupt" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Error interrupt status bit for APBH DMA channel 2" "No interrupt,Interrupt" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Error interrupt status bit for APBH DMA channel 1" "No interrupt,Interrupt" newline setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Error interrupt status bit for APBH DMA channel 0" "No interrupt,Interrupt" line.long 0x04 "CTRL2_SET,AHB To APBH Bridge Control And Status Set Register 2" rbitfld.long 0x04 31. " CH[15]_ERROR_STATUS ,Error status bit for APBH DMA channel 15" "No effect,Set" rbitfld.long 0x04 30. " [14] ,Error status bit for APBH DMA channel 14" "No effect,Set" rbitfld.long 0x04 29. " [13] ,Error status bit for APBH DMA channel 13" "No effect,Set" newline rbitfld.long 0x04 28. " [12] ,Error status bit for APBH DMA channel 12" "No effect,Set" rbitfld.long 0x04 27. " [11] ,Error status bit for APBH DMA channel 11" "No effect,Set" rbitfld.long 0x04 26. " [10] ,Error status bit for APBH DMA channel 10" "No effect,Set" newline rbitfld.long 0x04 25. " [9] ,Error status bit for APBH DMA channel 9" "No effect,Set" rbitfld.long 0x04 24. " [8] ,Error status bit for APBH DMA channel 8" "No effect,Set" rbitfld.long 0x04 23. " [7] ,Error status bit for APBH DMA channel 7" "No effect,Set" newline rbitfld.long 0x04 22. " [6] ,Error status bit for APBH DMA channel 6" "No effect,Set" rbitfld.long 0x04 21. " [5] ,Error status bit for APBH DMA channel 5" "No effect,Set" rbitfld.long 0x04 20. " [4] ,Error status bit for APBH DMA channel 4" "No effect,Set" newline rbitfld.long 0x04 19. " [3] ,Error status bit for APBH DMA channel 3" "No effect,Set" rbitfld.long 0x04 18. " [2] ,Error status bit for APBH DMA channel 2" "No effect,Set" rbitfld.long 0x04 17. " [1] ,Error status bit for APBH DMA channel 1" "No effect,Set" newline rbitfld.long 0x04 16. " [0] ,Error status bit for APBH DMA channel 0" "No effect,Set" line.long 0x08 "CTRL2_CLR,AHB To APBH Bridge Control And Status Clear Register 2" rbitfld.long 0x08 31. " CH[15]_ERROR_STATUS ,Error status bit for APBH DMA channel 15" "No effect,Clear" rbitfld.long 0x08 30. " [14] ,Error status bit for APBH DMA channel 14" "No effect,Clear" rbitfld.long 0x08 29. " [13] ,Error status bit for APBH DMA channel 13" "No effect,Clear" newline rbitfld.long 0x08 28. " [12] ,Error status bit for APBH DMA channel 12" "No effect,Clear" rbitfld.long 0x08 27. " [11] ,Error status bit for APBH DMA channel 11" "No effect,Clear" rbitfld.long 0x08 26. " [10] ,Error status bit for APBH DMA channel 10" "No effect,Clear" newline rbitfld.long 0x08 25. " [9] ,Error status bit for APBH DMA channel 9" "No effect,Clear" rbitfld.long 0x08 24. " [8] ,Error status bit for APBH DMA channel 8" "No effect,Clear" rbitfld.long 0x08 23. " [7] ,Error status bit for APBH DMA channel 7" "No effect,Clear" newline rbitfld.long 0x08 22. " [6] ,Error status bit for APBH DMA channel 6" "No effect,Clear" rbitfld.long 0x08 21. " [5] ,Error status bit for APBH DMA channel 5" "No effect,Clear" rbitfld.long 0x08 20. " [4] ,Error status bit for APBH DMA channel 4" "No effect,Clear" newline rbitfld.long 0x08 19. " [3] ,Error status bit for APBH DMA channel 3" "No effect,Clear" rbitfld.long 0x08 18. " [2] ,Error status bit for APBH DMA channel 2" "No effect,Clear" rbitfld.long 0x08 17. " [1] ,Error status bit for APBH DMA channel 1" "No effect,Clear" newline rbitfld.long 0x08 16. " [0] ,Error status bit for APBH DMA channel 0" "No effect,Clear" line.long 0x0C "CTRL2_TOG,AHB To APBH Bridge Control And Status Toggle Register 2" rbitfld.long 0x0C 31. " CH[15]_ERROR_STATUS ,Error status bit for APBH DMA channel 15" "No effect,Toggle" rbitfld.long 0x0C 30. " [14] ,Error status bit for APBH DMA channel 14" "No effect,Toggle" rbitfld.long 0x0C 29. " [13] ,Error status bit for APBH DMA channel 13" "No effect,Toggle" newline rbitfld.long 0x0C 28. " [12] ,Error status bit for APBH DMA channel 12" "No effect,Toggle" rbitfld.long 0x0C 27. " [11] ,Error status bit for APBH DMA channel 11" "No effect,Toggle" rbitfld.long 0x0C 26. " [10] ,Error status bit for APBH DMA channel 10" "No effect,Toggle" newline rbitfld.long 0x0C 25. " [9] ,Error status bit for APBH DMA channel 9" "No effect,Toggle" rbitfld.long 0x0C 24. " [8] ,Error status bit for APBH DMA channel 8" "No effect,Toggle" rbitfld.long 0x0C 23. " [7] ,Error status bit for APBH DMA channel 7" "No effect,Toggle" newline rbitfld.long 0x0C 22. " [6] ,Error status bit for APBH DMA channel 6" "No effect,Toggle" rbitfld.long 0x0C 21. " [5] ,Error status bit for APBH DMA channel 5" "No effect,Toggle" rbitfld.long 0x0C 20. " [4] ,Error status bit for APBH DMA channel 4" "No effect,Toggle" newline rbitfld.long 0x0C 19. " [3] ,Error status bit for APBH DMA channel 3" "No effect,Toggle" rbitfld.long 0x0C 18. " [2] ,Error status bit for APBH DMA channel 2" "No effect,Toggle" rbitfld.long 0x0C 17. " [1] ,Error status bit for APBH DMA channel 1" "No effect,Toggle" newline rbitfld.long 0x0C 16. " [0] ,Error status bit for APBH DMA channel 0" "No effect,Toggle" newline bitfld.long 0x0C 15. " CH[15]_ERROR_IRQ ,Error interrupt status bit for APBH DMA channel 15" "No effect,Toggle" bitfld.long 0x0C 14. " [14] ,Error interrupt status bit for APBH DMA channel 14" "No effect,Toggle" bitfld.long 0x0C 13. " [13] ,Error interrupt status bit for APBH DMA channel 13" "No effect,Toggle" newline bitfld.long 0x0C 12. " [12] ,Error interrupt status bit for APBH DMA channel 12" "No effect,Toggle" bitfld.long 0x0C 11. " [11] ,Error interrupt status bit for APBH DMA channel 11" "No effect,Toggle" bitfld.long 0x0C 10. " [10] ,Error interrupt status bit for APBH DMA channel 10" "No effect,Toggle" newline bitfld.long 0x0C 9. " [9] ,Error interrupt status bit for APBH DMA channel 9" "No effect,Toggle" bitfld.long 0x0C 8. " [8] ,Error interrupt status bit for APBH DMA channel 8" "No effect,Toggle" bitfld.long 0x0C 7. " [7] ,Error interrupt status bit for APBH DMA channel 7" "No effect,Toggle" newline bitfld.long 0x0C 6. " [6] ,Error interrupt status bit for APBH DMA channel 6" "No effect,Toggle" bitfld.long 0x0C 5. " [5] ,Error interrupt status bit for APBH DMA channel 5" "No effect,Toggle" bitfld.long 0x0C 4. " [4] ,Error interrupt status bit for APBH DMA channel 4" "No effect,Toggle" newline bitfld.long 0x0C 3. " [3] ,Error interrupt status bit for APBH DMA channel 3" "No effect,Toggle" bitfld.long 0x0C 2. " [2] ,Error interrupt status bit for APBH DMA channel 2" "No effect,Toggle" bitfld.long 0x0C 1. " [1] ,Error interrupt status bit for APBH DMA channel 1" "No effect,Toggle" newline bitfld.long 0x0C 0. " [0] ,Error interrupt status bit for APBH DMA channel 0" "No effect,Toggle" group.long 0x30++0x03 line.long 0x00 "CHANNEL_CTRL_SET/CLR,AHB To APBH Bridge Channel Set/Clear Register" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " RESET_CHANNEL[15] ,DMA channel 15 reset" "No reset,Reset" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [14] ,DMA channel 14 reset" "No reset,Reset" setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [13] ,DMA channel 13 reset" "No reset,Reset" newline setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [12] ,DMA channel 12 reset" "No reset,Reset" setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [11] ,DMA channel 11 reset" "No reset,Reset" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [10] ,DMA channel 10 reset" "No reset,Reset" newline setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [9] ,DMA channel 9 reset" "No reset,Reset" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [8] ,DMA channel 8 reset" "No reset,Reset" setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [7] ,DMA channel 7 reset" "No reset,Reset" newline setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [6] ,DMA channel 6 reset" "No reset,Reset" setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [5] ,DMA channel 5 reset" "No reset,Reset" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [4] ,DMA channel 4 reset" "No reset,Reset" newline setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [3] ,DMA channel 3 reset" "No reset,Reset" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [2] ,DMA channel 2 reset" "No reset,Reset" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [1] ,DMA channel 1 reset" "No reset,Reset" newline setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [0] ,DMA channel 0 reset" "No reset,Reset" newline setclrfld.long 0x00 15. 0x04 15. 0x08 15. " FREEZE_CHANNEL[15] ,DMA channel 15 freeze" "Not frozen,Frozen" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,DMA channel 14 freeze" "Not frozen,Frozen" newline setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,DMA channel 13 freeze" "Not frozen,Frozen" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,DMA channel 12 freeze" "Not frozen,Frozen" setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,DMA channel 11 freeze" "Not frozen,Frozen" newline setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,DMA channel 10 freeze" "Not frozen,Frozen" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,DMA channel 9 freeze" "Not frozen,Frozen" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,DMA channel 8 freeze" "Not frozen,Frozen" newline setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,DMA channel 7 freeze" "Not frozen,Frozen" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,DMA channel 6 freeze" "Not frozen,Frozen" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,DMA channel 5 freeze" "Not frozen,Frozen" newline setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,DMA channel 4 freeze" "Not frozen,Frozen" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,DMA channel 3 freeze" "Not frozen,Frozen" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,DMA channel 2 freeze" "Not frozen,Frozen" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,DMA channel 1 freeze" "Not frozen,Frozen" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,DMA channel 0 freeze" "Not frozen,Frozen" group.long 0x3C++0x03 line.long 0x00 "CHANNEL_CTRL_TOG,AHB To APBH Bridge Channel Toggle Register" bitfld.long 0x00 31. " RESET_CHANNEL[15] ,DMA channel 15 reset" "No effect,Toggle" bitfld.long 0x00 30. " [14] ,DMA channel 14 reset" "No effect,Toggle" bitfld.long 0x00 29. " [13] ,DMA channel 13 reset" "No effect,Toggle" newline bitfld.long 0x00 28. " [12] ,DMA channel 12 reset" "No effect,Toggle" bitfld.long 0x00 27. " [11] ,DMA channel 11 reset" "No effect,Toggle" bitfld.long 0x00 26. " [10] ,DMA channel 10 reset" "No effect,Toggle" newline bitfld.long 0x00 25. " [9] ,DMA channel 9 reset" "No effect,Toggle" bitfld.long 0x00 24. " [8] ,DMA channel 8 reset" "No effect,Toggle" bitfld.long 0x00 23. " [7] ,DMA channel 7 reset" "No effect,Toggle" newline bitfld.long 0x00 22. " [6] ,DMA channel 6 reset" "No effect,Toggle" bitfld.long 0x00 21. " [5] ,DMA channel 5 reset" "No effect,Toggle" bitfld.long 0x00 20. " [4] ,DMA channel 4 reset" "No effect,Toggle" newline bitfld.long 0x00 19. " [3] ,DMA channel 3 reset" "No effect,Toggle" bitfld.long 0x00 18. " [2] ,DMA channel 2 reset" "No effect,Toggle" bitfld.long 0x00 17. " [1] ,DMA channel 1 reset" "No effect,Toggle" newline bitfld.long 0x00 16. " [0] ,DMA channel 0 reset" "No effect,Toggle" newline bitfld.long 0x00 15. " FREEZE_CHANNEL[15] ,DMA channel 15 freeze" "No effect,Toggle" bitfld.long 0x00 14. " [14] ,DMA channel 14 freeze" "No effect,Toggle" newline bitfld.long 0x00 13. " [13] ,DMA channel 13 freeze" "No effect,Toggle" bitfld.long 0x00 12. " [12] ,DMA channel 12 freeze" "No effect,Toggle" bitfld.long 0x00 11. " [11] ,DMA channel 11 freeze" "No effect,Toggle" newline bitfld.long 0x00 10. " [10] ,DMA channel 10 freeze" "No effect,Toggle" bitfld.long 0x00 9. " [9] ,DMA channel 9 freeze" "No effect,Toggle" bitfld.long 0x00 8. " [8] ,DMA channel 8 freeze" "No effect,Toggle" newline bitfld.long 0x00 7. " [7] ,DMA channel 7 freeze" "No effect,Toggle" bitfld.long 0x00 6. " [6] ,DMA channel 6 freeze" "No effect,Toggle" bitfld.long 0x00 5. " [5] ,DMA channel 5 freeze" "No effect,Toggle" newline bitfld.long 0x00 4. " [4] ,DMA channel 4 freeze" "No effect,Toggle" bitfld.long 0x00 3. " [3] ,DMA channel 3 freeze" "No effect,Toggle" bitfld.long 0x00 2. " [2] ,DMA channel 2 freeze" "No effect,Toggle" newline bitfld.long 0x00 1. " [1] ,DMA channel 1 freeze" "No effect,Toggle" bitfld.long 0x00 0. " [0] ,DMA channel 0 freeze" "No effect,Toggle" group.long 0x50++0x03 line.long 0x00 "DMA_BURST_SIZE,AHB To APBH DMA Burst Size Register" bitfld.long 0x00 16.--17. " CH[8] ,DMA burst size for SSP" "BURST0,BURST4,BURST8,?..." bitfld.long 0x00 14.--15. " [7] ,DMA burst size for GPMI channel 7" ",BURST4,?..." bitfld.long 0x00 12.--13. " [6] ,DMA burst size for GPMI channel 6" ",BURST4,?..." newline bitfld.long 0x00 10.--11. " [5] ,DMA burst size for GPMI channel 5" ",BURST4,?..." bitfld.long 0x00 8.--9. " [4] ,DMA burst size for GPMI channel 4" ",BURST4,?..." bitfld.long 0x00 6.--7. " [3] ,DMA burst size for GPMI channel 3" ",BURST4,?..." newline bitfld.long 0x00 4.--5. " [2] ,DMA burst size for GPMI channel 2" ",BURST4,?..." bitfld.long 0x00 2.--3. " [1] ,DMA burst size for GPMI channel 1" ",BURST4,?..." bitfld.long 0x00 0.--1. " [0] ,DMA burst size for GPMI channel 0" ",BURST4,?..." group.long 0x60++0x03 line.long 0x00 "DEBUG,AHB To APBH DMA Debug Register" bitfld.long 0x00 0. " GPMI_ONE_FIFO ,DMA FIFO sharing" "Own,Shared" newline rgroup.long 0x100++0x03 line.long 0x00 "CH0_CURCMDAR,APBH DMA Channel 0 Current Command Address Register" group.long (0x100+0x10)++0x03 line.long 0x00 "CH0_NXTCMDAR,APBH DMA Channel 0 Next Command Address Register" rgroup.long (0x100+0x20)++0x03 line.long 0x00 "CH0_CMD,APBH DMA Channel 0 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No chain,Chain" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command after performing requested PIO word transfers" "Terminate before DMA transfer,DMA transfer from peripheral,DMA transfer to peripheral,Branch to the next chained device" rgroup.long (0x100+0x30)++0x03 line.long 0x00 "CH0_BAR,APBH DMA Channel 0 Buffer Address Register" group.long (0x100+0x40)++0x03 line.long 0x00 "CH0_SEMA,APBH DMA Channel 0 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x100+0x50)++0x03 line.long 0x00 "CH0_DEBUG1,AHB To APBH DMA Channel 0 Debug Information Register" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "Not requested,Requested" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "No burst,Burst" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal to the APB device" "Not kicked,Kicked" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "Not ended,Ended" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x100+0x60)++0x03 line.long 0x00 "CH0_DEBUG2,AHB To APBH DMA Channel 0 Debug Information Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x170++0x03 line.long 0x00 "CH1_CURCMDAR,APBH DMA Channel 1 Current Command Address Register" group.long (0x170+0x10)++0x03 line.long 0x00 "CH1_NXTCMDAR,APBH DMA Channel 1 Next Command Address Register" rgroup.long (0x170+0x20)++0x03 line.long 0x00 "CH1_CMD,APBH DMA Channel 1 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No chain,Chain" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command after performing requested PIO word transfers" "Terminate before DMA transfer,DMA transfer from peripheral,DMA transfer to peripheral,Branch to the next chained device" rgroup.long (0x170+0x30)++0x03 line.long 0x00 "CH1_BAR,APBH DMA Channel 1 Buffer Address Register" group.long (0x170+0x40)++0x03 line.long 0x00 "CH1_SEMA,APBH DMA Channel 1 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x170+0x50)++0x03 line.long 0x00 "CH1_DEBUG1,AHB To APBH DMA Channel 1 Debug Information Register" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "Not requested,Requested" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "No burst,Burst" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal to the APB device" "Not kicked,Kicked" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "Not ended,Ended" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x170+0x60)++0x03 line.long 0x00 "CH1_DEBUG2,AHB To APBH DMA Channel 1 Debug Information Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x1E0++0x03 line.long 0x00 "CH2_CURCMDAR,APBH DMA Channel 2 Current Command Address Register" group.long (0x1E0+0x10)++0x03 line.long 0x00 "CH2_NXTCMDAR,APBH DMA Channel 2 Next Command Address Register" rgroup.long (0x1E0+0x20)++0x03 line.long 0x00 "CH2_CMD,APBH DMA Channel 2 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No chain,Chain" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command after performing requested PIO word transfers" "Terminate before DMA transfer,DMA transfer from peripheral,DMA transfer to peripheral,Branch to the next chained device" rgroup.long (0x1E0+0x30)++0x03 line.long 0x00 "CH2_BAR,APBH DMA Channel 2 Buffer Address Register" group.long (0x1E0+0x40)++0x03 line.long 0x00 "CH2_SEMA,APBH DMA Channel 2 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x1E0+0x50)++0x03 line.long 0x00 "CH2_DEBUG1,AHB To APBH DMA Channel 2 Debug Information Register" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "Not requested,Requested" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "No burst,Burst" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal to the APB device" "Not kicked,Kicked" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "Not ended,Ended" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x1E0+0x60)++0x03 line.long 0x00 "CH2_DEBUG2,AHB To APBH DMA Channel 2 Debug Information Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x250++0x03 line.long 0x00 "CH3_CURCMDAR,APBH DMA Channel 3 Current Command Address Register" group.long (0x250+0x10)++0x03 line.long 0x00 "CH3_NXTCMDAR,APBH DMA Channel 3 Next Command Address Register" rgroup.long (0x250+0x20)++0x03 line.long 0x00 "CH3_CMD,APBH DMA Channel 3 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No chain,Chain" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command after performing requested PIO word transfers" "Terminate before DMA transfer,DMA transfer from peripheral,DMA transfer to peripheral,Branch to the next chained device" rgroup.long (0x250+0x30)++0x03 line.long 0x00 "CH3_BAR,APBH DMA Channel 3 Buffer Address Register" group.long (0x250+0x40)++0x03 line.long 0x00 "CH3_SEMA,APBH DMA Channel 3 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x250+0x50)++0x03 line.long 0x00 "CH3_DEBUG1,AHB To APBH DMA Channel 3 Debug Information Register" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "Not requested,Requested" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "No burst,Burst" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal to the APB device" "Not kicked,Kicked" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "Not ended,Ended" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x250+0x60)++0x03 line.long 0x00 "CH3_DEBUG2,AHB To APBH DMA Channel 3 Debug Information Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x2C0++0x03 line.long 0x00 "CH4_CURCMDAR,APBH DMA Channel 4 Current Command Address Register" group.long (0x2C0+0x10)++0x03 line.long 0x00 "CH4_NXTCMDAR,APBH DMA Channel 4 Next Command Address Register" rgroup.long (0x2C0+0x20)++0x03 line.long 0x00 "CH4_CMD,APBH DMA Channel 4 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No chain,Chain" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command after performing requested PIO word transfers" "Terminate before DMA transfer,DMA transfer from peripheral,DMA transfer to peripheral,Branch to the next chained device" rgroup.long (0x2C0+0x30)++0x03 line.long 0x00 "CH4_BAR,APBH DMA Channel 4 Buffer Address Register" group.long (0x2C0+0x40)++0x03 line.long 0x00 "CH4_SEMA,APBH DMA Channel 4 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x2C0+0x50)++0x03 line.long 0x00 "CH4_DEBUG1,AHB To APBH DMA Channel 4 Debug Information Register" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "Not requested,Requested" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "No burst,Burst" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal to the APB device" "Not kicked,Kicked" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "Not ended,Ended" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x2C0+0x60)++0x03 line.long 0x00 "CH4_DEBUG2,AHB To APBH DMA Channel 4 Debug Information Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x330++0x03 line.long 0x00 "CH5_CURCMDAR,APBH DMA Channel 5 Current Command Address Register" group.long (0x330+0x10)++0x03 line.long 0x00 "CH5_NXTCMDAR,APBH DMA Channel 5 Next Command Address Register" rgroup.long (0x330+0x20)++0x03 line.long 0x00 "CH5_CMD,APBH DMA Channel 5 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No chain,Chain" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command after performing requested PIO word transfers" "Terminate before DMA transfer,DMA transfer from peripheral,DMA transfer to peripheral,Branch to the next chained device" rgroup.long (0x330+0x30)++0x03 line.long 0x00 "CH5_BAR,APBH DMA Channel 5 Buffer Address Register" group.long (0x330+0x40)++0x03 line.long 0x00 "CH5_SEMA,APBH DMA Channel 5 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x330+0x50)++0x03 line.long 0x00 "CH5_DEBUG1,AHB To APBH DMA Channel 5 Debug Information Register" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "Not requested,Requested" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "No burst,Burst" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal to the APB device" "Not kicked,Kicked" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "Not ended,Ended" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x330+0x60)++0x03 line.long 0x00 "CH5_DEBUG2,AHB To APBH DMA Channel 5 Debug Information Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x3A0++0x03 line.long 0x00 "CH6_CURCMDAR,APBH DMA Channel 6 Current Command Address Register" group.long (0x3A0+0x10)++0x03 line.long 0x00 "CH6_NXTCMDAR,APBH DMA Channel 6 Next Command Address Register" rgroup.long (0x3A0+0x20)++0x03 line.long 0x00 "CH6_CMD,APBH DMA Channel 6 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No chain,Chain" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command after performing requested PIO word transfers" "Terminate before DMA transfer,DMA transfer from peripheral,DMA transfer to peripheral,Branch to the next chained device" rgroup.long (0x3A0+0x30)++0x03 line.long 0x00 "CH6_BAR,APBH DMA Channel 6 Buffer Address Register" group.long (0x3A0+0x40)++0x03 line.long 0x00 "CH6_SEMA,APBH DMA Channel 6 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x3A0+0x50)++0x03 line.long 0x00 "CH6_DEBUG1,AHB To APBH DMA Channel 6 Debug Information Register" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "Not requested,Requested" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "No burst,Burst" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal to the APB device" "Not kicked,Kicked" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "Not ended,Ended" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x3A0+0x60)++0x03 line.long 0x00 "CH6_DEBUG2,AHB To APBH DMA Channel 6 Debug Information Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x410++0x03 line.long 0x00 "CH7_CURCMDAR,APBH DMA Channel 7 Current Command Address Register" group.long (0x410+0x10)++0x03 line.long 0x00 "CH7_NXTCMDAR,APBH DMA Channel 7 Next Command Address Register" rgroup.long (0x410+0x20)++0x03 line.long 0x00 "CH7_CMD,APBH DMA Channel 7 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No chain,Chain" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command after performing requested PIO word transfers" "Terminate before DMA transfer,DMA transfer from peripheral,DMA transfer to peripheral,Branch to the next chained device" rgroup.long (0x410+0x30)++0x03 line.long 0x00 "CH7_BAR,APBH DMA Channel 7 Buffer Address Register" group.long (0x410+0x40)++0x03 line.long 0x00 "CH7_SEMA,APBH DMA Channel 7 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x410+0x50)++0x03 line.long 0x00 "CH7_DEBUG1,AHB To APBH DMA Channel 7 Debug Information Register" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "Not requested,Requested" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "No burst,Burst" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal to the APB device" "Not kicked,Kicked" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "Not ended,Ended" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x410+0x60)++0x03 line.long 0x00 "CH7_DEBUG2,AHB To APBH DMA Channel 7 Debug Information Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x480++0x03 line.long 0x00 "CH8_CURCMDAR,APBH DMA Channel 8 Current Command Address Register" group.long (0x480+0x10)++0x03 line.long 0x00 "CH8_NXTCMDAR,APBH DMA Channel 8 Next Command Address Register" rgroup.long (0x480+0x20)++0x03 line.long 0x00 "CH8_CMD,APBH DMA Channel 8 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No chain,Chain" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command after performing requested PIO word transfers" "Terminate before DMA transfer,DMA transfer from peripheral,DMA transfer to peripheral,Branch to the next chained device" rgroup.long (0x480+0x30)++0x03 line.long 0x00 "CH8_BAR,APBH DMA Channel 8 Buffer Address Register" group.long (0x480+0x40)++0x03 line.long 0x00 "CH8_SEMA,APBH DMA Channel 8 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x480+0x50)++0x03 line.long 0x00 "CH8_DEBUG1,AHB To APBH DMA Channel 8 Debug Information Register" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "Not requested,Requested" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "No burst,Burst" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal to the APB device" "Not kicked,Kicked" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "Not ended,Ended" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x480+0x60)++0x03 line.long 0x00 "CH8_DEBUG2,AHB To APBH DMA Channel 8 Debug Information Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x4F0++0x03 line.long 0x00 "CH9_CURCMDAR,APBH DMA Channel 9 Current Command Address Register" group.long (0x4F0+0x10)++0x03 line.long 0x00 "CH9_NXTCMDAR,APBH DMA Channel 9 Next Command Address Register" rgroup.long (0x4F0+0x20)++0x03 line.long 0x00 "CH9_CMD,APBH DMA Channel 9 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No chain,Chain" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command after performing requested PIO word transfers" "Terminate before DMA transfer,DMA transfer from peripheral,DMA transfer to peripheral,Branch to the next chained device" rgroup.long (0x4F0+0x30)++0x03 line.long 0x00 "CH9_BAR,APBH DMA Channel 9 Buffer Address Register" group.long (0x4F0+0x40)++0x03 line.long 0x00 "CH9_SEMA,APBH DMA Channel 9 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x4F0+0x50)++0x03 line.long 0x00 "CH9_DEBUG1,AHB To APBH DMA Channel 9 Debug Information Register" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "Not requested,Requested" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "No burst,Burst" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal to the APB device" "Not kicked,Kicked" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "Not ended,Ended" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x4F0+0x60)++0x03 line.long 0x00 "CH9_DEBUG2,AHB To APBH DMA Channel 9 Debug Information Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x560++0x03 line.long 0x00 "CH10_CURCMDAR,APBH DMA Channel 10 Current Command Address Register" group.long (0x560+0x10)++0x03 line.long 0x00 "CH10_NXTCMDAR,APBH DMA Channel 10 Next Command Address Register" rgroup.long (0x560+0x20)++0x03 line.long 0x00 "CH10_CMD,APBH DMA Channel 10 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No chain,Chain" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command after performing requested PIO word transfers" "Terminate before DMA transfer,DMA transfer from peripheral,DMA transfer to peripheral,Branch to the next chained device" rgroup.long (0x560+0x30)++0x03 line.long 0x00 "CH10_BAR,APBH DMA Channel 10 Buffer Address Register" group.long (0x560+0x40)++0x03 line.long 0x00 "CH10_SEMA,APBH DMA Channel 10 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x560+0x50)++0x03 line.long 0x00 "CH10_DEBUG1,AHB To APBH DMA Channel 10 Debug Information Register" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "Not requested,Requested" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "No burst,Burst" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal to the APB device" "Not kicked,Kicked" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "Not ended,Ended" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x560+0x60)++0x03 line.long 0x00 "CH10_DEBUG2,AHB To APBH DMA Channel 10 Debug Information Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x5D0++0x03 line.long 0x00 "CH11_CURCMDAR,APBH DMA Channel 11 Current Command Address Register" group.long (0x5D0+0x10)++0x03 line.long 0x00 "CH11_NXTCMDAR,APBH DMA Channel 11 Next Command Address Register" rgroup.long (0x5D0+0x20)++0x03 line.long 0x00 "CH11_CMD,APBH DMA Channel 11 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No chain,Chain" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command after performing requested PIO word transfers" "Terminate before DMA transfer,DMA transfer from peripheral,DMA transfer to peripheral,Branch to the next chained device" rgroup.long (0x5D0+0x30)++0x03 line.long 0x00 "CH11_BAR,APBH DMA Channel 11 Buffer Address Register" group.long (0x5D0+0x40)++0x03 line.long 0x00 "CH11_SEMA,APBH DMA Channel 11 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x5D0+0x50)++0x03 line.long 0x00 "CH11_DEBUG1,AHB To APBH DMA Channel 11 Debug Information Register" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "Not requested,Requested" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "No burst,Burst" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal to the APB device" "Not kicked,Kicked" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "Not ended,Ended" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x5D0+0x60)++0x03 line.long 0x00 "CH11_DEBUG2,AHB To APBH DMA Channel 11 Debug Information Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x640++0x03 line.long 0x00 "CH12_CURCMDAR,APBH DMA Channel 12 Current Command Address Register" group.long (0x640+0x10)++0x03 line.long 0x00 "CH12_NXTCMDAR,APBH DMA Channel 12 Next Command Address Register" rgroup.long (0x640+0x20)++0x03 line.long 0x00 "CH12_CMD,APBH DMA Channel 12 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No chain,Chain" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command after performing requested PIO word transfers" "Terminate before DMA transfer,DMA transfer from peripheral,DMA transfer to peripheral,Branch to the next chained device" rgroup.long (0x640+0x30)++0x03 line.long 0x00 "CH12_BAR,APBH DMA Channel 12 Buffer Address Register" group.long (0x640+0x40)++0x03 line.long 0x00 "CH12_SEMA,APBH DMA Channel 12 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x640+0x50)++0x03 line.long 0x00 "CH12_DEBUG1,AHB To APBH DMA Channel 12 Debug Information Register" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "Not requested,Requested" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "No burst,Burst" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal to the APB device" "Not kicked,Kicked" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "Not ended,Ended" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x640+0x60)++0x03 line.long 0x00 "CH12_DEBUG2,AHB To APBH DMA Channel 12 Debug Information Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x6B0++0x03 line.long 0x00 "CH13_CURCMDAR,APBH DMA Channel 13 Current Command Address Register" group.long (0x6B0+0x10)++0x03 line.long 0x00 "CH13_NXTCMDAR,APBH DMA Channel 13 Next Command Address Register" rgroup.long (0x6B0+0x20)++0x03 line.long 0x00 "CH13_CMD,APBH DMA Channel 13 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No chain,Chain" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command after performing requested PIO word transfers" "Terminate before DMA transfer,DMA transfer from peripheral,DMA transfer to peripheral,Branch to the next chained device" rgroup.long (0x6B0+0x30)++0x03 line.long 0x00 "CH13_BAR,APBH DMA Channel 13 Buffer Address Register" group.long (0x6B0+0x40)++0x03 line.long 0x00 "CH13_SEMA,APBH DMA Channel 13 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x6B0+0x50)++0x03 line.long 0x00 "CH13_DEBUG1,AHB To APBH DMA Channel 13 Debug Information Register" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "Not requested,Requested" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "No burst,Burst" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal to the APB device" "Not kicked,Kicked" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "Not ended,Ended" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x6B0+0x60)++0x03 line.long 0x00 "CH13_DEBUG2,AHB To APBH DMA Channel 13 Debug Information Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x720++0x03 line.long 0x00 "CH14_CURCMDAR,APBH DMA Channel 14 Current Command Address Register" group.long (0x720+0x10)++0x03 line.long 0x00 "CH14_NXTCMDAR,APBH DMA Channel 14 Next Command Address Register" rgroup.long (0x720+0x20)++0x03 line.long 0x00 "CH14_CMD,APBH DMA Channel 14 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No chain,Chain" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command after performing requested PIO word transfers" "Terminate before DMA transfer,DMA transfer from peripheral,DMA transfer to peripheral,Branch to the next chained device" rgroup.long (0x720+0x30)++0x03 line.long 0x00 "CH14_BAR,APBH DMA Channel 14 Buffer Address Register" group.long (0x720+0x40)++0x03 line.long 0x00 "CH14_SEMA,APBH DMA Channel 14 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x720+0x50)++0x03 line.long 0x00 "CH14_DEBUG1,AHB To APBH DMA Channel 14 Debug Information Register" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "Not requested,Requested" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "No burst,Burst" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal to the APB device" "Not kicked,Kicked" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "Not ended,Ended" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x720+0x60)++0x03 line.long 0x00 "CH14_DEBUG2,AHB To APBH DMA Channel 14 Debug Information Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x790++0x03 line.long 0x00 "CH15_CURCMDAR,APBH DMA Channel 15 Current Command Address Register" group.long (0x790+0x10)++0x03 line.long 0x00 "CH15_NXTCMDAR,APBH DMA Channel 15 Next Command Address Register" rgroup.long (0x790+0x20)++0x03 line.long 0x00 "CH15_CMD,APBH DMA Channel 15 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Indicates the number of command words to send to the GPMI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" newline bitfld.long 0x00 7. " WAIT4ENDCMD ,Waits for the end of CMD" "No wait,Wait" bitfld.long 0x00 6. " SEMAPHORE ,Indicates that the channel will decrement its semaphore at the completion of the current command structure" "No decrementation,Decrementation" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel will wait until the NAND device reports to be ready" "No wait,Wait" newline bitfld.long 0x00 4. " NANDLOCK ,NAND lock" "Not locked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt status bit to be set upon completion of the current command" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,Indicates that another command is chained onto the end of the current command structure" "No chain,Chain" newline bitfld.long 0x00 0.--1. " COMMAND ,Indicates the type of current command after performing requested PIO word transfers" "Terminate before DMA transfer,DMA transfer from peripheral,DMA transfer to peripheral,Branch to the next chained device" rgroup.long (0x790+0x30)++0x03 line.long 0x00 "CH15_BAR,APBH DMA Channel 15 Buffer Address Register" group.long (0x790+0x40)++0x03 line.long 0x00 "CH15_SEMA,APBH DMA Channel 15 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Shows the current (Instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Adds a value written to this field to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected" rgroup.long (0x790+0x50)++0x03 line.long 0x00 "CH15_DEBUG1,AHB To APBH DMA Channel 15 Debug Information Register" bitfld.long 0x00 31. " REQ ,Reflects the current state of the DMA request signal from the APB device" "Not requested,Requested" bitfld.long 0x00 30. " BURST ,Reflects the current state of the DMA burst signal from the APB device" "No burst,Burst" bitfld.long 0x00 29. " KICK ,Reflects the current state of the DMA kick signal to the APB device" "Not kicked,Kicked" newline bitfld.long 0x00 28. " END ,Reflects the current state of the DMA end command signal from the APB device" "Not ended,Ended" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Reflects the internal bit which indicates whether the channel's next command address is valid" "Invalid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,Reflects the current state of the DMA channel's read FIFO empty signal" "Not empty,Empty" newline bitfld.long 0x00 22. " RD_FIFO_FULL ,Reflects the current state of the DMA channel's read FIFO full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,Reflects the current state of the DMA channel's write FIFO empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,Reflects the current state of the DMA channel's write FIFO full signal" "Not full,Full" newline bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO display of the DMA channel n state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,,,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,,,,,TERMINATE,WAIT_END,,,,,,,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x790+0x60)++0x03 line.long 0x00 "CH15_DEBUG2,AHB To APBH DMA Channel 15 Debug Information Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,Reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,Reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x800++0x03 line.long 0x00 "VERSION,APBH Bridge Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Reflects the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Reflects the MINOR field of the RTL version" hexmask.long.word 0x00 0.--15. 1. " STEP ,Reflects the stepping of the RTL version" width 0x0B tree.end ; tree "BCH (62BIT Correcting ECC Accelerator)" ; base ad:0x00 ; %include imx8x/bch.ph ; tree.end tree "MLB (Media Local Bus)" base ad:0x5B060000 width 8. group.long 0x00++0x03 line.long 0x00 "MLBC0,MediaLB Control 0 Register" bitfld.long 0x00 15.--17. " FCNT ,The number of frames per sub-buffer for synchronous channels" "1,2,4,8,16,32,64,?..." bitfld.long 0x00 14. " CTLRETRY ,Control Tx packet retry enable" "Disabled,Enabled" bitfld.long 0x00 12. " ASYRETRY ,Asynchronous Tx packet retry enable" "Disabled,Enabled" newline rbitfld.long 0x00 7. " MLBLK ,MediaLB lock status" "Unlocked,Locked" bitfld.long 0x00 2.--4. " MLBCLK_2_0 ,MediaLB clock speed select" "256,512,1024,?..." bitfld.long 0x00 0. " MLBEN ,MediaLB enable" "Disabled,Enabled" rgroup.long 0x0C++0x03 line.long 0x00 "MS0,MediaLB Channel Status Register 0" bitfld.long 0x00 31. " MCS[31] ,MediaLB channel 31 status" "0,1" bitfld.long 0x00 30. " [30] ,MediaLB channel 30 status" "0,1" bitfld.long 0x00 29. " [29] ,MediaLB channel 29 status" "0,1" bitfld.long 0x00 28. " [28] ,MediaLB channel 28 status" "0,1" newline bitfld.long 0x00 27. " [27] ,MediaLB channel 27 status" "0,1" bitfld.long 0x00 26. " [26] ,MediaLB channel 26 status" "0,1" bitfld.long 0x00 25. " [25] ,MediaLB channel 25 status" "0,1" bitfld.long 0x00 24. " [24] ,MediaLB channel 24 status" "0,1" newline bitfld.long 0x00 23. " [23] ,MediaLB channel 23 status" "0,1" bitfld.long 0x00 22. " [22] ,MediaLB channel 22 status" "0,1" bitfld.long 0x00 21. " [21] ,MediaLB channel 21 status" "0,1" bitfld.long 0x00 20. " [20] ,MediaLB channel 20 status" "0,1" newline bitfld.long 0x00 19. " [19] ,MediaLB channel 19 status" "0,1" bitfld.long 0x00 18. " [18] ,MediaLB channel 18 status" "0,1" bitfld.long 0x00 17. " [17] ,MediaLB channel 17 status" "0,1" bitfld.long 0x00 16. " [16] ,MediaLB channel 16 status" "0,1" newline bitfld.long 0x00 15. " [15] ,MediaLB channel 15 status" "0,1" bitfld.long 0x00 14. " [14] ,MediaLB channel 14 status" "0,1" bitfld.long 0x00 13. " [13] ,MediaLB channel 13 status" "0,1" bitfld.long 0x00 12. " [12] ,MediaLB channel 12 status" "0,1" newline bitfld.long 0x00 11. " [11] ,MediaLB channel 11 status" "0,1" bitfld.long 0x00 10. " [10] ,MediaLB channel 10 status" "0,1" bitfld.long 0x00 9. " [9] ,MediaLB channel 9 status" "0,1" bitfld.long 0x00 8. " [8] ,MediaLB channel 8 status" "0,1" newline bitfld.long 0x00 7. " [7] ,MediaLB channel 7 status" "0,1" bitfld.long 0x00 6. " [6] ,MediaLB channel 6 status" "0,1" bitfld.long 0x00 5. " [5] ,MediaLB channel 5 status" "0,1" bitfld.long 0x00 4. " [4] ,MediaLB channel 4 status" "0,1" newline bitfld.long 0x00 3. " [3] ,MediaLB channel 3 status" "0,1" bitfld.long 0x00 2. " [2] ,MediaLB channel 2 status" "0,1" bitfld.long 0x00 1. " [1] ,MediaLB channel 1 status" "0,1" bitfld.long 0x00 0. " [0] ,MediaLB channel 0 status" "0,1" group.long 0x0D++0x03 line.long 0x00 "MLBPC2,MediaLB Control Register" bitfld.long 0x00 15. " MORCE ,Output reference clock enable" "Enabled,Disabled" hexmask.long.byte 0x00 8.--14. 1. " MORCD ,MediaLB divider factor" bitfld.long 0x00 0. " SDOPC ,Signal/Data output phase control" "Rising,Falling" rgroup.long 0x14++0x03 line.long 0x00 "MS1,MediaLB Channel Status Register 1" bitfld.long 0x00 31. " MCS[63] ,MediaLB channel 63 status" "0,1" bitfld.long 0x00 30. " [62] ,MediaLB channel 62 status" "0,1" bitfld.long 0x00 29. " [61] ,MediaLB channel 61 status" "0,1" bitfld.long 0x00 28. " [60] ,MediaLB channel 60 status" "0,1" newline bitfld.long 0x00 27. " [59] ,MediaLB channel 59 status" "0,1" bitfld.long 0x00 26. " [58] ,MediaLB channel 58 status" "0,1" bitfld.long 0x00 25. " [57] ,MediaLB channel 57 status" "0,1" bitfld.long 0x00 24. " [56] ,MediaLB channel 56 status" "0,1" newline bitfld.long 0x00 23. " [55] ,MediaLB channel 55 status" "0,1" bitfld.long 0x00 22. " [54] ,MediaLB channel 54 status" "0,1" bitfld.long 0x00 21. " [53] ,MediaLB channel 53 status" "0,1" bitfld.long 0x00 20. " [52] ,MediaLB channel 52 status" "0,1" newline bitfld.long 0x00 19. " [51] ,MediaLB channel 51 status" "0,1" bitfld.long 0x00 18. " [50] ,MediaLB channel 50 status" "0,1" bitfld.long 0x00 17. " [49] ,MediaLB channel 49 status" "0,1" bitfld.long 0x00 16. " [48] ,MediaLB channel 48 status" "0,1" newline bitfld.long 0x00 15. " [47] ,MediaLB channel 47 status" "0,1" bitfld.long 0x00 14. " [46] ,MediaLB channel 46 status" "0,1" bitfld.long 0x00 13. " [45] ,MediaLB channel 45 status" "0,1" bitfld.long 0x00 12. " [44] ,MediaLB channel 44 status" "0,1" newline bitfld.long 0x00 11. " [43] ,MediaLB channel 43 status" "0,1" bitfld.long 0x00 10. " [42] ,MediaLB channel 42 status" "0,1" bitfld.long 0x00 9. " [41] ,MediaLB channel 41 status" "0,1" bitfld.long 0x00 8. " [40] ,MediaLB channel 40 status" "0,1" newline bitfld.long 0x00 7. " [39] ,MediaLB channel 39 status" "0,1" bitfld.long 0x00 6. " [38] ,MediaLB channel 38 status" "0,1" bitfld.long 0x00 5. " [37] ,MediaLB channel 37 status" "0,1" bitfld.long 0x00 4. " [36] ,MediaLB channel 36 status" "0,1" newline bitfld.long 0x00 3. " [35] ,MediaLB channel 35 status" "0,1" bitfld.long 0x00 2. " [34] ,MediaLB channel 34 status" "0,1" bitfld.long 0x00 1. " [33] ,MediaLB channel 33 status" "0,1" bitfld.long 0x00 0. " [32] ,MediaLB channel 32 status" "0,1" group.long 0x20++0x03 line.long 0x00 "MSS,MediaLB System Status Register" bitfld.long 0x00 5. " SERVREQ ,Service request enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SWSYSCMD ,Software system command detected" "Not detected,Detected" rbitfld.long 0x00 3. " CSSYSCMD ,Channel scan system command detected" "Not detected,Detected" rbitfld.long 0x00 2. " ULKSYSCMD ,Network unlock system command detected" "Not detected,Detected" newline rbitfld.long 0x00 1. " LKSSYSCMD ,Network lock system command detected" "Not detected,Detected" rbitfld.long 0x00 0. " RSTSYSCMD ,Reset system command detected" "Not detected,Detected" rgroup.long 0x24++0x03 line.long 0x00 "MSD,MediaLB System Data Register" hexmask.long.byte 0x00 24.--31. 1. " SD3_7_0 ,System data (byte 3)" hexmask.long.byte 0x00 16.--23. 1. " SD2_7_0 ,System data (byte 2)" hexmask.long.byte 0x00 8.--15. 1. " SD1_7_0 ,System data (byte 1)" hexmask.long.byte 0x00 0.--7. 1. " SD0_7_0 ,System data (byte 0)" group.long 0x2C++0x03 line.long 0x00 "MIEN,MediaLB Interrupt Enable Register" bitfld.long 0x00 29. " CTX_BREAK ,Control Tx break enable" "Disabled,Enabled" bitfld.long 0x00 28. " CTX_PE ,Control Tx protocol error enable" "Disabled,Enabled" bitfld.long 0x00 27. " CTX_DONE ,Control Tx packet done enable" "Disabled,Enabled" bitfld.long 0x00 26. " CRX_BREAK ,Control Rx break enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " CRX_PE ,Control Rx protocol error enable" "Disabled,Enabled" bitfld.long 0x00 24. " CRX_DONE ,Control Rx packet done enable" "Disabled,Enabled" bitfld.long 0x00 22. " ATX_BREAK ,Asynchronous Tx break enable" "Disabled,Enabled" bitfld.long 0x00 21. " ATX_PE ,Asynchronous Tx protocol error enable" "Disabled,Enabled" newline bitfld.long 0x00 20. " ATX_DONE ,Asynchronous Tx packet done enable" "Disabled,Enabled" bitfld.long 0x00 19. " ARX_BREAK ,Asynchronous Rx break enable" "Disabled,Enabled" bitfld.long 0x00 18. " ARX_PE ,Asynchronous Rx protocol error enable" "Disabled,Enabled" bitfld.long 0x00 17. " ARX_DONE ,Asynchronous Rx packet done enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " SYNC_PE ,Synchronous Rx protocol error enable" "Disabled,Enabled" bitfld.long 0x00 1. " ISOC_BUFO ,Isochronous Rx buffer overflow enable" "Disabled,Enabled" bitfld.long 0x00 0. " ISOC_PE ,Isochronous Rx protocol error enable" "Disabled,Enabled" group.long 0x3C++0x03 line.long 0x00 "MLBC1,MediaLB Control 1 Register" hexmask.long.byte 0x00 8.--15. 0x01 " NDA_7_0 ,Node device address" rbitfld.long 0x00 7. " CLKM ,MediaLB clock missing status" "No,Yes" rbitfld.long 0x00 6. " LOCK ,MediaLB lock error status" "No,Yes" group.long 0x80++0x03 line.long 0x00 "HCTL,HBI Control Register" bitfld.long 0x00 15. " EN ,HBI enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST1 ,AGU1 software reset" "Active,Reset" bitfld.long 0x00 0. " RST0 ,AGU0 software reset" "Active,Reset" group.long 0x88++0x07 line.long 0x00 "HCMR0,HBI Channel Mask 0 Register" bitfld.long 0x00 31. " CHM[31] ,Bitwise channel mask bit 31" "Masked,Unmasked" bitfld.long 0x00 30. " [30] ,Bitwise channel mask bit 30" "Masked,Unmasked" bitfld.long 0x00 29. " [29] ,Bitwise channel mask bit 29" "Masked,Unmasked" bitfld.long 0x00 28. " [28] ,Bitwise channel mask bit 28" "Masked,Unmasked" newline bitfld.long 0x00 27. " [27] ,Bitwise channel mask bit 27" "Masked,Unmasked" bitfld.long 0x00 26. " [26] ,Bitwise channel mask bit 26" "Masked,Unmasked" bitfld.long 0x00 25. " [25] ,Bitwise channel mask bit 25" "Masked,Unmasked" bitfld.long 0x00 24. " [24] ,Bitwise channel mask bit 24" "Masked,Unmasked" newline bitfld.long 0x00 23. " [23] ,Bitwise channel mask bit 23" "Masked,Unmasked" bitfld.long 0x00 22. " [22] ,Bitwise channel mask bit 22" "Masked,Unmasked" bitfld.long 0x00 21. " [21] ,Bitwise channel mask bit 21" "Masked,Unmasked" bitfld.long 0x00 20. " [20] ,Bitwise channel mask bit 20" "Masked,Unmasked" newline bitfld.long 0x00 19. " [19] ,Bitwise channel mask bit 19" "Masked,Unmasked" bitfld.long 0x00 18. " [18] ,Bitwise channel mask bit 18" "Masked,Unmasked" bitfld.long 0x00 17. " [17] ,Bitwise channel mask bit 17" "Masked,Unmasked" bitfld.long 0x00 16. " [16] ,Bitwise channel mask bit 16" "Masked,Unmasked" newline bitfld.long 0x00 15. " [15] ,Bitwise channel mask bit 15" "Masked,Unmasked" bitfld.long 0x00 14. " [14] ,Bitwise channel mask bit 14" "Masked,Unmasked" bitfld.long 0x00 13. " [13] ,Bitwise channel mask bit 13" "Masked,Unmasked" bitfld.long 0x00 12. " [12] ,Bitwise channel mask bit 12" "Masked,Unmasked" newline bitfld.long 0x00 11. " [11] ,Bitwise channel mask bit 11" "Masked,Unmasked" bitfld.long 0x00 10. " [10] ,Bitwise channel mask bit 10" "Masked,Unmasked" bitfld.long 0x00 9. " [9] ,Bitwise channel mask bit 9" "Masked,Unmasked" bitfld.long 0x00 8. " [8] ,Bitwise channel mask bit 8" "Masked,Unmasked" newline bitfld.long 0x00 7. " [7] ,Bitwise channel mask bit 7" "Masked,Unmasked" bitfld.long 0x00 6. " [6] ,Bitwise channel mask bit 6" "Masked,Unmasked" bitfld.long 0x00 5. " [5] ,Bitwise channel mask bit 5" "Masked,Unmasked" bitfld.long 0x00 4. " [4] ,Bitwise channel mask bit 4" "Masked,Unmasked" newline bitfld.long 0x00 3. " [3] ,Bitwise channel mask bit 3" "Masked,Unmasked" bitfld.long 0x00 2. " [2] ,Bitwise channel mask bit 2" "Masked,Unmasked" bitfld.long 0x00 1. " [1] ,Bitwise channel mask bit 1" "Masked,Unmasked" bitfld.long 0x00 0. " [0] ,Bitwise channel mask bit 0" "Masked,Unmasked" line.long 0x04 "HCMR1,HBI Channel Mask 1 Register" bitfld.long 0x04 31. " CHM[63] ,Bitwise channel mask bit 63" "Masked,Unmasked" bitfld.long 0x04 30. " [62] ,Bitwise channel mask bit 62" "Masked,Unmasked" bitfld.long 0x04 29. " [61] ,Bitwise channel mask bit 61" "Masked,Unmasked" bitfld.long 0x04 28. " [60] ,Bitwise channel mask bit 60" "Masked,Unmasked" newline bitfld.long 0x04 27. " [59] ,Bitwise channel mask bit 59" "Masked,Unmasked" bitfld.long 0x04 26. " [58] ,Bitwise channel mask bit 58" "Masked,Unmasked" bitfld.long 0x04 25. " [57] ,Bitwise channel mask bit 57" "Masked,Unmasked" bitfld.long 0x04 24. " [56] ,Bitwise channel mask bit 56" "Masked,Unmasked" newline bitfld.long 0x04 23. " [55] ,Bitwise channel mask bit 55" "Masked,Unmasked" bitfld.long 0x04 22. " [54] ,Bitwise channel mask bit 54" "Masked,Unmasked" bitfld.long 0x04 21. " [53] ,Bitwise channel mask bit 53" "Masked,Unmasked" bitfld.long 0x04 20. " [52] ,Bitwise channel mask bit 52" "Masked,Unmasked" newline bitfld.long 0x04 19. " [51] ,Bitwise channel mask bit 51" "Masked,Unmasked" bitfld.long 0x04 18. " [50] ,Bitwise channel mask bit 50" "Masked,Unmasked" bitfld.long 0x04 17. " [49] ,Bitwise channel mask bit 49" "Masked,Unmasked" bitfld.long 0x04 16. " [48] ,Bitwise channel mask bit 48" "Masked,Unmasked" newline bitfld.long 0x04 15. " [47] ,Bitwise channel mask bit 47" "Masked,Unmasked" bitfld.long 0x04 14. " [46] ,Bitwise channel mask bit 46" "Masked,Unmasked" bitfld.long 0x04 13. " [45] ,Bitwise channel mask bit 45" "Masked,Unmasked" bitfld.long 0x04 12. " [44] ,Bitwise channel mask bit 44" "Masked,Unmasked" newline bitfld.long 0x04 11. " [43] ,Bitwise channel mask bit 43" "Masked,Unmasked" bitfld.long 0x04 10. " [42] ,Bitwise channel mask bit 42" "Masked,Unmasked" bitfld.long 0x04 9. " [41] ,Bitwise channel mask bit 41" "Masked,Unmasked" bitfld.long 0x04 8. " [40] ,Bitwise channel mask bit 40" "Masked,Unmasked" newline bitfld.long 0x04 7. " [39] ,Bitwise channel mask bit 39" "Masked,Unmasked" bitfld.long 0x04 6. " [38] ,Bitwise channel mask bit 38" "Masked,Unmasked" bitfld.long 0x04 5. " [37] ,Bitwise channel mask bit 37" "Masked,Unmasked" bitfld.long 0x04 4. " [36] ,Bitwise channel mask bit 36" "Masked,Unmasked" newline bitfld.long 0x04 3. " [35] ,Bitwise channel mask bit 35" "Masked,Unmasked" bitfld.long 0x04 2. " [34] ,Bitwise channel mask bit 34" "Masked,Unmasked" bitfld.long 0x04 1. " [33] ,Bitwise channel mask bit 33" "Masked,Unmasked" bitfld.long 0x04 0. " [32] ,Bitwise channel mask bit 32" "Masked,Unmasked" rgroup.long 0x90++0x0F line.long 0x00 "HCER0,HBI Channel Error 0 Register" bitfld.long 0x00 31. " CERR[31] ,Bitwise channel error bit 31" "No error,Error" bitfld.long 0x00 30. " [30] ,Bitwise channel error bit 30" "No error,Error" bitfld.long 0x00 29. " [29] ,Bitwise channel error bit 29" "No error,Error" bitfld.long 0x00 28. " [28] ,Bitwise channel error bit 28" "No error,Error" newline bitfld.long 0x00 27. " [27] ,Bitwise channel error bit 27" "No error,Error" bitfld.long 0x00 26. " [26] ,Bitwise channel error bit 26" "No error,Error" bitfld.long 0x00 25. " [25] ,Bitwise channel error bit 25" "No error,Error" bitfld.long 0x00 24. " [24] ,Bitwise channel error bit 24" "No error,Error" newline bitfld.long 0x00 23. " [23] ,Bitwise channel error bit 23" "No error,Error" bitfld.long 0x00 22. " [22] ,Bitwise channel error bit 22" "No error,Error" bitfld.long 0x00 21. " [21] ,Bitwise channel error bit 21" "No error,Error" bitfld.long 0x00 20. " [20] ,Bitwise channel error bit 20" "No error,Error" newline bitfld.long 0x00 19. " [19] ,Bitwise channel error bit 19" "No error,Error" bitfld.long 0x00 18. " [18] ,Bitwise channel error bit 18" "No error,Error" bitfld.long 0x00 17. " [17] ,Bitwise channel error bit 17" "No error,Error" bitfld.long 0x00 16. " [16] ,Bitwise channel error bit 16" "No error,Error" newline bitfld.long 0x00 15. " [15] ,Bitwise channel error bit 15" "No error,Error" bitfld.long 0x00 14. " [14] ,Bitwise channel error bit 14" "No error,Error" bitfld.long 0x00 13. " [13] ,Bitwise channel error bit 13" "No error,Error" bitfld.long 0x00 12. " [12] ,Bitwise channel error bit 12" "No error,Error" newline bitfld.long 0x00 11. " [11] ,Bitwise channel error bit 11" "No error,Error" bitfld.long 0x00 10. " [10] ,Bitwise channel error bit 10" "No error,Error" bitfld.long 0x00 9. " [9] ,Bitwise channel error bit 9" "No error,Error" bitfld.long 0x00 8. " [8] ,Bitwise channel error bit 8" "No error,Error" newline bitfld.long 0x00 7. " [7] ,Bitwise channel error bit 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Bitwise channel error bit 6" "No error,Error" bitfld.long 0x00 5. " [5] ,Bitwise channel error bit 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Bitwise channel error bit 4" "No error,Error" newline bitfld.long 0x00 3. " [3] ,Bitwise channel error bit 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Bitwise channel error bit 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Bitwise channel error bit 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Bitwise channel error bit 0" "No error,Error" line.long 0x04 "HCER1,HBI Channel Error 1 Register" bitfld.long 0x04 31. " CERR[63] ,Bitwise channel error bit 63" "No error,Error" bitfld.long 0x04 30. " [62] ,Bitwise channel error bit 62" "No error,Error" bitfld.long 0x04 29. " [61] ,Bitwise channel error bit 61" "No error,Error" bitfld.long 0x04 28. " [60] ,Bitwise channel error bit 60" "No error,Error" newline bitfld.long 0x04 27. " [59] ,Bitwise channel error bit 59" "No error,Error" bitfld.long 0x04 26. " [58] ,Bitwise channel error bit 58" "No error,Error" bitfld.long 0x04 25. " [57] ,Bitwise channel error bit 57" "No error,Error" bitfld.long 0x04 24. " [56] ,Bitwise channel error bit 56" "No error,Error" newline bitfld.long 0x04 23. " [55] ,Bitwise channel error bit 55" "No error,Error" bitfld.long 0x04 22. " [54] ,Bitwise channel error bit 54" "No error,Error" bitfld.long 0x04 21. " [53] ,Bitwise channel error bit 53" "No error,Error" bitfld.long 0x04 20. " [52] ,Bitwise channel error bit 52" "No error,Error" newline bitfld.long 0x04 19. " [51] ,Bitwise channel error bit 51" "No error,Error" bitfld.long 0x04 18. " [50] ,Bitwise channel error bit 50" "No error,Error" bitfld.long 0x04 17. " [49] ,Bitwise channel error bit 49" "No error,Error" bitfld.long 0x04 16. " [48] ,Bitwise channel error bit 48" "No error,Error" newline bitfld.long 0x04 15. " [47] ,Bitwise channel error bit 47" "No error,Error" bitfld.long 0x04 14. " [46] ,Bitwise channel error bit 46" "No error,Error" bitfld.long 0x04 13. " [45] ,Bitwise channel error bit 45" "No error,Error" bitfld.long 0x04 12. " [44] ,Bitwise channel error bit 44" "No error,Error" newline bitfld.long 0x04 11. " [43] ,Bitwise channel error bit 43" "No error,Error" bitfld.long 0x04 10. " [42] ,Bitwise channel error bit 42" "No error,Error" bitfld.long 0x04 9. " [41] ,Bitwise channel error bit 41" "No error,Error" bitfld.long 0x04 8. " [40] ,Bitwise channel error bit 40" "No error,Error" newline bitfld.long 0x04 7. " [39] ,Bitwise channel error bit 39" "No error,Error" bitfld.long 0x04 6. " [38] ,Bitwise channel error bit 38" "No error,Error" bitfld.long 0x04 5. " [37] ,Bitwise channel error bit 37" "No error,Error" bitfld.long 0x04 4. " [36] ,Bitwise channel error bit 36" "No error,Error" newline bitfld.long 0x04 3. " [35] ,Bitwise channel error bit 35" "No error,Error" bitfld.long 0x04 2. " [34] ,Bitwise channel error bit 34" "No error,Error" bitfld.long 0x04 1. " [33] ,Bitwise channel error bit 33" "No error,Error" bitfld.long 0x04 0. " [32] ,Bitwise channel error bit 32" "No error,Error" line.long 0x08 "HCBR0,HBI Channel Busy 0 Register" bitfld.long 0x08 31. " CHB[31] ,Bitwise channel busy bit 31" "Idle,Busy" bitfld.long 0x08 30. " [30] ,Bitwise channel busy bit 30" "Idle,Busy" bitfld.long 0x08 29. " [29] ,Bitwise channel busy bit 29" "Idle,Busy" bitfld.long 0x08 28. " [28] ,Bitwise channel busy bit 28" "Idle,Busy" newline bitfld.long 0x08 27. " [27] ,Bitwise channel busy bit 27" "Idle,Busy" bitfld.long 0x08 26. " [26] ,Bitwise channel busy bit 26" "Idle,Busy" bitfld.long 0x08 25. " [25] ,Bitwise channel busy bit 25" "Idle,Busy" bitfld.long 0x08 24. " [24] ,Bitwise channel busy bit 24" "Idle,Busy" newline bitfld.long 0x08 23. " [23] ,Bitwise channel busy bit 23" "Idle,Busy" bitfld.long 0x08 22. " [22] ,Bitwise channel busy bit 22" "Idle,Busy" bitfld.long 0x08 21. " [21] ,Bitwise channel busy bit 21" "Idle,Busy" bitfld.long 0x08 20. " [20] ,Bitwise channel busy bit 20" "Idle,Busy" newline bitfld.long 0x08 19. " [19] ,Bitwise channel busy bit 19" "Idle,Busy" bitfld.long 0x08 18. " [18] ,Bitwise channel busy bit 18" "Idle,Busy" bitfld.long 0x08 17. " [17] ,Bitwise channel busy bit 17" "Idle,Busy" bitfld.long 0x08 16. " [16] ,Bitwise channel busy bit 16" "Idle,Busy" newline bitfld.long 0x08 15. " [15] ,Bitwise channel busy bit 15" "Idle,Busy" bitfld.long 0x08 14. " [14] ,Bitwise channel busy bit 14" "Idle,Busy" bitfld.long 0x08 13. " [13] ,Bitwise channel busy bit 13" "Idle,Busy" bitfld.long 0x08 12. " [12] ,Bitwise channel busy bit 12" "Idle,Busy" newline bitfld.long 0x08 11. " [11] ,Bitwise channel busy bit 11" "Idle,Busy" bitfld.long 0x08 10. " [10] ,Bitwise channel busy bit 10" "Idle,Busy" bitfld.long 0x08 9. " [9] ,Bitwise channel busy bit 9" "Idle,Busy" bitfld.long 0x08 8. " [8] ,Bitwise channel busy bit 8" "Idle,Busy" newline bitfld.long 0x08 7. " [7] ,Bitwise channel busy bit 7" "Idle,Busy" bitfld.long 0x08 6. " [6] ,Bitwise channel busy bit 6" "Idle,Busy" bitfld.long 0x08 5. " [5] ,Bitwise channel busy bit 5" "Idle,Busy" bitfld.long 0x08 4. " [4] ,Bitwise channel busy bit 4" "Idle,Busy" newline bitfld.long 0x08 3. " [3] ,Bitwise channel busy bit 3" "Idle,Busy" bitfld.long 0x08 2. " [2] ,Bitwise channel busy bit 2" "Idle,Busy" bitfld.long 0x08 1. " [1] ,Bitwise channel busy bit 1" "Idle,Busy" bitfld.long 0x08 0. " [0] ,Bitwise channel busy bit 0" "Idle,Busy" line.long 0x0C "HCBR1,HBI Channel Busy 1 Register" bitfld.long 0x0C 31. " CHB[63] ,Bitwise channel busy bit 63" "Idle,Busy" bitfld.long 0x0C 30. " [62] ,Bitwise channel busy bit 62" "Idle,Busy" bitfld.long 0x0C 29. " [61] ,Bitwise channel busy bit 61" "Idle,Busy" bitfld.long 0x0C 28. " [60] ,Bitwise channel busy bit 60" "Idle,Busy" newline bitfld.long 0x0C 27. " [59] ,Bitwise channel busy bit 59" "Idle,Busy" bitfld.long 0x0C 26. " [58] ,Bitwise channel busy bit 58" "Idle,Busy" bitfld.long 0x0C 25. " [57] ,Bitwise channel busy bit 57" "Idle,Busy" bitfld.long 0x0C 24. " [56] ,Bitwise channel busy bit 56" "Idle,Busy" newline bitfld.long 0x0C 23. " [55] ,Bitwise channel busy bit 55" "Idle,Busy" bitfld.long 0x0C 22. " [54] ,Bitwise channel busy bit 54" "Idle,Busy" bitfld.long 0x0C 21. " [53] ,Bitwise channel busy bit 53" "Idle,Busy" bitfld.long 0x0C 20. " [52] ,Bitwise channel busy bit 52" "Idle,Busy" newline bitfld.long 0x0C 19. " [51] ,Bitwise channel busy bit 51" "Idle,Busy" bitfld.long 0x0C 18. " [50] ,Bitwise channel busy bit 50" "Idle,Busy" bitfld.long 0x0C 17. " [49] ,Bitwise channel busy bit 49" "Idle,Busy" bitfld.long 0x0C 16. " [48] ,Bitwise channel busy bit 48" "Idle,Busy" newline bitfld.long 0x0C 15. " [47] ,Bitwise channel busy bit 47" "Idle,Busy" bitfld.long 0x0C 14. " [46] ,Bitwise channel busy bit 46" "Idle,Busy" bitfld.long 0x0C 13. " [45] ,Bitwise channel busy bit 45" "Idle,Busy" bitfld.long 0x0C 12. " [44] ,Bitwise channel busy bit 44" "Idle,Busy" newline bitfld.long 0x0C 11. " [43] ,Bitwise channel busy bit 43" "Idle,Busy" bitfld.long 0x0C 10. " [42] ,Bitwise channel busy bit 42" "Idle,Busy" bitfld.long 0x0C 9. " [41] ,Bitwise channel busy bit 41" "Idle,Busy" bitfld.long 0x0C 8. " [40] ,Bitwise channel busy bit 40" "Idle,Busy" newline bitfld.long 0x0C 7. " [39] ,Bitwise channel busy bit 39" "Idle,Busy" bitfld.long 0x0C 6. " [38] ,Bitwise channel busy bit 38" "Idle,Busy" bitfld.long 0x0C 5. " [37] ,Bitwise channel busy bit 37" "Idle,Busy" bitfld.long 0x0C 4. " [36] ,Bitwise channel busy bit 36" "Idle,Busy" newline bitfld.long 0x0C 3. " [35] ,Bitwise channel busy bit 35" "Idle,Busy" bitfld.long 0x0C 2. " [34] ,Bitwise channel busy bit 34" "Idle,Busy" bitfld.long 0x0C 1. " [33] ,Bitwise channel busy bit 33" "Idle,Busy" bitfld.long 0x0C 0. " [32] ,Bitwise channel busy bit 32" "Idle,Busy" group.long 0xC0++0x1F line.long 0x00 "MDAT0,MIF data 0 Register" line.long 0x04 "MDAT1,MIF Data 1 Register" line.long 0x08 "MDAT2,MIF Data 2 Register" line.long 0x0C "MDAT3,MIF Data 3 Register" line.long 0x10 "MDWE0,MIF Data Write Enable 0 Register" bitfld.long 0x10 31. " MASK[31] ,Bitwise write enable for CTR data bit 31" "Disabled,Enabled" bitfld.long 0x10 30. " [30] ,Bitwise write enable for CTR data bit 30" "Disabled,Enabled" bitfld.long 0x10 29. " [29] ,Bitwise write enable for CTR data bit 29" "Disabled,Enabled" bitfld.long 0x10 28. " [28] ,Bitwise write enable for CTR data bit 28" "Disabled,Enabled" newline bitfld.long 0x10 27. " [27] ,Bitwise write enable for CTR data bit 27" "Disabled,Enabled" bitfld.long 0x10 26. " [26] ,Bitwise write enable for CTR data bit 26" "Disabled,Enabled" bitfld.long 0x10 25. " [25] ,Bitwise write enable for CTR data bit 25" "Disabled,Enabled" bitfld.long 0x10 24. " [24] ,Bitwise write enable for CTR data bit 24" "Disabled,Enabled" newline bitfld.long 0x10 23. " [23] ,Bitwise write enable for CTR data bit 23" "Disabled,Enabled" bitfld.long 0x10 22. " [22] ,Bitwise write enable for CTR data bit 22" "Disabled,Enabled" bitfld.long 0x10 21. " [21] ,Bitwise write enable for CTR data bit 21" "Disabled,Enabled" bitfld.long 0x10 20. " [20] ,Bitwise write enable for CTR data bit 20" "Disabled,Enabled" newline bitfld.long 0x10 19. " [19] ,Bitwise write enable for CTR data bit 19" "Disabled,Enabled" bitfld.long 0x10 18. " [18] ,Bitwise write enable for CTR data bit 18" "Disabled,Enabled" bitfld.long 0x10 17. " [17] ,Bitwise write enable for CTR data bit 17" "Disabled,Enabled" bitfld.long 0x10 16. " [16] ,Bitwise write enable for CTR data bit 16" "Disabled,Enabled" newline bitfld.long 0x10 15. " [15] ,Bitwise write enable for CTR data bit 15" "Disabled,Enabled" bitfld.long 0x10 14. " [14] ,Bitwise write enable for CTR data bit 14" "Disabled,Enabled" bitfld.long 0x10 13. " [13] ,Bitwise write enable for CTR data bit 13" "Disabled,Enabled" bitfld.long 0x10 12. " [12] ,Bitwise write enable for CTR data bit 12" "Disabled,Enabled" newline bitfld.long 0x10 11. " [11] ,Bitwise write enable for CTR data bit 11" "Disabled,Enabled" bitfld.long 0x10 10. " [10] ,Bitwise write enable for CTR data bit 10" "Disabled,Enabled" bitfld.long 0x10 9. " [9] ,Bitwise write enable for CTR data bit 9" "Disabled,Enabled" bitfld.long 0x10 8. " [8] ,Bitwise write enable for CTR data bit 8" "Disabled,Enabled" newline bitfld.long 0x10 7. " [7] ,Bitwise write enable for CTR data bit 7" "Disabled,Enabled" bitfld.long 0x10 6. " [6] ,Bitwise write enable for CTR data bit 6" "Disabled,Enabled" bitfld.long 0x10 5. " [5] ,Bitwise write enable for CTR data bit 5" "Disabled,Enabled" bitfld.long 0x10 4. " [4] ,Bitwise write enable for CTR data bit 4" "Disabled,Enabled" newline bitfld.long 0x10 3. " [3] ,Bitwise write enable for CTR data bit 3" "Disabled,Enabled" bitfld.long 0x10 2. " [2] ,Bitwise write enable for CTR data bit 2" "Disabled,Enabled" bitfld.long 0x10 1. " [1] ,Bitwise write enable for CTR data bit 1" "Disabled,Enabled" bitfld.long 0x10 0. " [0] ,Bitwise write enable for CTR data bit 0" "Disabled,Enabled" line.long 0x14 "MDWE1,MIF Data Write Enable 1 Register" bitfld.long 0x14 31. " MASK[63] ,Bitwise write enable for CTR data bit 63" "Disabled,Enabled" bitfld.long 0x14 30. " [62] ,Bitwise write enable for CTR data bit 62" "Disabled,Enabled" bitfld.long 0x14 29. " [61] ,Bitwise write enable for CTR data bit 61" "Disabled,Enabled" bitfld.long 0x14 28. " [60] ,Bitwise write enable for CTR data bit 60" "Disabled,Enabled" newline bitfld.long 0x14 27. " [59] ,Bitwise write enable for CTR data bit 59" "Disabled,Enabled" bitfld.long 0x14 26. " [58] ,Bitwise write enable for CTR data bit 58" "Disabled,Enabled" bitfld.long 0x14 25. " [57] ,Bitwise write enable for CTR data bit 57" "Disabled,Enabled" bitfld.long 0x14 24. " [56] ,Bitwise write enable for CTR data bit 56" "Disabled,Enabled" newline bitfld.long 0x14 23. " [55] ,Bitwise write enable for CTR data bit 55" "Disabled,Enabled" bitfld.long 0x14 22. " [54] ,Bitwise write enable for CTR data bit 54" "Disabled,Enabled" bitfld.long 0x14 21. " [53] ,Bitwise write enable for CTR data bit 53" "Disabled,Enabled" bitfld.long 0x14 20. " [52] ,Bitwise write enable for CTR data bit 52" "Disabled,Enabled" newline bitfld.long 0x14 19. " [51] ,Bitwise write enable for CTR data bit 51" "Disabled,Enabled" bitfld.long 0x14 18. " [50] ,Bitwise write enable for CTR data bit 50" "Disabled,Enabled" bitfld.long 0x14 17. " [49] ,Bitwise write enable for CTR data bit 49" "Disabled,Enabled" bitfld.long 0x14 16. " [48] ,Bitwise write enable for CTR data bit 48" "Disabled,Enabled" newline bitfld.long 0x14 15. " [47] ,Bitwise write enable for CTR data bit 47" "Disabled,Enabled" bitfld.long 0x14 14. " [46] ,Bitwise write enable for CTR data bit 46" "Disabled,Enabled" bitfld.long 0x14 13. " [45] ,Bitwise write enable for CTR data bit 45" "Disabled,Enabled" bitfld.long 0x14 12. " [44] ,Bitwise write enable for CTR data bit 44" "Disabled,Enabled" newline bitfld.long 0x14 11. " [43] ,Bitwise write enable for CTR data bit 43" "Disabled,Enabled" bitfld.long 0x14 10. " [42] ,Bitwise write enable for CTR data bit 42" "Disabled,Enabled" bitfld.long 0x14 9. " [41] ,Bitwise write enable for CTR data bit 41" "Disabled,Enabled" bitfld.long 0x14 8. " [40] ,Bitwise write enable for CTR data bit 40" "Disabled,Enabled" newline bitfld.long 0x14 7. " [39] ,Bitwise write enable for CTR data bit 39" "Disabled,Enabled" bitfld.long 0x14 6. " [38] ,Bitwise write enable for CTR data bit 38" "Disabled,Enabled" bitfld.long 0x14 5. " [37] ,Bitwise write enable for CTR data bit 37" "Disabled,Enabled" bitfld.long 0x14 4. " [36] ,Bitwise write enable for CTR data bit 36" "Disabled,Enabled" newline bitfld.long 0x14 3. " [35] ,Bitwise write enable for CTR data bit 35" "Disabled,Enabled" bitfld.long 0x14 2. " [34] ,Bitwise write enable for CTR data bit 34" "Disabled,Enabled" bitfld.long 0x14 1. " [33] ,Bitwise write enable for CTR data bit 33" "Disabled,Enabled" bitfld.long 0x14 0. " [32] ,Bitwise write enable for CTR data bit 32" "Disabled,Enabled" line.long 0x18 "MDWE2,MIF Data Write Enable 2 Register" bitfld.long 0x18 31. " MASK[95] ,Bitwise write enable for CTR data bit 95" "Disabled,Enabled" bitfld.long 0x18 30. " [94] ,Bitwise write enable for CTR data bit 94" "Disabled,Enabled" bitfld.long 0x18 29. " [93] ,Bitwise write enable for CTR data bit 93" "Disabled,Enabled" bitfld.long 0x18 28. " [92] ,Bitwise write enable for CTR data bit 92" "Disabled,Enabled" newline bitfld.long 0x18 27. " [91] ,Bitwise write enable for CTR data bit 91" "Disabled,Enabled" bitfld.long 0x18 26. " [90] ,Bitwise write enable for CTR data bit 90" "Disabled,Enabled" bitfld.long 0x18 25. " [89] ,Bitwise write enable for CTR data bit 89" "Disabled,Enabled" bitfld.long 0x18 24. " [88] ,Bitwise write enable for CTR data bit 88" "Disabled,Enabled" newline bitfld.long 0x18 23. " [87] ,Bitwise write enable for CTR data bit 87" "Disabled,Enabled" bitfld.long 0x18 22. " [86] ,Bitwise write enable for CTR data bit 86" "Disabled,Enabled" bitfld.long 0x18 21. " [85] ,Bitwise write enable for CTR data bit 85" "Disabled,Enabled" bitfld.long 0x18 20. " [84] ,Bitwise write enable for CTR data bit 84" "Disabled,Enabled" newline bitfld.long 0x18 19. " [83] ,Bitwise write enable for CTR data bit 83" "Disabled,Enabled" bitfld.long 0x18 18. " [82] ,Bitwise write enable for CTR data bit 82" "Disabled,Enabled" bitfld.long 0x18 17. " [81] ,Bitwise write enable for CTR data bit 81" "Disabled,Enabled" bitfld.long 0x18 16. " [80] ,Bitwise write enable for CTR data bit 80" "Disabled,Enabled" newline bitfld.long 0x18 15. " [79] ,Bitwise write enable for CTR data bit 79" "Disabled,Enabled" bitfld.long 0x18 14. " [78] ,Bitwise write enable for CTR data bit 78" "Disabled,Enabled" bitfld.long 0x18 13. " [77] ,Bitwise write enable for CTR data bit 77" "Disabled,Enabled" bitfld.long 0x18 12. " [76] ,Bitwise write enable for CTR data bit 76" "Disabled,Enabled" newline bitfld.long 0x18 11. " [75] ,Bitwise write enable for CTR data bit 75" "Disabled,Enabled" bitfld.long 0x18 10. " [74] ,Bitwise write enable for CTR data bit 74" "Disabled,Enabled" bitfld.long 0x18 9. " [73] ,Bitwise write enable for CTR data bit 73" "Disabled,Enabled" bitfld.long 0x18 8. " [72] ,Bitwise write enable for CTR data bit 72" "Disabled,Enabled" newline bitfld.long 0x18 7. " [71] ,Bitwise write enable for CTR data bit 71" "Disabled,Enabled" bitfld.long 0x18 6. " [70] ,Bitwise write enable for CTR data bit 70" "Disabled,Enabled" bitfld.long 0x18 5. " [69] ,Bitwise write enable for CTR data bit 69" "Disabled,Enabled" bitfld.long 0x18 4. " [68] ,Bitwise write enable for CTR data bit 68" "Disabled,Enabled" newline bitfld.long 0x18 3. " [67] ,Bitwise write enable for CTR data bit 67" "Disabled,Enabled" bitfld.long 0x18 2. " [66] ,Bitwise write enable for CTR data bit 66" "Disabled,Enabled" bitfld.long 0x18 1. " [65] ,Bitwise write enable for CTR data bit 65" "Disabled,Enabled" bitfld.long 0x18 0. " [64] ,Bitwise write enable for CTR data bit 64" "Disabled,Enabled" line.long 0x1C "MDWE3,MIF Data Write Enable 3 Register" bitfld.long 0x1C 31. " MASK[127] ,Bitwise write enable for CTR data bit 127" "Disabled,Enabled" bitfld.long 0x1C 30. " [126] ,Bitwise write enable for CTR data bit 126" "Disabled,Enabled" bitfld.long 0x1C 29. " [125] ,Bitwise write enable for CTR data bit 125" "Disabled,Enabled" bitfld.long 0x1C 28. " [124] ,Bitwise write enable for CTR data bit 124" "Disabled,Enabled" newline bitfld.long 0x1C 27. " [123] ,Bitwise write enable for CTR data bit 123" "Disabled,Enabled" bitfld.long 0x1C 26. " [122] ,Bitwise write enable for CTR data bit 122" "Disabled,Enabled" bitfld.long 0x1C 25. " [121] ,Bitwise write enable for CTR data bit 121" "Disabled,Enabled" bitfld.long 0x1C 24. " [120] ,Bitwise write enable for CTR data bit 120" "Disabled,Enabled" newline bitfld.long 0x1C 23. " [119] ,Bitwise write enable for CTR data bit 119" "Disabled,Enabled" bitfld.long 0x1C 22. " [118] ,Bitwise write enable for CTR data bit 118" "Disabled,Enabled" bitfld.long 0x1C 21. " [117] ,Bitwise write enable for CTR data bit 117" "Disabled,Enabled" bitfld.long 0x1C 20. " [116] ,Bitwise write enable for CTR data bit 116" "Disabled,Enabled" newline bitfld.long 0x1C 19. " [115] ,Bitwise write enable for CTR data bit 115" "Disabled,Enabled" bitfld.long 0x1C 18. " [114] ,Bitwise write enable for CTR data bit 114" "Disabled,Enabled" bitfld.long 0x1C 17. " [113] ,Bitwise write enable for CTR data bit 113" "Disabled,Enabled" bitfld.long 0x1C 16. " [112] ,Bitwise write enable for CTR data bit 112" "Disabled,Enabled" newline bitfld.long 0x1C 15. " [111] ,Bitwise write enable for CTR data bit 111" "Disabled,Enabled" bitfld.long 0x1C 14. " [110] ,Bitwise write enable for CTR data bit 110" "Disabled,Enabled" bitfld.long 0x1C 13. " [109] ,Bitwise write enable for CTR data bit 109" "Disabled,Enabled" bitfld.long 0x1C 12. " [108] ,Bitwise write enable for CTR data bit 108" "Disabled,Enabled" newline bitfld.long 0x1C 11. " [107] ,Bitwise write enable for CTR data bit 107" "Disabled,Enabled" bitfld.long 0x1C 10. " [106] ,Bitwise write enable for CTR data bit 106" "Disabled,Enabled" bitfld.long 0x1C 9. " [105] ,Bitwise write enable for CTR data bit 105" "Disabled,Enabled" bitfld.long 0x1C 8. " [104] ,Bitwise write enable for CTR data bit 104" "Disabled,Enabled" newline bitfld.long 0x1C 7. " [103] ,Bitwise write enable for CTR data bit 103" "Disabled,Enabled" bitfld.long 0x1C 6. " [102] ,Bitwise write enable for CTR data bit 102" "Disabled,Enabled" bitfld.long 0x1C 5. " [101] ,Bitwise write enable for CTR data bit 101" "Disabled,Enabled" bitfld.long 0x1C 4. " [100] ,Bitwise write enable for CTR data bit 100" "Disabled,Enabled" newline bitfld.long 0x1C 3. " [99] ,Bitwise write enable for CTR data bit 99" "Disabled,Enabled" bitfld.long 0x1C 2. " [98] ,Bitwise write enable for CTR data bit 98" "Disabled,Enabled" bitfld.long 0x1C 1. " [97] ,Bitwise write enable for CTR data bit 97" "Disabled,Enabled" bitfld.long 0x1C 0. " [96] ,Bitwise write enable for CTR data bit 96" "Disabled,Enabled" rgroup.long 0xE0++0x03 line.long 0x00 "MCTL,MIF Control Register" bitfld.long 0x00 0. " XCMP ,Transfer complete" "No,Yes" group.long 0xE4++0x03 line.long 0x00 "MADR,MIF Address Register" bitfld.long 0x00 31. " WNR ,Write-not-read selection" "Read,Write" bitfld.long 0x00 30. " TB ,Target location bit" "CTR,DBR" hexmask.long.byte 0x00 8.--13. 0x01 " ADDR_13_8 ,DBR address of 8-bit entry - bits[13:8]" hexmask.long.byte 0x00 0.--7. 0x01 " ADDR_7_0 ,DBR address of 8-bit entry - bits[7:0] OR CTR address of 128-bit entry" group.long 0x3C0++0x03 line.long 0x00 "ACTL,AHB Control Register" bitfld.long 0x00 4. " MPB ,DMA Packet buffering mode" "Single,Multiple" bitfld.long 0x00 2. " DMA_MODE ,DMA mode" "0,1" bitfld.long 0x00 1. " SMX ,AHB interrupt mux enable" "Disabled,Enabled" bitfld.long 0x00 0. " SCE ,Software clear enable" "Hardware,Software" rgroup.long 0x3D0++0x07 line.long 0x00 "ACSR0,AHB Channel Status 0 Register" bitfld.long 0x00 31. " CHS[31] ,Interrupt for logical channel 31 status" "No interrupt,Interrupt" bitfld.long 0x00 30. " [30] ,Interrupt for logical channel 30 status" "No interrupt,Interrupt" bitfld.long 0x00 29. " [29] ,Interrupt for logical channel 29 status" "No interrupt,Interrupt" bitfld.long 0x00 28. " [28] ,Interrupt for logical channel 28 status" "No interrupt,Interrupt" newline bitfld.long 0x00 27. " [27] ,Interrupt for logical channel 27 status" "No interrupt,Interrupt" bitfld.long 0x00 26. " [26] ,Interrupt for logical channel 26 status" "No interrupt,Interrupt" bitfld.long 0x00 25. " [25] ,Interrupt for logical channel 25 status" "No interrupt,Interrupt" bitfld.long 0x00 24. " [24] ,Interrupt for logical channel 24 status" "No interrupt,Interrupt" newline bitfld.long 0x00 23. " [23] ,Interrupt for logical channel 23 status" "No interrupt,Interrupt" bitfld.long 0x00 22. " [22] ,Interrupt for logical channel 22 status" "No interrupt,Interrupt" bitfld.long 0x00 21. " [21] ,Interrupt for logical channel 21 status" "No interrupt,Interrupt" bitfld.long 0x00 20. " [20] ,Interrupt for logical channel 20 status" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " [19] ,Interrupt for logical channel 19 status" "No interrupt,Interrupt" bitfld.long 0x00 18. " [18] ,Interrupt for logical channel 18 status" "No interrupt,Interrupt" bitfld.long 0x00 17. " [17] ,Interrupt for logical channel 17 status" "No interrupt,Interrupt" bitfld.long 0x00 16. " [16] ,Interrupt for logical channel 16 status" "No interrupt,Interrupt" newline bitfld.long 0x00 15. " [15] ,Interrupt for logical channel 15 status" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,Interrupt for logical channel 14 status" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Interrupt for logical channel 13 status" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Interrupt for logical channel 12 status" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [11] ,Interrupt for logical channel 11 status" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Interrupt for logical channel 10 status" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,Interrupt for logical channel 9 status" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,Interrupt for logical channel 8 status" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " [7] ,Interrupt for logical channel 7 status" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Interrupt for logical channel 6 status" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,Interrupt for logical channel 5 status" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Interrupt for logical channel 4 status" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " [3] ,Interrupt for logical channel 3 status" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,Interrupt for logical channel 2 status" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Interrupt for logical channel 1 status" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Interrupt for logical channel 0 status" "No interrupt,Interrupt" line.long 0x04 "ACSR1,AHB Channel Status 1 Register" bitfld.long 0x04 31. " CHS[63] ,Interrupt for logical channel 63 status" "No interrupt,Interrupt" bitfld.long 0x04 30. " [62] ,Interrupt for logical channel 62 status" "No interrupt,Interrupt" bitfld.long 0x04 29. " [61] ,Interrupt for logical channel 61 status" "No interrupt,Interrupt" bitfld.long 0x04 28. " [60] ,Interrupt for logical channel 60 status" "No interrupt,Interrupt" newline bitfld.long 0x04 27. " [59] ,Interrupt for logical channel 59 status" "No interrupt,Interrupt" bitfld.long 0x04 26. " [58] ,Interrupt for logical channel 58 status" "No interrupt,Interrupt" bitfld.long 0x04 25. " [57] ,Interrupt for logical channel 57 status" "No interrupt,Interrupt" bitfld.long 0x04 24. " [56] ,Interrupt for logical channel 56 status" "No interrupt,Interrupt" newline bitfld.long 0x04 23. " [55] ,Interrupt for logical channel 55 status" "No interrupt,Interrupt" bitfld.long 0x04 22. " [54] ,Interrupt for logical channel 54 status" "No interrupt,Interrupt" bitfld.long 0x04 21. " [53] ,Interrupt for logical channel 53 status" "No interrupt,Interrupt" bitfld.long 0x04 20. " [52] ,Interrupt for logical channel 52 status" "No interrupt,Interrupt" newline bitfld.long 0x04 19. " [51] ,Interrupt for logical channel 51 status" "No interrupt,Interrupt" bitfld.long 0x04 18. " [50] ,Interrupt for logical channel 50 status" "No interrupt,Interrupt" bitfld.long 0x04 17. " [49] ,Interrupt for logical channel 49 status" "No interrupt,Interrupt" bitfld.long 0x04 16. " [48] ,Interrupt for logical channel 48 status" "No interrupt,Interrupt" newline bitfld.long 0x04 15. " [47] ,Interrupt for logical channel 47 status" "No interrupt,Interrupt" bitfld.long 0x04 14. " [46] ,Interrupt for logical channel 46 status" "No interrupt,Interrupt" bitfld.long 0x04 13. " [45] ,Interrupt for logical channel 45 status" "No interrupt,Interrupt" bitfld.long 0x04 12. " [44] ,Interrupt for logical channel 44 status" "No interrupt,Interrupt" newline bitfld.long 0x04 11. " [43] ,Interrupt for logical channel 43 status" "No interrupt,Interrupt" bitfld.long 0x04 10. " [42] ,Interrupt for logical channel 42 status" "No interrupt,Interrupt" bitfld.long 0x04 9. " [41] ,Interrupt for logical channel 41 status" "No interrupt,Interrupt" bitfld.long 0x04 8. " [40] ,Interrupt for logical channel 40 status" "No interrupt,Interrupt" newline bitfld.long 0x04 7. " [39] ,Interrupt for logical channel 39 status" "No interrupt,Interrupt" bitfld.long 0x04 6. " [38] ,Interrupt for logical channel 38 status" "No interrupt,Interrupt" bitfld.long 0x04 5. " [37] ,Interrupt for logical channel 37 status" "No interrupt,Interrupt" bitfld.long 0x04 4. " [36] ,Interrupt for logical channel 36 status" "No interrupt,Interrupt" newline bitfld.long 0x04 3. " [35] ,Interrupt for logical channel 35 status" "No interrupt,Interrupt" bitfld.long 0x04 2. " [34] ,Interrupt for logical channel 34 status" "No interrupt,Interrupt" bitfld.long 0x04 1. " [33] ,Interrupt for logical channel 33 status" "No interrupt,Interrupt" bitfld.long 0x04 0. " [32] ,Interrupt for logical channel 32 status" "No interrupt,Interrupt" group.long 0x3D8++0x07 line.long 0x00 "ACMR0,AHB Channel Mask 0 Register" bitfld.long 0x00 31. " CHM[31] ,Bitwise channel 31 mask bit" "Masked,Unmasked" bitfld.long 0x00 30. " [30] ,Bitwise channel 30 mask bit" "Masked,Unmasked" bitfld.long 0x00 29. " [29] ,Bitwise channel 29 mask bit" "Masked,Unmasked" bitfld.long 0x00 28. " [28] ,Bitwise channel 28 mask bit" "Masked,Unmasked" newline bitfld.long 0x00 27. " [27] ,Bitwise channel 27 mask bit" "Masked,Unmasked" bitfld.long 0x00 26. " [26] ,Bitwise channel 26 mask bit" "Masked,Unmasked" bitfld.long 0x00 25. " [25] ,Bitwise channel 25 mask bit" "Masked,Unmasked" bitfld.long 0x00 24. " [24] ,Bitwise channel 24 mask bit" "Masked,Unmasked" newline bitfld.long 0x00 23. " [23] ,Bitwise channel 23 mask bit" "Masked,Unmasked" bitfld.long 0x00 22. " [22] ,Bitwise channel 22 mask bit" "Masked,Unmasked" bitfld.long 0x00 21. " [21] ,Bitwise channel 21 mask bit" "Masked,Unmasked" bitfld.long 0x00 20. " [20] ,Bitwise channel 20 mask bit" "Masked,Unmasked" newline bitfld.long 0x00 19. " [19] ,Bitwise channel 19 mask bit" "Masked,Unmasked" bitfld.long 0x00 18. " [18] ,Bitwise channel 18 mask bit" "Masked,Unmasked" bitfld.long 0x00 17. " [17] ,Bitwise channel 17 mask bit" "Masked,Unmasked" bitfld.long 0x00 16. " [16] ,Bitwise channel 16 mask bit" "Masked,Unmasked" newline bitfld.long 0x00 15. " [15] ,Bitwise channel 15 mask bit" "Masked,Unmasked" bitfld.long 0x00 14. " [14] ,Bitwise channel 14 mask bit" "Masked,Unmasked" bitfld.long 0x00 13. " [13] ,Bitwise channel 13 mask bit" "Masked,Unmasked" bitfld.long 0x00 12. " [12] ,Bitwise channel 12 mask bit" "Masked,Unmasked" newline bitfld.long 0x00 11. " [11] ,Bitwise channel 11 mask bit" "Masked,Unmasked" bitfld.long 0x00 10. " [10] ,Bitwise channel 10 mask bit" "Masked,Unmasked" bitfld.long 0x00 9. " [9] ,Bitwise channel 9 mask bit" "Masked,Unmasked" bitfld.long 0x00 8. " [8] ,Bitwise channel 8 mask bit" "Masked,Unmasked" newline bitfld.long 0x00 7. " [7] ,Bitwise channel 7 mask bit" "Masked,Unmasked" bitfld.long 0x00 6. " [6] ,Bitwise channel 6 mask bit" "Masked,Unmasked" bitfld.long 0x00 5. " [5] ,Bitwise channel 5 mask bit" "Masked,Unmasked" bitfld.long 0x00 4. " [4] ,Bitwise channel 4 mask bit" "Masked,Unmasked" newline bitfld.long 0x00 3. " [3] ,Bitwise channel 3 mask bit" "Masked,Unmasked" bitfld.long 0x00 2. " [2] ,Bitwise channel 2 mask bit" "Masked,Unmasked" bitfld.long 0x00 1. " [1] ,Bitwise channel 1 mask bit" "Masked,Unmasked" bitfld.long 0x00 0. " [0] ,Bitwise channel 0 mask bit" "Masked,Unmasked" line.long 0x04 "ACMR1,AHB Channel Mask 1 Register" bitfld.long 0x04 31. " CHM[63] ,Bitwise channel 63 mask bit" "Masked,Unmasked" bitfld.long 0x04 30. " [62] ,Bitwise channel 62 mask bit" "Masked,Unmasked" bitfld.long 0x04 29. " [61] ,Bitwise channel 61 mask bit" "Masked,Unmasked" bitfld.long 0x04 28. " [60] ,Bitwise channel 60 mask bit" "Masked,Unmasked" newline bitfld.long 0x04 27. " [59] ,Bitwise channel 59 mask bit" "Masked,Unmasked" bitfld.long 0x04 26. " [58] ,Bitwise channel 58 mask bit" "Masked,Unmasked" bitfld.long 0x04 25. " [57] ,Bitwise channel 57 mask bit" "Masked,Unmasked" bitfld.long 0x04 24. " [56] ,Bitwise channel 56 mask bit" "Masked,Unmasked" newline bitfld.long 0x04 23. " [55] ,Bitwise channel 55 mask bit" "Masked,Unmasked" bitfld.long 0x04 22. " [54] ,Bitwise channel 54 mask bit" "Masked,Unmasked" bitfld.long 0x04 21. " [53] ,Bitwise channel 53 mask bit" "Masked,Unmasked" bitfld.long 0x04 20. " [52] ,Bitwise channel 52 mask bit" "Masked,Unmasked" newline bitfld.long 0x04 19. " [51] ,Bitwise channel 51 mask bit" "Masked,Unmasked" bitfld.long 0x04 18. " [50] ,Bitwise channel 50 mask bit" "Masked,Unmasked" bitfld.long 0x04 17. " [49] ,Bitwise channel 49 mask bit" "Masked,Unmasked" bitfld.long 0x04 16. " [48] ,Bitwise channel 48 mask bit" "Masked,Unmasked" newline bitfld.long 0x04 15. " [47] ,Bitwise channel 47 mask bit" "Masked,Unmasked" bitfld.long 0x04 14. " [46] ,Bitwise channel 46 mask bit" "Masked,Unmasked" bitfld.long 0x04 13. " [45] ,Bitwise channel 45 mask bit" "Masked,Unmasked" bitfld.long 0x04 12. " [44] ,Bitwise channel 44 mask bit" "Masked,Unmasked" newline bitfld.long 0x04 11. " [43] ,Bitwise channel 43 mask bit" "Masked,Unmasked" bitfld.long 0x04 10. " [42] ,Bitwise channel 42 mask bit" "Masked,Unmasked" bitfld.long 0x04 9. " [41] ,Bitwise channel 41 mask bit" "Masked,Unmasked" bitfld.long 0x04 8. " [40] ,Bitwise channel 40 mask bit" "Masked,Unmasked" newline bitfld.long 0x04 7. " [39] ,Bitwise channel 39 mask bit" "Masked,Unmasked" bitfld.long 0x04 6. " [38] ,Bitwise channel 38 mask bit" "Masked,Unmasked" bitfld.long 0x04 5. " [37] ,Bitwise channel 37 mask bit" "Masked,Unmasked" bitfld.long 0x04 4. " [36] ,Bitwise channel 36 mask bit" "Masked,Unmasked" newline bitfld.long 0x04 3. " [35] ,Bitwise channel 35 mask bit" "Masked,Unmasked" bitfld.long 0x04 2. " [34] ,Bitwise channel 34 mask bit" "Masked,Unmasked" bitfld.long 0x04 1. " [33] ,Bitwise channel 33 mask bit" "Masked,Unmasked" bitfld.long 0x04 0. " [32] ,Bitwise channel 32 mask bit" "Masked,Unmasked" width 0x0B tree.end tree.open "eDMA (Enhanced Direct Memory Access)" tree "MP (Management Page)" base ad:0x5B070000 width 12. group.long 0x00++0x03 line.long 0x00 "CSR,Management Page Control Register" rbitfld.long 0x00 31. " ACTIVE ,DMA active status" "Idle,Executing" rbitfld.long 0x00 24.--28. " ACTIVE_ID ,Active channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 9. " CX ,Cancel transfer" "Not canceled,Canceled" bitfld.long 0x00 8. " ECX ,Cancel transfer with error" "Not canceled,Canceled" newline bitfld.long 0x00 7. " GMRC ,Global master ID replication control" "Disabled,Enabled" bitfld.long 0x00 6. " GCLC ,Global channel linking control" "Disabled,Enabled" bitfld.long 0x00 5. " HALT ,Halt DMA operations" "Not halted,Halted" bitfld.long 0x00 4. " HAE ,Halt after error" "Not halted,Halted" newline bitfld.long 0x00 2. " ERCA ,Channel arbitration select" "Fixed priority,Round robin" bitfld.long 0x00 1. " EDBG ,DMA operation in debug mode" "Continue,Stall" rgroup.long 0x04++0x0B line.long 0x00 "ES,Management Page Error Status Register" bitfld.long 0x00 31. " VLD ,Valid" "No error,Error" bitfld.long 0x00 24.--28. " ERRCHN ,Error channel number or canceled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 9. " UCE ,Uncorrectable TCD error during channel execution" "No error,Error" bitfld.long 0x00 8. " ECX ,Transfer canceled" "Not canceled,Canceled" newline bitfld.long 0x00 7. " SAE ,Source address error" "No error,Error" bitfld.long 0x00 6. " SOE ,Source offset error" "No error,Error" bitfld.long 0x00 5. " DAE ,Destination address error" "No error,Error" bitfld.long 0x00 4. " DOE ,Destination offset error" "No error,Error" newline bitfld.long 0x00 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" bitfld.long 0x00 2. " SGE ,Scatter/gather configuration error" "No error,Error" bitfld.long 0x00 1. " SBE ,Source bus error" "No error,Error" bitfld.long 0x00 0. " DBE ,Destination bus error" "No error,Error" line.long 0x04 "INT,Management Page Interrupt Request Status Register" bitfld.long 0x04 31. " INT[31] ,Interrupt request status for channel 31" "Not requested,Requested" bitfld.long 0x04 30. " [30] ,Interrupt request status for channel 30" "Not requested,Requested" bitfld.long 0x04 29. " [29] ,Interrupt request status for channel 29" "Not requested,Requested" bitfld.long 0x04 28. " [28] ,Interrupt request status for channel 28" "Not requested,Requested" newline bitfld.long 0x04 27. " [27] ,Interrupt request status for channel 27" "Not requested,Requested" bitfld.long 0x04 26. " [26] ,Interrupt request status for channel 26" "Not requested,Requested" bitfld.long 0x04 25. " [25] ,Interrupt request status for channel 25" "Not requested,Requested" bitfld.long 0x04 24. " [24] ,Interrupt request status for channel 24" "Not requested,Requested" newline bitfld.long 0x04 23. " [23] ,Interrupt request status for channel 23" "Not requested,Requested" bitfld.long 0x04 22. " [22] ,Interrupt request status for channel 22" "Not requested,Requested" bitfld.long 0x04 21. " [21] ,Interrupt request status for channel 21" "Not requested,Requested" bitfld.long 0x04 20. " [20] ,Interrupt request status for channel 20" "Not requested,Requested" newline bitfld.long 0x04 19. " [19] ,Interrupt request status for channel 19" "Not requested,Requested" bitfld.long 0x04 18. " [18] ,Interrupt request status for channel 18" "Not requested,Requested" bitfld.long 0x04 17. " [17] ,Interrupt request status for channel 17" "Not requested,Requested" bitfld.long 0x04 16. " [16] ,Interrupt request status for channel 16" "Not requested,Requested" newline bitfld.long 0x04 15. " [15] ,Interrupt request status for channel 15" "Not requested,Requested" bitfld.long 0x04 14. " [14] ,Interrupt request status for channel 14" "Not requested,Requested" bitfld.long 0x04 13. " [13] ,Interrupt request status for channel 13" "Not requested,Requested" bitfld.long 0x04 12. " [12] ,Interrupt request status for channel 12" "Not requested,Requested" newline bitfld.long 0x04 11. " [11] ,Interrupt request status for channel 11" "Not requested,Requested" bitfld.long 0x04 10. " [10] ,Interrupt request status for channel 10" "Not requested,Requested" bitfld.long 0x04 9. " [9] ,Interrupt request status for channel 9" "Not requested,Requested" bitfld.long 0x04 8. " [8] ,Interrupt request status for channel 8" "Not requested,Requested" newline bitfld.long 0x04 7. " [7] ,Interrupt request status for channel 7" "Not requested,Requested" bitfld.long 0x04 6. " [6] ,Interrupt request status for channel 6" "Not requested,Requested" bitfld.long 0x04 5. " [5] ,Interrupt request status for channel 5" "Not requested,Requested" bitfld.long 0x04 4. " [4] ,Interrupt request status for channel 4" "Not requested,Requested" newline bitfld.long 0x04 3. " [3] ,Interrupt request status for channel 3" "Not requested,Requested" bitfld.long 0x04 2. " [2] ,Interrupt request status for channel 2" "Not requested,Requested" bitfld.long 0x04 1. " [1] ,Interrupt request status for channel 1" "Not requested,Requested" bitfld.long 0x04 0. " [0] ,Interrupt request status for channel 0" "Not requested,Requested" line.long 0x08 "HRS,Management Page Hardware Request Status Register" bitfld.long 0x08 31. " HRS[31] ,Hardware request status for channel 31" "Not requested,Requested" bitfld.long 0x08 30. " [30] ,Hardware request status for channel 30" "Not requested,Requested" bitfld.long 0x08 29. " [29] ,Hardware request status for channel 29" "Not requested,Requested" bitfld.long 0x08 28. " [28] ,Hardware request status for channel 28" "Not requested,Requested" newline bitfld.long 0x08 27. " [27] ,Hardware request status for channel 27" "Not requested,Requested" bitfld.long 0x08 26. " [26] ,Hardware request status for channel 26" "Not requested,Requested" bitfld.long 0x08 25. " [25] ,Hardware request status for channel 25" "Not requested,Requested" bitfld.long 0x08 24. " [24] ,Hardware request status for channel 24" "Not requested,Requested" newline bitfld.long 0x08 23. " [23] ,Hardware request status for channel 23" "Not requested,Requested" bitfld.long 0x08 22. " [22] ,Hardware request status for channel 22" "Not requested,Requested" bitfld.long 0x08 21. " [21] ,Hardware request status for channel 21" "Not requested,Requested" bitfld.long 0x08 20. " [20] ,Hardware request status for channel 20" "Not requested,Requested" newline bitfld.long 0x08 19. " [19] ,Hardware request status for channel 19" "Not requested,Requested" bitfld.long 0x08 18. " [18] ,Hardware request status for channel 18" "Not requested,Requested" bitfld.long 0x08 17. " [17] ,Hardware request status for channel 17" "Not requested,Requested" bitfld.long 0x08 16. " [16] ,Hardware request status for channel 16" "Not requested,Requested" newline bitfld.long 0x08 15. " [15] ,Hardware request status for channel 15" "Not requested,Requested" bitfld.long 0x08 14. " [14] ,Hardware request status for channel 14" "Not requested,Requested" bitfld.long 0x08 13. " [13] ,Hardware request status for channel 13" "Not requested,Requested" bitfld.long 0x08 12. " [12] ,Hardware request status for channel 12" "Not requested,Requested" newline bitfld.long 0x08 11. " [11] ,Hardware request status for channel 11" "Not requested,Requested" bitfld.long 0x08 10. " [10] ,Hardware request status for channel 10" "Not requested,Requested" bitfld.long 0x08 9. " [9] ,Hardware request status for channel 9" "Not requested,Requested" bitfld.long 0x08 8. " [8] ,Hardware request status for channel 8" "Not requested,Requested" newline bitfld.long 0x08 7. " [7] ,Hardware request status for channel 7" "Not requested,Requested" bitfld.long 0x08 6. " [6] ,Hardware request status for channel 6" "Not requested,Requested" bitfld.long 0x08 5. " [5] ,Hardware request status for channel 5" "Not requested,Requested" bitfld.long 0x08 4. " [4] ,Hardware request status for channel 4" "Not requested,Requested" newline bitfld.long 0x08 3. " [3] ,Hardware request status for channel 3" "Not requested,Requested" bitfld.long 0x08 2. " [2] ,Hardware request status for channel 2" "Not requested,Requested" bitfld.long 0x08 1. " [1] ,Hardware request status for channel 1" "Not requested,Requested" bitfld.long 0x08 0. " [0] ,Hardware request status for channel 0" "Not requested,Requested" newline group.long 0x100++0x03 line.long 0x00 "CH0_GRPRI,Channel 0 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x104++0x03 line.long 0x00 "CH1_GRPRI,Channel 1 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x108++0x03 line.long 0x00 "CH2_GRPRI,Channel 2 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x10C++0x03 line.long 0x00 "CH3_GRPRI,Channel 3 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x110++0x03 line.long 0x00 "CH4_GRPRI,Channel 4 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree.open "TCD (Transfer Control Descriptor)" tree "Channel 0" base ad:0x5B080000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5B080000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5B080000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5B080000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 1" base ad:0x5B090000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5B090000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5B090000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5B090000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 2" base ad:0x5B0A0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5B0A0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5B0A0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5B0A0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 3" base ad:0x5B0B0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5B0B0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5B0B0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5B0B0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 4" base ad:0x5B0C0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5B0C0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5B0C0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5B0C0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree.end tree.end tree "ENET (Ethernet MAC)" tree "ENET-AVB1" base ad:0x5B040000 width 9. group.long 0x04++0x07 line.long 0x00 "EIR,Interrupt Event Register" eventfld.long 0x00 30. " BABR ,Babbling receive error" "No error,Error" eventfld.long 0x00 29. " BABT ,Babbling transmit error" "No error,Error" eventfld.long 0x00 28. " GRA ,Graceful stop complete" "Not completed,Completed" newline eventfld.long 0x00 27. " TXF ,Transmit frame interrupt" "No interrupt,Interrupt" eventfld.long 0x00 26. " TXB ,Transmit buffer interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " RXF ,Receive frame interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 24. " RXB ,Receive buffer interrupt" "No interrupt,Interrupt" eventfld.long 0x00 23. " MII ,MII interrupt" "No interrupt,Interrupt" eventfld.long 0x00 22. " EBERR ,Ethernet bus error" "No error,Error" newline eventfld.long 0x00 21. " LC ,Late collision occur" "Not occurred,Occurred" eventfld.long 0x00 20. " RL ,Collision retry limit occur" "Not occurred,Occurred" eventfld.long 0x00 19. " UN ,Transmit FIFO underrun" "No underrun,Underrun" newline eventfld.long 0x00 18. " PLR ,Payload receive error" "No error,Error" eventfld.long 0x00 17. " WAKEUP ,Node wakeup request indication" "Not detected,Detected" eventfld.long 0x00 16. " TS_AVAIL ,Transmit timestamp available" "Not available,Available" newline eventfld.long 0x00 15. " TS_TIMER ,Timestamp timer reached period event" "Not reached,Reached" eventfld.long 0x00 14. " RXFLUSH_2 ,RX DMA ring 2 flush indication" "Not flushed,Flushed" eventfld.long 0x00 13. " RXFLUSH_1 ,RX DMA ring 1 flush indication" "Not flushed,Flushed" newline eventfld.long 0x00 12. " RXFLUSH_0 ,RX DMA ring 0 flush indication" "Not flushed,Flushed" eventfld.long 0x00 10. " PARSERR ,Receive parser error" "No error,Error" eventfld.long 0x00 9. " PARSRF ,Receive frame rejection due to table entry MCONFIG[RF] = 1. match" "Not occurred,Occurred" newline eventfld.long 0x00 7. " TXF2 ,Transmit frame interrupt class 2" "No interrupt,Interrupt" eventfld.long 0x00 6. " TXB2 ,Transmit buffer interrupt class 2" "No interrupt,Interrupt" eventfld.long 0x00 5. " RXF2 ,Receive frame interrupt class 2" "No interrupt,Interrupt" newline eventfld.long 0x00 4. " RXB2 ,Receive buffer interrupt class 2" "No interrupt,Interrupt" eventfld.long 0x00 3. " TXF1 ,Transmit frame interrupt class 1" "No interrupt,Interrupt" eventfld.long 0x00 2. " TXB1 ,Transmit buffer interrupt class 1" "No interrupt,Interrupt" newline eventfld.long 0x00 1. " RXF1 ,Receive frame interrupt class 1" "No interrupt,Interrupt" eventfld.long 0x00 0. " RXB1 ,Receive buffer interrupt class 1" "No interrupt,Interrupt" line.long 0x04 "EIMR,Interrupt Mask Register" bitfld.long 0x04 30. " BABR ,BABR interrupt mask" "0,1" bitfld.long 0x04 29. " BABT ,BABT interrupt mask" "0,1" bitfld.long 0x04 28. " GRA ,GRA interrupt mask" "0,1" newline bitfld.long 0x04 27. " TXF ,TXF interrupt mask" "0,1" bitfld.long 0x04 26. " TXB ,TXB interrupt mask" "0,1" bitfld.long 0x04 25. " RXF ,RXF interrupt mask" "0,1" newline bitfld.long 0x04 24. " RXB ,RXB interrupt mask" "0,1" bitfld.long 0x04 23. " MII ,MII interrupt mask" "0,1" bitfld.long 0x04 22. " EBERR ,EBERR interrupt mask" "0,1" newline bitfld.long 0x04 21. " LC ,LC interrupt mask" "0,1" bitfld.long 0x04 20. " RL ,RL interrupt mask" "0,1" bitfld.long 0x04 19. " UN ,UN interrupt mask" "0,1" newline bitfld.long 0x04 18. " PLR ,PLR interrupt mask" "0,1" bitfld.long 0x04 17. " WAKEUP ,WAKEUP interrupt mask" "0,1" bitfld.long 0x04 16. " TS_AVAIL ,TS_AVAIL interrupt mask" "0,1" newline bitfld.long 0x04 15. " TS_TIMER ,TS_TIMER interrupt mask" "0,1" bitfld.long 0x04 14. " RXFLUSH_2 ,RXFLUSH_2 interrupt mask" "0,1" bitfld.long 0x04 13. " RXFLUSH_1 ,RXFLUSH_1 interrupt mask" "0,1" newline bitfld.long 0x04 12. " RXFLUSH_0 ,RXFLUSH_0 interrupt mask" "0,1" bitfld.long 0x04 10. " PARSERR ,Receive parser error mask" "0,1" bitfld.long 0x04 9. " PARSRF ,Receive frame rejected mask" "0,1" newline bitfld.long 0x04 7. " TXF2 ,TXF2 interrupt mask" "0,1" bitfld.long 0x04 6. " TXB2 ,TXB2 interrupt mask" "0,1" bitfld.long 0x04 5. " RXF2 ,RXF2 interrupt mask" "0,1" newline bitfld.long 0x04 4. " RXB2 ,RXB2 interrupt mask" "0,1" bitfld.long 0x04 3. " TXF1 ,TXF1 interrupt mask" "0,1" bitfld.long 0x04 2. " TXB1 ,TXB1 interrupt mask" "0,1" newline bitfld.long 0x04 1. " RXF1 ,RXF1 interrupt mask" "0,1" bitfld.long 0x04 0. " RXB1 ,RXB1 interrupt mask" "0,1" group.long 0x10++0x07 line.long 0x00 "RDAR,Receive Descriptor Active Register" bitfld.long 0x00 24. " RDAR ,Receive descriptor active" "Not active,Active" line.long 0x04 "TDAR,Transmit Descriptor Active Register" bitfld.long 0x04 24. " TDAR ,Transmit descriptor active" "Not active,Active" group.long 0x24++0x03 line.long 0x00 "ECR,Ethernet Control Register" bitfld.long 0x00 17. " RXC_DLY ,Receive clock delay" "Not delayed,Delayed" bitfld.long 0x00 16. " TXC_DLY ,Transmit clock delay" "Not delayed,Delayed" bitfld.long 0x00 11. " SVLANDBL ,S-VLAN double tag require" "Not required,Required" newline bitfld.long 0x00 10. " VLANUSE2ND ,VLAN use second tag" "Not used,Used" bitfld.long 0x00 9. " SVLANEN ,S-VLAN enable" "Disabled,Enabled" bitfld.long 0x00 8. " DBSWP ,Descriptor byte swapping enable" "Not swapped,Swapped" newline bitfld.long 0x00 6. " DBGEN ,Enter hardware freeze mode while device enters debug mode" "Debug mode only,Freeze mode in debug mode" bitfld.long 0x00 5. " SPEED ,Select between 10/100-Mbit/s and 1000-Mbit/s modes of operation" "10/100-Mbit/s,1000-Mbit/s" bitfld.long 0x00 4. " EN1588 ,Enhanced functionality of the MAC select" "Legacy FEC buffer,Enhanced frame time-stamping" newline bitfld.long 0x00 3. " SLEEP ,Sleep mode enable" "Disabled,Enabled" bitfld.long 0x00 2. " MAGICEN ,Magic packet detection enable" "Disabled,Enabled" bitfld.long 0x00 1. " ETHEREN ,Enable the ethernet MAC" "Disabled,Enabled" newline bitfld.long 0x00 0. " RESET ,Ethernet MAC reset" "Disabled,Enabled" group.long 0x40++0x07 line.long 0x00 "MMFR,MII Management Frame Register" bitfld.long 0x00 30.--31. " ST ,Start of frame delimiter" "Extended MDIO,Standard MDIO,?..." bitfld.long 0x00 28.--29. " OP ,Operation code" "Address write,Write operation,Read inc operation,Read operation" hexmask.long.byte 0x00 23.--27. 0x80 " PA ,PHY address" newline hexmask.long.byte 0x00 18.--22. 0x04 " RA ,Register address" bitfld.long 0x00 16.--17. " TA ,Turn around" ",,Enabled,?..." hexmask.long.word 0x00 0.--15. 1. " DATA ,Management frame data" line.long 0x04 "MSCR,MII Speed Control Register" bitfld.long 0x04 8.--10. " HOLDTIME ,Hold time on MDIO output [internal module clock cycle]" "1,2,3,,,,,8" bitfld.long 0x04 7. " DIS_PRE ,Disable preamble" "No,Yes" bitfld.long 0x04 1.--6. " MII_SPEED ,MII speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x64++0x03 line.long 0x00 "MIBC,MIB Control Register" bitfld.long 0x00 31. " MIB_DIS ,Disable MIB logic" "No,Yes" rbitfld.long 0x00 30. " MIB_IDLE ,MIB block updating/not updating(idle) counters mode" "Updating,Idle" bitfld.long 0x00 29. " MIB_CLEAR ,MIB clear" "No effect,Clear" group.long 0x84++0x03 line.long 0x00 "RCR,Receive Control Register" rbitfld.long 0x00 31. " GRS ,Graceful receive stop" "Not stopped,Stopped" bitfld.long 0x00 30. " NLC ,Enables/disables a payload length check" "Disabled,Enabled" hexmask.long.word 0x00 16.--29. 1. " MAX_FL ,Maximum frame length" newline bitfld.long 0x00 15. " CFEN ,MAC control frame enable" "Disabled,Enabled" bitfld.long 0x00 14. " CRCFWD ,CRC field of received frames were transmitted/stripped" "Transmitted,Stripped" bitfld.long 0x00 13. " PAUFWD ,Terminate/Forward pause frames" "Terminated,Forwarded" newline bitfld.long 0x00 12. " PADEN ,Enable frame padding remove on receive" "Disabled,Enabled" bitfld.long 0x00 9. " RMII_10T ,100-Mbits/10-Mbits mode of the RMII or RGMII" "100-Mbit/s,10-Mbit/s" bitfld.long 0x00 8. " RMII_MODE ,MAC MII/RMII mode enable" "MII,RMII" newline bitfld.long 0x00 6. " RGMII_EN ,RGMII mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " FCE ,Flow control enable" "Disabled,Enabled" bitfld.long 0x00 4. " BC_REJ ,Broadcast frame reject" "Not rejected,Rejected" newline bitfld.long 0x00 3. " PROM ,Promiscuous mode enable" "Disabled,Enabled" bitfld.long 0x00 2. " MII_MODE ,Media independent interface mode" ",MII/RMII" bitfld.long 0x00 1. " DRT ,Disable receive on transmit" "No,Yes" newline bitfld.long 0x00 0. " LOOP ,Internal loopback" "Disabled,Enabled" if (((per.l(ad:0x5B040000+0x24)&0x02)==0x00)) group.long 0xC4++0x03 line.long 0x00 "TCR,Transmit Control Register" bitfld.long 0x00 9. " CRCFWD ,Forward frame from application with CRC" "Without CRC,With CRC" bitfld.long 0x00 8. " ADDINS ,Modify MAC address on transmit" "Not modified,Modified" bitfld.long 0x00 5.--7. " ADDSEL ,Source MAC address select on transmit" "Node MAC on PADDR1/2,?..." newline rbitfld.long 0x00 4. " RFC_PAUSE ,Receive frame control pause" "Not paused,Paused" bitfld.long 0x00 3. " TFC_PAUSE ,Transmit frame control pause" "Not paused,Paused" rbitfld.long 0x00 2. " FDEN ,Full-duplex enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " GTS ,Graceful transmit stop" "Not stopped,Stopped" else group.long 0xC4++0x03 line.long 0x00 "TCR,Transmit Control Register" bitfld.long 0x00 9. " CRCFWD ,Forward frame from application with CRC" "Without CRC,With CRC" bitfld.long 0x00 8. " ADDINS ,Modify MAC address on transmit" "Not modified,Modified" bitfld.long 0x00 5.--7. " ADDSEL ,Source MAC address select on transmit" "Node MAC on PADDR1/2,?..." newline rbitfld.long 0x00 4. " RFC_PAUSE ,Receive frame control pause" "Not paused,Paused" bitfld.long 0x00 3. " TFC_PAUSE ,Transmit frame control pause" "Not paused,Paused" bitfld.long 0x00 2. " FDEN ,Full-duplex enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " GTS ,Graceful transmit stop" "Not stopped,Stopped" endif group.long 0xE4++0x0B line.long 0x00 "PALR,Physical Address Lower Register" line.long 0x04 "PAUR,Physical Address Upper Register" hexmask.long.word 0x04 16.--31. 0x01 " PADDR2 ,Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match and the source address field in PAUSE frames" hexmask.long.word 0x04 0.--15. 1. " TYPE ,Type field in PAUSE frames" line.long 0x08 "OPD,Opcode/Pause Duration Register ENET_OPD" hexmask.long.word 0x08 16.--31. 1. " OPCODE ,Opcode field in PAUSE frames" hexmask.long.word 0x08 0.--15. 1. " PAUSE_DUR ,Pause duration" group.long 0xF0++0x03 line.long 0x00 "TXIC0,Transmit Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x00 30. " ICCS ,Interrupt coalescing timer clock source select" "MII/GMII,ENET" hexmask.long.byte 0x00 20.--27. 1. " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0xF4++0x03 line.long 0x00 "TXIC1,Transmit Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x00 30. " ICCS ,Interrupt coalescing timer clock source select" "MII/GMII,ENET" hexmask.long.byte 0x00 20.--27. 1. " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0xF8++0x03 line.long 0x00 "TXIC2,Transmit Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x00 30. " ICCS ,Interrupt coalescing timer clock source select" "MII/GMII,ENET" hexmask.long.byte 0x00 20.--27. 1. " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0x100++0x03 line.long 0x00 "RXIC0,Receive Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x00 30. " ICCS ,Interrupt coalescing timer clock source select" "MII/GMII,ENET" hexmask.long.byte 0x00 20.--27. 1. " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0x104++0x03 line.long 0x00 "RXIC1,Receive Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x00 30. " ICCS ,Interrupt coalescing timer clock source select" "MII/GMII,ENET" hexmask.long.byte 0x00 20.--27. 1. " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0x108++0x03 line.long 0x00 "RXIC2,Receive Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x00 30. " ICCS ,Interrupt coalescing timer clock source select" "MII/GMII,ENET" hexmask.long.byte 0x00 20.--27. 1. " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0x118++0x0F line.long 0x00 "IAUR,Descriptor Individual Upper Address Register" line.long 0x04 "IALR,Descriptor Individual Lower Address Register" line.long 0x08 "GAUR,Descriptor Group Upper Address Register" line.long 0x0C "GALR,Descriptor Group Lower Address Register" group.long 0x144++0x03 line.long 0x00 "TFWR,Transmit FIFO Watermark Register" bitfld.long 0x00 8. " STRFWD ,Store and forward enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " TFWR ,Transmit FIFO write" "64 bytes,64 bytes,128 bytes,192 bytes,256 bytes,320 bytes,384 bytes,448 bytes,512 bytes,576 bytes,640 bytes,704 bytes,768 bytes,832 bytes,896 bytes,960 bytes,1024 bytes,1088 bytes,1152 bytes,1216 bytes,1280 bytes,1344 bytes,1408 bytes,1472 bytes,1536 bytes,1600 bytes,1664 bytes,1728 bytes,1792 bytes,1856 bytes,1920 bytes,1984 bytes,2048 bytes,2112 bytes,2176 bytes,2240 bytes,2304 bytes,2368 bytes,2432 bytes,2496 bytes,2560 bytes,2624 bytes,2688 bytes,2752 bytes,2816 bytes,2880 bytes,2944 bytes,3008 bytes,3072 bytes,3136 bytes,3200 bytes,3264 bytes,3328 bytes,3392 bytes,3456 bytes,3520 bytes,3584 bytes,3648 bytes,3712 bytes,3776 bytes,3840 bytes,3904 bytes,3968 bytes,4032 bytes" group.long 0x160++0x0B line.long 0x00 "RDSR1,Receive Descriptor Ring 1 Start Register" hexmask.long 0x00 3.--31. 0x08 " R_DES_START ,Pointer to the beginning of the receive buffer descriptor queue 1" line.long 0x04 "TDSR1,Transmit Buffer Descriptor Ring 1 Start Register" hexmask.long 0x04 3.--31. 0x08 " X_DES_START ,Pointer to the beginning of the transmit buffer descriptor queue 1" line.long 0x08 "MRBR1,Maximum Receive Buffer Size Register" hexmask.long.word 0x08 4.--13. 1. " R_BUF_SIZE ,Receive buffer size in bytes" group.long 0x16C++0x0B line.long 0x00 "RDSR2,Receive Descriptor Ring 2 Start Register" hexmask.long 0x00 3.--31. 0x08 " R_DES_START ,Pointer to the beginning of the receive buffer descriptor queue 2" line.long 0x04 "TDSR2,Transmit Buffer Descriptor Ring 2 Start Register" hexmask.long 0x04 3.--31. 0x08 " X_DES_START ,Pointer to the beginning of the transmit buffer descriptor queue 2" line.long 0x08 "MRBR2,Maximum Receive Buffer Size Register" hexmask.long.word 0x08 4.--13. 1. " R_BUF_SIZE ,Receive buffer size in bytes" group.long 0x180++0x0B line.long 0x00 "RDSR,Receive Descriptor Ring 0 Start Register" hexmask.long 0x00 3.--31. 0x08 " R_DES_START ,Pointer to the beginning of the receive buffer descriptor queue $2" line.long 0x04 "TDSR,Transmit Buffer Descriptor Ring 0 Start Register" hexmask.long 0x04 3.--31. 0x08 " X_DES_START ,Pointer to the beginning of the transmit buffer descriptor queue $2" line.long 0x08 "MRBR,Maximum Receive Buffer Size Register" hexmask.long.word 0x08 4.--13. 1. " R_BUF_SIZE ,Receive buffer size in bytes" group.long 0x190++0x23 line.long 0x00 "RSFL,Receive FIFO Section Full Threshold" hexmask.long.word 0x00 0.--9. 1. " RX_SECTION_FULL ,Value of receive FIFO section full threshold" line.long 0x04 "RSEM,Receive FIFO Section Empty Threshold" bitfld.long 0x04 16.--20. " STAT_SECTION_EMPTY ,RX status FIFO section empty threshold" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x04 0.--9. 1. " RX_SECTION_EMPTY ,Value of the receive FIFO section empty threshold" line.long 0x08 "RAEM,Receive FIFO Almost Empty Threshold" hexmask.long.word 0x08 0.--9. 1. " RX_ALMOST_EMPTY ,Value of the receive FIFO almost empty threshold" line.long 0x0C "RAFL,Receive FIFO Almost Full Threshold" hexmask.long.word 0x0C 0.--9. 1. " RX_ALMOST_FULL ,Value of the receive FIFO almost full threshold" line.long 0x10 "TSEM,Transmit FIFO Section Empty Threshold" hexmask.long.word 0x10 0.--9. 1. " TX_SECTION_EMPTY ,Value of the transmit FIFO section empty threshold" line.long 0x14 "TAEM,Transmit FIFO Almost Empty Threshold" hexmask.long.word 0x14 0.--9. 1. " TX_ALMOST_EMPTY ,Value of transmit FIFO almost empty threshold" line.long 0x18 "TAFL,Transmit FIFO Almost Full Threshold" hexmask.long.word 0x18 0.--9. 1. " TX_ALMOST_FULL ,Value of the transmit FIFO almost full threshold" line.long 0x1C "TIPG,Transmit Inter-Packet Gap" bitfld.long 0x1C 0.--4. " IPG ,Transmit inter-packet gap" "12,12,12,12,12,12,12,12,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,12,12,12,12,12" line.long 0x20 "FTRL,Frame Truncation Length" hexmask.long.word 0x20 0.--13. 1. " TRUNC_FL ,Frame truncation length" group.long 0x1C0++0x07 line.long 0x00 "TACC,Transmit Accelerator Function Configuration" bitfld.long 0x00 4. " PROCHK ,Enables insertion of protocol checksum" "Not inserted,Inserted" bitfld.long 0x00 3. " IPCHK ,Enables insertion of IP header checksum" "Not inserted,Inserted" bitfld.long 0x00 0. " SHIFT16 ,TX FIFO shift-16 enable" "Disabled,Enabled" line.long 0x04 "RACC,Receive Accelerator Function Configuration" bitfld.long 0x04 7. " SHIFT16 ,RX FIFO shift-16 enable" "Disabled,Enabled" bitfld.long 0x04 6. " LINEDIS ,Enable discard of frames with MAC layer errors" "Disabled,Enabled" bitfld.long 0x04 2. " PRODIS ,Enable discard of frames with wrong protocol checksum" "Disabled,Enabled" newline bitfld.long 0x04 1. " IPDIS ,Enable discard of frames with wrong IPv4 header checksum" "Disabled,Enabled" bitfld.long 0x04 0. " PADREM ,Enable padding removal for short IP frames" "Disabled,Enabled" group.long 0x1C8++0x03 line.long 0x00 "RCMR0,Receive Classification Match Register For Class 0" bitfld.long 0x00 16. " MATCHEN ,Match enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. " CMP3 ,Compare 3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " CMP2 ,Compare 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4.--6. " CMP1 ,Compare 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " CMP0 ,Compare 0" "0,1,2,3,4,5,6,7" group.long (0x1C8+0x10)++0x03 line.long 0x00 "DMA0CFG,DMA Class Based Configuration 0" bitfld.long 0x00 17. " CALC_NOIPG ,Disable inclusion of IPG bytes for bandwidth calculations" "No,Yes" bitfld.long 0x00 16. " DMA_CLASS_EN ,DMA class enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " IDLE_SLOPE ,Idle slope" group.long 0x1CC++0x03 line.long 0x00 "RCMR1,Receive Classification Match Register For Class 1" bitfld.long 0x00 16. " MATCHEN ,Match enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. " CMP3 ,Compare 3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " CMP2 ,Compare 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4.--6. " CMP1 ,Compare 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " CMP0 ,Compare 0" "0,1,2,3,4,5,6,7" group.long (0x1CC+0x10)++0x03 line.long 0x00 "DMA1CFG,DMA Class Based Configuration 1" bitfld.long 0x00 17. " CALC_NOIPG ,Disable inclusion of IPG bytes for bandwidth calculations" "No,Yes" bitfld.long 0x00 16. " DMA_CLASS_EN ,DMA class enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " IDLE_SLOPE ,Idle slope" group.long 0x1E0++0x07 line.long 0x00 "RDAR0,Receive Descriptor Active Register - Ring 0" bitfld.long 0x00 24. " RDAR ,Receive descriptor active" "Not active,Active" line.long 0x04 "TDAR0,Transmit Descriptor Active Register - Ring 0" bitfld.long 0x04 24. " TDAR ,Transmit descriptor active" "Not active,Active" group.long 0x1E8++0x07 line.long 0x00 "RDAR1,Receive Descriptor Active Register - Ring 1" bitfld.long 0x00 24. " RDAR ,Receive descriptor active" "Not active,Active" line.long 0x04 "TDAR1,Transmit Descriptor Active Register - Ring 1" bitfld.long 0x04 24. " TDAR ,Transmit descriptor active" "Not active,Active" group.long 0x1F0++0x03 line.long 0x00 "QOS,QOS Scheme" bitfld.long 0x00 5. " RX_FLUSH2 ,RX flush for ring 2 enable" "Disabled,Enabled" bitfld.long 0x00 4. " RX_FLUSH1 ,RX flush for ring 1 enable" "Disabled,Enabled" bitfld.long 0x00 3. " RX_FLUSH0 ,RX flush for ring 0 enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--2. " TX_SCHEME ,TX scheme configuration" "Credit-based scheme,Round-robin scheme,?..." newline width 20. rgroup.long 0x204++0x43 line.long 0x00 "RMON_T_PACKETS,Tx Packet Count Statistic Register" hexmask.long.word 0x00 0.--15. 1. " TXPKTS ,Transmit packet count" line.long 0x04 "RMON_T_BC_PKT,Tx Broadcast Packets Statistic Register" hexmask.long.word 0x04 0.--15. 1. " TXPKTS ,Broadcast packets" line.long 0x08 "RMON_T_MC_PKT,Tx Multicast Packets Statistic Register" hexmask.long.word 0x08 0.--15. 1. " TXPKTS ,Multicast packets" line.long 0x0C "RMON_T_CRC_ALIGN,Tx Packets With CRC/Align Error Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " TXPKTS ,Packets with CRC/align error" line.long 0x10 "RMON_T_UNDERSIZE,Tx Packets Less Than Bytes And Good CRC Statistic Register" hexmask.long.word 0x10 0.--15. 1. " TXPKTS ,Number of transmit packets less than 64 bytes with good CRC" line.long 0x14 "RMON_T_OVERSIZE,Tx Packets GT MAX_FL Bytes And Good CRC Statistic Register" hexmask.long.word 0x14 0.--15. 1. " TXPKTS ,Number of transmit packets greater than MAX_FL bytes with good CRC" line.long 0x18 "RMON_T_FRAG,Tx Packets Less Than 64 Bytes And Bad CRC Statistic Register" hexmask.long.word 0x18 0.--15. 1. " TXPKTS ,Number of packets less than 64 bytes with bad CRC" line.long 0x1C "RMON_T_JAB,Tx Packets Greater Than MAX_FL Bytes And Bad CRC Statistic Register" hexmask.long.word 0x1C 0.--15. 1. " TXPKTS ,Number of transmit packets greater than MAX_FL bytes and bad CRC" line.long 0x20 "RMON_T_COL,Tx Collision Count Statistic Register" hexmask.long.word 0x20 0.--15. 1. " TXPKTS ,Number of transmit collisions" line.long 0x24 "RMON_T_P64,Tx 64-Byte Packets Statistic Register" hexmask.long.word 0x24 0.--15. 1. " TXPKTS ,Number of 64-byte transmit packets" line.long 0x28 "RMON_T_P65TO127,Tx 65- To 127-byte Packets Statistic Register" hexmask.long.word 0x28 0.--15. 1. " TXPKTS ,Number of 65- to 127-byte transmit packets" line.long 0x2C "RMON_T_P128TO255,Tx 128- To 255-byte Packets Statistic Register" hexmask.long.word 0x2C 0.--15. 1. " TXPKTS ,Number of 128- to 255-byte transmit packets" line.long 0x30 "RMON_T_P256TO511,Tx 256- To 511-byte Packets Statistic Register" hexmask.long.word 0x30 0.--15. 1. " TXPKTS ,Number of 256- to 511-byte transmit packets" line.long 0x34 "RMON_T_P512TO1023,Tx 512- To 1023-byte Packets Statistic Register" hexmask.long.word 0x34 0.--15. 1. " TXPKTS ,Number of 512- to 1023-byte transmit packets" line.long 0x38 "RMON_T_P1024TO2047,Tx 1024- To 2047-byte Packets Statistic Register" hexmask.long.word 0x38 0.--15. 1. " TXPKTS ,Number of 1024- to 2047-byte transmit packets" line.long 0x3C "RMON_T_P_GTE2048,Tx Packets Greater Than 2048 Bytes Statistic Register" hexmask.long.word 0x3C 0.--15. 1. " TXPKTS ,Number of transmit packets greater than 2048 bytes" line.long 0x40 "RMON_T_OCTETS,Tx Octets Statistic Register" rgroup.long 0x24C++0x1F line.long 0x00 "IEEE_T_FRAME_OK,Frames Transmitted OK Statistic Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Number of frames transmitted OK" line.long 0x04 "IEEE_T_1COL,Frames Transmitted With Single Collision Statistic Register" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Number of frames transmitted with one collision" line.long 0x08 "IEEE_T_MCOL,Frames Transmitted With Multiple Collisions Statistic Register" hexmask.long.word 0x08 0.--15. 1. " COUNT ,Number of frames transmitted with multiple collisions" line.long 0x0C "IEEE_T_DEF,Frames Transmitted After Deferral Delay Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Number of frames transmitted with deferral delay" line.long 0x10 "IEEE_T_LCOL,Frames Transmitted With Late Collision Statistic Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of frames transmitted with late collision" line.long 0x14 "IEEE_T_EXCOL,Frames Transmitted With Excessive Collisions Statistic Register" hexmask.long.word 0x14 0.--15. 1. " COUNT ,Number of frames transmitted with excessive collisions" line.long 0x18 "IEEE_T_MACERR,Frames Transmitted With Tx FIFO Underrun Statistic Register" hexmask.long.word 0x18 0.--15. 1. " COUNT ,Number of frames transmitted with transmit FIFO underrun" line.long 0x1C "IEEE_T_CSERR,Frames Transmitted With Carrier Sense Error Statistic Register" hexmask.long.word 0x1C 0.--15. 1. " COUNT ,Number of frames transmitted with carrier sense error" rgroup.long 0x270++0x07 line.long 0x00 "IEEE_T_FDXFC,Flow Control Pause Frames Transmitted Statistic Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Number of flow-control pause frames transmitted" line.long 0x04 "IEEE_T_OCTETS_OK,Octet Count For Frames Transmitted w/o Error Statistic Register" rgroup.long 0x284++0x1F line.long 0x00 "RMON_R_PACKETS,Rx Packet Count Statistic Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Number of packets received" line.long 0x04 "RMON_R_BC_PKT,Rx Broadcast Packets Statistic Register" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Number of receive broadcast packets" line.long 0x08 "RMON_R_MC_PKT,Rx Multicast Packets Statistic Register" hexmask.long.word 0x08 0.--15. 1. " COUNT ,Number of receive multicast packets" line.long 0x0C "RMON_R_CRC_ALIGN,Rx Packets With CRC/Align Error Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Number of receive packets with CRC or align error" line.long 0x10 "RMON_R_UNDERSIZE,Rx Packets With Less Than 64 Bytes And Good CRC Statistic Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of receive packets with less than 64 bytes and good CRC" line.long 0x14 "RMON_R_OVERSIZE,Rx Packets Greater Than MAX_FL And Good CRC Statistic Register" hexmask.long.word 0x14 0.--15. 1. " COUNT ,Number of receive packets greater than MAX_FL and good CRC" line.long 0x18 "RMON_R_FRAG,Rx Packets Less Than 64 Bytes And Bad CRC Statistic Register" hexmask.long.word 0x18 0.--15. 1. " COUNT ,Number of receive packets with less than 64 bytes and bad CRC" line.long 0x1C "RMON_R_JAB,Rx Packets Greater Than MAX_FL Bytes And Bad CRC Statistic Register" hexmask.long.word 0x1C 0.--15. 1. " COUNT ,Number of receive packets greater than MAX_FL and bad CRC" rgroup.long 0x2A8++0x3B line.long 0x00 "RMON_R_P64,Rx 64-Byte Packets Statistic Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Number of 64-byte receive packets" line.long 0x04 "RMON_R_P65TO127,Rx 65- To 127-Byte Packets Statistic Register" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Number of 65- to 127-byte recieve packets" line.long 0x08 "RMON_R_P128TO255,Rx 128- To 255-Byte Packets Statistic Register" hexmask.long.word 0x08 0.--15. 1. " COUNT ,Number of 128- to 255-byte recieve packets" line.long 0x0C "RMON_R_P256TO511,Rx 256- To 511-Byte Packets Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Number of 256- to 511-byte recieve packets" line.long 0x10 "RMON_R_P512TO1023,Rx 512- To 1023-Byte Packets Statistic Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of 512- to 1023-byte recieve packets" line.long 0x14 "RMON_R_P1024TO2047,Rx 1024- To 2047-Byte Packets Statistic Register" hexmask.long.word 0x14 0.--15. 1. " COUNT ,Number of 1024- to 2047-byte recieve packets" line.long 0x18 "RMON_R_P_GTE2048,Rx Packets Greater Than 2048 Bytes Statistic Register" hexmask.long.word 0x18 0.--15. 1. " COUNT ,Number of greater-than-2048-byte recieve packets" line.long 0x1C "RMON_R_OCTETS,Rx Octets Statistic Register" line.long 0x20 "IEEE_R_DROP,Frames Not Counted Correctly Statistic Register" hexmask.long.word 0x20 0.--15. 1. " COUNT ,Frame count" line.long 0x24 "IEEE_R_FRAME_OK,Frames Received OK Statistic Register" hexmask.long.word 0x24 0.--15. 1. " COUNT ,Number of frames received OK" line.long 0x28 "IEEE_R_CRC,Frames Received With CRC Error Statistic Register" hexmask.long.word 0x28 0.--15. 1. " COUNT ,Number of frames received with CRC error" line.long 0x2C "IEEE_R_ALIGN,Frames Received With Alignment Error Statistic Register" hexmask.long.word 0x2C 0.--15. 1. " COUNT ,Number of frames received with alignment error" line.long 0x30 "IEEE_R_MACERR,Receive FIFO Overflow Count Statistic Register" hexmask.long.word 0x30 0.--15. 1. " COUNT ,Receive FIFO overflow count" line.long 0x34 "IEEE_R_FDXFC,Flow Control Pause Frames Received Statistic Register" hexmask.long.word 0x34 0.--15. 1. " COUNT ,Number of flow-control pause frames received" line.long 0x38 "IEEE_R_OCTETS_OK,Octet Count For Frames Received Without Error Statistic Register" if (((per.long((ad:0x5B040000)+0x400))&0xA00)==0x00) group.long 0x400++0x03 line.long 0x00 "ATCR,Adjustable Timer Control Register" bitfld.long 0x00 13. " SLAVE ,Enable timer slave mode" "Disabled,Enabled" bitfld.long 0x00 11. " CAPTURE ,Capture current time" "No effect,Time captured" bitfld.long 0x00 9. " RESTART ,Reset timer" "No reset,Reset" newline bitfld.long 0x00 7. " PINPER ,Enables event signal output assertion on period event" "Disabled,Enabled" bitfld.long 0x00 4. " PEREN ,Enable periodical event" "Disabled,Enabled" bitfld.long 0x00 3. " OFFRST ,Reset timer on offset event" "No reset,Reset" newline bitfld.long 0x00 2. " OFFEN ,Enable one-shot offset event" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Enable timer" "Disabled,Enabled" else group.long 0x400++0x03 line.long 0x00 "ATCR,Adjustable Timer Control Register" rbitfld.long 0x00 13. " SLAVE ,Enable timer slave mode" "Disabled,Enabled" bitfld.long 0x00 11. " CAPTURE ,Capture current time" "No effect,Time captured" bitfld.long 0x00 9. " RESTART ,Reset timer" "No reset,Reset" newline rbitfld.long 0x00 7. " PINPER ,Enables event signal output assertion on period event" "Disabled,Enabled" rbitfld.long 0x00 4. " PEREN ,Enable periodical event" "Disabled,Enabled" rbitfld.long 0x00 3. " OFFRST ,Reset timer on offset event" "No reset,Reset" newline rbitfld.long 0x00 2. " OFFEN ,Enable one-shot offset event" "Disabled,Enabled" rbitfld.long 0x00 0. " EN ,Enable timer" "Disabled,Enabled" endif group.long 0x404++0x13 line.long 0x00 "ATVR,Timer Value Register" line.long 0x04 "ATOFF,Timer Offset Register" line.long 0x08 "ATPER,Timer Period Register" line.long 0x0C "ATCOR,Timer Correction Register" hexmask.long 0x0C 0.--30. 1. " COR ,Correction counter wrap-around value" line.long 0x10 "ATINC,Time-Stamping Clock Period Register" hexmask.long.byte 0x10 8.--14. 1. " INC_CORR ,Correction increment value" hexmask.long.byte 0x10 0.--6. 1. " INC ,Clock period of the timestamping clock in nanoseconds" rgroup.long 0x418++0x03 line.long 0x00 "ATSTMP,Timestamp Of Last Transmitted Frame" group.long 0x580++0x17 line.long 0x00 "MDATA,Pattern Match Data Register" newline line.long 0x04 "MMASK,Match Entry Mask Register" bitfld.long 0x04 31. " MATCHMASK ,MDATA bit 31 mask" "0,1" bitfld.long 0x04 30. ",MDATA bit 30 mask" "0,1" bitfld.long 0x04 29. ",MDATA bit 29 mask" "0,1" bitfld.long 0x04 28. ",MDATA bit 28 mask" "0,1" bitfld.long 0x04 27. ",MDATA bit 27 mask" "0,1" bitfld.long 0x04 26. ",MDATA bit 26 mask" "0,1" bitfld.long 0x04 25. ",MDATA bit 25 mask" "0,1" bitfld.long 0x04 24. ",MDATA bit 24 mask" "0,1" bitfld.long 0x04 23. ",MDATA bit 23 mask" "0,1" bitfld.long 0x04 22. ",MDATA bit 22 mask" "0,1" bitfld.long 0x04 21. ",MDATA bit 21 mask" "0,1" bitfld.long 0x04 20. ",MDATA bit 20 mask" "0,1" bitfld.long 0x04 19. ",MDATA bit 19 mask" "0,1" bitfld.long 0x04 18. ",MDATA bit 18 mask" "0,1" bitfld.long 0x04 17. ",MDATA bit 17 mask" "0,1" bitfld.long 0x04 16. ",MDATA bit 16 mask" "0,1" bitfld.long 0x04 15. ",MDATA bit 15 mask" "0,1" bitfld.long 0x04 14. ",MDATA bit 14 mask" "0,1" bitfld.long 0x04 13. ",MDATA bit 13 mask" "0,1" bitfld.long 0x04 12. ",MDATA bit 12 mask" "0,1" bitfld.long 0x04 11. ",MDATA bit 11 mask" "0,1" bitfld.long 0x04 10. ",MDATA bit 10 mask" "0,1" bitfld.long 0x04 9. ",MDATA bit 9 mask" "0,1" bitfld.long 0x04 8. ",MDATA bit 8 mask" "0,1" bitfld.long 0x04 7. ",MDATA bit 7 mask" "0,1" bitfld.long 0x04 6. ",MDATA bit 6 mask" "0,1" bitfld.long 0x04 5. ",MDATA bit 5 mask" "0,1" bitfld.long 0x04 4. ",MDATA bit 4 mask" "0,1" bitfld.long 0x04 3. ",MDATA bit 3 mask" "0,1" bitfld.long 0x04 2. ",MDATA bit 2 mask" "0,1" bitfld.long 0x04 1. ",MDATA bit 1 mask" "0,1" bitfld.long 0x04 0. ",MDATA bit 0 mask" "0,1" newline line.long 0x08 "MCONFIG,Match Entry Rules Configuration Register" bitfld.long 0x08 31. " AF ,Accept frame" "Not accepted,Accepted" bitfld.long 0x08 30. " RF ,Reject frame" "Not rejected,Rejected" bitfld.long 0x08 29. " IM ,Invert match" "Not inverted,Inverted" newline hexmask.long.byte 0x08 16.--23. 1. " OK_INDEX ,OK index" bitfld.long 0x08 2.--7. " FRMOFF ,Frame offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "MENTRYRW,Match Entry Read/Write Command Register" bitfld.long 0x0C 9. " RD ,Entry read command" "No read,Read" bitfld.long 0x0C 8. " WR ,Entry write command" "No write,Write" hexmask.long.byte 0x0C 0.--7. 0x01 " ENTRYADD ,Entry address" line.long 0x10 "RXPCTL,Receive Parser Control Register" bitfld.long 0x10 24. " ACPTEERR ,Accept end error" "Not accepted,Accepted" hexmask.long.byte 0x10 16.--23. 1. " ENDERRQ ,End error queue" hexmask.long.byte 0x10 8.--15. 1. " MAXINDEX ,Maximum index" newline bitfld.long 0x10 4. " PRSRSCLR ,Clear parser statistics counter" "Not cleared,Cleared" bitfld.long 0x10 1. " INVBYTORD ,Inverse frame byte order" "Not inversed,Inversed" bitfld.long 0x10 0. " ENPARSER ,Enable receive parser" "Disabled,Enabled" line.long 0x14 "MAXFRMOFF,Maximum Frame Offset" bitfld.long 0x14 0.--5. " MXFRMOFF ,Maximum frame offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hgroup.long 0x598++0x03 hide.long 0x00 "RXPARST,Receive Parser Status" in newline rgroup.long 0x5A0++0x1B line.long 0x00 "PARSDSCD,Parser Discard Count" line.long 0x04 "PRSACPT0,Parser Accept Count 0" line.long 0x08 "PRSRJCT0,Parser Reject Count 0" line.long 0x0C "PRSACPT1,Parser Accept Count 1" line.long 0x10 "PRSRJCT1,Parser Reject Count 1" line.long 0x14 "PRSACPT2,Parser Accept Count 2" line.long 0x18 "PRSRJCT2,Parser Reject Count 2" group.long 0x604++0x03 line.long 0x00 "TGSR,Timer Global Status Register" eventfld.long 0x00 3. " TF3 ,Copy of timer flag for channel 3" "No effect,Clear" eventfld.long 0x00 2. " TF2 ,Copy of timer flag for channel 2" "No effect,Clear" eventfld.long 0x00 1. " TF1 ,Copy of timer flag for channel 1" "No effect,Clear" newline eventfld.long 0x00 0. " TF0 ,Copy of timer flag for channel 0" "No effect,Clear" group.long 0x608++0x07 line.long 0x00 "TCSR0,Timer Control Status Register" bitfld.long 0x00 11.--15. " TPWC ,Timer pulse width in 1588-clock cycles" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" eventfld.long 0x00 7. " TF ,Timer flag occur" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--5. " TMODE ,Timer mode" "Disabled,Rising edge,Falling edge,Both edges,Software only,Toggle output on compare,Clear output on compare,Set output on compare,,Set output on compare,Clear output on compare,Set output on compare,,,Pulse output low,Pulse output high" bitfld.long 0x00 0. " TDRE ,Timer DMA request enable" "Disabled,Enabled" line.long 0x04 "TCCR0,Timer Compare Capture Register" group.long 0x610++0x07 line.long 0x00 "TCSR1,Timer Control Status Register" bitfld.long 0x00 11.--15. " TPWC ,Timer pulse width in 1588-clock cycles" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" eventfld.long 0x00 7. " TF ,Timer flag occur" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--5. " TMODE ,Timer mode" "Disabled,Rising edge,Falling edge,Both edges,Software only,Toggle output on compare,Clear output on compare,Set output on compare,,Set output on compare,Clear output on compare,Set output on compare,,,Pulse output low,Pulse output high" bitfld.long 0x00 0. " TDRE ,Timer DMA request enable" "Disabled,Enabled" line.long 0x04 "TCCR1,Timer Compare Capture Register" group.long 0x618++0x07 line.long 0x00 "TCSR2,Timer Control Status Register" bitfld.long 0x00 11.--15. " TPWC ,Timer pulse width in 1588-clock cycles" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" eventfld.long 0x00 7. " TF ,Timer flag occur" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--5. " TMODE ,Timer mode" "Disabled,Rising edge,Falling edge,Both edges,Software only,Toggle output on compare,Clear output on compare,Set output on compare,,Set output on compare,Clear output on compare,Set output on compare,,,Pulse output low,Pulse output high" bitfld.long 0x00 0. " TDRE ,Timer DMA request enable" "Disabled,Enabled" line.long 0x04 "TCCR2,Timer Compare Capture Register" group.long 0x620++0x07 line.long 0x00 "TCSR3,Timer Control Status Register" bitfld.long 0x00 11.--15. " TPWC ,Timer pulse width in 1588-clock cycles" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" eventfld.long 0x00 7. " TF ,Timer flag occur" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--5. " TMODE ,Timer mode" "Disabled,Rising edge,Falling edge,Both edges,Software only,Toggle output on compare,Clear output on compare,Set output on compare,,Set output on compare,Clear output on compare,Set output on compare,,,Pulse output low,Pulse output high" bitfld.long 0x00 0. " TDRE ,Timer DMA request enable" "Disabled,Enabled" line.long 0x04 "TCCR3,Timer Compare Capture Register" width 0x0B tree.end tree "ENET-AVB2" base ad:0x5B050000 width 9. group.long 0x04++0x07 line.long 0x00 "EIR,Interrupt Event Register" eventfld.long 0x00 30. " BABR ,Babbling receive error" "No error,Error" eventfld.long 0x00 29. " BABT ,Babbling transmit error" "No error,Error" eventfld.long 0x00 28. " GRA ,Graceful stop complete" "Not completed,Completed" newline eventfld.long 0x00 27. " TXF ,Transmit frame interrupt" "No interrupt,Interrupt" eventfld.long 0x00 26. " TXB ,Transmit buffer interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " RXF ,Receive frame interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 24. " RXB ,Receive buffer interrupt" "No interrupt,Interrupt" eventfld.long 0x00 23. " MII ,MII interrupt" "No interrupt,Interrupt" eventfld.long 0x00 22. " EBERR ,Ethernet bus error" "No error,Error" newline eventfld.long 0x00 21. " LC ,Late collision occur" "Not occurred,Occurred" eventfld.long 0x00 20. " RL ,Collision retry limit occur" "Not occurred,Occurred" eventfld.long 0x00 19. " UN ,Transmit FIFO underrun" "No underrun,Underrun" newline eventfld.long 0x00 18. " PLR ,Payload receive error" "No error,Error" eventfld.long 0x00 17. " WAKEUP ,Node wakeup request indication" "Not detected,Detected" eventfld.long 0x00 16. " TS_AVAIL ,Transmit timestamp available" "Not available,Available" newline eventfld.long 0x00 15. " TS_TIMER ,Timestamp timer reached period event" "Not reached,Reached" eventfld.long 0x00 14. " RXFLUSH_2 ,RX DMA ring 2 flush indication" "Not flushed,Flushed" eventfld.long 0x00 13. " RXFLUSH_1 ,RX DMA ring 1 flush indication" "Not flushed,Flushed" newline eventfld.long 0x00 12. " RXFLUSH_0 ,RX DMA ring 0 flush indication" "Not flushed,Flushed" eventfld.long 0x00 10. " PARSERR ,Receive parser error" "No error,Error" eventfld.long 0x00 9. " PARSRF ,Receive frame rejection due to table entry MCONFIG[RF] = 1. match" "Not occurred,Occurred" newline eventfld.long 0x00 7. " TXF2 ,Transmit frame interrupt class 2" "No interrupt,Interrupt" eventfld.long 0x00 6. " TXB2 ,Transmit buffer interrupt class 2" "No interrupt,Interrupt" eventfld.long 0x00 5. " RXF2 ,Receive frame interrupt class 2" "No interrupt,Interrupt" newline eventfld.long 0x00 4. " RXB2 ,Receive buffer interrupt class 2" "No interrupt,Interrupt" eventfld.long 0x00 3. " TXF1 ,Transmit frame interrupt class 1" "No interrupt,Interrupt" eventfld.long 0x00 2. " TXB1 ,Transmit buffer interrupt class 1" "No interrupt,Interrupt" newline eventfld.long 0x00 1. " RXF1 ,Receive frame interrupt class 1" "No interrupt,Interrupt" eventfld.long 0x00 0. " RXB1 ,Receive buffer interrupt class 1" "No interrupt,Interrupt" line.long 0x04 "EIMR,Interrupt Mask Register" bitfld.long 0x04 30. " BABR ,BABR interrupt mask" "0,1" bitfld.long 0x04 29. " BABT ,BABT interrupt mask" "0,1" bitfld.long 0x04 28. " GRA ,GRA interrupt mask" "0,1" newline bitfld.long 0x04 27. " TXF ,TXF interrupt mask" "0,1" bitfld.long 0x04 26. " TXB ,TXB interrupt mask" "0,1" bitfld.long 0x04 25. " RXF ,RXF interrupt mask" "0,1" newline bitfld.long 0x04 24. " RXB ,RXB interrupt mask" "0,1" bitfld.long 0x04 23. " MII ,MII interrupt mask" "0,1" bitfld.long 0x04 22. " EBERR ,EBERR interrupt mask" "0,1" newline bitfld.long 0x04 21. " LC ,LC interrupt mask" "0,1" bitfld.long 0x04 20. " RL ,RL interrupt mask" "0,1" bitfld.long 0x04 19. " UN ,UN interrupt mask" "0,1" newline bitfld.long 0x04 18. " PLR ,PLR interrupt mask" "0,1" bitfld.long 0x04 17. " WAKEUP ,WAKEUP interrupt mask" "0,1" bitfld.long 0x04 16. " TS_AVAIL ,TS_AVAIL interrupt mask" "0,1" newline bitfld.long 0x04 15. " TS_TIMER ,TS_TIMER interrupt mask" "0,1" bitfld.long 0x04 14. " RXFLUSH_2 ,RXFLUSH_2 interrupt mask" "0,1" bitfld.long 0x04 13. " RXFLUSH_1 ,RXFLUSH_1 interrupt mask" "0,1" newline bitfld.long 0x04 12. " RXFLUSH_0 ,RXFLUSH_0 interrupt mask" "0,1" bitfld.long 0x04 10. " PARSERR ,Receive parser error mask" "0,1" bitfld.long 0x04 9. " PARSRF ,Receive frame rejected mask" "0,1" newline bitfld.long 0x04 7. " TXF2 ,TXF2 interrupt mask" "0,1" bitfld.long 0x04 6. " TXB2 ,TXB2 interrupt mask" "0,1" bitfld.long 0x04 5. " RXF2 ,RXF2 interrupt mask" "0,1" newline bitfld.long 0x04 4. " RXB2 ,RXB2 interrupt mask" "0,1" bitfld.long 0x04 3. " TXF1 ,TXF1 interrupt mask" "0,1" bitfld.long 0x04 2. " TXB1 ,TXB1 interrupt mask" "0,1" newline bitfld.long 0x04 1. " RXF1 ,RXF1 interrupt mask" "0,1" bitfld.long 0x04 0. " RXB1 ,RXB1 interrupt mask" "0,1" group.long 0x10++0x07 line.long 0x00 "RDAR,Receive Descriptor Active Register" bitfld.long 0x00 24. " RDAR ,Receive descriptor active" "Not active,Active" line.long 0x04 "TDAR,Transmit Descriptor Active Register" bitfld.long 0x04 24. " TDAR ,Transmit descriptor active" "Not active,Active" group.long 0x24++0x03 line.long 0x00 "ECR,Ethernet Control Register" bitfld.long 0x00 17. " RXC_DLY ,Receive clock delay" "Not delayed,Delayed" bitfld.long 0x00 16. " TXC_DLY ,Transmit clock delay" "Not delayed,Delayed" bitfld.long 0x00 11. " SVLANDBL ,S-VLAN double tag require" "Not required,Required" newline bitfld.long 0x00 10. " VLANUSE2ND ,VLAN use second tag" "Not used,Used" bitfld.long 0x00 9. " SVLANEN ,S-VLAN enable" "Disabled,Enabled" bitfld.long 0x00 8. " DBSWP ,Descriptor byte swapping enable" "Not swapped,Swapped" newline bitfld.long 0x00 6. " DBGEN ,Enter hardware freeze mode while device enters debug mode" "Debug mode only,Freeze mode in debug mode" bitfld.long 0x00 5. " SPEED ,Select between 10/100-Mbit/s and 1000-Mbit/s modes of operation" "10/100-Mbit/s,1000-Mbit/s" bitfld.long 0x00 4. " EN1588 ,Enhanced functionality of the MAC select" "Legacy FEC buffer,Enhanced frame time-stamping" newline bitfld.long 0x00 3. " SLEEP ,Sleep mode enable" "Disabled,Enabled" bitfld.long 0x00 2. " MAGICEN ,Magic packet detection enable" "Disabled,Enabled" bitfld.long 0x00 1. " ETHEREN ,Enable the ethernet MAC" "Disabled,Enabled" newline bitfld.long 0x00 0. " RESET ,Ethernet MAC reset" "Disabled,Enabled" group.long 0x40++0x07 line.long 0x00 "MMFR,MII Management Frame Register" bitfld.long 0x00 30.--31. " ST ,Start of frame delimiter" "Extended MDIO,Standard MDIO,?..." bitfld.long 0x00 28.--29. " OP ,Operation code" "Address write,Write operation,Read inc operation,Read operation" hexmask.long.byte 0x00 23.--27. 0x80 " PA ,PHY address" newline hexmask.long.byte 0x00 18.--22. 0x04 " RA ,Register address" bitfld.long 0x00 16.--17. " TA ,Turn around" ",,Enabled,?..." hexmask.long.word 0x00 0.--15. 1. " DATA ,Management frame data" line.long 0x04 "MSCR,MII Speed Control Register" bitfld.long 0x04 8.--10. " HOLDTIME ,Hold time on MDIO output [internal module clock cycle]" "1,2,3,,,,,8" bitfld.long 0x04 7. " DIS_PRE ,Disable preamble" "No,Yes" bitfld.long 0x04 1.--6. " MII_SPEED ,MII speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x64++0x03 line.long 0x00 "MIBC,MIB Control Register" bitfld.long 0x00 31. " MIB_DIS ,Disable MIB logic" "No,Yes" rbitfld.long 0x00 30. " MIB_IDLE ,MIB block updating/not updating(idle) counters mode" "Updating,Idle" bitfld.long 0x00 29. " MIB_CLEAR ,MIB clear" "No effect,Clear" group.long 0x84++0x03 line.long 0x00 "RCR,Receive Control Register" rbitfld.long 0x00 31. " GRS ,Graceful receive stop" "Not stopped,Stopped" bitfld.long 0x00 30. " NLC ,Enables/disables a payload length check" "Disabled,Enabled" hexmask.long.word 0x00 16.--29. 1. " MAX_FL ,Maximum frame length" newline bitfld.long 0x00 15. " CFEN ,MAC control frame enable" "Disabled,Enabled" bitfld.long 0x00 14. " CRCFWD ,CRC field of received frames were transmitted/stripped" "Transmitted,Stripped" bitfld.long 0x00 13. " PAUFWD ,Terminate/Forward pause frames" "Terminated,Forwarded" newline bitfld.long 0x00 12. " PADEN ,Enable frame padding remove on receive" "Disabled,Enabled" bitfld.long 0x00 9. " RMII_10T ,100-Mbits/10-Mbits mode of the RMII or RGMII" "100-Mbit/s,10-Mbit/s" bitfld.long 0x00 8. " RMII_MODE ,MAC MII/RMII mode enable" "MII,RMII" newline bitfld.long 0x00 6. " RGMII_EN ,RGMII mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " FCE ,Flow control enable" "Disabled,Enabled" bitfld.long 0x00 4. " BC_REJ ,Broadcast frame reject" "Not rejected,Rejected" newline bitfld.long 0x00 3. " PROM ,Promiscuous mode enable" "Disabled,Enabled" bitfld.long 0x00 2. " MII_MODE ,Media independent interface mode" ",MII/RMII" bitfld.long 0x00 1. " DRT ,Disable receive on transmit" "No,Yes" newline bitfld.long 0x00 0. " LOOP ,Internal loopback" "Disabled,Enabled" if (((per.l(ad:0x5B050000+0x24)&0x02)==0x00)) group.long 0xC4++0x03 line.long 0x00 "TCR,Transmit Control Register" bitfld.long 0x00 9. " CRCFWD ,Forward frame from application with CRC" "Without CRC,With CRC" bitfld.long 0x00 8. " ADDINS ,Modify MAC address on transmit" "Not modified,Modified" bitfld.long 0x00 5.--7. " ADDSEL ,Source MAC address select on transmit" "Node MAC on PADDR1/2,?..." newline rbitfld.long 0x00 4. " RFC_PAUSE ,Receive frame control pause" "Not paused,Paused" bitfld.long 0x00 3. " TFC_PAUSE ,Transmit frame control pause" "Not paused,Paused" rbitfld.long 0x00 2. " FDEN ,Full-duplex enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " GTS ,Graceful transmit stop" "Not stopped,Stopped" else group.long 0xC4++0x03 line.long 0x00 "TCR,Transmit Control Register" bitfld.long 0x00 9. " CRCFWD ,Forward frame from application with CRC" "Without CRC,With CRC" bitfld.long 0x00 8. " ADDINS ,Modify MAC address on transmit" "Not modified,Modified" bitfld.long 0x00 5.--7. " ADDSEL ,Source MAC address select on transmit" "Node MAC on PADDR1/2,?..." newline rbitfld.long 0x00 4. " RFC_PAUSE ,Receive frame control pause" "Not paused,Paused" bitfld.long 0x00 3. " TFC_PAUSE ,Transmit frame control pause" "Not paused,Paused" bitfld.long 0x00 2. " FDEN ,Full-duplex enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " GTS ,Graceful transmit stop" "Not stopped,Stopped" endif group.long 0xE4++0x0B line.long 0x00 "PALR,Physical Address Lower Register" line.long 0x04 "PAUR,Physical Address Upper Register" hexmask.long.word 0x04 16.--31. 0x01 " PADDR2 ,Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match and the source address field in PAUSE frames" hexmask.long.word 0x04 0.--15. 1. " TYPE ,Type field in PAUSE frames" line.long 0x08 "OPD,Opcode/Pause Duration Register ENET_OPD" hexmask.long.word 0x08 16.--31. 1. " OPCODE ,Opcode field in PAUSE frames" hexmask.long.word 0x08 0.--15. 1. " PAUSE_DUR ,Pause duration" group.long 0xF0++0x03 line.long 0x00 "TXIC0,Transmit Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x00 30. " ICCS ,Interrupt coalescing timer clock source select" "MII/GMII,ENET" hexmask.long.byte 0x00 20.--27. 1. " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0xF4++0x03 line.long 0x00 "TXIC1,Transmit Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x00 30. " ICCS ,Interrupt coalescing timer clock source select" "MII/GMII,ENET" hexmask.long.byte 0x00 20.--27. 1. " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0xF8++0x03 line.long 0x00 "TXIC2,Transmit Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x00 30. " ICCS ,Interrupt coalescing timer clock source select" "MII/GMII,ENET" hexmask.long.byte 0x00 20.--27. 1. " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0x100++0x03 line.long 0x00 "RXIC0,Receive Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x00 30. " ICCS ,Interrupt coalescing timer clock source select" "MII/GMII,ENET" hexmask.long.byte 0x00 20.--27. 1. " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0x104++0x03 line.long 0x00 "RXIC1,Receive Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x00 30. " ICCS ,Interrupt coalescing timer clock source select" "MII/GMII,ENET" hexmask.long.byte 0x00 20.--27. 1. " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0x108++0x03 line.long 0x00 "RXIC2,Receive Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x00 30. " ICCS ,Interrupt coalescing timer clock source select" "MII/GMII,ENET" hexmask.long.byte 0x00 20.--27. 1. " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0x118++0x0F line.long 0x00 "IAUR,Descriptor Individual Upper Address Register" line.long 0x04 "IALR,Descriptor Individual Lower Address Register" line.long 0x08 "GAUR,Descriptor Group Upper Address Register" line.long 0x0C "GALR,Descriptor Group Lower Address Register" group.long 0x144++0x03 line.long 0x00 "TFWR,Transmit FIFO Watermark Register" bitfld.long 0x00 8. " STRFWD ,Store and forward enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " TFWR ,Transmit FIFO write" "64 bytes,64 bytes,128 bytes,192 bytes,256 bytes,320 bytes,384 bytes,448 bytes,512 bytes,576 bytes,640 bytes,704 bytes,768 bytes,832 bytes,896 bytes,960 bytes,1024 bytes,1088 bytes,1152 bytes,1216 bytes,1280 bytes,1344 bytes,1408 bytes,1472 bytes,1536 bytes,1600 bytes,1664 bytes,1728 bytes,1792 bytes,1856 bytes,1920 bytes,1984 bytes,2048 bytes,2112 bytes,2176 bytes,2240 bytes,2304 bytes,2368 bytes,2432 bytes,2496 bytes,2560 bytes,2624 bytes,2688 bytes,2752 bytes,2816 bytes,2880 bytes,2944 bytes,3008 bytes,3072 bytes,3136 bytes,3200 bytes,3264 bytes,3328 bytes,3392 bytes,3456 bytes,3520 bytes,3584 bytes,3648 bytes,3712 bytes,3776 bytes,3840 bytes,3904 bytes,3968 bytes,4032 bytes" group.long 0x160++0x0B line.long 0x00 "RDSR1,Receive Descriptor Ring 1 Start Register" hexmask.long 0x00 3.--31. 0x08 " R_DES_START ,Pointer to the beginning of the receive buffer descriptor queue 1" line.long 0x04 "TDSR1,Transmit Buffer Descriptor Ring 1 Start Register" hexmask.long 0x04 3.--31. 0x08 " X_DES_START ,Pointer to the beginning of the transmit buffer descriptor queue 1" line.long 0x08 "MRBR1,Maximum Receive Buffer Size Register" hexmask.long.word 0x08 4.--13. 1. " R_BUF_SIZE ,Receive buffer size in bytes" group.long 0x16C++0x0B line.long 0x00 "RDSR2,Receive Descriptor Ring 2 Start Register" hexmask.long 0x00 3.--31. 0x08 " R_DES_START ,Pointer to the beginning of the receive buffer descriptor queue 2" line.long 0x04 "TDSR2,Transmit Buffer Descriptor Ring 2 Start Register" hexmask.long 0x04 3.--31. 0x08 " X_DES_START ,Pointer to the beginning of the transmit buffer descriptor queue 2" line.long 0x08 "MRBR2,Maximum Receive Buffer Size Register" hexmask.long.word 0x08 4.--13. 1. " R_BUF_SIZE ,Receive buffer size in bytes" group.long 0x180++0x0B line.long 0x00 "RDSR,Receive Descriptor Ring 0 Start Register" hexmask.long 0x00 3.--31. 0x08 " R_DES_START ,Pointer to the beginning of the receive buffer descriptor queue $2" line.long 0x04 "TDSR,Transmit Buffer Descriptor Ring 0 Start Register" hexmask.long 0x04 3.--31. 0x08 " X_DES_START ,Pointer to the beginning of the transmit buffer descriptor queue $2" line.long 0x08 "MRBR,Maximum Receive Buffer Size Register" hexmask.long.word 0x08 4.--13. 1. " R_BUF_SIZE ,Receive buffer size in bytes" group.long 0x190++0x23 line.long 0x00 "RSFL,Receive FIFO Section Full Threshold" hexmask.long.word 0x00 0.--9. 1. " RX_SECTION_FULL ,Value of receive FIFO section full threshold" line.long 0x04 "RSEM,Receive FIFO Section Empty Threshold" bitfld.long 0x04 16.--20. " STAT_SECTION_EMPTY ,RX status FIFO section empty threshold" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x04 0.--9. 1. " RX_SECTION_EMPTY ,Value of the receive FIFO section empty threshold" line.long 0x08 "RAEM,Receive FIFO Almost Empty Threshold" hexmask.long.word 0x08 0.--9. 1. " RX_ALMOST_EMPTY ,Value of the receive FIFO almost empty threshold" line.long 0x0C "RAFL,Receive FIFO Almost Full Threshold" hexmask.long.word 0x0C 0.--9. 1. " RX_ALMOST_FULL ,Value of the receive FIFO almost full threshold" line.long 0x10 "TSEM,Transmit FIFO Section Empty Threshold" hexmask.long.word 0x10 0.--9. 1. " TX_SECTION_EMPTY ,Value of the transmit FIFO section empty threshold" line.long 0x14 "TAEM,Transmit FIFO Almost Empty Threshold" hexmask.long.word 0x14 0.--9. 1. " TX_ALMOST_EMPTY ,Value of transmit FIFO almost empty threshold" line.long 0x18 "TAFL,Transmit FIFO Almost Full Threshold" hexmask.long.word 0x18 0.--9. 1. " TX_ALMOST_FULL ,Value of the transmit FIFO almost full threshold" line.long 0x1C "TIPG,Transmit Inter-Packet Gap" bitfld.long 0x1C 0.--4. " IPG ,Transmit inter-packet gap" "12,12,12,12,12,12,12,12,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,12,12,12,12,12" line.long 0x20 "FTRL,Frame Truncation Length" hexmask.long.word 0x20 0.--13. 1. " TRUNC_FL ,Frame truncation length" group.long 0x1C0++0x07 line.long 0x00 "TACC,Transmit Accelerator Function Configuration" bitfld.long 0x00 4. " PROCHK ,Enables insertion of protocol checksum" "Not inserted,Inserted" bitfld.long 0x00 3. " IPCHK ,Enables insertion of IP header checksum" "Not inserted,Inserted" bitfld.long 0x00 0. " SHIFT16 ,TX FIFO shift-16 enable" "Disabled,Enabled" line.long 0x04 "RACC,Receive Accelerator Function Configuration" bitfld.long 0x04 7. " SHIFT16 ,RX FIFO shift-16 enable" "Disabled,Enabled" bitfld.long 0x04 6. " LINEDIS ,Enable discard of frames with MAC layer errors" "Disabled,Enabled" bitfld.long 0x04 2. " PRODIS ,Enable discard of frames with wrong protocol checksum" "Disabled,Enabled" newline bitfld.long 0x04 1. " IPDIS ,Enable discard of frames with wrong IPv4 header checksum" "Disabled,Enabled" bitfld.long 0x04 0. " PADREM ,Enable padding removal for short IP frames" "Disabled,Enabled" group.long 0x1C8++0x03 line.long 0x00 "RCMR0,Receive Classification Match Register For Class 0" bitfld.long 0x00 16. " MATCHEN ,Match enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. " CMP3 ,Compare 3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " CMP2 ,Compare 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4.--6. " CMP1 ,Compare 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " CMP0 ,Compare 0" "0,1,2,3,4,5,6,7" group.long (0x1C8+0x10)++0x03 line.long 0x00 "DMA0CFG,DMA Class Based Configuration 0" bitfld.long 0x00 17. " CALC_NOIPG ,Disable inclusion of IPG bytes for bandwidth calculations" "No,Yes" bitfld.long 0x00 16. " DMA_CLASS_EN ,DMA class enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " IDLE_SLOPE ,Idle slope" group.long 0x1CC++0x03 line.long 0x00 "RCMR1,Receive Classification Match Register For Class 1" bitfld.long 0x00 16. " MATCHEN ,Match enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. " CMP3 ,Compare 3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " CMP2 ,Compare 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4.--6. " CMP1 ,Compare 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " CMP0 ,Compare 0" "0,1,2,3,4,5,6,7" group.long (0x1CC+0x10)++0x03 line.long 0x00 "DMA1CFG,DMA Class Based Configuration 1" bitfld.long 0x00 17. " CALC_NOIPG ,Disable inclusion of IPG bytes for bandwidth calculations" "No,Yes" bitfld.long 0x00 16. " DMA_CLASS_EN ,DMA class enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " IDLE_SLOPE ,Idle slope" group.long 0x1E0++0x07 line.long 0x00 "RDAR0,Receive Descriptor Active Register - Ring 0" bitfld.long 0x00 24. " RDAR ,Receive descriptor active" "Not active,Active" line.long 0x04 "TDAR0,Transmit Descriptor Active Register - Ring 0" bitfld.long 0x04 24. " TDAR ,Transmit descriptor active" "Not active,Active" group.long 0x1E8++0x07 line.long 0x00 "RDAR1,Receive Descriptor Active Register - Ring 1" bitfld.long 0x00 24. " RDAR ,Receive descriptor active" "Not active,Active" line.long 0x04 "TDAR1,Transmit Descriptor Active Register - Ring 1" bitfld.long 0x04 24. " TDAR ,Transmit descriptor active" "Not active,Active" group.long 0x1F0++0x03 line.long 0x00 "QOS,QOS Scheme" bitfld.long 0x00 5. " RX_FLUSH2 ,RX flush for ring 2 enable" "Disabled,Enabled" bitfld.long 0x00 4. " RX_FLUSH1 ,RX flush for ring 1 enable" "Disabled,Enabled" bitfld.long 0x00 3. " RX_FLUSH0 ,RX flush for ring 0 enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--2. " TX_SCHEME ,TX scheme configuration" "Credit-based scheme,Round-robin scheme,?..." newline width 20. rgroup.long 0x204++0x43 line.long 0x00 "RMON_T_PACKETS,Tx Packet Count Statistic Register" hexmask.long.word 0x00 0.--15. 1. " TXPKTS ,Transmit packet count" line.long 0x04 "RMON_T_BC_PKT,Tx Broadcast Packets Statistic Register" hexmask.long.word 0x04 0.--15. 1. " TXPKTS ,Broadcast packets" line.long 0x08 "RMON_T_MC_PKT,Tx Multicast Packets Statistic Register" hexmask.long.word 0x08 0.--15. 1. " TXPKTS ,Multicast packets" line.long 0x0C "RMON_T_CRC_ALIGN,Tx Packets With CRC/Align Error Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " TXPKTS ,Packets with CRC/align error" line.long 0x10 "RMON_T_UNDERSIZE,Tx Packets Less Than Bytes And Good CRC Statistic Register" hexmask.long.word 0x10 0.--15. 1. " TXPKTS ,Number of transmit packets less than 64 bytes with good CRC" line.long 0x14 "RMON_T_OVERSIZE,Tx Packets GT MAX_FL Bytes And Good CRC Statistic Register" hexmask.long.word 0x14 0.--15. 1. " TXPKTS ,Number of transmit packets greater than MAX_FL bytes with good CRC" line.long 0x18 "RMON_T_FRAG,Tx Packets Less Than 64 Bytes And Bad CRC Statistic Register" hexmask.long.word 0x18 0.--15. 1. " TXPKTS ,Number of packets less than 64 bytes with bad CRC" line.long 0x1C "RMON_T_JAB,Tx Packets Greater Than MAX_FL Bytes And Bad CRC Statistic Register" hexmask.long.word 0x1C 0.--15. 1. " TXPKTS ,Number of transmit packets greater than MAX_FL bytes and bad CRC" line.long 0x20 "RMON_T_COL,Tx Collision Count Statistic Register" hexmask.long.word 0x20 0.--15. 1. " TXPKTS ,Number of transmit collisions" line.long 0x24 "RMON_T_P64,Tx 64-Byte Packets Statistic Register" hexmask.long.word 0x24 0.--15. 1. " TXPKTS ,Number of 64-byte transmit packets" line.long 0x28 "RMON_T_P65TO127,Tx 65- To 127-byte Packets Statistic Register" hexmask.long.word 0x28 0.--15. 1. " TXPKTS ,Number of 65- to 127-byte transmit packets" line.long 0x2C "RMON_T_P128TO255,Tx 128- To 255-byte Packets Statistic Register" hexmask.long.word 0x2C 0.--15. 1. " TXPKTS ,Number of 128- to 255-byte transmit packets" line.long 0x30 "RMON_T_P256TO511,Tx 256- To 511-byte Packets Statistic Register" hexmask.long.word 0x30 0.--15. 1. " TXPKTS ,Number of 256- to 511-byte transmit packets" line.long 0x34 "RMON_T_P512TO1023,Tx 512- To 1023-byte Packets Statistic Register" hexmask.long.word 0x34 0.--15. 1. " TXPKTS ,Number of 512- to 1023-byte transmit packets" line.long 0x38 "RMON_T_P1024TO2047,Tx 1024- To 2047-byte Packets Statistic Register" hexmask.long.word 0x38 0.--15. 1. " TXPKTS ,Number of 1024- to 2047-byte transmit packets" line.long 0x3C "RMON_T_P_GTE2048,Tx Packets Greater Than 2048 Bytes Statistic Register" hexmask.long.word 0x3C 0.--15. 1. " TXPKTS ,Number of transmit packets greater than 2048 bytes" line.long 0x40 "RMON_T_OCTETS,Tx Octets Statistic Register" rgroup.long 0x24C++0x1F line.long 0x00 "IEEE_T_FRAME_OK,Frames Transmitted OK Statistic Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Number of frames transmitted OK" line.long 0x04 "IEEE_T_1COL,Frames Transmitted With Single Collision Statistic Register" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Number of frames transmitted with one collision" line.long 0x08 "IEEE_T_MCOL,Frames Transmitted With Multiple Collisions Statistic Register" hexmask.long.word 0x08 0.--15. 1. " COUNT ,Number of frames transmitted with multiple collisions" line.long 0x0C "IEEE_T_DEF,Frames Transmitted After Deferral Delay Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Number of frames transmitted with deferral delay" line.long 0x10 "IEEE_T_LCOL,Frames Transmitted With Late Collision Statistic Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of frames transmitted with late collision" line.long 0x14 "IEEE_T_EXCOL,Frames Transmitted With Excessive Collisions Statistic Register" hexmask.long.word 0x14 0.--15. 1. " COUNT ,Number of frames transmitted with excessive collisions" line.long 0x18 "IEEE_T_MACERR,Frames Transmitted With Tx FIFO Underrun Statistic Register" hexmask.long.word 0x18 0.--15. 1. " COUNT ,Number of frames transmitted with transmit FIFO underrun" line.long 0x1C "IEEE_T_CSERR,Frames Transmitted With Carrier Sense Error Statistic Register" hexmask.long.word 0x1C 0.--15. 1. " COUNT ,Number of frames transmitted with carrier sense error" rgroup.long 0x270++0x07 line.long 0x00 "IEEE_T_FDXFC,Flow Control Pause Frames Transmitted Statistic Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Number of flow-control pause frames transmitted" line.long 0x04 "IEEE_T_OCTETS_OK,Octet Count For Frames Transmitted w/o Error Statistic Register" rgroup.long 0x284++0x1F line.long 0x00 "RMON_R_PACKETS,Rx Packet Count Statistic Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Number of packets received" line.long 0x04 "RMON_R_BC_PKT,Rx Broadcast Packets Statistic Register" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Number of receive broadcast packets" line.long 0x08 "RMON_R_MC_PKT,Rx Multicast Packets Statistic Register" hexmask.long.word 0x08 0.--15. 1. " COUNT ,Number of receive multicast packets" line.long 0x0C "RMON_R_CRC_ALIGN,Rx Packets With CRC/Align Error Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Number of receive packets with CRC or align error" line.long 0x10 "RMON_R_UNDERSIZE,Rx Packets With Less Than 64 Bytes And Good CRC Statistic Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of receive packets with less than 64 bytes and good CRC" line.long 0x14 "RMON_R_OVERSIZE,Rx Packets Greater Than MAX_FL And Good CRC Statistic Register" hexmask.long.word 0x14 0.--15. 1. " COUNT ,Number of receive packets greater than MAX_FL and good CRC" line.long 0x18 "RMON_R_FRAG,Rx Packets Less Than 64 Bytes And Bad CRC Statistic Register" hexmask.long.word 0x18 0.--15. 1. " COUNT ,Number of receive packets with less than 64 bytes and bad CRC" line.long 0x1C "RMON_R_JAB,Rx Packets Greater Than MAX_FL Bytes And Bad CRC Statistic Register" hexmask.long.word 0x1C 0.--15. 1. " COUNT ,Number of receive packets greater than MAX_FL and bad CRC" rgroup.long 0x2A8++0x3B line.long 0x00 "RMON_R_P64,Rx 64-Byte Packets Statistic Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Number of 64-byte receive packets" line.long 0x04 "RMON_R_P65TO127,Rx 65- To 127-Byte Packets Statistic Register" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Number of 65- to 127-byte recieve packets" line.long 0x08 "RMON_R_P128TO255,Rx 128- To 255-Byte Packets Statistic Register" hexmask.long.word 0x08 0.--15. 1. " COUNT ,Number of 128- to 255-byte recieve packets" line.long 0x0C "RMON_R_P256TO511,Rx 256- To 511-Byte Packets Statistic Register" hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Number of 256- to 511-byte recieve packets" line.long 0x10 "RMON_R_P512TO1023,Rx 512- To 1023-Byte Packets Statistic Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of 512- to 1023-byte recieve packets" line.long 0x14 "RMON_R_P1024TO2047,Rx 1024- To 2047-Byte Packets Statistic Register" hexmask.long.word 0x14 0.--15. 1. " COUNT ,Number of 1024- to 2047-byte recieve packets" line.long 0x18 "RMON_R_P_GTE2048,Rx Packets Greater Than 2048 Bytes Statistic Register" hexmask.long.word 0x18 0.--15. 1. " COUNT ,Number of greater-than-2048-byte recieve packets" line.long 0x1C "RMON_R_OCTETS,Rx Octets Statistic Register" line.long 0x20 "IEEE_R_DROP,Frames Not Counted Correctly Statistic Register" hexmask.long.word 0x20 0.--15. 1. " COUNT ,Frame count" line.long 0x24 "IEEE_R_FRAME_OK,Frames Received OK Statistic Register" hexmask.long.word 0x24 0.--15. 1. " COUNT ,Number of frames received OK" line.long 0x28 "IEEE_R_CRC,Frames Received With CRC Error Statistic Register" hexmask.long.word 0x28 0.--15. 1. " COUNT ,Number of frames received with CRC error" line.long 0x2C "IEEE_R_ALIGN,Frames Received With Alignment Error Statistic Register" hexmask.long.word 0x2C 0.--15. 1. " COUNT ,Number of frames received with alignment error" line.long 0x30 "IEEE_R_MACERR,Receive FIFO Overflow Count Statistic Register" hexmask.long.word 0x30 0.--15. 1. " COUNT ,Receive FIFO overflow count" line.long 0x34 "IEEE_R_FDXFC,Flow Control Pause Frames Received Statistic Register" hexmask.long.word 0x34 0.--15. 1. " COUNT ,Number of flow-control pause frames received" line.long 0x38 "IEEE_R_OCTETS_OK,Octet Count For Frames Received Without Error Statistic Register" if (((per.long((ad:0x5B050000)+0x400))&0xA00)==0x00) group.long 0x400++0x03 line.long 0x00 "ATCR,Adjustable Timer Control Register" bitfld.long 0x00 13. " SLAVE ,Enable timer slave mode" "Disabled,Enabled" bitfld.long 0x00 11. " CAPTURE ,Capture current time" "No effect,Time captured" bitfld.long 0x00 9. " RESTART ,Reset timer" "No reset,Reset" newline bitfld.long 0x00 7. " PINPER ,Enables event signal output assertion on period event" "Disabled,Enabled" bitfld.long 0x00 4. " PEREN ,Enable periodical event" "Disabled,Enabled" bitfld.long 0x00 3. " OFFRST ,Reset timer on offset event" "No reset,Reset" newline bitfld.long 0x00 2. " OFFEN ,Enable one-shot offset event" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Enable timer" "Disabled,Enabled" else group.long 0x400++0x03 line.long 0x00 "ATCR,Adjustable Timer Control Register" rbitfld.long 0x00 13. " SLAVE ,Enable timer slave mode" "Disabled,Enabled" bitfld.long 0x00 11. " CAPTURE ,Capture current time" "No effect,Time captured" bitfld.long 0x00 9. " RESTART ,Reset timer" "No reset,Reset" newline rbitfld.long 0x00 7. " PINPER ,Enables event signal output assertion on period event" "Disabled,Enabled" rbitfld.long 0x00 4. " PEREN ,Enable periodical event" "Disabled,Enabled" rbitfld.long 0x00 3. " OFFRST ,Reset timer on offset event" "No reset,Reset" newline rbitfld.long 0x00 2. " OFFEN ,Enable one-shot offset event" "Disabled,Enabled" rbitfld.long 0x00 0. " EN ,Enable timer" "Disabled,Enabled" endif group.long 0x404++0x13 line.long 0x00 "ATVR,Timer Value Register" line.long 0x04 "ATOFF,Timer Offset Register" line.long 0x08 "ATPER,Timer Period Register" line.long 0x0C "ATCOR,Timer Correction Register" hexmask.long 0x0C 0.--30. 1. " COR ,Correction counter wrap-around value" line.long 0x10 "ATINC,Time-Stamping Clock Period Register" hexmask.long.byte 0x10 8.--14. 1. " INC_CORR ,Correction increment value" hexmask.long.byte 0x10 0.--6. 1. " INC ,Clock period of the timestamping clock in nanoseconds" rgroup.long 0x418++0x03 line.long 0x00 "ATSTMP,Timestamp Of Last Transmitted Frame" group.long 0x580++0x17 line.long 0x00 "MDATA,Pattern Match Data Register" newline line.long 0x04 "MMASK,Match Entry Mask Register" bitfld.long 0x04 31. " MATCHMASK ,MDATA bit 31 mask" "0,1" bitfld.long 0x04 30. ",MDATA bit 30 mask" "0,1" bitfld.long 0x04 29. ",MDATA bit 29 mask" "0,1" bitfld.long 0x04 28. ",MDATA bit 28 mask" "0,1" bitfld.long 0x04 27. ",MDATA bit 27 mask" "0,1" bitfld.long 0x04 26. ",MDATA bit 26 mask" "0,1" bitfld.long 0x04 25. ",MDATA bit 25 mask" "0,1" bitfld.long 0x04 24. ",MDATA bit 24 mask" "0,1" bitfld.long 0x04 23. ",MDATA bit 23 mask" "0,1" bitfld.long 0x04 22. ",MDATA bit 22 mask" "0,1" bitfld.long 0x04 21. ",MDATA bit 21 mask" "0,1" bitfld.long 0x04 20. ",MDATA bit 20 mask" "0,1" bitfld.long 0x04 19. ",MDATA bit 19 mask" "0,1" bitfld.long 0x04 18. ",MDATA bit 18 mask" "0,1" bitfld.long 0x04 17. ",MDATA bit 17 mask" "0,1" bitfld.long 0x04 16. ",MDATA bit 16 mask" "0,1" bitfld.long 0x04 15. ",MDATA bit 15 mask" "0,1" bitfld.long 0x04 14. ",MDATA bit 14 mask" "0,1" bitfld.long 0x04 13. ",MDATA bit 13 mask" "0,1" bitfld.long 0x04 12. ",MDATA bit 12 mask" "0,1" bitfld.long 0x04 11. ",MDATA bit 11 mask" "0,1" bitfld.long 0x04 10. ",MDATA bit 10 mask" "0,1" bitfld.long 0x04 9. ",MDATA bit 9 mask" "0,1" bitfld.long 0x04 8. ",MDATA bit 8 mask" "0,1" bitfld.long 0x04 7. ",MDATA bit 7 mask" "0,1" bitfld.long 0x04 6. ",MDATA bit 6 mask" "0,1" bitfld.long 0x04 5. ",MDATA bit 5 mask" "0,1" bitfld.long 0x04 4. ",MDATA bit 4 mask" "0,1" bitfld.long 0x04 3. ",MDATA bit 3 mask" "0,1" bitfld.long 0x04 2. ",MDATA bit 2 mask" "0,1" bitfld.long 0x04 1. ",MDATA bit 1 mask" "0,1" bitfld.long 0x04 0. ",MDATA bit 0 mask" "0,1" newline line.long 0x08 "MCONFIG,Match Entry Rules Configuration Register" bitfld.long 0x08 31. " AF ,Accept frame" "Not accepted,Accepted" bitfld.long 0x08 30. " RF ,Reject frame" "Not rejected,Rejected" bitfld.long 0x08 29. " IM ,Invert match" "Not inverted,Inverted" newline hexmask.long.byte 0x08 16.--23. 1. " OK_INDEX ,OK index" bitfld.long 0x08 2.--7. " FRMOFF ,Frame offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "MENTRYRW,Match Entry Read/Write Command Register" bitfld.long 0x0C 9. " RD ,Entry read command" "No read,Read" bitfld.long 0x0C 8. " WR ,Entry write command" "No write,Write" hexmask.long.byte 0x0C 0.--7. 0x01 " ENTRYADD ,Entry address" line.long 0x10 "RXPCTL,Receive Parser Control Register" bitfld.long 0x10 24. " ACPTEERR ,Accept end error" "Not accepted,Accepted" hexmask.long.byte 0x10 16.--23. 1. " ENDERRQ ,End error queue" hexmask.long.byte 0x10 8.--15. 1. " MAXINDEX ,Maximum index" newline bitfld.long 0x10 4. " PRSRSCLR ,Clear parser statistics counter" "Not cleared,Cleared" bitfld.long 0x10 1. " INVBYTORD ,Inverse frame byte order" "Not inversed,Inversed" bitfld.long 0x10 0. " ENPARSER ,Enable receive parser" "Disabled,Enabled" line.long 0x14 "MAXFRMOFF,Maximum Frame Offset" bitfld.long 0x14 0.--5. " MXFRMOFF ,Maximum frame offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hgroup.long 0x598++0x03 hide.long 0x00 "RXPARST,Receive Parser Status" in newline rgroup.long 0x5A0++0x1B line.long 0x00 "PARSDSCD,Parser Discard Count" line.long 0x04 "PRSACPT0,Parser Accept Count 0" line.long 0x08 "PRSRJCT0,Parser Reject Count 0" line.long 0x0C "PRSACPT1,Parser Accept Count 1" line.long 0x10 "PRSRJCT1,Parser Reject Count 1" line.long 0x14 "PRSACPT2,Parser Accept Count 2" line.long 0x18 "PRSRJCT2,Parser Reject Count 2" group.long 0x604++0x03 line.long 0x00 "TGSR,Timer Global Status Register" eventfld.long 0x00 3. " TF3 ,Copy of timer flag for channel 3" "No effect,Clear" eventfld.long 0x00 2. " TF2 ,Copy of timer flag for channel 2" "No effect,Clear" eventfld.long 0x00 1. " TF1 ,Copy of timer flag for channel 1" "No effect,Clear" newline eventfld.long 0x00 0. " TF0 ,Copy of timer flag for channel 0" "No effect,Clear" group.long 0x608++0x07 line.long 0x00 "TCSR0,Timer Control Status Register" bitfld.long 0x00 11.--15. " TPWC ,Timer pulse width in 1588-clock cycles" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" eventfld.long 0x00 7. " TF ,Timer flag occur" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--5. " TMODE ,Timer mode" "Disabled,Rising edge,Falling edge,Both edges,Software only,Toggle output on compare,Clear output on compare,Set output on compare,,Set output on compare,Clear output on compare,Set output on compare,,,Pulse output low,Pulse output high" bitfld.long 0x00 0. " TDRE ,Timer DMA request enable" "Disabled,Enabled" line.long 0x04 "TCCR0,Timer Compare Capture Register" group.long 0x610++0x07 line.long 0x00 "TCSR1,Timer Control Status Register" bitfld.long 0x00 11.--15. " TPWC ,Timer pulse width in 1588-clock cycles" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" eventfld.long 0x00 7. " TF ,Timer flag occur" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--5. " TMODE ,Timer mode" "Disabled,Rising edge,Falling edge,Both edges,Software only,Toggle output on compare,Clear output on compare,Set output on compare,,Set output on compare,Clear output on compare,Set output on compare,,,Pulse output low,Pulse output high" bitfld.long 0x00 0. " TDRE ,Timer DMA request enable" "Disabled,Enabled" line.long 0x04 "TCCR1,Timer Compare Capture Register" group.long 0x618++0x07 line.long 0x00 "TCSR2,Timer Control Status Register" bitfld.long 0x00 11.--15. " TPWC ,Timer pulse width in 1588-clock cycles" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" eventfld.long 0x00 7. " TF ,Timer flag occur" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--5. " TMODE ,Timer mode" "Disabled,Rising edge,Falling edge,Both edges,Software only,Toggle output on compare,Clear output on compare,Set output on compare,,Set output on compare,Clear output on compare,Set output on compare,,,Pulse output low,Pulse output high" bitfld.long 0x00 0. " TDRE ,Timer DMA request enable" "Disabled,Enabled" line.long 0x04 "TCCR2,Timer Compare Capture Register" group.long 0x620++0x07 line.long 0x00 "TCSR3,Timer Control Status Register" bitfld.long 0x00 11.--15. " TPWC ,Timer pulse width in 1588-clock cycles" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" eventfld.long 0x00 7. " TF ,Timer flag occur" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--5. " TMODE ,Timer mode" "Disabled,Rising edge,Falling edge,Both edges,Software only,Toggle output on compare,Clear output on compare,Set output on compare,,Set output on compare,Clear output on compare,Set output on compare,,,Pulse output low,Pulse output high" bitfld.long 0x00 0. " TDRE ,Timer DMA request enable" "Disabled,Enabled" line.long 0x04 "TCCR3,Timer Compare Capture Register" width 0x0B tree.end tree.end ; tree "GPMI (General Purpose Media Interface)" ; base ad:0x00 ; %include imx8x/gpmi.ph ad:0x00 ; tree.end tree "uSDHC (Ultra Secured Digital Host Controller)" tree "uSDHC1" base ad:0x5B010000 width 22. if ((((per.l(ad:0x5B010000+0x24))&0x04)==0x04)||(((per.l(ad:0x5B010000+0x30))&0x02)==0x02)) rgroup.long 0x00++0x03 line.long 0x00 "DS_ADDR,DMA System Address Register" hexmask.long 0x00 2.--31. 0x04 " DS_ADDR ,DMA system address" else group.long 0x00++0x03 line.long 0x00 "DS_ADDR,DMA System Address Register" hexmask.long 0x00 2.--31. 0x04 " DS_ADDR ,DMA system address" endif if (((per.l(ad:0x5B010000+0x48))&0x02)==0x02) group.long 0x04++0x03 line.long 0x00 "BLK_ATT,Block Attributes Register" hexmask.long.word 0x00 16.--31. 1. " BLKCNT ,Blocks count for current transfer" hexmask.long.word 0x00 0.--12. 1. " BLKSIZE ,Transfer block size" else group.long 0x04++0x03 line.long 0x00 "BLK_ATT,Block Attributes Register" textfld " " hexmask.long.word 0x00 0.--12. 1. " BLKSIZE ,Transfer block size" endif if (((per.l(ad:0x5B010000+0x24))&0x01)==0x00) group.long 0x08++0x03 line.long 0x00 "CMD_ARG,Command Argument Register" else rgroup.long 0x08++0x03 line.long 0x00 "CMD_ARG,Command Argument Register" endif if (((per.l(ad:0x5B010000+0x24))&0x80003)==0x80000) group.long 0x0C++0x03 line.long 0x00 "CMD_XFR_TYP,Command Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspended,Resumed,Aborted" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,Length 136,Length 48,Length 48/busy check" else rgroup.long 0x0C++0x03 line.long 0x00 "CMD_XFR_TYP,Command Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspended,Resumed,Aborted" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,Length 136,Length 48,Length 48/busy check" endif rgroup.long 0x10++0x03 line.long 0x00 "CMD_RSP0,Command Response Register 0" rgroup.long 0x14++0x03 line.long 0x00 "CMD_RSP1,Command Response Register 1" rgroup.long 0x18++0x03 line.long 0x00 "CMD_RSP2,Command Response Register 2" rgroup.long 0x1C++0x03 line.long 0x00 "CMD_RSP3,Command Response Register 3" group.long 0x20++0x03 line.long 0x00 "DATA_BUFF_ACC_PORT,Data Buffer Access Port Register" rgroup.long 0x24++0x03 line.long 0x00 "PRES_STATE,Present State Register" hexmask.long.byte 0x00 24.--31. 1. " DLSL ,DATA line signal level" bitfld.long 0x00 23. " CLSL ,CMD line signal level" "Low,High" bitfld.long 0x00 19. " WPSPL ,Write protect switch pin level" "Protected,Not protected" newline bitfld.long 0x00 18. " CDPL ,Card detect pin level" "Not detected,Detected" bitfld.long 0x00 16. " CINST ,Card inserted" "Reset/not inserted,Inserted" bitfld.long 0x00 11. " BREN ,Buffer read enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " BWEN ,Buffer write enable" "Disabled,Enabled" bitfld.long 0x00 9. " RTA ,Read transfer active" "Inactive,Active" bitfld.long 0x00 8. " WTA ,Write transfer active" "Inactive,Active" newline bitfld.long 0x00 7. " SDOFF ,SD clock gated off internally" "No,Yes" bitfld.long 0x00 6. " PEROFF ,IPG_PERCLK gated off internally" "No,Yes" bitfld.long 0x00 5. " HCKOFF ,HCLK gated off internally" "No,Yes" newline bitfld.long 0x00 4. " IPGOFF ,IPG_CLK gated off internally" "No,Yes" bitfld.long 0x00 3. " SDSTB ,SD clock stable" "Unstable,Stable" bitfld.long 0x00 2. " DLA ,Data line active" "Inactive,Active" newline bitfld.long 0x00 1. " CDIHB ,Command inhibit (DATA)" "Not inhibited,Inhibited" bitfld.long 0x00 0. " CIHB ,Command inhibit (CMD)" "Not inhibited,Inhibited" if (((per.l(ad:0x5B010000+0x28))&0x06)==0x02) group.long 0x28++0x03 line.long 0x00 "PROT_CTRL,Protocol Control Register" bitfld.long 0x00 30. " NON_EXACT_BLK_RD ,Non-exact block read" "Exact,Non-exact" bitfld.long 0x00 26. " WECRM ,Wakeup event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " WECINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled" newline bitfld.long 0x00 24. " WECINT ,Wakeup event enable on card interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " RD_DONE_NO_8_CLK ,Read done no 8 clock" "Low,High" bitfld.long 0x00 19. " IABG ,Interrupt at block gap" "Disabled,Enabled" newline bitfld.long 0x00 18. " RWCTL ,Read wait control" "Disabled,Enabled" bitfld.long 0x00 17. " CREQ ,Continue request" "No effect,Restart" bitfld.long 0x00 16. " SABGREQ ,Stop at block gap request" "Transferred,Stopped" newline bitfld.long 0x00 8.--9. " DMASEL ,DMA select" "Not selected,ADMA1,ADMA2,?..." bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "Normal,Test" bitfld.long 0x00 6. " CDTL ,Card detect test level" "Not detected,Detected" newline bitfld.long 0x00 4.--5. " EMODE ,Endian mode" "Big endian,Half word big endian,Little endian,?..." bitfld.long 0x00 3. " D3CD ,DAT3 as card detection pin" "No,Yes" bitfld.long 0x00 1.--2. " DTW ,Data transfer width" "1-bit,4-bit,8-bit,?..." newline bitfld.long 0x00 0. " LCTL ,LED control" "Off,On" else group.long 0x28++0x03 line.long 0x00 "PROT_CTRL,Protocol Control Register" bitfld.long 0x00 30. " NON_EXACT_BLK_RD ,Non-exact block read" "Exact,Non-exact" bitfld.long 0x00 26. " WECRM ,Wakeup event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " WECINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled" newline bitfld.long 0x00 24. " WECINT ,Wakeup event enable on card interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " RD_DONE_NO_8_CLK ,Read done no 8 clock" "Low,High" newline bitfld.long 0x00 18. " RWCTL ,Read wait control" "Disabled,Enabled" bitfld.long 0x00 17. " CREQ ,Continue request" "No effect,Restart" bitfld.long 0x00 16. " SABGREQ ,Stop at block gap request" "Transferred,Stopped" newline bitfld.long 0x00 8.--9. " DMASEL ,DMA select" "Not selected,ADMA1,ADMA2,?..." bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "Normal,Test" bitfld.long 0x00 6. " CDTL ,Card detect test level" "Not detected,Detected" newline bitfld.long 0x00 4.--5. " EMODE ,Endian mode" "Big endian,Half word big endian,Little endian,?..." bitfld.long 0x00 3. " D3CD ,DAT3 as card detection pin" "No,Yes" bitfld.long 0x00 1.--2. " DTW ,Data transfer width" "1-bit,4-bit,8-bit,?..." newline bitfld.long 0x00 0. " LCTL ,LED control" "Off,On" endif group.long 0x2C++0x0F line.long 0x00 "SYS_CTRL,System Control Register" bitfld.long 0x00 27. " INITA ,Initialization active" "Inactive,Active" bitfld.long 0x00 26. " RSTD ,Software reset for DATA line" "No reset,Reset" bitfld.long 0x00 25. " RSTC ,Software reset for CMD line" "No reset,Reset" newline bitfld.long 0x00 24. " RSTA ,Software reset for ALL" "No reset,Reset" bitfld.long 0x00 23. " IPP_RST_N ,Value output to CARD for hardware reset" "Low,High" bitfld.long 0x00 16.--19. " DTOCV ,Data timeout counter value" "SDCLK x 2^14,SDCLK x 2^15,,,,,,,,,,,,SDCLK x 2^27,SDCLK x 2^28,SDCLK x 2^29" newline hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK frequency select" bitfld.long 0x00 4.--7. " DVS ,Divisor" "/1,/2,,,,,,,,,,,,,/15,/16" line.long 0x04 "INT_STATUS,Interrupt Status Register" eventfld.long 0x04 28. " DMAE ,DMA error" "No error,Error" eventfld.long 0x04 24. " AC12E ,Auto CMD12 error" "No error,Error" eventfld.long 0x04 22. " DEBE ,Data end bit error" "No error,Error" newline eventfld.long 0x04 21. " DCE ,Data CRC error" "No error,Error" eventfld.long 0x04 20. " DTOE ,Data timeout error" "No error,Error" eventfld.long 0x04 19. " CIE ,Command index error" "No error,Error" newline eventfld.long 0x04 18. " CEBE ,Command end bit error" "No error,Error" eventfld.long 0x04 17. " CCE ,Command CRC error" "No error,Error" eventfld.long 0x04 16. " CTOE ,Command timeout error" "No error,Error" newline eventfld.long 0x04 8. " CINT ,Card interrupt" "No interrupt,Interrupt" eventfld.long 0x04 7. " CRM ,Card removal" "Not removed,Removed" eventfld.long 0x04 6. " CINS ,Card insertion" "Not inserted,Inserted" newline eventfld.long 0x04 5. " BRR ,Buffer read ready" "Not ready,Ready" eventfld.long 0x04 4. " BWR ,Buffer write ready" "Not ready,Ready" eventfld.long 0x04 3. " DINT ,DMA interrupt" "No interrupt,Interrupt" newline eventfld.long 0x04 2. " BGE ,Block gap event" "Not occurred,Occurred" eventfld.long 0x04 1. " TC ,Transfer complete" "Not completed,Completed" eventfld.long 0x04 0. " CC ,Command complete" "Not completed,Completed" line.long 0x08 "INT_STATUS_EN,Interrupt Status Enable Register" bitfld.long 0x08 28. " DMAESEN ,DMA error status enable" "Disabled,Enabled" bitfld.long 0x08 24. " AC12ESEN ,Auto CMD12 error status enable" "Disabled,Enabled" bitfld.long 0x08 22. " DEBESEN ,Data end bit error status enable" "Disabled,Enabled" newline bitfld.long 0x08 21. " DCESEN ,Data CRC error status enable" "Disabled,Enabled" bitfld.long 0x08 20. " DTOESEN ,Data timeout error status enable" "Disabled,Enabled" bitfld.long 0x08 19. " CIESEN ,Command index error status enable" "Disabled,Enabled" newline bitfld.long 0x08 18. " CEBESEN ,Command end bit error status enable" "Disabled,Enabled" bitfld.long 0x08 17. " CCESEN ,Command CRC error status enable" "Disabled,Enabled" bitfld.long 0x08 16. " CTOESEN ,Command timeout error status enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " CINTSEN ,Card interrupt status enable" "Disabled,Enabled" bitfld.long 0x08 7. " CRMSEN ,Card removal status enable" "Disabled,Enabled" bitfld.long 0x08 6. " CINSSEN ,Card insertion status enable" "Disabled,Enabled" newline bitfld.long 0x08 5. " BRRSEN ,Buffer read ready status enable" "Disabled,Enabled" bitfld.long 0x08 4. " BWRSEN ,Buffer write ready status enable" "Disabled,Enabled" bitfld.long 0x08 3. " DINTSEN ,DMA interrupt status enable" "Disabled,Enabled" newline bitfld.long 0x08 2. " BGESEN ,Block gap event status enable" "Disabled,Enabled" bitfld.long 0x08 1. " TCSEN ,Transfer complete status enable" "Disabled,Enabled" bitfld.long 0x08 0. " CCSEN ,Command complete status enable" "Disabled,Enabled" line.long 0x0C "INT_SIGNAL_EN,Interrupt Signal Enable Register" bitfld.long 0x0C 28. " DMAEIEN ,DMA error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 24. " AC12EIEN ,Auto CMD12 error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 22. " DEBEIEN ,Data end bit error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 21. " DCEIEN ,Data CRC error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 20. " DTOEIEN ,Data timeout error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 19. " CIEIEN ,Command index error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 18. " CEBEIEN ,Command end bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 17. " CCEIEN ,Command CRC error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 16. " CTOEIEN ,Command timeout error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 8. " CINTIEN ,Card interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 7. " CRMIEN ,Card removal interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 6. " CINSIEN ,Card insertion interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 5. " BRRIEN ,Buffer read ready interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " BWRIEN ,Buffer write ready interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " DINTIEN ,DMA interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 2. " BGEIEN ,Block gap event interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 1. " TCIEN ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " CCIEN ,Command complete interrupt enable" "Disabled,Enabled" rgroup.long 0x3C++0x03 line.long 0x00 "AUTOCMD12_ERR_STATUS,Auto CMD12 Error Status Register" bitfld.long 0x00 7. " CNIBAC12E ,Command not issued by auto CMD12 error" "No error,Not issued" bitfld.long 0x00 4. " AC12IE ,Auto CMD12 index error" "No error,Error" bitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC error" "No error,Error" newline bitfld.long 0x00 2. " AC12EBE ,Auto CMD12 end bit error" "No error,Error" bitfld.long 0x00 1. " AC12TOE ,Auto CMD12 timeout error" "No error,Error" bitfld.long 0x00 0. " AC12NE ,Auto CMD12 not executed" "Executed,Not executed" group.long 0x40++0x0B line.long 0x00 "HOST_CTRL_CAP,Host Controller Capabilities Register" rbitfld.long 0x00 26. " VS18 ,Voltage support 1.8V" "Not supported,Supported" rbitfld.long 0x00 25. " VS30 ,Voltage support 3.0V" "Not supported,Supported" rbitfld.long 0x00 24. " VS33 ,Voltage support 3.3V" "Not supported,Supported" newline rbitfld.long 0x00 23. " SRS ,Suspend / resume support" "Not supported,Supported" rbitfld.long 0x00 22. " DMAS ,DMA support" "Not supported,Supported" rbitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported" newline rbitfld.long 0x00 20. " ADMAS ,ADMA support" "Not supported,Supported" rbitfld.long 0x00 16.--18. " MBL ,Max block length" "512 bytes,1024 bytes,2048 bytes,4096 bytes,?..." line.long 0x04 "WTMK_LVL,Watermark Level Register" hexmask.long.byte 0x04 16.--23. 1. " WR_WML ,Write watermark level" hexmask.long.byte 0x04 0.--7. 1. " RD_WML ,Read watermark level" line.long 0x08 "MIX_CTRL,Mixer Control Register" bitfld.long 0x08 26. " HS400_MODE ,HS400 enable" "Disabled,Enabled" bitfld.long 0x08 7. " AC23EN ,Auto CMD23 enable" "Disabled,Enabled" bitfld.long 0x08 6. " NIBBLE_POS ,Nibble position" "Disabled,Enabled" newline bitfld.long 0x08 5. " MSBSEL ,Multi/single block select" "Single,Multiple" bitfld.long 0x08 4. " DTDSEL ,Data transfer direction select" "Write,Read" bitfld.long 0x08 3. " DDR_EN ,Dual data rate mode selection" "Disabled,Enabled" newline bitfld.long 0x08 2. " AC12EN ,Auto CMD12 enable" "Disabled,Enabled" bitfld.long 0x08 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x08 0. " DMAEN ,DMA enable" "Disabled,Enabled" wgroup.long 0x50++0x03 line.long 0x00 "FORCE_EVENT,Force Event Register" bitfld.long 0x00 31. " FEVTCINT ,Force event card interrupt" "No interrupt,Interrupt" bitfld.long 0x00 28. " FEVTDMAE ,Force event DMA error" "No error,Error" bitfld.long 0x00 24. " FEVTAC12E ,Force event auto command 12 error" "No error,Error" newline bitfld.long 0x00 22. " FEVTDEBE ,Force event data end bit error" "No error,Error" bitfld.long 0x00 21. " FEVTDCE ,Force event data CRC error" "No error,Error" bitfld.long 0x00 20. " FEVTDTOE ,Force event data time out error" "No error,Error" newline bitfld.long 0x00 19. " FEVTCIE ,Force event command index error" "No error,Error" bitfld.long 0x00 18. " FEVTCEBE ,Force event command end bit error" "No error,Error" bitfld.long 0x00 17. " FEVTCCE ,Force event command CRC error" "No error,Error" newline bitfld.long 0x00 16. " FEVTCTOE ,Force event command time out error" "No error,Error" bitfld.long 0x00 7. " FEVTCNIBAC12E ,Force event command not executed by auto command 12 error" "No error,Error" bitfld.long 0x00 4. " FEVTAC12IE ,Force event auto command 12 index error" "No error,Error" newline bitfld.long 0x00 3. " FEVTAC12EBE ,Force event auto command 12 end bit error" "No error,Error" bitfld.long 0x00 2. " FEVTAC12CE ,Force event auto command 12 CRC error" "No error,Error" bitfld.long 0x00 1. " FEVTAC12TOE ,Force event auto command 12 time out error" "No error,Error" newline bitfld.long 0x00 0. " FEVTAC12NE ,Force event auto command 12 not executed" "No error,Error" rgroup.long 0x54++0x03 line.long 0x00 "ADMA_ERR_STATUS,ADMA Error Status Register" bitfld.long 0x00 3. " ADMADCE ,ADMA descriptor error" "No error,Error" bitfld.long 0x00 2. " ADMALME ,ADMA length mismatch error" "No error,Error" bitfld.long 0x00 0.--1. " ADMAES ,ADMA error state" "ST_STOP,ST_FDS,ST_CADR,ST_TFR" if (((per.l(ad:0x5B010000+0x30))&0x02)==0x02) rgroup.long 0x58++0x03 line.long 0x00 "ADMA_SYS_ADDR,ADMA System Address Register" hexmask.long 0x00 2.--31. 0x04 " ADS_ADDR ,ADMA system address" else group.long 0x58++0x03 line.long 0x00 "ADMA_SYS_ADDR,ADMA System Address Register" hexmask.long 0x00 2.--31. 0x04 " ADS_ADDR ,ADMA system address" endif group.long 0x70++0x03 line.long 0x00 "STROBE_DLL_CTRL,Strobe DLL Control" bitfld.long 0x00 28.--31. " STROBE_DLL_CTRL_REF_UPDATE_INT ,Strobe DLL control reference update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 20.--27. 1. " STROBE_DLL_CTRL_SLV_UPDATE_INT ,Strobe DLL control slave update interval" newline hexmask.long.byte 0x00 9.--15. 1. " STROBE_DLL_CTRL_SLV_OVERRIDE_VAL ,Strobe DLL control slave override value" newline bitfld.long 0x00 8. " STROBE_DLL_CTRL_SLV_OVERRIDE ,Strobe DLL control slave override enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " STROBE_DLL_CTRL_GATE_UPDATE_1 ,Strobe DLL control gate update" "Automatically,No update" newline bitfld.long 0x00 6. " STROBE_DLL_CTRL_GATE_UPDATE_0 ,Strobe DLL control gate update" "Automatically,No update" newline bitfld.long 0x00 3.--5. " STROBE_DLL_CTRL_SLV_DLY_TARGET ,Strobe DLL control slave delay target" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " STROBE_DLL_CTRL_SLV_FORCE_UPD ,Strobe DLL control slave force updated" "Not forced,Forced" newline bitfld.long 0x00 1. " STROBE_DLL_CTRL_RESET ,Strobe DLL control reset" "No reset,Reset" newline bitfld.long 0x00 0. " STROBE_DLL_CTRL_ENABLE ,Strobe DLL control enable" "Disabled,Enabled" rgroup.long 0x74++0x03 line.long 0x00 "STROBE_DLL_STATUS,Strobe DLL Status" hexmask.long.byte 0x00 9.--15. 1. " STROBE_DLL_STS_REF_SEL ,Strobe DLL status reference select" hexmask.long.word 0x00 2.--8. 1. " STROBE_DLL_STS_SLV_SEL ,Strobe DLL status slave select" newline bitfld.long 0x00 1. " STROBE_DLL_STS_REF_LOCK ,Strobe DLL status reference lock" "Not locked,Locked" bitfld.long 0x00 0. " STROBE_DLL_STS_SLV_LOCK ,Strobe DLL status slave lock" "Not locked,Locked" group.long 0xC0++0x0B line.long 0x00 "VEND_SPEC,Vendor Specific Register" bitfld.long 0x00 31. " CMD_BYTE_EN ,Byte access" "Disabled,Enabled" bitfld.long 0x00 15. " CRC_CHK_DIS ,CRC check disable" "No,Yes" bitfld.long 0x00 8. " FRC_SDCLK_ON ,Force CLK output active" "Not forced,Forced" newline bitfld.long 0x00 3. " AC12_WR_CHKBUSY_EN ,Check busy enable after auto CMD12 for write data packet" "Disabled,Enabled" bitfld.long 0x00 2. " CONFLICT_CHK_EN ,Conflict check enable" "Disabled,Enabled" bitfld.long 0x00 1. " VSELECT ,Voltage selection (around: 3.0V (high) / 1.8V (low))" "High,Low" line.long 0x04 "MMC_BOOT,MMC Boot Register" hexmask.long.word 0x04 16.--31. 1. " BOOT_BLK_CNT ,Boot block gap counter" bitfld.long 0x04 8. " DISABLE_TIME_OUT ,Disable time out" "No,Yes" bitfld.long 0x04 7. " AUTO_SABG_EN ,Auto stop at block gap enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " BOOT_EN ,Boot mode enable" "Disable,Enabled" bitfld.long 0x04 5. " BOOT_MODE ,Boot mode select" "Normal,Alternative" bitfld.long 0x04 4. " BOOT_ACK ,Boot ACK mode select" "No ACK,ACK" newline bitfld.long 0x04 0.--3. " DTOCV_ACK ,Boot ACK timeout counter value" "SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,,,,,,,SDCLK x 2^28,SDCLK x 2^29" line.long 0x08 "VEND_SPEC2,Vendor Specific 2 Register" bitfld.long 0x08 11. " HS400_RD_CLK_STOP_EN ,HS400 read clock stop enable" "Disabled,Enabled" bitfld.long 0x08 10. " HS400_WR_CLK_STOP_EN ,HS400 write clock stop enable" "Disabled,Enabled" bitfld.long 0x08 3. " CARD_INT_D3_TEST ,Card interrupt detection test" "DAT[3] high,Ignored DAT[3]" width 0x0B tree.end tree "uSDHC2" base ad:0x5B020000 width 22. if ((((per.l(ad:0x5B020000+0x24))&0x04)==0x04)||(((per.l(ad:0x5B020000+0x30))&0x02)==0x02)) rgroup.long 0x00++0x03 line.long 0x00 "DS_ADDR,DMA System Address Register" hexmask.long 0x00 2.--31. 0x04 " DS_ADDR ,DMA system address" else group.long 0x00++0x03 line.long 0x00 "DS_ADDR,DMA System Address Register" hexmask.long 0x00 2.--31. 0x04 " DS_ADDR ,DMA system address" endif if (((per.l(ad:0x5B020000+0x48))&0x02)==0x02) group.long 0x04++0x03 line.long 0x00 "BLK_ATT,Block Attributes Register" hexmask.long.word 0x00 16.--31. 1. " BLKCNT ,Blocks count for current transfer" hexmask.long.word 0x00 0.--12. 1. " BLKSIZE ,Transfer block size" else group.long 0x04++0x03 line.long 0x00 "BLK_ATT,Block Attributes Register" textfld " " hexmask.long.word 0x00 0.--12. 1. " BLKSIZE ,Transfer block size" endif if (((per.l(ad:0x5B020000+0x24))&0x01)==0x00) group.long 0x08++0x03 line.long 0x00 "CMD_ARG,Command Argument Register" else rgroup.long 0x08++0x03 line.long 0x00 "CMD_ARG,Command Argument Register" endif if (((per.l(ad:0x5B020000+0x24))&0x80003)==0x80000) group.long 0x0C++0x03 line.long 0x00 "CMD_XFR_TYP,Command Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspended,Resumed,Aborted" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,Length 136,Length 48,Length 48/busy check" else rgroup.long 0x0C++0x03 line.long 0x00 "CMD_XFR_TYP,Command Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspended,Resumed,Aborted" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,Length 136,Length 48,Length 48/busy check" endif rgroup.long 0x10++0x03 line.long 0x00 "CMD_RSP0,Command Response Register 0" rgroup.long 0x14++0x03 line.long 0x00 "CMD_RSP1,Command Response Register 1" rgroup.long 0x18++0x03 line.long 0x00 "CMD_RSP2,Command Response Register 2" rgroup.long 0x1C++0x03 line.long 0x00 "CMD_RSP3,Command Response Register 3" group.long 0x20++0x03 line.long 0x00 "DATA_BUFF_ACC_PORT,Data Buffer Access Port Register" rgroup.long 0x24++0x03 line.long 0x00 "PRES_STATE,Present State Register" hexmask.long.byte 0x00 24.--31. 1. " DLSL ,DATA line signal level" bitfld.long 0x00 23. " CLSL ,CMD line signal level" "Low,High" bitfld.long 0x00 19. " WPSPL ,Write protect switch pin level" "Protected,Not protected" newline bitfld.long 0x00 18. " CDPL ,Card detect pin level" "Not detected,Detected" bitfld.long 0x00 16. " CINST ,Card inserted" "Reset/not inserted,Inserted" bitfld.long 0x00 11. " BREN ,Buffer read enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " BWEN ,Buffer write enable" "Disabled,Enabled" bitfld.long 0x00 9. " RTA ,Read transfer active" "Inactive,Active" bitfld.long 0x00 8. " WTA ,Write transfer active" "Inactive,Active" newline bitfld.long 0x00 7. " SDOFF ,SD clock gated off internally" "No,Yes" bitfld.long 0x00 6. " PEROFF ,IPG_PERCLK gated off internally" "No,Yes" bitfld.long 0x00 5. " HCKOFF ,HCLK gated off internally" "No,Yes" newline bitfld.long 0x00 4. " IPGOFF ,IPG_CLK gated off internally" "No,Yes" bitfld.long 0x00 3. " SDSTB ,SD clock stable" "Unstable,Stable" bitfld.long 0x00 2. " DLA ,Data line active" "Inactive,Active" newline bitfld.long 0x00 1. " CDIHB ,Command inhibit (DATA)" "Not inhibited,Inhibited" bitfld.long 0x00 0. " CIHB ,Command inhibit (CMD)" "Not inhibited,Inhibited" if (((per.l(ad:0x5B020000+0x28))&0x06)==0x02) group.long 0x28++0x03 line.long 0x00 "PROT_CTRL,Protocol Control Register" bitfld.long 0x00 30. " NON_EXACT_BLK_RD ,Non-exact block read" "Exact,Non-exact" bitfld.long 0x00 26. " WECRM ,Wakeup event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " WECINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled" newline bitfld.long 0x00 24. " WECINT ,Wakeup event enable on card interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " RD_DONE_NO_8_CLK ,Read done no 8 clock" "Low,High" bitfld.long 0x00 19. " IABG ,Interrupt at block gap" "Disabled,Enabled" newline bitfld.long 0x00 18. " RWCTL ,Read wait control" "Disabled,Enabled" bitfld.long 0x00 17. " CREQ ,Continue request" "No effect,Restart" bitfld.long 0x00 16. " SABGREQ ,Stop at block gap request" "Transferred,Stopped" newline bitfld.long 0x00 8.--9. " DMASEL ,DMA select" "Not selected,ADMA1,ADMA2,?..." bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "Normal,Test" bitfld.long 0x00 6. " CDTL ,Card detect test level" "Not detected,Detected" newline bitfld.long 0x00 4.--5. " EMODE ,Endian mode" "Big endian,Half word big endian,Little endian,?..." bitfld.long 0x00 3. " D3CD ,DAT3 as card detection pin" "No,Yes" bitfld.long 0x00 1.--2. " DTW ,Data transfer width" "1-bit,4-bit,8-bit,?..." newline bitfld.long 0x00 0. " LCTL ,LED control" "Off,On" else group.long 0x28++0x03 line.long 0x00 "PROT_CTRL,Protocol Control Register" bitfld.long 0x00 30. " NON_EXACT_BLK_RD ,Non-exact block read" "Exact,Non-exact" bitfld.long 0x00 26. " WECRM ,Wakeup event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " WECINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled" newline bitfld.long 0x00 24. " WECINT ,Wakeup event enable on card interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " RD_DONE_NO_8_CLK ,Read done no 8 clock" "Low,High" newline bitfld.long 0x00 18. " RWCTL ,Read wait control" "Disabled,Enabled" bitfld.long 0x00 17. " CREQ ,Continue request" "No effect,Restart" bitfld.long 0x00 16. " SABGREQ ,Stop at block gap request" "Transferred,Stopped" newline bitfld.long 0x00 8.--9. " DMASEL ,DMA select" "Not selected,ADMA1,ADMA2,?..." bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "Normal,Test" bitfld.long 0x00 6. " CDTL ,Card detect test level" "Not detected,Detected" newline bitfld.long 0x00 4.--5. " EMODE ,Endian mode" "Big endian,Half word big endian,Little endian,?..." bitfld.long 0x00 3. " D3CD ,DAT3 as card detection pin" "No,Yes" bitfld.long 0x00 1.--2. " DTW ,Data transfer width" "1-bit,4-bit,8-bit,?..." newline bitfld.long 0x00 0. " LCTL ,LED control" "Off,On" endif group.long 0x2C++0x0F line.long 0x00 "SYS_CTRL,System Control Register" bitfld.long 0x00 27. " INITA ,Initialization active" "Inactive,Active" bitfld.long 0x00 26. " RSTD ,Software reset for DATA line" "No reset,Reset" bitfld.long 0x00 25. " RSTC ,Software reset for CMD line" "No reset,Reset" newline bitfld.long 0x00 24. " RSTA ,Software reset for ALL" "No reset,Reset" bitfld.long 0x00 23. " IPP_RST_N ,Value output to CARD for hardware reset" "Low,High" bitfld.long 0x00 16.--19. " DTOCV ,Data timeout counter value" "SDCLK x 2^14,SDCLK x 2^15,,,,,,,,,,,,SDCLK x 2^27,SDCLK x 2^28,SDCLK x 2^29" newline hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK frequency select" bitfld.long 0x00 4.--7. " DVS ,Divisor" "/1,/2,,,,,,,,,,,,,/15,/16" line.long 0x04 "INT_STATUS,Interrupt Status Register" eventfld.long 0x04 28. " DMAE ,DMA error" "No error,Error" eventfld.long 0x04 24. " AC12E ,Auto CMD12 error" "No error,Error" eventfld.long 0x04 22. " DEBE ,Data end bit error" "No error,Error" newline eventfld.long 0x04 21. " DCE ,Data CRC error" "No error,Error" eventfld.long 0x04 20. " DTOE ,Data timeout error" "No error,Error" eventfld.long 0x04 19. " CIE ,Command index error" "No error,Error" newline eventfld.long 0x04 18. " CEBE ,Command end bit error" "No error,Error" eventfld.long 0x04 17. " CCE ,Command CRC error" "No error,Error" eventfld.long 0x04 16. " CTOE ,Command timeout error" "No error,Error" newline eventfld.long 0x04 8. " CINT ,Card interrupt" "No interrupt,Interrupt" eventfld.long 0x04 7. " CRM ,Card removal" "Not removed,Removed" eventfld.long 0x04 6. " CINS ,Card insertion" "Not inserted,Inserted" newline eventfld.long 0x04 5. " BRR ,Buffer read ready" "Not ready,Ready" eventfld.long 0x04 4. " BWR ,Buffer write ready" "Not ready,Ready" eventfld.long 0x04 3. " DINT ,DMA interrupt" "No interrupt,Interrupt" newline eventfld.long 0x04 2. " BGE ,Block gap event" "Not occurred,Occurred" eventfld.long 0x04 1. " TC ,Transfer complete" "Not completed,Completed" eventfld.long 0x04 0. " CC ,Command complete" "Not completed,Completed" line.long 0x08 "INT_STATUS_EN,Interrupt Status Enable Register" bitfld.long 0x08 28. " DMAESEN ,DMA error status enable" "Disabled,Enabled" bitfld.long 0x08 24. " AC12ESEN ,Auto CMD12 error status enable" "Disabled,Enabled" bitfld.long 0x08 22. " DEBESEN ,Data end bit error status enable" "Disabled,Enabled" newline bitfld.long 0x08 21. " DCESEN ,Data CRC error status enable" "Disabled,Enabled" bitfld.long 0x08 20. " DTOESEN ,Data timeout error status enable" "Disabled,Enabled" bitfld.long 0x08 19. " CIESEN ,Command index error status enable" "Disabled,Enabled" newline bitfld.long 0x08 18. " CEBESEN ,Command end bit error status enable" "Disabled,Enabled" bitfld.long 0x08 17. " CCESEN ,Command CRC error status enable" "Disabled,Enabled" bitfld.long 0x08 16. " CTOESEN ,Command timeout error status enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " CINTSEN ,Card interrupt status enable" "Disabled,Enabled" bitfld.long 0x08 7. " CRMSEN ,Card removal status enable" "Disabled,Enabled" bitfld.long 0x08 6. " CINSSEN ,Card insertion status enable" "Disabled,Enabled" newline bitfld.long 0x08 5. " BRRSEN ,Buffer read ready status enable" "Disabled,Enabled" bitfld.long 0x08 4. " BWRSEN ,Buffer write ready status enable" "Disabled,Enabled" bitfld.long 0x08 3. " DINTSEN ,DMA interrupt status enable" "Disabled,Enabled" newline bitfld.long 0x08 2. " BGESEN ,Block gap event status enable" "Disabled,Enabled" bitfld.long 0x08 1. " TCSEN ,Transfer complete status enable" "Disabled,Enabled" bitfld.long 0x08 0. " CCSEN ,Command complete status enable" "Disabled,Enabled" line.long 0x0C "INT_SIGNAL_EN,Interrupt Signal Enable Register" bitfld.long 0x0C 28. " DMAEIEN ,DMA error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 24. " AC12EIEN ,Auto CMD12 error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 22. " DEBEIEN ,Data end bit error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 21. " DCEIEN ,Data CRC error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 20. " DTOEIEN ,Data timeout error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 19. " CIEIEN ,Command index error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 18. " CEBEIEN ,Command end bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 17. " CCEIEN ,Command CRC error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 16. " CTOEIEN ,Command timeout error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 8. " CINTIEN ,Card interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 7. " CRMIEN ,Card removal interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 6. " CINSIEN ,Card insertion interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 5. " BRRIEN ,Buffer read ready interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " BWRIEN ,Buffer write ready interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " DINTIEN ,DMA interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 2. " BGEIEN ,Block gap event interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 1. " TCIEN ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " CCIEN ,Command complete interrupt enable" "Disabled,Enabled" rgroup.long 0x3C++0x03 line.long 0x00 "AUTOCMD12_ERR_STATUS,Auto CMD12 Error Status Register" bitfld.long 0x00 7. " CNIBAC12E ,Command not issued by auto CMD12 error" "No error,Not issued" bitfld.long 0x00 4. " AC12IE ,Auto CMD12 index error" "No error,Error" bitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC error" "No error,Error" newline bitfld.long 0x00 2. " AC12EBE ,Auto CMD12 end bit error" "No error,Error" bitfld.long 0x00 1. " AC12TOE ,Auto CMD12 timeout error" "No error,Error" bitfld.long 0x00 0. " AC12NE ,Auto CMD12 not executed" "Executed,Not executed" group.long 0x40++0x0B line.long 0x00 "HOST_CTRL_CAP,Host Controller Capabilities Register" rbitfld.long 0x00 26. " VS18 ,Voltage support 1.8V" "Not supported,Supported" rbitfld.long 0x00 25. " VS30 ,Voltage support 3.0V" "Not supported,Supported" rbitfld.long 0x00 24. " VS33 ,Voltage support 3.3V" "Not supported,Supported" newline rbitfld.long 0x00 23. " SRS ,Suspend / resume support" "Not supported,Supported" rbitfld.long 0x00 22. " DMAS ,DMA support" "Not supported,Supported" rbitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported" newline rbitfld.long 0x00 20. " ADMAS ,ADMA support" "Not supported,Supported" rbitfld.long 0x00 16.--18. " MBL ,Max block length" "512 bytes,1024 bytes,2048 bytes,4096 bytes,?..." line.long 0x04 "WTMK_LVL,Watermark Level Register" hexmask.long.byte 0x04 16.--23. 1. " WR_WML ,Write watermark level" hexmask.long.byte 0x04 0.--7. 1. " RD_WML ,Read watermark level" line.long 0x08 "MIX_CTRL,Mixer Control Register" bitfld.long 0x08 26. " HS400_MODE ,HS400 enable" "Disabled,Enabled" bitfld.long 0x08 7. " AC23EN ,Auto CMD23 enable" "Disabled,Enabled" bitfld.long 0x08 6. " NIBBLE_POS ,Nibble position" "Disabled,Enabled" newline bitfld.long 0x08 5. " MSBSEL ,Multi/single block select" "Single,Multiple" bitfld.long 0x08 4. " DTDSEL ,Data transfer direction select" "Write,Read" bitfld.long 0x08 3. " DDR_EN ,Dual data rate mode selection" "Disabled,Enabled" newline bitfld.long 0x08 2. " AC12EN ,Auto CMD12 enable" "Disabled,Enabled" bitfld.long 0x08 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x08 0. " DMAEN ,DMA enable" "Disabled,Enabled" wgroup.long 0x50++0x03 line.long 0x00 "FORCE_EVENT,Force Event Register" bitfld.long 0x00 31. " FEVTCINT ,Force event card interrupt" "No interrupt,Interrupt" bitfld.long 0x00 28. " FEVTDMAE ,Force event DMA error" "No error,Error" bitfld.long 0x00 24. " FEVTAC12E ,Force event auto command 12 error" "No error,Error" newline bitfld.long 0x00 22. " FEVTDEBE ,Force event data end bit error" "No error,Error" bitfld.long 0x00 21. " FEVTDCE ,Force event data CRC error" "No error,Error" bitfld.long 0x00 20. " FEVTDTOE ,Force event data time out error" "No error,Error" newline bitfld.long 0x00 19. " FEVTCIE ,Force event command index error" "No error,Error" bitfld.long 0x00 18. " FEVTCEBE ,Force event command end bit error" "No error,Error" bitfld.long 0x00 17. " FEVTCCE ,Force event command CRC error" "No error,Error" newline bitfld.long 0x00 16. " FEVTCTOE ,Force event command time out error" "No error,Error" bitfld.long 0x00 7. " FEVTCNIBAC12E ,Force event command not executed by auto command 12 error" "No error,Error" bitfld.long 0x00 4. " FEVTAC12IE ,Force event auto command 12 index error" "No error,Error" newline bitfld.long 0x00 3. " FEVTAC12EBE ,Force event auto command 12 end bit error" "No error,Error" bitfld.long 0x00 2. " FEVTAC12CE ,Force event auto command 12 CRC error" "No error,Error" bitfld.long 0x00 1. " FEVTAC12TOE ,Force event auto command 12 time out error" "No error,Error" newline bitfld.long 0x00 0. " FEVTAC12NE ,Force event auto command 12 not executed" "No error,Error" rgroup.long 0x54++0x03 line.long 0x00 "ADMA_ERR_STATUS,ADMA Error Status Register" bitfld.long 0x00 3. " ADMADCE ,ADMA descriptor error" "No error,Error" bitfld.long 0x00 2. " ADMALME ,ADMA length mismatch error" "No error,Error" bitfld.long 0x00 0.--1. " ADMAES ,ADMA error state" "ST_STOP,ST_FDS,ST_CADR,ST_TFR" if (((per.l(ad:0x5B020000+0x30))&0x02)==0x02) rgroup.long 0x58++0x03 line.long 0x00 "ADMA_SYS_ADDR,ADMA System Address Register" hexmask.long 0x00 2.--31. 0x04 " ADS_ADDR ,ADMA system address" else group.long 0x58++0x03 line.long 0x00 "ADMA_SYS_ADDR,ADMA System Address Register" hexmask.long 0x00 2.--31. 0x04 " ADS_ADDR ,ADMA system address" endif group.long 0x70++0x03 line.long 0x00 "STROBE_DLL_CTRL,Strobe DLL Control" bitfld.long 0x00 28.--31. " STROBE_DLL_CTRL_REF_UPDATE_INT ,Strobe DLL control reference update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 20.--27. 1. " STROBE_DLL_CTRL_SLV_UPDATE_INT ,Strobe DLL control slave update interval" newline hexmask.long.byte 0x00 9.--15. 1. " STROBE_DLL_CTRL_SLV_OVERRIDE_VAL ,Strobe DLL control slave override value" newline bitfld.long 0x00 8. " STROBE_DLL_CTRL_SLV_OVERRIDE ,Strobe DLL control slave override enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " STROBE_DLL_CTRL_GATE_UPDATE_1 ,Strobe DLL control gate update" "Automatically,No update" newline bitfld.long 0x00 6. " STROBE_DLL_CTRL_GATE_UPDATE_0 ,Strobe DLL control gate update" "Automatically,No update" newline bitfld.long 0x00 3.--5. " STROBE_DLL_CTRL_SLV_DLY_TARGET ,Strobe DLL control slave delay target" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " STROBE_DLL_CTRL_SLV_FORCE_UPD ,Strobe DLL control slave force updated" "Not forced,Forced" newline bitfld.long 0x00 1. " STROBE_DLL_CTRL_RESET ,Strobe DLL control reset" "No reset,Reset" newline bitfld.long 0x00 0. " STROBE_DLL_CTRL_ENABLE ,Strobe DLL control enable" "Disabled,Enabled" rgroup.long 0x74++0x03 line.long 0x00 "STROBE_DLL_STATUS,Strobe DLL Status" hexmask.long.byte 0x00 9.--15. 1. " STROBE_DLL_STS_REF_SEL ,Strobe DLL status reference select" hexmask.long.word 0x00 2.--8. 1. " STROBE_DLL_STS_SLV_SEL ,Strobe DLL status slave select" newline bitfld.long 0x00 1. " STROBE_DLL_STS_REF_LOCK ,Strobe DLL status reference lock" "Not locked,Locked" bitfld.long 0x00 0. " STROBE_DLL_STS_SLV_LOCK ,Strobe DLL status slave lock" "Not locked,Locked" group.long 0xC0++0x0B line.long 0x00 "VEND_SPEC,Vendor Specific Register" bitfld.long 0x00 31. " CMD_BYTE_EN ,Byte access" "Disabled,Enabled" bitfld.long 0x00 15. " CRC_CHK_DIS ,CRC check disable" "No,Yes" bitfld.long 0x00 8. " FRC_SDCLK_ON ,Force CLK output active" "Not forced,Forced" newline bitfld.long 0x00 3. " AC12_WR_CHKBUSY_EN ,Check busy enable after auto CMD12 for write data packet" "Disabled,Enabled" bitfld.long 0x00 2. " CONFLICT_CHK_EN ,Conflict check enable" "Disabled,Enabled" bitfld.long 0x00 1. " VSELECT ,Voltage selection (around: 3.0V (high) / 1.8V (low))" "High,Low" line.long 0x04 "MMC_BOOT,MMC Boot Register" hexmask.long.word 0x04 16.--31. 1. " BOOT_BLK_CNT ,Boot block gap counter" bitfld.long 0x04 8. " DISABLE_TIME_OUT ,Disable time out" "No,Yes" bitfld.long 0x04 7. " AUTO_SABG_EN ,Auto stop at block gap enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " BOOT_EN ,Boot mode enable" "Disable,Enabled" bitfld.long 0x04 5. " BOOT_MODE ,Boot mode select" "Normal,Alternative" bitfld.long 0x04 4. " BOOT_ACK ,Boot ACK mode select" "No ACK,ACK" newline bitfld.long 0x04 0.--3. " DTOCV_ACK ,Boot ACK timeout counter value" "SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,,,,,,,SDCLK x 2^28,SDCLK x 2^29" line.long 0x08 "VEND_SPEC2,Vendor Specific 2 Register" bitfld.long 0x08 11. " HS400_RD_CLK_STOP_EN ,HS400 read clock stop enable" "Disabled,Enabled" bitfld.long 0x08 10. " HS400_WR_CLK_STOP_EN ,HS400 write clock stop enable" "Disabled,Enabled" bitfld.long 0x08 3. " CARD_INT_D3_TEST ,Card interrupt detection test" "DAT[3] high,Ignored DAT[3]" width 0x0B tree.end tree.end ; tree "USBDCD (USB Device Charger Detection Module)" ; base ad:0x00 ; %include imx8x/usbdcd.ph ad:0x00 ; tree.end ; tree "USB2 (Universal Serial Bus 2.0 Controller)" ; tree "Core" ; base ad:0x00 ; %include imx8x/usb2.ph ad:0x00 ; tree.end ; tree "Non-core" ; base ad:0x00 ; %include imx8x/usb2nc.ph ad:0x00 ; tree.end ; tree.end ; tree "USB2-PHY (Universal Serial Bus 2.0 Integrated PHY)" ; base ad:0x00 ; %include imx8x/usbphy.ph ad:0x00 ; tree.end tree "USB3 (Universal Serial Bus 3.0 Controller)" tree "Core" base ad:0x5B110000 width 15. if (((per.l(ad:0x5B110000+0x04))&0x20)==0x20) wgroup.long 0x00++0x03 line.long 0x00 "OTGCMD,OTG Command Register" bitfld.long 0x00 28. " INIT_SRP ,Initiate SRP" "Not initiated,Initiated" bitfld.long 0x00 27. " OTG2_SWITCH_TO_PERIPH ,Switch to peripheral mode when operating at USB 2.0" "Not Switched,Switched" bitfld.long 0x00 12. " HOST_POWER_OFF ,Power down CDNSXHCI" "No power down,Power down" newline bitfld.long 0x00 11. " DEV_POWER_OFF ,Power down USBSS-DEV" "No power down,Power down" bitfld.long 0x00 10. " DIS_VBUS_DROP ,Do not disable vbus while bus is dropped" "Yes,No" bitfld.long 0x00 9. " HOST_BUS_DROP ,Drop the bus for host mode" "Not dropped,Dropped" newline bitfld.long 0x00 8. " DEV_BUS_DROP ,Drop the bus for device mode" "Not dropped,Dropped" bitfld.long 0x00 5. " A_DEV_DIS ,Configure OTG as B-device" "Not configured,Configured" bitfld.long 0x00 4. " A_DEV_EN ,Configure OTG as A-device" "Not configured,Configured" newline bitfld.long 0x00 3. " OTG_DIS ,Disable OTG mode" "Yes,No" bitfld.long 0x00 2. " OTG_EN ,Enable OTG mode" "Disabled,Enabled" bitfld.long 0x00 1. " HOST_BUS_REQ ,Request the bus for host mode" "Not requested,Requested" newline bitfld.long 0x00 0. " DEV_BUS_REQ ,Request the bus for device mode" "Not requested,Requested" group.long 0x04++0x03 line.long 0x00 "OTGSTS,OTG Status Register" rbitfld.long 0x00 27. " DEV_READY ,Device mode is turned on" "Off,On" rbitfld.long 0x00 26. " XHC_READY ,Host mode is turned on" "Off,On" setclrfld.long 0x00 25. -0x04 25. -0x04 26. " B_HNP_EN_SET/CLR ,Device forcing short VBUS decounce is enabled" "Disabled,Enabled" newline setclrfld.long 0x00 23. -0x04 23. -0x04 24. " A_SET_B_HNP_EN_SET/CLR ,SetFeature(b_hnp_enable) has been sent and is valid" "Disabled,Enabled" rbitfld.long 0x00 19. " SRP_DET_NOT_COMPLIANT_DEV ,OTG A-device detected not compliant device" "Not detected,Detected" rbitfld.long 0x00 18. " SRP_INITIAL_CONDITION_MET ,SRP initial condition are met" "Not met,Met" newline setclrfld.long 0x00 17. -0x04 17. -0x04 18. " D_WRST_FOR_SWAP_SET/CLR ,Upcoming warm reset will be received for role swapping from Peripheral to host" "Not swapped,Swapped" setclrfld.long 0x00 16. -0x04 13. -0x04 14. " DEV_DEVEN_FORCE_SET/CLR ,Device forcing DEVEN bit is enabled" "Disabled,Enabled" setclrfld.long 0x00 15. -0x04 15. -0x04 16. " H_WRST_FOR_SWAP_SET/CLR ,Upcoming warm reset will be generated for role swapping from host to peripheral" "Disabled,Enabled" newline rbitfld.long 0x00 12.--14. " STRAP ,Value of the strap pins" "No default configuration,,Host,,Device,?..." rbitfld.long 0x00 11. " OTG_NRDY ,OTG controller not ready" "Ready,Not ready" setclrfld.long 0x00 10. -0x04 6. -0x04 7. " DEV_SESS_VLD_USE_SET/CLR ,Device mode vbus valid indication" "A_VBUS_VLD,B_SESS_VLD" newline setclrfld.long 0x00 9. -0x04 29. -0x04 30. " DEV_VBUS_DEB_SHORT_SET/CLR ,Device forcing short VBUS decounce is enabled" "Disabled,Enabled" setclrfld.long 0x00 8. -0x04 21. -0x04 22. " SS_PERIPH_DISABLED_SET/CLR ,SuperSpeed device functionality is disabled" "Yes,No" setclrfld.long 0x00 7. -0x04 19. -0x04 20. " SS_HOST_DISABLED_SET/CLR ,SuperSpeed host functionality is disabled" "Yes,No" newline rbitfld.long 0x00 6. " OTG_MODE ,OTG mode" "A-device,B-device" rbitfld.long 0x00 5. " OTG_IS_ENABLED ,OTG functionality is enabled" "Disabled,Enabled" rbitfld.long 0x00 4. " HOST_ACTIVE ,Host mode is active" "Not active,Active" newline rbitfld.long 0x00 3. " DEV_ACTIVE ,Device mode is active" "Not active,Active" rbitfld.long 0x00 2. " SESSION_VALID ,Current value of the b_sess_vld" "0,1" rbitfld.long 0x00 1. " VBUS_VALID ,Current value of the vbus_vld" "0,1" newline rbitfld.long 0x00 0. " ID_VALUE ,Current value of the ID pin" "Low,High" else wgroup.long 0x00++0x03 line.long 0x00 "OTGCMD,OTG Command Register" bitfld.long 0x00 28. " INIT_SRP ,Initiate SRP" "Not initiated,Initiated" bitfld.long 0x00 27. " OTG2_SWITCH_TO_PERIPH ,Switch to peripheral mode when operating at USB 2.0" "Not Switched,Switched" bitfld.long 0x00 12. " HOST_POWER_OFF ,Power down CDNSXHCI" "No power down,Power down" newline bitfld.long 0x00 11. " DEV_POWER_OFF ,Power down USBSS-DEV" "No power down,Power down" bitfld.long 0x00 10. " DIS_VBUS_DROP ,Do not disable vbus while bus is dropped" "Yes,No" bitfld.long 0x00 9. " HOST_BUS_DROP ,Drop the bus for host mode" "Not dropped,Dropped" newline bitfld.long 0x00 8. " DEV_BUS_DROP ,Drop the bus for device mode" "Not dropped,Dropped" newline bitfld.long 0x00 3. " OTG_DIS ,Disable OTG mode" "Yes,No" bitfld.long 0x00 2. " OTG_EN ,Enable OTG mode" "Disabled,Enabled" bitfld.long 0x00 1. " HOST_BUS_REQ ,Request the bus for host mode" "Not requested,Requested" newline bitfld.long 0x00 0. " DEV_BUS_REQ ,Request the bus for device mode" "Not requested,Requested" group.long 0x04++0x03 line.long 0x00 "OTGSTS,OTG Status Register" rbitfld.long 0x00 27. " DEV_READY ,Device mode is turned on" "Off,On" rbitfld.long 0x00 26. " XHC_READY ,Host mode is turned on" "Off,On" setclrfld.long 0x00 25. -0x04 25. -0x04 26. " B_HNP_EN_SET/CLR ,Device forcing short VBUS decounce is enabled" "Disabled,Enabled" newline setclrfld.long 0x00 23. -0x04 23. -0x04 24. " A_SET_B_HNP_EN_SET/CLR ,SetFeature(b_hnp_enable) has been sent and is valid" "Disabled,Enabled" rbitfld.long 0x00 19. " SRP_DET_NOT_COMPLIANT_DEV ,OTG A-device detected not compliant device" "Not detected,Detected" rbitfld.long 0x00 18. " SRP_INITIAL_CONDITION_MET ,SRP initial condition are met" "Not met,Met" newline setclrfld.long 0x00 17. -0x04 17. -0x04 18. " D_WRST_FOR_SWAP_SET/CLR ,Upcoming warm reset will be received for role swapping from Peripheral to host" "Not swapped,Swapped" setclrfld.long 0x00 16. -0x04 13. -0x04 14. " DEV_DEVEN_FORCE_SET/CLR ,Device forcing DEVEN bit is enabled" "Disabled,Enabled" setclrfld.long 0x00 15. -0x04 15. -0x04 16. " H_WRST_FOR_SWAP_SET/CLR ,Upcoming warm reset will be generated for role swapping from host to peripheral" "Disabled,Enabled" newline rbitfld.long 0x00 12.--14. " STRAP ,Value of the strap pins" "No default configuration,,Host,,Device,?..." rbitfld.long 0x00 11. " OTG_NRDY ,OTG controller not ready" "Ready,Not ready" setclrfld.long 0x00 10. -0x04 6. -0x04 7. " DEV_SESS_VLD_USE_SET/CLR ,Device mode vbus valid indication" "A_VBUS_VLD,B_SESS_VLD" newline setclrfld.long 0x00 9. -0x04 29. -0x04 30. " DEV_VBUS_DEB_SHORT_SET/CLR ,Device forcing short VBUS decounce is enabled" "Disabled,Enabled" setclrfld.long 0x00 8. -0x04 21. -0x04 22. " SS_PERIPH_DISABLED_SET/CLR ,SuperSpeed device functionality is disabled" "Yes,No" setclrfld.long 0x00 7. -0x04 19. -0x04 20. " SS_HOST_DISABLED_SET/CLR ,SuperSpeed host functionality is disabled" "Yes,No" newline textfld " " rbitfld.long 0x00 5. " OTG_IS_ENABLED ,OTG functionality is enabled" "Disabled,Enabled" rbitfld.long 0x00 4. " HOST_ACTIVE ,Host mode is active" "Not active,Active" newline rbitfld.long 0x00 3. " DEV_ACTIVE ,Device mode is active" "Not active,Active" rbitfld.long 0x00 2. " SESSION_VALID ,Current value of the b_sess_vld" "0,1" rbitfld.long 0x00 1. " VBUS_VALID ,Current value of the vbus_vld" "0,1" newline rbitfld.long 0x00 0. " ID_VALUE ,Current value of the ID pin" "Low,High" endif newline rgroup.long 0x08++0x03 line.long 0x00 "OTGSTATE,OTG State Register" bitfld.long 0x00 27.--29. " REFCLK_FSM ,Reference clock control FSM state" "IDLE,SWITCH32_GATE_ON,REFCLK_OFF,REFCLK_REQ,GATE_OFF,REFCLK_ON_SWITCH32,REFCLK_ON_PHY3_AT_SLOW,REFCLK_ON_SWITCH24" bitfld.long 0x00 26. " PHY_REFCLK_VALID ,Value of the phy_refclk_valid signal" "0,1" bitfld.long 0x00 25. " PHY_REFCLK_1PCT_VALID ,Value of the phy_refclk_1pct_valid signal" "0,1" newline bitfld.long 0x00 24. " PHY_REFCLK_REQ ,Value of the phy_refclk_req signal" "0,1" bitfld.long 0x00 19.--21. " HOST_POWER_STATE ,Current state of the host power controlling FSM" "IDLE,OFF_ACK,OFF_MAIN_ACK,OFF,ON_REQ,ISO_DIS,ON,ON_READY" bitfld.long 0x00 16.--18. " DEV_POWER_STATE ,Current state of the device power controlling FSM" "IDLE,OFF_ACK,OFF_MAIN_ACK,OFF,ON_REQ,ISO_DIS,ON,ON_READY" newline bitfld.long 0x00 12.--13. " UTMI_CTRL ,Current state of the USB2 UTMI mux selector" "OFF,Host,Device,?..." bitfld.long 0x00 10.--11. " PIPE_CTRL ,Current state of the USB3 PIPE mux selector" "Off,Host,Device,?..." bitfld.long 0x00 8.--9. " APB_AXI_CTRL ,Current state of the ABP/AXI mux selector" "OFF,Host,Device,?..." newline bitfld.long 0x00 3.--5. " HOST_OTG_STATE ,Current state of the OTG host FSM" "IDLE,VBUS_ON,VBUS_FAILED,OTG_HOST_MODE,HOST_MODE,SWITCH_TO_DEVICE,A_SUSPEND,WAIT_VBUS_FALL" bitfld.long 0x00 0.--2. " DEV_OTG_STATE ,Current state of the OTG device FSM" "IDLE,MODE,SRP,WAIT_VBUS_FALL,SWITCH_TO_HOST,WAIT_FOR_CONN,?..." group.long 0x0C++0x0B line.long 0x00 "OTGREFCLK,OTG Reference Clock Register" bitfld.long 0x00 31. " OTG_STB_CLK_SWITCH_EN ,Allow PHY reference clock source to be either low frequency or turned off when host/device modes are disable" "Not allowed,Allowed" hexmask.long.word 0x00 16.--29. 1. " SUSPEND_TO_REFCLK_REQ ,Time within which Reference clock won't be requested after USB 2.0 PHY is requested to enter suspend (L2) state" hexmask.long.word 0x00 0.--13. 1. " P3_TO_REFCLK_REQ ,Time within which reference clock won't be requested after USB 3.0 PHY powerdown changes to P3" line.long 0x04 "OTGIEN,OTG Interrupt Enable Register" bitfld.long 0x04 31. " DM_VLGC_COMP_RISE_INT_EN ,DM VLGC comparator rise detect interrupt enable" "Disabled,Enabled" bitfld.long 0x04 30. " DCD_COMP_FALL_INT_EN ,DCD comparator fall detect interrupt enable" "Disabled,Enabled" bitfld.long 0x04 29. " DCD_COMP_RISE_INT_EN ,DCD comparator rise detect interrupt enable" "Disabled,Enabled" newline bitfld.long 0x04 28. " DP_VDAT_REF_RISE_INT_EN ,DP VDAT comparator rise detect interrupt enable" "Disabled,Enabled" bitfld.long 0x04 27. " DM_VDAT_REF_RISE_INT_EN ,DM VDAT comparator rise detect interrupt enable" "Disabled,Enabled" bitfld.long 0x04 26. " RID_A_RISE_INT_EN ,RID A comparator rise detect interrupt enable" "Disabled,Enabled" newline bitfld.long 0x04 25. " RID_B_RISE_INT_EN ,RID B comparator rise detect interrupt enable" "Disabled,Enabled" bitfld.long 0x04 24. " RID_C_RISE_INT_EN ,RID C comparator rise detect interrupt enable" "Disabled,Enabled" bitfld.long 0x04 23. " RID_GND_RISE_INT_EN ,RID GND comparator rise detect interrupt enable" "Disabled,Enabled" newline bitfld.long 0x04 22. " RID_FLOAT_RISE_INT_EN ,RID floating comparator rise detect interrupt enable" "Disabled,Enabled" bitfld.long 0x04 21. " RID_FLOAT_FALL_INT_EN ,RID floating comparator detect interrupt enable" "Disabled,Enabled" bitfld.long 0x04 20. " H_WRST_GEN_CMPL_INT_EN ,Host Warm Reset generation completed interrupt enable" "Disabled,Enabled" newline bitfld.long 0x04 19. " H_POOL_ENTRY_INT_EN ,Host Polling state entry interrupt enable" "Disabled,Enabled" bitfld.long 0x04 18. " TIMER_TMOUT_INT_EN ,Timer timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x04 17. " TB_AIDL_BDIS_MIN_TMOUT_INT_EN ,The bus has been in idle state for the required time during HNP interrupt enable" "Disabled,Enabled" newline bitfld.long 0x04 16. " TB_ASE0_BRST_TMOUT_INT_EN ,No response from A-device to HNP interrupt enable" "Disabled,Enabled" bitfld.long 0x04 15. " SRP_CMPL_INT_EN ,SRP completed interrupt enable" "Disabled,Enabled" bitfld.long 0x04 14. " SRP_FAIL_INT_EN ,No response from SRP from A-device interrupt enable" "Disabled,Enabled" newline bitfld.long 0x04 13. " OVERCURRENT_INT_EN ,Overcurrent condition detected interrupt enable" "Disabled,Enabled" bitfld.long 0x04 12. " SRP_NOT_COMP_DEV_REMOVED_INT_EN ,Non compliant device disconnect interrupt enable" "Disabled,Enabled" bitfld.long 0x04 11. " SRP_DET_INT_EN ,Non compliant device disconnect interrupt enable" "Disabled,Enabled" newline bitfld.long 0x04 10. " TA_BIDL_ADIS_TMOUT_INT_EN ,No activity from B-device timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x04 9. " TA_AIDL_ADIS_TMOUT_INT_EN ,No response from B-Device for HNP interrupt enable" "Disabled,Enabled" bitfld.long 0x04 8. " ADP_PROBE_COMPLETED_INT_EN ,ADP probe completed interrupt enable" "Disabled,Enabled" newline bitfld.long 0x04 7. " PROBE_RISE_INT_EN ,ADP probe comparator rise detected interrupt enable" "Disabled,Enabled" bitfld.long 0x04 6. " SENSE_RISE_INT_EN ,ADP sense comparator rise detected interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " VBUSVALID_FALL_INT_EN ,Vbusvalid fall detected interrupt enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " VBUSVALID_RISE_INT_EN ,Vbusvalid rise detected interrupt enable" "Disabled,Enabled" bitfld.long 0x04 3. " OTGSESSVALID_FALL_INT_EN ,Otgsessvalid fall detected interrupt enable" "Disabled,Enabled" bitfld.long 0x04 2. " OTGSESSVALID_RISE_INT_EN ,Otgsessvalid rise detected interrupt enable" "Disabled,Enabled" newline bitfld.long 0x04 1. " VBUS_ON_FAILED_INT_EN ,Enabling Vbus by A-device has failed interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " ID_CHANGE_INT_EN ,ID change interrupt enable" "Disabled,Enabled" line.long 0x08 "OTGIVECT,OTG Interrupt Vector Register" bitfld.long 0x08 31. " DM_VLGC_COMP_RISE_INT ,DM VLGC comparator rise detect interrupt" "Not occurred,Occurred" bitfld.long 0x08 30. " DCD_COMP_FALL_INT ,DCD comparator fall detect interrupt" "Not occurred,Occurred" bitfld.long 0x08 29. " DCD_COMP_RISE_INT ,DCD comparator rise detect interrupt" "Not occurred,Occurred" newline bitfld.long 0x08 28. " DP_VDAT_REF_RISE_INT ,DP VDAT comparator rise detect interrupt" "Not occurred,Occurred" bitfld.long 0x08 27. " DM_VDAT_REF_RISE_INT ,DM VDAT comparator rise detect interrupt" "Not occurred,Occurred" bitfld.long 0x08 26. " RID_A_RISE_INT ,RID A comparator rise detect interrupt" "Not occurred,Occurred" newline bitfld.long 0x08 25. " RID_B_RISE_INT ,RID B comparator rise detect interrupt" "Not occurred,Occurred" bitfld.long 0x08 24. " RID_C_RISE_INT ,RID C comparator rise detect interrupt" "Not occurred,Occurred" bitfld.long 0x08 23. " RID_GND_RISE_INT ,RID GND comparator rise detect interrupt" "Not occurred,Occurred" newline bitfld.long 0x08 22. " RID_FLOAT_RISE_INT ,RID floating comparator rise detect interrupt" "Not occurred,Occurred" bitfld.long 0x08 21. " RID_FLOAT_FALL_INT ,RID floating comparator detect interrupt" "Not occurred,Occurred" bitfld.long 0x08 20. " H_WRST_GEN_CMPL_INT ,Host warm reset generation completed interrupt" "Not occurred,Occurred" newline bitfld.long 0x08 19. " H_POOLTRY_INT ,Host polling state entry interrupt" "Not occurred,Occurred" bitfld.long 0x08 18. " TIMER_TMOUT_INT ,Timer timeout interrupt" "Not occurred,Occurred" bitfld.long 0x08 17. " TB_AIDL_BDIS_MIN_TMOUT_INT ,The bus has been in idle state for the required time during HNP interrupt" "Not occurred,Occurred" newline bitfld.long 0x08 16. " TB_ASE0_BRST_TMOUT_INT ,No response from A-Device to HNP interrupt" "Not occurred,Occurred" bitfld.long 0x08 15. " SRP_CMPL_INT ,SRP completed interrupt" "Not occurred,Occurred" bitfld.long 0x08 14. " SRP_FAIL_INT ,No response from SRP from A-Device interrupt" "Not occurred,Occurred" newline bitfld.long 0x08 13. " OVERCURRENT_INT ,Overcurrent condition detected interrupt" "Not occurred,Occurred" bitfld.long 0x08 12. " SRP_NOT_COMP_DEV_REMOVED_INT ,Non compliant device disconnect detect interrupt" "Not occurred,Occurred" bitfld.long 0x08 11. " SRP_DET_INT ,SRP pulse detected interrupt" "Not occurred,Occurred" newline bitfld.long 0x08 10. " TA_BIDL_ADIS_TMOUT_INT ,No activity from B-device timeout interrupt" "Not occurred,Occurred" bitfld.long 0x08 9. " TA_AIDL_ADIS_TMOUT_INT ,No response from B-device for HNP interrupt" "Not occurred,Occurred" bitfld.long 0x08 8. " ADP_PROBE_COMPLETED_INT ,ADP probe completed interrupt" "Not occurred,Occurred" newline bitfld.long 0x08 7. " PROBE_RISE_INT ,ADP probe comparator rise detected interrupt" "Not occurred,Occurred" bitfld.long 0x08 6. " SENSE_RISE_INT ,ADP sense comparator rise detected interrupt" "Not occurred,Occurred" bitfld.long 0x08 5. " VBUSVALID_FALL_INT ,Vbusvalid fall detected interrupt" "Not occurred,Occurred" newline bitfld.long 0x08 4. " VBUSVALID_RISE_INT ,Vbusvalid rise detected interrupt" "Not occurred,Occurred" bitfld.long 0x08 3. " OTGSESSVALID_FALL_INT ,Otgsessvalid fall detected interrupt" "Not occurred,Occurred" bitfld.long 0x08 2. " OTGSESSVALID_RISE_INT ,Otgsessvalid rise detected interrupt" "Not occurred,Occurred" newline bitfld.long 0x08 1. " VBUS_ON_FAILED_INT ,Enabling Vbus by A-device has failed interrupt" "Not occurred,Occurred" bitfld.long 0x08 0. " ID_CHANGE_INT ,ID change interrupt" "Not occurred,Occurred" group.long 0x20++0x03 line.long 0x00 "CLK_FREQ,Clock Frequency Register" hexmask.long.word 0x00 16.--31. 1. " CLK_FREQ_KHZ ,Clock frequency KHZ" hexmask.long.word 0x00 0.--15. 1. " CLK_FREQ_MHZ ,Clock frequency MHZ" if (((per.l(ad:0x5B110000+0x24))&0x40000)==0x40000) wgroup.long 0x24++0x03 line.long 0x00 "OTGTMR,OTG Timer Register" bitfld.long 0x00 20. " TIMER_STOP ,Stop timer" "No,Yes" bitfld.long 0x00 19. " TIMER_START ,Start timer" "No,Yes" bitfld.long 0x00 18. " TIMER_WRITE ,Timer value and units write strobe" "No,Yes" newline bitfld.long 0x00 16.--17. " TIMEOUT_UNITS ,Time units" "Hundreds of microseconds,Milliseconds,Tens of milliseconds,Hundreds of milliseconds" hexmask.long.word 0x00 0.--15. 1. " TIMEOUT_VALUE ,Timeout value for timer" else wgroup.long 0x24++0x03 line.long 0x00 "OTGTMR,OTG Timer Register" bitfld.long 0x00 20. " TIMER_STOP ,Stop timer" "No,Yes" bitfld.long 0x00 19. " TIMER_START ,Start timer" "No,Yes" bitfld.long 0x00 18. " TIMER_WRITE ,Timer value and units write strobe" "No,Yes" newline bitfld.long 0x00 16.--17. " TIMEOUT_UNITS ,Time units" "Hundreds of microseconds,Milliseconds,Tens of milliseconds,?..." endif newline rgroup.long 0x30++0x07 line.long 0x00 "OTGVERSION,OTG Version Register" hexmask.long.word 0x00 0.--15. 1. " OTGVERSION ,OTG core revision" line.long 0x04 "OTGCAPABILITY,Capability Register" hexmask.long.word 0x04 20.--31. 1. " OTG3REVISION ,Specifies implemented OTG3.0 specification revision" hexmask.long.word 0x04 8.--19. 1. " OTG2REVISION ,Specifies implemented OTG2.0 specification revision" bitfld.long 0x04 4. " RSP_SUPPORT ,RSP support" "Not supported,Supported" newline bitfld.long 0x04 3. " BC_SUPPORT ,BC support" "Not supported,Supported" bitfld.long 0x04 2. " ADP_SUPPORT ,ADP support" "Not supported,Supported" bitfld.long 0x04 1. " HNP_SUPPORT ,HNP support" "Not supported,Supported" newline bitfld.long 0x04 0. " SRP_SUPPORT ,SRP support" "Not supported,Supported" rgroup.long 0x40++0x03 line.long 0x00 "OTGSIMULATE,OTG Simulate Register" bitfld.long 0x00 0. " OTG_CFG_FAST_SIMS ,Fast simulation timing modes enable" "Disabled,Enabled" newline if (((per.l(ad:0x5B110000+0x58))&0x1000000)==0x1000000) rgroup.long 0x50++0x03 line.long 0x00 "OTGANASTS,OTG Attach Detection Protocol BC Status Register" bitfld.long 0x00 24. " ADP_CHRG_TMOUT_DET ,ADP charge timeout detected" "Not detected,Detected" bitfld.long 0x00 20. " RID_A ,RID A status reg" "0,1" bitfld.long 0x00 19. " RID_B ,RID B status reg" "0,1" bitfld.long 0x00 18. " RID_C ,RID C status reg" "0,1" newline bitfld.long 0x00 17. " RID_GND ,RID GND status reg" "0,1" bitfld.long 0x00 16. " RID_FLOAT ,RID float status reg" "0,1" bitfld.long 0x00 14.--15. " LINESTATE ,Single ended receivers current state" "SE0,J,K,SE1" bitfld.long 0x00 13. " IDDIG ,ID pin status" "Micro-A,Micro-B" newline bitfld.long 0x00 12. " RID_A_COMP_STS ,RID A comparator status" "Not detected,Detected" bitfld.long 0x00 11. " RID_B_COMP_STS ,RID B comparator status" "Not detected,Detected" bitfld.long 0x00 10. " RID_C_COMP_STS ,RID C comparator status" "Not detected,Detected" bitfld.long 0x00 9. " RID_GND_COMP_STS ,RID GND comparator status" "Not detected,Detected" newline bitfld.long 0x00 8. " RID_FLOAT_COMP_STS ,RID FLOAT comparator status" "Not detected,Detected" bitfld.long 0x00 7. " SESSEND ,VBUS valid" "No,Yes" bitfld.long 0x00 6. " ADP_SENSE_ANA ,Output of ADP sense comparator" "<0.2V,>0.55V" bitfld.long 0x00 5. " ADP_PROBE_ANA ,Output of ADP probe comparator" "<0.6V,>0.75V" newline bitfld.long 0x00 4. " OTGSESSVALID ,VBUS voltage level" "<0.8V,>4.0V" bitfld.long 0x00 3. " DCD_COMP_STS ,Data contact detect comparator status" "Asserted,Not asserted" bitfld.long 0x00 2. " DM_VLGC_COMP_STS ,DM to VLGC comparator status" "DMVLGC" bitfld.long 0x00 1. " DM_VDAT_REF_COMP_STS ,DM to VDAT_REF comparator status" "DMVDAT_REF" newline bitfld.long 0x00 0. " DP_VDAT_REF_COMP_STS ,DP to VDAT_REF comparator status" "DPVDAT_REF" else rgroup.long 0x50++0x03 line.long 0x00 "OTGANASTS,OTG Attach Detection Protocol BC Status Register" bitfld.long 0x00 24. " ADP_CHRG_TMOUT_DET ,ADP charge timeout detected" "Not detected,Detected" bitfld.long 0x00 20. " RID_A ,RID A status reg" "0,1" bitfld.long 0x00 19. " RID_B ,RID B status reg" "0,1" bitfld.long 0x00 18. " RID_C ,RID C status reg" "0,1" newline bitfld.long 0x00 17. " RID_GND ,RID GND status reg" "0,1" bitfld.long 0x00 16. " RID_FLOAT ,RID FLOAT status reg" "0,1" bitfld.long 0x00 14.--15. " LINESTATE ,Single ended receivers current state" "SE0,J,K,SE1" newline bitfld.long 0x00 12. " RID_A_COMP_STS ,RID A comparator status" "Not detected,Detected" bitfld.long 0x00 11. " RID_B_COMP_STS ,RID B comparator status" "Not detected,Detected" bitfld.long 0x00 10. " RID_C_COMP_STS ,RID C comparator status" "Not detected,Detected" bitfld.long 0x00 9. " RID_GND_COMP_STS ,RID GND comparator status" "Not detected,Detected" newline bitfld.long 0x00 8. " RID_FLOAT_COMP_STS ,RID FLOAT comparator status" "Not detected,Detected" bitfld.long 0x00 7. " SESSEND ,VBUS valid" "No,Yes" bitfld.long 0x00 6. " ADP_SENSE_ANA ,Output of ADP sense comparator" "<0.2V,>0.55V" bitfld.long 0x00 5. " ADP_PROBE_ANA ,Output of ADP probe comparator" "<0.6V,>0.75V" newline bitfld.long 0x00 4. " OTGSESSVALID ,VBUS voltage level" "<0.8V,>4.0V" bitfld.long 0x00 3. " DCD_COMP_STS ,Data contact detect comparator status" "Asserted,Not asserted" bitfld.long 0x00 2. " DM_VLGC_COMP_STS ,DM to VLGC comparator status" "DMVLGC" bitfld.long 0x00 1. " DM_VDAT_REF_COMP_STS ,DM to VDAT_REF comparator status" "DMVDAT_REF" newline bitfld.long 0x00 0. " DP_VDAT_REF_COMP_STS ,DP to VDAT_REF comparator status" "DPVDAT_REF" endif rgroup.long 0x54++0x03 line.long 0x00 "ADP_RAMP_TIME,Attach Detection Protocol Ramp Time Register" if (((per.l(ad:0x5B110000+0x58))&0x2000000)==0x2000000) group.long 0x58++0x03 line.long 0x00 "OTGCTRL1,OTG Control Register" bitfld.long 0x00 27. " FORCE_OPMODE01 ,Force UTMI opmode" "No,Yes" bitfld.long 0x00 26. " DRIVE_VBUS_STR ,SFR drive_vbus control" "0,1" bitfld.long 0x00 25. " DRIVE_VBUS_SEL ,VBUS drive control select" "OTG,SFR" bitfld.long 0x00 24. " IDPULLUP ,ID pin sample enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " BC_PULLDOWNCTRL ,BC pull-down control" "OTG,DP and DM" bitfld.long 0x00 22. " BC_DPPULLDOWN ,BC DP pull-down enable" "Disabled,Enabled" bitfld.long 0x00 21. " BC_DMPULLDOWN ,BC DM pull-down enable" "Disabled,Enabled" bitfld.long 0x00 20. " RID_NONFLOAT_COMP_EN ,RID non-float comparator enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " RID_FLOAT_COMP_EN ,RID float comparator enable" "Disabled,Enabled" bitfld.long 0x00 18. " DP_VDAT_REF_COMP_EN ,DP to VDAT_REF comparator enable" "Disabled,Enabled" bitfld.long 0x00 17. " DM_VLGC_COMP_EN ,DM to VLGC comparator enable" "Disabled,Enabled" bitfld.long 0x00 16. " DM_VDAT_REF_COMP_EN ,DM to VDAT_REF comparator enable" "Disabled,Enabled" newline bitfld.long 0x00 13. " VDP_SRC_EN ,Voltage source on DP enable" "Disabled,Enabled" bitfld.long 0x00 12. " VDM_SRC_EN ,Voltage source on DM enable" "Disabled,Enabled" bitfld.long 0x00 11. " IDP_SRC_EN ,Current source on DP enable" "Disabled,Enabled" bitfld.long 0x00 10. " IDP_SINK_EN ,Current sink on DP enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " IDM_SINK_EN ,Current sink on DM enable" "Disabled,Enabled" bitfld.long 0x00 8. " BN_EN ,Battery charging circuits master enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADP_AUTO ,ADP mode" "FSM,Software" bitfld.long 0x00 6. " DO_ADP_SNS ,ADP sensing enable in automated mode" "Disabled,Enabled" newline bitfld.long 0x00 5. " DO_ADP_PRB ,ADP probing enable in automated mode" "Disabled,Enabled" bitfld.long 0x00 4. " ADP_SOURCE_CURRENT_EN ,ADP source current enable" "Disabled,Enabled" bitfld.long 0x00 3. " ADP_SINK_CURRENT_EN ,ADP sink current enable" "Disabled,Enabled" bitfld.long 0x00 2. " ADP_SENSE_EN ,Sense mode of ADP enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " ADP_PROBE_EN ,Probe mode of ADP enable" "Disabled,Enabled" bitfld.long 0x00 0. " ADP_EN ,ADP feature enable" "Disabled,Enabled" else group.long 0x58++0x03 line.long 0x00 "OTGCTRL1,OTG Control Register" bitfld.long 0x00 27. " FORCE_OPMODE01 ,Force UTMI opmode" "No,Yes" textfld " " bitfld.long 0x00 25. " DRIVE_VBUS_SEL ,VBUS drive control select" "OTG,SFR" bitfld.long 0x00 24. " IDPULLUP ,ID pin sample enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " BC_PULLDOWNCTRL ,BC pull-down control" "OTG,DP and DM" bitfld.long 0x00 22. " BC_DPPULLDOWN ,BC DP pull-down enable" "Disabled,Enabled" bitfld.long 0x00 21. " BC_DMPULLDOWN ,BC DM pull-down enable" "Disabled,Enabled" bitfld.long 0x00 20. " RID_NONFLOAT_COMP_EN ,RID non-float comparator enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " RID_FLOAT_COMP_EN ,RID float comparator enable" "Disabled,Enabled" bitfld.long 0x00 18. " DP_VDAT_REF_COMP_EN ,DP to VDAT_REF comparator enable" "Disabled,Enabled" bitfld.long 0x00 17. " DM_VLGC_COMP_EN ,DM to VLGC comparator enable" "Disabled,Enabled" bitfld.long 0x00 16. " DM_VDAT_REF_COMP_EN ,DM to VDAT_REF comparator enable" "Disabled,Enabled" newline bitfld.long 0x00 13. " VDP_SRC_EN ,Voltage source on DP enable" "Disabled,Enabled" bitfld.long 0x00 12. " VDM_SRC_EN ,Voltage source on DM enable" "Disabled,Enabled" bitfld.long 0x00 11. " IDP_SRC_EN ,Current source on DP enable" "Disabled,Enabled" bitfld.long 0x00 10. " IDP_SINK_EN ,Current sink on DP enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " IDM_SINK_EN ,Current sink on DM enable" "Disabled,Enabled" bitfld.long 0x00 8. " BN_EN ,Battery charging circuits master enable" "Disabled,Enabled" bitfld.long 0x00 7. " ADP_AUTO ,ADP mode" "FSM,Software" bitfld.long 0x00 6. " DO_ADP_SNS ,ADP sensing enable in automated mode" "Disabled,Enabled" newline bitfld.long 0x00 5. " DO_ADP_PRB ,ADP probing enable in automated mode" "Disabled,Enabled" bitfld.long 0x00 4. " ADP_SOURCE_CURRENT_EN ,ADP source current enable" "Disabled,Enabled" bitfld.long 0x00 3. " ADP_SINK_CURRENT_EN ,ADP sink current enable" "Disabled,Enabled" bitfld.long 0x00 2. " ADP_SENSE_EN ,Sense mode of ADP enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " ADP_PROBE_EN ,Probe mode of ADP enable" "Disabled,Enabled" bitfld.long 0x00 0. " ADP_EN ,ADP feature enable" "Disabled,Enabled" endif group.long 0x5C++0x03 line.long 0x00 "OTGCTRL2,OTG Control Register" hexmask.long.byte 0x00 24.--31. 1. " T_ADP_DSCHG ,ADP probing discharge time" hexmask.long.byte 0x00 16.--23. 1. " ADP_CHRG_TMOUT ,ADP probing timeout value" hexmask.long.byte 0x00 8.--15. 1. " TB_ADP_PRB ,B-device ADP probing period" hexmask.long.byte 0x00 0.--7. 1. " TA_ADP_PRB ,A-device ADP probing period" newline width 22. rgroup.long 0x10000++0x1B line.long 0x00 "HCIVERSION_CAPLENGTH,HCI Version And CAPLENGTH Register" hexmask.long.word 0x00 16.--31. 1. " HCIVERSION ,Host controller interface version number" hexmask.long.byte 0x00 0.--7. 1. " CAPLENGTH ,Capability registers length" line.long 0x04 "HCSPARAMS1,Structural Parameters 1 Register" hexmask.long.byte 0x04 24.--31. 1. " MAXPORTS ,Number of ports" hexmask.long.word 0x04 8.--18. 1. " MAXINTRS ,Number of interrupters" hexmask.long.byte 0x04 0.--7. 1. " MAXSLOTS ,Number of device slots" line.long 0x08 "HCSPARAMS2,Structural Parameters 2 Register" bitfld.long 0x08 27.--31. " MAXSPBUFLO ,Max scratchpad buffers low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 26. " SPR ,Scratchpad restore" "0,1" bitfld.long 0x08 21.--25. " MAXSPBUFHI ,Max scratchpad buffers high" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 4.--7. " ERSTMAX ,Event ring segment table max" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 0.--3. " IST ,Isochronous scheduling threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "HCSPARAMS3,Structural Parameters 3 Register" hexmask.long.word 0x0C 16.--31. 1. " U2DEVEXITLAT ,U2 device exit latency" hexmask.long.byte 0x0C 0.--7. 1. " U1DEVEXITLAT ,U1 device exit latency" line.long 0x10 "HCCPARAMS,Capability Parameters Register" hexmask.long.word 0x10 16.--31. 0x01 " XECP ,XHCI extended capabilities pointer" bitfld.long 0x10 12.--15. " MAXPSASIZE ,Maximum primary stream array size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 9. " SPC ,Stopped - short packet capability" "Not capable,Capable" bitfld.long 0x10 8. " PAE ,Parse all event data" "No,Yes" newline bitfld.long 0x10 7. " NSS ,No secondary SID support" "Supported,Not supported" bitfld.long 0x10 6. " LTC ,Latency tolerance messaging capability" "Not supported,Supported" bitfld.long 0x10 5. " LHRC ,Light HC reset capability" "Not supported,Supported" bitfld.long 0x10 4. " PIND ,Port indicators" "0,1" newline bitfld.long 0x10 3. " PPC ,Port power control" "No,Yes" bitfld.long 0x10 2. " CSZ ,Context size" "32,64" bitfld.long 0x10 1. " BNC ,BW negotiation capability" "Not implemented,Implemented" bitfld.long 0x10 0. " AC64 ,64-bit addressing capability" "32,64" line.long 0x14 "DBOFF,DoorBell Array Offset Register" hexmask.long 0x14 2.--31. 0x04 " DAO ,Doorbell array offset" line.long 0x18 "RTSOFF,XHCI Runtime Registers Offset" hexmask.long 0x18 5.--31. 0x20 " RRSO ,Runtime register space offset" newline width 15. group.long 0x10080++0x07 line.long 0x00 "USBCMD,USB Command Register" bitfld.long 0x00 11. " EU3S ,Enable U3 MFINDEX stop" "Disabled,Enabled" bitfld.long 0x00 10. " EWE ,Enable wrap event" "Disabled,Enabled" bitfld.long 0x00 9. " CRS ,Controller restore state" "0,1" bitfld.long 0x00 8. " CSS ,Controller save state" "0,1" newline rbitfld.long 0x00 7. " LHCRST ,Light host controller reset" "0,1" bitfld.long 0x00 3. " HSEE ,Host system error enable" "Disabled,Enabled" bitfld.long 0x00 2. " INTE ,Interrupter enable" "Disabled,Enabled" bitfld.long 0x00 1. " HCRST ,Host controller reset" "No reset,Reset" newline bitfld.long 0x00 0. " R_S ,Run/Stop" "Stopped,Running" line.long 0x04 "USBSTS,USB Status Register" rbitfld.long 0x04 12. " HCE ,Host controller error" "Not occurred,Occurred" rbitfld.long 0x04 11. " CNR ,Controller not ready" "Ready,Not ready" eventfld.long 0x04 10. " SRE ,Save/Restore error" "Not occurred,Occurred" rbitfld.long 0x04 9. " RSS ,Restore state status" "Not restored,Restored" newline rbitfld.long 0x04 8. " SSS ,Save state status" "Not saved,Saved" eventfld.long 0x04 4. " PCD ,Port change detect" "Not detected,Detected" eventfld.long 0x04 3. " EINT ,Event interrupt" "No interrupt,Interrupt" eventfld.long 0x04 2. " HSE ,Host system error" "No error,Error" newline rbitfld.long 0x04 0. " HCH ,HC halted" "Not halted,Halted" rgroup.long 0x10088++0x03 line.long 0x00 "PAGESIZE,Page Size Register" hexmask.long.word 0x00 0.--15. 1. " PAGESIZE ,Page size" group.long 0x10094++0x0B line.long 0x00 "DNCTRL,Device Notification Control Register" bitfld.long 0x00 15. " N15 ,Notification enable flag 15" "Disabled,Enabled" bitfld.long 0x00 14. " N14 ,Notification enable flag 14" "Disabled,Enabled" bitfld.long 0x00 13. " N13 ,Notification enable flag 13" "Disabled,Enabled" bitfld.long 0x00 12. " N12 ,Notification enable flag 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " N11 ,Notification enable flag 11" "Disabled,Enabled" bitfld.long 0x00 10. " N10 ,Notification enable flag 10" "Disabled,Enabled" bitfld.long 0x00 9. " N9 ,Notification enable flag 9" "Disabled,Enabled" bitfld.long 0x00 8. " N8 ,Notification enable flag 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " N7 ,Notification enable flag 7" "Disabled,Enabled" bitfld.long 0x00 6. " N6 ,Notification enable flag 6" "Disabled,Enabled" bitfld.long 0x00 5. " N5 ,Notification enable flag 5" "Disabled,Enabled" bitfld.long 0x00 4. " N4 ,Notification enable flag 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " N3 ,Notification enable flag 3" "Disabled,Enabled" bitfld.long 0x00 2. " N2 ,Notification enable flag 2" "Disabled,Enabled" bitfld.long 0x00 1. " N1 ,Notification enable flag 1" "Disabled,Enabled" bitfld.long 0x00 0. " N0 ,Notification enable flag 0" "Disabled,Enabled" line.long 0x04 "CRCR_LO,Command Ring Control Register Low" hexmask.long 0x04 6.--31. 0x40 " CRPTR_L ,Command ring pointer low" rbitfld.long 0x04 3. " CRR ,Command ring running" "0,1" bitfld.long 0x04 2. " CA ,Command abort" "0,1" bitfld.long 0x04 1. " CS ,Command abort" "0,1" newline bitfld.long 0x04 0. " RCS ,Ring cycle state" "0,1" line.long 0x08 "CRCR_HI,Command Ring Control Register High" group.long 0x100B0++0x0B line.long 0x00 "DCBAAP_LO,Device Context Base Address Array Pointer(LOW)" hexmask.long 0x00 6.--31. 0x40 " DCBAAPTR_L ,Device context base address array pointer" line.long 0x04 "DCBAAP_HI,Device Context Base Address Array Pointer (HIGH)" line.long 0x08 "CONFIG,Configure Register" hexmask.long.byte 0x08 0.--7. 1. " MAXSLOTSEN ,Max device slot enabled" newline if (((per.l(ad:0x5B110000+0x10480))&0x200)==0x200) group.long 0x10480++0x03 line.long 0x00 "PORTSC1USB2,USB2 Port Status And Control Register" rbitfld.long 0x00 30. " DR ,Device removable" "Yes,No" bitfld.long 0x00 27. " WOE ,Wake on over-current enable" "Disabled,Enabled" bitfld.long 0x00 26. " WDE ,Wake on disconnect enable" "Disabled,Enabled" bitfld.long 0x00 25. " WCE ,Wake on connect enable" "Disabled,Enabled" newline rbitfld.long 0x00 24. " CAS ,Cold attach status" "0,1" eventfld.long 0x00 22. " PLC ,Port link state change" "No,Yes" eventfld.long 0x00 21. " PRC ,Port reset change" "No,Yes" eventfld.long 0x00 20. " OCC ,Over-current change" "No,Yes" newline eventfld.long 0x00 18. " PEC ,Port enabled/disabled change" "No,Yes" eventfld.long 0x00 17. " CSC ,Connect status change" "No,Yes" bitfld.long 0x00 16. " LWS ,Port link state write strobe" "0,1" bitfld.long 0x00 14.--15. " PIC ,Port indicator control" "OFF,Amber,Green,?..." newline rbitfld.long 0x00 10.--13. " PORTSPEED ,Port speed" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 9. " PP ,Port power" "0,1" bitfld.long 0x00 5.--8. " PLS ,Port link state" "U0,U1,U2,U3,Disabled,RxDetect,Inactive,Polling,Recovery,Hot reset,Compliance mode,Test mode,,,,Resume" bitfld.long 0x00 4. " PR ,Port reset" "No reset,Reset" newline rbitfld.long 0x00 3. " OCA ,Over-current active" "No,Yes" eventfld.long 0x00 1. " PED ,Port enabled/disabled" "Disabled,Enabled" rbitfld.long 0x00 0. " CCS ,Current connect status" "Disconnected,Connected" else group.long 0x10480++0x03 line.long 0x00 "PORTSC1USB2,USB2 Port Status And Control Register" rbitfld.long 0x00 30. " DR ,Device removable" "Yes,No" bitfld.long 0x00 27. " WOE ,Wake on over-current enable" "Disabled,Enabled" bitfld.long 0x00 26. " WDE ,Wake on disconnect enable" "Disabled,Enabled" bitfld.long 0x00 25. " WCE ,Wake on connect enable" "Disabled,Enabled" newline rbitfld.long 0x00 24. " CAS ,Cold attach status" "0,1" eventfld.long 0x00 22. " PLC ,Port link state change" "No,Yes" eventfld.long 0x00 21. " PRC ,Port reset change" "No,Yes" eventfld.long 0x00 20. " OCC ,Over-current change" "No,Yes" newline eventfld.long 0x00 18. " PEC ,Port enabled/disabled change" "No,Yes" eventfld.long 0x00 17. " CSC ,Connect status change" "No,Yes" bitfld.long 0x00 16. " LWS ,Port link state write strobe" "0,1" bitfld.long 0x00 14.--15. " PIC ,Port indicator control" "OFF,Amber,Green,?..." newline rbitfld.long 0x00 10.--13. " PORTSPEED ,Port speed" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 9. " PP ,Port power" "0,1" textfld " " bitfld.long 0x00 4. " PR ,Port reset" "No reset,Reset" newline rbitfld.long 0x00 3. " OCA ,Over-current active" "No,Yes" eventfld.long 0x00 1. " PED ,Port enabled/disabled" "Disabled,Enabled" rbitfld.long 0x00 0. " CCS ,Current connect status" "Disconnected,Connected" endif if (((per.l(ad:0x5B110000+0x10480))&0x1E0)==0x80) if (((per.l(ad:0x5B110000+0x18048))&0x80000)==0x80000) group.long 0x10484++0x03 line.long 0x00 "PORTPMSC1USB2,USB2 Port Power Management Status And Control Register" bitfld.long 0x00 28.--31. " PTC ,Port test control" "Disabled,J_STATE,K_STATE,SE0_NAK,FORCE_ENABLE,,,,,,,,,,,Error" bitfld.long 0x00 16. " HLE ,Hardware LPM enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--15. 1. " L1DS ,L1 device slot" bitfld.long 0x00 4.--7. " BESL ,Best effort service latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. " RWE ,Remote wake enabled" "Disabled,Enabled" bitfld.long 0x00 0.--2. " L1S ,L1 status" ",Success,Not yet,Not supported,Timeout/error,?..." else group.long 0x10484++0x03 line.long 0x00 "PORTPMSC1USB2,USB2 Port Power Management Status And Control Register" bitfld.long 0x00 28.--31. " PTC ,Port test control" "Disabled,J_STATE,K_STATE,SE0_NAK,FORCE_ENABLE,,,,,,,,,,,Error" textfld " " hexmask.long.byte 0x00 8.--15. 1. " L1DS ,L1 device slot" bitfld.long 0x00 4.--7. " BESL ,Best effort service latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. " RWE ,Remote wake enabled" "Disabled,Enabled" bitfld.long 0x00 0.--2. " L1S ,L1 status" ",Success,Not yet,Not supported,Timeout/error,?..." endif else if (((per.l(ad:0x5B110000+0x18048))&0x80000)==0x80000) group.long 0x10484++0x03 line.long 0x00 "PORTPMSC1USB2,USB2 Port Power Management Status And Control Register" bitfld.long 0x00 28.--31. " PTC ,Port test control" "Disabled,?..." bitfld.long 0x00 16. " HLE ,Hardware LPM enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--15. 1. " L1DS ,L1 device slot" bitfld.long 0x00 4.--7. " BESL ,Best effort service latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. " RWE ,Remote wake enabled" "Disabled,Enabled" bitfld.long 0x00 0.--2. " L1S ,L1 status" ",Success,Not yet,Not supported,Timeout/error,?..." else group.long 0x10484++0x03 line.long 0x00 "PORTPMSC1USB2,USB2 Port Power Management Status And Control Register" bitfld.long 0x00 28.--31. " PTC ,Port test control" "Disabled,?..." textfld " " hexmask.long.byte 0x00 8.--15. 1. " L1DS ,L1 device slot" bitfld.long 0x00 4.--7. " BESL ,Best effort service latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. " RWE ,Remote wake enabled" "Disabled,Enabled" bitfld.long 0x00 0.--2. " L1S ,L1 status" ",Success,Not yet,Not supported,Timeout/error,?..." endif endif group.long 0x1048C++0x03 line.long 0x00 "PORT1HLPMC,USB2 Port Hardware LPM Control Register" bitfld.long 0x00 10.--13. " BESLD ,Best effort service latency deep" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 2.--9. 0x04 " L1_TIMEOUT ,L1 timeout" bitfld.long 0x00 0.--1. " HIRDM ,Host initiated resume duration mode" "BESL,BESL/BESLD,?..." if (((per.l(ad:0x5B110000+0x10490))&0x200)==0x200) group.long 0x10490++0x03 line.long 0x00 "PORTSC1USB3,USB3 Port Status And Control Register" bitfld.long 0x00 31. " WPR ,Warm port reset" "No,Yes" rbitfld.long 0x00 30. " DR ,Device removable" "Yes,No" bitfld.long 0x00 27. " WOE ,Wake on over-current enable" "Disabled,Enabled" bitfld.long 0x00 26. " WDE ,Wake on disconnect enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " WCE ,Wake on connect enable" "Disabled,Enabled" rbitfld.long 0x00 24. " CAS ,Cold attach status" "0,1" eventfld.long 0x00 23. " CEC ,Port config error change" "No,Yes" eventfld.long 0x00 22. " PLC ,Port link state change" "No,Yes" newline eventfld.long 0x00 21. " PRC ,Port reset change" "No,Yes" eventfld.long 0x00 20. " OOC ,Over-current change" "No,Yes" eventfld.long 0x00 19. " WRC ,Warm port reset change" "No,Yes" eventfld.long 0x00 18. " PEC ,Port enabled/disabled change" "No,Yes" newline eventfld.long 0x00 17. " CSC ,Connect status change" "No,Yes" bitfld.long 0x00 16. " LWS ,Port link state write strobe" "0,1" bitfld.long 0x00 14.--15. " PIC ,Port indicator control" "OFF,Amber,Green,?..." bitfld.long 0x00 10.--13. " PORTSPEED ,Port speed" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 9. " PP ,Port power" "0,1" bitfld.long 0x00 5.--8. " PLS ,Port link state" "U0,U1,U2,U3,Disabled,RxDetect,Inactive,Polling,Recovery,Hot reset,Compliance mode,Test mode,,,,Resume" bitfld.long 0x00 4. " PR ,Port reset" "No,Yes" rbitfld.long 0x00 3. " OCA ,Over-current active" "No,Yes" newline eventfld.long 0x00 1. " PED ,Port enabled/disabled" "Disabled,Enabled" rbitfld.long 0x00 0. " CCS ,Current connect status" "Disconnected,Connected" else group.long 0x10490++0x03 line.long 0x00 "PORTSC1USB3,USB3 Port Status And Control Register" bitfld.long 0x00 31. " WPR ,Warm port reset" "No,Yes" rbitfld.long 0x00 30. " DR ,Device removable" "Yes,No" bitfld.long 0x00 27. " WOE ,Wake on over-current enable" "Disabled,Enabled" bitfld.long 0x00 26. " WDE ,Wake on disconnect enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " WCE ,Wake on connect enable" "Disabled,Enabled" rbitfld.long 0x00 24. " CAS ,Cold attach status" "0,1" eventfld.long 0x00 23. " CEC ,Port config error change" "No,Yes" eventfld.long 0x00 22. " PLC ,Port link state change" "No,Yes" newline eventfld.long 0x00 21. " PRC ,Port reset change" "No,Yes" eventfld.long 0x00 20. " OOC ,Over-current change" "No,Yes" eventfld.long 0x00 19. " WRC ,Warm port reset change" "No,Yes" eventfld.long 0x00 18. " PEC ,Port enabled/disabled change" "No,Yes" newline eventfld.long 0x00 17. " CSC ,Connect status change" "No,Yes" bitfld.long 0x00 16. " LWS ,Port link state write strobe" "0,1" bitfld.long 0x00 14.--15. " PIC ,Port indicator control" "OFF,Amber,Green,?..." bitfld.long 0x00 10.--13. " PORTSPEED ,Port speed" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 9. " PP ,Port power" "0,1" textfld " " bitfld.long 0x00 4. " PR ,Port reset" "No,Yes" rbitfld.long 0x00 3. " OCA ,Over-current active" "No,Yes" newline eventfld.long 0x00 1. " PED ,Port enabled/disabled" "Disabled,Enabled" rbitfld.long 0x00 0. " CCS ,Current connect status" "Disconnected,Connected" endif group.long 0x10494++0x03 line.long 0x00 "PORTPMSC1USB3,USB3 Port Power Management Status And Control Register" bitfld.long 0x00 16. " FLA ,Force link PM accept" "No,Yes" hexmask.long.byte 0x00 8.--15. 1. " U2_TIMEOUT ,U2 timeout" hexmask.long.byte 0x00 0.--7. 1. " U1_TIMEOUT ,U1 timeout" rgroup.long 0x10498++0x03 line.long 0x00 "PORTLI1,USB3 Port Link Info Register" hexmask.long.word 0x00 0.--15. 1. " LEC ,Link error count" rgroup.long 0x12000++0x03 line.long 0x00 "MFINDEX,MicroFrame Index Register" hexmask.long.word 0x00 0.--13. 1. " MFINDEX ,Microframe index" newline group.long 0x12020++0x0B line.long 0x00 "IMAN0,Interrupter Management 0 Register" bitfld.long 0x00 1. " IE ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " IP ,Interrupt pending" "Not pending,Pending" line.long 0x04 "IMOD0,Interrupter Moderation 0 Register" hexmask.long.word 0x04 16.--31. 1. " IMODC ,Interrupt moderation counter" hexmask.long.word 0x04 0.--15. 1. " IMODI ,Interrupt moderation interval" line.long 0x08 "ERSTSZ0,Event Ring Segment Table Size 0 Register" hexmask.long.word 0x08 0.--15. 1. " ERSTS ,Event ring segment table size" if ((per.l(ad:0x5B110000+0x10000+0x84)&0x01)==0x01) group.long (0x12020+0x10)++0x07 line.long 0x00 "ERSTBA00_LO,Event Ring Segment Table Base Address Low 0" hexmask.long 0x00 6.--31. 0x40 " ERSTBADDR_LO ,Event ring segment table base address register" line.long 0x04 "ERSTBA00_HI,Event Ring Segment Table Base Address High 0" else rgroup.long (0x12020+0x10)++0x07 line.long 0x00 "ERSTBA00_LO,Event Ring Segment Table Base Address Low 0" hexmask.long 0x00 6.--31. 0x40 " ERSTBADDR_LO ,Event ring segment table base address register" line.long 0x04 "ERSTBA00_HI,Event Ring Segment Table Base Address High 0" endif group.long (0x12020+0x18)++0x07 line.long 0x00 "ERDP0_LO,Event Ring Dequeue Pointer Low Register 0" hexmask.long 0x00 4.--31. 0x10 " ERDPTR ,Event ring dequeue pointer" eventfld.long 0x00 3. " EHB ,Event handler busy" "Not busy,Busy" bitfld.long 0x00 0.--2. " DESI ,Dequeue ERST segment index" "0,1,2,3,4,5,6,7" line.long 0x04 "ERDP0_HI,Event Ring Dequeue Pointer HIGH Register 0" group.long 0x12040++0x0B line.long 0x00 "IMAN1,Interrupter Management 1 Register" bitfld.long 0x00 1. " IE ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " IP ,Interrupt pending" "Not pending,Pending" line.long 0x04 "IMOD1,Interrupter Moderation 1 Register" hexmask.long.word 0x04 16.--31. 1. " IMODC ,Interrupt moderation counter" hexmask.long.word 0x04 0.--15. 1. " IMODI ,Interrupt moderation interval" line.long 0x08 "ERSTSZ1,Event Ring Segment Table Size 1 Register" hexmask.long.word 0x08 0.--15. 1. " ERSTS ,Event ring segment table size" if ((per.l(ad:0x5B110000+0x10000+0x84)&0x01)==0x01) group.long (0x12040+0x10)++0x07 line.long 0x00 "ERSTBA01_LO,Event Ring Segment Table Base Address Low 1" hexmask.long 0x00 6.--31. 0x40 " ERSTBADDR_LO ,Event ring segment table base address register" line.long 0x04 "ERSTBA01_HI,Event Ring Segment Table Base Address High 1" else rgroup.long (0x12040+0x10)++0x07 line.long 0x00 "ERSTBA01_LO,Event Ring Segment Table Base Address Low 1" hexmask.long 0x00 6.--31. 0x40 " ERSTBADDR_LO ,Event ring segment table base address register" line.long 0x04 "ERSTBA01_HI,Event Ring Segment Table Base Address High 1" endif group.long (0x12040+0x18)++0x07 line.long 0x00 "ERDP1_LO,Event Ring Dequeue Pointer Low Register 1" hexmask.long 0x00 4.--31. 0x10 " ERDPTR ,Event ring dequeue pointer" eventfld.long 0x00 3. " EHB ,Event handler busy" "Not busy,Busy" bitfld.long 0x00 0.--2. " DESI ,Dequeue ERST segment index" "0,1,2,3,4,5,6,7" line.long 0x04 "ERDP1_HI,Event Ring Dequeue Pointer HIGH Register 1" group.long 0x12060++0x0B line.long 0x00 "IMAN2,Interrupter Management 2 Register" bitfld.long 0x00 1. " IE ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " IP ,Interrupt pending" "Not pending,Pending" line.long 0x04 "IMOD2,Interrupter Moderation 2 Register" hexmask.long.word 0x04 16.--31. 1. " IMODC ,Interrupt moderation counter" hexmask.long.word 0x04 0.--15. 1. " IMODI ,Interrupt moderation interval" line.long 0x08 "ERSTSZ2,Event Ring Segment Table Size 2 Register" hexmask.long.word 0x08 0.--15. 1. " ERSTS ,Event ring segment table size" if ((per.l(ad:0x5B110000+0x10000+0x84)&0x01)==0x01) group.long (0x12060+0x10)++0x07 line.long 0x00 "ERSTBA02_LO,Event Ring Segment Table Base Address Low 2" hexmask.long 0x00 6.--31. 0x40 " ERSTBADDR_LO ,Event ring segment table base address register" line.long 0x04 "ERSTBA02_HI,Event Ring Segment Table Base Address High 2" else rgroup.long (0x12060+0x10)++0x07 line.long 0x00 "ERSTBA02_LO,Event Ring Segment Table Base Address Low 2" hexmask.long 0x00 6.--31. 0x40 " ERSTBADDR_LO ,Event ring segment table base address register" line.long 0x04 "ERSTBA02_HI,Event Ring Segment Table Base Address High 2" endif group.long (0x12060+0x18)++0x07 line.long 0x00 "ERDP2_LO,Event Ring Dequeue Pointer Low Register 2" hexmask.long 0x00 4.--31. 0x10 " ERDPTR ,Event ring dequeue pointer" eventfld.long 0x00 3. " EHB ,Event handler busy" "Not busy,Busy" bitfld.long 0x00 0.--2. " DESI ,Dequeue ERST segment index" "0,1,2,3,4,5,6,7" line.long 0x04 "ERDP2_HI,Event Ring Dequeue Pointer HIGH Register 2" group.long 0x12080++0x0B line.long 0x00 "IMAN3,Interrupter Management 3 Register" bitfld.long 0x00 1. " IE ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " IP ,Interrupt pending" "Not pending,Pending" line.long 0x04 "IMOD3,Interrupter Moderation 3 Register" hexmask.long.word 0x04 16.--31. 1. " IMODC ,Interrupt moderation counter" hexmask.long.word 0x04 0.--15. 1. " IMODI ,Interrupt moderation interval" line.long 0x08 "ERSTSZ3,Event Ring Segment Table Size 3 Register" hexmask.long.word 0x08 0.--15. 1. " ERSTS ,Event ring segment table size" if ((per.l(ad:0x5B110000+0x10000+0x84)&0x01)==0x01) group.long (0x12080+0x10)++0x07 line.long 0x00 "ERSTBA03_LO,Event Ring Segment Table Base Address Low 3" hexmask.long 0x00 6.--31. 0x40 " ERSTBADDR_LO ,Event ring segment table base address register" line.long 0x04 "ERSTBA03_HI,Event Ring Segment Table Base Address High 3" else rgroup.long (0x12080+0x10)++0x07 line.long 0x00 "ERSTBA03_LO,Event Ring Segment Table Base Address Low 3" hexmask.long 0x00 6.--31. 0x40 " ERSTBADDR_LO ,Event ring segment table base address register" line.long 0x04 "ERSTBA03_HI,Event Ring Segment Table Base Address High 3" endif group.long (0x12080+0x18)++0x07 line.long 0x00 "ERDP3_LO,Event Ring Dequeue Pointer Low Register 3" hexmask.long 0x00 4.--31. 0x10 " ERDPTR ,Event ring dequeue pointer" eventfld.long 0x00 3. " EHB ,Event handler busy" "Not busy,Busy" bitfld.long 0x00 0.--2. " DESI ,Dequeue ERST segment index" "0,1,2,3,4,5,6,7" line.long 0x04 "ERDP3_HI,Event Ring Dequeue Pointer HIGH Register 3" group.long 0x120A0++0x0B line.long 0x00 "IMAN4,Interrupter Management 4 Register" bitfld.long 0x00 1. " IE ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " IP ,Interrupt pending" "Not pending,Pending" line.long 0x04 "IMOD4,Interrupter Moderation 4 Register" hexmask.long.word 0x04 16.--31. 1. " IMODC ,Interrupt moderation counter" hexmask.long.word 0x04 0.--15. 1. " IMODI ,Interrupt moderation interval" line.long 0x08 "ERSTSZ4,Event Ring Segment Table Size 4 Register" hexmask.long.word 0x08 0.--15. 1. " ERSTS ,Event ring segment table size" if ((per.l(ad:0x5B110000+0x10000+0x84)&0x01)==0x01) group.long (0x120A0+0x10)++0x07 line.long 0x00 "ERSTBA04_LO,Event Ring Segment Table Base Address Low 4" hexmask.long 0x00 6.--31. 0x40 " ERSTBADDR_LO ,Event ring segment table base address register" line.long 0x04 "ERSTBA04_HI,Event Ring Segment Table Base Address High 4" else rgroup.long (0x120A0+0x10)++0x07 line.long 0x00 "ERSTBA04_LO,Event Ring Segment Table Base Address Low 4" hexmask.long 0x00 6.--31. 0x40 " ERSTBADDR_LO ,Event ring segment table base address register" line.long 0x04 "ERSTBA04_HI,Event Ring Segment Table Base Address High 4" endif group.long (0x120A0+0x18)++0x07 line.long 0x00 "ERDP4_LO,Event Ring Dequeue Pointer Low Register 4" hexmask.long 0x00 4.--31. 0x10 " ERDPTR ,Event ring dequeue pointer" eventfld.long 0x00 3. " EHB ,Event handler busy" "Not busy,Busy" bitfld.long 0x00 0.--2. " DESI ,Dequeue ERST segment index" "0,1,2,3,4,5,6,7" line.long 0x04 "ERDP4_HI,Event Ring Dequeue Pointer HIGH Register 4" group.long 0x120C0++0x0B line.long 0x00 "IMAN5,Interrupter Management 5 Register" bitfld.long 0x00 1. " IE ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " IP ,Interrupt pending" "Not pending,Pending" line.long 0x04 "IMOD5,Interrupter Moderation 5 Register" hexmask.long.word 0x04 16.--31. 1. " IMODC ,Interrupt moderation counter" hexmask.long.word 0x04 0.--15. 1. " IMODI ,Interrupt moderation interval" line.long 0x08 "ERSTSZ5,Event Ring Segment Table Size 5 Register" hexmask.long.word 0x08 0.--15. 1. " ERSTS ,Event ring segment table size" if ((per.l(ad:0x5B110000+0x10000+0x84)&0x01)==0x01) group.long (0x120C0+0x10)++0x07 line.long 0x00 "ERSTBA05_LO,Event Ring Segment Table Base Address Low 5" hexmask.long 0x00 6.--31. 0x40 " ERSTBADDR_LO ,Event ring segment table base address register" line.long 0x04 "ERSTBA05_HI,Event Ring Segment Table Base Address High 5" else rgroup.long (0x120C0+0x10)++0x07 line.long 0x00 "ERSTBA05_LO,Event Ring Segment Table Base Address Low 5" hexmask.long 0x00 6.--31. 0x40 " ERSTBADDR_LO ,Event ring segment table base address register" line.long 0x04 "ERSTBA05_HI,Event Ring Segment Table Base Address High 5" endif group.long (0x120C0+0x18)++0x07 line.long 0x00 "ERDP5_LO,Event Ring Dequeue Pointer Low Register 5" hexmask.long 0x00 4.--31. 0x10 " ERDPTR ,Event ring dequeue pointer" eventfld.long 0x00 3. " EHB ,Event handler busy" "Not busy,Busy" bitfld.long 0x00 0.--2. " DESI ,Dequeue ERST segment index" "0,1,2,3,4,5,6,7" line.long 0x04 "ERDP5_HI,Event Ring Dequeue Pointer HIGH Register 5" group.long 0x120E0++0x0B line.long 0x00 "IMAN6,Interrupter Management 6 Register" bitfld.long 0x00 1. " IE ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " IP ,Interrupt pending" "Not pending,Pending" line.long 0x04 "IMOD6,Interrupter Moderation 6 Register" hexmask.long.word 0x04 16.--31. 1. " IMODC ,Interrupt moderation counter" hexmask.long.word 0x04 0.--15. 1. " IMODI ,Interrupt moderation interval" line.long 0x08 "ERSTSZ6,Event Ring Segment Table Size 6 Register" hexmask.long.word 0x08 0.--15. 1. " ERSTS ,Event ring segment table size" if ((per.l(ad:0x5B110000+0x10000+0x84)&0x01)==0x01) group.long (0x120E0+0x10)++0x07 line.long 0x00 "ERSTBA06_LO,Event Ring Segment Table Base Address Low 6" hexmask.long 0x00 6.--31. 0x40 " ERSTBADDR_LO ,Event ring segment table base address register" line.long 0x04 "ERSTBA06_HI,Event Ring Segment Table Base Address High 6" else rgroup.long (0x120E0+0x10)++0x07 line.long 0x00 "ERSTBA06_LO,Event Ring Segment Table Base Address Low 6" hexmask.long 0x00 6.--31. 0x40 " ERSTBADDR_LO ,Event ring segment table base address register" line.long 0x04 "ERSTBA06_HI,Event Ring Segment Table Base Address High 6" endif group.long (0x120E0+0x18)++0x07 line.long 0x00 "ERDP6_LO,Event Ring Dequeue Pointer Low Register 6" hexmask.long 0x00 4.--31. 0x10 " ERDPTR ,Event ring dequeue pointer" eventfld.long 0x00 3. " EHB ,Event handler busy" "Not busy,Busy" bitfld.long 0x00 0.--2. " DESI ,Dequeue ERST segment index" "0,1,2,3,4,5,6,7" line.long 0x04 "ERDP6_HI,Event Ring Dequeue Pointer HIGH Register 6" group.long 0x12100++0x0B line.long 0x00 "IMAN7,Interrupter Management 7 Register" bitfld.long 0x00 1. " IE ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " IP ,Interrupt pending" "Not pending,Pending" line.long 0x04 "IMOD7,Interrupter Moderation 7 Register" hexmask.long.word 0x04 16.--31. 1. " IMODC ,Interrupt moderation counter" hexmask.long.word 0x04 0.--15. 1. " IMODI ,Interrupt moderation interval" line.long 0x08 "ERSTSZ7,Event Ring Segment Table Size 7 Register" hexmask.long.word 0x08 0.--15. 1. " ERSTS ,Event ring segment table size" if ((per.l(ad:0x5B110000+0x10000+0x84)&0x01)==0x01) group.long (0x12100+0x10)++0x07 line.long 0x00 "ERSTBA07_LO,Event Ring Segment Table Base Address Low 7" hexmask.long 0x00 6.--31. 0x40 " ERSTBADDR_LO ,Event ring segment table base address register" line.long 0x04 "ERSTBA07_HI,Event Ring Segment Table Base Address High 7" else rgroup.long (0x12100+0x10)++0x07 line.long 0x00 "ERSTBA07_LO,Event Ring Segment Table Base Address Low 7" hexmask.long 0x00 6.--31. 0x40 " ERSTBADDR_LO ,Event ring segment table base address register" line.long 0x04 "ERSTBA07_HI,Event Ring Segment Table Base Address High 7" endif group.long (0x12100+0x18)++0x07 line.long 0x00 "ERDP7_LO,Event Ring Dequeue Pointer Low Register 7" hexmask.long 0x00 4.--31. 0x10 " ERDPTR ,Event ring dequeue pointer" eventfld.long 0x00 3. " EHB ,Event handler busy" "Not busy,Busy" bitfld.long 0x00 0.--2. " DESI ,Dequeue ERST segment index" "0,1,2,3,4,5,6,7" line.long 0x04 "ERDP7_HI,Event Ring Dequeue Pointer HIGH Register 7" width 6. tree "Doorbell Registers" group.long 0x13000++0x03 line.long 0x00 "DB0,Doorbell Array 0 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" group.long 0x13004++0x03 line.long 0x00 "DB1,Doorbell Array 1 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" group.long 0x13008++0x03 line.long 0x00 "DB2,Doorbell Array 2 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" group.long 0x1300C++0x03 line.long 0x00 "DB3,Doorbell Array 3 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" group.long 0x13010++0x03 line.long 0x00 "DB4,Doorbell Array 4 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" group.long 0x13014++0x03 line.long 0x00 "DB5,Doorbell Array 5 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" group.long 0x13018++0x03 line.long 0x00 "DB6,Doorbell Array 6 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" group.long 0x1301C++0x03 line.long 0x00 "DB7,Doorbell Array 7 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" group.long 0x13020++0x03 line.long 0x00 "DB8,Doorbell Array 8 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" group.long 0x13024++0x03 line.long 0x00 "DB9,Doorbell Array 9 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" group.long 0x13028++0x03 line.long 0x00 "DB10,Doorbell Array 10 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" group.long 0x1302C++0x03 line.long 0x00 "DB11,Doorbell Array 11 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" group.long 0x13030++0x03 line.long 0x00 "DB12,Doorbell Array 12 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" group.long 0x13034++0x03 line.long 0x00 "DB13,Doorbell Array 13 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" group.long 0x13038++0x03 line.long 0x00 "DB14,Doorbell Array 14 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" group.long 0x1303C++0x03 line.long 0x00 "DB15,Doorbell Array 15 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" group.long 0x13040++0x03 line.long 0x00 "DB16,Doorbell Array 16 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" group.long 0x13044++0x03 line.long 0x00 "DB17,Doorbell Array 17 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" group.long 0x13048++0x03 line.long 0x00 "DB18,Doorbell Array 18 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" group.long 0x1304C++0x03 line.long 0x00 "DB19,Doorbell Array 19 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" group.long 0x13050++0x03 line.long 0x00 "DB20,Doorbell Array 20 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" group.long 0x13054++0x03 line.long 0x00 "DB21,Doorbell Array 21 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" group.long 0x13058++0x03 line.long 0x00 "DB22,Doorbell Array 22 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" group.long 0x1305C++0x03 line.long 0x00 "DB23,Doorbell Array 23 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" group.long 0x13060++0x03 line.long 0x00 "DB24,Doorbell Array 24 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" group.long 0x13064++0x03 line.long 0x00 "DB25,Doorbell Array 25 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" group.long 0x13068++0x03 line.long 0x00 "DB26,Doorbell Array 26 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" group.long 0x1306C++0x03 line.long 0x00 "DB27,Doorbell Array 27 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" group.long 0x13070++0x03 line.long 0x00 "DB28,Doorbell Array 28 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" group.long 0x13074++0x03 line.long 0x00 "DB29,Doorbell Array 29 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" group.long 0x13078++0x03 line.long 0x00 "DB30,Doorbell Array 30 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" group.long 0x1307C++0x03 line.long 0x00 "DB31,Doorbell Array 31 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" group.long 0x13080++0x03 line.long 0x00 "DB32,Doorbell Array 32 Register" hexmask.long.word 0x00 16.--31. 1. " DB_STREAM_ID ,Doorbell stream ID" hexmask.long.byte 0x00 0.--7. 1. " DB_TARGET ,Doorbell target" tree.end newline width 30. tree "XECP Registers" group.long 0x18008++0x07 line.long 0x00 "CDNS_DEBUG_BUS_CAP,XHCI Debug Bus Capability Register" bitfld.long 0x00 31. " CPU_DEBUG_EN ,Debug bus enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--15. 0x01 " XHCI_DEBUG_BUS_DW ,Next capability pointer" newline hexmask.long.byte 0x00 0.--7. 1. " XHCI_DEBUG_BUS_CAP_ID ,Capability ID" line.long 0x04 "CDNS_DEBUG_BUS_CTRL,XHCI Debug Bus Control Register" bitfld.long 0x04 0.--4. " CPU_DEBUG_BUS_SEL ,Debug bus select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x18010++0x03 line.long 0x00 "CDNS_DEBUG_BUS_STATUS,XHCI Debug Bus Status Register" group.long 0x18014++0x07 line.long 0x00 "PM_CAP,Extended Power Management Capability Register" rbitfld.long 0x00 31. " PME_SUPPORT[4] ,Assert PME from D3COLD support" "Not asserted,Asserted" rbitfld.long 0x00 30. " [3] ,Assert PME from D3HOT support" "Not supported,Supported" newline rbitfld.long 0x00 29. " [2] ,Assert PME from D2 support" "Not supported,Supported" rbitfld.long 0x00 28. " [1] ,Assert PME from D1 support" "Not supported,Supported" newline rbitfld.long 0x00 27. " [0] ,Assert PME from D0 support" "Not supported,Supported" rbitfld.long 0x00 26. " D2_SUPPORT ,D2 support" "Not supported,Supported" newline rbitfld.long 0x00 25. " D1_SUPPORT ,D1 support" "Not supported,Supported" bitfld.long 0x00 22.--24. " AUX_CURRENT ,Auxiliary current requirement for PCI" "Self power,55 mA,100 mA,160 mA,220 mA,270 mA,320 mA,375 mA" newline rbitfld.long 0x00 21. " DSI ,Device specific initialization required" "Not required,Required" rbitfld.long 0x00 19. " PME_CLOCK ,PME requires PCI clock" "Not required,Required" newline rbitfld.long 0x00 16.--18. " VERSION ,Version" ",,,1.2,?..." hexmask.long.byte 0x00 8.--15. 0x01 " XHCI_PM_CAPABILITY_DW ,Next item pointer" newline hexmask.long.byte 0x00 0.--7. 1. " XHCI_PM_CAP_ID ,Power management capability ID" line.long 0x04 "PM_PMCSR,Extended Power Management Control/Status Register" hexmask.long.byte 0x04 24.--31. 1. " DATA_REGISTER ,Data register" rbitfld.long 0x04 23. " BPCC_EN ,Bus power/clock control enable" "Disabled,Enabled" newline rbitfld.long 0x04 22. " B2_B3 ,D3HOT action" "B3,B2" eventfld.long 0x04 15. " PME_STATUS ,PME independent generation enable" "Disabled,Enabled" newline rbitfld.long 0x04 13.--14. " DATA_SCALE ,Data scale" "0,1,2,3" bitfld.long 0x04 9.--12. " DATA_SELECT ,Data select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8. " PME_EN ,PME generation enable" "Disabled,Enabled" rbitfld.long 0x04 3. " NO_SOFT_RESET ,Soft reset disable" "No,Yes" newline bitfld.long 0x04 0.--1. " POWERSTATE ,Current power state" "D0,D1,D2,D3HOT" if (((per.l(ad:0x5B110000+0x10000+0x84)&0x01)==0x00)) group.long 0x1801C++0x03 line.long 0x00 "MSI_CAP,MSI Configuration Register" rbitfld.long 0x00 24. " PER_VECTOR_MASKING ,Per vector masking support" "Not supported,Supported" rbitfld.long 0x00 23. " AC64 ,64 bit address capability" "Not capable,Capable" newline bitfld.long 0x00 20.--22. " MSI_MME ,Number of allocated vectors" "1,2,4,8,16,32,?..." rbitfld.long 0x00 17.--19. " MSI_MMC ,Number of requested vectors" "1,2,4,8,16,32,?..." newline bitfld.long 0x00 16. " MSI_EN ,MSI enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--15. 0x01 " XECP_MSI_CAP_OFFSET ,Pointer to next item in capabilities list" newline hexmask.long.byte 0x00 0.--7. 1. " MSI_ID ,Message signaled interrupts capability ID" else rgroup.long 0x1801C++0x03 line.long 0x00 "MSI_CAP,MSI Configuration Register" bitfld.long 0x00 24. " PER_VECTOR_MASKING ,Per vector masking support" "Not supported,Supported" bitfld.long 0x00 23. " AC64 ,64 bit address capability" "Not capable,Capable" newline bitfld.long 0x00 20.--22. " MSI_MME ,Number of allocated vectors" "1,2,4,8,16,32,?..." bitfld.long 0x00 17.--19. " MSI_MMC ,Number of requested vectors" "1,2,4,8,16,32,?..." newline bitfld.long 0x00 16. " MSI_EN ,MSI enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--15. 0x01 " XECP_MSI_CAP_OFFSET ,Pointer to next item in capabilities list" newline hexmask.long.byte 0x00 0.--7. 1. " MSI_ID ,Message signaled interrupts capability ID" endif if (((per.l(ad:0x5B110000+0x10000+0x84)&0x01)==0x00)&&((per.l(ad:0x5B110000+0x10000+0x801C)&0x10000)==0x00)) group.long 0x18020++0x03 line.long 0x00 "MSI_ADDR_L,Message Lower Address" hexmask.long 0x00 2.--31. 0x04 " MSI_ADDR_LOW ,MSI message address low" if ((per.l(ad:0x5B110000+0x10000+0x801C)&0x800000)==0x800000) group.long 0x18024++0x03 line.long 0x00 "MSI_ADDR_H,Message Upper Address" else hgroup.long 0x18024++0x03 hide.long 0x00 "MSI_ADDR_H,Message Upper Address" endif group.long 0x18028++0x03 line.long 0x00 "MSI_DATA,Message Data Register" hexmask.long.word 0x00 0.--15. 1. " MSI_DATA ,Message data" else rgroup.long 0x18020++0x03 line.long 0x00 "MSI_ADDR_L,Message Lower Address" hexmask.long 0x00 2.--31. 0x04 " MSI_ADDR_LOW ,MSI message address low" if ((per.l(ad:0x5B110000+0x10000+0x801C)&0x800000)==0x800000) rgroup.long 0x18024++0x03 line.long 0x00 "MSI_ADDR_H,Message Upper Address" else hgroup.long 0x18024++0x03 hide.long 0x00 "MSI_ADDR_H,Message Upper Address" endif rgroup.long 0x18028++0x03 line.long 0x00 "MSI_DATA,Message Data Register" hexmask.long.word 0x00 0.--15. 1. " MSI_DATA ,Message data" endif group.long 0x1802C++0x03 line.long 0x00 "AXI_CAP,AXI Master Wrapper Extended Capability Register" bitfld.long 0x00 31. " AXI_HALT ,AXI halt" "Not halted,Halted" rbitfld.long 0x00 30. " AXI_IDLE ,AXI idle" "Not idle,Idle" newline eventfld.long 0x00 29. " AXI_ERROR ,AXI error" "No error,Error" rbitfld.long 0x00 24.--26. " AXI_DATA_BUS_SIZE ,AXI data bus size" ",,,64 bit,128 bit,?..." newline rbitfld.long 0x00 23. " AXI_DISABLE_OOO ,Disable out-of-order R channel responses" "Single,Multiple" rbitfld.long 0x00 22. " AXI_MASTER_WRAPPER_SPLIT_BYTE_BURSTS ,AXI byte burst enable" "Disabled,Enabled" newline rbitfld.long 0x00 16. " AXI_ADDRESS_WIDTH_64 ,AXI address bus width" "32 bit,64 bit" hexmask.long.byte 0x00 8.--15. 0x01 " XECP_AXI_CAP_OFFSET ,Next capability offset" newline hexmask.long.byte 0x00 0.--7. 1. " AXI_CAP_ID ,Vendor defined xHCI extended capability" rgroup.long 0x18030++0x03 line.long 0x00 "AXI_CFG0,AXI Master Wrapper Extended Capability Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " AXI_RD_DEPTH ,AXI read buffer depth" bitfld.long 0x00 16.--21. " AXI_MAX_RD_OT ,AXI maximum outstanding read transactions count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x00 8.--15. 1. " AXI_WR_DEPTH ,AXI write buffer depth" bitfld.long 0x00 0.--5. " AXI_MAX_WR_OT ,AXI maximum outstanding write transaction count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if ((per.l(ad:0x5B110000+0x10000+0x802C)&0xC0000000)==0xC0000000) group.long 0x18034++0x0B line.long 0x00 "AXI_CTRL0,AXI Master Wrapper Extended Capability Control 0 Register" bitfld.long 0x00 0.--3. " AXI_BMAX ,AXI maximum burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "AXI_CTRL1,AXI Master Wrapper Extended Capability Control 1 Register" bitfld.long 0x04 16.--21. " AXI_ROT ,AXI outstanding read transactions count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " AXI_WOT ,AXI outstanding write transactions count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "AXI_CTRL2,AXI Master Wrapper Extended Capability Control 2 Register" bitfld.long 0x08 0.--4. " AXI_WTHRES ,AXI write buffer threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else rgroup.long 0x18034++0x0B line.long 0x00 "AXI_CTRL0,AXI Master Wrapper Extended Capability Control 0 Register" bitfld.long 0x00 0.--3. " AXI_BMAX ,AXI maximum burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "AXI_CTRL1,AXI Master Wrapper Extended Capability Control 1 Register" bitfld.long 0x04 16.--21. " AXI_ROT ,AXI outstanding read transactions count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " AXI_WOT ,AXI outstanding write transactions count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "AXI_CTRL2,AXI Master Wrapper Extended Capability Control 2 Register" bitfld.long 0x08 0.--4. " AXI_WTHRES ,AXI write buffer threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif rgroup.long 0x18040++0x1B line.long 0x00 "SUPP_USB2_CAP0,XHCI Supported Protocol Capability 0 Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR_REV ,Major release number" hexmask.long.byte 0x00 16.--23. 1. " MINOR_REV ,Minot release number" newline hexmask.long.byte 0x00 8.--15. 0x01 " NEXTCPAID ,Next capability location" hexmask.long.byte 0x00 0.--7. 1. " PID ,Capability ID" line.long 0x04 "SUPP_USB2_CAP1,XHCI Supported Protocol Capability 1 Register" line.long 0x08 "SUPP_USB2_CAP2,XHCI Supported Protocol Capability 2 Register" bitfld.long 0x08 28.--31. " PSIC ,Protocol speed ID count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 20. " HLC_BESL ,HIRD/BESL timing for BESL and BESLD select" "HIRD,BESL" newline bitfld.long 0x08 19. " HLC ,Hardware LPM support" "Not supported,Supported" bitfld.long 0x08 18. " IHI ,Integrated hub implemented" "Not implemented,Implemented" newline bitfld.long 0x08 17. " HSO ,High speed only" "LS/FS/HS,HS only" bitfld.long 0x08 16. " L1C ,LPM support" "Not supported,Supported" newline hexmask.long.byte 0x08 8.--15. 1. " COMPATIBLE_PORT_COUNT ,Root hub ports count" hexmask.long.byte 0x08 0.--7. 0x01 " COMPATIBLE_PORT_OFFSET ,Root hub ports starting port number" line.long 0x0C "SUPP_USB2_PROTOCOL_SLOT_TYPE,Protocol Slot Type Register" bitfld.long 0x0C 0.--4. " PST ,Protocol slot type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PSI_FULL_SPEED,Protocol Speed ID Full Speed Register" hexmask.long.word 0x10 16.--31. 1. " PSIM ,Protocol speed ID mantissa" bitfld.long 0x10 8. " PFD ,PSI half/full duplex select" "Half,Full" newline bitfld.long 0x10 6.--7. " PLT ,PSI type" "Symmetric,,Asymmetric RX,Asymmetric TX" bitfld.long 0x10 4.--5. " PSIE ,Protocol speed ID exponent" "Bits per second,Kb/s,Mb/s,Gb/s" newline bitfld.long 0x10 0.--3. " PSIV ,Protocol speed ID value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "PSI_LOW_SPEED,Protocol Speed ID Low Speed Register" hexmask.long.word 0x14 16.--31. 1. " PSIM ,Protocol speed ID mantissa" bitfld.long 0x14 8. " PFD ,PSI half/full duplex select" "Half,Full" newline bitfld.long 0x14 6.--7. " PLT ,PSI type" "Symmetric,,Asymmetric RX,Asymmetric TX" bitfld.long 0x14 4.--5. " PSIE ,Protocol speed ID exponent" "Bits per second,Kb/s,Mb/s,Gb/s" newline bitfld.long 0x14 0.--3. " PSIV ,Protocol speed ID value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "PSI_HIGH_SPEED,Protocol Speed ID High Speed Register" hexmask.long.word 0x18 16.--31. 1. " PSIM ,Protocol speed ID mantissa" bitfld.long 0x18 8. " PFD ,PSI half/full duplex select" "Half,Full" newline bitfld.long 0x18 6.--7. " PLT ,PSI type" "Symmetric,,Asymmetric RX,Asymmetric TX" bitfld.long 0x18 4.--5. " PSIE ,Protocol speed ID exponent" "Bits per second,Kb/s,Mb/s,Gb/s" newline bitfld.long 0x18 0.--3. " PSIV ,Protocol speed ID value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x18060++0x13 line.long 0x00 "SUPP_USB3_CAP0,XHCI Supported Protocol Capability 0 Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR_REV ,Major release number" hexmask.long.byte 0x00 16.--23. 1. " MINOR_REV ,Minot release number" newline hexmask.long.byte 0x00 8.--15. 0x01 " NEXTCPAID ,Next capability location" hexmask.long.byte 0x00 0.--7. 1. " PID ,Capability ID" line.long 0x04 "SUPP_USB3_CAP1,XHCI Supported Protocol Capability 1 Register" line.long 0x08 "SUPP_USB3_CAP2,XHCI Supported Protocol Capability 2 Register" bitfld.long 0x08 28.--31. " PSIC ,Protocol speed ID count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x08 8.--15. 1. " COMPATIBLE_PORT_COUNT ,Root hub ports count" newline hexmask.long.byte 0x08 0.--7. 0x01 " COMPATIBLE_PORT_OFFSET ,Root hub ports starting port number" line.long 0x0C "SUPP_USB3_PROTOCOL_SLOT_TYPE,Protocol Slot Type Register" bitfld.long 0x0C 0.--4. " PST ,Protocol slot type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PSI_SUPER_SPEED,Protocol Speed ID Super Speed Register" hexmask.long.word 0x10 16.--31. 1. " PSIM ,Protocol speed ID mantissa" bitfld.long 0x10 8. " PFD ,PSI half/full duplex select" "Half,Full" newline bitfld.long 0x10 6.--7. " PLT ,PSI type" "Symmetric,,Asymmetric RX,Asymmetric TX" bitfld.long 0x10 4.--5. " PSIE ,Protocol speed ID exponent" "Bits per second,Kb/s,Mb/s,Gb/s" newline bitfld.long 0x10 0.--3. " PSIV ,Protocol speed ID value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x180B0++0x03 line.long 0x00 "HOST_CTRL_CAP,Host Control Capability Register" hexmask.long.byte 0x00 8.--15. 0x01 " XECP_HOST_NEXT_CAP_OFFSET ,Next xHCI extended capability pointer" hexmask.long.byte 0x00 0.--7. 1. " VEND_DEF_HOST_CAP_ID_192 ,Capability ID" group.long 0x18370++0x07 line.long 0x00 "USBLEGSUP,USB Legacy Support Capability Register" bitfld.long 0x00 24. " HCOSOS ,HC system owned semaphore" "0,1" bitfld.long 0x00 16. " HCBIOSOS ,HC BIOS owned semaphore" "0,1" newline hexmask.long.byte 0x00 8.--15. 0x01 " NEXTCP ,Next capability pointer" hexmask.long.byte 0x00 0.--7. 1. " CID ,USB legacy support capability" line.long 0x04 "USBLEGCTLSTS,USB Legacy Support Control Status Register" eventfld.long 0x04 31. " SMIBAR ,SMI on BAR" "Not written,Written" eventfld.long 0x04 30. " SMIPCIC ,SMI on PCI command" "Not written,Written" newline eventfld.long 0x04 29. " SMIOSOC ,SMI on system ownership change" "Not changed,Changed" rbitfld.long 0x04 20. " SMIHSE ,SMI on host system error" "No error,Error" newline rbitfld.long 0x04 16. " SMIEI ,SMI on event interrupt" "No interrupt,Interrupt" bitfld.long 0x04 15. " SMIBARE ,SMI on BAR enable" "Disabled,Enabled" newline bitfld.long 0x04 14. " SMIPCICE ,SMI on PCI command enable" "Disabled,Enabled" bitfld.long 0x04 13. " SMIOSOE ,SMI on system ownership enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " SMIHSEE ,SMI on host system error enable" "Disabled,Enabled" bitfld.long 0x04 0. " USBSMIE ,USB SMI enable" "Disabled,Enabled" rgroup.long 0x18380++0x03 line.long 0x00 "DCID,Debug Capability ID Register" bitfld.long 0x00 16.--20. " DCERST_MAX ,Debug capability event ring segment table maximum" "1,2,4,8,16,32,64,128,256,512,1k,2k,4k,8k,16k,32k,65k,131k,262k,524k,1M,2M,4M,8M,16M,33M,67M,134M,268M,536M,1G,2G" hexmask.long.byte 0x00 8.--15. 0x01 " NEXTCAPID ,Next capability pointer" newline hexmask.long.byte 0x00 0.--7. 1. " CAPID ,Debug capability ID" group.long 0x18384++0x07 line.long 0x00 "DCDB,Debug Capability Doorbell Register" hexmask.long.byte 0x00 8.--15. 1. " DB_TARGET ,Doorbell target" line.long 0x04 "DCERSTSZ,Debug Capability Event Ring Segment Table Size Register" hexmask.long.word 0x04 0.--15. 1. " ERSTSZ ,Event ring segment table size" group.long 0x18390++0x0F line.long 0x00 "DCERSTBA_LOW,Debug Capability Event Ring Segment Table Base Address Low" hexmask.long 0x00 4.--31. 0x10 " ERSTBA_L ,Event ring segment table base address low" line.long 0x04 "DCERSTBA_HIGH,Debug Capability Event Ring Segment Table Base Address High" line.long 0x08 "DCERDP_LOW,Debug Capability Event Ring Dequeue Pointer Low" hexmask.long 0x08 4.--31. 0x10 " DEQ_PTR_L ,Dequeue pointer low" bitfld.long 0x08 0.--2. " DESI ,Dequeue ERST segment index" "0,1,2,3,4,5,6,7" line.long 0x0C "DCERDP_HIGH,Debug Capability Event Ring Dequeue Pointer High" if ((per.l(ad:0x5B110000+0x10000+0x83A0)&0x01)==0x01) group.long 0x183A0++0x03 line.long 0x00 "DCCTRL,Debug Capability Control Register" bitfld.long 0x00 31. " DCE ,Debug capability enable" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 0x01 " DEV_ADDR ,Device address" newline hexmask.long.byte 0x00 16.--23. 1. " DMAXBSIZE ,Debug maximum burst size" eventfld.long 0x00 4. " DRC ,DbC run change" "DCDB enabled,DCDB disabled" newline bitfld.long 0x00 3. " HIT ,Halt IN TR" "Not halted,Halted" bitfld.long 0x00 2. " HOT ,Halt OUT TR" "Not halted,Halted" newline bitfld.long 0x00 1. " LSE ,Link status event enable" "Disabled,Enabled" rbitfld.long 0x00 0. " DCR ,DbC run" "Stopped,Running" else group.long 0x183A0++0x03 line.long 0x00 "DCCTRL,Debug Capability Control Register" bitfld.long 0x00 31. " DCE ,Debug capability enable" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 0x01 " DEV_ADDR ,Device address" newline hexmask.long.byte 0x00 16.--23. 1. " DMAXBSIZE ,Debug maximum burst size" eventfld.long 0x00 4. " DRC ,DbC run change" "DCDB enabled,DCDB disabled" newline newline bitfld.long 0x00 1. " LSE ,Link status event enable" "Disabled,Enabled" rbitfld.long 0x00 0. " DCR ,DbC run" "Stopped,Running" endif rgroup.long 0x183A4++0x03 line.long 0x00 "DCST,Debug Capability Status Register" hexmask.long.byte 0x00 24.--31. 1. " DBGP_NUM ,Debug port number" bitfld.long 0x00 0. " ER ,Event ring not empty" "No,Yes" hgroup.long 0x183A8++0x03 hide.long 0x00 "DCPORTSC,Debug Capability Port Status And Control Register" in group.long 0x183B0++0x0F line.long 0x00 "DCCP_LOW,Debug Capability Context Pointer Low" hexmask.long 0x00 4.--31. 0x10 " DBGP_CNTX_PTR_L ,Debug capability context pointer low" line.long 0x04 "DCCP_HIGH,Debug Capability Context Pointer High" line.long 0x08 "DCDDI1,Debug Capability Device Descriptor Information 1 Register" hexmask.long.word 0x08 16.--31. 1. " VID ,Vendor ID" hexmask.long.byte 0x08 0.--7. 1. " DBC_PROT ,DbC Protocol" line.long 0x0C "DCDDI2,Debug Capability Device Descriptor Information 2 Register" hexmask.long.word 0x0C 16.--31. 1. " DEV_REV ,Device revision" hexmask.long.word 0x0C 0.--15. 1. " PROD_ID ,Product ID" tree.end newline width 12. if ((per.l(ad:0x5B110000+0x20000+0x04)&0x70)==0x40) if ((per.l(ad:0x5B110000+0x20000+0x4C)&0x8000000)==0x8000000) group.long 0x20000++0x0B line.long 0x00 "USB_CONF,Global Configuration Register" bitfld.long 0x00 31. " LGO_SSINACT ,SS inactive state entry request" "Not requested,Requested" bitfld.long 0x00 30. " LGO_U2 ,U2 state entry request" "Not requested,Requested" bitfld.long 0x00 29. " LGO_U1 ,U1 state entry request" "Not requested,Requested" newline bitfld.long 0x00 28. " LGO_U0 ,U0 state entry request" "Not requested,Requested" bitfld.long 0x00 7. " SWRST ,Device software reset" "No reset,Reset" newline bitfld.long 0x00 4. " USB2DIS ,Disconnect USB device in HS/FS" "Not disconnected,Disconnected" bitfld.long 0x00 3. " USB3DIS ,Disconnect USB device in super speed" "Not disconnected,Disconnected" line.long 0x04 "USB_STS,Global Status Register" setclrfld.long 0x04 31. -0x04 6. -0x04 5. " ENDIAN_SET/CLR ,SFR endianness" "Little endian,Big endian" setclrfld.long 0x04 30. -0x04 11. -0x04 10. " DMAOFF_SET/CLR ,DMA clock disable" "No,Yes" rbitfld.long 0x04 26.--29. " LST ,Super speed link LTSSM state" "U0,U1,U2,U3,Disabled,RxDetect,Inactive,Polling,Recovery,Hot reset,Compliance mode,Loopback,,,,Uninitialized" newline setclrfld.long 0x04 25. -0x04 26. -0x04 27. " U2ENS_SET/CLR ,U2 state entry enable" "Disabled,Enabled" setclrfld.long 0x04 24. -0x04 24. -0x04 25. " U1ENS_SET/CLR ,U1 state entry enable" "Disabled,Enabled" newline textfld " " rbitfld.long 0x04 17. " VBUSS ,Internal VBUS connection status" "Not connected,Connected" newline textfld " " rbitfld.long 0x04 15. " ADDRESSED ,Address status" "Default,Address" setclrfld.long 0x04 14. -0x04 14. -0x04 15. " DEVS_SET/CLR ,Device enable" "Disabled,Enabled" newline rbitfld.long 0x04 10. " IN_RST ,Controller in reset state" "No reset,Reset" setclrfld.long 0x04 9. -0x04 22. -0x04 21. " CLK3OFF_SET/CLR ,PCLK turn off" "On,Off" setclrfld.long 0x04 8. -0x04 19. -0x04 18. " CLK2OFF_SET/CLR ,HS/FS clock turn off" "On,Off" newline rbitfld.long 0x04 7. " ENDIAN_MIRROR ,SFR endianness mirror" "Little endian,Big endian" rbitfld.long 0x04 4.--6. " USBSPEED ,Device speed" "Undefined,LS,FS,HS,SS,?..." setclrfld.long 0x04 3. -0x04 9. -0x04 8. " DTRANS_SET/CLR ,DMA transfer mode" "Single,Multiple" newline rbitfld.long 0x04 2. " USB3CONS ,Super speed connection status" "Disconnected,Connected" rbitfld.long 0x04 1. " MEM_OV ,On chip memory overflow" "No overflow,Overflow" setclrfld.long 0x04 0. -0x04 1. -0x04 0. " CFGSTS_SET/CLR ,Configuration status" "Not configured,Configured" line.long 0x08 "USB_CMD,Global Command Register" bitfld.long 0x08 24.--27. " DNLTM_BELT[11:8] ,Device notification latency tolerance message BELT [11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x08 16.--23. 1. " DNLTM_BELT[7:0] ,Device notification latency tolerance message BELT [7:0]" bitfld.long 0x08 13. " SPKT ,Send custom transaction packet" "Not sent,Sent" newline bitfld.long 0x08 12. " SDNLTM ,Send latency tolerance message device notification TP" "Not sent,Sent" newline bitfld.long 0x08 8. " SDNFW ,Send function wake device notification TP" "Not sent,Sent" hexmask.long.byte 0x08 1.--7. 0x02 " FADDR ,Function address" bitfld.long 0x08 0. " SET_ADDR ,Function address set" "Not set,Set" else group.long 0x20000++0x0B line.long 0x00 "USB_CONF,Global Configuration Register" textfld " " bitfld.long 0x00 30. " LGO_U2 ,U2 state entry request" "Not requested,Requested" bitfld.long 0x00 29. " LGO_U1 ,U1 state entry request" "Not requested,Requested" newline bitfld.long 0x00 28. " LGO_U0 ,U0 state entry request" "Not requested,Requested" bitfld.long 0x00 7. " SWRST ,Device software reset" "No reset,Reset" newline bitfld.long 0x00 4. " USB2DIS ,Disconnect USB device in HS/FS" "Not disconnected,Disconnected" bitfld.long 0x00 3. " USB3DIS ,Disconnect USB device in super speed" "Not disconnected,Disconnected" line.long 0x04 "USB_STS,Global Status Register" setclrfld.long 0x04 31. -0x04 6. -0x04 5. " ENDIAN_SET/CLR ,SFR endianness" "Little endian,Big endian" setclrfld.long 0x04 30. -0x04 11. -0x04 10. " DMAOFF_SET/CLR ,DMA clock disable" "No,Yes" rbitfld.long 0x04 26.--29. " LST ,Super speed link LTSSM state" "U0,U1,U2,U3,Disabled,RxDetect,Inactive,Polling,Recovery,Hot reset,Compliance mode,Loopback,,,,Uninitialized" newline setclrfld.long 0x04 25. -0x04 26. -0x04 27. " U2ENS_SET/CLR ,U2 state entry enable" "Disabled,Enabled" setclrfld.long 0x04 24. -0x04 24. -0x04 25. " U1ENS_SET/CLR ,U1 state entry enable" "Disabled,Enabled" newline textfld " " rbitfld.long 0x04 17. " VBUSS ,Internal VBUS connection status" "Not connected,Connected" newline textfld " " rbitfld.long 0x04 15. " ADDRESSED ,Address status" "Default,Address" setclrfld.long 0x04 14. -0x04 14. -0x04 15. " DEVS_SET/CLR ,Device enable" "Disabled,Enabled" newline rbitfld.long 0x04 10. " IN_RST ,Controller in reset state" "No reset,Reset" setclrfld.long 0x04 9. -0x04 22. -0x04 21. " CLK3OFF_SET/CLR ,PCLK turn off" "On,Off" setclrfld.long 0x04 8. -0x04 19. -0x04 18. " CLK2OFF_SET/CLR ,HS/FS clock turn off" "On,Off" newline rbitfld.long 0x04 7. " ENDIAN_MIRROR ,SFR endianness mirror" "Little endian,Big endian" rbitfld.long 0x04 4.--6. " USBSPEED ,Device speed" "Undefined,LS,FS,HS,SS,?..." setclrfld.long 0x04 3. -0x04 9. -0x04 8. " DTRANS_SET/CLR ,DMA transfer mode" "Single,Multiple" newline rbitfld.long 0x04 2. " USB3CONS ,Super speed connection status" "Disconnected,Connected" rbitfld.long 0x04 1. " MEM_OV ,On chip memory overflow" "No overflow,Overflow" setclrfld.long 0x04 0. -0x04 1. -0x04 0. " CFGSTS_SET/CLR ,Configuration status" "Not configured,Configured" line.long 0x08 "USB_CMD,Global Command Register" bitfld.long 0x08 24.--27. " DNLTM_BELT[11:8] ,Device notification latency tolerance message BELT [11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x08 16.--23. 1. " DNLTM_BELT[7:0] ,Device notification latency tolerance message BELT [7:0]" bitfld.long 0x08 13. " SPKT ,Send custom transaction packet" "Not sent,Sent" newline bitfld.long 0x08 12. " SDNLTM ,Send latency tolerance message device notification TP" "Not sent,Sent" newline bitfld.long 0x08 8. " SDNFW ,Send function wake device notification TP" "Not sent,Sent" hexmask.long.byte 0x08 1.--7. 0x02 " FADDR ,Function address" bitfld.long 0x08 0. " SET_ADDR ,Function address set" "Not set,Set" endif elif (((per.l(ad:0x5B110000+0x20000+0x04)&0x70)==0x30)||((per.l(ad:0x5B110000+0x20000+0x04)&0x70)==0x20)) group.long 0x20000++0x07 line.long 0x00 "USB_CONF,Global Configuration Register" newline textfld " " bitfld.long 0x00 20. " LGO_L0 ,L0 LPM state entry request" "Not requested,Requested" bitfld.long 0x00 7. " SWRST ,Device software reset" "No reset,Reset" newline bitfld.long 0x00 4. " USB2DIS ,Disconnect USB device in HS/FS" "Not disconnected,Disconnected" bitfld.long 0x00 3. " USB3DIS ,Disconnect USB device in super speed" "Not disconnected,Disconnected" line.long 0x04 "USB_STS,Global Status Register" setclrfld.long 0x04 31. 0x00 6. 0x00 5. " ENDIAN_SET/CLR ,SFR endianness" "Little endian,Big endian" setclrfld.long 0x04 30. 0x00 11. 0x00 10. " DMAOFF_SET/CLR ,DMA clock disable" "No,Yes" rbitfld.long 0x04 26.--29. " LST ,Super speed link LTSSM state" "U0,U1,U2,U3,Disabled,RxDetect,Inactive,Polling,Recovery,Hot reset,Compliance mode,Loopback,,,,Uninitialized" newline textfld " " setclrfld.long 0x04 21. 0x00 13. 0x00 12. " DISABLE_HS_SET/CLR ,High speed disable" "No,Yes" newline rbitfld.long 0x04 20. " USB2CONS ,USB_CONF.USB2DIS status" "Set,Not set" rbitfld.long 0x04 18.--19. " LPMST ,HS/FS LPM state" "L0,L1,L2,L3" rbitfld.long 0x04 17. " VBUSS ,Internal VBUS connection status" "Not connected,Connected" newline setclrfld.long 0x04 16. 0x00 16. 0x00 17. " L1ENS_SET/CLR ,L1 LPM state entry enable" "Disabled,Enabled" rbitfld.long 0x04 15. " ADDRESSED ,Address status" "Default,Address" setclrfld.long 0x04 14. 0x00 14. 0x00 15. " DEVS_SET/CLR ,Device enable" "Disabled,Enabled" newline rbitfld.long 0x04 10. " IN_RST ,Controller in reset state" "No reset,Reset" setclrfld.long 0x04 9. 0x00 22. 0x00 21. " CLK3OFF_SET/CLR ,PCLK turn off" "On,Off" setclrfld.long 0x04 8. 0x00 19. 0x00 18. " CLK2OFF_SET/CLR ,HS/FS clock turn off" "On,Off" newline rbitfld.long 0x04 7. " ENDIAN_MIRROR ,SFR endianness mirror" "Little endian,Big endian" rbitfld.long 0x04 4.--6. " USBSPEED ,Device speed" "Undefined,LS,FS,HS,SS,?..." setclrfld.long 0x04 3. 0x00 9. 0x00 8. " DTRANS_SET/CLR ,DMA transfer mode" "Single,Multiple" newline rbitfld.long 0x04 2. " USB3CONS ,Super speed connection status" "Disconnected,Connected" rbitfld.long 0x04 1. " MEM_OV ,On-chip memory overflow" "No overflow,Overflow" setclrfld.long 0x04 0. 0x00 1. 0x00 0. " CFGSTS_SET/CLR ,Configuration status" "Not configured,Configured" wgroup.long 0x20008++0x03 line.long 0x00 "USB_CMD,Global Command Register" newline textfld " " bitfld.long 0x00 10.--11. " TMODE_SEL ,Test mode selector" "J,K,SE0_NAK,Packet" bitfld.long 0x00 9. " STMODE ,Test mode set" "Not set,Set" newline textfld " " hexmask.long.byte 0x00 1.--7. 0x02 " FADDR ,Function address" bitfld.long 0x00 0. " SET_ADDR ,Function address set" "Not set,Set" else group.long 0x20000++0x07 line.long 0x00 "USB_CONF,Global Configuration Register" newline textfld " " bitfld.long 0x00 7. " SWRST ,Device software reset" "No reset,Reset" newline bitfld.long 0x00 4. " USB2DIS ,Disconnect USB device in HS/FS" "Not disconnected,Disconnected" bitfld.long 0x00 3. " USB3DIS ,Disconnect USB device in super speed" "Not disconnected,Disconnected" line.long 0x04 "USB_STS,Global Status Register" setclrfld.long 0x04 31. 0x00 6. 0x00 5. " ENDIAN_SET/CLR ,SFR endianness" "Little endian,Big endian" setclrfld.long 0x04 30. 0x00 11. 0x00 10. " DMAOFF_SET/CLR ,DMA clock disable" "No,Yes" rbitfld.long 0x04 26.--29. " LST ,Super speed link LTSSM state" "U0,U1,U2,U3,Disabled,RxDetect,Inactive,Polling,Recovery,Hot reset,Compliance mode,Loopback,,,,Uninitialized" newline newline textfld " " rbitfld.long 0x04 17. " VBUSS ,Internal VBUS connection status" "Not connected,Connected" newline textfld " " rbitfld.long 0x04 15. " ADDRESSED ,Address status" "Default,Address" setclrfld.long 0x04 14. 0x00 14. 0x00 15. " DEVS_SET/CLR ,Device enable" "Disabled,Enabled" newline rbitfld.long 0x04 10. " IN_RST ,Controller in reset state" "No reset,Reset" setclrfld.long 0x04 9. 0x00 22. 0x00 21. " CLK3OFF_SET/CLR ,PCLK turn off" "On,Off" setclrfld.long 0x04 8. 0x00 19. 0x00 18. " CLK2OFF_SET/CLR ,HS/FS clock turn off" "On,Off" newline rbitfld.long 0x04 7. " ENDIAN_MIRROR ,SFR endianness mirror" "Little endian,Big endian" rbitfld.long 0x04 4.--6. " USBSPEED ,Device speed" "Undefined,LS,FS,HS,SS,?..." setclrfld.long 0x04 3. 0x00 9. 0x00 8. " DTRANS_SET/CLR ,DMA transfer mode" "Single,Multiple" newline rbitfld.long 0x04 2. " USB3CONS ,Super speed connection status" "Disconnected,Connected" rbitfld.long 0x04 1. " MEM_OV ,On chip memory overflow" "No overflow,Overflow" setclrfld.long 0x04 0. 0x00 1. 0x00 0. " CFGSTS_SET/CLR ,Configuration status" "Not configured,Configured" wgroup.long 0x20008++0x03 line.long 0x00 "USB_CMD,Global Command Register" newline newline textfld " " hexmask.long.byte 0x00 1.--7. 0x02 " FADDR ,Function address" bitfld.long 0x00 0. " SET_ADDR ,Function address set" "Not set,Set" endif if (((per.l(ad:0x5B110000+0x20000+0x04)&0x70)==0x30)||((per.l(ad:0x5B110000+0x20000+0x04)&0x70)==0x20)) rgroup.long 0x2000C++0x03 line.long 0x00 "USB_SOFN,SOF Number Register" hexmask.long.word 0x00 0.--13. 1. " SOFN ,Number of last SOF received from host" else rgroup.long 0x2000C++0x03 line.long 0x00 "USB_IPTN,ITP Number Register" hexmask.long.word 0x00 0.--13. 1. " ITP ,Number of last ITP received from host" endif rgroup.long 0x20010++0x03 line.long 0x00 "USB_LPM,Link Power Management Register" bitfld.long 0x00 4. " BRW ,Remote wakeup enable" "Disabled,Enabled" bitfld.long 0x00 0.--3. " HIRD ,Host initiated resume duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x20014++0x0F line.long 0x00 "USB_IEN,Interrupt Enable Register" bitfld.long 0x00 29. " UWRESEIEN ,End of USB SS warm reset interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " UWRESSIEN ,Start of USB SS warm reset interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " CFGRESIEN ,Configuration reset interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " L1EXTIEN ,LPM L1 state exit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " L1ENTIEN ,LPM L1 state enter interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " L2EXTIEN ,LPM L2 state exit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 20. " L2ENTIEN ,LPM L2 state enter interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " U2RESIEN ,HS/FS mode USB reset interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " DIS2IEN ,HS/FS mode disconnection interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " CON2IEN ,HS/FS mode connection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " SPKTIEN ,Send custom packet interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " WAKEIEN ,Wake interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " ITPIEN ,ITP/SOF packet detected interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " U1EXTIEN ,SS link U1 state exit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " U1ENTIEN ,SS link U1 state enter interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " U2EXTIEN ,SS link U2 state exit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " U2ENTIEN ,SS link U2 state enter interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " U3EXTIEN ,SS link U3 state exit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " U3ENTIEN ,SS link U3 state enter interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " UHRESIEN ,USB SS hot reset interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " UWRESIEN ,USB SS warm reset interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " DISIEN ,SS disconnection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " CONIEN ,SS connection interrupt enable" "Disabled,Enabled" line.long 0x04 "USB_ISTS,Interrupt Status Register" eventfld.long 0x04 29. " UWRESEI ,End of the USB warm reset detected interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 28. " UWRESSI ,Start of the USB warm reset detected interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 26. " CFGRESI ,USB configuration reset detected interrupt status" "No interrupt,Interrupt" newline eventfld.long 0x04 25. " L1EXTI ,LPM L1 state exit detected interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 24. " L1ENTI ,LPM L1 state enter detected interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 21. " L2EXTI ,LPM L2 state exit detected interrupt status" "No interrupt,Interrupt" newline eventfld.long 0x04 20. " L2ENTI ,LPM L2 state enter detected interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 18. " U2RESI ,HS/FS mode USB reset detected interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 17. " DIS2I ,HS/FS mode disconnection detected interrupt status" "No interrupt,Interrupt" newline eventfld.long 0x04 16. " CON2I ,HS/FS mode connection detected interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 12. " SPKTI ,Send custom packet interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 11. " WAKEI ,Wake interrupt status" "No interrupt,Interrupt" newline eventfld.long 0x04 10. " ITPI ,ITP/SOF packet detected interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 9. " U1EXTI ,SS link U1 state exit detected interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 8. " U1ENTI ,SS link U1 state enter detected interrupt status" "No interrupt,Interrupt" newline eventfld.long 0x04 7. " U2EXTI ,SS link U2 state exit detected interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 6. " U2ENTI ,SS link U2 state enter detected interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 5. " U3EXTI ,SS link U3 state exit detected interrupt status" "No interrupt,Interrupt" newline eventfld.long 0x04 4. " U3ENTI ,SS link U3 state enter detected interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 3. " UHRESI ,USB SS hot reset detected interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 2. " UWRESI ,USB SS warm reset detected interrupt status" "No interrupt,Interrupt" newline eventfld.long 0x04 1. " DISI ,SS disconnection detected interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 0. " CONI ,SS connection detected interrupt status" "No interrupt,Interrupt" line.long 0x08 "EP_SEL,Endpoint Select Register" bitfld.long 0x08 7. " DIR ,Selected endpoint direction" "OUT,IN" bitfld.long 0x08 0.--3. " EPNO ,Selected endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "EP_TRADDR,Endpoint Transfer Ring Address" if ((per.l(ad:0x5B110000+0x20000+0x04)&0x70)==0x40) if ((per.l(ad:0x5B110000+0x20000+0x24)&0x06)==0x02) group.long 0x20024++0x03 line.long 0x00 "EP_CFG,Endpoint Configuration Register" bitfld.long 0x00 27.--31. " BUFFERING ,Maximum number of buffered packets" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." hexmask.long.word 0x00 16.--26. 1. " MAXPKTSIZE ,Maximum packet size" bitfld.long 0x00 14.--15. " MULT ,ISO maximum burst" "1,2,3,?..." newline bitfld.long 0x00 8.--11. " MAXBURST ,Maximum burst size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 7. " EPENDIAN ,DMA transfer endianness" "Off,On" newline textfld " " bitfld.long 0x00 3. " STREAM_EN ,Stream support enable" "Disabled,Enabled" bitfld.long 0x00 1.--2. " EPTYPE ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" newline bitfld.long 0x00 0. " ENABLE ,Endpoint enable" "Disabled,Enabled" elif ((per.l(ad:0x5B110000+0x20000+0x24)&0x06)==0x04) group.long 0x20024++0x03 line.long 0x00 "EP_CFG,Endpoint Configuration Register" bitfld.long 0x00 27.--31. " BUFFERING ,Maximum number of buffered packets" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." hexmask.long.word 0x00 16.--26. 1. " MAXPKTSIZE ,Maximum packet size" newline bitfld.long 0x00 8.--11. " MAXBURST ,Maximum burst size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 7. " EPENDIAN ,DMA transfer endianness" "Off,On" bitfld.long 0x00 5. " SID_CHK ,SID check" "No check,Check" newline bitfld.long 0x00 4. " TDL_CHK ,TDL check" "No check,Check" bitfld.long 0x00 3. " STREAM_EN ,Stream support enable" "Disabled,Enabled" bitfld.long 0x00 1.--2. " EPTYPE ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" newline bitfld.long 0x00 0. " ENABLE ,Endpoint enable" "Disabled,Enabled" else group.long 0x20024++0x03 line.long 0x00 "EP_CFG,Endpoint Configuration Register" bitfld.long 0x00 27.--31. " BUFFERING ,Maximum number of buffered packets" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." hexmask.long.word 0x00 16.--26. 1. " MAXPKTSIZE ,Maximum packet size" newline bitfld.long 0x00 8.--11. " MAXBURST ,Maximum burst size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 7. " EPENDIAN ,DMA transfer endianness" "Off,On" newline textfld " " bitfld.long 0x00 3. " STREAM_EN ,Stream support enable" "Disabled,Enabled" bitfld.long 0x00 1.--2. " EPTYPE ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" newline bitfld.long 0x00 0. " ENABLE ,Endpoint enable" "Disabled,Enabled" endif elif ((per.l(ad:0x5B110000+0x20000+0x04)&0x70)==0x30) group.long 0x20024++0x03 line.long 0x00 "EP_CFG,Endpoint Configuration Register" bitfld.long 0x00 27.--31. " BUFFERING ,Maximum number of buffered packets" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." hexmask.long.word 0x00 16.--26. 1. " MAXPKTSIZE ,Maximum packet size" bitfld.long 0x00 14.--15. " MULT ,ISO maximum burst" "1,2,3,?..." newline bitfld.long 0x00 8.--11. " MAXBURST ,Maximum burst size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 7. " EPENDIAN ,DMA transfer endianness" "Off,On" newline textfld " " bitfld.long 0x00 1.--2. " EPTYPE ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" newline bitfld.long 0x00 0. " ENABLE ,Endpoint enable" "Disabled,Enabled" elif ((per.l(ad:0x5B110000+0x20000+0x04)&0x70)==0x20) group.long 0x20024++0x03 line.long 0x00 "EP_CFG,Endpoint Configuration Register" bitfld.long 0x00 27.--31. " BUFFERING ,Maximum number of buffered packets" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." hexmask.long.word 0x00 16.--26. 1. " MAXPKTSIZE ,Maximum packet size" bitfld.long 0x00 14.--15. " MULT ,ISO maximum burst" "1,?..." newline bitfld.long 0x00 8.--11. " MAXBURST ,Maximum burst size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 7. " EPENDIAN ,DMA transfer endianness" "Off,On" newline textfld " " bitfld.long 0x00 1.--2. " EPTYPE ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" newline bitfld.long 0x00 0. " ENABLE ,Endpoint enable" "Disabled,Enabled" else group.long 0x20024++0x03 line.long 0x00 "EP_CFG,Endpoint Configuration Register" bitfld.long 0x00 27.--31. " BUFFERING ,Maximum number of buffered packets" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." hexmask.long.word 0x00 16.--26. 1. " MAXPKTSIZE ,Maximum packet size" newline bitfld.long 0x00 8.--11. " MAXBURST ,Maximum burst size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 7. " EPENDIAN ,DMA transfer endianness" "Off,On" newline textfld " " bitfld.long 0x00 1.--2. " EPTYPE ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" newline bitfld.long 0x00 0. " ENABLE ,Endpoint enable" "Disabled,Enabled" endif if (((per.l(ad:0x5B110000+0x20000+0x04)&0x70)==0x40)&&((per.l(ad:0x5B110000+0x20000+0x24)&0x06)==0x04)) group.long 0x20028++0x03 line.long 0x00 "EP_CMD,Endpoint Command Register" hexmask.long.word 0x00 16.--31. 1. " ERDY_SID ,ERDY stream ID value" hexmask.long.byte 0x00 9.--15. 1. " TDL ,Transfer descriptor length" bitfld.long 0x00 8. " STDL ,Transfer descriptor length write" "No write,Write" newline bitfld.long 0x00 7. " DFLUSH ,Data flush" "No flush,Flush" bitfld.long 0x00 6. " DRDY ,Transfer descriptor ready" "Not ready,Ready" bitfld.long 0x00 5. " REQ_CMPL ,Request complete" "Not completed,Completed" newline bitfld.long 0x00 3. " ERDY ,Send ERDY TP" "Not sent,Sent" bitfld.long 0x00 2. " CSTALL ,Endpoint STALL clear" "No clear,Clear" bitfld.long 0x00 1. " SSTALL ,Endpoint STALL set" "Not set,Set" newline bitfld.long 0x00 0. " EPRST ,Endpoint reset" "No reset,Reset" elif (((per.l(ad:0x5B110000+0x20000+0x04)&0x70)==0x40)&&((per.l(ad:0x5B110000+0x20000+0x24)&0x06)!=0x04)) group.long 0x20028++0x03 line.long 0x00 "EP_CMD,Endpoint Command Register" hexmask.long.word 0x00 16.--31. 1. " ERDY_SID ,ERDY stream ID value" newline bitfld.long 0x00 7. " DFLUSH ,Data flush" "No flush,Flush" bitfld.long 0x00 6. " DRDY ,Transfer descriptor ready" "Not ready,Ready" bitfld.long 0x00 5. " REQ_CMPL ,Request complete" "Not completed,Completed" newline bitfld.long 0x00 3. " ERDY ,Send ERDY TP" "Not sent,Sent" bitfld.long 0x00 2. " CSTALL ,Endpoint STALL clear" "No clear,Clear" bitfld.long 0x00 1. " SSTALL ,Endpoint STALL set" "Not set,Set" newline bitfld.long 0x00 0. " EPRST ,Endpoint reset" "No reset,Reset" else group.long 0x20028++0x03 line.long 0x00 "EP_CMD,Endpoint Command Register" newline bitfld.long 0x00 7. " DFLUSH ,Data flush" "No flush,Flush" bitfld.long 0x00 6. " DRDY ,Transfer descriptor ready" "Not ready,Ready" bitfld.long 0x00 5. " REQ_CMPL ,Request complete" "Not completed,Completed" newline bitfld.long 0x00 3. " ERDY ,Send ERDY TP" "Not sent,Sent" bitfld.long 0x00 2. " CSTALL ,Endpoint STALL clear" "No clear,Clear" bitfld.long 0x00 1. " SSTALL ,Endpoint STALL set" "Not set,Set" newline bitfld.long 0x00 0. " EPRST ,Endpoint reset" "No reset,Reset" endif if ((per.l(ad:0x5B110000+0x20000+0x24)&0x06)==0x04) if ((per.l(ad:0x5B110000+0x20000+0x04)&0x70)==0x40) group.long 0x2002C++0x07 line.long 0x00 "EP_STS,Endpoint Status Register" eventfld.long 0x00 31. " STPWAIT ,Setup packet received and stored interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 28. " OUTQ_VAL ,OUT queue valid" "Invalid,Valid" rbitfld.long 0x00 24.--27. " OUTQ_NO ,OUT queue endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline eventfld.long 0x00 19. " IOT ,Interrupt on transfer complete interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 17.--18. " SPSMST ,Stream protocol state machine state" "DISABLED,IDLE,START_STREAM,MOVE_DATA" rbitfld.long 0x00 16. " HOSTPP ,Host packet pending" "Not pending,Pending" newline eventfld.long 0x00 15. " ISOERR ,ISO transmission error interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " OUTSMM ,OUT size mismatch interrupt" "No interrupt,Interrupt" eventfld.long 0x00 13. " SIDERR ,Stream error interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 12. " PRIME ,Packet with prime ID received interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 11. " CCS ,Current cycle status" "0,1" rbitfld.long 0x00 10. " BUFFEMPTY ,Endpoint buffer empty" "Not empty,Empty" newline rbitfld.long 0x00 9. " DBUSY ,DMA busy" "Not busy,Busy" eventfld.long 0x00 8. " NRDY ,Not ready interrupt" "No interrupt,Interrupt" eventfld.long 0x00 7. " TRBERR ,TRB error interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 6. " MD_EXIT ,MOVE_DATA state exit interrupt" "No interrupt,Interrupt" eventfld.long 0x00 5. " STREAMR ,Stream rejected interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " DESCMIS ,Transfer descriptor missing interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 3. " ISP ,Short packet interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " IOC ,DMA transfer completed interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 1. " STALL ,Endpoint stall status" "Not stalled,Stalled" newline eventfld.long 0x00 0. " SETUP ,Setup transfer complete interrupt" "No interrupt,Interrupt" line.long 0x04 "EP_STS_SID,Endpoint Status Stream ID Register" hexmask.long.word 0x04 0.--15. 1. " SID ,Stream ID" else group.long 0x2002C++0x03 line.long 0x00 "EP_STS,Endpoint Status Register" eventfld.long 0x00 31. " STPWAIT ,Setup packet received and stored interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 28. " OUTQ_VAL ,OUT queue valid" "Invalid,Valid" rbitfld.long 0x00 24.--27. " OUTQ_NO ,OUT queue endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline eventfld.long 0x00 19. " IOT ,Interrupt on transfer complete interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 17.--18. " SPSMST ,Stream protocol state machine state" "DISABLED,IDLE,START_STREAM,MOVE_DATA" newline eventfld.long 0x00 15. " ISOERR ,ISO transmission error interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " OUTSMM ,OUT size mismatch interrupt" "No interrupt,Interrupt" newline textfld " " rbitfld.long 0x00 11. " CCS ,Current cycle status" "0,1" rbitfld.long 0x00 10. " BUFFEMPTY ,Endpoint buffer empty" "Not empty,Empty" newline rbitfld.long 0x00 9. " DBUSY ,DMA busy" "Not busy,Busy" textfld " " eventfld.long 0x00 7. " TRBERR ,TRB error interrupt" "No interrupt,Interrupt" newline textfld " " eventfld.long 0x00 4. " DESCMIS ,Transfer descriptor missing interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 3. " ISP ,Short packet interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " IOC ,DMA transfer completed interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 1. " STALL ,Endpoint stall status" "Not stalled,Stalled" newline eventfld.long 0x00 0. " SETUP ,Setup transfer complete interrupt" "No interrupt,Interrupt" hgroup.long 0x20030++0x03 hide.long 0x00 "EP_STS_SID,Endpoint Status Stream ID Register" endif else if ((per.l(ad:0x5B110000+0x20000+0x04)&0x70)==0x40) group.long 0x2002C++0x07 line.long 0x00 "EP_STS,Endpoint Status Register" eventfld.long 0x00 31. " STPWAIT ,Setup packet received and stored interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 28. " OUTQ_VAL ,OUT queue valid" "Invalid,Valid" rbitfld.long 0x00 24.--27. " OUTQ_NO ,OUT queue endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline eventfld.long 0x00 19. " IOT ,Interrupt on transfer complete interrupt" "No interrupt,Interrupt" textfld " " rbitfld.long 0x00 16. " HOSTPP ,Host packet pending" "Not pending,Pending" newline eventfld.long 0x00 15. " ISOERR ,ISO transmission error interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " OUTSMM ,OUT size mismatch interrupt" "No interrupt,Interrupt" eventfld.long 0x00 13. " SIDERR ,Stream error interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 12. " PRIME ,Packet with prime ID received interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 11. " CCS ,Current cycle status" "0,1" rbitfld.long 0x00 10. " BUFFEMPTY ,Endpoint buffer empty" "Not empty,Empty" newline rbitfld.long 0x00 9. " DBUSY ,DMA busy" "Not busy,Busy" eventfld.long 0x00 8. " NRDY ,Not ready interrupt" "No interrupt,Interrupt" eventfld.long 0x00 7. " TRBERR ,TRB error interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 6. " MD_EXIT ,MOVE_DATA state exit interrupt" "No interrupt,Interrupt" eventfld.long 0x00 5. " STREAMR ,Stream rejected interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " DESCMIS ,Transfer descriptor missing interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 3. " ISP ,Short packet interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " IOC ,DMA transfer completed interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 1. " STALL ,Endpoint stall status" "Not stalled,Stalled" newline eventfld.long 0x00 0. " SETUP ,Setup transfer complete interrupt" "No interrupt,Interrupt" line.long 0x04 "EP_STS_SID,Endpoint Status Stream ID Register" hexmask.long.word 0x04 0.--15. 1. " SID ,Stream ID" else group.long 0x2002C++0x03 line.long 0x00 "EP_STS,Endpoint Status Register" eventfld.long 0x00 31. " STPWAIT ,Setup packet received and stored interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 28. " OUTQ_VAL ,OUT queue valid" "Invalid,Valid" rbitfld.long 0x00 24.--27. " OUTQ_NO ,OUT queue endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline eventfld.long 0x00 19. " IOT ,Interrupt on transfer complete interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 15. " ISOERR ,ISO transmission error interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " OUTSMM ,OUT size mismatch interrupt" "No interrupt,Interrupt" newline textfld " " rbitfld.long 0x00 11. " CCS ,Current cycle status" "0,1" rbitfld.long 0x00 10. " BUFFEMPTY ,Endpoint buffer empty" "Not empty,Empty" newline rbitfld.long 0x00 9. " DBUSY ,DMA busy" "Not busy,Busy" textfld " " eventfld.long 0x00 7. " TRBERR ,TRB error interrupt" "No interrupt,Interrupt" newline textfld " " eventfld.long 0x00 4. " DESCMIS ,Transfer descriptor missing interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 3. " ISP ,Short packet interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " IOC ,DMA transfer completed interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 1. " STALL ,Endpoint stall status" "Not stalled,Stalled" newline eventfld.long 0x00 0. " SETUP ,Setup transfer complete interrupt" "No interrupt,Interrupt" hgroup.long 0x20030++0x03 hide.long 0x00 "EP_STS_SID,Endpoint Status Stream ID Register" endif endif group.long 0x20034++0x0B line.long 0x00 "EP_STS_EN,Endpoint Status Register Enable" bitfld.long 0x00 31. " STPWAITEN ,Setup wait interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " IOTEN ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 15. " ISOERREN ,ISO transmission error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 14. " OUTSMMEN ,OUT size mismatch interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " SIDERREN ,Stream error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " PRIMEEN ,Prime interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " NRDYEN ,NRDY interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TRBERREN ,TRB error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " MD_EXITEN ,Move data exit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " STREAMREN ,Stream rejected interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " DESCMISEN ,OUT transfer missing descriptor interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " SETUPEN ,Setup transfer complete interrupt enable" "Disabled,Enabled" line.long 0x04 "DRBL,Doorbell Register" bitfld.long 0x04 23. " DRBL7I ,Doorbell 7I" "0,1" bitfld.long 0x04 22. " DRBL6I ,Doorbell 6I" "0,1" bitfld.long 0x04 21. " DRBL5I ,Doorbell 5I" "0,1" newline bitfld.long 0x04 20. " DRBL4I ,Doorbell 4I" "0,1" bitfld.long 0x04 19. " DRBL3I ,Doorbell 3I" "0,1" bitfld.long 0x04 18. " DRBL2I ,Doorbell 2I" "0,1" newline bitfld.long 0x04 17. " DRBL1I ,Doorbell 1I" "0,1" bitfld.long 0x04 16. " DRBL0I ,Doorbell 0I" "0,1" newline bitfld.long 0x04 7. " DRBL7O ,Doorbell 7O" "0,1" bitfld.long 0x04 6. " DRBL6O ,Doorbell 6O" "0,1" bitfld.long 0x04 5. " DRBL5O ,Doorbell 5O" "0,1" newline bitfld.long 0x04 4. " DRBL4O ,Doorbell 4O" "0,1" bitfld.long 0x04 3. " DRBL3O ,Doorbell 3O" "0,1" bitfld.long 0x04 2. " DRBL2O ,Doorbell 2O" "0,1" newline bitfld.long 0x04 1. " DRBL1O ,Doorbell 1O" "0,1" bitfld.long 0x04 0. " DRBL0O ,Doorbell 0O" "0,1" line.long 0x08 "EP_IEN,Endpoints Interrupt Enable Register" bitfld.long 0x08 23. " EINEN7 ,Endpoint 7IN interrupt enable" "Disabled,Enabled" bitfld.long 0x08 22. " EINEN6 ,Endpoint 6IN interrupt enable" "Disabled,Enabled" bitfld.long 0x08 21. " EINEN5 ,Endpoint 5IN interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 20. " EINEN4 ,Endpoint 4IN interrupt enable" "Disabled,Enabled" bitfld.long 0x08 19. " EINEN3 ,Endpoint 3IN interrupt enable" "Disabled,Enabled" bitfld.long 0x08 18. " EINEN2 ,Endpoint 2IN interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 17. " EINEN1 ,Endpoint 1IN interrupt enable" "Disabled,Enabled" bitfld.long 0x08 16. " EINEN0 ,Endpoint 0IN interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 7. " EOUTEN7 ,Endpoint 7OUT interrupt enable" "Disabled,Enabled" bitfld.long 0x08 6. " EOUTEN6 ,Endpoint 6OUT interrupt enable" "Disabled,Enabled" bitfld.long 0x08 5. " EOUTEN5 ,Endpoint 5OUT interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " EOUTEN4 ,Endpoint 4OUT interrupt enable" "Disabled,Enabled" bitfld.long 0x08 3. " EOUTEN3 ,Endpoint 3OUT interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " EOUTEN2 ,Endpoint 2OUT interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 1. " EOUTEN1 ,Endpoint 1OUT interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " EOUTEN0 ,Endpoint 0OUT interrupt enable" "Disabled,Enabled" rgroup.long 0x20040++0x03 line.long 0x00 "EP_ISTS,Endpoints Interrupt Status Register" bitfld.long 0x00 23. " EIN7 ,Endpoint 7IN interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 22. " EIN6 ,Endpoint 6IN interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 21. " EIN5 ,Endpoint 5IN interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x00 20. " EIN4 ,Endpoint 4IN interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 19. " EIN3 ,Endpoint 3IN interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 18. " EIN2 ,Endpoint 2IN interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x00 17. " EIN1 ,Endpoint 1IN interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 16. " EIN0 ,Endpoint 0IN interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " EOUT7 ,Endpoint 7OUT interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 6. " EOUT6 ,Endpoint 6OUT interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 5. " EOUT5 ,Endpoint 5OUT interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x00 4. " EOUT4 ,Endpoint 4OUT interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 3. " EOUT3 ,Endpoint 3OUT interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 2. " EOUT2 ,Endpoint 2OUT interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x00 1. " EOUT1 ,Endpoint 1OUT interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 0. " EOUT0 ,Endpoint 0OUT interrupt status" "No interrupt,Interrupt" if ((per.l(ad:0x5B110000+0x20000+0x4C)&0x8000000)==0x8000000) group.long 0x20044++0x03 line.long 0x00 "USB_PWR,Global Power Configuration Register" bitfld.long 0x00 31. " FAST_REG_ACCESS ,Fast registers access" "Disabled,Enabled" rbitfld.long 0x00 30. " FAST_REG_ACCESS_STAT ,Fast registers access status" "Disabled,Enabled" rbitfld.long 0x00 9. " STB_CLK_SWITCH_DONE ,STB clock switch enable completed" "Not completed,Completed" newline bitfld.long 0x00 8. " STB_CLK_SWITCH_EN ,Reference clock turn off enable" "Disabled,Enabled" bitfld.long 0x00 1. " PSO_DS ,Power shut off capability disable" "No,Yes" bitfld.long 0x00 0. " PSO_EN ,Power shut off capability enable" "Disabled,Enabled" else group.long 0x20044++0x03 line.long 0x00 "USB_PWR,Global Power Configuration Register" bitfld.long 0x00 31. " FAST_REG_ACCESS ,Fast registers access" "Disabled,Enabled" rbitfld.long 0x00 30. " FAST_REG_ACCESS_STAT ,Fast registers access status" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 1. " PSO_DS ,Power shut off capability disable" "No,Yes" bitfld.long 0x00 0. " PSO_EN ,Power shut off capability enable" "Disabled,Enabled" endif group.long 0x20048++0x03 line.long 0x00 "USB_CONF2,USB Configuration 2 Register" bitfld.long 0x00 0. " AHB_RETRY_EN ,AHB retry enable" "Disabled,Enabled" rgroup.long 0x2004C++0x17 line.long 0x00 "USB_CAP1,USB Capability 1 Register" bitfld.long 0x00 27. " OTG_READY ,OTG device ready" "Pure,Some" bitfld.long 0x00 26. " U2PHY_WIDTH ,USB2 PHY interface width" "8 bit,16 bit" bitfld.long 0x00 25. " U2PHY_TYPE ,USB2 PHY interface type" "UTMI,ULPI" newline bitfld.long 0x00 24. " U2PHY_EN ,USB2 PHY interface enable" "Disabled,Enabled" bitfld.long 0x00 20.--23. " U3PHY_WIDTH ,USB3 PHY width" "8 bit,16 bit,32 bit,64 bit,?..." bitfld.long 0x00 16.--19. " U3PHY_TYPE ,USB3 PHY interface type" "USB PIPE,RMMI,?..." newline bitfld.long 0x00 12.--15. " DMA_WIDTH ,DMA interface width" ",,32 bit,64 bit,?..." bitfld.long 0x00 8.--11. " DMA_TYPE ,DMA interface type" "OCP,AHB,PLB,AXI,?..." bitfld.long 0x00 4.--7. " SFR_WIDTH ,SFR interface width" "8 bit,16 bit,32 bit,64 bit,?..." newline bitfld.long 0x00 0.--3. " SFR_TYPE ,SFR interface type" "OCP,AHB,PLB,AXI,?..." line.long 0x04 "USB_CAP2,USB Capability 2 Register" bitfld.long 0x04 8.--12. " MAX_MEM_SIZE ,Maximum supported memory size" ",,,,,,,,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." hexmask.long.byte 0x04 0.--7. 1. " ACTUAL_MEM_SIZE ,Connected RAM actual memory size" line.long 0x08 "USB_CAP3,USB Capability 3 Register" hexmask.long.word 0x08 16.--31. 1. " EPIN_N ,Endpoint IN number" hexmask.long.word 0x08 0.--15. 1. " EPOUT_N ,Endpoint OUT number" line.long 0x0C "USB_CAP4,USB Capability 4: ISO HW Support Register" hexmask.long.word 0x0C 16.--31. 1. " EPINI_N ,Endpoint IN I number" hexmask.long.word 0x0C 0.--15. 1. " EPOUTI_N ,Endpoint OUT I number" line.long 0x10 "USB_CAP5,USB Capability 5: Bulk Stream HW Register" hexmask.long.word 0x10 16.--31. 1. " EPINI_N ,Endpoint IN I number" hexmask.long.word 0x10 0.--15. 1. " EPOUTI_N ,Endpoint OUT I number" line.long 0x14 "USB_CAP6,USB Capability 6: Device Controller Version Register" if (((per.l(ad:0x5B110000+0x20008))&0x2000)==0x0000) group.long 0x20064++0x0B line.long 0x00 "USB_CPKT1,Custom Packet 1 Value" line.long 0x04 "USB_CPKT2,Custom Packet 2 Value" line.long 0x08 "USB_CPKT3,Custom Packet 3 Value" else rgroup.long 0x20064++0x0B line.long 0x00 "USB_CPKT1,Custom Packet 1 Value" line.long 0x04 "USB_CPKT2,Custom Packet 2 Value" line.long 0x08 "USB_CPKT3,Custom Packet 3 Value" endif width 12. tree "Configuration Registers" group.long 0x20100++0x8B line.long 0x00 "CFG_REG1,VBUS Debouncer Configuration Register" hexmask.long.tbyte 0x00 0.--17. 1. " DEBOUNCER_CNT ,VBUS debouncer delay" line.long 0x04 "DBG_LINK1,Link 1" bitfld.long 0x04 27. " LFPS_GEN_PING_SET ,LFPS_GEN_PING set" "No effect,Set" bitfld.long 0x04 26. " RXDET_BREAK_DIS_SET ,RXDET_BREAK_DIS set" "No effect,Set" bitfld.long 0x04 25. " LFPS_MIN_GEN_U1_EXIT_SET ,LFPS_MIN_GEN_U1_EXIT set" "No effect,Set" newline bitfld.long 0x04 24. " LFPS_MIN_DET_U1_EXIT_SET ,LFPS_MIN_DET_U1_EXIT set" "No effect,Set" bitfld.long 0x04 17.--21. " LFPS_GEN_PING ,LFPS generation ping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16. " RXDET_BREAK_DIS ,Far end receiver termination possibility" "Terminated,Not terminated" newline hexmask.long.byte 0x04 8.--15. 1. " LFPS_MIN_GEN_U1_EXIT ,PHYTXELECIDLE deassertion minimum time" hexmask.long.byte 0x04 0.--7. 1. " LFPS_MIN_DET_U1_EXIT ,LFPS decoding minimum time" line.long 0x08 "DBG_LINK2,Link 2" bitfld.long 0x08 31. " TXDET_DVAL_SET ,TXDET_DVAL set" "No effect,Set" bitfld.long 0x08 30. " PHYRXVAL_DVAL_SET ,PHYRXVAL_DVAL set" "No effect,Set" bitfld.long 0x08 29. " RXEQTR_DVAL_SET ,RXEQTR_DVAL set" "No effect,Set" newline bitfld.long 0x08 28. " RXEQTR_AVAL_SET ,RXEQTR_AVAL set" "No effect,Set" bitfld.long 0x08 24.--26. " TXDET_DVAL ,TXDET deassertion value" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 16.--23. 1. " PHYRXVAL_DVAL ,PHY RX valid latency deassertion value" newline hexmask.long.byte 0x08 8.--15. 1. " RXEQTR_DVAL ,RX EQ training deassertion time" hexmask.long.byte 0x08 0.--7. 1. " RXEQTR_AVAL ,RX EQ training assertion time" line.long 0x0C "CFG_REG4,USB3 Configuration 4 Register" bitfld.long 0x0C 30.--31. " RXDETECT_QUIET_TIMEOUT_PRESCALE ,RXDETECT_QUIET_TIMEOUT prescaler" "8 ns,1 us,100 us,No clock" hexmask.long.byte 0x0C 0.--7. 1. " RXDETECT_QUIET_TIMEOUT ,RX detect quiet timeout" line.long 0x10 "CFG_REG5,USB3 Configuration 5 Register" bitfld.long 0x10 30.--31. " U3_HDSK_FAIL_TIMEOUT_PRESCALE ,U3_HDSK_FAIL_TIMEOUT prescaler" "8 ns,1 us,100 us,No clock" hexmask.long.word 0x10 0.--10. 1. " U3_HDSK_FAIL_TIMEOUT ,U3 HDSK fail timeout" line.long 0x14 "CFG_REG6,USB3 Configuration 6 Register" bitfld.long 0x14 30.--31. " SSINACTIVE_QUIET_TIMEOUT_PRESCALE ,SSINACTIVE_QUIET_TIMEOUT prescaler" "8 ns,1 us,100 us,No clock" hexmask.long.byte 0x14 0.--7. 1. " SSINACTIVE_QUIET_TIMEOUT ,SS inactive quiet timeout" line.long 0x18 "CFG_REG7,USB3 Configuration 7 Register" bitfld.long 0x18 30.--31. " POLLING_LFPS_TIMEOUT_PRESCALE ,POLLING_LFPS_TIMEOUT prescaler" "8 ns,1 us,100 us,No clock" hexmask.long.word 0x18 0.--12. 1. " POLLING_LFPS_TIMEOUT ,Polling LFPS timeout" line.long 0x1C "CFG_REG8,USB3 Configuration 8 Register" bitfld.long 0x1C 30.--31. " POLLING_ACTIVE_TIMEOUT_PRESCALE ,POLLING_ACTIVE_TIMEOUT prescaler" "8 ns,1 us,100 us,No clock" hexmask.long.word 0x1C 0.--9. 1. " POLLING_ACTIVE_TIMEOUT ,Polling active timeout" line.long 0x20 "CFG_REG9,USB3 Configuration 9 Register" bitfld.long 0x20 30.--31. " POLLING_IDLE_TIMEOUT_PRESCALE ,POLLING_IDLE_TIMEOUT prescaler" "8 ns,1 us,100 us,No clock" bitfld.long 0x20 0.--4. " POLLING_IDLE_TIMEOUT ,Polling idle timeout" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x24 "CFG_REG10,USB3 Configuration 10 Register" bitfld.long 0x24 30.--31. " POLLING_CONF_TIMEOUT_PRESCALE ,POLLING_CONF_TIMEOUT prescaler" "8 ns,1 us,100 us,No clock" hexmask.long.byte 0x24 0.--7. 1. " POLLING_CONF_TIMEOUT ,Polling configuration timeout" line.long 0x28 "CFG_REG11,USB3 Configuration 11 Register" bitfld.long 0x28 30.--31. " RECOVERY_ACTIVE_TIMEOUT_PRESCALE ,RECOVERY_ACTIVE_TIMEOUT prescaler" "8 ns,1 us,100 us,No clock" hexmask.long.byte 0x28 0.--7. 1. " RECOVERY_ACTIVE_TIMEOUT ,Recovery active timeout" line.long 0x2C "CFG_REG12,USB3 Configuration 12 Register" bitfld.long 0x2C 30.--31. " RECOVERY_CONF_TIMEOUT_PRESCALE ,RECOVERY_CONF_TIMEOUT prescaler" "8 ns,1 us,100 us,No clock" hexmask.long.byte 0x2C 0.--7. 1. " RECOVERY_CONF_TIMEOUT ,Recovery configuration timeout" line.long 0x30 "CFG_REG13,USB3 Configuration 13 Register" bitfld.long 0x30 30.--31. " RECOVERY_IDLE_TIMEOUT_PRESCALE ,RECOVERY_IDLE_TIMEOUT prescaler" "8 ns,1 us,100 us,No clock" bitfld.long 0x30 0.--4. " RECOVERY_IDLE_TIMEOUT ,Recovery idle timeout" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x34 "CFG_REG14,USB3 Configuration 14 Register" bitfld.long 0x34 30.--31. " HOTRESET_ACTIVE_TIMEOUT_PRESCALE ,HOTRESET_ACTIVE_TIMEOUT prescaler" "8 ns,1 us,100 us,No clock" hexmask.long.byte 0x34 0.--7. 1. " HOTRESET_ACTIVE_TIMEOUT ,Hot reset active timeout" line.long 0x38 "CFG_REG15,USB3 Configuration 15 Register" bitfld.long 0x38 30.--31. " HOTRESET_EXIT_TIMEOUT_PRESCALE ,HOTRESET_EXIT_TIMEOUT prescaler" "8 ns,1 us,100 us,No clock" bitfld.long 0x38 0.--4. " HOTRESET_EXIT_TIMEOUT ,Hot reset exit timeout" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x3C "CFG_REG16,USB3 Configuration 16 Register" bitfld.long 0x3C 30.--31. " LFPS_PING_REPEAT_PRESCALE ,LFPS_PING_REPEAT prescaler" "8 ns,1 us,100 us,No clock" hexmask.long.word 0x3C 0.--11. 1. " LFPS_PING_REPEAT ,LFPS ping repeat" line.long 0x40 "CFG_REG17,USB3 Configuration 17 Register" bitfld.long 0x40 30.--31. " PENDING_HP_TIMEOUT_PRESCALE ,PENDING_HP_TIMEOUT prescaler" "8 ns,1 us,100 us,No clock" hexmask.long.word 0x40 0.--9. 1. " PENDING_HP_TIMEOUT ,Pending HP timeout" line.long 0x44 "CFG_REG18,USB3 Configuration 18 Register" bitfld.long 0x44 30.--31. " CREDIT_HP_TIMEOUT_PRESCALE ,CREDIT_HP_TIMEOUT prescaler" "8 ns,1 us,100 us,No clock" hexmask.long.byte 0x44 0.--6. 1. " CREDIT_HP_TIMEOUT ,Credit HP timeout" line.long 0x48 "CFG_REG19,USB3 Configuration 19 Register" bitfld.long 0x48 30.--31. " LUP_TIMEOUT_PRESCALE ,LUP_TIMEOUT prescaler" "8 ns,1 us,100 us,No clock" hexmask.long.word 0x48 0.--9. 1. " LUP_TIMEOUT ,LUP timeout" line.long 0x4C "CFG_REG20,USB3 Configuration 20 Register" bitfld.long 0x4C 30.--31. " LDN_TIMEOUT_PRESCALE ,LDN_TIMEOUT prescaler" "8 ns,1 us,100 us,No clock" hexmask.long.byte 0x4C 0.--7. 1. " LDN_TIMEOUT ,LDN timeout" line.long 0x50 "CFG_REG21,USB3 Configuration 21 Register" bitfld.long 0x50 30.--31. " PM_LC_TIMEOUT_PRESCALE ,PM_LC_TIMEOUT prescaler" "8 ns,1 us,100 us,No clock" hexmask.long.word 0x50 0.--9. 1. " PM_LC_TIMEOUT ,PM LC timeout" line.long 0x54 "CFG_REG22,USB3 Configuration 22 Register" bitfld.long 0x54 30.--31. " PM_ENTRY_TIMEOUT_PRESCALE ,PM_ENTRY_TIMEOUT prescaler" "8 ns,1 us,100 us,No clock" hexmask.long.word 0x54 0.--10. 1. " PM_ENTRY_TIMEOUT ,PM entry timeout" line.long 0x58 "CFG_REG23,USB3 Configuration 23 Register" bitfld.long 0x58 30.--31. " UX_EXIT_TIMEOUT_PRESCALE ,UX_EXIT_TIMEOUT prescaler" "8 ns,1 us,100 us,No clock" hexmask.long.byte 0x58 0.--6. 1. " UX_EXIT_TIMEOUT ,UX exit timeout" line.long 0x5C "CFG_REG24,USB3 Configuration 24 Register" hexmask.long.tbyte 0x5C 0.--22. 1. " LFPS_DET_RESET_MIN ,LFPS DET reset minimum" line.long 0x60 "CFG_REG25,USB3 Configuration 25 Register" hexmask.long.tbyte 0x60 0.--23. 1. " LFPS_DET_RESET_MAX ,LFPS DET reset maximum" line.long 0x64 "CFG_REG26,USB3 Configuration 26 Register" hexmask.long.byte 0x64 0.--6. 1. " LFPS_DET_POLLING_MIN ,LFPS DET polling minimum" line.long 0x68 "CFG_REG27,USB3 Configuration 27 Register" hexmask.long.byte 0x68 0.--7. 1. " LFPS_DET_POLLING_MAX ,LFPS DET polling maximum" line.long 0x6C "CFG_REG28,USB3 Configuration 28 Register" bitfld.long 0x6C 0.--2. " LFPS_DET_PING_MIN ,LFPS DET ping minimum" "8 ns,16 ns,24 ns,32 ns,40 ns,48 ns,56 ns,64 ns" line.long 0x70 "CFG_REG29,USB3 Configuration 29 Register" bitfld.long 0x70 0.--4. " LFPS_DET_PING_MAX ,LFPS DET ping maximum" "8 ns,16 ns,24 ns,32 ns,40 ns,48 ns,56 ns,64 ns,72 ns,80 ns,88 ns,96 ns,104 ns,112 ns,120 ns,128 ns,136 ns,144 ns,152 ns,160 ns,168 ns,176 ns,184 ns,192 ns,200 ns,208 ns,216 ns,224 ns,232 ns,240 ns,248 ns,256 ns" line.long 0x74 "CFG_REG30,USB3 Configuration 30 Register" bitfld.long 0x74 0.--5. " LFPS_DET_U1EXIT_MIN ,LFPS DET U1 exit minimum" "8 ns,16 ns,24 ns,32 ns,40 ns,48 ns,56 ns,64 ns,72 ns,80 ns,88 ns,96 ns,104 ns,112 ns,120 ns,128 ns,136 ns,144 ns,152 ns,160 ns,168 ns,176 ns,184 ns,192 ns,200 ns,208 ns,216 ns,224 ns,232 ns,240 ns,248 ns,256 ns,264 ns,272 ns,280 ns,288 ns,296 ns,304 ns,312 ns,320 ns,328 ns,336 ns,344 ns,352 ns,360 ns,368 ns,376 ns,384 ns,392 ns,400 ns,408 ns,416 ns,424 ns,432 ns,440 ns,448 ns,456 ns,464 ns,472 ns,480 ns,488 ns,496 ns,504 ns,512 ns" line.long 0x78 "CFG_REG31,USB3 Configuration 31 Register" hexmask.long.byte 0x78 0.--6. 1. " LFPS_DET_U1EXIT_MAX ,LFPS DET U1 exit maximum" line.long 0x7C "CFG_REG32,USB3 Configuration 32 Register" bitfld.long 0x7C 0.--5. " LFPS_DET_U2EXIT_MIN ,LFPS DET U2 exit minimum" "8 ns,16 ns,24 ns,32 ns,40 ns,48 ns,56 ns,64 ns,72 ns,80 ns,88 ns,96 ns,104 ns,112 ns,120 ns,128 ns,136 ns,144 ns,152 ns,160 ns,168 ns,176 ns,184 ns,192 ns,200 ns,208 ns,216 ns,224 ns,232 ns,240 ns,248 ns,256 ns,264 ns,272 ns,280 ns,288 ns,296 ns,304 ns,312 ns,320 ns,328 ns,336 ns,344 ns,352 ns,360 ns,368 ns,376 ns,384 ns,392 ns,400 ns,408 ns,416 ns,424 ns,432 ns,440 ns,448 ns,456 ns,464 ns,472 ns,480 ns,488 ns,496 ns,504 ns,512 ns" line.long 0x80 "CFG_REG33,USB3 Configuration 33 Register" hexmask.long.tbyte 0x80 0.--17. 1. " LFPS_DET_U2EXIT_MAX ,LFPS DET U2 exit maximum" line.long 0x84 "CFG_REG34,USB3 Configuration 34 Register" bitfld.long 0x84 0.--5. " LFPS_DET_U3EXIT_MIN ,LFPS DET U3 exit minimum" "8 ns,16 ns,24 ns,32 ns,40 ns,48 ns,56 ns,64 ns,72 ns,80 ns,88 ns,96 ns,104 ns,112 ns,120 ns,128 ns,136 ns,144 ns,152 ns,160 ns,168 ns,176 ns,184 ns,192 ns,200 ns,208 ns,216 ns,224 ns,232 ns,240 ns,248 ns,256 ns,264 ns,272 ns,280 ns,288 ns,296 ns,304 ns,312 ns,320 ns,328 ns,336 ns,344 ns,352 ns,360 ns,368 ns,376 ns,384 ns,392 ns,400 ns,408 ns,416 ns,424 ns,432 ns,440 ns,448 ns,456 ns,464 ns,472 ns,480 ns,488 ns,496 ns,504 ns,512 ns" line.long 0x88 "CFG_REG35,USB3 Configuration 35 Register" hexmask.long.tbyte 0x88 0.--20. 1. " LFPS_DET_U3EXIT_MAX ,LFPS DET U3 exit maximum" group.long 0x201AC++0x6F line.long 0x00 "CFG_REG36,USB Configuration 36 Register" bitfld.long 0x00 0.--4. " LFPS_GEN_PING ,LFPS GEN ping" "8 ns,16 ns,24 ns,32 ns,40 ns,48 ns,56 ns,64 ns,72 ns,80 ns,88 ns,96 ns,104 ns,112 ns,120 ns,128 ns,136 ns,144 ns,152 ns,160 ns,168 ns,176 ns,184 ns,192 ns,200 ns,208 ns,216 ns,224 ns,232 ns,240 ns,248 ns,256 ns" line.long 0x04 "CFG_REG37,USB Configuration 37 Register" hexmask.long.byte 0x04 0.--7. 1. " LFPS_GEN_POLLING ,LFPS GEN polling" line.long 0x08 "CFG_REG38,USB Configuration 38 Register" hexmask.long.tbyte 0x08 0.--17. 1. " LFPS_GEN_U1EXIT ,LFPS GEN U1 exit" line.long 0x0C "CFG_REG39,USB Configuration 39 Register" hexmask.long.tbyte 0x0C 0.--20. 1. " LFPS_GEN_U3EXIT ,LFPS GEN U3 exit" line.long 0x10 "CFG_REG40,USB Configuration 40 Register" hexmask.long.byte 0x10 0.--6. 1. " LFPS_MIN_GEN_U1EXIT ,LFPS minimum GEN U1 exit" line.long 0x14 "CFG_REG41,USB Configuration 41 Register" hexmask.long.word 0x14 0.--14. 1. " LFPS_MIN_GEN_U2EXIT ,LFPS minimum GEN U2 exit" line.long 0x18 "CFG_REG42,USB Configuration 42 Register" hexmask.long.word 0x18 0.--10. 1. " LFPS_POLLING_REPEAT ,LFPS polling repeat" line.long 0x1C "CFG_REG43,USB Configuration 43 Register" hexmask.long.word 0x1C 0.--10. 1. " LFPS_POLLING_MAX_TREPEAT ,LFPS polling maximum T repeat" line.long 0x20 "CFG_REG44,USB Configuration 44 Register" hexmask.long.word 0x20 0.--10. 1. " LFPS_POLLING_MIN_TREPEAT ,LFPS polling minimum T repeat" line.long 0x24 "CFG_REG45,USB Configuration 45 Register" bitfld.long 0x24 30.--31. " ITP_WAKEUP_TIMEOUT_PRESCALE ,ITP_WAKEUP_TIMEOUT prescaler" "8 ns,1 us,100 us,No clock" hexmask.long.byte 0x24 0.--6. 1. " ITP_WAKEUP_TIMEOUT ,ITP wakeup timeout" line.long 0x28 "CFG_REG46,USB Configuration 46 Register" hexmask.long.word 0x28 0.--15. 1. " TSEQ_QUANTITY ,TSEQ training sequences count" line.long 0x2C "CFG_REG47,USB Configuration 47 Register" hexmask.long.tbyte 0x2C 0.--19. 1. " ERDY_TIMEOUT_CNT ,ERDY timeout count" line.long 0x30 "CFG_REG48,USB Configuration 48 Register" hexmask.long.tbyte 0x30 0.--17. 1. " TWTRSTFS_J_CNT ,TWTRSTFS J count" line.long 0x34 "CFG_REG49,USB Configuration 49 Register" hexmask.long.word 0x34 0.--15. 1. " TUCH_CNT ,TUCH count" line.long 0x38 "CFG_REG50,USB Configuration 50 Register" hexmask.long.word 0x38 0.--11. 1. " TWAITCHK_CNT ,TWAITCHK count" line.long 0x3C "CFG_REG51,USB Configuration 51 Register" hexmask.long.tbyte 0x3C 0.--16. 1. " TWTFS_CNT ,TWTFS count" line.long 0x40 "CFG_REG52,USB Configuration 52 Register" hexmask.long.tbyte 0x40 0.--16. 1. " TWTREV_CNT ,TWTREV count" line.long 0x44 "CFG_REG53,USB Configuration 53 Register" hexmask.long.word 0x44 0.--14. 1. " TWTRSTHS_CNT ,TWTRSTHS count" line.long 0x48 "CFG_REG54,USB Configuration 54 Register" hexmask.long.tbyte 0x48 0.--17. 1. " TWTRSM_CNT ,TWTRSM count" line.long 0x4C "CFG_REG55,USB Configuration 55 Register" hexmask.long.word 0x4C 0.--15. 1. " TDRSMUP_CNT ,TDRSMUP count" line.long 0x50 "CFG_REG56,USB Configuration 56 Register" bitfld.long 0x50 0.--5. " TOUTHS_CNT ,TOUTHS count" "0 ns,33.3 ns,66.6 ns,99.9 ns,133.2 ns,166.5 ns,199.8 ns,233.1 ns,266.4 ns,299.7 ns,333 ns,366.3 ns,399.6 ns,432.9 ns,466.2 ns,499.5 ns,532.8 ns,566.1 ns,599.4 ns,632.7 ns,666 ns,699.3 ns,732.6 ns,765.9 ns,799.2 ns,832.5 ns,865.8 ns,899.1 ns,932.4 ns,965.7 ns,999 ns,1.03 us,1.07 us,1.1 us,1.13 us,1.17 us,1.2 us,1.23 us,1.27 us,1.3 us,1.33 us,1.37 us,1.4 us,1.43 us,1.47 us,1.5 us,1.53 us,1.57 us,1.6 us,1.63 us,1.66 us,1.7 us,1.73 us,1.76 us,1.8 us,1.83 us,1.86 us,1.9 us,1.93 us,1.96 us,2 us,2.03 us,2.06 us,2.1 us" line.long 0x54 "CFG_REG57,USB Configuration 57 Register" bitfld.long 0x54 0.--1. " LFPS_DEB_WIDTH ,LFPS debouncer delay" ",1,2,?..." line.long 0x58 "CFG_REG58,USB Configuration 58 Register" hexmask.long.tbyte 0x58 0.--17. 1. " LFPS_GEN_U2EXIT ,LFPS GEN U2 exit" line.long 0x5C "CFG_REG59,USB Configuration 59 Register" hexmask.long.word 0x5C 0.--15. 1. " LFPS_MIN_GEN_U3EXIT ,LFPS minimum GEN U3 exit" line.long 0x60 "CFG_REG60,USB Configuration 60 Register" hexmask.long.byte 0x60 0.--6. 1. " PORT_CONFIG_TIMEOUT ,Port configuration timeout" line.long 0x64 "CFG_REG61,USB Configuration 61 Register" hexmask.long.word 0x64 0.--10. 1. " LFPS_POL_LFPS_TO_RXEQ ,LFPS POL LFPS to RXEQ" line.long 0x68 "CFG_REG62,USB Configuration 62 Register" bitfld.long 0x68 30.--31. " PHY_TX_LATENCY_PRESCALE ,PHY_TX_LATENCY prescaler" "8 ns,1 us,100 us,No clock" bitfld.long 0x68 0.--5. " PHY_TX_LATENCY ,PHY TX latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x6C "CFG_REG63,USB Configuration 63 Register" hexmask.long.word 0x6C 0.--14. 1. " U2_INACTIVITY_TMOUT ,U2 inactivity timeout" group.long 0x20220++0x0B line.long 0x00 "CFG_REG64,USB Configuration 64 Register" hexmask.long.byte 0x00 0.--6. 1. " TFILTSE0 ,TFILT SE0" line.long 0x04 "CFG_REG65,USB Configuration 65 Register" hexmask.long.byte 0x04 0.--6. 1. " TFILT ,TFILT" line.long 0x08 "CFG_REG66,USB Configuration 66 Register" hexmask.long.byte 0x08 0.--6. 1. " TWTRSTFS_SE0 ,TWTRSTFS SE0" tree.end newline width 16. if ((per.l(ad:0x5B110000+0x20000+0x4C)&0xF00)==0x300) group.long 0x20300++0x13 line.long 0x00 "DMA_AXI_CTRL,DMA AXI Master Control Register" bitfld.long 0x00 24.--25. " MAWLOCK ,MAW lock" "0,1,2,3" bitfld.long 0x00 20.--23. " MAWCACHE ,MAW cache" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--18. " MAWPROT ,MAW prot" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--9. " MARLOCK ,MAR lock" "0,1,2,3" bitfld.long 0x00 4.--7. " MARCACHE ,MAR cache" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--2. " MARPROT ,MAR prot" "0,1,2,3,4,5,6,7" line.long 0x04 "DMA_AXI_ID,DMA AXI Master ID Register" bitfld.long 0x04 16.--20. " MAR_ID ,MAR ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--4. " MAW_ID ,MAW ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "DMA_AXI_CAP,DMA AXI Master Extended Capability Register" rbitfld.long 0x08 30. " AXI_IDLE ,AXI idle" "Not idle,Idle" eventfld.long 0x08 29. " AXI_SLVERR ,AXI slave error" "No error,Error" eventfld.long 0x08 28. " AXI_DECERR ,AXI decode error" "No error,Error" newline bitfld.long 0x08 21. " AXI_SLVERR_EN ,AXI slave error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 20. " AXI_DECERR_EN ,AXI decode error interrupt enable" "Disabled,Enabled" line.long 0x0C "DMA_AXI_CTRL0,DMA AXI Master Control 0 Register" bitfld.long 0x0C 0.--3. " B_MAX ,Maximum burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "DMA_AXI_CTRL1,DMA AXI Master Control 1 Register" bitfld.long 0x10 16.--20. " WOT ,Outstanding write transaction count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 0.--4. " ROT ,Outstanding read transaction count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else hgroup.long 0x20300++0x03 hide.long 0x00 "DMA_AXI_CTRL,DMA AXI Master Control Register" hgroup.long 0x20304++0x03 hide.long 0x00 "DMA_AXI_ID,DMA AXI Master ID Register" hgroup.long 0x20308++0x03 hide.long 0x00 "DMA_AXI_CAP,DMA AXI Master Extended Capability Register" hgroup.long 0x2030C++0x03 hide.long 0x00 "DMA_AXI_CTRL0,DMA AXI Master Control 0 Register" hgroup.long 0x20310++0x03 hide.long 0x00 "DMA_AXI_CTRL1,DMA AXI Master Control 1 Register" endif width 0x0B tree.end ; tree "Non-core" ; base ad:0x00 ; %include imx8x/usb3nc.ph ; tree.end tree.end tree.end tree.open "Display/Imaging/Camera" tree.open "MIPI-CSI2" tree.open "Parallel Camera" tree "I2C (I2C Controller)" base ad:0x58266000 width 8. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number" line.long 0x04 "PARAM,Parameter Register" bitfld.long 0x04 8.--11. " MRXFIFO ,Master receive FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x04 0.--3. " MTXFIFO ,Master transmit FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" group.long 0x10++0x13 line.long 0x00 "MCR,Master Control Register" bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset" bitfld.long 0x00 3. " DBGEN ,Debug enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " MEN ,Master enable" "Disabled,Enabled" line.long 0x04 "MSR,Master Status Register" rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x04 24. " MBF ,Master busy flag" "Idle,Busy" eventfld.long 0x04 14. " DMF ,Data match flag" "Not received,Received" eventfld.long 0x04 13. " PLTF ,Pin low timeout flag" "Not occurred/disabled,Occurred" newline eventfld.long 0x04 12. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x04 11. " ALF ,Arbitration lost flag" "Not lost,Lost" eventfld.long 0x04 10. " NDF ,NACK detect flag" "Not detected,Detected" eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected" newline eventfld.long 0x04 8. " EPF ,End packet flag" "Not generated/Repeated,Generated/Repeated" rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "MIER,Master Interrupt Enable Register" bitfld.long 0x08 14. " DMIE ,Data match interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " PLTIE ,Pin low timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " FEIE ,FIFO error interrupt disable" "No,Yes" newline bitfld.long 0x08 11. " ALIE ,Arbitration lost interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " NDIE ,NACK detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " EPIE ,End packet interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "MDER,Master DMA Enable Register" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" line.long 0x10 "MCFGR0,Master Configuration Register 0" bitfld.long 0x10 9. " RDMO ,Receive data match only" "Stored,Discarded" bitfld.long 0x10 8. " CIRFIFO ,Circular FIFO enable" "Disabled,Enabled" bitfld.long 0x10 2. " HRSEL ,Host request select" "HREQ pin,Input trigger" newline bitfld.long 0x10 1. " HRPOL ,Host request polarity" "Active low,Active high" bitfld.long 0x10 0. " HREN ,Host request enable" "Disabled,Enabled" newline if (((per.l(ad:0x58266000+0x10))&0x01)==0x01) rgroup.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Disabled,,1st word = MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "SCL,SCL or SDA" newline bitfld.long 0x00 9. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "No effect,Enabled" bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" else group.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Disabled,,1st word = MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "On SCL low too long,On SCL or SDA low too long" newline bitfld.long 0x00 9. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "No effect,Enabled" bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" endif newline if ((((per.l(ad:0x58266000+0x10))&0x01)==0x00)||(((per.l(ad:0x58266000+0x14))&0x1000000)==0x00)) group.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" else rgroup.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" endif if (((per.l(ad:0x58266000+0x10))&0x01)==0x01) rgroup.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x58++0x03 line.long 0x00 "MFCR,Master FIFO Control Register" bitfld.long 0x00 16.--17. " RXWATER ,Receive FIFO watermark" "0,1,2,3" bitfld.long 0x00 0.--1. " TXWATER ,Transmit FIFO watermark" "0,1,2,3" rgroup.long 0x5C++0x03 line.long 0x00 "MFSR,Master FIFO Status Register" bitfld.long 0x00 16.--18. " RXCOUNT ,Receive FIFO count" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " TXCOUNT ,Transmit FIFO count" "0,1,2,3,4,5,6,7" newline wgroup.long 0x60++0x03 line.long 0x00 "MTDR,Master Transmit Data Register" bitfld.long 0x00 8.--10. " CMD ,Command data" "Transmit,Receive,Generate STOP,Receive and discard,START and transmit,START and transmit (NACK returned),START and transmit (high speed mode),START and transmit high speed mode (NACK returned)" newline hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data" newline hgroup.long 0x70++0x03 hide.long 0x00 "MRDR,Master Receive Data Register" in newline group.long 0x110++0x0F line.long 0x00 "SCR,Slave Control Register" bitfld.long 0x00 9. " RRF ,Receive FIFO reset" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Transmit FIFO reset" "No effect,Reset" bitfld.long 0x00 5. " FILTDZ ,Filter doze enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " FILTEN ,Filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " SEN ,Slave enable" "Disabled,Enabled" line.long 0x04 "SSR,Slave Status Register" rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x04 24. " SBF ,Slave busy flag" "Idle,Busy" rbitfld.long 0x04 15. " SARF ,SMBus alert response flag" "Not detected,Detected" rbitfld.long 0x04 14. " GCF ,General call flag" "Not detected,Detected" newline rbitfld.long 0x04 13. " AM1F ,Address match 1 flag" "Not matched,Matched" rbitfld.long 0x04 12. " AM0F ,Address match 0 flag" "Not matched,Matched" eventfld.long 0x04 11. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x04 10. " BEF ,Bit error flag" "No error,Error" newline eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected" eventfld.long 0x04 8. " RSF ,Repeated start flag" "Not detected,Detected" rbitfld.long 0x04 3. " TAF ,Transmit ACK flag" "Not required,Required" rbitfld.long 0x04 2. " AVF ,Address valid flag" "Invalid,Valid" newline rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "SIER,Slave Interrupt Enable Register" bitfld.long 0x08 15. " SARIE ,SMBus alert response interrupt enable" "Disabled,Enabled" bitfld.long 0x08 14. " GCIE ,General call interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " AM1F ,Address match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " AM0IE ,Address match 0 interrupt disable" "No,Yes" newline bitfld.long 0x08 11. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " BEIE ,Bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 8. " RSIE ,Repeated start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " TAIE ,Transmit ACK interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " AVIE ,Address valid interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "SDER,Slave DMA Enable Register" bitfld.long 0x0C 2. " AVDE ,Address valid DMA enable" "Disabled,Enabled" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" newline if (((per.l(ad:0x58266000+0x110))&0x01)==0x01) rgroup.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration match" "0 (7-bit),0 (10-bit),0 (7-bit) / 1 (7-bit),0 (10-bit) / 1 (10-bit),0 (7-bit) / 1 (10-bit),0 (10-bit) / 1 (7-bit),From 0 (7-bit) to 1 (7-bit),From 0 (10-bit) to 1 (10-bit)" bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" bitfld.long 0x00 12. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return data / clear RDF,Return address / clear AVF" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer,On TDR empty" bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration match" "0 (7-bit),0 (10-bit),0 (7-bit) / 1 (7-bit),0 (10-bit) / 1 (10-bit),0 (7-bit) / 1 (10-bit),0 (10-bit) / 1 (7-bit),From 0 (7-bit) to 1 (7-bit),From 0 (10-bit) to 1 (10-bit)" bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" bitfld.long 0x00 12. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return data / clear RDF,Return address / clear AVF" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer,On TDR empty" bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline if (((per.l(ad:0x58266000+0x110))&0x01)==0x01) rgroup.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" else group.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" endif rgroup.long 0x150++0x03 line.long 0x00 "SASR,Slave Address Status Register" bitfld.long 0x00 14. " ANV ,Address invalid" "No,Yes" hexmask.long.word 0x00 0.--10. 0x01 " RADDR ,Received address" if (((per.l(ad:0x58266000+0x124))&0x08)==0x08) group.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,NACK transmit" "ACK,NACK" else rgroup.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,NACK transmit" "ACK,NACK" endif wgroup.long 0x160++0x03 line.long 0x00 "STDR,Slave Transmit Data Register" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data" rgroup.long 0x170++0x03 line.long 0x00 "SRDR,Slave Receive Data Register" bitfld.long 0x00 15. " SOF ,Start of frame" "Not the first data word,First data word" bitfld.long 0x00 14. " RXEMPTY ,RX empty" "Not empty,Empty" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data receive" width 0x0B tree.end tree "PWM (Pulse Width Modulation)" base ad:0x58264000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO water mark (FIFO empty flag set threshold)" ">= 1 empty slot,>= 2 empty slots,>= 3 empty slots,>= 4 empty slots" bitfld.long 0x00 25. " STOPEN ,Stop mode enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait mode enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " DBGEN ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte data swap control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word data swap control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM output configuration" "Set=rollover/Cleared=comparison,Set=comparison/Cleared=rollover,Disconnected,Disconnected" newline bitfld.long 0x00 16.--17. " CLKSRC ,Clock source select" "Off,IPG_CLK,IPG_CLK_HIGHFREQ,IPG_CLK_32K" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter clock prescaler value" bitfld.long 0x00 3. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample repeat" "Once,Twice,Four times,Eight times" newline bitfld.long 0x00 0. " EN ,PWM enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO write error status" "No error,Error" eventfld.long 0x04 5. " CMP ,Compare event status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over event status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO empty status" "Not empty,Empty" newline rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO available" "No available,1 word,2 words,3 words,4 words,?..." line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO empty interrupt enable" "Disabled,Enabled" line.long 0x0C "PWMSAR,PWM Sample Register" hexmask.long.word 0x0C 0.--15. 1. " SAMPLE ,Sample value" line.long 0x10 "PWMPR,PWM Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Period value" rgroup.long 0x14++0x03 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" width 0x0B tree.end tree "GPIO (General Purpose Input/Output)" base ad:0x58262000 width 11. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data Register" bitfld.long 0x00 31. " DR[31] ,Data bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,Data bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,Data bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,Data bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,Data bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,Data bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,Data bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,Data bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,Data bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,Data bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,Data bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,Data bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,Data bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,Data bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,Data bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,Data bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,Data bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,Data bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,Data bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,Data bit 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,Data bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,Data bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,Data bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,Data bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,Data bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,Data bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,Data bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,Data bit 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,Data bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,Data bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,Data bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,Data bit 0" "Low,High" line.long 0x04 "GDIR,GPIO Direction Register" bitfld.long 0x04 31. " GDIR[31] ,GPIO direction 31 bit" "Input,Output" bitfld.long 0x04 30. " [30] ,GPIO direction 30 bit" "Input,Output" bitfld.long 0x04 29. " [29] ,GPIO direction 29 bit" "Input,Output" bitfld.long 0x04 28. " [28] ,GPIO direction 28 bit" "Input,Output" newline bitfld.long 0x04 27. " [27] ,GPIO direction 27 bit" "Input,Output" bitfld.long 0x04 26. " [26] ,GPIO direction 26 bit" "Input,Output" bitfld.long 0x04 25. " [25] ,GPIO direction 25 bit" "Input,Output" bitfld.long 0x04 24. " [24] ,GPIO direction 24 bit" "Input,Output" newline bitfld.long 0x04 23. " [23] ,GPIO direction 23 bit" "Input,Output" bitfld.long 0x04 22. " [22] ,GPIO direction 22 bit" "Input,Output" bitfld.long 0x04 21. " [21] ,GPIO direction 21 bit" "Input,Output" bitfld.long 0x04 20. " [20] ,GPIO direction 20 bit" "Input,Output" newline bitfld.long 0x04 19. " [19] ,GPIO direction 19 bit" "Input,Output" bitfld.long 0x04 18. " [18] ,GPIO direction 18 bit" "Input,Output" bitfld.long 0x04 17. " [17] ,GPIO direction 17 bit" "Input,Output" bitfld.long 0x04 16. " [16] ,GPIO direction 16 bit" "Input,Output" newline bitfld.long 0x04 15. " [15] ,GPIO direction 15 bit" "Input,Output" bitfld.long 0x04 14. " [14] ,GPIO direction 14 bit" "Input,Output" bitfld.long 0x04 13. " [13] ,GPIO direction 13 bit" "Input,Output" bitfld.long 0x04 12. " [12] ,GPIO direction 12 bit" "Input,Output" newline bitfld.long 0x04 11. " [11] ,GPIO direction 11 bit" "Input,Output" bitfld.long 0x04 10. " [10] ,GPIO direction 10 bit" "Input,Output" bitfld.long 0x04 9. " [9] ,GPIO direction 9 bit" "Input,Output" bitfld.long 0x04 8. " [8] ,GPIO direction 8 bit" "Input,Output" newline bitfld.long 0x04 7. " [7] ,GPIO direction 7 bit" "Input,Output" bitfld.long 0x04 6. " [6] ,GPIO direction 6 bit" "Input,Output" bitfld.long 0x04 5. " [5] ,GPIO direction 5 bit" "Input,Output" bitfld.long 0x04 4. " [4] ,GPIO direction 4 bit" "Input,Output" newline bitfld.long 0x04 3. " [3] ,GPIO direction 3 bit" "Input,Output" bitfld.long 0x04 2. " [2] ,GPIO direction 2 bit" "Input,Output" bitfld.long 0x04 1. " [1] ,GPIO direction 1 bit" "Input,Output" bitfld.long 0x04 0. " [0] ,GPIO direction 0 bit" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO Pad Status Register" bitfld.long 0x00 31. " PSR[31] ,GPIO pad status bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,GPIO pad status bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,GPIO pad status bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,GPIO pad status bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,GPIO pad status bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,GPIO pad status bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,GPIO pad status bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,GPIO pad status bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,GPIO pad status bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,GPIO pad status bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,GPIO pad status bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,GPIO pad status bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,GPIO pad status bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,GPIO pad status bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,GPIO pad status bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,GPIO pad status bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,GPIO pad status bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,GPIO pad status bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,GPIO pad status bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,GPIO pad status bit 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,GPIO pad status bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,GPIO pad status bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,GPIO pad status bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,GPIO pad status bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,GPIO pad status bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,GPIO pad status bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,GPIO pad status bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,GPIO pad status bit 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,GPIO pad status bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,GPIO pad status bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,GPIO pad status bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,GPIO pad status bit 0" "Low,High" group.long 0x0C++0x13 line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1" bitfld.long 0x00 30.--31. " ICR[15] ,Controls the active condition of the interrupt function for GPIO interrupt 15" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 28.--29. " [14] ,Controls the active condition of the interrupt function for GPIO interrupt 14" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 26.--27. " [13] ,Controls the active condition of the interrupt function for GPIO interrupt 13" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 24.--25. " [12] ,Controls the active condition of the interrupt function for GPIO interrupt 12" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 22.--23. " [11] ,Controls the active condition of the interrupt function for GPIO interrupt 11" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 20.--21. " [10] ,Controls the active condition of the interrupt function for GPIO interrupt 10" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 18.--19. " [9] ,Controls the active condition of the interrupt function for GPIO interrupt 9" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 16.--17. " [8] ,Controls the active condition of the interrupt function for GPIO interrupt 8" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 14.--15. " [7] ,Controls the active condition of the interrupt function for GPIO interrupt 7" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 12.--13. " [6] ,Controls the active condition of the interrupt function for GPIO interrupt 6" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 10.--11. " [5] ,Controls the active condition of the interrupt function for GPIO interrupt 5" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 8.--9. " [4] ,Controls the active condition of the interrupt function for GPIO interrupt 4" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 6.--7. " [3] ,Controls the active condition of the interrupt function for GPIO interrupt 3" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 4.--5. " [2] ,Controls the active condition of the interrupt function for GPIO interrupt 2" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 2.--3. " [1] ,Controls the active condition of the interrupt function for GPIO interrupt 1" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 0.--1. " [0] ,Controls the active condition of the interrupt function for GPIO interrupt 0" "Low-level,High-level,Rising-edge,Falling-edge" line.long 0x04 "ICR2,GPIO Interrupt Configuration Register 2" bitfld.long 0x04 30.--31. " [31] ,Controls the active condition of the interrupt function for GPIO interrupt 31" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 28.--29. " [30] ,Controls the active condition of the interrupt function for GPIO interrupt 30" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 26.--27. " [29] ,Controls the active condition of the interrupt function for GPIO interrupt 29" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 24.--25. " [28] ,Controls the active condition of the interrupt function for GPIO interrupt 28" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 22.--23. " [27] ,Controls the active condition of the interrupt function for GPIO interrupt 27" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 20.--21. " [26] ,Controls the active condition of the interrupt function for GPIO interrupt 26" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 18.--19. " [25] ,Controls the active condition of the interrupt function for GPIO interrupt 25" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 16.--17. " [24] ,Controls the active condition of the interrupt function for GPIO interrupt 24" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 14.--15. " [23] ,Controls the active condition of the interrupt function for GPIO interrupt 23" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 12.--13. " [22] ,Controls the active condition of the interrupt function for GPIO interrupt 22" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 10.--11. " [21] ,Controls the active condition of the interrupt function for GPIO interrupt 21" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 8.--9. " [20] ,Controls the active condition of the interrupt function for GPIO interrupt 20" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 6.--7. " [19] ,Controls the active condition of the interrupt function for GPIO interrupt 19" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 4.--5. " [18] ,Controls the active condition of the interrupt function for GPIO interrupt 18" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 2.--3. " [17] ,Controls the active condition of the interrupt function for GPIO interrupt 17" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 0.--1. " [16] ,Controls the active condition of the interrupt function for GPIO interrupt 16" "Low-level,High-level,Rising-edge,Falling-edge" line.long 0x08 "IMR,GPIO Interrupt Mask Register" bitfld.long 0x08 31. " IMR[31] ,Interrupt 31 mask bit" "Disabled,Enabled" bitfld.long 0x08 30. " [30] ,Interrupt 30 mask bit" "Disabled,Enabled" bitfld.long 0x08 29. " [29] ,Interrupt 29 mask bit" "Disabled,Enabled" bitfld.long 0x08 28. " [28] ,Interrupt 28 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 27. " [27] ,Interrupt 27 mask bit" "Disabled,Enabled" bitfld.long 0x08 26. " [26] ,Interrupt 26 mask bit" "Disabled,Enabled" bitfld.long 0x08 25. " [25] ,Interrupt 25 mask bit" "Disabled,Enabled" bitfld.long 0x08 24. " [24] ,Interrupt 24 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 23. " [23] ,Interrupt 23 mask bit" "Disabled,Enabled" bitfld.long 0x08 22. " [22] ,Interrupt 22 mask bit" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Interrupt 21 mask bit" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Interrupt 20 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 19. " [19] ,Interrupt 19 mask bit" "Disabled,Enabled" bitfld.long 0x08 18. " [18] ,Interrupt 18 mask bit" "Disabled,Enabled" bitfld.long 0x08 17. " [17] ,Interrupt 17 mask bit" "Disabled,Enabled" bitfld.long 0x08 16. " [16] ,Interrupt 16 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 15. " [15] ,Interrupt 15 mask bit" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Interrupt 14 mask bit" "Disabled,Enabled" bitfld.long 0x08 13. " [13] ,Interrupt 13 mask bit" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Interrupt 12 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 11. " [11] ,Interrupt 11 mask bit" "Disabled,Enabled" bitfld.long 0x08 10. " [10] ,Interrupt 10 mask bit" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Interrupt 9 mask bit" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Interrupt 8 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Interrupt 7 mask bit" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Interrupt 6 mask bit" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Interrupt 5 mask bit" "Disabled,Enabled" bitfld.long 0x08 4. " [4] ,Interrupt 4 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 3. " [3] ,Interrupt 3 mask bit" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Interrupt 2 mask bit" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Interrupt 1 mask bit" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Interrupt 0 mask bit" "Disabled,Enabled" line.long 0x0C "ISR,GPIO Interrupt Status Register" eventfld.long 0x0C 31. " ISR[31] ,Interrupt 31 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 30. " [30] ,Interrupt 30 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 29. " [29] ,Interrupt 29 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 28. " [28] ,Interrupt 28 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 27. " [27] ,Interrupt 27 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 26. " [26] ,Interrupt 26 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 25. " [25] ,Interrupt 25 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 24. " [24] ,Interrupt 24 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 23. " [23] ,Interrupt 23 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 22. " [22] ,Interrupt 22 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 21. " [21] ,Interrupt 21 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 20. " [20] ,Interrupt 20 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 19. " [19] ,Interrupt 19 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 18. " [18] ,Interrupt 18 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 17. " [17] ,Interrupt 17 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 16. " [16] ,Interrupt 16 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 15. " [15] ,Interrupt 15 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 14. " [14] ,Interrupt 14 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 13. " [13] ,Interrupt 13 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 12. " [12] ,Interrupt 12 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 11. " [11] ,Interrupt 11 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 10. " [10] ,Interrupt 10 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 9. " [9] ,Interrupt 9 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 8. " [8] ,Interrupt 8 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 7. " [7] ,Interrupt 7 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 6. " [6] ,Interrupt 6 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 5. " [5] ,Interrupt 5 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 4. " [4] ,Interrupt 4 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 3. " [3] ,Interrupt 3 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 2. " [2] ,Interrupt 2 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 1. " [1] ,Interrupt 1 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 0. " [0] ,Interrupt 0 status bit" "No interrupt,Interrupt" line.long 0x10 "EDGE_SEL,GPIO Edge Select Register" bitfld.long 0x10 31. " GPIO_EDGE_SEL[31] ,Edge select bit 31" "31 setting,Any edge" bitfld.long 0x10 30. " [30] ,Edge select bit 30" "30 setting,Any edge" bitfld.long 0x10 29. " [29] ,Edge select bit 29" "29 setting,Any edge" bitfld.long 0x10 28. " [28] ,Edge select bit 28" "28 setting,Any edge" newline bitfld.long 0x10 27. " [27] ,Edge select bit 27" "27 setting,Any edge" bitfld.long 0x10 26. " [26] ,Edge select bit 26" "26 setting,Any edge" bitfld.long 0x10 25. " [25] ,Edge select bit 25" "25 setting,Any edge" bitfld.long 0x10 24. " [24] ,Edge select bit 24" "24 setting,Any edge" newline bitfld.long 0x10 23. " [23] ,Edge select bit 23" "23 setting,Any edge" bitfld.long 0x10 22. " [22] ,Edge select bit 22" "22 setting,Any edge" bitfld.long 0x10 21. " [21] ,Edge select bit 21" "21 setting,Any edge" bitfld.long 0x10 20. " [20] ,Edge select bit 20" "20 setting,Any edge" newline bitfld.long 0x10 19. " [19] ,Edge select bit 19" "19 setting,Any edge" bitfld.long 0x10 18. " [18] ,Edge select bit 18" "18 setting,Any edge" bitfld.long 0x10 17. " [17] ,Edge select bit 17" "17 setting,Any edge" bitfld.long 0x10 16. " [16] ,Edge select bit 16" "16 setting,Any edge" newline bitfld.long 0x10 15. " [15] ,Edge select bit 15" "15 setting,Any edge" bitfld.long 0x10 14. " [14] ,Edge select bit 14" "14 setting,Any edge" bitfld.long 0x10 13. " [13] ,Edge select bit 13" "13 setting,Any edge" bitfld.long 0x10 12. " [12] ,Edge select bit 12" "12 setting,Any edge" newline bitfld.long 0x10 11. " [11] ,Edge select bit 11" "11 setting,Any edge" bitfld.long 0x10 10. " [10] ,Edge select bit 10" "10 setting,Any edge" bitfld.long 0x10 9. " [9] ,Edge select bit 9" "9 setting,Any edge" bitfld.long 0x10 8. " [8] ,Edge select bit 8" "8 setting,Any edge" newline bitfld.long 0x10 7. " [7] ,Edge select bit 7" "7 setting,Any edge" bitfld.long 0x10 6. " [6] ,Edge select bit 6" "6 setting,Any edge" bitfld.long 0x10 5. " [5] ,Edge select bit 5" "5 setting,Any edge" bitfld.long 0x10 4. " [4] ,Edge select bit 4" "4 setting,Any edge" newline bitfld.long 0x10 3. " [3] ,Edge select bit 3" "3 setting,Any edge" bitfld.long 0x10 2. " [2] ,Edge select bit 2" "2 setting,Any edge" bitfld.long 0x10 1. " [1] ,Edge select bit 1" "1 setting,Any edge" bitfld.long 0x10 0. " [0] ,Edge select bit 0" "0 setting,Any edge" wgroup.long 0x84++0x0B line.long 0x00 "DR_SET,GPIO Data Register SET Register" bitfld.long 0x00 31. " DR_SET[31] ,Data bit 31 set" "Not set,Set" bitfld.long 0x00 30. " [30] ,Data bit 30 set" "Not set,Set" bitfld.long 0x00 29. " [29] ,Data bit 29 set" "Not set,Set" bitfld.long 0x00 28. " [28] ,Data bit 28 set" "Not set,Set" newline bitfld.long 0x00 27. " [27] ,Data bit 27 set" "Not set,Set" bitfld.long 0x00 26. " [26] ,Data bit 26 set" "Not set,Set" bitfld.long 0x00 25. " [25] ,Data bit 25 set" "Not set,Set" bitfld.long 0x00 24. " [24] ,Data bit 24 set" "Not set,Set" newline bitfld.long 0x00 23. " [23] ,Data bit 23 set" "Not set,Set" bitfld.long 0x00 22. " [22] ,Data bit 22 set" "Not set,Set" bitfld.long 0x00 21. " [21] ,Data bit 21 set" "Not set,Set" bitfld.long 0x00 20. " [20] ,Data bit 20 set" "Not set,Set" newline bitfld.long 0x00 19. " [19] ,Data bit 19 set" "Not set,Set" bitfld.long 0x00 18. " [18] ,Data bit 18 set" "Not set,Set" bitfld.long 0x00 17. " [17] ,Data bit 17 set" "Not set,Set" bitfld.long 0x00 16. " [16] ,Data bit 16 set" "Not set,Set" newline bitfld.long 0x00 15. " [15] ,Data bit 15 set" "Not set,Set" bitfld.long 0x00 14. " [14] ,Data bit 14 set" "Not set,Set" bitfld.long 0x00 13. " [13] ,Data bit 13 set" "Not set,Set" bitfld.long 0x00 12. " [12] ,Data bit 12 set" "Not set,Set" newline bitfld.long 0x00 11. " [11] ,Data bit 11 set" "Not set,Set" bitfld.long 0x00 10. " [10] ,Data bit 10 set" "Not set,Set" bitfld.long 0x00 9. " [9] ,Data bit 9 set" "Not set,Set" bitfld.long 0x00 8. " [8] ,Data bit 8 set" "Not set,Set" newline bitfld.long 0x00 7. " [7] ,Data bit 7 set" "Not set,Set" bitfld.long 0x00 6. " [6] ,Data bit 6 set" "Not set,Set" bitfld.long 0x00 5. " [5] ,Data bit 5 set" "Not set,Set" bitfld.long 0x00 4. " [4] ,Data bit 4 set" "Not set,Set" newline bitfld.long 0x00 3. " [3] ,Data bit 3 set" "Not set,Set" bitfld.long 0x00 2. " [2] ,Data bit 2 set" "Not set,Set" bitfld.long 0x00 1. " [1] ,Data bit 1 set" "Not set,Set" bitfld.long 0x00 0. " [0] ,Data bit 0 set" "Not set,Set" line.long 0x04 "DR_CLEAR,GPIO Data Register CLEAR Register" bitfld.long 0x04 31. " DR_CLEAR[31] ,Data bit 31 clear" "No effect,Clear" bitfld.long 0x04 30. " [30] ,Data bit 30 clear" "No effect,Clear" bitfld.long 0x04 29. " [29] ,Data bit 29 clear" "No effect,Clear" bitfld.long 0x04 28. " [28] ,Data bit 28 clear" "No effect,Clear" newline bitfld.long 0x04 27. " [27] ,Data bit 27 clear" "No effect,Clear" bitfld.long 0x04 26. " [26] ,Data bit 26 clear" "No effect,Clear" bitfld.long 0x04 25. " [25] ,Data bit 25 clear" "No effect,Clear" bitfld.long 0x04 24. " [24] ,Data bit 24 clear" "No effect,Clear" newline bitfld.long 0x04 23. " [23] ,Data bit 23 clear" "No effect,Clear" bitfld.long 0x04 22. " [22] ,Data bit 22 clear" "No effect,Clear" bitfld.long 0x04 21. " [21] ,Data bit 21 clear" "No effect,Clear" bitfld.long 0x04 20. " [20] ,Data bit 20 clear" "No effect,Clear" newline bitfld.long 0x04 19. " [19] ,Data bit 19 clear" "No effect,Clear" bitfld.long 0x04 18. " [18] ,Data bit 18 clear" "No effect,Clear" bitfld.long 0x04 17. " [17] ,Data bit 17 clear" "No effect,Clear" bitfld.long 0x04 16. " [16] ,Data bit 16 clear" "No effect,Clear" newline bitfld.long 0x04 15. " [15] ,Data bit 15 clear" "No effect,Clear" bitfld.long 0x04 14. " [14] ,Data bit 14 clear" "No effect,Clear" bitfld.long 0x04 13. " [13] ,Data bit 13 clear" "No effect,Clear" bitfld.long 0x04 12. " [12] ,Data bit 12 clear" "No effect,Clear" newline bitfld.long 0x04 11. " [11] ,Data bit 11 clear" "No effect,Clear" bitfld.long 0x04 10. " [10] ,Data bit 10 clear" "No effect,Clear" bitfld.long 0x04 9. " [9] ,Data bit 9 clear" "No effect,Clear" bitfld.long 0x04 8. " [8] ,Data bit 8 clear" "No effect,Clear" newline bitfld.long 0x04 7. " [7] ,Data bit 7 clear" "No effect,Clear" bitfld.long 0x04 6. " [6] ,Data bit 6 clear" "No effect,Clear" bitfld.long 0x04 5. " [5] ,Data bit 5 clear" "No effect,Clear" bitfld.long 0x04 4. " [4] ,Data bit 4 clear" "No effect,Clear" newline bitfld.long 0x04 3. " [3] ,Data bit 3 clear" "No effect,Clear" bitfld.long 0x04 2. " [2] ,Data bit 2 clear" "No effect,Clear" bitfld.long 0x04 1. " [1] ,Data bit 1 clear" "No effect,Clear" bitfld.long 0x04 0. " [0] ,Data bit 0 clear" "No effect,Clear" line.long 0x08 "DR_TOGGLE,GPIO Data Register TOGGLE Register" bitfld.long 0x08 31. " DR_TOGGLE[31] ,Data bit 31 toggle" "Not toggled,Toggled" bitfld.long 0x08 30. " [30] ,Data bit 30 toggle" "No effect,Clear" bitfld.long 0x08 29. " [29] ,Data bit 29 toggle" "Not toggled,Toggled" bitfld.long 0x08 28. " [28] ,Data bit 28 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 27. " [27] ,Data bit 27 toggle" "Not toggled,Toggled" bitfld.long 0x08 26. " [26] ,Data bit 26 toggle" "Not toggled,Toggled" bitfld.long 0x08 25. " [25] ,Data bit 25 toggle" "Not toggled,Toggled" bitfld.long 0x08 24. " [24] ,Data bit 24 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 23. " [23] ,Data bit 23 toggle" "Not toggled,Toggled" bitfld.long 0x08 22. " [22] ,Data bit 22 toggle" "Not toggled,Toggled" bitfld.long 0x08 21. " [21] ,Data bit 21 toggle" "Not toggled,Toggled" bitfld.long 0x08 20. " [20] ,Data bit 20 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 19. " [19] ,Data bit 19 toggle" "Not toggled,Toggled" bitfld.long 0x08 18. " [18] ,Data bit 18 toggle" "Not toggled,Toggled" bitfld.long 0x08 17. " [17] ,Data bit 17 toggle" "Not toggled,Toggled" bitfld.long 0x08 16. " [16] ,Data bit 16 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 15. " [15] ,Data bit 15 toggle" "Not toggled,Toggled" bitfld.long 0x08 14. " [14] ,Data bit 14 toggle" "Not toggled,Toggled" bitfld.long 0x08 13. " [13] ,Data bit 13 toggle" "Not toggled,Toggled" bitfld.long 0x08 12. " [12] ,Data bit 12 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 11. " [11] ,Data bit 11 toggle" "Not toggled,Toggled" bitfld.long 0x08 10. " [10] ,Data bit 10 toggle" "Not toggled,Toggled" bitfld.long 0x08 9. " [9] ,Data bit 9 toggle" "Not toggled,Toggled" bitfld.long 0x08 8. " [8] ,Data bit 8 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 7. " [7] ,Data bit 7 toggle" "Not toggled,Toggled" bitfld.long 0x08 6. " [6] ,Data bit 6 toggle" "Not toggled,Toggled" bitfld.long 0x08 5. " [5] ,Data bit 5 toggle" "Not toggled,Toggled" bitfld.long 0x08 4. " [4] ,Data bit 4 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 3. " [3] ,Data bit 3 toggle" "Not toggled,Toggled" bitfld.long 0x08 2. " [2] ,Data bit 2 toggle" "Not toggled,Toggled" bitfld.long 0x08 1. " [1] ,Data bit 1 toggle" "Not toggled,Toggled" bitfld.long 0x08 0. " [0] ,Data bit 0 toggle" "Not toggled,Toggled" width 0x0B tree.end tree "CSR (MIPI CSI Control and Status Registers)" base ad:0x58261000 width 32. group.long 0x00++0x07 line.long 0x00 "PLM_CTRL,Pixel Link Master Control Register" bitfld.long 0x00 12. " POLARITY ,HSYNC and VSYNC signals polarity" "Active low,Active high" bitfld.long 0x00 11. " VALID_OVERRIDE ,Drive valid on the pixel link" "Not driven,Driven" newline bitfld.long 0x00 10. " HSYNC_OVERIDE ,Force pixel link master HSYNC input to be active" "Not forced,Forced" bitfld.long 0x00 9. " VSYNC_OVERIDE ,Force pixel link master VSYNC input to be active" "Not forced,Forced" newline bitfld.long 0x00 1.--2. " ADDR ,Destination module select" "0,1,2,3" bitfld.long 0x00 0. " ENABLE ,Pixel link enable" "Disabled,Enabled" line.long 0x04 "PHY_CTRL,Physical Layer Control Register" bitfld.long 0x04 22. " PD ,Description missing" "0,1" bitfld.long 0x04 21. " RTERM_SEL ,Description missing" "0,1" newline bitfld.long 0x04 4.--9. " S_PRG_RXHS_SETTLE ,Description missing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 3. " CONT_CLK_MODE ,Description missing" "0,1" newline bitfld.long 0x04 2. " DDRCLK_EN ,DDRCLK enable" "Disabled,Enabled" bitfld.long 0x04 1. " AUTO_PD_EN ,AUTO_PD enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " RX_ENABLE ,RX enabled" "Disabled,Enabled" rgroup.long 0x08++0x03 line.long 0x00 "PHY_STATUS,Physical Layer Status Register" bitfld.long 0x00 0. " LANES_STOPPED ,Lanes stopped" "0,1" group.long 0x30++0x03 line.long 0x00 "VC_INTERLACED,Virtual Channel Interlace Register" bitfld.long 0x00 3. " VC3 ,Virtual channel 3 interlace" "Default,Interlaced" bitfld.long 0x00 2. " VC2 ,Virtual channel 2 interlace" "Default,Interlaced" newline bitfld.long 0x00 1. " VC1 ,Virtual channel 1 interlace" "Default,Interlaced" bitfld.long 0x00 0. " VC0 ,Virtual channel 0 interlace" "Default,Interlaced" group.long 0x38++0x03 line.long 0x00 "DATA_TYPE_DISABLE_BF,Data Type Disable Register" bitfld.long 0x00 21. " DATA_TYPE_DISABLE_RAW14 ,RAW14 data type disable" "No,Yes" bitfld.long 0x00 20. " DATA_TYPE_DISABLE_RAW12 ,RAW12 data type disable" "No,Yes" newline bitfld.long 0x00 19. " DATA_TYPE_DISABLE_RAW10 ,RAW10 data type disable" "No,Yes" bitfld.long 0x00 18. " DATA_TYPE_DISABLE_RAW8 ,RAW8 data type disable" "No,Yes" newline bitfld.long 0x00 16. " DATA_TYPE_DISABLE_RAW6 ,RAW6 data type disable" "No,Yes" bitfld.long 0x00 12. " DATA_TYPE_DISABLE_RGB888 ,RGB888 data type disable" "No,Yes" newline bitfld.long 0x00 11. " DATA_TYPE_DISABLE_RGB666 ,RGB666 data type disable" "No,Yes" bitfld.long 0x00 10. " DATA_TYPE_DISABLE_RGB565 ,RGB565 data type disable" "No,Yes" newline bitfld.long 0x00 9. " DATA_TYPE_DISABLE_RGB555 ,RGB555 data type disable" "No,Yes" bitfld.long 0x00 8. " DATA_TYPE_DISABLE_RGB444 ,RGB444 data type disable" "No,Yes" newline bitfld.long 0x00 7. " DATA_TYPE_DISABLE_YUV422_10BIT ,YUV422_10BIT data type disable" "No,Yes" bitfld.long 0x00 6. " DATA_TYPE_DISABLE_YUV422_8BIT ,YUV422_8BIT data type disable" "No,Yes" newline bitfld.long 0x00 2. " DATA_TYPE_DISABLE_L_YUV420_8BIT ,Legacy YUV422_8BIT data type disable" "No,Yes" group.long 0x40++0x0B line.long 0x00 "YUV420_FIRST_LINE_DATA_TYPE,YUV420 First Line Data Type Register" bitfld.long 0x00 0. " YUV420_FIRST_LINE_DATA_TYPE ,YUV420 first line data type" "Odd,Even" line.long 0x04 "CONTROLLER_CLOCK_RESET_CONTROL,Controller Clock Reset Control Register" bitfld.long 0x04 0.--1. " CONTROLLER_CLOCK_RESET_CONTROL ,Controller clock reset control" "SW_RESETN,CTL_CLK_OFF,?..." line.long 0x08 "STREAM_FENCING_CONTROL,Stream Fencing Control Register" bitfld.long 0x08 0.--3. " STREAM_FENCING_CONTROL ,Stream fencing control" "Fence VC0,Fence VC1,Fence VC2,Fence VC3,?..." rgroup.long 0x4C++0x03 line.long 0x00 "STREAM_FENCING_STATUS,Stream Fencing Status Register" bitfld.long 0x00 0.--3. " STREAM_FENCING_STATUS ,Stream fencing status" "VC0 fenced,VC1 fenced,VC2 fenced,VC3 fenced,?..." width 0x0B tree.end tree.open "Local Interrupt Steer" tree "Channel 0" base ad:0x58260000 width 10. group.long 0x00++0x03 line.long 0x00 "CHAN0CTL,Channel 0 Control Register" bitfld.long 0x00 4. " CH4 ,Channel 4 control" "Disabled,Enabled" bitfld.long 0x00 3. " CH3 ,Channel 3 control" "Disabled,Enabled" bitfld.long 0x00 2. " CH2 ,Channel 2 control" "Disabled,Enabled" bitfld.long 0x00 1. " CH1 ,Channel 1 control" "Disabled,Enabled" newline bitfld.long 0x00 0. " CH0 ,Channel 0 control" "Disabled,Enabled" group.long 0x08++0x3B line.long 0x00 "MASK1,Interrupt Mask 1 Register" bitfld.long 0x00 22. " MASKFLD[22] ,Mask for VPU_INT_6" "Masked,Unmasked" bitfld.long 0x00 21. " [21] ,Mask for VPU_INT_5" "Masked,Unmasked" bitfld.long 0x00 20. " [20] ,Mask for VPU_INT_4" "Masked,Unmasked" bitfld.long 0x00 19. " [19] ,Mask for VPU_INT_3" "Masked,Unmasked" newline bitfld.long 0x00 18. " [18] ,Mask for VPU_INT_2" "Masked,Unmasked" bitfld.long 0x00 17. " [17] ,Mask for VPU_INT_1" "Masked,Unmasked" bitfld.long 0x00 16. " [16] ,Mask for VPU_INT_0" "Masked,Unmasked" bitfld.long 0x00 11. " [11] ,Mask for SPDIF0_TX_DMA_INT" "Masked,Unmasked" newline bitfld.long 0x00 10. " [10] ,Mask for SPDIF0_TX_MOD_INT" "Masked,Unmasked" bitfld.long 0x00 9. " [9] ,Mask for SPDIF0_RX_DMA_INT" "Masked,Unmasked" bitfld.long 0x00 8. " [8] ,Mask for SPDIF0_RX_MOD_INT" "Masked,Unmasked" bitfld.long 0x00 7. " [7] ,Mask for CAAM_RTIC_INT" "Masked,Unmasked" newline bitfld.long 0x00 6. " [6] ,Mask for CAAM_INT3" "Masked,Unmasked" bitfld.long 0x00 5. " [5] ,Mask for CAAM_INT2" "Masked,Unmasked" bitfld.long 0x00 4. " [4] ,Mask for CAAM_INT1" "Masked,Unmasked" bitfld.long 0x00 3. " [3] ,Mask for CAAM_INT0" "Masked,Unmasked" newline bitfld.long 0x00 2. " [2] ,Mask for SEC_MU3_A_INT" "Masked,Unmasked" bitfld.long 0x00 1. " [1] ,Mask for SEC_MU2_A_INT" "Masked,Unmasked" bitfld.long 0x00 0. " [0] ,Mask for SEC_MU1_A_INT" "Masked,Unmasked" line.long 0x04 "MASK2,Interrupt Mask 2 Register" bitfld.long 0x04 25. " MASKFLD[25] ,Mask for UART3_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 24. " [24] ,Mask for UART3_DMA_RX_INT" "Masked,Unmasked" bitfld.long 0x04 23. " [23] ,Mask for UART2_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 22. " [22] ,Mask for UART2_DMA_RX_INT" "Masked,Unmasked" newline bitfld.long 0x04 21. " [21] ,Mask for UART1_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 20. " [20] ,Mask for UART1_DMA_RX_INT" "Masked,Unmasked" bitfld.long 0x04 19. " [19] ,Mask for UART0_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 18. " [18] ,Mask for UART0_DMA_RX_INT" "Masked,Unmasked" newline bitfld.long 0x04 15. " [15] ,Mask for I2C3_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 14. " [14] ,Mask for I2C3_DMA_RX_INT" "Masked,Unmasked" bitfld.long 0x04 13. " [13] ,Mask for I2C2_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 12. " [12] ,Mask for I2C2_DMA_RX_INT" "Masked,Unmasked" newline bitfld.long 0x04 11. " [11] ,Mask for I2C1_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 10. " [10] ,Mask for I2C1_DMA_RX_INT" "Masked,Unmasked" bitfld.long 0x04 9. " [9] ,Mask for I2C0_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 8. " [8] ,Mask for I2C0_DMA_RX_INT" "Masked,Unmasked" newline bitfld.long 0x04 7. " [7] ,Mask for SPI3_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 6. " [6] ,Mask for SPI3_DMA_RX_INT" "Masked,Unmasked" bitfld.long 0x04 5. " [5] ,Mask for SPI2_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 4. " [4] ,Mask for SPI2_DMA_RX_INT" "Masked,Unmasked" newline bitfld.long 0x04 3. " [3] ,Mask for SPI1_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 2. " [2] ,Mask for SPI1_DMA_RX_INT" "Masked,Unmasked" bitfld.long 0x04 1. " [1] ,Mask for SPI0_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 0. " [0] ,Mask for SPI0_DMA_RX_INT" "Masked,Unmasked" line.long 0x08 "MASK3,Interrupt Mask 3 Register" bitfld.long 0x08 26. " MASKFLD[26] ,Mask for ESAI0_DMA_INT" "Masked,Unmasked" bitfld.long 0x08 25. " [25] ,Mask for ESAI0_MOD_INT" "Masked,Unmasked" bitfld.long 0x08 22. " [22] ,Mask for SPDIF0_TX_INT" "Masked,Unmasked" bitfld.long 0x08 21. " [21] ,Mask for SPDIF0_RX_INT" "Masked,Unmasked" newline bitfld.long 0x08 20. " [20] ,Mask for SAI5_INT" "Masked,Unmasked" bitfld.long 0x08 19. " [19] ,Mask for SAI4_INT" "Masked,Unmasked" bitfld.long 0x08 16. " [16] ,Mask for SAI3_INT" "Masked,Unmasked" bitfld.long 0x08 15. " [15] ,Mask for SAI2_INT" "Masked,Unmasked" newline bitfld.long 0x08 14. " [14] ,Mask for SAI1_INT" "Masked,Unmasked" bitfld.long 0x08 13. " [13] ,Mask for SAI0_INT" "Masked,Unmasked" bitfld.long 0x08 12. " [12] ,Mask for GPT5_INT" "Masked,Unmasked" bitfld.long 0x08 11. " [11] ,Mask for GPT4_INT" "Masked,Unmasked" newline bitfld.long 0x08 10. " [10] ,Mask for GPT3_INT" "Masked,Unmasked" bitfld.long 0x08 9. " [9] ,Mask for GPT2_INT" "Masked,Unmasked" bitfld.long 0x08 8. " [8] ,Mask for GPT1_INT" "Masked,Unmasked" bitfld.long 0x08 7. " [7] ,Mask for GPT0_INT" "Masked,Unmasked" newline bitfld.long 0x08 4. " [4] ,Mask for ESAI0_INT" "Masked,Unmasked" bitfld.long 0x08 3. " [3] ,Mask for DMA1_CH5_INT" "Masked,Unmasked" bitfld.long 0x08 2. " [2] ,Mask for DMA1_CH4_INT" "Masked,Unmasked" bitfld.long 0x08 1. " [1] ,Mask for DMA1_CH3_INT" "Masked,Unmasked" newline bitfld.long 0x08 0. " [0] ,Mask for DMA1_CH2_INT" "Masked,Unmasked" line.long 0x0C "MASK4,Interrupt Mask 4 Register" bitfld.long 0x0C 31. " MASKFLD[31] ,Mask for DMA1_CH1_INT" "Masked,Unmasked" bitfld.long 0x0C 30. " [30] ,Mask for DMA1_CH0_INT" "Masked,Unmasked" bitfld.long 0x0C 29. " [29] ,Mask for ASRC1_INT2" "Masked,Unmasked" bitfld.long 0x0C 28. " [28] ,Mask for ASRC1_INT1" "Masked,Unmasked" newline bitfld.long 0x0C 27. " [27] ,Mask for DMA0_CH5_INT" "Masked,Unmasked" bitfld.long 0x0C 26. " [26] ,Mask for DMA0_CH4_INT" "Masked,Unmasked" bitfld.long 0x0C 25. " [25] ,Mask for DMA0_CH3_INT" "Masked,Unmasked" bitfld.long 0x0C 24. " [24] ,Mask for DMA0_CH2_INT" "Masked,Unmasked" newline bitfld.long 0x0C 23. " [23] ,Mask for DMA0_CH1_INT" "Masked,Unmasked" bitfld.long 0x0C 22. " [22] ,Mask for DMA0_CH0_INT" "Masked,Unmasked" bitfld.long 0x0C 21. " [21] ,Mask for ASRC0_INT2" "Masked,Unmasked" bitfld.long 0x0C 20. " [20] ,Mask for ASRC0_INT1" "Masked,Unmasked" newline bitfld.long 0x0C 19. " [19] ,Mask for DMA1_ERR_INT" "Masked,Unmasked" bitfld.long 0x0C 18. " [18] ,Mask for DMA1_INT" "Masked,Unmasked" bitfld.long 0x0C 17. " [17] ,Mask for DMA0_ERR_INT" "Masked,Unmasked" bitfld.long 0x0C 16. " [16] ,Mask for DMA0_INT" "Masked,Unmasked" newline bitfld.long 0x0C 12. " [12] ,Mask for ADC_DMA_INT" "Masked,Unmasked" bitfld.long 0x0C 11. " [11] ,Mask for FTM1_DMA_INT" "Masked,Unmasked" bitfld.long 0x0C 10. " [10] ,Mask for FTM_DMA_INT" "Masked,Unmasked" bitfld.long 0x0C 9. " [9] ,Mask for FLEXCAN2_DMA_INT" "Masked,Unmasked" newline bitfld.long 0x0C 8. " [8] ,Mask for FLEXCAN1_DMA_INT" "Masked,Unmasked" bitfld.long 0x0C 7. " [7] ,Mask for FLEXCAN0_DMA_INT" "Masked,Unmasked" bitfld.long 0x0C 5. " [5] ,Mask for ADC_MOD_INT" "Masked,Unmasked" bitfld.long 0x0C 4. " [4] ,Mask for FTM1_MOD_INT" "Masked,Unmasked" newline bitfld.long 0x0C 3. " [3] ,Mask for FTM_MOD_INT" "Masked,Unmasked" bitfld.long 0x0C 2. " [2] ,Mask for FLEXCAN2_MOD_INT" "Masked,Unmasked" bitfld.long 0x0C 1. " [1] ,Mask for FLEXCAN1_MOD_INT" "Masked,Unmasked" bitfld.long 0x0C 0. " [0] ,Mask for FLEXCAN0_MOD_INT" "Masked,Unmasked" line.long 0x10 "MASK5,Interrupt Mask 5 Register" bitfld.long 0x10 28. " MASKFLD[28] ,Mask for UART3_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 27. " [27] ,Mask for UART2_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 26. " [26] ,Mask for UART1_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 25. " [25] ,Mask for UART0_MOD_INT" "Masked,Unmasked" newline bitfld.long 0x10 23. " [23] ,Mask for I2C3_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 22. " [22] ,Mask for I2C2_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 21. " [21] ,Mask for I2C1_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 20. " [20] ,Mask for I2C0_MOD_INT" "Masked,Unmasked" newline bitfld.long 0x10 19. " [19] ,Mask for SPI3_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 18. " [18] ,Mask for SPI2_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 17. " [17] ,Mask for SPI1_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 16. " [16] ,Mask for SPI0_MOD_INT" "Masked,Unmasked" newline bitfld.long 0x10 12. " [12] ,Mask for SAI5_DMA_INT" "Masked,Unmasked" bitfld.long 0x10 11. " [11] ,Mask for SAI5_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 10. " [10] ,Mask for SAI4_DMA_INT" "Masked,Unmasked" bitfld.long 0x10 9. " [9] ,Mask for SAI4_MOD_INT" "Masked,Unmasked" newline bitfld.long 0x10 4. " [4] ,Mask for SAI3_DMA_INT" "Masked,Unmasked" bitfld.long 0x10 3. " [3] ,Mask for SAI3_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 0. " [0] ,Mask for INT_OUT" "Masked,Unmasked" line.long 0x14 "MASK6,Interrupt Mask 6 Register" bitfld.long 0x14 31. " MASKFLD[31] ,Mask for SAI2_DMA_INT" "Masked,Unmasked" bitfld.long 0x14 30. " [30] ,Mask for SAI2_MOD_INT" "Masked,Unmasked" bitfld.long 0x14 29. " [29] ,Mask for SAI1_DMA_INT" "Masked,Unmasked" bitfld.long 0x14 28. " [28] ,Mask for SAI1_MOD_INT" "Masked,Unmasked" newline bitfld.long 0x14 27. " [27] ,Mask for SAI0_DMA_INT" "Masked,Unmasked" bitfld.long 0x14 26. " [26] ,Mask for SAI0_MOD_INT" "Masked,Unmasked" bitfld.long 0x14 24. " [24] ,Mask for MJPEG_DEC3_INT" "Masked,Unmasked" bitfld.long 0x14 23. " [23] ,Mask for MJPEG_DEC2_INT" "Masked,Unmasked" newline bitfld.long 0x14 22. " [22] ,Mask for MJPEG_DEC1_INT" "Masked,Unmasked" bitfld.long 0x14 21. " [21] ,Mask for MJPEG_DEC0_INT" "Masked,Unmasked" bitfld.long 0x14 20. " [20] ,Mask for MJPEG_ENC3_INT" "Masked,Unmasked" bitfld.long 0x14 19. " [19] ,Mask for MJPEG_ENC2_INT" "Masked,Unmasked" newline bitfld.long 0x14 18. " [18] ,Mask for MJPEG_ENC1_INT" "Masked,Unmasked" bitfld.long 0x14 17. " [17] ,Mask for MJPEG_ENC0_INT" "Masked,Unmasked" bitfld.long 0x14 16. " [16] ,Mask for PDMA_STREAM7_INT" "Masked,Unmasked" bitfld.long 0x14 15. " [15] ,Mask for PDMA_STREAM6_INT" "Masked,Unmasked" newline bitfld.long 0x14 14. " [14] ,Mask for PDMA_STREAM5_INT" "Masked,Unmasked" bitfld.long 0x14 13. " [13] ,Mask for PDMA_STREAM4_INT" "Masked,Unmasked" bitfld.long 0x14 12. " [12] ,Mask for PDMA_STREAM3_INT" "Masked,Unmasked" bitfld.long 0x14 11. " [11] ,Mask for PDMA_STREAM2_INT" "Masked,Unmasked" newline bitfld.long 0x14 10. " [10] ,Mask for PDMA_STREAM1_INT" "Masked,Unmasked" bitfld.long 0x14 9. " [9] ,Mask for PDMA_STREAM0_INT" "Masked,Unmasked" bitfld.long 0x14 0. " [0] ,Mask for MSI_INT" "Masked,Unmasked" line.long 0x18 "MASK7,Interrupt Mask 7 Register" bitfld.long 0x18 20. " MASKFLD[20] ,Mask for DMA_ERR_INT" "Masked,Unmasked" bitfld.long 0x18 19. " [19] ,Mask for DMA_INT" "Masked,Unmasked" bitfld.long 0x18 18. " [18] ,Mask for APBHDMA" "Masked,Unmasked" bitfld.long 0x18 17. " [17] ,Mask for NAND_GPMI_INT" "Masked,Unmasked" newline bitfld.long 0x18 16. " [16] ,Mask for NAND_BCH_INT" "Masked,Unmasked" bitfld.long 0x18 15. " [15] ,Mask for USB3_INT" "Masked,Unmasked" bitfld.long 0x18 14. " [14] ,Mask for WAKEUP_INT" "Masked,Unmasked" bitfld.long 0x18 13. " [13] ,Mask for UTMI_INT" "Masked,Unmasked" newline bitfld.long 0x18 12. " [12] ,Mask for USB_HOST_INT" "Masked,Unmasked" bitfld.long 0x18 11. " [11] ,Mask for USB_OTG_INT" "Masked,Unmasked" bitfld.long 0x18 10. " [10] ,Mask for MLB_AHB_INT" "Masked,Unmasked" bitfld.long 0x18 9. " [9] ,Mask for MLB_INT" "Masked,Unmasked" newline bitfld.long 0x18 7. " [7] ,Mask for ENET1_TIMER_INT" "Masked,Unmasked" bitfld.long 0x18 6. " [6] ,Mask for ENET1_FRAME0_EVENT_INT" "Masked,Unmasked" bitfld.long 0x18 5. " [5] ,Mask for ENET1_FRAME2_INT" "Masked,Unmasked" bitfld.long 0x18 4. " [4] ,Mask for ENET1_FRAME1_INT" "Masked,Unmasked" newline bitfld.long 0x18 3. " [3] ,Mask for ENET0_TIMER_INT" "Masked,Unmasked" bitfld.long 0x18 2. " [2] ,Mask for ENET0_FRAME0_EVENT_INT" "Masked,Unmasked" bitfld.long 0x18 1. " [1] ,Mask for ENET0_FRAME2_INT" "Masked,Unmasked" bitfld.long 0x18 0. " [0] ,Mask for ENET0_FRAME1_INT" "Masked,Unmasked" line.long 0x1C "MASK8,Interrupt Mask 8 Register" bitfld.long 0x1C 23. " MASKFLD[23] ,Mask for EXTERNAL_DMA_INT_5" "Masked,Unmasked" bitfld.long 0x1C 22. " [22] ,Mask for EXTERNAL_DMA_INT_4" "Masked,Unmasked" bitfld.long 0x1C 21. " [21] ,Mask for EXTERNAL_DMA_INT_3" "Masked,Unmasked" bitfld.long 0x1C 20. " [20] ,Mask for EXTERNAL_DMA_INT_2" "Masked,Unmasked" newline bitfld.long 0x1C 19. " [19] ,Mask for EXTERNAL_DMA_INT_1" "Masked,Unmasked" bitfld.long 0x1C 18. " [18] ,Mask for EXTERNAL_DMA_INT_0" "Masked,Unmasked" bitfld.long 0x1C 16. " [16] ,Mask for ADC_INT" "Masked,Unmasked" bitfld.long 0x1C 15. " [15] ,Mask for FTM1_INT" "Masked,Unmasked" newline bitfld.long 0x1C 14. " [14] ,Mask for FTM_INT" "Masked,Unmasked" bitfld.long 0x1C 13. " [13] ,Mask for FLEXCAN2_INT" "Masked,Unmasked" bitfld.long 0x1C 12. " [12] ,Mask for FLEXCAN1_INT" "Masked,Unmasked" bitfld.long 0x1C 11. " [11] ,Mask for FLEXCAN0_INT" "Masked,Unmasked" newline bitfld.long 0x1C 10. " [10] ,Mask for USDHC2_INT" "Masked,Unmasked" bitfld.long 0x1C 9. " [9] ,Mask for USDHC1_INT" "Masked,Unmasked" bitfld.long 0x1C 8. " [8] ,Mask for EMMC0_INT/USDHC0_INT" "Masked,Unmasked" bitfld.long 0x1C 4. " [4] ,Mask for UART3_INT" "Masked,Unmasked" newline bitfld.long 0x1C 3. " [3] ,Mask for UART2_INT" "Masked,Unmasked" bitfld.long 0x1C 2. " [2] ,Mask for UART1_INT" "Masked,Unmasked" bitfld.long 0x1C 1. " [1] ,Mask for UART0_INT" "Masked,Unmasked" line.long 0x20 "MASK9,Interrupt Mask 9 Register" bitfld.long 0x20 31. " MASKFLD[31] ,Mask for I2C3_INT" "Masked,Unmasked" bitfld.long 0x20 30. " [30] ,Mask for I2C2_INT" "Masked,Unmasked" bitfld.long 0x20 29. " [29] ,Mask for I2C1_INT" "Masked,Unmasked" bitfld.long 0x20 28. " [28] ,Mask for I2C0_INT" "Masked,Unmasked" newline bitfld.long 0x20 27. " [27] ,Mask for SPI3_INT" "Masked,Unmasked" bitfld.long 0x20 26. " [26] ,Mask for SPI2_INT" "Masked,Unmasked" bitfld.long 0x20 25. " [25] ,Mask for SPI1_INT" "Masked,Unmasked" bitfld.long 0x20 24. " [24] ,Mask for SPI0_INT" "Masked,Unmasked" newline bitfld.long 0x20 16. " [16] ,Mask for MU13_INT_B" "Masked,Unmasked" bitfld.long 0x20 15. " [15] ,Mask for MU12_INT_B" "Masked,Unmasked" bitfld.long 0x20 14. " [14] ,Mask for MU11_INT_B" "Masked,Unmasked" bitfld.long 0x20 13. " [13] ,Mask for MU10_INT_B" "Masked,Unmasked" newline bitfld.long 0x20 12. " [12] ,Mask for MU9_INT_B" "Masked,Unmasked" bitfld.long 0x20 11. " [11] ,Mask for MU8_INT_B" "Masked,Unmasked" bitfld.long 0x20 10. " [10] ,Mask for MU7_INT_B" "Masked,Unmasked" bitfld.long 0x20 9. " [9] ,Mask for MU6_INT_B" "Masked,Unmasked" newline bitfld.long 0x20 8. " [8] ,Mask for MU5_INT_B" "Masked,Unmasked" bitfld.long 0x20 0. " [0] ,Mask for MU13_INT_A" "Masked,Unmasked" line.long 0x24 "MASK10,Interrupt Mask 10 Register" bitfld.long 0x24 31. " MASKFLD[31] ,Mask for MU12_INT_A" "Masked,Unmasked" bitfld.long 0x24 30. " [30] ,Mask for MU11_INT_A" "Masked,Unmasked" bitfld.long 0x24 29. " [29] ,Mask for MU10_INT_A" "Masked,Unmasked" bitfld.long 0x24 28. " [28] ,Mask for MU9_INT_A" "Masked,Unmasked" newline bitfld.long 0x24 27. " [27] ,Mask for MU8_INT_A" "Masked,Unmasked" bitfld.long 0x24 26. " [26] ,Mask for MU7_INT_A" "Masked,Unmasked" bitfld.long 0x24 25. " [25] ,Mask for MU6_INT_A" "Masked,Unmasked" bitfld.long 0x24 24. " [24] ,Mask for MU5_INT_A" "Masked,Unmasked" newline bitfld.long 0x24 20. " [20] ,Mask for MU4_INT" "Masked,Unmasked" bitfld.long 0x24 19. " [19] ,Mask for MU3_INT" "Masked,Unmasked" bitfld.long 0x24 18. " [18] ,Mask for MU2_INT" "Masked,Unmasked" bitfld.long 0x24 17. " [17] ,Mask for MU1_INT" "Masked,Unmasked" newline bitfld.long 0x24 16. " [16] ,Mask for MU0_INT" "Masked,Unmasked" line.long 0x28 "MASK11,Interrupt Mask 11 Register" bitfld.long 0x28 15. " MASKFLD[15] ,Mask for GPIO_INT[7]" "Masked,Unmasked" bitfld.long 0x28 14. " [14] ,Mask for GPIO_INT[6]" "Masked,Unmasked" bitfld.long 0x28 13. " [13] ,Mask for GPIO_INT[5]" "Masked,Unmasked" bitfld.long 0x28 12. " [12] ,Mask for GPIO_INT[4]" "Masked,Unmasked" newline bitfld.long 0x28 11. " [11] ,Mask for GPIO_INT[3]" "Masked,Unmasked" bitfld.long 0x28 10. " [10] ,Mask for GPIO_INT[2]" "Masked,Unmasked" bitfld.long 0x28 9. " [9] ,Mask for GPIO_INT[1]" "Masked,Unmasked" bitfld.long 0x28 8. " [8] ,Mask for GPIO_INT[0]" "Masked,Unmasked" newline bitfld.long 0x28 3. " [3] ,Mask for PERF_CNT_INT" "Masked,Unmasked" bitfld.long 0x28 2. " [2] ,Mask for SBR_DONE_INT" "Masked,Unmasked" bitfld.long 0x28 1. " [1] ,Mask for ECC_NCORRECT_INT" "Masked,Unmasked" bitfld.long 0x28 0. " [0] ,Mask for ECC_CORRECT_INT" "Masked,Unmasked" line.long 0x2C "MASK12,Interrupt Mask 12 Register" bitfld.long 0x2C 27. " MASKFLD[27] ,Mask for SYS_COUNT_INT[3]" "Masked,Unmasked" bitfld.long 0x2C 26. " [26] ,Mask for SYS_COUNT_INT[2]" "Masked,Unmasked" bitfld.long 0x2C 25. " [25] ,Mask for SYS_COUNT_INT[1]" "Masked,Unmasked" bitfld.long 0x2C 24. " [24] ,Mask for SYS_COUNT_INT[0]" "Masked,Unmasked" newline bitfld.long 0x2C 23. " [23] ,Mask for INT_OUT[7]" "Masked,Unmasked" bitfld.long 0x2C 22. " [22] ,Mask for INT_OUT[6]" "Masked,Unmasked" bitfld.long 0x2C 21. " [21] ,Mask for INT_OUT[5]" "Masked,Unmasked" bitfld.long 0x2C 20. " [20] ,Mask for INT_OUT[4]" "Masked,Unmasked" newline bitfld.long 0x2C 19. " [19] ,Mask for INT_OUT[3]" "Masked,Unmasked" bitfld.long 0x2C 18. " [18] ,Mask for INT_OUT[2]" "Masked,Unmasked" bitfld.long 0x2C 17. " [17] ,Mask for INT_OUT[1]" "Masked,Unmasked" bitfld.long 0x2C 16. " [16] ,Mask for INT_OUT[0]" "Masked,Unmasked" newline bitfld.long 0x2C 15. " [15] ,Mask for PCIE9_GPIO_WAKEUP[1]" "Masked,Unmasked" bitfld.long 0x2C 14. " [14] ,Mask for PCIE9_GPIO_WAKEUP[0]" "Masked,Unmasked" bitfld.long 0x2C 13. " [13] ,Mask for PCIE0_SMLH_REQ_RST" "Masked,Unmasked" bitfld.long 0x2C 12. " [12] ,Mask for PCIE0_INT_A" "Masked,Unmasked" newline bitfld.long 0x2C 11. " [11] ,Mask for PCIE0_INT_B" "Masked,Unmasked" bitfld.long 0x2C 10. " [10] ,Mask for PCIE0_INT_C" "Masked,Unmasked" bitfld.long 0x2C 9. " [9] ,Mask for PCIE0_INT_D" "Masked,Unmasked" bitfld.long 0x2C 8. " [8] ,Mask for PCIE0_DMA_INT" "Masked,Unmasked" newline bitfld.long 0x2C 7. " [7] ,Mask for PCIE0_CLK_REQ_INT" "Masked,Unmasked" bitfld.long 0x2C 6. " [6] ,Mask for PCIE0_MSI_CTRL_INT" "Masked,Unmasked" bitfld.long 0x2C 5. " [5] ,Mask for PWM7_INT" "Masked,Unmasked" bitfld.long 0x2C 4. " [4] ,Mask for PWM6_INT" "Masked,Unmasked" newline bitfld.long 0x2C 3. " [3] ,Mask for PWM5_INT" "Masked,Unmasked" bitfld.long 0x2C 2. " [2] ,Mask for PWM4_INT" "Masked,Unmasked" bitfld.long 0x2C 1. " [1] ,Mask for PWM3_INT" "Masked,Unmasked" bitfld.long 0x2C 0. " [0] ,Mask for PWM2_INT" "Masked,Unmasked" line.long 0x30 "MASK13,Interrupt Mask 13 Register" bitfld.long 0x30 31. " MASKFLD[31] ,Mask for PWM1_INT" "Masked,Unmasked" bitfld.long 0x30 30. " [30] ,Mask for PWM0_INT" "Masked,Unmasked" bitfld.long 0x30 29. " [29] ,Mask for FLEXSPI1_INT" "Masked,Unmasked" bitfld.long 0x30 28. " [28] ,Mask for FLEXSPI0_INT" "Masked,Unmasked" newline bitfld.long 0x30 21. " [21] ,Mask for KPP0_INT" "Masked,Unmasked" bitfld.long 0x30 20. " [20] ,Mask for GPT4_INT" "Masked,Unmasked" bitfld.long 0x30 19. " [19] ,Mask for GPT3_INT" "Masked,Unmasked" bitfld.long 0x30 18. " [18] ,Mask for GPT2_INT" "Masked,Unmasked" newline bitfld.long 0x30 17. " [17] ,Mask for GPT1_INT" "Masked,Unmasked" bitfld.long 0x30 16. " [16] ,Mask for GPT0_INT" "Masked,Unmasked" bitfld.long 0x30 5. " [5] ,Mask for DMA3_ERR_INT" "Masked,Unmasked" bitfld.long 0x30 4. " [4] ,Mask for DMA3_INT" "Masked,Unmasked" newline bitfld.long 0x30 3. " [3] ,Mask for DMA2_ERR_INT" "Masked,Unmasked" bitfld.long 0x30 2. " [2] ,Mask for DMA2_INT" "Masked,Unmasked" bitfld.long 0x30 0. " [0] ,Mask for XAQ2_INTR" "Masked,Unmasked" line.long 0x34 "MASK14,Interrupt Mask 14 Register" bitfld.long 0x34 31. " MASKFLD[31] ,Mask for LCD_PWM_INT" "Masked,Unmasked" bitfld.long 0x34 30. " [30] ,Mask for LCD_MOD_INT" "Masked,Unmasked" bitfld.long 0x34 28. " [28] ,Mask for INT_OUT" "Masked,Unmasked" bitfld.long 0x34 27. " [27] ,Mask for INT_OUT" "Masked,Unmasked" newline bitfld.long 0x34 20. " [20] ,Mask for INT_OUT[12]" "Masked,Unmasked" bitfld.long 0x34 19. " [19] ,Mask for INT_OUT[11]" "Masked,Unmasked" bitfld.long 0x34 18. " [18] ,Mask for INT_OUT[10]" "Masked,Unmasked" bitfld.long 0x34 17. " [17] ,Mask for INT_OUT[9]" "Masked,Unmasked" newline bitfld.long 0x34 15. " [15] ,Mask for INT_OUT[7]" "Masked,Unmasked" bitfld.long 0x34 14. " [14] ,Mask for INT_OUT[6]" "Masked,Unmasked" bitfld.long 0x34 13. " [13] ,Mask for INT_OUT[5]" "Masked,Unmasked" bitfld.long 0x34 12. " [12] ,Mask for INT_OUT[4]" "Masked,Unmasked" newline bitfld.long 0x34 11. " [11] ,Mask for INT_OUT[3]" "Masked,Unmasked" bitfld.long 0x34 10. " [10] ,Mask for INT_OUT[2]" "Masked,Unmasked" bitfld.long 0x34 9. " [9] ,Mask for INT_OUT[1]" "Masked,Unmasked" bitfld.long 0x34 8. " [8] ,Mask for INT_OUT[0]" "Masked,Unmasked" line.long 0x38 "MASK15,Interrupt Mask 15 Register" bitfld.long 0x38 23. " MASKFLD[23] ,Mask for INT_OUT[7]" "Masked,Unmasked" bitfld.long 0x38 22. " [22] ,Mask for INT_OUT[6]" "Masked,Unmasked" bitfld.long 0x38 21. " [21] ,Mask for INT_OUT[5]" "Masked,Unmasked" bitfld.long 0x38 20. " [20] ,Mask for INT_OUT[4]" "Masked,Unmasked" newline bitfld.long 0x38 19. " [19] ,Mask for INT_OUT[3]" "Masked,Unmasked" bitfld.long 0x38 18. " [18] ,Mask for INT_OUT[2]" "Masked,Unmasked" bitfld.long 0x38 17. " [17] ,Mask for INT_OUT[1]" "Masked,Unmasked" bitfld.long 0x38 16. " [16] ,Mask for INT_OUT[0]" "Masked,Unmasked" newline bitfld.long 0x38 1. " [1] ,Mask for nEXTERRIRQ" "Masked,Unmasked" bitfld.long 0x38 0. " [0] ,Mask for nINTERRIRQ" "Masked,Unmasked" group.long 0x48++0x3B line.long 0x00 "SET1,Interrupt Set 1 Register" bitfld.long 0x00 22. " FORCEFLD[22] ,Force VPU_INT_6" "Normal,Forced" bitfld.long 0x00 21. " [21] ,Force VPU_INT_5" "Normal,Forced" bitfld.long 0x00 20. " [20] ,Force VPU_INT_4" "Normal,Forced" bitfld.long 0x00 19. " [19] ,Force VPU_INT_3" "Normal,Forced" newline bitfld.long 0x00 18. " [18] ,Force VPU_INT_2" "Normal,Forced" bitfld.long 0x00 17. " [17] ,Force VPU_INT_1" "Normal,Forced" bitfld.long 0x00 16. " [16] ,Force VPU_INT_0" "Normal,Forced" bitfld.long 0x00 11. " [11] ,Force SPDIF0_TX_DMA_INT" "Normal,Forced" newline bitfld.long 0x00 10. " [10] ,Force SPDIF0_TX_MOD_INT" "Normal,Forced" bitfld.long 0x00 9. " [9] ,Force SPDIF0_RX_DMA_INT" "Normal,Forced" bitfld.long 0x00 8. " [8] ,Force SPDIF0_RX_MOD_INT" "Normal,Forced" bitfld.long 0x00 7. " [7] ,Force CAAM_RTIC_INT" "Normal,Forced" newline bitfld.long 0x00 6. " [6] ,Force CAAM_INT3" "Normal,Forced" bitfld.long 0x00 5. " [5] ,Force CAAM_INT2" "Normal,Forced" bitfld.long 0x00 4. " [4] ,Force CAAM_INT1" "Normal,Forced" bitfld.long 0x00 3. " [3] ,Force CAAM_INT0" "Normal,Forced" newline bitfld.long 0x00 2. " [2] ,Force SEC_MU3_A_INT" "Normal,Forced" bitfld.long 0x00 1. " [1] ,Force SEC_MU2_A_INT" "Normal,Forced" bitfld.long 0x00 0. " [0] ,Force SEC_MU1_A_INT" "Normal,Forced" line.long 0x04 "SET2,Interrupt Set 2 Register" bitfld.long 0x04 25. " FORCEFLD[25] ,Force UART3_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 24. " [24] ,Force UART3_DMA_RX_INT" "Normal,Forced" bitfld.long 0x04 23. " [23] ,Force UART2_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 22. " [22] ,Force UART2_DMA_RX_INT" "Normal,Forced" newline bitfld.long 0x04 21. " [21] ,Force UART1_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 20. " [20] ,Force UART1_DMA_RX_INT" "Normal,Forced" bitfld.long 0x04 19. " [19] ,Force UART0_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 18. " [18] ,Force UART0_DMA_RX_INT" "Normal,Forced" newline bitfld.long 0x04 15. " [15] ,Force I2C3_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 14. " [14] ,Force I2C3_DMA_RX_INT" "Normal,Forced" bitfld.long 0x04 13. " [13] ,Force I2C2_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 12. " [12] ,Force I2C2_DMA_RX_INT" "Normal,Forced" newline bitfld.long 0x04 11. " [11] ,Force I2C1_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 10. " [10] ,Force I2C1_DMA_RX_INT" "Normal,Forced" bitfld.long 0x04 9. " [9] ,Force I2C0_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 8. " [8] ,Force I2C0_DMA_RX_INT" "Normal,Forced" newline bitfld.long 0x04 7. " [7] ,Force SPI3_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 6. " [6] ,Force SPI3_DMA_RX_INT" "Normal,Forced" bitfld.long 0x04 5. " [5] ,Force SPI2_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 4. " [4] ,Force SPI2_DMA_RX_INT" "Normal,Forced" newline bitfld.long 0x04 3. " [3] ,Force SPI1_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 2. " [2] ,Force SPI1_DMA_RX_INT" "Normal,Forced" bitfld.long 0x04 1. " [1] ,Force SPI0_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 0. " [0] ,Force SPI0_DMA_RX_INT" "Normal,Forced" line.long 0x08 "SET3,Interrupt Set 3 Register" bitfld.long 0x08 26. " FORCEFLD[26] ,Force ESAI0_DMA_INT" "Normal,Forced" bitfld.long 0x08 25. " [25] ,Force ESAI0_MOD_INT" "Normal,Forced" bitfld.long 0x08 22. " [22] ,Force SPDIF0_TX_INT" "Normal,Forced" bitfld.long 0x08 21. " [21] ,Force SPDIF0_RX_INT" "Normal,Forced" newline bitfld.long 0x08 20. " [20] ,Force SAI5_INT" "Normal,Forced" bitfld.long 0x08 19. " [19] ,Force SAI4_INT" "Normal,Forced" bitfld.long 0x08 16. " [16] ,Force SAI3_INT" "Normal,Forced" bitfld.long 0x08 15. " [15] ,Force SAI2_INT" "Normal,Forced" newline bitfld.long 0x08 14. " [14] ,Force SAI1_INT" "Normal,Forced" bitfld.long 0x08 13. " [13] ,Force SAI0_INT" "Normal,Forced" bitfld.long 0x08 12. " [12] ,Force GPT5_INT" "Normal,Forced" bitfld.long 0x08 11. " [11] ,Force GPT4_INT" "Normal,Forced" newline bitfld.long 0x08 10. " [10] ,Force GPT3_INT" "Normal,Forced" bitfld.long 0x08 9. " [9] ,Force GPT2_INT" "Normal,Forced" bitfld.long 0x08 8. " [8] ,Force GPT1_INT" "Normal,Forced" bitfld.long 0x08 7. " [7] ,Force GPT0_INT" "Normal,Forced" newline bitfld.long 0x08 4. " [4] ,Force ESAI0_INT" "Normal,Forced" bitfld.long 0x08 3. " [3] ,Force DMA1_CH5_INT" "Normal,Forced" bitfld.long 0x08 2. " [2] ,Force DMA1_CH4_INT" "Normal,Forced" bitfld.long 0x08 1. " [1] ,Force DMA1_CH3_INT" "Normal,Forced" newline bitfld.long 0x08 0. " [0] ,Force DMA1_CH2_INT" "Normal,Forced" line.long 0x0C "SET4,Interrupt Set 4 Register" bitfld.long 0x0C 31. " FORCEFLD[31] ,Force DMA1_CH1_INT" "Normal,Forced" bitfld.long 0x0C 30. " [30] ,Force DMA1_CH0_INT" "Normal,Forced" bitfld.long 0x0C 29. " [29] ,Force ASRC1_INT2" "Normal,Forced" bitfld.long 0x0C 28. " [28] ,Force ASRC1_INT1" "Normal,Forced" newline bitfld.long 0x0C 27. " [27] ,Force DMA0_CH5_INT" "Normal,Forced" bitfld.long 0x0C 26. " [26] ,Force DMA0_CH4_INT" "Normal,Forced" bitfld.long 0x0C 25. " [25] ,Force DMA0_CH3_INT" "Normal,Forced" bitfld.long 0x0C 24. " [24] ,Force DMA0_CH2_INT" "Normal,Forced" newline bitfld.long 0x0C 23. " [23] ,Force DMA0_CH1_INT" "Normal,Forced" bitfld.long 0x0C 22. " [22] ,Force DMA0_CH0_INT" "Normal,Forced" bitfld.long 0x0C 21. " [21] ,Force ASRC0_INT2" "Normal,Forced" bitfld.long 0x0C 20. " [20] ,Force ASRC0_INT1" "Normal,Forced" newline bitfld.long 0x0C 19. " [19] ,Force DMA1_ERR_INT" "Normal,Forced" bitfld.long 0x0C 18. " [18] ,Force DMA1_INT" "Normal,Forced" bitfld.long 0x0C 17. " [17] ,Force DMA0_ERR_INT" "Normal,Forced" bitfld.long 0x0C 16. " [16] ,Force DMA0_INT" "Normal,Forced" newline bitfld.long 0x0C 12. " [12] ,Force ADC_DMA_INT" "Normal,Forced" bitfld.long 0x0C 11. " [11] ,Force FTM1_DMA_INT" "Normal,Forced" bitfld.long 0x0C 10. " [10] ,Force FTM_DMA_INT" "Normal,Forced" bitfld.long 0x0C 9. " [9] ,Force FLEXCAN2_DMA_INT" "Normal,Forced" newline bitfld.long 0x0C 8. " [8] ,Force FLEXCAN1_DMA_INT" "Normal,Forced" bitfld.long 0x0C 7. " [7] ,Force FLEXCAN0_DMA_INT" "Normal,Forced" bitfld.long 0x0C 5. " [5] ,Force ADC_MOD_INT" "Normal,Forced" bitfld.long 0x0C 4. " [4] ,Force FTM1_MOD_INT" "Normal,Forced" newline bitfld.long 0x0C 3. " [3] ,Force FTM_MOD_INT" "Normal,Forced" bitfld.long 0x0C 2. " [2] ,Force FLEXCAN2_MOD_INT" "Normal,Forced" bitfld.long 0x0C 1. " [1] ,Force FLEXCAN1_MOD_INT" "Normal,Forced" bitfld.long 0x0C 0. " [0] ,Force FLEXCAN0_MOD_INT" "Normal,Forced" line.long 0x10 "SET5,Interrupt Set 5 Register" bitfld.long 0x10 28. " FORCEFLD[28] ,Force UART3_MOD_INT" "Normal,Forced" bitfld.long 0x10 27. " [27] ,Force UART2_MOD_INT" "Normal,Forced" bitfld.long 0x10 26. " [26] ,Force UART1_MOD_INT" "Normal,Forced" bitfld.long 0x10 25. " [25] ,Force UART0_MOD_INT" "Normal,Forced" newline bitfld.long 0x10 23. " [23] ,Force I2C3_MOD_INT" "Normal,Forced" bitfld.long 0x10 22. " [22] ,Force I2C2_MOD_INT" "Normal,Forced" bitfld.long 0x10 21. " [21] ,Force I2C1_MOD_INT" "Normal,Forced" bitfld.long 0x10 20. " [20] ,Force I2C0_MOD_INT" "Normal,Forced" newline bitfld.long 0x10 19. " [19] ,Force SPI3_MOD_INT" "Normal,Forced" bitfld.long 0x10 18. " [18] ,Force SPI2_MOD_INT" "Normal,Forced" bitfld.long 0x10 17. " [17] ,Force SPI1_MOD_INT" "Normal,Forced" bitfld.long 0x10 16. " [16] ,Force SPI0_MOD_INT" "Normal,Forced" newline bitfld.long 0x10 12. " [12] ,Force SAI5_DMA_INT" "Normal,Forced" bitfld.long 0x10 11. " [11] ,Force SAI5_MOD_INT" "Normal,Forced" bitfld.long 0x10 10. " [10] ,Force SAI4_DMA_INT" "Normal,Forced" bitfld.long 0x10 9. " [9] ,Force SAI4_MOD_INT" "Normal,Forced" newline bitfld.long 0x10 4. " [4] ,Force SAI3_DMA_INT" "Normal,Forced" bitfld.long 0x10 3. " [3] ,Force SAI3_MOD_INT" "Normal,Forced" bitfld.long 0x10 0. " [0] ,Force INT_OUT" "Normal,Forced" line.long 0x14 "SET6,Interrupt Set 6 Register" bitfld.long 0x14 31. " FORCEFLD[31] ,Force SAI2_DMA_INT" "Normal,Forced" bitfld.long 0x14 30. " [30] ,Force SAI2_MOD_INT" "Normal,Forced" bitfld.long 0x14 29. " [29] ,Force SAI1_DMA_INT" "Normal,Forced" bitfld.long 0x14 28. " [28] ,Force SAI1_MOD_INT" "Normal,Forced" newline bitfld.long 0x14 27. " [27] ,Force SAI0_DMA_INT" "Normal,Forced" bitfld.long 0x14 26. " [26] ,Force SAI0_MOD_INT" "Normal,Forced" bitfld.long 0x14 24. " [24] ,Force MJPEG_DEC3_INT" "Normal,Forced" bitfld.long 0x14 23. " [23] ,Force MJPEG_DEC2_INT" "Normal,Forced" newline bitfld.long 0x14 22. " [22] ,Force MJPEG_DEC1_INT" "Normal,Forced" bitfld.long 0x14 21. " [21] ,Force MJPEG_DEC0_INT" "Normal,Forced" bitfld.long 0x14 20. " [20] ,Force MJPEG_ENC3_INT" "Normal,Forced" bitfld.long 0x14 19. " [19] ,Force MJPEG_ENC2_INT" "Normal,Forced" newline bitfld.long 0x14 18. " [18] ,Force MJPEG_ENC1_INT" "Normal,Forced" bitfld.long 0x14 17. " [17] ,Force MJPEG_ENC0_INT" "Normal,Forced" bitfld.long 0x14 16. " [16] ,Force PDMA_STREAM7_INT" "Normal,Forced" bitfld.long 0x14 15. " [15] ,Force PDMA_STREAM6_INT" "Normal,Forced" newline bitfld.long 0x14 14. " [14] ,Force PDMA_STREAM5_INT" "Normal,Forced" bitfld.long 0x14 13. " [13] ,Force PDMA_STREAM4_INT" "Normal,Forced" bitfld.long 0x14 12. " [12] ,Force PDMA_STREAM3_INT" "Normal,Forced" bitfld.long 0x14 11. " [11] ,Force PDMA_STREAM2_INT" "Normal,Forced" newline bitfld.long 0x14 10. " [10] ,Force PDMA_STREAM1_INT" "Normal,Forced" bitfld.long 0x14 9. " [9] ,Force PDMA_STREAM0_INT" "Normal,Forced" bitfld.long 0x14 0. " [0] ,Force MSI_INT" "Normal,Forced" line.long 0x18 "SET7,Interrupt Set 7 Register" bitfld.long 0x18 20. " FORCEFLD[20] ,Force DMA_ERR_INT" "Normal,Forced" bitfld.long 0x18 19. " [19] ,Force DMA_INT" "Normal,Forced" bitfld.long 0x18 18. " [18] ,Force APBHDMA" "Normal,Forced" bitfld.long 0x18 17. " [17] ,Force NAND_GPMI_INT" "Normal,Forced" newline bitfld.long 0x18 16. " [16] ,Force NAND_BCH_INT" "Normal,Forced" bitfld.long 0x18 15. " [15] ,Force USB3_INT" "Normal,Forced" bitfld.long 0x18 14. " [14] ,Force WAKEUP_INT" "Normal,Forced" bitfld.long 0x18 13. " [13] ,Force UTMI_INT" "Normal,Forced" newline bitfld.long 0x18 12. " [12] ,Force USB_HOST_INT" "Normal,Forced" bitfld.long 0x18 11. " [11] ,Force USB_OTG_INT" "Normal,Forced" bitfld.long 0x18 10. " [10] ,Force MLB_AHB_INT" "Normal,Forced" bitfld.long 0x18 9. " [9] ,Force MLB_INT" "Normal,Forced" newline bitfld.long 0x18 7. " [7] ,Force ENET1_TIMER_INT" "Normal,Forced" bitfld.long 0x18 6. " [6] ,Force ENET1_FRAME0_EVENT_INT" "Normal,Forced" bitfld.long 0x18 5. " [5] ,Force ENET1_FRAME2_INT" "Normal,Forced" bitfld.long 0x18 4. " [4] ,Force ENET1_FRAME1_INT" "Normal,Forced" newline bitfld.long 0x18 3. " [3] ,Force ENET0_TIMER_INT" "Normal,Forced" bitfld.long 0x18 2. " [2] ,Force ENET0_FRAME0_EVENT_INT" "Normal,Forced" bitfld.long 0x18 1. " [1] ,Force ENET0_FRAME2_INT" "Normal,Forced" bitfld.long 0x18 0. " [0] ,Force ENET0_FRAME1_INT" "Normal,Forced" line.long 0x1C "SET8,Interrupt Set 8 Register" bitfld.long 0x1C 23. " FORCEFLD[23] ,Force EXTERNAL_DMA_INT_5" "Normal,Forced" bitfld.long 0x1C 22. " [22] ,Force EXTERNAL_DMA_INT_4" "Normal,Forced" bitfld.long 0x1C 21. " [21] ,Force EXTERNAL_DMA_INT_3" "Normal,Forced" bitfld.long 0x1C 20. " [20] ,Force EXTERNAL_DMA_INT_2" "Normal,Forced" newline bitfld.long 0x1C 19. " [19] ,Force EXTERNAL_DMA_INT_1" "Normal,Forced" bitfld.long 0x1C 18. " [18] ,Force EXTERNAL_DMA_INT_0" "Normal,Forced" bitfld.long 0x1C 16. " [16] ,Force ADC_INT" "Normal,Forced" bitfld.long 0x1C 15. " [15] ,Force FTM1_INT" "Normal,Forced" newline bitfld.long 0x1C 14. " [14] ,Force FTM_INT" "Normal,Forced" bitfld.long 0x1C 13. " [13] ,Force FLEXCAN2_INT" "Normal,Forced" bitfld.long 0x1C 12. " [12] ,Force FLEXCAN1_INT" "Normal,Forced" bitfld.long 0x1C 11. " [11] ,Force FLEXCAN0_INT" "Normal,Forced" newline bitfld.long 0x1C 10. " [10] ,Force USDHC2_INT" "Normal,Forced" bitfld.long 0x1C 9. " [9] ,Force USDHC1_INT" "Normal,Forced" bitfld.long 0x1C 8. " [8] ,Force EMMC0_INT/USDHC0_INT" "Normal,Forced" bitfld.long 0x1C 4. " [4] ,Force UART3_INT" "Normal,Forced" newline bitfld.long 0x1C 3. " [3] ,Force UART2_INT" "Normal,Forced" bitfld.long 0x1C 2. " [2] ,Force UART1_INT" "Normal,Forced" bitfld.long 0x1C 1. " [1] ,Force UART0_INT" "Normal,Forced" line.long 0x20 "SET9,Interrupt Set 9 Register" bitfld.long 0x20 31. " FORCEFLD[31] ,Force I2C3_INT" "Normal,Forced" bitfld.long 0x20 30. " [30] ,Force I2C2_INT" "Normal,Forced" bitfld.long 0x20 29. " [29] ,Force I2C1_INT" "Normal,Forced" bitfld.long 0x20 28. " [28] ,Force I2C0_INT" "Normal,Forced" newline bitfld.long 0x20 27. " [27] ,Force SPI3_INT" "Normal,Forced" bitfld.long 0x20 26. " [26] ,Force SPI2_INT" "Normal,Forced" bitfld.long 0x20 25. " [25] ,Force SPI1_INT" "Normal,Forced" bitfld.long 0x20 24. " [24] ,Force SPI0_INT" "Normal,Forced" newline bitfld.long 0x20 16. " [16] ,Force MU13_INT_B" "Normal,Forced" bitfld.long 0x20 15. " [15] ,Force MU12_INT_B" "Normal,Forced" bitfld.long 0x20 14. " [14] ,Force MU11_INT_B" "Normal,Forced" bitfld.long 0x20 13. " [13] ,Force MU10_INT_B" "Normal,Forced" newline bitfld.long 0x20 12. " [12] ,Force MU9_INT_B" "Normal,Forced" bitfld.long 0x20 11. " [11] ,Force MU8_INT_B" "Normal,Forced" bitfld.long 0x20 10. " [10] ,Force MU7_INT_B" "Normal,Forced" bitfld.long 0x20 9. " [9] ,Force MU6_INT_B" "Normal,Forced" newline bitfld.long 0x20 8. " [8] ,Force MU5_INT_B" "Normal,Forced" bitfld.long 0x20 0. " [0] ,Force MU13_INT_A" "Normal,Forced" line.long 0x24 "SET10,Interrupt Set 10 Register" bitfld.long 0x24 31. " FORCEFLD[31] ,Force MU12_INT_A" "Normal,Forced" bitfld.long 0x24 30. " [30] ,Force MU11_INT_A" "Normal,Forced" bitfld.long 0x24 29. " [29] ,Force MU10_INT_A" "Normal,Forced" bitfld.long 0x24 28. " [28] ,Force MU9_INT_A" "Normal,Forced" newline bitfld.long 0x24 27. " [27] ,Force MU8_INT_A" "Normal,Forced" bitfld.long 0x24 26. " [26] ,Force MU7_INT_A" "Normal,Forced" bitfld.long 0x24 25. " [25] ,Force MU6_INT_A" "Normal,Forced" bitfld.long 0x24 24. " [24] ,Force MU5_INT_A" "Normal,Forced" newline bitfld.long 0x24 20. " [20] ,Force MU4_INT" "Normal,Forced" bitfld.long 0x24 19. " [19] ,Force MU3_INT" "Normal,Forced" bitfld.long 0x24 18. " [18] ,Force MU2_INT" "Normal,Forced" bitfld.long 0x24 17. " [17] ,Force MU1_INT" "Normal,Forced" newline bitfld.long 0x24 16. " [16] ,Force MU0_INT" "Normal,Forced" line.long 0x28 "SET11,Interrupt Set 11 Register" bitfld.long 0x28 15. " FORCEFLD[15] ,Force GPIO_INT[7]" "Normal,Forced" bitfld.long 0x28 14. " [14] ,Force GPIO_INT[6]" "Normal,Forced" bitfld.long 0x28 13. " [13] ,Force GPIO_INT[5]" "Normal,Forced" bitfld.long 0x28 12. " [12] ,Force GPIO_INT[4]" "Normal,Forced" newline bitfld.long 0x28 11. " [11] ,Force GPIO_INT[3]" "Normal,Forced" bitfld.long 0x28 10. " [10] ,Force GPIO_INT[2]" "Normal,Forced" bitfld.long 0x28 9. " [9] ,Force GPIO_INT[1]" "Normal,Forced" bitfld.long 0x28 8. " [8] ,Force GPIO_INT[0]" "Normal,Forced" newline bitfld.long 0x28 3. " [3] ,Force PERF_CNT_INT" "Normal,Forced" bitfld.long 0x28 2. " [2] ,Force SBR_DONE_INT" "Normal,Forced" bitfld.long 0x28 1. " [1] ,Force ECC_NCORRECT_INT" "Normal,Forced" bitfld.long 0x28 0. " [0] ,Force ECC_CORRECT_INT" "Normal,Forced" line.long 0x2C "SET12,Interrupt Set 12 Register" bitfld.long 0x2C 27. " FORCEFLD[27] ,Force SYS_COUNT_INT[3]" "Normal,Forced" bitfld.long 0x2C 26. " [26] ,Force SYS_COUNT_INT[2]" "Normal,Forced" bitfld.long 0x2C 25. " [25] ,Force SYS_COUNT_INT[1]" "Normal,Forced" bitfld.long 0x2C 24. " [24] ,Force SYS_COUNT_INT[0]" "Normal,Forced" newline bitfld.long 0x2C 23. " [23] ,Force INT_OUT[7]" "Normal,Forced" bitfld.long 0x2C 22. " [22] ,Force INT_OUT[6]" "Normal,Forced" bitfld.long 0x2C 21. " [21] ,Force INT_OUT[5]" "Normal,Forced" bitfld.long 0x2C 20. " [20] ,Force INT_OUT[4]" "Normal,Forced" newline bitfld.long 0x2C 19. " [19] ,Force INT_OUT[3]" "Normal,Forced" bitfld.long 0x2C 18. " [18] ,Force INT_OUT[2]" "Normal,Forced" bitfld.long 0x2C 17. " [17] ,Force INT_OUT[1]" "Normal,Forced" bitfld.long 0x2C 16. " [16] ,Force INT_OUT[0]" "Normal,Forced" newline bitfld.long 0x2C 15. " [15] ,Force PCIE9_GPIO_WAKEUP[1]" "Normal,Forced" bitfld.long 0x2C 14. " [14] ,Force PCIE9_GPIO_WAKEUP[0]" "Normal,Forced" bitfld.long 0x2C 13. " [13] ,Force PCIE0_SMLH_REQ_RST" "Normal,Forced" bitfld.long 0x2C 12. " [12] ,Force PCIE0_INT_A" "Normal,Forced" newline bitfld.long 0x2C 11. " [11] ,Force PCIE0_INT_B" "Normal,Forced" bitfld.long 0x2C 10. " [10] ,Force PCIE0_INT_C" "Normal,Forced" bitfld.long 0x2C 9. " [9] ,Force PCIE0_INT_D" "Normal,Forced" bitfld.long 0x2C 8. " [8] ,Force PCIE0_DMA_INT" "Normal,Forced" newline bitfld.long 0x2C 7. " [7] ,Force PCIE0_CLK_REQ_INT" "Normal,Forced" bitfld.long 0x2C 6. " [6] ,Force PCIE0_MSI_CTRL_INT" "Normal,Forced" bitfld.long 0x2C 5. " [5] ,Force PWM7_INT" "Normal,Forced" bitfld.long 0x2C 4. " [4] ,Force PWM6_INT" "Normal,Forced" newline bitfld.long 0x2C 3. " [3] ,Force PWM5_INT" "Normal,Forced" bitfld.long 0x2C 2. " [2] ,Force PWM4_INT" "Normal,Forced" bitfld.long 0x2C 1. " [1] ,Force PWM3_INT" "Normal,Forced" bitfld.long 0x2C 0. " [0] ,Force PWM2_INT" "Normal,Forced" line.long 0x30 "SET13,Interrupt Set 13 Register" bitfld.long 0x30 31. " FORCEFLD[31] ,Force PWM1_INT" "Normal,Forced" bitfld.long 0x30 30. " [30] ,Force PWM0_INT" "Normal,Forced" bitfld.long 0x30 29. " [29] ,Force FLEXSPI1_INT" "Normal,Forced" bitfld.long 0x30 28. " [28] ,Force FLEXSPI0_INT" "Normal,Forced" newline bitfld.long 0x30 21. " [21] ,Force KPP0_INT" "Normal,Forced" bitfld.long 0x30 20. " [20] ,Force GPT4_INT" "Normal,Forced" bitfld.long 0x30 19. " [19] ,Force GPT3_INT" "Normal,Forced" bitfld.long 0x30 18. " [18] ,Force GPT2_INT" "Normal,Forced" newline bitfld.long 0x30 17. " [17] ,Force GPT1_INT" "Normal,Forced" bitfld.long 0x30 16. " [16] ,Force GPT0_INT" "Normal,Forced" bitfld.long 0x30 5. " [5] ,Force DMA3_ERR_INT" "Normal,Forced" bitfld.long 0x30 4. " [4] ,Force DMA3_INT" "Normal,Forced" newline bitfld.long 0x30 3. " [3] ,Force DMA2_ERR_INT" "Normal,Forced" bitfld.long 0x30 2. " [2] ,Force DMA2_INT" "Normal,Forced" bitfld.long 0x30 0. " [0] ,Force XAQ2_INTR" "Normal,Forced" line.long 0x34 "SET14,Interrupt Set 14 Register" bitfld.long 0x34 31. " FORCEFLD[31] ,Force LCD_PWM_INT" "Normal,Forced" bitfld.long 0x34 30. " [30] ,Force LCD_MOD_INT" "Normal,Forced" bitfld.long 0x34 28. " [28] ,Force INT_OUT" "Normal,Forced" bitfld.long 0x34 27. " [27] ,Force INT_OUT" "Normal,Forced" newline bitfld.long 0x34 20. " [20] ,Force INT_OUT[12]" "Normal,Forced" bitfld.long 0x34 19. " [19] ,Force INT_OUT[11]" "Normal,Forced" bitfld.long 0x34 18. " [18] ,Force INT_OUT[10]" "Normal,Forced" bitfld.long 0x34 17. " [17] ,Force INT_OUT[9]" "Normal,Forced" newline bitfld.long 0x34 15. " [15] ,Force INT_OUT[7]" "Normal,Forced" bitfld.long 0x34 14. " [14] ,Force INT_OUT[6]" "Normal,Forced" bitfld.long 0x34 13. " [13] ,Force INT_OUT[5]" "Normal,Forced" bitfld.long 0x34 12. " [12] ,Force INT_OUT[4]" "Normal,Forced" newline bitfld.long 0x34 11. " [11] ,Force INT_OUT[3]" "Normal,Forced" bitfld.long 0x34 10. " [10] ,Force INT_OUT[2]" "Normal,Forced" bitfld.long 0x34 9. " [9] ,Force INT_OUT[1]" "Normal,Forced" bitfld.long 0x34 8. " [8] ,Force INT_OUT[0]" "Normal,Forced" line.long 0x38 "SET15,Interrupt Set 15 Register" bitfld.long 0x38 23. " FORCEFLD[23] ,Force INT_OUT[7]" "Normal,Forced" bitfld.long 0x38 22. " [22] ,Force INT_OUT[6]" "Normal,Forced" bitfld.long 0x38 21. " [21] ,Force INT_OUT[5]" "Normal,Forced" bitfld.long 0x38 20. " [20] ,Force INT_OUT[4]" "Normal,Forced" newline bitfld.long 0x38 19. " [19] ,Force INT_OUT[3]" "Normal,Forced" bitfld.long 0x38 18. " [18] ,Force INT_OUT[2]" "Normal,Forced" bitfld.long 0x38 17. " [17] ,Force INT_OUT[1]" "Normal,Forced" bitfld.long 0x38 16. " [16] ,Force INT_OUT[0]" "Normal,Forced" newline bitfld.long 0x38 1. " [1] ,Force nEXTERRIRQ" "Normal,Forced" bitfld.long 0x38 0. " [0] ,Force nINTERRIRQ" "Normal,Forced" rgroup.long 0x88++0x3B line.long 0x00 "STATUS1,Interrupt Status 1 Register" bitfld.long 0x00 22. " STATUS[22] ,VPU_INT_6 status" "Not set,Set" bitfld.long 0x00 21. " [21] ,VPU_INT_5 status" "Not set,Set" bitfld.long 0x00 20. " [20] ,VPU_INT_4 status" "Not set,Set" bitfld.long 0x00 19. " [19] ,VPU_INT_3 status" "Not set,Set" newline bitfld.long 0x00 18. " [18] ,VPU_INT_2 status" "Not set,Set" bitfld.long 0x00 17. " [17] ,VPU_INT_1 status" "Not set,Set" bitfld.long 0x00 16. " [16] ,VPU_INT_0 status" "Not set,Set" bitfld.long 0x00 11. " [11] ,SPDIF0_TX_DMA_INT status" "Not set,Set" newline bitfld.long 0x00 10. " [10] ,SPDIF0_TX_MOD_INT status" "Not set,Set" bitfld.long 0x00 9. " [9] ,SPDIF0_RX_DMA_INT status" "Not set,Set" bitfld.long 0x00 8. " [8] ,SPDIF0_RX_MOD_INT status" "Not set,Set" bitfld.long 0x00 7. " [7] ,CAAM_RTIC_INT status" "Not set,Set" newline bitfld.long 0x00 6. " [6] ,CAAM_INT3 status" "Not set,Set" bitfld.long 0x00 5. " [5] ,CAAM_INT2 status" "Not set,Set" bitfld.long 0x00 4. " [4] ,CAAM_INT1 status" "Not set,Set" bitfld.long 0x00 3. " [3] ,CAAM_INT0 status" "Not set,Set" newline bitfld.long 0x00 2. " [2] ,SEC_MU3_A_INT status" "Not set,Set" bitfld.long 0x00 1. " [1] ,SEC_MU2_A_INT status" "Not set,Set" bitfld.long 0x00 0. " [0] ,SEC_MU1_A_INT status" "Not set,Set" line.long 0x04 "STATUS2,Interrupt Status 2 Register" bitfld.long 0x04 25. " STATUS[25] ,UART3_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 24. " [24] ,UART3_DMA_RX_INT status" "Not set,Set" bitfld.long 0x04 23. " [23] ,UART2_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 22. " [22] ,UART2_DMA_RX_INT status" "Not set,Set" newline bitfld.long 0x04 21. " [21] ,UART1_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 20. " [20] ,UART1_DMA_RX_INT status" "Not set,Set" bitfld.long 0x04 19. " [19] ,UART0_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 18. " [18] ,UART0_DMA_RX_INT status" "Not set,Set" newline bitfld.long 0x04 15. " [15] ,I2C3_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 14. " [14] ,I2C3_DMA_RX_INT status" "Not set,Set" bitfld.long 0x04 13. " [13] ,I2C2_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 12. " [12] ,I2C2_DMA_RX_INT status" "Not set,Set" newline bitfld.long 0x04 11. " [11] ,I2C1_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 10. " [10] ,I2C1_DMA_RX_INT status" "Not set,Set" bitfld.long 0x04 9. " [9] ,I2C0_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 8. " [8] ,I2C0_DMA_RX_INT status" "Not set,Set" newline bitfld.long 0x04 7. " [7] ,SPI3_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 6. " [6] ,SPI3_DMA_RX_INT status" "Not set,Set" bitfld.long 0x04 5. " [5] ,SPI2_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 4. " [4] ,SPI2_DMA_RX_INT status" "Not set,Set" newline bitfld.long 0x04 3. " [3] ,SPI1_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 2. " [2] ,SPI1_DMA_RX_INT status" "Not set,Set" bitfld.long 0x04 1. " [1] ,SPI0_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 0. " [0] ,SPI0_DMA_RX_INT status" "Not set,Set" line.long 0x08 "STATUS3,Interrupt Status 3 Register" bitfld.long 0x08 26. " STATUS[26] ,ESAI0_DMA_INT status" "Not set,Set" bitfld.long 0x08 25. " [25] ,ESAI0_MOD_INT status" "Not set,Set" bitfld.long 0x08 22. " [22] ,SPDIF0_TX_INT status" "Not set,Set" bitfld.long 0x08 21. " [21] ,SPDIF0_RX_INT status" "Not set,Set" newline bitfld.long 0x08 20. " [20] ,SAI5_INT status" "Not set,Set" bitfld.long 0x08 19. " [19] ,SAI4_INT status" "Not set,Set" bitfld.long 0x08 16. " [16] ,SAI3_INT status" "Not set,Set" bitfld.long 0x08 15. " [15] ,SAI2_INT status" "Not set,Set" newline bitfld.long 0x08 14. " [14] ,SAI1_INT status" "Not set,Set" bitfld.long 0x08 13. " [13] ,SAI0_INT status" "Not set,Set" bitfld.long 0x08 12. " [12] ,GPT5_INT status" "Not set,Set" bitfld.long 0x08 11. " [11] ,GPT4_INT status" "Not set,Set" newline bitfld.long 0x08 10. " [10] ,GPT3_INT status" "Not set,Set" bitfld.long 0x08 9. " [9] ,GPT2_INT status" "Not set,Set" bitfld.long 0x08 8. " [8] ,GPT1_INT status" "Not set,Set" bitfld.long 0x08 7. " [7] ,GPT0_INT status" "Not set,Set" newline bitfld.long 0x08 4. " [4] ,ESAI0_INT status" "Not set,Set" bitfld.long 0x08 3. " [3] ,DMA1_CH5_INT status" "Not set,Set" bitfld.long 0x08 2. " [2] ,DMA1_CH4_INT status" "Not set,Set" bitfld.long 0x08 1. " [1] ,DMA1_CH3_INT status" "Not set,Set" newline bitfld.long 0x08 0. " [0] ,DMA1_CH2_INT status" "Not set,Set" line.long 0x0C "STATUS4,Interrupt Status 4 Register" bitfld.long 0x0C 31. " STATUS[31] ,DMA1_CH1_INT status" "Not set,Set" bitfld.long 0x0C 30. " [30] ,DMA1_CH0_INT status" "Not set,Set" bitfld.long 0x0C 29. " [29] ,ASRC1_INT2 status" "Not set,Set" bitfld.long 0x0C 28. " [28] ,ASRC1_INT1 status" "Not set,Set" newline bitfld.long 0x0C 27. " [27] ,DMA0_CH5_INT status" "Not set,Set" bitfld.long 0x0C 26. " [26] ,DMA0_CH4_INT status" "Not set,Set" bitfld.long 0x0C 25. " [25] ,DMA0_CH3_INT status" "Not set,Set" bitfld.long 0x0C 24. " [24] ,DMA0_CH2_INT status" "Not set,Set" newline bitfld.long 0x0C 23. " [23] ,DMA0_CH1_INT status" "Not set,Set" bitfld.long 0x0C 22. " [22] ,DMA0_CH0_INT status" "Not set,Set" bitfld.long 0x0C 21. " [21] ,ASRC0_INT2 status" "Not set,Set" bitfld.long 0x0C 20. " [20] ,ASRC0_INT1 status" "Not set,Set" newline bitfld.long 0x0C 19. " [19] ,DMA1_ERR_INT status" "Not set,Set" bitfld.long 0x0C 18. " [18] ,DMA1_INT status" "Not set,Set" bitfld.long 0x0C 17. " [17] ,DMA0_ERR_INT status" "Not set,Set" bitfld.long 0x0C 16. " [16] ,DMA0_INT status" "Not set,Set" newline bitfld.long 0x0C 12. " [12] ,ADC_DMA_INT status" "Not set,Set" bitfld.long 0x0C 11. " [11] ,FTM1_DMA_INT status" "Not set,Set" bitfld.long 0x0C 10. " [10] ,FTM_DMA_INT status" "Not set,Set" bitfld.long 0x0C 9. " [9] ,FLEXCAN2_DMA_INT status" "Not set,Set" newline bitfld.long 0x0C 8. " [8] ,FLEXCAN1_DMA_INT status" "Not set,Set" bitfld.long 0x0C 7. " [7] ,FLEXCAN0_DMA_INT status" "Not set,Set" bitfld.long 0x0C 5. " [5] ,ADC_MOD_INT status" "Not set,Set" bitfld.long 0x0C 4. " [4] ,FTM1_MOD_INT status" "Not set,Set" newline bitfld.long 0x0C 3. " [3] ,FTM_MOD_INT status" "Not set,Set" bitfld.long 0x0C 2. " [2] ,FLEXCAN2_MOD_INT status" "Not set,Set" bitfld.long 0x0C 1. " [1] ,FLEXCAN1_MOD_INT status" "Not set,Set" bitfld.long 0x0C 0. " [0] ,FLEXCAN0_MOD_INT status" "Not set,Set" line.long 0x10 "STATUS5,Interrupt Status 5 Register" bitfld.long 0x10 28. " STATUS[28] ,UART3_MOD_INT status" "Not set,Set" bitfld.long 0x10 27. " [27] ,UART2_MOD_INT status" "Not set,Set" bitfld.long 0x10 26. " [26] ,UART1_MOD_INT status" "Not set,Set" bitfld.long 0x10 25. " [25] ,UART0_MOD_INT status" "Not set,Set" newline bitfld.long 0x10 23. " [23] ,I2C3_MOD_INT status" "Not set,Set" bitfld.long 0x10 22. " [22] ,I2C2_MOD_INT status" "Not set,Set" bitfld.long 0x10 21. " [21] ,I2C1_MOD_INT status" "Not set,Set" bitfld.long 0x10 20. " [20] ,I2C0_MOD_INT status" "Not set,Set" newline bitfld.long 0x10 19. " [19] ,SPI3_MOD_INT status" "Not set,Set" bitfld.long 0x10 18. " [18] ,SPI2_MOD_INT status" "Not set,Set" bitfld.long 0x10 17. " [17] ,SPI1_MOD_INT status" "Not set,Set" bitfld.long 0x10 16. " [16] ,SPI0_MOD_INT status" "Not set,Set" newline bitfld.long 0x10 12. " [12] ,SAI5_DMA_INT status" "Not set,Set" bitfld.long 0x10 11. " [11] ,SAI5_MOD_INT status" "Not set,Set" bitfld.long 0x10 10. " [10] ,SAI4_DMA_INT status" "Not set,Set" bitfld.long 0x10 9. " [9] ,SAI4_MOD_INT status" "Not set,Set" newline bitfld.long 0x10 4. " [4] ,SAI3_DMA_INT status" "Not set,Set" bitfld.long 0x10 3. " [3] ,SAI3_MOD_INT status" "Not set,Set" bitfld.long 0x10 0. " [0] ,INT_OUT status" "Not set,Set" line.long 0x14 "STATUS6,Interrupt Status 6 Register" bitfld.long 0x14 31. " STATUS[31] ,SAI2_DMA_INT status" "Not set,Set" bitfld.long 0x14 30. " [30] ,SAI2_MOD_INT status" "Not set,Set" bitfld.long 0x14 29. " [29] ,SAI1_DMA_INT status" "Not set,Set" bitfld.long 0x14 28. " [28] ,SAI1_MOD_INT status" "Not set,Set" newline bitfld.long 0x14 27. " [27] ,SAI0_DMA_INT status" "Not set,Set" bitfld.long 0x14 26. " [26] ,SAI0_MOD_INT status" "Not set,Set" bitfld.long 0x14 24. " [24] ,MJPEG_DEC3_INT status" "Not set,Set" bitfld.long 0x14 23. " [23] ,MJPEG_DEC2_INT status" "Not set,Set" newline bitfld.long 0x14 22. " [22] ,MJPEG_DEC1_INT status" "Not set,Set" bitfld.long 0x14 21. " [21] ,MJPEG_DEC0_INT status" "Not set,Set" bitfld.long 0x14 20. " [20] ,MJPEG_ENC3_INT status" "Not set,Set" bitfld.long 0x14 19. " [19] ,MJPEG_ENC2_INT status" "Not set,Set" newline bitfld.long 0x14 18. " [18] ,MJPEG_ENC1_INT status" "Not set,Set" bitfld.long 0x14 17. " [17] ,MJPEG_ENC0_INT status" "Not set,Set" bitfld.long 0x14 16. " [16] ,PDMA_STREAM7_INT status" "Not set,Set" bitfld.long 0x14 15. " [15] ,PDMA_STREAM6_INT status" "Not set,Set" newline bitfld.long 0x14 14. " [14] ,PDMA_STREAM5_INT status" "Not set,Set" bitfld.long 0x14 13. " [13] ,PDMA_STREAM4_INT status" "Not set,Set" bitfld.long 0x14 12. " [12] ,PDMA_STREAM3_INT status" "Not set,Set" bitfld.long 0x14 11. " [11] ,PDMA_STREAM2_INT status" "Not set,Set" newline bitfld.long 0x14 10. " [10] ,PDMA_STREAM1_INT status" "Not set,Set" bitfld.long 0x14 9. " [9] ,PDMA_STREAM0_INT status" "Not set,Set" bitfld.long 0x14 0. " [0] ,MSI_INT status" "Not set,Set" line.long 0x18 "STATUS7,Interrupt Status 7 Register" bitfld.long 0x18 20. " STATUS[20] ,DMA_ERR_INT status" "Not set,Set" bitfld.long 0x18 19. " [19] ,DMA_INT status" "Not set,Set" bitfld.long 0x18 18. " [18] ,APBHDMA status" "Not set,Set" bitfld.long 0x18 17. " [17] ,NAND_GPMI_INT status" "Not set,Set" newline bitfld.long 0x18 16. " [16] ,NAND_BCH_INT status" "Not set,Set" bitfld.long 0x18 15. " [15] ,USB3_INT status" "Not set,Set" bitfld.long 0x18 14. " [14] ,WAKEUP_INT status" "Not set,Set" bitfld.long 0x18 13. " [13] ,UTMI_INT status" "Not set,Set" newline bitfld.long 0x18 12. " [12] ,USB_HOST_INT status" "Not set,Set" bitfld.long 0x18 11. " [11] ,USB_OTG_INT status" "Not set,Set" bitfld.long 0x18 10. " [10] ,MLB_AHB_INT status" "Not set,Set" bitfld.long 0x18 9. " [9] ,MLB_INT status" "Not set,Set" newline bitfld.long 0x18 7. " [7] ,ENET1_TIMER_INT status" "Not set,Set" bitfld.long 0x18 6. " [6] ,ENET1_FRAME0_EVENT_INT status" "Not set,Set" bitfld.long 0x18 5. " [5] ,ENET1_FRAME2_INT status" "Not set,Set" bitfld.long 0x18 4. " [4] ,ENET1_FRAME1_INT status" "Not set,Set" newline bitfld.long 0x18 3. " [3] ,ENET0_TIMER_INT status" "Not set,Set" bitfld.long 0x18 2. " [2] ,ENET0_FRAME0_EVENT_INT status" "Not set,Set" bitfld.long 0x18 1. " [1] ,ENET0_FRAME2_INT status" "Not set,Set" bitfld.long 0x18 0. " [0] ,ENET0_FRAME1_INT status" "Not set,Set" line.long 0x1C "STATUS8,Interrupt Status 8 Register" bitfld.long 0x1C 23. " STATUS[23] ,EXTERNAL_DMA_INT_5 status" "Not set,Set" bitfld.long 0x1C 22. " [22] ,EXTERNAL_DMA_INT_4 status" "Not set,Set" bitfld.long 0x1C 21. " [21] ,EXTERNAL_DMA_INT_3 status" "Not set,Set" bitfld.long 0x1C 20. " [20] ,EXTERNAL_DMA_INT_2 status" "Not set,Set" newline bitfld.long 0x1C 19. " [19] ,EXTERNAL_DMA_INT_1 status" "Not set,Set" bitfld.long 0x1C 18. " [18] ,EXTERNAL_DMA_INT_0 status" "Not set,Set" bitfld.long 0x1C 16. " [16] ,ADC_INT status" "Not set,Set" bitfld.long 0x1C 15. " [15] ,FTM1_INT status" "Not set,Set" newline bitfld.long 0x1C 14. " [14] ,FTM_INT status" "Not set,Set" bitfld.long 0x1C 13. " [13] ,FLEXCAN2_INT status" "Not set,Set" bitfld.long 0x1C 12. " [12] ,FLEXCAN1_INT status" "Not set,Set" bitfld.long 0x1C 11. " [11] ,FLEXCAN0_INT status" "Not set,Set" newline bitfld.long 0x1C 10. " [10] ,USDHC2_INT status" "Not set,Set" bitfld.long 0x1C 9. " [9] ,USDHC1_INT status" "Not set,Set" bitfld.long 0x1C 8. " [8] ,EMMC0_INT/USDHC0_INT status" "Not set,Set" bitfld.long 0x1C 4. " [4] ,UART3_INT status" "Not set,Set" newline bitfld.long 0x1C 3. " [3] ,UART2_INT status" "Not set,Set" bitfld.long 0x1C 2. " [2] ,UART1_INT status" "Not set,Set" bitfld.long 0x1C 1. " [1] ,UART0_INT status" "Not set,Set" line.long 0x20 "STATUS9,Interrupt Status 9 Register" bitfld.long 0x20 31. " STATUS[31] ,I2C3_INT status" "Not set,Set" bitfld.long 0x20 30. " [30] ,I2C2_INT status" "Not set,Set" bitfld.long 0x20 29. " [29] ,I2C1_INT status" "Not set,Set" bitfld.long 0x20 28. " [28] ,I2C0_INT status" "Not set,Set" newline bitfld.long 0x20 27. " [27] ,SPI3_INT status" "Not set,Set" bitfld.long 0x20 26. " [26] ,SPI2_INT status" "Not set,Set" bitfld.long 0x20 25. " [25] ,SPI1_INT status" "Not set,Set" bitfld.long 0x20 24. " [24] ,SPI0_INT status" "Not set,Set" newline bitfld.long 0x20 16. " [16] ,MU13_INT_B status" "Not set,Set" bitfld.long 0x20 15. " [15] ,MU12_INT_B status" "Not set,Set" bitfld.long 0x20 14. " [14] ,MU11_INT_B status" "Not set,Set" bitfld.long 0x20 13. " [13] ,MU10_INT_B status" "Not set,Set" newline bitfld.long 0x20 12. " [12] ,MU9_INT_B status" "Not set,Set" bitfld.long 0x20 11. " [11] ,MU8_INT_B status" "Not set,Set" bitfld.long 0x20 10. " [10] ,MU7_INT_B status" "Not set,Set" bitfld.long 0x20 9. " [9] ,MU6_INT_B status" "Not set,Set" newline bitfld.long 0x20 8. " [8] ,MU5_INT_B status" "Not set,Set" bitfld.long 0x20 0. " [0] ,MU13_INT_A status" "Not set,Set" line.long 0x24 "STATUS10,Interrupt Status 10 Register" bitfld.long 0x24 31. " STATUS[31] ,MU12_INT_A status" "Not set,Set" bitfld.long 0x24 30. " [30] ,MU11_INT_A status" "Not set,Set" bitfld.long 0x24 29. " [29] ,MU10_INT_A status" "Not set,Set" bitfld.long 0x24 28. " [28] ,MU9_INT_A status" "Not set,Set" newline bitfld.long 0x24 27. " [27] ,MU8_INT_A status" "Not set,Set" bitfld.long 0x24 26. " [26] ,MU7_INT_A status" "Not set,Set" bitfld.long 0x24 25. " [25] ,MU6_INT_A status" "Not set,Set" bitfld.long 0x24 24. " [24] ,MU5_INT_A status" "Not set,Set" newline bitfld.long 0x24 20. " [20] ,MU4_INT status" "Not set,Set" bitfld.long 0x24 19. " [19] ,MU3_INT status" "Not set,Set" bitfld.long 0x24 18. " [18] ,MU2_INT status" "Not set,Set" bitfld.long 0x24 17. " [17] ,MU1_INT status" "Not set,Set" newline bitfld.long 0x24 16. " [16] ,MU0_INT status" "Not set,Set" line.long 0x28 "STATUS11,Interrupt Status 11 Register" bitfld.long 0x28 15. " STATUS[15] ,GPIO_INT[7] status" "Not set,Set" bitfld.long 0x28 14. " [14] ,GPIO_INT[6] status" "Not set,Set" bitfld.long 0x28 13. " [13] ,GPIO_INT[5] status" "Not set,Set" bitfld.long 0x28 12. " [12] ,GPIO_INT[4] status" "Not set,Set" newline bitfld.long 0x28 11. " [11] ,GPIO_INT[3] status" "Not set,Set" bitfld.long 0x28 10. " [10] ,GPIO_INT[2] status" "Not set,Set" bitfld.long 0x28 9. " [9] ,GPIO_INT[1] status" "Not set,Set" bitfld.long 0x28 8. " [8] ,GPIO_INT[0] status" "Not set,Set" newline bitfld.long 0x28 3. " [3] ,PERF_CNT_INT status" "Not set,Set" bitfld.long 0x28 2. " [2] ,SBR_DONE_INT status" "Not set,Set" bitfld.long 0x28 1. " [1] ,ECC_NCORRECT_INT status" "Not set,Set" bitfld.long 0x28 0. " [0] ,ECC_CORRECT_INT status" "Not set,Set" line.long 0x2C "STATUS12,Interrupt Status 12 Register" bitfld.long 0x2C 27. " STATUS[27] ,SYS_COUNT_INT[3] status" "Not set,Set" bitfld.long 0x2C 26. " [26] ,SYS_COUNT_INT[2] status" "Not set,Set" bitfld.long 0x2C 25. " [25] ,SYS_COUNT_INT[1] status" "Not set,Set" bitfld.long 0x2C 24. " [24] ,SYS_COUNT_INT[0] status" "Not set,Set" newline bitfld.long 0x2C 23. " [23] ,INT_OUT[7] status" "Not set,Set" bitfld.long 0x2C 22. " [22] ,INT_OUT[6] status" "Not set,Set" bitfld.long 0x2C 21. " [21] ,INT_OUT[5] status" "Not set,Set" bitfld.long 0x2C 20. " [20] ,INT_OUT[4] status" "Not set,Set" newline bitfld.long 0x2C 19. " [19] ,INT_OUT[3] status" "Not set,Set" bitfld.long 0x2C 18. " [18] ,INT_OUT[2] status" "Not set,Set" bitfld.long 0x2C 17. " [17] ,INT_OUT[1] status" "Not set,Set" bitfld.long 0x2C 16. " [16] ,INT_OUT[0] status" "Not set,Set" newline bitfld.long 0x2C 15. " [15] ,PCIE9_GPIO_WAKEUP[1] status" "Not set,Set" bitfld.long 0x2C 14. " [14] ,PCIE9_GPIO_WAKEUP[0] status" "Not set,Set" bitfld.long 0x2C 13. " [13] ,PCIE0_SMLH_REQ_RST status" "Not set,Set" bitfld.long 0x2C 12. " [12] ,PCIE0_INT_A status" "Not set,Set" newline bitfld.long 0x2C 11. " [11] ,PCIE0_INT_B status" "Not set,Set" bitfld.long 0x2C 10. " [10] ,PCIE0_INT_C status" "Not set,Set" bitfld.long 0x2C 9. " [9] ,PCIE0_INT_D status" "Not set,Set" bitfld.long 0x2C 8. " [8] ,PCIE0_DMA_INT status" "Not set,Set" newline bitfld.long 0x2C 7. " [7] ,PCIE0_CLK_REQ_INT status" "Not set,Set" bitfld.long 0x2C 6. " [6] ,PCIE0_MSI_CTRL_INT status" "Not set,Set" bitfld.long 0x2C 5. " [5] ,PWM7_INT status" "Not set,Set" bitfld.long 0x2C 4. " [4] ,PWM6_INT status" "Not set,Set" newline bitfld.long 0x2C 3. " [3] ,PWM5_INT status" "Not set,Set" bitfld.long 0x2C 2. " [2] ,PWM4_INT status" "Not set,Set" bitfld.long 0x2C 1. " [1] ,PWM3_INT status" "Not set,Set" bitfld.long 0x2C 0. " [0] ,PWM2_INT status" "Not set,Set" line.long 0x30 "STATUS13,Interrupt Status 13 Register" bitfld.long 0x30 31. " STATUS[31] ,PWM1_INT status" "Not set,Set" bitfld.long 0x30 30. " [30] ,PWM0_INT status" "Not set,Set" bitfld.long 0x30 29. " [29] ,FLEXSPI1_INT status" "Not set,Set" bitfld.long 0x30 28. " [28] ,FLEXSPI0_INT status" "Not set,Set" newline bitfld.long 0x30 21. " [21] ,KPP0_INT status" "Not set,Set" bitfld.long 0x30 20. " [20] ,GPT4_INT status" "Not set,Set" bitfld.long 0x30 19. " [19] ,GPT3_INT status" "Not set,Set" bitfld.long 0x30 18. " [18] ,GPT2_INT status" "Not set,Set" newline bitfld.long 0x30 17. " [17] ,GPT1_INT status" "Not set,Set" bitfld.long 0x30 16. " [16] ,GPT0_INT status" "Not set,Set" bitfld.long 0x30 5. " [5] ,DMA3_ERR_INT status" "Not set,Set" bitfld.long 0x30 4. " [4] ,DMA3_INT status" "Not set,Set" newline bitfld.long 0x30 3. " [3] ,DMA2_ERR_INT status" "Not set,Set" bitfld.long 0x30 2. " [2] ,DMA2_INT status" "Not set,Set" bitfld.long 0x30 0. " [0] ,XAQ2_INTR status" "Not set,Set" line.long 0x34 "STATUS14,Interrupt Status 14 Register" bitfld.long 0x34 31. " STATUS[31] ,LCD_PWM_INT status" "Not set,Set" bitfld.long 0x34 30. " [30] ,LCD_MOD_INT status" "Not set,Set" bitfld.long 0x34 28. " [28] ,INT_OUT status" "Not set,Set" bitfld.long 0x34 27. " [27] ,INT_OUT status" "Not set,Set" newline bitfld.long 0x34 20. " [20] ,INT_OUT[12] status" "Not set,Set" bitfld.long 0x34 19. " [19] ,INT_OUT[11] status" "Not set,Set" bitfld.long 0x34 18. " [18] ,INT_OUT[10] status" "Not set,Set" bitfld.long 0x34 17. " [17] ,INT_OUT[9] status" "Not set,Set" newline bitfld.long 0x34 15. " [15] ,INT_OUT[7] status" "Not set,Set" bitfld.long 0x34 14. " [14] ,INT_OUT[6] status" "Not set,Set" bitfld.long 0x34 13. " [13] ,INT_OUT[5] status" "Not set,Set" bitfld.long 0x34 12. " [12] ,INT_OUT[4] status" "Not set,Set" newline bitfld.long 0x34 11. " [11] ,INT_OUT[3] status" "Not set,Set" bitfld.long 0x34 10. " [10] ,INT_OUT[2] status" "Not set,Set" bitfld.long 0x34 9. " [9] ,INT_OUT[1] status" "Not set,Set" bitfld.long 0x34 8. " [8] ,INT_OUT[0] status" "Not set,Set" line.long 0x38 "STATUS15,Interrupt Status 15 Register" bitfld.long 0x38 23. " STATUS[23] ,INT_OUT[7] status" "Not set,Set" bitfld.long 0x38 22. " [22] ,INT_OUT[6] status" "Not set,Set" bitfld.long 0x38 21. " [21] ,INT_OUT[5] status" "Not set,Set" bitfld.long 0x38 20. " [20] ,INT_OUT[4] status" "Not set,Set" newline bitfld.long 0x38 19. " [19] ,INT_OUT[3] status" "Not set,Set" bitfld.long 0x38 18. " [18] ,INT_OUT[2] status" "Not set,Set" bitfld.long 0x38 17. " [17] ,INT_OUT[1] status" "Not set,Set" bitfld.long 0x38 16. " [16] ,INT_OUT[0] status" "Not set,Set" newline bitfld.long 0x38 1. " [1] ,nEXTERRIRQ status" "Not set,Set" bitfld.long 0x38 0. " [0] ,nINTERRIRQ status" "Not set,Set" group.long 0xC4++0x03 line.long 0x00 "MINTDIS,Master Interrupt Disable Register" bitfld.long 0x00 7. " DISABLE[7] ,Disables interrupts from 511 to 448" "No,Yes" bitfld.long 0x00 6. " [6] ,Disables interrupts from 447 to 384" "No,Yes" bitfld.long 0x00 5. " [5] ,Disables interrupts from 383 to 320" "No,Yes" bitfld.long 0x00 4. " [4] ,Disables interrupts from 319 to 256" "No,Yes" newline bitfld.long 0x00 3. " [3] ,Disables interrupts from 255 to 192" "No,Yes" bitfld.long 0x00 2. " [2] ,Disables interrupts from 191 to 128" "No,Yes" bitfld.long 0x00 1. " [1] ,Disables interrupts from 127 to 64" "No,Yes" bitfld.long 0x00 0. " [0] ,Disables interrupts from 63 to 0" "No,Yes" newline rgroup.long 0xC8++0x03 line.long 0x00 "MSTRSTAT,Master Status Register" bitfld.long 0x00 0. " STATUS ,Status of all interrupts" "Not asserted,At least one interrupt is asserted" width 0x0B tree.end tree.end tree.end tree.open "Imaging" tree "MIPI-CSI-2 (MIPI-CSI-2 Control)" base ad:0x58227000 width 27. group.long 0x00++0x07 line.long 0x00 "CFG_NUM_LANES,Lane Configuration Register" bitfld.long 0x00 0.--1. " CFG_NUM_LANES ,Sets the number of active lanes that are to be used for receiving data" "1 lane,2 lanes,3 lanes,4 lanes" line.long 0x04 "CFG_DISABLE_DATA_LANES,Disable Data Lane Register" bitfld.long 0x04 3. " CFG_DISABLE_DATA_LANES[3] ,Data line 3 disable" "No,Yes" bitfld.long 0x04 2. " [2] ,Data line 2 disable" "No,Yes" newline bitfld.long 0x04 1. " [1] ,Data line 1 disable" "No,Yes" bitfld.long 0x04 0. " [0] ,Data line 0 disable" "No,Yes" rgroup.long 0x08++0x07 line.long 0x00 "BIT_ERR,ECC/CRC Error Status Register" bitfld.long 0x00 9. " BIT_ERR[9] ,RX video interface signal vid_err_fifo_wr_ovfl has asserted since the last read of this register" "No,Yes" bitfld.long 0x00 8. " [8] ,RX video interface signal vid_err_send_level has asserted since the last read of this register" "No,Yes" newline bitfld.long 0x00 7. " [7] ,CRC error has occurred since the last read of this register" "Not occurred,Occurred" bitfld.long 0x00 2.--6. " [6:2] ,ECC one bit error bit position that occurred since the last read of this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 1. " [1] ,ECC one bit error has occurred since the last read of this register" "Not occurred,Occurred" bitfld.long 0x00 0. " [0] ,ECC two bit error has occurred since the last read of this register" "Not occurred,Occurred" line.long 0x04 "IRQ_STATUS,IRQ Status Register" bitfld.long 0x04 8. " IRQ_STATUS[8] ,CSI2 RX IRQ DPHY ErrControl status" "Not occurred,Occurred" bitfld.long 0x04 7. " [7] ,CSI2 RX IRQ DPHY ErrSyncEsc status" "Not occurred,Occurred" newline bitfld.long 0x04 6. " [6] ,CSI2 RX IRQ DPHY ErrEsc status" "Not occurred,Occurred" bitfld.long 0x04 5. " [5] ,CSI2 RX IRQ DPHY ErrSotSync_HS status" "Not occurred,Occurred" newline bitfld.long 0x04 4. " [4] ,CSI2 RX IRQ DPHY ErrSotHS status" "Not occurred,Occurred" bitfld.long 0x04 3. " [3] ,CSI2 RX IRQ ULPS status change status" "Not occurred,Occurred" newline bitfld.long 0x04 2. " [2] ,CSI2 RX IRQ two bit ECC error status" "Not occurred,Occurred" bitfld.long 0x04 1. " [1] ,CSI2 RX IRQ one bit ECC error status" "Not occurred,Occurred" newline bitfld.long 0x04 0. " [0] ,CSI2 RX IRQ CRC error status" "Not occurred,Occurred" group.long 0x10++0x03 line.long 0x00 "IRQ_MASK,IRQ Mask Setting Register" bitfld.long 0x00 8. " MASK[8:0] ,IRQ_STATUS bit 8 mask" "0,1" bitfld.long 0x00 7. ",IRQ_STATUS bit 7 mask" "0,1" bitfld.long 0x00 6. ",IRQ_STATUS bit 6 mask" "0,1" bitfld.long 0x00 5. ",IRQ_STATUS bit 5 mask" "0,1" bitfld.long 0x00 4. ",IRQ_STATUS bit 4 mask" "0,1" bitfld.long 0x00 3. ",IRQ_STATUS bit 3 mask" "0,1" bitfld.long 0x00 2. ",IRQ_STATUS bit 2 mask" "0,1" bitfld.long 0x00 1. ",IRQ_STATUS bit 1 mask" "0,1" bitfld.long 0x00 0. ",IRQ_STATUS bit 0 mask" "0,1" rgroup.long 0x14++0x17 line.long 0x00 "ULPS_STATUS,ULPS Status Register" bitfld.long 0x00 9. " ULPS_STATUS[9] ,Data lane 3 in Mark state indicator" "Not Mark,Mark" bitfld.long 0x00 8. " [8] ,Data lane 2 in Mark state indicator" "Not Mark,Mark" newline bitfld.long 0x00 7. " [7] ,Data lane 1 in Mark state indicator" "Not Mark,Mark" bitfld.long 0x00 6. " [6] ,Data lane 0 in Mark state indicator" "Not Mark,Mark" newline bitfld.long 0x00 5. " [5] ,Clock lane in Mark state indicator" "Not Mark,Mark" bitfld.long 0x00 4. " [4] ,Data lane 3 in ULPS state indicator" "Not ULPS,ULPS" newline bitfld.long 0x00 3. " [3] ,Data lane 2 in ULPS state indicator" "Not ULPS,ULPS" bitfld.long 0x00 2. " [2] ,Data lane 1 in ULPS state indicator" "Not ULPS,ULPS" newline bitfld.long 0x00 1. " [1] ,Data lane 0 in ULPS state indicator" "Not ULPS,ULPS" bitfld.long 0x00 0. " [0] ,Clock lane in ULPS state indicator" "Not ULPS,ULPS" line.long 0x04 "PPI_ERRSOT_HS,ErrSot HS Status Register" bitfld.long 0x04 0.--3. " PPI_ERRSOT_HS ,CSI2 RX DPHY PPI ErrSotHS captured status from the DPHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "PPI_ERRSOTSYNC_HS,ErrSotSync HS Status Register" bitfld.long 0x08 0.--3. " PPI_ERRSOTSYNC_HS ,CSI2 RX DPHY PPI ErrSotSync_HS captured status from the DPHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "PPI_ERRESC,ErrEsc Status Register" bitfld.long 0x0C 0.--3. " PPI_ERRESC ,CSI2 RX DPHY PPI ErrEsc captured status from the DPHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "PPI_ERRSYNCESC,ErrSyncEsc Status Register" bitfld.long 0x10 0.--3. " PPI_ERRSYNCESC ,CSI2 RX DPHY PPI ErrSyncEsc captured status from the DPHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "PPI_ERRCONTROL,ErrControl Status Register" bitfld.long 0x14 0.--3. " PPI_ERRCONTROL ,CSI2 RX DPHY PPI ErrControl captured status from the DPHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline group.long 0x2C++0x07 line.long 0x00 "CFG_DISABLE_PAYLOAD_0,Disable Payload 0 Register" bitfld.long 0x00 29. " CFG_DISABLE_PAYLOAD_RAW14 ,RAW14 payload disable" "No,Yes" bitfld.long 0x00 28. " CFG_DISABLE_PAYLOAD_RAW12 ,RAW12 payload disable" "No,Yes" newline bitfld.long 0x00 27. " CFG_DISABLE_PAYLOAD_RAW10 ,RAW10 payload disable" "No,Yes" bitfld.long 0x00 26. " CFG_DISABLE_PAYLOAD_RAW8 ,RAW8 payload disable" "No,Yes" newline bitfld.long 0x00 25. " CFG_DISABLE_PAYLOAD_RAW7 ,RAW7 payload disable" "No,Yes" bitfld.long 0x00 24. " CFG_DISABLE_PAYLOAD_RAW6 ,RAW6 payload disable" "No,yes" newline bitfld.long 0x00 20. " CFG_DISABLE_PAYLOAD_RGB888 ,RGB888 payload disable" "No,Yes" bitfld.long 0x00 19. " CFG_DISABLE_PAYLOAD_RGB666 ,RGB666 payload disable" "No,Yes" newline bitfld.long 0x00 18. " CFG_DISABLE_PAYLOAD_RGB565 ,RGB565 payload disable" "No,Yes" bitfld.long 0x00 17. " CFG_DISABLE_PAYLOAD_RGB555 ,RGB555 payload disable" "No,Yes" newline bitfld.long 0x00 16. " CFG_DISABLE_PAYLOAD_RGB444 ,RGB444 payload disable" "No,Yes" bitfld.long 0x00 15. " CFG_DISABLE_PAYLOAD_YUV_10 ,YUV422 10 bit payload disable" "No,Yes" newline bitfld.long 0x00 14. " CFG_DISABLE_PAYLOAD_YUV_8 ,YUV422 8 bit payload disable" "No,Yes" bitfld.long 0x00 10. " CFG_DISABLE_PAYLOAD_LEGACY_YUV_8 ,Legacy YUV 420 8 bit payload disable" "No,Yes" newline bitfld.long 0x00 2. " CFG_DISABLE_PAYLOAD_EMBEDDED ,Embedded payload disable" "No,Yes" bitfld.long 0x00 1. " CFG_DISABLE_PAYLOAD_BLANK ,Blank payload disable" "No,Yes" newline bitfld.long 0x00 0. " CFG_DISABLE_PAYLOAD_NULL ,Null payload disable" "No,Yes" line.long 0x04 "CFG_DISABLE_PAYLOAD_1,Disable Payload 1 Register" bitfld.long 0x04 16. " CFG_DISABLE_PAYLOAD_UNSUPPORTED ,Unsupported data types payload disable" "No,Yes" bitfld.long 0x04 7. " CFG_DISABLE_PAYLOAD_UDEF_37 ,User defined type 0x37 payload disable" "No,Yes" newline bitfld.long 0x04 6. " CFG_DISABLE_PAYLOAD_UDEF_36 ,User defined type 0x36 payload disable" "No,Yes" bitfld.long 0x04 5. " CFG_DISABLE_PAYLOAD_UDEF_35 ,User defined type 0x35 payload disable" "No,Yes" newline bitfld.long 0x04 4. " CFG_DISABLE_PAYLOAD_UDEF_34 ,User defined type 0x34 payload disable" "No,Yes" bitfld.long 0x04 3. " CFG_DISABLE_PAYLOAD_UDEF_33 ,User defined type 0x33 payload disable" "No,Yes" newline bitfld.long 0x04 2. " CFG_DISABLE_PAYLOAD_UDEF_32 ,User defined type 0x32 payload disable" "No,Yes" bitfld.long 0x04 1. " CFG_DISABLE_PAYLOAD_UDEF_31 ,User defined type 0x31 payload disable" "No,Yes" newline bitfld.long 0x04 0. " CFG_DISABLE_PAYLOAD_UDEF_30 ,User defined type 0x30 payload disable" "No,Yes" group.long 0x88++0x13 line.long 0x00 "CFG_VID_P_FIFO_SEND_LEVEL,FIFO Send Level Configuration Register" hexmask.long.word 0x00 0.--15. 1. " CFG_VID_P_FIFO_SEND_LEVEL ,Entries number accumulated in Pixel FIFO" line.long 0x04 "CFG_VID_VSYNC,VSYNC Configuration Register" hexmask.long.byte 0x04 0.--7. 1. " CFG_VID_VSYNC ,VSYNC width" line.long 0x08 "CFG_VID_HSYNC_FP,Start Of HSYNC Delay Control Register" hexmask.long.byte 0x08 0.--7. 1. " CFG_VID_HSYNC_FP ,Delay control for beginning of HSYNC pulse" line.long 0x0C "CFG_VID_HSYNC,HSYNC Configuration Register" hexmask.long.byte 0x0C 0.--7. 1. " CFG_VID_HSYNC ,HSYNC width" line.long 0x10 "CFG_VID_HSYNC_BP,End Of HSYNC Delay Control Register" hexmask.long.byte 0x10 0.--7. 1. " CFG_VID_HSYNC_BP ,Delay control for end of HSYNC pulse" width 0x0B tree.end tree "I2C (I2C Controller)" base ad:0x58226000 width 8. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number" line.long 0x04 "PARAM,Parameter Register" bitfld.long 0x04 8.--11. " MRXFIFO ,Master receive FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x04 0.--3. " MTXFIFO ,Master transmit FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" group.long 0x10++0x13 line.long 0x00 "MCR,Master Control Register" bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset" bitfld.long 0x00 3. " DBGEN ,Debug enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " MEN ,Master enable" "Disabled,Enabled" line.long 0x04 "MSR,Master Status Register" rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x04 24. " MBF ,Master busy flag" "Idle,Busy" eventfld.long 0x04 14. " DMF ,Data match flag" "Not received,Received" eventfld.long 0x04 13. " PLTF ,Pin low timeout flag" "Not occurred/disabled,Occurred" newline eventfld.long 0x04 12. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x04 11. " ALF ,Arbitration lost flag" "Not lost,Lost" eventfld.long 0x04 10. " NDF ,NACK detect flag" "Not detected,Detected" eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected" newline eventfld.long 0x04 8. " EPF ,End packet flag" "Not generated/Repeated,Generated/Repeated" rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "MIER,Master Interrupt Enable Register" bitfld.long 0x08 14. " DMIE ,Data match interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " PLTIE ,Pin low timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " FEIE ,FIFO error interrupt disable" "No,Yes" newline bitfld.long 0x08 11. " ALIE ,Arbitration lost interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " NDIE ,NACK detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " EPIE ,End packet interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "MDER,Master DMA Enable Register" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" line.long 0x10 "MCFGR0,Master Configuration Register 0" bitfld.long 0x10 9. " RDMO ,Receive data match only" "Stored,Discarded" bitfld.long 0x10 8. " CIRFIFO ,Circular FIFO enable" "Disabled,Enabled" bitfld.long 0x10 2. " HRSEL ,Host request select" "HREQ pin,Input trigger" newline bitfld.long 0x10 1. " HRPOL ,Host request polarity" "Active low,Active high" bitfld.long 0x10 0. " HREN ,Host request enable" "Disabled,Enabled" newline if (((per.l(ad:0x58226000+0x10))&0x01)==0x01) rgroup.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Disabled,,1st word = MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "SCL,SCL or SDA" newline bitfld.long 0x00 9. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "No effect,Enabled" bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" else group.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Disabled,,1st word = MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "On SCL low too long,On SCL or SDA low too long" newline bitfld.long 0x00 9. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "No effect,Enabled" bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" endif newline if ((((per.l(ad:0x58226000+0x10))&0x01)==0x00)||(((per.l(ad:0x58226000+0x14))&0x1000000)==0x00)) group.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" else rgroup.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" endif if (((per.l(ad:0x58226000+0x10))&0x01)==0x01) rgroup.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x58++0x03 line.long 0x00 "MFCR,Master FIFO Control Register" bitfld.long 0x00 16.--17. " RXWATER ,Receive FIFO watermark" "0,1,2,3" bitfld.long 0x00 0.--1. " TXWATER ,Transmit FIFO watermark" "0,1,2,3" rgroup.long 0x5C++0x03 line.long 0x00 "MFSR,Master FIFO Status Register" bitfld.long 0x00 16.--18. " RXCOUNT ,Receive FIFO count" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " TXCOUNT ,Transmit FIFO count" "0,1,2,3,4,5,6,7" newline wgroup.long 0x60++0x03 line.long 0x00 "MTDR,Master Transmit Data Register" bitfld.long 0x00 8.--10. " CMD ,Command data" "Transmit,Receive,Generate STOP,Receive and discard,START and transmit,START and transmit (NACK returned),START and transmit (high speed mode),START and transmit high speed mode (NACK returned)" newline hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data" newline hgroup.long 0x70++0x03 hide.long 0x00 "MRDR,Master Receive Data Register" in newline group.long 0x110++0x0F line.long 0x00 "SCR,Slave Control Register" bitfld.long 0x00 9. " RRF ,Receive FIFO reset" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Transmit FIFO reset" "No effect,Reset" bitfld.long 0x00 5. " FILTDZ ,Filter doze enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " FILTEN ,Filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " SEN ,Slave enable" "Disabled,Enabled" line.long 0x04 "SSR,Slave Status Register" rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x04 24. " SBF ,Slave busy flag" "Idle,Busy" rbitfld.long 0x04 15. " SARF ,SMBus alert response flag" "Not detected,Detected" rbitfld.long 0x04 14. " GCF ,General call flag" "Not detected,Detected" newline rbitfld.long 0x04 13. " AM1F ,Address match 1 flag" "Not matched,Matched" rbitfld.long 0x04 12. " AM0F ,Address match 0 flag" "Not matched,Matched" eventfld.long 0x04 11. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x04 10. " BEF ,Bit error flag" "No error,Error" newline eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected" eventfld.long 0x04 8. " RSF ,Repeated start flag" "Not detected,Detected" rbitfld.long 0x04 3. " TAF ,Transmit ACK flag" "Not required,Required" rbitfld.long 0x04 2. " AVF ,Address valid flag" "Invalid,Valid" newline rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "SIER,Slave Interrupt Enable Register" bitfld.long 0x08 15. " SARIE ,SMBus alert response interrupt enable" "Disabled,Enabled" bitfld.long 0x08 14. " GCIE ,General call interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " AM1F ,Address match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " AM0IE ,Address match 0 interrupt disable" "No,Yes" newline bitfld.long 0x08 11. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " BEIE ,Bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 8. " RSIE ,Repeated start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " TAIE ,Transmit ACK interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " AVIE ,Address valid interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "SDER,Slave DMA Enable Register" bitfld.long 0x0C 2. " AVDE ,Address valid DMA enable" "Disabled,Enabled" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" newline if (((per.l(ad:0x58226000+0x110))&0x01)==0x01) rgroup.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration match" "0 (7-bit),0 (10-bit),0 (7-bit) / 1 (7-bit),0 (10-bit) / 1 (10-bit),0 (7-bit) / 1 (10-bit),0 (10-bit) / 1 (7-bit),From 0 (7-bit) to 1 (7-bit),From 0 (10-bit) to 1 (10-bit)" bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" bitfld.long 0x00 12. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return data / clear RDF,Return address / clear AVF" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer,On TDR empty" bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration match" "0 (7-bit),0 (10-bit),0 (7-bit) / 1 (7-bit),0 (10-bit) / 1 (10-bit),0 (7-bit) / 1 (10-bit),0 (10-bit) / 1 (7-bit),From 0 (7-bit) to 1 (7-bit),From 0 (10-bit) to 1 (10-bit)" bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" bitfld.long 0x00 12. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return data / clear RDF,Return address / clear AVF" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer,On TDR empty" bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline if (((per.l(ad:0x58226000+0x110))&0x01)==0x01) rgroup.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" else group.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" endif rgroup.long 0x150++0x03 line.long 0x00 "SASR,Slave Address Status Register" bitfld.long 0x00 14. " ANV ,Address invalid" "No,Yes" hexmask.long.word 0x00 0.--10. 0x01 " RADDR ,Received address" if (((per.l(ad:0x58226000+0x124))&0x08)==0x08) group.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,NACK transmit" "ACK,NACK" else rgroup.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,NACK transmit" "ACK,NACK" endif wgroup.long 0x160++0x03 line.long 0x00 "STDR,Slave Transmit Data Register" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data" rgroup.long 0x170++0x03 line.long 0x00 "SRDR,Slave Receive Data Register" bitfld.long 0x00 15. " SOF ,Start of frame" "Not the first data word,First data word" bitfld.long 0x00 14. " RXEMPTY ,RX empty" "Not empty,Empty" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data receive" width 0x0B tree.end tree "PWM (Pulse Width Modulation)" base ad:0x58224000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO water mark (FIFO empty flag set threshold)" ">= 1 empty slot,>= 2 empty slots,>= 3 empty slots,>= 4 empty slots" bitfld.long 0x00 25. " STOPEN ,Stop mode enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait mode enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " DBGEN ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte data swap control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word data swap control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM output configuration" "Set=rollover/Cleared=comparison,Set=comparison/Cleared=rollover,Disconnected,Disconnected" newline bitfld.long 0x00 16.--17. " CLKSRC ,Clock source select" "Off,IPG_CLK,IPG_CLK_HIGHFREQ,IPG_CLK_32K" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter clock prescaler value" bitfld.long 0x00 3. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample repeat" "Once,Twice,Four times,Eight times" newline bitfld.long 0x00 0. " EN ,PWM enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO write error status" "No error,Error" eventfld.long 0x04 5. " CMP ,Compare event status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over event status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO empty status" "Not empty,Empty" newline rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO available" "No available,1 word,2 words,3 words,4 words,?..." line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO empty interrupt enable" "Disabled,Enabled" line.long 0x0C "PWMSAR,PWM Sample Register" hexmask.long.word 0x0C 0.--15. 1. " SAMPLE ,Sample value" line.long 0x10 "PWMPR,PWM Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Period value" rgroup.long 0x14++0x03 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" width 0x0B tree.end tree "GPIO (General Purpose Input/Output)" base ad:0x58222000 width 11. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data Register" bitfld.long 0x00 31. " DR[31] ,Data bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,Data bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,Data bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,Data bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,Data bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,Data bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,Data bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,Data bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,Data bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,Data bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,Data bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,Data bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,Data bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,Data bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,Data bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,Data bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,Data bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,Data bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,Data bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,Data bit 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,Data bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,Data bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,Data bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,Data bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,Data bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,Data bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,Data bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,Data bit 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,Data bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,Data bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,Data bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,Data bit 0" "Low,High" line.long 0x04 "GDIR,GPIO Direction Register" bitfld.long 0x04 31. " GDIR[31] ,GPIO direction 31 bit" "Input,Output" bitfld.long 0x04 30. " [30] ,GPIO direction 30 bit" "Input,Output" bitfld.long 0x04 29. " [29] ,GPIO direction 29 bit" "Input,Output" bitfld.long 0x04 28. " [28] ,GPIO direction 28 bit" "Input,Output" newline bitfld.long 0x04 27. " [27] ,GPIO direction 27 bit" "Input,Output" bitfld.long 0x04 26. " [26] ,GPIO direction 26 bit" "Input,Output" bitfld.long 0x04 25. " [25] ,GPIO direction 25 bit" "Input,Output" bitfld.long 0x04 24. " [24] ,GPIO direction 24 bit" "Input,Output" newline bitfld.long 0x04 23. " [23] ,GPIO direction 23 bit" "Input,Output" bitfld.long 0x04 22. " [22] ,GPIO direction 22 bit" "Input,Output" bitfld.long 0x04 21. " [21] ,GPIO direction 21 bit" "Input,Output" bitfld.long 0x04 20. " [20] ,GPIO direction 20 bit" "Input,Output" newline bitfld.long 0x04 19. " [19] ,GPIO direction 19 bit" "Input,Output" bitfld.long 0x04 18. " [18] ,GPIO direction 18 bit" "Input,Output" bitfld.long 0x04 17. " [17] ,GPIO direction 17 bit" "Input,Output" bitfld.long 0x04 16. " [16] ,GPIO direction 16 bit" "Input,Output" newline bitfld.long 0x04 15. " [15] ,GPIO direction 15 bit" "Input,Output" bitfld.long 0x04 14. " [14] ,GPIO direction 14 bit" "Input,Output" bitfld.long 0x04 13. " [13] ,GPIO direction 13 bit" "Input,Output" bitfld.long 0x04 12. " [12] ,GPIO direction 12 bit" "Input,Output" newline bitfld.long 0x04 11. " [11] ,GPIO direction 11 bit" "Input,Output" bitfld.long 0x04 10. " [10] ,GPIO direction 10 bit" "Input,Output" bitfld.long 0x04 9. " [9] ,GPIO direction 9 bit" "Input,Output" bitfld.long 0x04 8. " [8] ,GPIO direction 8 bit" "Input,Output" newline bitfld.long 0x04 7. " [7] ,GPIO direction 7 bit" "Input,Output" bitfld.long 0x04 6. " [6] ,GPIO direction 6 bit" "Input,Output" bitfld.long 0x04 5. " [5] ,GPIO direction 5 bit" "Input,Output" bitfld.long 0x04 4. " [4] ,GPIO direction 4 bit" "Input,Output" newline bitfld.long 0x04 3. " [3] ,GPIO direction 3 bit" "Input,Output" bitfld.long 0x04 2. " [2] ,GPIO direction 2 bit" "Input,Output" bitfld.long 0x04 1. " [1] ,GPIO direction 1 bit" "Input,Output" bitfld.long 0x04 0. " [0] ,GPIO direction 0 bit" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO Pad Status Register" bitfld.long 0x00 31. " PSR[31] ,GPIO pad status bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,GPIO pad status bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,GPIO pad status bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,GPIO pad status bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,GPIO pad status bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,GPIO pad status bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,GPIO pad status bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,GPIO pad status bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,GPIO pad status bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,GPIO pad status bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,GPIO pad status bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,GPIO pad status bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,GPIO pad status bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,GPIO pad status bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,GPIO pad status bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,GPIO pad status bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,GPIO pad status bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,GPIO pad status bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,GPIO pad status bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,GPIO pad status bit 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,GPIO pad status bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,GPIO pad status bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,GPIO pad status bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,GPIO pad status bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,GPIO pad status bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,GPIO pad status bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,GPIO pad status bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,GPIO pad status bit 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,GPIO pad status bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,GPIO pad status bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,GPIO pad status bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,GPIO pad status bit 0" "Low,High" group.long 0x0C++0x13 line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1" bitfld.long 0x00 30.--31. " ICR[15] ,Controls the active condition of the interrupt function for GPIO interrupt 15" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 28.--29. " [14] ,Controls the active condition of the interrupt function for GPIO interrupt 14" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 26.--27. " [13] ,Controls the active condition of the interrupt function for GPIO interrupt 13" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 24.--25. " [12] ,Controls the active condition of the interrupt function for GPIO interrupt 12" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 22.--23. " [11] ,Controls the active condition of the interrupt function for GPIO interrupt 11" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 20.--21. " [10] ,Controls the active condition of the interrupt function for GPIO interrupt 10" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 18.--19. " [9] ,Controls the active condition of the interrupt function for GPIO interrupt 9" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 16.--17. " [8] ,Controls the active condition of the interrupt function for GPIO interrupt 8" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 14.--15. " [7] ,Controls the active condition of the interrupt function for GPIO interrupt 7" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 12.--13. " [6] ,Controls the active condition of the interrupt function for GPIO interrupt 6" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 10.--11. " [5] ,Controls the active condition of the interrupt function for GPIO interrupt 5" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 8.--9. " [4] ,Controls the active condition of the interrupt function for GPIO interrupt 4" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 6.--7. " [3] ,Controls the active condition of the interrupt function for GPIO interrupt 3" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 4.--5. " [2] ,Controls the active condition of the interrupt function for GPIO interrupt 2" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 2.--3. " [1] ,Controls the active condition of the interrupt function for GPIO interrupt 1" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 0.--1. " [0] ,Controls the active condition of the interrupt function for GPIO interrupt 0" "Low-level,High-level,Rising-edge,Falling-edge" line.long 0x04 "ICR2,GPIO Interrupt Configuration Register 2" bitfld.long 0x04 30.--31. " [31] ,Controls the active condition of the interrupt function for GPIO interrupt 31" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 28.--29. " [30] ,Controls the active condition of the interrupt function for GPIO interrupt 30" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 26.--27. " [29] ,Controls the active condition of the interrupt function for GPIO interrupt 29" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 24.--25. " [28] ,Controls the active condition of the interrupt function for GPIO interrupt 28" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 22.--23. " [27] ,Controls the active condition of the interrupt function for GPIO interrupt 27" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 20.--21. " [26] ,Controls the active condition of the interrupt function for GPIO interrupt 26" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 18.--19. " [25] ,Controls the active condition of the interrupt function for GPIO interrupt 25" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 16.--17. " [24] ,Controls the active condition of the interrupt function for GPIO interrupt 24" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 14.--15. " [23] ,Controls the active condition of the interrupt function for GPIO interrupt 23" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 12.--13. " [22] ,Controls the active condition of the interrupt function for GPIO interrupt 22" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 10.--11. " [21] ,Controls the active condition of the interrupt function for GPIO interrupt 21" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 8.--9. " [20] ,Controls the active condition of the interrupt function for GPIO interrupt 20" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 6.--7. " [19] ,Controls the active condition of the interrupt function for GPIO interrupt 19" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 4.--5. " [18] ,Controls the active condition of the interrupt function for GPIO interrupt 18" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 2.--3. " [17] ,Controls the active condition of the interrupt function for GPIO interrupt 17" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 0.--1. " [16] ,Controls the active condition of the interrupt function for GPIO interrupt 16" "Low-level,High-level,Rising-edge,Falling-edge" line.long 0x08 "IMR,GPIO Interrupt Mask Register" bitfld.long 0x08 31. " IMR[31] ,Interrupt 31 mask bit" "Disabled,Enabled" bitfld.long 0x08 30. " [30] ,Interrupt 30 mask bit" "Disabled,Enabled" bitfld.long 0x08 29. " [29] ,Interrupt 29 mask bit" "Disabled,Enabled" bitfld.long 0x08 28. " [28] ,Interrupt 28 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 27. " [27] ,Interrupt 27 mask bit" "Disabled,Enabled" bitfld.long 0x08 26. " [26] ,Interrupt 26 mask bit" "Disabled,Enabled" bitfld.long 0x08 25. " [25] ,Interrupt 25 mask bit" "Disabled,Enabled" bitfld.long 0x08 24. " [24] ,Interrupt 24 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 23. " [23] ,Interrupt 23 mask bit" "Disabled,Enabled" bitfld.long 0x08 22. " [22] ,Interrupt 22 mask bit" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Interrupt 21 mask bit" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Interrupt 20 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 19. " [19] ,Interrupt 19 mask bit" "Disabled,Enabled" bitfld.long 0x08 18. " [18] ,Interrupt 18 mask bit" "Disabled,Enabled" bitfld.long 0x08 17. " [17] ,Interrupt 17 mask bit" "Disabled,Enabled" bitfld.long 0x08 16. " [16] ,Interrupt 16 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 15. " [15] ,Interrupt 15 mask bit" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Interrupt 14 mask bit" "Disabled,Enabled" bitfld.long 0x08 13. " [13] ,Interrupt 13 mask bit" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Interrupt 12 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 11. " [11] ,Interrupt 11 mask bit" "Disabled,Enabled" bitfld.long 0x08 10. " [10] ,Interrupt 10 mask bit" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Interrupt 9 mask bit" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Interrupt 8 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Interrupt 7 mask bit" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Interrupt 6 mask bit" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Interrupt 5 mask bit" "Disabled,Enabled" bitfld.long 0x08 4. " [4] ,Interrupt 4 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 3. " [3] ,Interrupt 3 mask bit" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Interrupt 2 mask bit" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Interrupt 1 mask bit" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Interrupt 0 mask bit" "Disabled,Enabled" line.long 0x0C "ISR,GPIO Interrupt Status Register" eventfld.long 0x0C 31. " ISR[31] ,Interrupt 31 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 30. " [30] ,Interrupt 30 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 29. " [29] ,Interrupt 29 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 28. " [28] ,Interrupt 28 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 27. " [27] ,Interrupt 27 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 26. " [26] ,Interrupt 26 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 25. " [25] ,Interrupt 25 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 24. " [24] ,Interrupt 24 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 23. " [23] ,Interrupt 23 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 22. " [22] ,Interrupt 22 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 21. " [21] ,Interrupt 21 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 20. " [20] ,Interrupt 20 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 19. " [19] ,Interrupt 19 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 18. " [18] ,Interrupt 18 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 17. " [17] ,Interrupt 17 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 16. " [16] ,Interrupt 16 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 15. " [15] ,Interrupt 15 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 14. " [14] ,Interrupt 14 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 13. " [13] ,Interrupt 13 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 12. " [12] ,Interrupt 12 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 11. " [11] ,Interrupt 11 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 10. " [10] ,Interrupt 10 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 9. " [9] ,Interrupt 9 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 8. " [8] ,Interrupt 8 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 7. " [7] ,Interrupt 7 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 6. " [6] ,Interrupt 6 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 5. " [5] ,Interrupt 5 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 4. " [4] ,Interrupt 4 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 3. " [3] ,Interrupt 3 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 2. " [2] ,Interrupt 2 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 1. " [1] ,Interrupt 1 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 0. " [0] ,Interrupt 0 status bit" "No interrupt,Interrupt" line.long 0x10 "EDGE_SEL,GPIO Edge Select Register" bitfld.long 0x10 31. " GPIO_EDGE_SEL[31] ,Edge select bit 31" "31 setting,Any edge" bitfld.long 0x10 30. " [30] ,Edge select bit 30" "30 setting,Any edge" bitfld.long 0x10 29. " [29] ,Edge select bit 29" "29 setting,Any edge" bitfld.long 0x10 28. " [28] ,Edge select bit 28" "28 setting,Any edge" newline bitfld.long 0x10 27. " [27] ,Edge select bit 27" "27 setting,Any edge" bitfld.long 0x10 26. " [26] ,Edge select bit 26" "26 setting,Any edge" bitfld.long 0x10 25. " [25] ,Edge select bit 25" "25 setting,Any edge" bitfld.long 0x10 24. " [24] ,Edge select bit 24" "24 setting,Any edge" newline bitfld.long 0x10 23. " [23] ,Edge select bit 23" "23 setting,Any edge" bitfld.long 0x10 22. " [22] ,Edge select bit 22" "22 setting,Any edge" bitfld.long 0x10 21. " [21] ,Edge select bit 21" "21 setting,Any edge" bitfld.long 0x10 20. " [20] ,Edge select bit 20" "20 setting,Any edge" newline bitfld.long 0x10 19. " [19] ,Edge select bit 19" "19 setting,Any edge" bitfld.long 0x10 18. " [18] ,Edge select bit 18" "18 setting,Any edge" bitfld.long 0x10 17. " [17] ,Edge select bit 17" "17 setting,Any edge" bitfld.long 0x10 16. " [16] ,Edge select bit 16" "16 setting,Any edge" newline bitfld.long 0x10 15. " [15] ,Edge select bit 15" "15 setting,Any edge" bitfld.long 0x10 14. " [14] ,Edge select bit 14" "14 setting,Any edge" bitfld.long 0x10 13. " [13] ,Edge select bit 13" "13 setting,Any edge" bitfld.long 0x10 12. " [12] ,Edge select bit 12" "12 setting,Any edge" newline bitfld.long 0x10 11. " [11] ,Edge select bit 11" "11 setting,Any edge" bitfld.long 0x10 10. " [10] ,Edge select bit 10" "10 setting,Any edge" bitfld.long 0x10 9. " [9] ,Edge select bit 9" "9 setting,Any edge" bitfld.long 0x10 8. " [8] ,Edge select bit 8" "8 setting,Any edge" newline bitfld.long 0x10 7. " [7] ,Edge select bit 7" "7 setting,Any edge" bitfld.long 0x10 6. " [6] ,Edge select bit 6" "6 setting,Any edge" bitfld.long 0x10 5. " [5] ,Edge select bit 5" "5 setting,Any edge" bitfld.long 0x10 4. " [4] ,Edge select bit 4" "4 setting,Any edge" newline bitfld.long 0x10 3. " [3] ,Edge select bit 3" "3 setting,Any edge" bitfld.long 0x10 2. " [2] ,Edge select bit 2" "2 setting,Any edge" bitfld.long 0x10 1. " [1] ,Edge select bit 1" "1 setting,Any edge" bitfld.long 0x10 0. " [0] ,Edge select bit 0" "0 setting,Any edge" wgroup.long 0x84++0x0B line.long 0x00 "DR_SET,GPIO Data Register SET Register" bitfld.long 0x00 31. " DR_SET[31] ,Data bit 31 set" "Not set,Set" bitfld.long 0x00 30. " [30] ,Data bit 30 set" "Not set,Set" bitfld.long 0x00 29. " [29] ,Data bit 29 set" "Not set,Set" bitfld.long 0x00 28. " [28] ,Data bit 28 set" "Not set,Set" newline bitfld.long 0x00 27. " [27] ,Data bit 27 set" "Not set,Set" bitfld.long 0x00 26. " [26] ,Data bit 26 set" "Not set,Set" bitfld.long 0x00 25. " [25] ,Data bit 25 set" "Not set,Set" bitfld.long 0x00 24. " [24] ,Data bit 24 set" "Not set,Set" newline bitfld.long 0x00 23. " [23] ,Data bit 23 set" "Not set,Set" bitfld.long 0x00 22. " [22] ,Data bit 22 set" "Not set,Set" bitfld.long 0x00 21. " [21] ,Data bit 21 set" "Not set,Set" bitfld.long 0x00 20. " [20] ,Data bit 20 set" "Not set,Set" newline bitfld.long 0x00 19. " [19] ,Data bit 19 set" "Not set,Set" bitfld.long 0x00 18. " [18] ,Data bit 18 set" "Not set,Set" bitfld.long 0x00 17. " [17] ,Data bit 17 set" "Not set,Set" bitfld.long 0x00 16. " [16] ,Data bit 16 set" "Not set,Set" newline bitfld.long 0x00 15. " [15] ,Data bit 15 set" "Not set,Set" bitfld.long 0x00 14. " [14] ,Data bit 14 set" "Not set,Set" bitfld.long 0x00 13. " [13] ,Data bit 13 set" "Not set,Set" bitfld.long 0x00 12. " [12] ,Data bit 12 set" "Not set,Set" newline bitfld.long 0x00 11. " [11] ,Data bit 11 set" "Not set,Set" bitfld.long 0x00 10. " [10] ,Data bit 10 set" "Not set,Set" bitfld.long 0x00 9. " [9] ,Data bit 9 set" "Not set,Set" bitfld.long 0x00 8. " [8] ,Data bit 8 set" "Not set,Set" newline bitfld.long 0x00 7. " [7] ,Data bit 7 set" "Not set,Set" bitfld.long 0x00 6. " [6] ,Data bit 6 set" "Not set,Set" bitfld.long 0x00 5. " [5] ,Data bit 5 set" "Not set,Set" bitfld.long 0x00 4. " [4] ,Data bit 4 set" "Not set,Set" newline bitfld.long 0x00 3. " [3] ,Data bit 3 set" "Not set,Set" bitfld.long 0x00 2. " [2] ,Data bit 2 set" "Not set,Set" bitfld.long 0x00 1. " [1] ,Data bit 1 set" "Not set,Set" bitfld.long 0x00 0. " [0] ,Data bit 0 set" "Not set,Set" line.long 0x04 "DR_CLEAR,GPIO Data Register CLEAR Register" bitfld.long 0x04 31. " DR_CLEAR[31] ,Data bit 31 clear" "No effect,Clear" bitfld.long 0x04 30. " [30] ,Data bit 30 clear" "No effect,Clear" bitfld.long 0x04 29. " [29] ,Data bit 29 clear" "No effect,Clear" bitfld.long 0x04 28. " [28] ,Data bit 28 clear" "No effect,Clear" newline bitfld.long 0x04 27. " [27] ,Data bit 27 clear" "No effect,Clear" bitfld.long 0x04 26. " [26] ,Data bit 26 clear" "No effect,Clear" bitfld.long 0x04 25. " [25] ,Data bit 25 clear" "No effect,Clear" bitfld.long 0x04 24. " [24] ,Data bit 24 clear" "No effect,Clear" newline bitfld.long 0x04 23. " [23] ,Data bit 23 clear" "No effect,Clear" bitfld.long 0x04 22. " [22] ,Data bit 22 clear" "No effect,Clear" bitfld.long 0x04 21. " [21] ,Data bit 21 clear" "No effect,Clear" bitfld.long 0x04 20. " [20] ,Data bit 20 clear" "No effect,Clear" newline bitfld.long 0x04 19. " [19] ,Data bit 19 clear" "No effect,Clear" bitfld.long 0x04 18. " [18] ,Data bit 18 clear" "No effect,Clear" bitfld.long 0x04 17. " [17] ,Data bit 17 clear" "No effect,Clear" bitfld.long 0x04 16. " [16] ,Data bit 16 clear" "No effect,Clear" newline bitfld.long 0x04 15. " [15] ,Data bit 15 clear" "No effect,Clear" bitfld.long 0x04 14. " [14] ,Data bit 14 clear" "No effect,Clear" bitfld.long 0x04 13. " [13] ,Data bit 13 clear" "No effect,Clear" bitfld.long 0x04 12. " [12] ,Data bit 12 clear" "No effect,Clear" newline bitfld.long 0x04 11. " [11] ,Data bit 11 clear" "No effect,Clear" bitfld.long 0x04 10. " [10] ,Data bit 10 clear" "No effect,Clear" bitfld.long 0x04 9. " [9] ,Data bit 9 clear" "No effect,Clear" bitfld.long 0x04 8. " [8] ,Data bit 8 clear" "No effect,Clear" newline bitfld.long 0x04 7. " [7] ,Data bit 7 clear" "No effect,Clear" bitfld.long 0x04 6. " [6] ,Data bit 6 clear" "No effect,Clear" bitfld.long 0x04 5. " [5] ,Data bit 5 clear" "No effect,Clear" bitfld.long 0x04 4. " [4] ,Data bit 4 clear" "No effect,Clear" newline bitfld.long 0x04 3. " [3] ,Data bit 3 clear" "No effect,Clear" bitfld.long 0x04 2. " [2] ,Data bit 2 clear" "No effect,Clear" bitfld.long 0x04 1. " [1] ,Data bit 1 clear" "No effect,Clear" bitfld.long 0x04 0. " [0] ,Data bit 0 clear" "No effect,Clear" line.long 0x08 "DR_TOGGLE,GPIO Data Register TOGGLE Register" bitfld.long 0x08 31. " DR_TOGGLE[31] ,Data bit 31 toggle" "Not toggled,Toggled" bitfld.long 0x08 30. " [30] ,Data bit 30 toggle" "No effect,Clear" bitfld.long 0x08 29. " [29] ,Data bit 29 toggle" "Not toggled,Toggled" bitfld.long 0x08 28. " [28] ,Data bit 28 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 27. " [27] ,Data bit 27 toggle" "Not toggled,Toggled" bitfld.long 0x08 26. " [26] ,Data bit 26 toggle" "Not toggled,Toggled" bitfld.long 0x08 25. " [25] ,Data bit 25 toggle" "Not toggled,Toggled" bitfld.long 0x08 24. " [24] ,Data bit 24 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 23. " [23] ,Data bit 23 toggle" "Not toggled,Toggled" bitfld.long 0x08 22. " [22] ,Data bit 22 toggle" "Not toggled,Toggled" bitfld.long 0x08 21. " [21] ,Data bit 21 toggle" "Not toggled,Toggled" bitfld.long 0x08 20. " [20] ,Data bit 20 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 19. " [19] ,Data bit 19 toggle" "Not toggled,Toggled" bitfld.long 0x08 18. " [18] ,Data bit 18 toggle" "Not toggled,Toggled" bitfld.long 0x08 17. " [17] ,Data bit 17 toggle" "Not toggled,Toggled" bitfld.long 0x08 16. " [16] ,Data bit 16 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 15. " [15] ,Data bit 15 toggle" "Not toggled,Toggled" bitfld.long 0x08 14. " [14] ,Data bit 14 toggle" "Not toggled,Toggled" bitfld.long 0x08 13. " [13] ,Data bit 13 toggle" "Not toggled,Toggled" bitfld.long 0x08 12. " [12] ,Data bit 12 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 11. " [11] ,Data bit 11 toggle" "Not toggled,Toggled" bitfld.long 0x08 10. " [10] ,Data bit 10 toggle" "Not toggled,Toggled" bitfld.long 0x08 9. " [9] ,Data bit 9 toggle" "Not toggled,Toggled" bitfld.long 0x08 8. " [8] ,Data bit 8 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 7. " [7] ,Data bit 7 toggle" "Not toggled,Toggled" bitfld.long 0x08 6. " [6] ,Data bit 6 toggle" "Not toggled,Toggled" bitfld.long 0x08 5. " [5] ,Data bit 5 toggle" "Not toggled,Toggled" bitfld.long 0x08 4. " [4] ,Data bit 4 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 3. " [3] ,Data bit 3 toggle" "Not toggled,Toggled" bitfld.long 0x08 2. " [2] ,Data bit 2 toggle" "Not toggled,Toggled" bitfld.long 0x08 1. " [1] ,Data bit 1 toggle" "Not toggled,Toggled" bitfld.long 0x08 0. " [0] ,Data bit 0 toggle" "Not toggled,Toggled" width 0x0B tree.end tree "CSR (MIPI CSI Control and Status Registers)" base ad:0x58221000 width 32. group.long 0x00++0x07 line.long 0x00 "PLM_CTRL,Pixel Link Master Control Register" bitfld.long 0x00 12. " POLARITY ,HSYNC and VSYNC signals polarity" "Active low,Active high" bitfld.long 0x00 11. " VALID_OVERRIDE ,Drive valid on the pixel link" "Not driven,Driven" newline bitfld.long 0x00 10. " HSYNC_OVERIDE ,Force pixel link master HSYNC input to be active" "Not forced,Forced" bitfld.long 0x00 9. " VSYNC_OVERIDE ,Force pixel link master VSYNC input to be active" "Not forced,Forced" newline bitfld.long 0x00 1.--2. " ADDR ,Destination module select" "0,1,2,3" bitfld.long 0x00 0. " ENABLE ,Pixel link enable" "Disabled,Enabled" line.long 0x04 "PHY_CTRL,Physical Layer Control Register" bitfld.long 0x04 22. " PD ,Description missing" "0,1" bitfld.long 0x04 21. " RTERM_SEL ,Description missing" "0,1" newline bitfld.long 0x04 4.--9. " S_PRG_RXHS_SETTLE ,Description missing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 3. " CONT_CLK_MODE ,Description missing" "0,1" newline bitfld.long 0x04 2. " DDRCLK_EN ,DDRCLK enable" "Disabled,Enabled" bitfld.long 0x04 1. " AUTO_PD_EN ,AUTO_PD enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " RX_ENABLE ,RX enabled" "Disabled,Enabled" rgroup.long 0x08++0x03 line.long 0x00 "PHY_STATUS,Physical Layer Status Register" bitfld.long 0x00 0. " LANES_STOPPED ,Lanes stopped" "0,1" group.long 0x30++0x03 line.long 0x00 "VC_INTERLACED,Virtual Channel Interlace Register" bitfld.long 0x00 3. " VC3 ,Virtual channel 3 interlace" "Default,Interlaced" bitfld.long 0x00 2. " VC2 ,Virtual channel 2 interlace" "Default,Interlaced" newline bitfld.long 0x00 1. " VC1 ,Virtual channel 1 interlace" "Default,Interlaced" bitfld.long 0x00 0. " VC0 ,Virtual channel 0 interlace" "Default,Interlaced" group.long 0x38++0x03 line.long 0x00 "DATA_TYPE_DISABLE_BF,Data Type Disable Register" bitfld.long 0x00 21. " DATA_TYPE_DISABLE_RAW14 ,RAW14 data type disable" "No,Yes" bitfld.long 0x00 20. " DATA_TYPE_DISABLE_RAW12 ,RAW12 data type disable" "No,Yes" newline bitfld.long 0x00 19. " DATA_TYPE_DISABLE_RAW10 ,RAW10 data type disable" "No,Yes" bitfld.long 0x00 18. " DATA_TYPE_DISABLE_RAW8 ,RAW8 data type disable" "No,Yes" newline bitfld.long 0x00 16. " DATA_TYPE_DISABLE_RAW6 ,RAW6 data type disable" "No,Yes" bitfld.long 0x00 12. " DATA_TYPE_DISABLE_RGB888 ,RGB888 data type disable" "No,Yes" newline bitfld.long 0x00 11. " DATA_TYPE_DISABLE_RGB666 ,RGB666 data type disable" "No,Yes" bitfld.long 0x00 10. " DATA_TYPE_DISABLE_RGB565 ,RGB565 data type disable" "No,Yes" newline bitfld.long 0x00 9. " DATA_TYPE_DISABLE_RGB555 ,RGB555 data type disable" "No,Yes" bitfld.long 0x00 8. " DATA_TYPE_DISABLE_RGB444 ,RGB444 data type disable" "No,Yes" newline bitfld.long 0x00 7. " DATA_TYPE_DISABLE_YUV422_10BIT ,YUV422_10BIT data type disable" "No,Yes" bitfld.long 0x00 6. " DATA_TYPE_DISABLE_YUV422_8BIT ,YUV422_8BIT data type disable" "No,Yes" newline bitfld.long 0x00 2. " DATA_TYPE_DISABLE_L_YUV420_8BIT ,Legacy YUV422_8BIT data type disable" "No,Yes" group.long 0x40++0x0B line.long 0x00 "YUV420_FIRST_LINE_DATA_TYPE,YUV420 First Line Data Type Register" bitfld.long 0x00 0. " YUV420_FIRST_LINE_DATA_TYPE ,YUV420 first line data type" "Odd,Even" line.long 0x04 "CONTROLLER_CLOCK_RESET_CONTROL,Controller Clock Reset Control Register" bitfld.long 0x04 0.--1. " CONTROLLER_CLOCK_RESET_CONTROL ,Controller clock reset control" "SW_RESETN,CTL_CLK_OFF,?..." line.long 0x08 "STREAM_FENCING_CONTROL,Stream Fencing Control Register" bitfld.long 0x08 0.--3. " STREAM_FENCING_CONTROL ,Stream fencing control" "Fence VC0,Fence VC1,Fence VC2,Fence VC3,?..." rgroup.long 0x4C++0x03 line.long 0x00 "STREAM_FENCING_STATUS,Stream Fencing Status Register" bitfld.long 0x00 0.--3. " STREAM_FENCING_STATUS ,Stream fencing status" "VC0 fenced,VC1 fenced,VC2 fenced,VC3 fenced,?..." width 0x0B tree.end tree.open "Local Interrupt Steer" tree "Channel 0" base ad:0x58220000 width 10. group.long 0x00++0x03 line.long 0x00 "CHAN0CTL,Channel 0 Control Register" bitfld.long 0x00 4. " CH4 ,Channel 4 control" "Disabled,Enabled" bitfld.long 0x00 3. " CH3 ,Channel 3 control" "Disabled,Enabled" bitfld.long 0x00 2. " CH2 ,Channel 2 control" "Disabled,Enabled" bitfld.long 0x00 1. " CH1 ,Channel 1 control" "Disabled,Enabled" newline bitfld.long 0x00 0. " CH0 ,Channel 0 control" "Disabled,Enabled" group.long 0x08++0x3B line.long 0x00 "MASK1,Interrupt Mask 1 Register" bitfld.long 0x00 22. " MASKFLD[22] ,Mask for VPU_INT_6" "Masked,Unmasked" bitfld.long 0x00 21. " [21] ,Mask for VPU_INT_5" "Masked,Unmasked" bitfld.long 0x00 20. " [20] ,Mask for VPU_INT_4" "Masked,Unmasked" bitfld.long 0x00 19. " [19] ,Mask for VPU_INT_3" "Masked,Unmasked" newline bitfld.long 0x00 18. " [18] ,Mask for VPU_INT_2" "Masked,Unmasked" bitfld.long 0x00 17. " [17] ,Mask for VPU_INT_1" "Masked,Unmasked" bitfld.long 0x00 16. " [16] ,Mask for VPU_INT_0" "Masked,Unmasked" bitfld.long 0x00 11. " [11] ,Mask for SPDIF0_TX_DMA_INT" "Masked,Unmasked" newline bitfld.long 0x00 10. " [10] ,Mask for SPDIF0_TX_MOD_INT" "Masked,Unmasked" bitfld.long 0x00 9. " [9] ,Mask for SPDIF0_RX_DMA_INT" "Masked,Unmasked" bitfld.long 0x00 8. " [8] ,Mask for SPDIF0_RX_MOD_INT" "Masked,Unmasked" bitfld.long 0x00 7. " [7] ,Mask for CAAM_RTIC_INT" "Masked,Unmasked" newline bitfld.long 0x00 6. " [6] ,Mask for CAAM_INT3" "Masked,Unmasked" bitfld.long 0x00 5. " [5] ,Mask for CAAM_INT2" "Masked,Unmasked" bitfld.long 0x00 4. " [4] ,Mask for CAAM_INT1" "Masked,Unmasked" bitfld.long 0x00 3. " [3] ,Mask for CAAM_INT0" "Masked,Unmasked" newline bitfld.long 0x00 2. " [2] ,Mask for SEC_MU3_A_INT" "Masked,Unmasked" bitfld.long 0x00 1. " [1] ,Mask for SEC_MU2_A_INT" "Masked,Unmasked" bitfld.long 0x00 0. " [0] ,Mask for SEC_MU1_A_INT" "Masked,Unmasked" line.long 0x04 "MASK2,Interrupt Mask 2 Register" bitfld.long 0x04 25. " MASKFLD[25] ,Mask for UART3_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 24. " [24] ,Mask for UART3_DMA_RX_INT" "Masked,Unmasked" bitfld.long 0x04 23. " [23] ,Mask for UART2_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 22. " [22] ,Mask for UART2_DMA_RX_INT" "Masked,Unmasked" newline bitfld.long 0x04 21. " [21] ,Mask for UART1_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 20. " [20] ,Mask for UART1_DMA_RX_INT" "Masked,Unmasked" bitfld.long 0x04 19. " [19] ,Mask for UART0_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 18. " [18] ,Mask for UART0_DMA_RX_INT" "Masked,Unmasked" newline bitfld.long 0x04 15. " [15] ,Mask for I2C3_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 14. " [14] ,Mask for I2C3_DMA_RX_INT" "Masked,Unmasked" bitfld.long 0x04 13. " [13] ,Mask for I2C2_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 12. " [12] ,Mask for I2C2_DMA_RX_INT" "Masked,Unmasked" newline bitfld.long 0x04 11. " [11] ,Mask for I2C1_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 10. " [10] ,Mask for I2C1_DMA_RX_INT" "Masked,Unmasked" bitfld.long 0x04 9. " [9] ,Mask for I2C0_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 8. " [8] ,Mask for I2C0_DMA_RX_INT" "Masked,Unmasked" newline bitfld.long 0x04 7. " [7] ,Mask for SPI3_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 6. " [6] ,Mask for SPI3_DMA_RX_INT" "Masked,Unmasked" bitfld.long 0x04 5. " [5] ,Mask for SPI2_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 4. " [4] ,Mask for SPI2_DMA_RX_INT" "Masked,Unmasked" newline bitfld.long 0x04 3. " [3] ,Mask for SPI1_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 2. " [2] ,Mask for SPI1_DMA_RX_INT" "Masked,Unmasked" bitfld.long 0x04 1. " [1] ,Mask for SPI0_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 0. " [0] ,Mask for SPI0_DMA_RX_INT" "Masked,Unmasked" line.long 0x08 "MASK3,Interrupt Mask 3 Register" bitfld.long 0x08 26. " MASKFLD[26] ,Mask for ESAI0_DMA_INT" "Masked,Unmasked" bitfld.long 0x08 25. " [25] ,Mask for ESAI0_MOD_INT" "Masked,Unmasked" bitfld.long 0x08 22. " [22] ,Mask for SPDIF0_TX_INT" "Masked,Unmasked" bitfld.long 0x08 21. " [21] ,Mask for SPDIF0_RX_INT" "Masked,Unmasked" newline bitfld.long 0x08 20. " [20] ,Mask for SAI5_INT" "Masked,Unmasked" bitfld.long 0x08 19. " [19] ,Mask for SAI4_INT" "Masked,Unmasked" bitfld.long 0x08 16. " [16] ,Mask for SAI3_INT" "Masked,Unmasked" bitfld.long 0x08 15. " [15] ,Mask for SAI2_INT" "Masked,Unmasked" newline bitfld.long 0x08 14. " [14] ,Mask for SAI1_INT" "Masked,Unmasked" bitfld.long 0x08 13. " [13] ,Mask for SAI0_INT" "Masked,Unmasked" bitfld.long 0x08 12. " [12] ,Mask for GPT5_INT" "Masked,Unmasked" bitfld.long 0x08 11. " [11] ,Mask for GPT4_INT" "Masked,Unmasked" newline bitfld.long 0x08 10. " [10] ,Mask for GPT3_INT" "Masked,Unmasked" bitfld.long 0x08 9. " [9] ,Mask for GPT2_INT" "Masked,Unmasked" bitfld.long 0x08 8. " [8] ,Mask for GPT1_INT" "Masked,Unmasked" bitfld.long 0x08 7. " [7] ,Mask for GPT0_INT" "Masked,Unmasked" newline bitfld.long 0x08 4. " [4] ,Mask for ESAI0_INT" "Masked,Unmasked" bitfld.long 0x08 3. " [3] ,Mask for DMA1_CH5_INT" "Masked,Unmasked" bitfld.long 0x08 2. " [2] ,Mask for DMA1_CH4_INT" "Masked,Unmasked" bitfld.long 0x08 1. " [1] ,Mask for DMA1_CH3_INT" "Masked,Unmasked" newline bitfld.long 0x08 0. " [0] ,Mask for DMA1_CH2_INT" "Masked,Unmasked" line.long 0x0C "MASK4,Interrupt Mask 4 Register" bitfld.long 0x0C 31. " MASKFLD[31] ,Mask for DMA1_CH1_INT" "Masked,Unmasked" bitfld.long 0x0C 30. " [30] ,Mask for DMA1_CH0_INT" "Masked,Unmasked" bitfld.long 0x0C 29. " [29] ,Mask for ASRC1_INT2" "Masked,Unmasked" bitfld.long 0x0C 28. " [28] ,Mask for ASRC1_INT1" "Masked,Unmasked" newline bitfld.long 0x0C 27. " [27] ,Mask for DMA0_CH5_INT" "Masked,Unmasked" bitfld.long 0x0C 26. " [26] ,Mask for DMA0_CH4_INT" "Masked,Unmasked" bitfld.long 0x0C 25. " [25] ,Mask for DMA0_CH3_INT" "Masked,Unmasked" bitfld.long 0x0C 24. " [24] ,Mask for DMA0_CH2_INT" "Masked,Unmasked" newline bitfld.long 0x0C 23. " [23] ,Mask for DMA0_CH1_INT" "Masked,Unmasked" bitfld.long 0x0C 22. " [22] ,Mask for DMA0_CH0_INT" "Masked,Unmasked" bitfld.long 0x0C 21. " [21] ,Mask for ASRC0_INT2" "Masked,Unmasked" bitfld.long 0x0C 20. " [20] ,Mask for ASRC0_INT1" "Masked,Unmasked" newline bitfld.long 0x0C 19. " [19] ,Mask for DMA1_ERR_INT" "Masked,Unmasked" bitfld.long 0x0C 18. " [18] ,Mask for DMA1_INT" "Masked,Unmasked" bitfld.long 0x0C 17. " [17] ,Mask for DMA0_ERR_INT" "Masked,Unmasked" bitfld.long 0x0C 16. " [16] ,Mask for DMA0_INT" "Masked,Unmasked" newline bitfld.long 0x0C 12. " [12] ,Mask for ADC_DMA_INT" "Masked,Unmasked" bitfld.long 0x0C 11. " [11] ,Mask for FTM1_DMA_INT" "Masked,Unmasked" bitfld.long 0x0C 10. " [10] ,Mask for FTM_DMA_INT" "Masked,Unmasked" bitfld.long 0x0C 9. " [9] ,Mask for FLEXCAN2_DMA_INT" "Masked,Unmasked" newline bitfld.long 0x0C 8. " [8] ,Mask for FLEXCAN1_DMA_INT" "Masked,Unmasked" bitfld.long 0x0C 7. " [7] ,Mask for FLEXCAN0_DMA_INT" "Masked,Unmasked" bitfld.long 0x0C 5. " [5] ,Mask for ADC_MOD_INT" "Masked,Unmasked" bitfld.long 0x0C 4. " [4] ,Mask for FTM1_MOD_INT" "Masked,Unmasked" newline bitfld.long 0x0C 3. " [3] ,Mask for FTM_MOD_INT" "Masked,Unmasked" bitfld.long 0x0C 2. " [2] ,Mask for FLEXCAN2_MOD_INT" "Masked,Unmasked" bitfld.long 0x0C 1. " [1] ,Mask for FLEXCAN1_MOD_INT" "Masked,Unmasked" bitfld.long 0x0C 0. " [0] ,Mask for FLEXCAN0_MOD_INT" "Masked,Unmasked" line.long 0x10 "MASK5,Interrupt Mask 5 Register" bitfld.long 0x10 28. " MASKFLD[28] ,Mask for UART3_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 27. " [27] ,Mask for UART2_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 26. " [26] ,Mask for UART1_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 25. " [25] ,Mask for UART0_MOD_INT" "Masked,Unmasked" newline bitfld.long 0x10 23. " [23] ,Mask for I2C3_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 22. " [22] ,Mask for I2C2_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 21. " [21] ,Mask for I2C1_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 20. " [20] ,Mask for I2C0_MOD_INT" "Masked,Unmasked" newline bitfld.long 0x10 19. " [19] ,Mask for SPI3_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 18. " [18] ,Mask for SPI2_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 17. " [17] ,Mask for SPI1_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 16. " [16] ,Mask for SPI0_MOD_INT" "Masked,Unmasked" newline bitfld.long 0x10 12. " [12] ,Mask for SAI5_DMA_INT" "Masked,Unmasked" bitfld.long 0x10 11. " [11] ,Mask for SAI5_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 10. " [10] ,Mask for SAI4_DMA_INT" "Masked,Unmasked" bitfld.long 0x10 9. " [9] ,Mask for SAI4_MOD_INT" "Masked,Unmasked" newline bitfld.long 0x10 4. " [4] ,Mask for SAI3_DMA_INT" "Masked,Unmasked" bitfld.long 0x10 3. " [3] ,Mask for SAI3_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 0. " [0] ,Mask for INT_OUT" "Masked,Unmasked" line.long 0x14 "MASK6,Interrupt Mask 6 Register" bitfld.long 0x14 31. " MASKFLD[31] ,Mask for SAI2_DMA_INT" "Masked,Unmasked" bitfld.long 0x14 30. " [30] ,Mask for SAI2_MOD_INT" "Masked,Unmasked" bitfld.long 0x14 29. " [29] ,Mask for SAI1_DMA_INT" "Masked,Unmasked" bitfld.long 0x14 28. " [28] ,Mask for SAI1_MOD_INT" "Masked,Unmasked" newline bitfld.long 0x14 27. " [27] ,Mask for SAI0_DMA_INT" "Masked,Unmasked" bitfld.long 0x14 26. " [26] ,Mask for SAI0_MOD_INT" "Masked,Unmasked" bitfld.long 0x14 24. " [24] ,Mask for MJPEG_DEC3_INT" "Masked,Unmasked" bitfld.long 0x14 23. " [23] ,Mask for MJPEG_DEC2_INT" "Masked,Unmasked" newline bitfld.long 0x14 22. " [22] ,Mask for MJPEG_DEC1_INT" "Masked,Unmasked" bitfld.long 0x14 21. " [21] ,Mask for MJPEG_DEC0_INT" "Masked,Unmasked" bitfld.long 0x14 20. " [20] ,Mask for MJPEG_ENC3_INT" "Masked,Unmasked" bitfld.long 0x14 19. " [19] ,Mask for MJPEG_ENC2_INT" "Masked,Unmasked" newline bitfld.long 0x14 18. " [18] ,Mask for MJPEG_ENC1_INT" "Masked,Unmasked" bitfld.long 0x14 17. " [17] ,Mask for MJPEG_ENC0_INT" "Masked,Unmasked" bitfld.long 0x14 16. " [16] ,Mask for PDMA_STREAM7_INT" "Masked,Unmasked" bitfld.long 0x14 15. " [15] ,Mask for PDMA_STREAM6_INT" "Masked,Unmasked" newline bitfld.long 0x14 14. " [14] ,Mask for PDMA_STREAM5_INT" "Masked,Unmasked" bitfld.long 0x14 13. " [13] ,Mask for PDMA_STREAM4_INT" "Masked,Unmasked" bitfld.long 0x14 12. " [12] ,Mask for PDMA_STREAM3_INT" "Masked,Unmasked" bitfld.long 0x14 11. " [11] ,Mask for PDMA_STREAM2_INT" "Masked,Unmasked" newline bitfld.long 0x14 10. " [10] ,Mask for PDMA_STREAM1_INT" "Masked,Unmasked" bitfld.long 0x14 9. " [9] ,Mask for PDMA_STREAM0_INT" "Masked,Unmasked" bitfld.long 0x14 0. " [0] ,Mask for MSI_INT" "Masked,Unmasked" line.long 0x18 "MASK7,Interrupt Mask 7 Register" bitfld.long 0x18 20. " MASKFLD[20] ,Mask for DMA_ERR_INT" "Masked,Unmasked" bitfld.long 0x18 19. " [19] ,Mask for DMA_INT" "Masked,Unmasked" bitfld.long 0x18 18. " [18] ,Mask for APBHDMA" "Masked,Unmasked" bitfld.long 0x18 17. " [17] ,Mask for NAND_GPMI_INT" "Masked,Unmasked" newline bitfld.long 0x18 16. " [16] ,Mask for NAND_BCH_INT" "Masked,Unmasked" bitfld.long 0x18 15. " [15] ,Mask for USB3_INT" "Masked,Unmasked" bitfld.long 0x18 14. " [14] ,Mask for WAKEUP_INT" "Masked,Unmasked" bitfld.long 0x18 13. " [13] ,Mask for UTMI_INT" "Masked,Unmasked" newline bitfld.long 0x18 12. " [12] ,Mask for USB_HOST_INT" "Masked,Unmasked" bitfld.long 0x18 11. " [11] ,Mask for USB_OTG_INT" "Masked,Unmasked" bitfld.long 0x18 10. " [10] ,Mask for MLB_AHB_INT" "Masked,Unmasked" bitfld.long 0x18 9. " [9] ,Mask for MLB_INT" "Masked,Unmasked" newline bitfld.long 0x18 7. " [7] ,Mask for ENET1_TIMER_INT" "Masked,Unmasked" bitfld.long 0x18 6. " [6] ,Mask for ENET1_FRAME0_EVENT_INT" "Masked,Unmasked" bitfld.long 0x18 5. " [5] ,Mask for ENET1_FRAME2_INT" "Masked,Unmasked" bitfld.long 0x18 4. " [4] ,Mask for ENET1_FRAME1_INT" "Masked,Unmasked" newline bitfld.long 0x18 3. " [3] ,Mask for ENET0_TIMER_INT" "Masked,Unmasked" bitfld.long 0x18 2. " [2] ,Mask for ENET0_FRAME0_EVENT_INT" "Masked,Unmasked" bitfld.long 0x18 1. " [1] ,Mask for ENET0_FRAME2_INT" "Masked,Unmasked" bitfld.long 0x18 0. " [0] ,Mask for ENET0_FRAME1_INT" "Masked,Unmasked" line.long 0x1C "MASK8,Interrupt Mask 8 Register" bitfld.long 0x1C 23. " MASKFLD[23] ,Mask for EXTERNAL_DMA_INT_5" "Masked,Unmasked" bitfld.long 0x1C 22. " [22] ,Mask for EXTERNAL_DMA_INT_4" "Masked,Unmasked" bitfld.long 0x1C 21. " [21] ,Mask for EXTERNAL_DMA_INT_3" "Masked,Unmasked" bitfld.long 0x1C 20. " [20] ,Mask for EXTERNAL_DMA_INT_2" "Masked,Unmasked" newline bitfld.long 0x1C 19. " [19] ,Mask for EXTERNAL_DMA_INT_1" "Masked,Unmasked" bitfld.long 0x1C 18. " [18] ,Mask for EXTERNAL_DMA_INT_0" "Masked,Unmasked" bitfld.long 0x1C 16. " [16] ,Mask for ADC_INT" "Masked,Unmasked" bitfld.long 0x1C 15. " [15] ,Mask for FTM1_INT" "Masked,Unmasked" newline bitfld.long 0x1C 14. " [14] ,Mask for FTM_INT" "Masked,Unmasked" bitfld.long 0x1C 13. " [13] ,Mask for FLEXCAN2_INT" "Masked,Unmasked" bitfld.long 0x1C 12. " [12] ,Mask for FLEXCAN1_INT" "Masked,Unmasked" bitfld.long 0x1C 11. " [11] ,Mask for FLEXCAN0_INT" "Masked,Unmasked" newline bitfld.long 0x1C 10. " [10] ,Mask for USDHC2_INT" "Masked,Unmasked" bitfld.long 0x1C 9. " [9] ,Mask for USDHC1_INT" "Masked,Unmasked" bitfld.long 0x1C 8. " [8] ,Mask for EMMC0_INT/USDHC0_INT" "Masked,Unmasked" bitfld.long 0x1C 4. " [4] ,Mask for UART3_INT" "Masked,Unmasked" newline bitfld.long 0x1C 3. " [3] ,Mask for UART2_INT" "Masked,Unmasked" bitfld.long 0x1C 2. " [2] ,Mask for UART1_INT" "Masked,Unmasked" bitfld.long 0x1C 1. " [1] ,Mask for UART0_INT" "Masked,Unmasked" line.long 0x20 "MASK9,Interrupt Mask 9 Register" bitfld.long 0x20 31. " MASKFLD[31] ,Mask for I2C3_INT" "Masked,Unmasked" bitfld.long 0x20 30. " [30] ,Mask for I2C2_INT" "Masked,Unmasked" bitfld.long 0x20 29. " [29] ,Mask for I2C1_INT" "Masked,Unmasked" bitfld.long 0x20 28. " [28] ,Mask for I2C0_INT" "Masked,Unmasked" newline bitfld.long 0x20 27. " [27] ,Mask for SPI3_INT" "Masked,Unmasked" bitfld.long 0x20 26. " [26] ,Mask for SPI2_INT" "Masked,Unmasked" bitfld.long 0x20 25. " [25] ,Mask for SPI1_INT" "Masked,Unmasked" bitfld.long 0x20 24. " [24] ,Mask for SPI0_INT" "Masked,Unmasked" newline bitfld.long 0x20 16. " [16] ,Mask for MU13_INT_B" "Masked,Unmasked" bitfld.long 0x20 15. " [15] ,Mask for MU12_INT_B" "Masked,Unmasked" bitfld.long 0x20 14. " [14] ,Mask for MU11_INT_B" "Masked,Unmasked" bitfld.long 0x20 13. " [13] ,Mask for MU10_INT_B" "Masked,Unmasked" newline bitfld.long 0x20 12. " [12] ,Mask for MU9_INT_B" "Masked,Unmasked" bitfld.long 0x20 11. " [11] ,Mask for MU8_INT_B" "Masked,Unmasked" bitfld.long 0x20 10. " [10] ,Mask for MU7_INT_B" "Masked,Unmasked" bitfld.long 0x20 9. " [9] ,Mask for MU6_INT_B" "Masked,Unmasked" newline bitfld.long 0x20 8. " [8] ,Mask for MU5_INT_B" "Masked,Unmasked" bitfld.long 0x20 0. " [0] ,Mask for MU13_INT_A" "Masked,Unmasked" line.long 0x24 "MASK10,Interrupt Mask 10 Register" bitfld.long 0x24 31. " MASKFLD[31] ,Mask for MU12_INT_A" "Masked,Unmasked" bitfld.long 0x24 30. " [30] ,Mask for MU11_INT_A" "Masked,Unmasked" bitfld.long 0x24 29. " [29] ,Mask for MU10_INT_A" "Masked,Unmasked" bitfld.long 0x24 28. " [28] ,Mask for MU9_INT_A" "Masked,Unmasked" newline bitfld.long 0x24 27. " [27] ,Mask for MU8_INT_A" "Masked,Unmasked" bitfld.long 0x24 26. " [26] ,Mask for MU7_INT_A" "Masked,Unmasked" bitfld.long 0x24 25. " [25] ,Mask for MU6_INT_A" "Masked,Unmasked" bitfld.long 0x24 24. " [24] ,Mask for MU5_INT_A" "Masked,Unmasked" newline bitfld.long 0x24 20. " [20] ,Mask for MU4_INT" "Masked,Unmasked" bitfld.long 0x24 19. " [19] ,Mask for MU3_INT" "Masked,Unmasked" bitfld.long 0x24 18. " [18] ,Mask for MU2_INT" "Masked,Unmasked" bitfld.long 0x24 17. " [17] ,Mask for MU1_INT" "Masked,Unmasked" newline bitfld.long 0x24 16. " [16] ,Mask for MU0_INT" "Masked,Unmasked" line.long 0x28 "MASK11,Interrupt Mask 11 Register" bitfld.long 0x28 15. " MASKFLD[15] ,Mask for GPIO_INT[7]" "Masked,Unmasked" bitfld.long 0x28 14. " [14] ,Mask for GPIO_INT[6]" "Masked,Unmasked" bitfld.long 0x28 13. " [13] ,Mask for GPIO_INT[5]" "Masked,Unmasked" bitfld.long 0x28 12. " [12] ,Mask for GPIO_INT[4]" "Masked,Unmasked" newline bitfld.long 0x28 11. " [11] ,Mask for GPIO_INT[3]" "Masked,Unmasked" bitfld.long 0x28 10. " [10] ,Mask for GPIO_INT[2]" "Masked,Unmasked" bitfld.long 0x28 9. " [9] ,Mask for GPIO_INT[1]" "Masked,Unmasked" bitfld.long 0x28 8. " [8] ,Mask for GPIO_INT[0]" "Masked,Unmasked" newline bitfld.long 0x28 3. " [3] ,Mask for PERF_CNT_INT" "Masked,Unmasked" bitfld.long 0x28 2. " [2] ,Mask for SBR_DONE_INT" "Masked,Unmasked" bitfld.long 0x28 1. " [1] ,Mask for ECC_NCORRECT_INT" "Masked,Unmasked" bitfld.long 0x28 0. " [0] ,Mask for ECC_CORRECT_INT" "Masked,Unmasked" line.long 0x2C "MASK12,Interrupt Mask 12 Register" bitfld.long 0x2C 27. " MASKFLD[27] ,Mask for SYS_COUNT_INT[3]" "Masked,Unmasked" bitfld.long 0x2C 26. " [26] ,Mask for SYS_COUNT_INT[2]" "Masked,Unmasked" bitfld.long 0x2C 25. " [25] ,Mask for SYS_COUNT_INT[1]" "Masked,Unmasked" bitfld.long 0x2C 24. " [24] ,Mask for SYS_COUNT_INT[0]" "Masked,Unmasked" newline bitfld.long 0x2C 23. " [23] ,Mask for INT_OUT[7]" "Masked,Unmasked" bitfld.long 0x2C 22. " [22] ,Mask for INT_OUT[6]" "Masked,Unmasked" bitfld.long 0x2C 21. " [21] ,Mask for INT_OUT[5]" "Masked,Unmasked" bitfld.long 0x2C 20. " [20] ,Mask for INT_OUT[4]" "Masked,Unmasked" newline bitfld.long 0x2C 19. " [19] ,Mask for INT_OUT[3]" "Masked,Unmasked" bitfld.long 0x2C 18. " [18] ,Mask for INT_OUT[2]" "Masked,Unmasked" bitfld.long 0x2C 17. " [17] ,Mask for INT_OUT[1]" "Masked,Unmasked" bitfld.long 0x2C 16. " [16] ,Mask for INT_OUT[0]" "Masked,Unmasked" newline bitfld.long 0x2C 15. " [15] ,Mask for PCIE9_GPIO_WAKEUP[1]" "Masked,Unmasked" bitfld.long 0x2C 14. " [14] ,Mask for PCIE9_GPIO_WAKEUP[0]" "Masked,Unmasked" bitfld.long 0x2C 13. " [13] ,Mask for PCIE0_SMLH_REQ_RST" "Masked,Unmasked" bitfld.long 0x2C 12. " [12] ,Mask for PCIE0_INT_A" "Masked,Unmasked" newline bitfld.long 0x2C 11. " [11] ,Mask for PCIE0_INT_B" "Masked,Unmasked" bitfld.long 0x2C 10. " [10] ,Mask for PCIE0_INT_C" "Masked,Unmasked" bitfld.long 0x2C 9. " [9] ,Mask for PCIE0_INT_D" "Masked,Unmasked" bitfld.long 0x2C 8. " [8] ,Mask for PCIE0_DMA_INT" "Masked,Unmasked" newline bitfld.long 0x2C 7. " [7] ,Mask for PCIE0_CLK_REQ_INT" "Masked,Unmasked" bitfld.long 0x2C 6. " [6] ,Mask for PCIE0_MSI_CTRL_INT" "Masked,Unmasked" bitfld.long 0x2C 5. " [5] ,Mask for PWM7_INT" "Masked,Unmasked" bitfld.long 0x2C 4. " [4] ,Mask for PWM6_INT" "Masked,Unmasked" newline bitfld.long 0x2C 3. " [3] ,Mask for PWM5_INT" "Masked,Unmasked" bitfld.long 0x2C 2. " [2] ,Mask for PWM4_INT" "Masked,Unmasked" bitfld.long 0x2C 1. " [1] ,Mask for PWM3_INT" "Masked,Unmasked" bitfld.long 0x2C 0. " [0] ,Mask for PWM2_INT" "Masked,Unmasked" line.long 0x30 "MASK13,Interrupt Mask 13 Register" bitfld.long 0x30 31. " MASKFLD[31] ,Mask for PWM1_INT" "Masked,Unmasked" bitfld.long 0x30 30. " [30] ,Mask for PWM0_INT" "Masked,Unmasked" bitfld.long 0x30 29. " [29] ,Mask for FLEXSPI1_INT" "Masked,Unmasked" bitfld.long 0x30 28. " [28] ,Mask for FLEXSPI0_INT" "Masked,Unmasked" newline bitfld.long 0x30 21. " [21] ,Mask for KPP0_INT" "Masked,Unmasked" bitfld.long 0x30 20. " [20] ,Mask for GPT4_INT" "Masked,Unmasked" bitfld.long 0x30 19. " [19] ,Mask for GPT3_INT" "Masked,Unmasked" bitfld.long 0x30 18. " [18] ,Mask for GPT2_INT" "Masked,Unmasked" newline bitfld.long 0x30 17. " [17] ,Mask for GPT1_INT" "Masked,Unmasked" bitfld.long 0x30 16. " [16] ,Mask for GPT0_INT" "Masked,Unmasked" bitfld.long 0x30 5. " [5] ,Mask for DMA3_ERR_INT" "Masked,Unmasked" bitfld.long 0x30 4. " [4] ,Mask for DMA3_INT" "Masked,Unmasked" newline bitfld.long 0x30 3. " [3] ,Mask for DMA2_ERR_INT" "Masked,Unmasked" bitfld.long 0x30 2. " [2] ,Mask for DMA2_INT" "Masked,Unmasked" bitfld.long 0x30 0. " [0] ,Mask for XAQ2_INTR" "Masked,Unmasked" line.long 0x34 "MASK14,Interrupt Mask 14 Register" bitfld.long 0x34 31. " MASKFLD[31] ,Mask for LCD_PWM_INT" "Masked,Unmasked" bitfld.long 0x34 30. " [30] ,Mask for LCD_MOD_INT" "Masked,Unmasked" bitfld.long 0x34 28. " [28] ,Mask for INT_OUT" "Masked,Unmasked" bitfld.long 0x34 27. " [27] ,Mask for INT_OUT" "Masked,Unmasked" newline bitfld.long 0x34 20. " [20] ,Mask for INT_OUT[12]" "Masked,Unmasked" bitfld.long 0x34 19. " [19] ,Mask for INT_OUT[11]" "Masked,Unmasked" bitfld.long 0x34 18. " [18] ,Mask for INT_OUT[10]" "Masked,Unmasked" bitfld.long 0x34 17. " [17] ,Mask for INT_OUT[9]" "Masked,Unmasked" newline bitfld.long 0x34 15. " [15] ,Mask for INT_OUT[7]" "Masked,Unmasked" bitfld.long 0x34 14. " [14] ,Mask for INT_OUT[6]" "Masked,Unmasked" bitfld.long 0x34 13. " [13] ,Mask for INT_OUT[5]" "Masked,Unmasked" bitfld.long 0x34 12. " [12] ,Mask for INT_OUT[4]" "Masked,Unmasked" newline bitfld.long 0x34 11. " [11] ,Mask for INT_OUT[3]" "Masked,Unmasked" bitfld.long 0x34 10. " [10] ,Mask for INT_OUT[2]" "Masked,Unmasked" bitfld.long 0x34 9. " [9] ,Mask for INT_OUT[1]" "Masked,Unmasked" bitfld.long 0x34 8. " [8] ,Mask for INT_OUT[0]" "Masked,Unmasked" line.long 0x38 "MASK15,Interrupt Mask 15 Register" bitfld.long 0x38 23. " MASKFLD[23] ,Mask for INT_OUT[7]" "Masked,Unmasked" bitfld.long 0x38 22. " [22] ,Mask for INT_OUT[6]" "Masked,Unmasked" bitfld.long 0x38 21. " [21] ,Mask for INT_OUT[5]" "Masked,Unmasked" bitfld.long 0x38 20. " [20] ,Mask for INT_OUT[4]" "Masked,Unmasked" newline bitfld.long 0x38 19. " [19] ,Mask for INT_OUT[3]" "Masked,Unmasked" bitfld.long 0x38 18. " [18] ,Mask for INT_OUT[2]" "Masked,Unmasked" bitfld.long 0x38 17. " [17] ,Mask for INT_OUT[1]" "Masked,Unmasked" bitfld.long 0x38 16. " [16] ,Mask for INT_OUT[0]" "Masked,Unmasked" newline bitfld.long 0x38 1. " [1] ,Mask for nEXTERRIRQ" "Masked,Unmasked" bitfld.long 0x38 0. " [0] ,Mask for nINTERRIRQ" "Masked,Unmasked" group.long 0x48++0x3B line.long 0x00 "SET1,Interrupt Set 1 Register" bitfld.long 0x00 22. " FORCEFLD[22] ,Force VPU_INT_6" "Normal,Forced" bitfld.long 0x00 21. " [21] ,Force VPU_INT_5" "Normal,Forced" bitfld.long 0x00 20. " [20] ,Force VPU_INT_4" "Normal,Forced" bitfld.long 0x00 19. " [19] ,Force VPU_INT_3" "Normal,Forced" newline bitfld.long 0x00 18. " [18] ,Force VPU_INT_2" "Normal,Forced" bitfld.long 0x00 17. " [17] ,Force VPU_INT_1" "Normal,Forced" bitfld.long 0x00 16. " [16] ,Force VPU_INT_0" "Normal,Forced" bitfld.long 0x00 11. " [11] ,Force SPDIF0_TX_DMA_INT" "Normal,Forced" newline bitfld.long 0x00 10. " [10] ,Force SPDIF0_TX_MOD_INT" "Normal,Forced" bitfld.long 0x00 9. " [9] ,Force SPDIF0_RX_DMA_INT" "Normal,Forced" bitfld.long 0x00 8. " [8] ,Force SPDIF0_RX_MOD_INT" "Normal,Forced" bitfld.long 0x00 7. " [7] ,Force CAAM_RTIC_INT" "Normal,Forced" newline bitfld.long 0x00 6. " [6] ,Force CAAM_INT3" "Normal,Forced" bitfld.long 0x00 5. " [5] ,Force CAAM_INT2" "Normal,Forced" bitfld.long 0x00 4. " [4] ,Force CAAM_INT1" "Normal,Forced" bitfld.long 0x00 3. " [3] ,Force CAAM_INT0" "Normal,Forced" newline bitfld.long 0x00 2. " [2] ,Force SEC_MU3_A_INT" "Normal,Forced" bitfld.long 0x00 1. " [1] ,Force SEC_MU2_A_INT" "Normal,Forced" bitfld.long 0x00 0. " [0] ,Force SEC_MU1_A_INT" "Normal,Forced" line.long 0x04 "SET2,Interrupt Set 2 Register" bitfld.long 0x04 25. " FORCEFLD[25] ,Force UART3_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 24. " [24] ,Force UART3_DMA_RX_INT" "Normal,Forced" bitfld.long 0x04 23. " [23] ,Force UART2_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 22. " [22] ,Force UART2_DMA_RX_INT" "Normal,Forced" newline bitfld.long 0x04 21. " [21] ,Force UART1_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 20. " [20] ,Force UART1_DMA_RX_INT" "Normal,Forced" bitfld.long 0x04 19. " [19] ,Force UART0_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 18. " [18] ,Force UART0_DMA_RX_INT" "Normal,Forced" newline bitfld.long 0x04 15. " [15] ,Force I2C3_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 14. " [14] ,Force I2C3_DMA_RX_INT" "Normal,Forced" bitfld.long 0x04 13. " [13] ,Force I2C2_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 12. " [12] ,Force I2C2_DMA_RX_INT" "Normal,Forced" newline bitfld.long 0x04 11. " [11] ,Force I2C1_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 10. " [10] ,Force I2C1_DMA_RX_INT" "Normal,Forced" bitfld.long 0x04 9. " [9] ,Force I2C0_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 8. " [8] ,Force I2C0_DMA_RX_INT" "Normal,Forced" newline bitfld.long 0x04 7. " [7] ,Force SPI3_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 6. " [6] ,Force SPI3_DMA_RX_INT" "Normal,Forced" bitfld.long 0x04 5. " [5] ,Force SPI2_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 4. " [4] ,Force SPI2_DMA_RX_INT" "Normal,Forced" newline bitfld.long 0x04 3. " [3] ,Force SPI1_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 2. " [2] ,Force SPI1_DMA_RX_INT" "Normal,Forced" bitfld.long 0x04 1. " [1] ,Force SPI0_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 0. " [0] ,Force SPI0_DMA_RX_INT" "Normal,Forced" line.long 0x08 "SET3,Interrupt Set 3 Register" bitfld.long 0x08 26. " FORCEFLD[26] ,Force ESAI0_DMA_INT" "Normal,Forced" bitfld.long 0x08 25. " [25] ,Force ESAI0_MOD_INT" "Normal,Forced" bitfld.long 0x08 22. " [22] ,Force SPDIF0_TX_INT" "Normal,Forced" bitfld.long 0x08 21. " [21] ,Force SPDIF0_RX_INT" "Normal,Forced" newline bitfld.long 0x08 20. " [20] ,Force SAI5_INT" "Normal,Forced" bitfld.long 0x08 19. " [19] ,Force SAI4_INT" "Normal,Forced" bitfld.long 0x08 16. " [16] ,Force SAI3_INT" "Normal,Forced" bitfld.long 0x08 15. " [15] ,Force SAI2_INT" "Normal,Forced" newline bitfld.long 0x08 14. " [14] ,Force SAI1_INT" "Normal,Forced" bitfld.long 0x08 13. " [13] ,Force SAI0_INT" "Normal,Forced" bitfld.long 0x08 12. " [12] ,Force GPT5_INT" "Normal,Forced" bitfld.long 0x08 11. " [11] ,Force GPT4_INT" "Normal,Forced" newline bitfld.long 0x08 10. " [10] ,Force GPT3_INT" "Normal,Forced" bitfld.long 0x08 9. " [9] ,Force GPT2_INT" "Normal,Forced" bitfld.long 0x08 8. " [8] ,Force GPT1_INT" "Normal,Forced" bitfld.long 0x08 7. " [7] ,Force GPT0_INT" "Normal,Forced" newline bitfld.long 0x08 4. " [4] ,Force ESAI0_INT" "Normal,Forced" bitfld.long 0x08 3. " [3] ,Force DMA1_CH5_INT" "Normal,Forced" bitfld.long 0x08 2. " [2] ,Force DMA1_CH4_INT" "Normal,Forced" bitfld.long 0x08 1. " [1] ,Force DMA1_CH3_INT" "Normal,Forced" newline bitfld.long 0x08 0. " [0] ,Force DMA1_CH2_INT" "Normal,Forced" line.long 0x0C "SET4,Interrupt Set 4 Register" bitfld.long 0x0C 31. " FORCEFLD[31] ,Force DMA1_CH1_INT" "Normal,Forced" bitfld.long 0x0C 30. " [30] ,Force DMA1_CH0_INT" "Normal,Forced" bitfld.long 0x0C 29. " [29] ,Force ASRC1_INT2" "Normal,Forced" bitfld.long 0x0C 28. " [28] ,Force ASRC1_INT1" "Normal,Forced" newline bitfld.long 0x0C 27. " [27] ,Force DMA0_CH5_INT" "Normal,Forced" bitfld.long 0x0C 26. " [26] ,Force DMA0_CH4_INT" "Normal,Forced" bitfld.long 0x0C 25. " [25] ,Force DMA0_CH3_INT" "Normal,Forced" bitfld.long 0x0C 24. " [24] ,Force DMA0_CH2_INT" "Normal,Forced" newline bitfld.long 0x0C 23. " [23] ,Force DMA0_CH1_INT" "Normal,Forced" bitfld.long 0x0C 22. " [22] ,Force DMA0_CH0_INT" "Normal,Forced" bitfld.long 0x0C 21. " [21] ,Force ASRC0_INT2" "Normal,Forced" bitfld.long 0x0C 20. " [20] ,Force ASRC0_INT1" "Normal,Forced" newline bitfld.long 0x0C 19. " [19] ,Force DMA1_ERR_INT" "Normal,Forced" bitfld.long 0x0C 18. " [18] ,Force DMA1_INT" "Normal,Forced" bitfld.long 0x0C 17. " [17] ,Force DMA0_ERR_INT" "Normal,Forced" bitfld.long 0x0C 16. " [16] ,Force DMA0_INT" "Normal,Forced" newline bitfld.long 0x0C 12. " [12] ,Force ADC_DMA_INT" "Normal,Forced" bitfld.long 0x0C 11. " [11] ,Force FTM1_DMA_INT" "Normal,Forced" bitfld.long 0x0C 10. " [10] ,Force FTM_DMA_INT" "Normal,Forced" bitfld.long 0x0C 9. " [9] ,Force FLEXCAN2_DMA_INT" "Normal,Forced" newline bitfld.long 0x0C 8. " [8] ,Force FLEXCAN1_DMA_INT" "Normal,Forced" bitfld.long 0x0C 7. " [7] ,Force FLEXCAN0_DMA_INT" "Normal,Forced" bitfld.long 0x0C 5. " [5] ,Force ADC_MOD_INT" "Normal,Forced" bitfld.long 0x0C 4. " [4] ,Force FTM1_MOD_INT" "Normal,Forced" newline bitfld.long 0x0C 3. " [3] ,Force FTM_MOD_INT" "Normal,Forced" bitfld.long 0x0C 2. " [2] ,Force FLEXCAN2_MOD_INT" "Normal,Forced" bitfld.long 0x0C 1. " [1] ,Force FLEXCAN1_MOD_INT" "Normal,Forced" bitfld.long 0x0C 0. " [0] ,Force FLEXCAN0_MOD_INT" "Normal,Forced" line.long 0x10 "SET5,Interrupt Set 5 Register" bitfld.long 0x10 28. " FORCEFLD[28] ,Force UART3_MOD_INT" "Normal,Forced" bitfld.long 0x10 27. " [27] ,Force UART2_MOD_INT" "Normal,Forced" bitfld.long 0x10 26. " [26] ,Force UART1_MOD_INT" "Normal,Forced" bitfld.long 0x10 25. " [25] ,Force UART0_MOD_INT" "Normal,Forced" newline bitfld.long 0x10 23. " [23] ,Force I2C3_MOD_INT" "Normal,Forced" bitfld.long 0x10 22. " [22] ,Force I2C2_MOD_INT" "Normal,Forced" bitfld.long 0x10 21. " [21] ,Force I2C1_MOD_INT" "Normal,Forced" bitfld.long 0x10 20. " [20] ,Force I2C0_MOD_INT" "Normal,Forced" newline bitfld.long 0x10 19. " [19] ,Force SPI3_MOD_INT" "Normal,Forced" bitfld.long 0x10 18. " [18] ,Force SPI2_MOD_INT" "Normal,Forced" bitfld.long 0x10 17. " [17] ,Force SPI1_MOD_INT" "Normal,Forced" bitfld.long 0x10 16. " [16] ,Force SPI0_MOD_INT" "Normal,Forced" newline bitfld.long 0x10 12. " [12] ,Force SAI5_DMA_INT" "Normal,Forced" bitfld.long 0x10 11. " [11] ,Force SAI5_MOD_INT" "Normal,Forced" bitfld.long 0x10 10. " [10] ,Force SAI4_DMA_INT" "Normal,Forced" bitfld.long 0x10 9. " [9] ,Force SAI4_MOD_INT" "Normal,Forced" newline bitfld.long 0x10 4. " [4] ,Force SAI3_DMA_INT" "Normal,Forced" bitfld.long 0x10 3. " [3] ,Force SAI3_MOD_INT" "Normal,Forced" bitfld.long 0x10 0. " [0] ,Force INT_OUT" "Normal,Forced" line.long 0x14 "SET6,Interrupt Set 6 Register" bitfld.long 0x14 31. " FORCEFLD[31] ,Force SAI2_DMA_INT" "Normal,Forced" bitfld.long 0x14 30. " [30] ,Force SAI2_MOD_INT" "Normal,Forced" bitfld.long 0x14 29. " [29] ,Force SAI1_DMA_INT" "Normal,Forced" bitfld.long 0x14 28. " [28] ,Force SAI1_MOD_INT" "Normal,Forced" newline bitfld.long 0x14 27. " [27] ,Force SAI0_DMA_INT" "Normal,Forced" bitfld.long 0x14 26. " [26] ,Force SAI0_MOD_INT" "Normal,Forced" bitfld.long 0x14 24. " [24] ,Force MJPEG_DEC3_INT" "Normal,Forced" bitfld.long 0x14 23. " [23] ,Force MJPEG_DEC2_INT" "Normal,Forced" newline bitfld.long 0x14 22. " [22] ,Force MJPEG_DEC1_INT" "Normal,Forced" bitfld.long 0x14 21. " [21] ,Force MJPEG_DEC0_INT" "Normal,Forced" bitfld.long 0x14 20. " [20] ,Force MJPEG_ENC3_INT" "Normal,Forced" bitfld.long 0x14 19. " [19] ,Force MJPEG_ENC2_INT" "Normal,Forced" newline bitfld.long 0x14 18. " [18] ,Force MJPEG_ENC1_INT" "Normal,Forced" bitfld.long 0x14 17. " [17] ,Force MJPEG_ENC0_INT" "Normal,Forced" bitfld.long 0x14 16. " [16] ,Force PDMA_STREAM7_INT" "Normal,Forced" bitfld.long 0x14 15. " [15] ,Force PDMA_STREAM6_INT" "Normal,Forced" newline bitfld.long 0x14 14. " [14] ,Force PDMA_STREAM5_INT" "Normal,Forced" bitfld.long 0x14 13. " [13] ,Force PDMA_STREAM4_INT" "Normal,Forced" bitfld.long 0x14 12. " [12] ,Force PDMA_STREAM3_INT" "Normal,Forced" bitfld.long 0x14 11. " [11] ,Force PDMA_STREAM2_INT" "Normal,Forced" newline bitfld.long 0x14 10. " [10] ,Force PDMA_STREAM1_INT" "Normal,Forced" bitfld.long 0x14 9. " [9] ,Force PDMA_STREAM0_INT" "Normal,Forced" bitfld.long 0x14 0. " [0] ,Force MSI_INT" "Normal,Forced" line.long 0x18 "SET7,Interrupt Set 7 Register" bitfld.long 0x18 20. " FORCEFLD[20] ,Force DMA_ERR_INT" "Normal,Forced" bitfld.long 0x18 19. " [19] ,Force DMA_INT" "Normal,Forced" bitfld.long 0x18 18. " [18] ,Force APBHDMA" "Normal,Forced" bitfld.long 0x18 17. " [17] ,Force NAND_GPMI_INT" "Normal,Forced" newline bitfld.long 0x18 16. " [16] ,Force NAND_BCH_INT" "Normal,Forced" bitfld.long 0x18 15. " [15] ,Force USB3_INT" "Normal,Forced" bitfld.long 0x18 14. " [14] ,Force WAKEUP_INT" "Normal,Forced" bitfld.long 0x18 13. " [13] ,Force UTMI_INT" "Normal,Forced" newline bitfld.long 0x18 12. " [12] ,Force USB_HOST_INT" "Normal,Forced" bitfld.long 0x18 11. " [11] ,Force USB_OTG_INT" "Normal,Forced" bitfld.long 0x18 10. " [10] ,Force MLB_AHB_INT" "Normal,Forced" bitfld.long 0x18 9. " [9] ,Force MLB_INT" "Normal,Forced" newline bitfld.long 0x18 7. " [7] ,Force ENET1_TIMER_INT" "Normal,Forced" bitfld.long 0x18 6. " [6] ,Force ENET1_FRAME0_EVENT_INT" "Normal,Forced" bitfld.long 0x18 5. " [5] ,Force ENET1_FRAME2_INT" "Normal,Forced" bitfld.long 0x18 4. " [4] ,Force ENET1_FRAME1_INT" "Normal,Forced" newline bitfld.long 0x18 3. " [3] ,Force ENET0_TIMER_INT" "Normal,Forced" bitfld.long 0x18 2. " [2] ,Force ENET0_FRAME0_EVENT_INT" "Normal,Forced" bitfld.long 0x18 1. " [1] ,Force ENET0_FRAME2_INT" "Normal,Forced" bitfld.long 0x18 0. " [0] ,Force ENET0_FRAME1_INT" "Normal,Forced" line.long 0x1C "SET8,Interrupt Set 8 Register" bitfld.long 0x1C 23. " FORCEFLD[23] ,Force EXTERNAL_DMA_INT_5" "Normal,Forced" bitfld.long 0x1C 22. " [22] ,Force EXTERNAL_DMA_INT_4" "Normal,Forced" bitfld.long 0x1C 21. " [21] ,Force EXTERNAL_DMA_INT_3" "Normal,Forced" bitfld.long 0x1C 20. " [20] ,Force EXTERNAL_DMA_INT_2" "Normal,Forced" newline bitfld.long 0x1C 19. " [19] ,Force EXTERNAL_DMA_INT_1" "Normal,Forced" bitfld.long 0x1C 18. " [18] ,Force EXTERNAL_DMA_INT_0" "Normal,Forced" bitfld.long 0x1C 16. " [16] ,Force ADC_INT" "Normal,Forced" bitfld.long 0x1C 15. " [15] ,Force FTM1_INT" "Normal,Forced" newline bitfld.long 0x1C 14. " [14] ,Force FTM_INT" "Normal,Forced" bitfld.long 0x1C 13. " [13] ,Force FLEXCAN2_INT" "Normal,Forced" bitfld.long 0x1C 12. " [12] ,Force FLEXCAN1_INT" "Normal,Forced" bitfld.long 0x1C 11. " [11] ,Force FLEXCAN0_INT" "Normal,Forced" newline bitfld.long 0x1C 10. " [10] ,Force USDHC2_INT" "Normal,Forced" bitfld.long 0x1C 9. " [9] ,Force USDHC1_INT" "Normal,Forced" bitfld.long 0x1C 8. " [8] ,Force EMMC0_INT/USDHC0_INT" "Normal,Forced" bitfld.long 0x1C 4. " [4] ,Force UART3_INT" "Normal,Forced" newline bitfld.long 0x1C 3. " [3] ,Force UART2_INT" "Normal,Forced" bitfld.long 0x1C 2. " [2] ,Force UART1_INT" "Normal,Forced" bitfld.long 0x1C 1. " [1] ,Force UART0_INT" "Normal,Forced" line.long 0x20 "SET9,Interrupt Set 9 Register" bitfld.long 0x20 31. " FORCEFLD[31] ,Force I2C3_INT" "Normal,Forced" bitfld.long 0x20 30. " [30] ,Force I2C2_INT" "Normal,Forced" bitfld.long 0x20 29. " [29] ,Force I2C1_INT" "Normal,Forced" bitfld.long 0x20 28. " [28] ,Force I2C0_INT" "Normal,Forced" newline bitfld.long 0x20 27. " [27] ,Force SPI3_INT" "Normal,Forced" bitfld.long 0x20 26. " [26] ,Force SPI2_INT" "Normal,Forced" bitfld.long 0x20 25. " [25] ,Force SPI1_INT" "Normal,Forced" bitfld.long 0x20 24. " [24] ,Force SPI0_INT" "Normal,Forced" newline bitfld.long 0x20 16. " [16] ,Force MU13_INT_B" "Normal,Forced" bitfld.long 0x20 15. " [15] ,Force MU12_INT_B" "Normal,Forced" bitfld.long 0x20 14. " [14] ,Force MU11_INT_B" "Normal,Forced" bitfld.long 0x20 13. " [13] ,Force MU10_INT_B" "Normal,Forced" newline bitfld.long 0x20 12. " [12] ,Force MU9_INT_B" "Normal,Forced" bitfld.long 0x20 11. " [11] ,Force MU8_INT_B" "Normal,Forced" bitfld.long 0x20 10. " [10] ,Force MU7_INT_B" "Normal,Forced" bitfld.long 0x20 9. " [9] ,Force MU6_INT_B" "Normal,Forced" newline bitfld.long 0x20 8. " [8] ,Force MU5_INT_B" "Normal,Forced" bitfld.long 0x20 0. " [0] ,Force MU13_INT_A" "Normal,Forced" line.long 0x24 "SET10,Interrupt Set 10 Register" bitfld.long 0x24 31. " FORCEFLD[31] ,Force MU12_INT_A" "Normal,Forced" bitfld.long 0x24 30. " [30] ,Force MU11_INT_A" "Normal,Forced" bitfld.long 0x24 29. " [29] ,Force MU10_INT_A" "Normal,Forced" bitfld.long 0x24 28. " [28] ,Force MU9_INT_A" "Normal,Forced" newline bitfld.long 0x24 27. " [27] ,Force MU8_INT_A" "Normal,Forced" bitfld.long 0x24 26. " [26] ,Force MU7_INT_A" "Normal,Forced" bitfld.long 0x24 25. " [25] ,Force MU6_INT_A" "Normal,Forced" bitfld.long 0x24 24. " [24] ,Force MU5_INT_A" "Normal,Forced" newline bitfld.long 0x24 20. " [20] ,Force MU4_INT" "Normal,Forced" bitfld.long 0x24 19. " [19] ,Force MU3_INT" "Normal,Forced" bitfld.long 0x24 18. " [18] ,Force MU2_INT" "Normal,Forced" bitfld.long 0x24 17. " [17] ,Force MU1_INT" "Normal,Forced" newline bitfld.long 0x24 16. " [16] ,Force MU0_INT" "Normal,Forced" line.long 0x28 "SET11,Interrupt Set 11 Register" bitfld.long 0x28 15. " FORCEFLD[15] ,Force GPIO_INT[7]" "Normal,Forced" bitfld.long 0x28 14. " [14] ,Force GPIO_INT[6]" "Normal,Forced" bitfld.long 0x28 13. " [13] ,Force GPIO_INT[5]" "Normal,Forced" bitfld.long 0x28 12. " [12] ,Force GPIO_INT[4]" "Normal,Forced" newline bitfld.long 0x28 11. " [11] ,Force GPIO_INT[3]" "Normal,Forced" bitfld.long 0x28 10. " [10] ,Force GPIO_INT[2]" "Normal,Forced" bitfld.long 0x28 9. " [9] ,Force GPIO_INT[1]" "Normal,Forced" bitfld.long 0x28 8. " [8] ,Force GPIO_INT[0]" "Normal,Forced" newline bitfld.long 0x28 3. " [3] ,Force PERF_CNT_INT" "Normal,Forced" bitfld.long 0x28 2. " [2] ,Force SBR_DONE_INT" "Normal,Forced" bitfld.long 0x28 1. " [1] ,Force ECC_NCORRECT_INT" "Normal,Forced" bitfld.long 0x28 0. " [0] ,Force ECC_CORRECT_INT" "Normal,Forced" line.long 0x2C "SET12,Interrupt Set 12 Register" bitfld.long 0x2C 27. " FORCEFLD[27] ,Force SYS_COUNT_INT[3]" "Normal,Forced" bitfld.long 0x2C 26. " [26] ,Force SYS_COUNT_INT[2]" "Normal,Forced" bitfld.long 0x2C 25. " [25] ,Force SYS_COUNT_INT[1]" "Normal,Forced" bitfld.long 0x2C 24. " [24] ,Force SYS_COUNT_INT[0]" "Normal,Forced" newline bitfld.long 0x2C 23. " [23] ,Force INT_OUT[7]" "Normal,Forced" bitfld.long 0x2C 22. " [22] ,Force INT_OUT[6]" "Normal,Forced" bitfld.long 0x2C 21. " [21] ,Force INT_OUT[5]" "Normal,Forced" bitfld.long 0x2C 20. " [20] ,Force INT_OUT[4]" "Normal,Forced" newline bitfld.long 0x2C 19. " [19] ,Force INT_OUT[3]" "Normal,Forced" bitfld.long 0x2C 18. " [18] ,Force INT_OUT[2]" "Normal,Forced" bitfld.long 0x2C 17. " [17] ,Force INT_OUT[1]" "Normal,Forced" bitfld.long 0x2C 16. " [16] ,Force INT_OUT[0]" "Normal,Forced" newline bitfld.long 0x2C 15. " [15] ,Force PCIE9_GPIO_WAKEUP[1]" "Normal,Forced" bitfld.long 0x2C 14. " [14] ,Force PCIE9_GPIO_WAKEUP[0]" "Normal,Forced" bitfld.long 0x2C 13. " [13] ,Force PCIE0_SMLH_REQ_RST" "Normal,Forced" bitfld.long 0x2C 12. " [12] ,Force PCIE0_INT_A" "Normal,Forced" newline bitfld.long 0x2C 11. " [11] ,Force PCIE0_INT_B" "Normal,Forced" bitfld.long 0x2C 10. " [10] ,Force PCIE0_INT_C" "Normal,Forced" bitfld.long 0x2C 9. " [9] ,Force PCIE0_INT_D" "Normal,Forced" bitfld.long 0x2C 8. " [8] ,Force PCIE0_DMA_INT" "Normal,Forced" newline bitfld.long 0x2C 7. " [7] ,Force PCIE0_CLK_REQ_INT" "Normal,Forced" bitfld.long 0x2C 6. " [6] ,Force PCIE0_MSI_CTRL_INT" "Normal,Forced" bitfld.long 0x2C 5. " [5] ,Force PWM7_INT" "Normal,Forced" bitfld.long 0x2C 4. " [4] ,Force PWM6_INT" "Normal,Forced" newline bitfld.long 0x2C 3. " [3] ,Force PWM5_INT" "Normal,Forced" bitfld.long 0x2C 2. " [2] ,Force PWM4_INT" "Normal,Forced" bitfld.long 0x2C 1. " [1] ,Force PWM3_INT" "Normal,Forced" bitfld.long 0x2C 0. " [0] ,Force PWM2_INT" "Normal,Forced" line.long 0x30 "SET13,Interrupt Set 13 Register" bitfld.long 0x30 31. " FORCEFLD[31] ,Force PWM1_INT" "Normal,Forced" bitfld.long 0x30 30. " [30] ,Force PWM0_INT" "Normal,Forced" bitfld.long 0x30 29. " [29] ,Force FLEXSPI1_INT" "Normal,Forced" bitfld.long 0x30 28. " [28] ,Force FLEXSPI0_INT" "Normal,Forced" newline bitfld.long 0x30 21. " [21] ,Force KPP0_INT" "Normal,Forced" bitfld.long 0x30 20. " [20] ,Force GPT4_INT" "Normal,Forced" bitfld.long 0x30 19. " [19] ,Force GPT3_INT" "Normal,Forced" bitfld.long 0x30 18. " [18] ,Force GPT2_INT" "Normal,Forced" newline bitfld.long 0x30 17. " [17] ,Force GPT1_INT" "Normal,Forced" bitfld.long 0x30 16. " [16] ,Force GPT0_INT" "Normal,Forced" bitfld.long 0x30 5. " [5] ,Force DMA3_ERR_INT" "Normal,Forced" bitfld.long 0x30 4. " [4] ,Force DMA3_INT" "Normal,Forced" newline bitfld.long 0x30 3. " [3] ,Force DMA2_ERR_INT" "Normal,Forced" bitfld.long 0x30 2. " [2] ,Force DMA2_INT" "Normal,Forced" bitfld.long 0x30 0. " [0] ,Force XAQ2_INTR" "Normal,Forced" line.long 0x34 "SET14,Interrupt Set 14 Register" bitfld.long 0x34 31. " FORCEFLD[31] ,Force LCD_PWM_INT" "Normal,Forced" bitfld.long 0x34 30. " [30] ,Force LCD_MOD_INT" "Normal,Forced" bitfld.long 0x34 28. " [28] ,Force INT_OUT" "Normal,Forced" bitfld.long 0x34 27. " [27] ,Force INT_OUT" "Normal,Forced" newline bitfld.long 0x34 20. " [20] ,Force INT_OUT[12]" "Normal,Forced" bitfld.long 0x34 19. " [19] ,Force INT_OUT[11]" "Normal,Forced" bitfld.long 0x34 18. " [18] ,Force INT_OUT[10]" "Normal,Forced" bitfld.long 0x34 17. " [17] ,Force INT_OUT[9]" "Normal,Forced" newline bitfld.long 0x34 15. " [15] ,Force INT_OUT[7]" "Normal,Forced" bitfld.long 0x34 14. " [14] ,Force INT_OUT[6]" "Normal,Forced" bitfld.long 0x34 13. " [13] ,Force INT_OUT[5]" "Normal,Forced" bitfld.long 0x34 12. " [12] ,Force INT_OUT[4]" "Normal,Forced" newline bitfld.long 0x34 11. " [11] ,Force INT_OUT[3]" "Normal,Forced" bitfld.long 0x34 10. " [10] ,Force INT_OUT[2]" "Normal,Forced" bitfld.long 0x34 9. " [9] ,Force INT_OUT[1]" "Normal,Forced" bitfld.long 0x34 8. " [8] ,Force INT_OUT[0]" "Normal,Forced" line.long 0x38 "SET15,Interrupt Set 15 Register" bitfld.long 0x38 23. " FORCEFLD[23] ,Force INT_OUT[7]" "Normal,Forced" bitfld.long 0x38 22. " [22] ,Force INT_OUT[6]" "Normal,Forced" bitfld.long 0x38 21. " [21] ,Force INT_OUT[5]" "Normal,Forced" bitfld.long 0x38 20. " [20] ,Force INT_OUT[4]" "Normal,Forced" newline bitfld.long 0x38 19. " [19] ,Force INT_OUT[3]" "Normal,Forced" bitfld.long 0x38 18. " [18] ,Force INT_OUT[2]" "Normal,Forced" bitfld.long 0x38 17. " [17] ,Force INT_OUT[1]" "Normal,Forced" bitfld.long 0x38 16. " [16] ,Force INT_OUT[0]" "Normal,Forced" newline bitfld.long 0x38 1. " [1] ,Force nEXTERRIRQ" "Normal,Forced" bitfld.long 0x38 0. " [0] ,Force nINTERRIRQ" "Normal,Forced" rgroup.long 0x88++0x3B line.long 0x00 "STATUS1,Interrupt Status 1 Register" bitfld.long 0x00 22. " STATUS[22] ,VPU_INT_6 status" "Not set,Set" bitfld.long 0x00 21. " [21] ,VPU_INT_5 status" "Not set,Set" bitfld.long 0x00 20. " [20] ,VPU_INT_4 status" "Not set,Set" bitfld.long 0x00 19. " [19] ,VPU_INT_3 status" "Not set,Set" newline bitfld.long 0x00 18. " [18] ,VPU_INT_2 status" "Not set,Set" bitfld.long 0x00 17. " [17] ,VPU_INT_1 status" "Not set,Set" bitfld.long 0x00 16. " [16] ,VPU_INT_0 status" "Not set,Set" bitfld.long 0x00 11. " [11] ,SPDIF0_TX_DMA_INT status" "Not set,Set" newline bitfld.long 0x00 10. " [10] ,SPDIF0_TX_MOD_INT status" "Not set,Set" bitfld.long 0x00 9. " [9] ,SPDIF0_RX_DMA_INT status" "Not set,Set" bitfld.long 0x00 8. " [8] ,SPDIF0_RX_MOD_INT status" "Not set,Set" bitfld.long 0x00 7. " [7] ,CAAM_RTIC_INT status" "Not set,Set" newline bitfld.long 0x00 6. " [6] ,CAAM_INT3 status" "Not set,Set" bitfld.long 0x00 5. " [5] ,CAAM_INT2 status" "Not set,Set" bitfld.long 0x00 4. " [4] ,CAAM_INT1 status" "Not set,Set" bitfld.long 0x00 3. " [3] ,CAAM_INT0 status" "Not set,Set" newline bitfld.long 0x00 2. " [2] ,SEC_MU3_A_INT status" "Not set,Set" bitfld.long 0x00 1. " [1] ,SEC_MU2_A_INT status" "Not set,Set" bitfld.long 0x00 0. " [0] ,SEC_MU1_A_INT status" "Not set,Set" line.long 0x04 "STATUS2,Interrupt Status 2 Register" bitfld.long 0x04 25. " STATUS[25] ,UART3_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 24. " [24] ,UART3_DMA_RX_INT status" "Not set,Set" bitfld.long 0x04 23. " [23] ,UART2_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 22. " [22] ,UART2_DMA_RX_INT status" "Not set,Set" newline bitfld.long 0x04 21. " [21] ,UART1_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 20. " [20] ,UART1_DMA_RX_INT status" "Not set,Set" bitfld.long 0x04 19. " [19] ,UART0_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 18. " [18] ,UART0_DMA_RX_INT status" "Not set,Set" newline bitfld.long 0x04 15. " [15] ,I2C3_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 14. " [14] ,I2C3_DMA_RX_INT status" "Not set,Set" bitfld.long 0x04 13. " [13] ,I2C2_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 12. " [12] ,I2C2_DMA_RX_INT status" "Not set,Set" newline bitfld.long 0x04 11. " [11] ,I2C1_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 10. " [10] ,I2C1_DMA_RX_INT status" "Not set,Set" bitfld.long 0x04 9. " [9] ,I2C0_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 8. " [8] ,I2C0_DMA_RX_INT status" "Not set,Set" newline bitfld.long 0x04 7. " [7] ,SPI3_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 6. " [6] ,SPI3_DMA_RX_INT status" "Not set,Set" bitfld.long 0x04 5. " [5] ,SPI2_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 4. " [4] ,SPI2_DMA_RX_INT status" "Not set,Set" newline bitfld.long 0x04 3. " [3] ,SPI1_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 2. " [2] ,SPI1_DMA_RX_INT status" "Not set,Set" bitfld.long 0x04 1. " [1] ,SPI0_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 0. " [0] ,SPI0_DMA_RX_INT status" "Not set,Set" line.long 0x08 "STATUS3,Interrupt Status 3 Register" bitfld.long 0x08 26. " STATUS[26] ,ESAI0_DMA_INT status" "Not set,Set" bitfld.long 0x08 25. " [25] ,ESAI0_MOD_INT status" "Not set,Set" bitfld.long 0x08 22. " [22] ,SPDIF0_TX_INT status" "Not set,Set" bitfld.long 0x08 21. " [21] ,SPDIF0_RX_INT status" "Not set,Set" newline bitfld.long 0x08 20. " [20] ,SAI5_INT status" "Not set,Set" bitfld.long 0x08 19. " [19] ,SAI4_INT status" "Not set,Set" bitfld.long 0x08 16. " [16] ,SAI3_INT status" "Not set,Set" bitfld.long 0x08 15. " [15] ,SAI2_INT status" "Not set,Set" newline bitfld.long 0x08 14. " [14] ,SAI1_INT status" "Not set,Set" bitfld.long 0x08 13. " [13] ,SAI0_INT status" "Not set,Set" bitfld.long 0x08 12. " [12] ,GPT5_INT status" "Not set,Set" bitfld.long 0x08 11. " [11] ,GPT4_INT status" "Not set,Set" newline bitfld.long 0x08 10. " [10] ,GPT3_INT status" "Not set,Set" bitfld.long 0x08 9. " [9] ,GPT2_INT status" "Not set,Set" bitfld.long 0x08 8. " [8] ,GPT1_INT status" "Not set,Set" bitfld.long 0x08 7. " [7] ,GPT0_INT status" "Not set,Set" newline bitfld.long 0x08 4. " [4] ,ESAI0_INT status" "Not set,Set" bitfld.long 0x08 3. " [3] ,DMA1_CH5_INT status" "Not set,Set" bitfld.long 0x08 2. " [2] ,DMA1_CH4_INT status" "Not set,Set" bitfld.long 0x08 1. " [1] ,DMA1_CH3_INT status" "Not set,Set" newline bitfld.long 0x08 0. " [0] ,DMA1_CH2_INT status" "Not set,Set" line.long 0x0C "STATUS4,Interrupt Status 4 Register" bitfld.long 0x0C 31. " STATUS[31] ,DMA1_CH1_INT status" "Not set,Set" bitfld.long 0x0C 30. " [30] ,DMA1_CH0_INT status" "Not set,Set" bitfld.long 0x0C 29. " [29] ,ASRC1_INT2 status" "Not set,Set" bitfld.long 0x0C 28. " [28] ,ASRC1_INT1 status" "Not set,Set" newline bitfld.long 0x0C 27. " [27] ,DMA0_CH5_INT status" "Not set,Set" bitfld.long 0x0C 26. " [26] ,DMA0_CH4_INT status" "Not set,Set" bitfld.long 0x0C 25. " [25] ,DMA0_CH3_INT status" "Not set,Set" bitfld.long 0x0C 24. " [24] ,DMA0_CH2_INT status" "Not set,Set" newline bitfld.long 0x0C 23. " [23] ,DMA0_CH1_INT status" "Not set,Set" bitfld.long 0x0C 22. " [22] ,DMA0_CH0_INT status" "Not set,Set" bitfld.long 0x0C 21. " [21] ,ASRC0_INT2 status" "Not set,Set" bitfld.long 0x0C 20. " [20] ,ASRC0_INT1 status" "Not set,Set" newline bitfld.long 0x0C 19. " [19] ,DMA1_ERR_INT status" "Not set,Set" bitfld.long 0x0C 18. " [18] ,DMA1_INT status" "Not set,Set" bitfld.long 0x0C 17. " [17] ,DMA0_ERR_INT status" "Not set,Set" bitfld.long 0x0C 16. " [16] ,DMA0_INT status" "Not set,Set" newline bitfld.long 0x0C 12. " [12] ,ADC_DMA_INT status" "Not set,Set" bitfld.long 0x0C 11. " [11] ,FTM1_DMA_INT status" "Not set,Set" bitfld.long 0x0C 10. " [10] ,FTM_DMA_INT status" "Not set,Set" bitfld.long 0x0C 9. " [9] ,FLEXCAN2_DMA_INT status" "Not set,Set" newline bitfld.long 0x0C 8. " [8] ,FLEXCAN1_DMA_INT status" "Not set,Set" bitfld.long 0x0C 7. " [7] ,FLEXCAN0_DMA_INT status" "Not set,Set" bitfld.long 0x0C 5. " [5] ,ADC_MOD_INT status" "Not set,Set" bitfld.long 0x0C 4. " [4] ,FTM1_MOD_INT status" "Not set,Set" newline bitfld.long 0x0C 3. " [3] ,FTM_MOD_INT status" "Not set,Set" bitfld.long 0x0C 2. " [2] ,FLEXCAN2_MOD_INT status" "Not set,Set" bitfld.long 0x0C 1. " [1] ,FLEXCAN1_MOD_INT status" "Not set,Set" bitfld.long 0x0C 0. " [0] ,FLEXCAN0_MOD_INT status" "Not set,Set" line.long 0x10 "STATUS5,Interrupt Status 5 Register" bitfld.long 0x10 28. " STATUS[28] ,UART3_MOD_INT status" "Not set,Set" bitfld.long 0x10 27. " [27] ,UART2_MOD_INT status" "Not set,Set" bitfld.long 0x10 26. " [26] ,UART1_MOD_INT status" "Not set,Set" bitfld.long 0x10 25. " [25] ,UART0_MOD_INT status" "Not set,Set" newline bitfld.long 0x10 23. " [23] ,I2C3_MOD_INT status" "Not set,Set" bitfld.long 0x10 22. " [22] ,I2C2_MOD_INT status" "Not set,Set" bitfld.long 0x10 21. " [21] ,I2C1_MOD_INT status" "Not set,Set" bitfld.long 0x10 20. " [20] ,I2C0_MOD_INT status" "Not set,Set" newline bitfld.long 0x10 19. " [19] ,SPI3_MOD_INT status" "Not set,Set" bitfld.long 0x10 18. " [18] ,SPI2_MOD_INT status" "Not set,Set" bitfld.long 0x10 17. " [17] ,SPI1_MOD_INT status" "Not set,Set" bitfld.long 0x10 16. " [16] ,SPI0_MOD_INT status" "Not set,Set" newline bitfld.long 0x10 12. " [12] ,SAI5_DMA_INT status" "Not set,Set" bitfld.long 0x10 11. " [11] ,SAI5_MOD_INT status" "Not set,Set" bitfld.long 0x10 10. " [10] ,SAI4_DMA_INT status" "Not set,Set" bitfld.long 0x10 9. " [9] ,SAI4_MOD_INT status" "Not set,Set" newline bitfld.long 0x10 4. " [4] ,SAI3_DMA_INT status" "Not set,Set" bitfld.long 0x10 3. " [3] ,SAI3_MOD_INT status" "Not set,Set" bitfld.long 0x10 0. " [0] ,INT_OUT status" "Not set,Set" line.long 0x14 "STATUS6,Interrupt Status 6 Register" bitfld.long 0x14 31. " STATUS[31] ,SAI2_DMA_INT status" "Not set,Set" bitfld.long 0x14 30. " [30] ,SAI2_MOD_INT status" "Not set,Set" bitfld.long 0x14 29. " [29] ,SAI1_DMA_INT status" "Not set,Set" bitfld.long 0x14 28. " [28] ,SAI1_MOD_INT status" "Not set,Set" newline bitfld.long 0x14 27. " [27] ,SAI0_DMA_INT status" "Not set,Set" bitfld.long 0x14 26. " [26] ,SAI0_MOD_INT status" "Not set,Set" bitfld.long 0x14 24. " [24] ,MJPEG_DEC3_INT status" "Not set,Set" bitfld.long 0x14 23. " [23] ,MJPEG_DEC2_INT status" "Not set,Set" newline bitfld.long 0x14 22. " [22] ,MJPEG_DEC1_INT status" "Not set,Set" bitfld.long 0x14 21. " [21] ,MJPEG_DEC0_INT status" "Not set,Set" bitfld.long 0x14 20. " [20] ,MJPEG_ENC3_INT status" "Not set,Set" bitfld.long 0x14 19. " [19] ,MJPEG_ENC2_INT status" "Not set,Set" newline bitfld.long 0x14 18. " [18] ,MJPEG_ENC1_INT status" "Not set,Set" bitfld.long 0x14 17. " [17] ,MJPEG_ENC0_INT status" "Not set,Set" bitfld.long 0x14 16. " [16] ,PDMA_STREAM7_INT status" "Not set,Set" bitfld.long 0x14 15. " [15] ,PDMA_STREAM6_INT status" "Not set,Set" newline bitfld.long 0x14 14. " [14] ,PDMA_STREAM5_INT status" "Not set,Set" bitfld.long 0x14 13. " [13] ,PDMA_STREAM4_INT status" "Not set,Set" bitfld.long 0x14 12. " [12] ,PDMA_STREAM3_INT status" "Not set,Set" bitfld.long 0x14 11. " [11] ,PDMA_STREAM2_INT status" "Not set,Set" newline bitfld.long 0x14 10. " [10] ,PDMA_STREAM1_INT status" "Not set,Set" bitfld.long 0x14 9. " [9] ,PDMA_STREAM0_INT status" "Not set,Set" bitfld.long 0x14 0. " [0] ,MSI_INT status" "Not set,Set" line.long 0x18 "STATUS7,Interrupt Status 7 Register" bitfld.long 0x18 20. " STATUS[20] ,DMA_ERR_INT status" "Not set,Set" bitfld.long 0x18 19. " [19] ,DMA_INT status" "Not set,Set" bitfld.long 0x18 18. " [18] ,APBHDMA status" "Not set,Set" bitfld.long 0x18 17. " [17] ,NAND_GPMI_INT status" "Not set,Set" newline bitfld.long 0x18 16. " [16] ,NAND_BCH_INT status" "Not set,Set" bitfld.long 0x18 15. " [15] ,USB3_INT status" "Not set,Set" bitfld.long 0x18 14. " [14] ,WAKEUP_INT status" "Not set,Set" bitfld.long 0x18 13. " [13] ,UTMI_INT status" "Not set,Set" newline bitfld.long 0x18 12. " [12] ,USB_HOST_INT status" "Not set,Set" bitfld.long 0x18 11. " [11] ,USB_OTG_INT status" "Not set,Set" bitfld.long 0x18 10. " [10] ,MLB_AHB_INT status" "Not set,Set" bitfld.long 0x18 9. " [9] ,MLB_INT status" "Not set,Set" newline bitfld.long 0x18 7. " [7] ,ENET1_TIMER_INT status" "Not set,Set" bitfld.long 0x18 6. " [6] ,ENET1_FRAME0_EVENT_INT status" "Not set,Set" bitfld.long 0x18 5. " [5] ,ENET1_FRAME2_INT status" "Not set,Set" bitfld.long 0x18 4. " [4] ,ENET1_FRAME1_INT status" "Not set,Set" newline bitfld.long 0x18 3. " [3] ,ENET0_TIMER_INT status" "Not set,Set" bitfld.long 0x18 2. " [2] ,ENET0_FRAME0_EVENT_INT status" "Not set,Set" bitfld.long 0x18 1. " [1] ,ENET0_FRAME2_INT status" "Not set,Set" bitfld.long 0x18 0. " [0] ,ENET0_FRAME1_INT status" "Not set,Set" line.long 0x1C "STATUS8,Interrupt Status 8 Register" bitfld.long 0x1C 23. " STATUS[23] ,EXTERNAL_DMA_INT_5 status" "Not set,Set" bitfld.long 0x1C 22. " [22] ,EXTERNAL_DMA_INT_4 status" "Not set,Set" bitfld.long 0x1C 21. " [21] ,EXTERNAL_DMA_INT_3 status" "Not set,Set" bitfld.long 0x1C 20. " [20] ,EXTERNAL_DMA_INT_2 status" "Not set,Set" newline bitfld.long 0x1C 19. " [19] ,EXTERNAL_DMA_INT_1 status" "Not set,Set" bitfld.long 0x1C 18. " [18] ,EXTERNAL_DMA_INT_0 status" "Not set,Set" bitfld.long 0x1C 16. " [16] ,ADC_INT status" "Not set,Set" bitfld.long 0x1C 15. " [15] ,FTM1_INT status" "Not set,Set" newline bitfld.long 0x1C 14. " [14] ,FTM_INT status" "Not set,Set" bitfld.long 0x1C 13. " [13] ,FLEXCAN2_INT status" "Not set,Set" bitfld.long 0x1C 12. " [12] ,FLEXCAN1_INT status" "Not set,Set" bitfld.long 0x1C 11. " [11] ,FLEXCAN0_INT status" "Not set,Set" newline bitfld.long 0x1C 10. " [10] ,USDHC2_INT status" "Not set,Set" bitfld.long 0x1C 9. " [9] ,USDHC1_INT status" "Not set,Set" bitfld.long 0x1C 8. " [8] ,EMMC0_INT/USDHC0_INT status" "Not set,Set" bitfld.long 0x1C 4. " [4] ,UART3_INT status" "Not set,Set" newline bitfld.long 0x1C 3. " [3] ,UART2_INT status" "Not set,Set" bitfld.long 0x1C 2. " [2] ,UART1_INT status" "Not set,Set" bitfld.long 0x1C 1. " [1] ,UART0_INT status" "Not set,Set" line.long 0x20 "STATUS9,Interrupt Status 9 Register" bitfld.long 0x20 31. " STATUS[31] ,I2C3_INT status" "Not set,Set" bitfld.long 0x20 30. " [30] ,I2C2_INT status" "Not set,Set" bitfld.long 0x20 29. " [29] ,I2C1_INT status" "Not set,Set" bitfld.long 0x20 28. " [28] ,I2C0_INT status" "Not set,Set" newline bitfld.long 0x20 27. " [27] ,SPI3_INT status" "Not set,Set" bitfld.long 0x20 26. " [26] ,SPI2_INT status" "Not set,Set" bitfld.long 0x20 25. " [25] ,SPI1_INT status" "Not set,Set" bitfld.long 0x20 24. " [24] ,SPI0_INT status" "Not set,Set" newline bitfld.long 0x20 16. " [16] ,MU13_INT_B status" "Not set,Set" bitfld.long 0x20 15. " [15] ,MU12_INT_B status" "Not set,Set" bitfld.long 0x20 14. " [14] ,MU11_INT_B status" "Not set,Set" bitfld.long 0x20 13. " [13] ,MU10_INT_B status" "Not set,Set" newline bitfld.long 0x20 12. " [12] ,MU9_INT_B status" "Not set,Set" bitfld.long 0x20 11. " [11] ,MU8_INT_B status" "Not set,Set" bitfld.long 0x20 10. " [10] ,MU7_INT_B status" "Not set,Set" bitfld.long 0x20 9. " [9] ,MU6_INT_B status" "Not set,Set" newline bitfld.long 0x20 8. " [8] ,MU5_INT_B status" "Not set,Set" bitfld.long 0x20 0. " [0] ,MU13_INT_A status" "Not set,Set" line.long 0x24 "STATUS10,Interrupt Status 10 Register" bitfld.long 0x24 31. " STATUS[31] ,MU12_INT_A status" "Not set,Set" bitfld.long 0x24 30. " [30] ,MU11_INT_A status" "Not set,Set" bitfld.long 0x24 29. " [29] ,MU10_INT_A status" "Not set,Set" bitfld.long 0x24 28. " [28] ,MU9_INT_A status" "Not set,Set" newline bitfld.long 0x24 27. " [27] ,MU8_INT_A status" "Not set,Set" bitfld.long 0x24 26. " [26] ,MU7_INT_A status" "Not set,Set" bitfld.long 0x24 25. " [25] ,MU6_INT_A status" "Not set,Set" bitfld.long 0x24 24. " [24] ,MU5_INT_A status" "Not set,Set" newline bitfld.long 0x24 20. " [20] ,MU4_INT status" "Not set,Set" bitfld.long 0x24 19. " [19] ,MU3_INT status" "Not set,Set" bitfld.long 0x24 18. " [18] ,MU2_INT status" "Not set,Set" bitfld.long 0x24 17. " [17] ,MU1_INT status" "Not set,Set" newline bitfld.long 0x24 16. " [16] ,MU0_INT status" "Not set,Set" line.long 0x28 "STATUS11,Interrupt Status 11 Register" bitfld.long 0x28 15. " STATUS[15] ,GPIO_INT[7] status" "Not set,Set" bitfld.long 0x28 14. " [14] ,GPIO_INT[6] status" "Not set,Set" bitfld.long 0x28 13. " [13] ,GPIO_INT[5] status" "Not set,Set" bitfld.long 0x28 12. " [12] ,GPIO_INT[4] status" "Not set,Set" newline bitfld.long 0x28 11. " [11] ,GPIO_INT[3] status" "Not set,Set" bitfld.long 0x28 10. " [10] ,GPIO_INT[2] status" "Not set,Set" bitfld.long 0x28 9. " [9] ,GPIO_INT[1] status" "Not set,Set" bitfld.long 0x28 8. " [8] ,GPIO_INT[0] status" "Not set,Set" newline bitfld.long 0x28 3. " [3] ,PERF_CNT_INT status" "Not set,Set" bitfld.long 0x28 2. " [2] ,SBR_DONE_INT status" "Not set,Set" bitfld.long 0x28 1. " [1] ,ECC_NCORRECT_INT status" "Not set,Set" bitfld.long 0x28 0. " [0] ,ECC_CORRECT_INT status" "Not set,Set" line.long 0x2C "STATUS12,Interrupt Status 12 Register" bitfld.long 0x2C 27. " STATUS[27] ,SYS_COUNT_INT[3] status" "Not set,Set" bitfld.long 0x2C 26. " [26] ,SYS_COUNT_INT[2] status" "Not set,Set" bitfld.long 0x2C 25. " [25] ,SYS_COUNT_INT[1] status" "Not set,Set" bitfld.long 0x2C 24. " [24] ,SYS_COUNT_INT[0] status" "Not set,Set" newline bitfld.long 0x2C 23. " [23] ,INT_OUT[7] status" "Not set,Set" bitfld.long 0x2C 22. " [22] ,INT_OUT[6] status" "Not set,Set" bitfld.long 0x2C 21. " [21] ,INT_OUT[5] status" "Not set,Set" bitfld.long 0x2C 20. " [20] ,INT_OUT[4] status" "Not set,Set" newline bitfld.long 0x2C 19. " [19] ,INT_OUT[3] status" "Not set,Set" bitfld.long 0x2C 18. " [18] ,INT_OUT[2] status" "Not set,Set" bitfld.long 0x2C 17. " [17] ,INT_OUT[1] status" "Not set,Set" bitfld.long 0x2C 16. " [16] ,INT_OUT[0] status" "Not set,Set" newline bitfld.long 0x2C 15. " [15] ,PCIE9_GPIO_WAKEUP[1] status" "Not set,Set" bitfld.long 0x2C 14. " [14] ,PCIE9_GPIO_WAKEUP[0] status" "Not set,Set" bitfld.long 0x2C 13. " [13] ,PCIE0_SMLH_REQ_RST status" "Not set,Set" bitfld.long 0x2C 12. " [12] ,PCIE0_INT_A status" "Not set,Set" newline bitfld.long 0x2C 11. " [11] ,PCIE0_INT_B status" "Not set,Set" bitfld.long 0x2C 10. " [10] ,PCIE0_INT_C status" "Not set,Set" bitfld.long 0x2C 9. " [9] ,PCIE0_INT_D status" "Not set,Set" bitfld.long 0x2C 8. " [8] ,PCIE0_DMA_INT status" "Not set,Set" newline bitfld.long 0x2C 7. " [7] ,PCIE0_CLK_REQ_INT status" "Not set,Set" bitfld.long 0x2C 6. " [6] ,PCIE0_MSI_CTRL_INT status" "Not set,Set" bitfld.long 0x2C 5. " [5] ,PWM7_INT status" "Not set,Set" bitfld.long 0x2C 4. " [4] ,PWM6_INT status" "Not set,Set" newline bitfld.long 0x2C 3. " [3] ,PWM5_INT status" "Not set,Set" bitfld.long 0x2C 2. " [2] ,PWM4_INT status" "Not set,Set" bitfld.long 0x2C 1. " [1] ,PWM3_INT status" "Not set,Set" bitfld.long 0x2C 0. " [0] ,PWM2_INT status" "Not set,Set" line.long 0x30 "STATUS13,Interrupt Status 13 Register" bitfld.long 0x30 31. " STATUS[31] ,PWM1_INT status" "Not set,Set" bitfld.long 0x30 30. " [30] ,PWM0_INT status" "Not set,Set" bitfld.long 0x30 29. " [29] ,FLEXSPI1_INT status" "Not set,Set" bitfld.long 0x30 28. " [28] ,FLEXSPI0_INT status" "Not set,Set" newline bitfld.long 0x30 21. " [21] ,KPP0_INT status" "Not set,Set" bitfld.long 0x30 20. " [20] ,GPT4_INT status" "Not set,Set" bitfld.long 0x30 19. " [19] ,GPT3_INT status" "Not set,Set" bitfld.long 0x30 18. " [18] ,GPT2_INT status" "Not set,Set" newline bitfld.long 0x30 17. " [17] ,GPT1_INT status" "Not set,Set" bitfld.long 0x30 16. " [16] ,GPT0_INT status" "Not set,Set" bitfld.long 0x30 5. " [5] ,DMA3_ERR_INT status" "Not set,Set" bitfld.long 0x30 4. " [4] ,DMA3_INT status" "Not set,Set" newline bitfld.long 0x30 3. " [3] ,DMA2_ERR_INT status" "Not set,Set" bitfld.long 0x30 2. " [2] ,DMA2_INT status" "Not set,Set" bitfld.long 0x30 0. " [0] ,XAQ2_INTR status" "Not set,Set" line.long 0x34 "STATUS14,Interrupt Status 14 Register" bitfld.long 0x34 31. " STATUS[31] ,LCD_PWM_INT status" "Not set,Set" bitfld.long 0x34 30. " [30] ,LCD_MOD_INT status" "Not set,Set" bitfld.long 0x34 28. " [28] ,INT_OUT status" "Not set,Set" bitfld.long 0x34 27. " [27] ,INT_OUT status" "Not set,Set" newline bitfld.long 0x34 20. " [20] ,INT_OUT[12] status" "Not set,Set" bitfld.long 0x34 19. " [19] ,INT_OUT[11] status" "Not set,Set" bitfld.long 0x34 18. " [18] ,INT_OUT[10] status" "Not set,Set" bitfld.long 0x34 17. " [17] ,INT_OUT[9] status" "Not set,Set" newline bitfld.long 0x34 15. " [15] ,INT_OUT[7] status" "Not set,Set" bitfld.long 0x34 14. " [14] ,INT_OUT[6] status" "Not set,Set" bitfld.long 0x34 13. " [13] ,INT_OUT[5] status" "Not set,Set" bitfld.long 0x34 12. " [12] ,INT_OUT[4] status" "Not set,Set" newline bitfld.long 0x34 11. " [11] ,INT_OUT[3] status" "Not set,Set" bitfld.long 0x34 10. " [10] ,INT_OUT[2] status" "Not set,Set" bitfld.long 0x34 9. " [9] ,INT_OUT[1] status" "Not set,Set" bitfld.long 0x34 8. " [8] ,INT_OUT[0] status" "Not set,Set" line.long 0x38 "STATUS15,Interrupt Status 15 Register" bitfld.long 0x38 23. " STATUS[23] ,INT_OUT[7] status" "Not set,Set" bitfld.long 0x38 22. " [22] ,INT_OUT[6] status" "Not set,Set" bitfld.long 0x38 21. " [21] ,INT_OUT[5] status" "Not set,Set" bitfld.long 0x38 20. " [20] ,INT_OUT[4] status" "Not set,Set" newline bitfld.long 0x38 19. " [19] ,INT_OUT[3] status" "Not set,Set" bitfld.long 0x38 18. " [18] ,INT_OUT[2] status" "Not set,Set" bitfld.long 0x38 17. " [17] ,INT_OUT[1] status" "Not set,Set" bitfld.long 0x38 16. " [16] ,INT_OUT[0] status" "Not set,Set" newline bitfld.long 0x38 1. " [1] ,nEXTERRIRQ status" "Not set,Set" bitfld.long 0x38 0. " [0] ,nINTERRIRQ status" "Not set,Set" group.long 0xC4++0x03 line.long 0x00 "MINTDIS,Master Interrupt Disable Register" bitfld.long 0x00 7. " DISABLE[7] ,Disables interrupts from 511 to 448" "No,Yes" bitfld.long 0x00 6. " [6] ,Disables interrupts from 447 to 384" "No,Yes" bitfld.long 0x00 5. " [5] ,Disables interrupts from 383 to 320" "No,Yes" bitfld.long 0x00 4. " [4] ,Disables interrupts from 319 to 256" "No,Yes" newline bitfld.long 0x00 3. " [3] ,Disables interrupts from 255 to 192" "No,Yes" bitfld.long 0x00 2. " [2] ,Disables interrupts from 191 to 128" "No,Yes" bitfld.long 0x00 1. " [1] ,Disables interrupts from 127 to 64" "No,Yes" bitfld.long 0x00 0. " [0] ,Disables interrupts from 63 to 0" "No,Yes" newline rgroup.long 0xC8++0x03 line.long 0x00 "MSTRSTAT,Master Status Register" bitfld.long 0x00 0. " STATUS ,Status of all interrupts" "Not asserted,At least one interrupt is asserted" width 0x0B tree.end tree.end tree.end tree.end tree.open "MIPI DSI/LVDS 0" tree.open "MIPI_LVDS (MIPI-DSI/LVDS Controller)" tree "MIPI_LVDS_DSI_HOST" base ad:0x56228000 width 27. group.long 0x00++0x2B line.long 0x00 "CFG_NUM_LANES,MIPI DSI Host DSI Host Configuration Number Lanes" bitfld.long 0x00 0.--1. " CFG_NUM_LANES ,Number of active lanes that are to be used for transmitting data" "1 lane,2 lanes,3 lanes,4 lanes" line.long 0x04 "CFG_NONCONTINUOUS_CLK,MIPI DSI Host DSI Host Configuration Non-continuous Clock" bitfld.long 0x04 0. " CFG_NONCONTINUOUS_CLK ,Host controller into non-continuous MIPI clock mode" "Continuous,Non-continuous" line.long 0x08 "CFG_T_PRE,MIPI DSI Host DSI Host Configuration T PRE" hexmask.long.byte 0x08 0.--7. 1. " CFG_T_PRE ,Number of byte clock periods that the controller will wait after enabling the clock lane for HS operation before enabling the data lanes for HS operation" line.long 0x0C "CFG_T_POST,MIPI DSI Host DSI Host Configuration T Post" hexmask.long.byte 0x0C 0.--7. 1. " CFG_T_POST ,Number of byte clock periods to wait before putting the clock lane into LP mode after the data lanes have been detected to be in stop state" line.long 0x10 "CFG_TX_GAP,MIPI DSI Host DSI Host Configuration TX GAP" hexmask.long.byte 0x10 0.--7. 1. " CFG_TX_GAP ,Number of byte clock periods that the controller will wait after the clock lane has been put into LP mode before enabling the clock lane for HS mode again" line.long 0x14 "CFG_AUTOINSERT_EOTP,MIPI DSI Host DSI Host Configuration Autoinsert EOTP" bitfld.long 0x14 0. " CFG_AUTOINSERT_EOTP ,Enable the host controller to automatically insert an EoTp short packet when switching from HS to LP" "Not auto-inserted,Auto-inserted" line.long 0x18 "CFG_EXTRA_CMDS_AFTER_EOTP,MIPI DSI Host Controller Register" hexmask.long.byte 0x18 0.--7. 1. " CFG_EXTRA_CMDS_AFTER_EOTP ,Number of extra EOTP packets sent after the end of a packet" line.long 0x1C "CFG_HTX_TO_COUNT,MIPI DSI Host DSI Host Configuration HTX To Count" hexmask.long.tbyte 0x1C 0.--23. 1. " CFG_HTX_TO_COUNT ,Value of the DSI host high speed TX timeout count in clk_byte clock periods" line.long 0x20 "CFG_LRX_H_TO_COUNT,MIPI DSI Host DSI Host Configuration LRX H To Count" hexmask.long.tbyte 0x20 0.--23. 1. " CFG_LRX_H_TO_COUNT ,Value of the DSI host low power RX timeout count in clk_byte clock periods" line.long 0x24 "CFG_BTA_H_TO_COUNT,MIPI DSI Host DSI Host Configuration LRX H To Count" hexmask.long.tbyte 0x24 0.--23. 1. " CFG_BTA_H_TO_COUNT ,Value of the DSI host bus turn around (BTA) timeout in clk_byte clock periods" line.long 0x28 "CFG_TWAKEUP,MIPI DSI Host DSI Host Configuration TWAKEUP" hexmask.long.tbyte 0x28 0.--18. 1. " CFG_TWAKEUP ,Number of clk_esc clock periods to keep a clock or data lane in Mark-1 state after exiting ULPS" rgroup.long 0x2C++0x07 line.long 0x00 "CFG_STATUS_OUT,MIPI DSI Host DSI Host Configuration Status Out" line.long 0x04 "RX_ERROR_STATUS,MIPI DSI Host DSI Host RX Error Status" hexmask.long.word 0x04 0.--10. 1. " RX_ERROR_STATUS ,Status Register for Host receive error detection/ECC errors/CRC errors/timeout indicators" width 0x0B tree.end tree "MIPI_LVDS_DSI_HOST_DPI_INTFC" base ad:0x56228200 width 24. group.long 0x00++0x43 line.long 0x00 "PIXEL_PAYLOAD_SIZE,MIPI DSI Host DPI INTFC DSI Host Configuration DPI Pixel Payload Size" hexmask.long.word 0x00 0.--15. 1. " PIXEL_PAYLOAD_SIZE ,Maximum number of pixels that should be sent as one DSI packet" line.long 0x04 "PIXEL_FIFO_SEND_LEVEL,MIPI DSI Host DPI INTFC DSI Host Configuration DPI Pixel FIFO Send Level" hexmask.long.word 0x04 0.--15. 1. " PIXEL_FIFO_SEND_LEVEL ,In order to optimize DSI utility the DPI bridge buffers a certain number of DPI pixels before initiating a DSI packet" line.long 0x08 "INTERFACE_COLOR_CODING,MIPI DSI Host DPI INTFC DSI Host Configuration DPI Interface Color Coding" bitfld.long 0x08 0.--2. " INTERFACE_COLOR_CODING ,Distribution of RGB bits within the 24-bit d bus" "16-bit configuration 1,16-bit configuration 2,16-bit configuration 3,18-bit configuration 1,18-bit configuration 2,24-bit,?..." line.long 0x0C "PIXEL_FORMAT,MIPI DSI Host DPI INTFC DSI Host Configuration DPI Pixel Format" bitfld.long 0x0C 0.--1. " PIXEL_FORMAT ,DSI packet type of the pixels" "16-bit 1,18-bit 2,18-bit loosely packed,24-bit" line.long 0x10 "VSYNC_POLARITY,MIPI DSI Host DPI INTFC DSI Host Configuration DPI VSYNC Polarity" bitfld.long 0x10 0. " VSYNC_POLARITY ,Polarity of dpi_vsync_input" "Active low,Active high" line.long 0x14 "HSYNC_POLARITY,MIPI DSI Host DPI INTFC DSI Host Configuration DPI HSYNC Polarity" bitfld.long 0x14 0. " HSYNC_POLARITY ,Polarity of dpi_hsync_input" "Active low,Active high" line.long 0x18 "VIDEO_MODE,MIPI DSI Host DPI INTFC DSI Host Configuration DPI Video Mode" bitfld.long 0x18 0.--1. " VIDEO_MODE ,DSI video mode that the host DPI module should generate packets for" "Non-Burst with Sync Pulses,Non-Burst with Sync Events,Burst mode,?..." line.long 0x1C "HFP,MIPI DSI Host DPI INTFC DSI Host Configuration DPI HFP" hexmask.long.word 0x1C 0.--15. 1. " HFP ,DSI packet payload size" line.long 0x20 "HBP,MIPI DSI Host DPI INTFC DSI Host Configuration DPI HBP" hexmask.long.word 0x20 0.--15. 1. " HBP ,DSI packet payload size" line.long 0x24 "HSA,MIPI DSI Host DPI INTFC DSI Host Configuration DPI HSA" hexmask.long.word 0x24 0.--15. 1. " HSA ,DSI packet payload size" line.long 0x28 "ENABLE_MULT_PKTS,MIPI DSI Host DPI INTFC DSI Host Configuration DPI Enable MULT PKTS" bitfld.long 0x28 0. " ENABLE_MULT_PKTS ,Multiple packets per video line" "Single packet,Two packets" line.long 0x2C "VBP,MIPI DSI Host DPI INTFC DSI Host Configuration DPI VBP" hexmask.long.byte 0x2C 0.--7. 1. " VBP ,Number of lines in the vertical back porch" line.long 0x30 "VFP,MIPI DSI Host DPI INTFC DSI Host Configuration DPI VFP" hexmask.long.byte 0x30 0.--7. 1. " VFP ,Number of lines in the vertical front porch" line.long 0x34 "BLLP_MODE,MIPI DSI Host DPI INTF DSI Host Configuration DPI BLLP Mode" bitfld.long 0x34 0. " BLLP_MODE ,Optimize bllp periods to low power mode when possible" "Blanking packets sent during BLLP periods,LP mode used for BLLP periods" line.long 0x38 "USE_NULL_PKT_BLLP,MIPI DSI Host DPI INTFC DSI Host Configuration DPI Use Null PKT BLLP" bitfld.long 0x38 0. " USE_NULL_PKT_BLLP ,Type of blanking packet to be sent during bllp region" "Blanking packet used in BLLP region,Null packet used in BLLP region" line.long 0x3C "VACTIVE,MIPI DSI Host DPI INTFC DSI Host Configuration DPI Vactive" hexmask.long.word 0x3C 0.--13. 1. " VACTIVE ,Number of lines in the vertical active area" line.long 0x40 "VC,MIPI DSI Host DPI INTFC DSI Host Configuration DPI VC" bitfld.long 0x40 0.--1. " VC ,Virtual channel (VC) of packets that will be sent to the receive packet interface" "0,1,2,3" width 0x0B tree.end tree "MIPI_LVDS_DSI_HOST_APB" base ad:0x56228280 width 19. group.long 0x00++0x0B line.long 0x00 "TX_PAYLOAD,MIPI DSI Host APB PKT IF DSI Host TX Payload" line.long 0x04 "PKT_CONTROL,MIPI DSI Host APB PKT IF DSI Host PKT Control" hexmask.long 0x04 0.--26. 1. " PKT_CONTROL ,Tx packet control register" line.long 0x08 "SEND_PACKET,MIPI DSI Host APB PKT IF DSI Host Send Packet" bitfld.long 0x08 0. " SEND_PACKET ,Tx send packet" "Not sent,Sent" rgroup.long 0x0C++0x13 line.long 0x00 "PKT_STATUS,MIPI DSI Host APB PKT IF DSI PKT Status" hexmask.long.word 0x00 0.--8. 1. " PKT_STATUS ,Status of APB to packet interface" line.long 0x04 "PKT_FIFO_WR_LEVEL,MIPI DSI Host APB PKT IF DSI Host PKT FIFO WR Level" hexmask.long.word 0x04 0.--15. 1. " PKT_FIFO_WR_LEVEL ,Write level of APB to pkt interface FIFO" line.long 0x08 "PKT_FIFO_RD_LEVEL,MIPI DSI Host APB PKT IF DSI Host PKT FIFO RD Level" hexmask.long.word 0x08 0.--15. 1. " PKT_FIFO_RD_LEVEL ,Read level of APB to pkt interface FIFO" line.long 0x0C "PKT_RX_PAYLOAD,MIPI DSI Host APB PKT IF DSI Host PKT RX Payload" line.long 0x10 "PKT_RX_PKT_HEADER,MIPI DSI Host APB PKT IF DSI Host PKT RX PKT Header" hexmask.long.tbyte 0x10 0.--23. 1. " PKT_RX_PKT_HEADER ,APB to pkt interface rx packet header" rgroup.long 0x20++0x07 line.long 0x00 "IRQ_STATUS,MIPI DSI Host APB PKT IF DSI Host Interrupt Status" line.long 0x04 "IRQ_STATUS2,MIPI DSI Host APB PKT IF DSI Host Interrupt Status 2" bitfld.long 0x04 0.--2. " IRQ_STATUS2 ,Status of APB to packet interface part 2" "Single bit ECC error,Multi bit ECC error,CRC error,?..." group.long 0x28++0x07 line.long 0x00 "IRQ_MASK,MIPI DSI Host APB PKT IF DSI Host Interrupt Mask" bitfld.long 0x00 31. " MASK[31:0] ,IRQ_STATUS bit 31 mask" "0,1" bitfld.long 0x00 30. ",IRQ_STATUS bit 30 mask" "0,1" bitfld.long 0x00 29. ",IRQ_STATUS bit 29 mask" "0,1" bitfld.long 0x00 28. ",IRQ_STATUS bit 28 mask" "0,1" bitfld.long 0x00 27. ",IRQ_STATUS bit 27 mask" "0,1" bitfld.long 0x00 26. ",IRQ_STATUS bit 26 mask" "0,1" bitfld.long 0x00 25. ",IRQ_STATUS bit 25 mask" "0,1" bitfld.long 0x00 24. ",IRQ_STATUS bit 24 mask" "0,1" bitfld.long 0x00 23. ",IRQ_STATUS bit 23 mask" "0,1" bitfld.long 0x00 22. ",IRQ_STATUS bit 22 mask" "0,1" bitfld.long 0x00 21. ",IRQ_STATUS bit 21 mask" "0,1" bitfld.long 0x00 20. ",IRQ_STATUS bit 20 mask" "0,1" bitfld.long 0x00 19. ",IRQ_STATUS bit 19 mask" "0,1" bitfld.long 0x00 18. ",IRQ_STATUS bit 18 mask" "0,1" bitfld.long 0x00 17. ",IRQ_STATUS bit 17 mask" "0,1" bitfld.long 0x00 16. ",IRQ_STATUS bit 16 mask" "0,1" bitfld.long 0x00 15. ",IRQ_STATUS bit 15 mask" "0,1" bitfld.long 0x00 14. ",IRQ_STATUS bit 14 mask" "0,1" bitfld.long 0x00 13. ",IRQ_STATUS bit 13 mask" "0,1" bitfld.long 0x00 12. ",IRQ_STATUS bit 12 mask" "0,1" bitfld.long 0x00 11. ",IRQ_STATUS bit 11 mask" "0,1" bitfld.long 0x00 10. ",IRQ_STATUS bit 10 mask" "0,1" bitfld.long 0x00 9. ",IRQ_STATUS bit 9 mask" "0,1" bitfld.long 0x00 8. ",IRQ_STATUS bit 8 mask" "0,1" bitfld.long 0x00 7. ",IRQ_STATUS bit 7 mask" "0,1" bitfld.long 0x00 6. ",IRQ_STATUS bit 6 mask" "0,1" bitfld.long 0x00 5. ",IRQ_STATUS bit 5 mask" "0,1" bitfld.long 0x00 4. ",IRQ_STATUS bit 4 mask" "0,1" bitfld.long 0x00 3. ",IRQ_STATUS bit 3 mask" "0,1" bitfld.long 0x00 2. ",IRQ_STATUS bit 2 mask" "0,1" bitfld.long 0x00 1. ",IRQ_STATUS bit 1 mask" "0,1" bitfld.long 0x00 0. ",IRQ_STATUS bit 0 mask" "0,1" line.long 0x04 "IRQ_MASK2,MIPI DSI Host APB PKT IF DSI Host Interrupt Mask 2" bitfld.long 0x04 2. " MASK[2:0] ,IRQ_STATUS2 bit 2 mask" "0,1" bitfld.long 0x04 1. ",IRQ_STATUS2 bit 1 mask" "0,1" bitfld.long 0x04 0. ",IRQ_STATUS2 bit 0 mask" "0,1" width 0x0B tree.end tree "MIPI_LVDS_DSI_HOST_NXP_FDSOI28_DPHY_INTFC" base ad:0x56228300 width 19. group.long 0x00++0x2F line.long 0x00 "PD_TX,DPHY PD_TX Input Control Register" bitfld.long 0x00 0. " PD_TX ,DPHY PD_TX input control" "0,1" line.long 0x04 "M_PRG_HS_PREPARE,DPHY M_PRG_HS_PREPARE Input Register" bitfld.long 0x04 0.--1. " M_PRG_HS_PREPARE ,DPHY M_PRG_HS_PREPARE input" "0,1,2,3" line.long 0x08 "MC_PRG_HS_PREPARE,DPHY MC_PRG_HS_PREPARE Input Register" bitfld.long 0x08 0. " MC_PRG_HS_PREPARE ,DPHY MC_PRG_HS_PREPARE input" "0,1" line.long 0x0C "M_PRG_HS_ZERO,DPHY M_PRG_HS_ZERO Input Register" bitfld.long 0x0C 0.--4. " M_PRG_HS_ZERO ,DPHY M_PRG_HS_ZERO input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "MC_PRG_HS_ZERO,DPHY MC_PRG_HS_ZERO Input Register" bitfld.long 0x10 0.--5. " MC_PRG_HS_ZERO ,DPHY MC_PRG_HS_ZERO input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x14 "M_PRG_HS_TRAIL,DPHY M_PRG_HS_TRAL Input Register" bitfld.long 0x14 0.--3. " M_PRG_HS_TRAIL ,DPHY M_PRG_HS_TRAIL input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "MC_PRG_HS_TRAIL,DPHY MC_PRG_HS_TRAL Input Register" bitfld.long 0x18 0.--3. " M_PRG_HS_TRAIL ,DPHY M_PRG_HS_TRAIL input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x1C "PD_PLL,DPHY PD_PLL Input Register" bitfld.long 0x1C 0. " PD_PLL ,DPHY PD_PLL input" "0,1" line.long 0x20 "TST,DPHY TST Input Register" bitfld.long 0x20 0.--5. " TST ,DPHY TST input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x24 "CN,DPHY CN Input Register" bitfld.long 0x24 0.--4. " CN ,DPHY CN input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x28 "CM,DPHY CM Input Register" hexmask.long.byte 0x28 0.--7. 1. " CM ,DPHY CM input" line.long 0x2C "CO,DPHY CO Input Register" bitfld.long 0x2C 0.--1. " CO ,DPHY CO input" "0,1,2,3" rgroup.long 0x30++0x03 line.long 0x00 "LOCK,DPHY PLL LOCK Output Register" bitfld.long 0x00 0. " LOCK ,DPHY PLL LOCK output" "Unlocked,Locked" group.long 0x34++0x13 line.long 0x00 "LOCK_BYP,DPHY LOCK_BYP Input Register" bitfld.long 0x00 0. " LOCK_BYP ,DPHY LOCK_BYP input" "Unlocked,Locked" line.long 0x04 "TX_RCAL,DPHY RTERM_SEL Input Register" bitfld.long 0x04 0.--1. " TX_RCAL ,DPHY RTERM_SEL input" "0,1,2,3" line.long 0x08 "AUTO_PD_EN,DPHY AUTO_PD_EN Input Register" bitfld.long 0x08 0. " AUTO_PD_EN ,DPHY AUTO_PD_EN input" "Disabled,Enabled" line.long 0x0C "RXLPRP,DPHY RXLPRP Input Register" bitfld.long 0x0C 0.--1. " RXLPRP ,DPHY RXLPRP input" "0,1,2,3" line.long 0x10 "RXCDRP,DPHY RXCDRP Input Register" bitfld.long 0x10 0.--1. " RXCDRP ,DPHY RXCDRP input" "0,1,2,3" width 0x0B tree.end tree.end tree "I2C0 (I2C Controller)" base ad:0x56226000 width 8. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number" line.long 0x04 "PARAM,Parameter Register" bitfld.long 0x04 8.--11. " MRXFIFO ,Master receive FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x04 0.--3. " MTXFIFO ,Master transmit FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" group.long 0x10++0x13 line.long 0x00 "MCR,Master Control Register" bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset" bitfld.long 0x00 3. " DBGEN ,Debug enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " MEN ,Master enable" "Disabled,Enabled" line.long 0x04 "MSR,Master Status Register" rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x04 24. " MBF ,Master busy flag" "Idle,Busy" eventfld.long 0x04 14. " DMF ,Data match flag" "Not received,Received" eventfld.long 0x04 13. " PLTF ,Pin low timeout flag" "Not occurred/disabled,Occurred" newline eventfld.long 0x04 12. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x04 11. " ALF ,Arbitration lost flag" "Not lost,Lost" eventfld.long 0x04 10. " NDF ,NACK detect flag" "Not detected,Detected" eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected" newline eventfld.long 0x04 8. " EPF ,End packet flag" "Not generated/Repeated,Generated/Repeated" rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "MIER,Master Interrupt Enable Register" bitfld.long 0x08 14. " DMIE ,Data match interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " PLTIE ,Pin low timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " FEIE ,FIFO error interrupt disable" "No,Yes" newline bitfld.long 0x08 11. " ALIE ,Arbitration lost interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " NDIE ,NACK detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " EPIE ,End packet interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "MDER,Master DMA Enable Register" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" line.long 0x10 "MCFGR0,Master Configuration Register 0" bitfld.long 0x10 9. " RDMO ,Receive data match only" "Stored,Discarded" bitfld.long 0x10 8. " CIRFIFO ,Circular FIFO enable" "Disabled,Enabled" bitfld.long 0x10 2. " HRSEL ,Host request select" "HREQ pin,Input trigger" newline bitfld.long 0x10 1. " HRPOL ,Host request polarity" "Active low,Active high" bitfld.long 0x10 0. " HREN ,Host request enable" "Disabled,Enabled" newline if (((per.l(ad:0x56226000+0x10))&0x01)==0x01) rgroup.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Disabled,,1st word = MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "SCL,SCL or SDA" newline bitfld.long 0x00 9. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "No effect,Enabled" bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" else group.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Disabled,,1st word = MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "On SCL low too long,On SCL or SDA low too long" newline bitfld.long 0x00 9. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "No effect,Enabled" bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" endif newline if ((((per.l(ad:0x56226000+0x10))&0x01)==0x00)||(((per.l(ad:0x56226000+0x14))&0x1000000)==0x00)) group.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" else rgroup.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" endif if (((per.l(ad:0x56226000+0x10))&0x01)==0x01) rgroup.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x58++0x03 line.long 0x00 "MFCR,Master FIFO Control Register" bitfld.long 0x00 16.--17. " RXWATER ,Receive FIFO watermark" "0,1,2,3" bitfld.long 0x00 0.--1. " TXWATER ,Transmit FIFO watermark" "0,1,2,3" rgroup.long 0x5C++0x03 line.long 0x00 "MFSR,Master FIFO Status Register" bitfld.long 0x00 16.--18. " RXCOUNT ,Receive FIFO count" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " TXCOUNT ,Transmit FIFO count" "0,1,2,3,4,5,6,7" newline wgroup.long 0x60++0x03 line.long 0x00 "MTDR,Master Transmit Data Register" bitfld.long 0x00 8.--10. " CMD ,Command data" "Transmit,Receive,Generate STOP,Receive and discard,START and transmit,START and transmit (NACK returned),START and transmit (high speed mode),START and transmit high speed mode (NACK returned)" newline hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data" newline hgroup.long 0x70++0x03 hide.long 0x00 "MRDR,Master Receive Data Register" in newline group.long 0x110++0x0F line.long 0x00 "SCR,Slave Control Register" bitfld.long 0x00 9. " RRF ,Receive FIFO reset" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Transmit FIFO reset" "No effect,Reset" bitfld.long 0x00 5. " FILTDZ ,Filter doze enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " FILTEN ,Filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " SEN ,Slave enable" "Disabled,Enabled" line.long 0x04 "SSR,Slave Status Register" rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x04 24. " SBF ,Slave busy flag" "Idle,Busy" rbitfld.long 0x04 15. " SARF ,SMBus alert response flag" "Not detected,Detected" rbitfld.long 0x04 14. " GCF ,General call flag" "Not detected,Detected" newline rbitfld.long 0x04 13. " AM1F ,Address match 1 flag" "Not matched,Matched" rbitfld.long 0x04 12. " AM0F ,Address match 0 flag" "Not matched,Matched" eventfld.long 0x04 11. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x04 10. " BEF ,Bit error flag" "No error,Error" newline eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected" eventfld.long 0x04 8. " RSF ,Repeated start flag" "Not detected,Detected" rbitfld.long 0x04 3. " TAF ,Transmit ACK flag" "Not required,Required" rbitfld.long 0x04 2. " AVF ,Address valid flag" "Invalid,Valid" newline rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "SIER,Slave Interrupt Enable Register" bitfld.long 0x08 15. " SARIE ,SMBus alert response interrupt enable" "Disabled,Enabled" bitfld.long 0x08 14. " GCIE ,General call interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " AM1F ,Address match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " AM0IE ,Address match 0 interrupt disable" "No,Yes" newline bitfld.long 0x08 11. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " BEIE ,Bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 8. " RSIE ,Repeated start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " TAIE ,Transmit ACK interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " AVIE ,Address valid interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "SDER,Slave DMA Enable Register" bitfld.long 0x0C 2. " AVDE ,Address valid DMA enable" "Disabled,Enabled" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" newline if (((per.l(ad:0x56226000+0x110))&0x01)==0x01) rgroup.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration match" "0 (7-bit),0 (10-bit),0 (7-bit) / 1 (7-bit),0 (10-bit) / 1 (10-bit),0 (7-bit) / 1 (10-bit),0 (10-bit) / 1 (7-bit),From 0 (7-bit) to 1 (7-bit),From 0 (10-bit) to 1 (10-bit)" bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" bitfld.long 0x00 12. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return data / clear RDF,Return address / clear AVF" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer,On TDR empty" bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration match" "0 (7-bit),0 (10-bit),0 (7-bit) / 1 (7-bit),0 (10-bit) / 1 (10-bit),0 (7-bit) / 1 (10-bit),0 (10-bit) / 1 (7-bit),From 0 (7-bit) to 1 (7-bit),From 0 (10-bit) to 1 (10-bit)" bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" bitfld.long 0x00 12. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return data / clear RDF,Return address / clear AVF" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer,On TDR empty" bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline if (((per.l(ad:0x56226000+0x110))&0x01)==0x01) rgroup.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" else group.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" endif rgroup.long 0x150++0x03 line.long 0x00 "SASR,Slave Address Status Register" bitfld.long 0x00 14. " ANV ,Address invalid" "No,Yes" hexmask.long.word 0x00 0.--10. 0x01 " RADDR ,Received address" if (((per.l(ad:0x56226000+0x124))&0x08)==0x08) group.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,NACK transmit" "ACK,NACK" else rgroup.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,NACK transmit" "ACK,NACK" endif wgroup.long 0x160++0x03 line.long 0x00 "STDR,Slave Transmit Data Register" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data" rgroup.long 0x170++0x03 line.long 0x00 "SRDR,Slave Receive Data Register" bitfld.long 0x00 15. " SOF ,Start of frame" "Not the first data word,First data word" bitfld.long 0x00 14. " RXEMPTY ,RX empty" "Not empty,Empty" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data receive" width 0x0B tree.end tree "PWM (Pulse Width Modulation)" base ad:0x56224000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO water mark (FIFO empty flag set threshold)" ">= 1 empty slot,>= 2 empty slots,>= 3 empty slots,>= 4 empty slots" bitfld.long 0x00 25. " STOPEN ,Stop mode enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait mode enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " DBGEN ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte data swap control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word data swap control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM output configuration" "Set=rollover/Cleared=comparison,Set=comparison/Cleared=rollover,Disconnected,Disconnected" newline bitfld.long 0x00 16.--17. " CLKSRC ,Clock source select" "Off,IPG_CLK,IPG_CLK_HIGHFREQ,IPG_CLK_32K" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter clock prescaler value" bitfld.long 0x00 3. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample repeat" "Once,Twice,Four times,Eight times" newline bitfld.long 0x00 0. " EN ,PWM enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO write error status" "No error,Error" eventfld.long 0x04 5. " CMP ,Compare event status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over event status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO empty status" "Not empty,Empty" newline rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO available" "No available,1 word,2 words,3 words,4 words,?..." line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO empty interrupt enable" "Disabled,Enabled" line.long 0x0C "PWMSAR,PWM Sample Register" hexmask.long.word 0x0C 0.--15. 1. " SAMPLE ,Sample value" line.long 0x10 "PWMPR,PWM Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Period value" rgroup.long 0x14++0x03 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" width 0x0B tree.end tree "GPIO (General Purpose Input/Output)" base ad:0x56222000 width 11. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data Register" bitfld.long 0x00 31. " DR[31] ,Data bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,Data bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,Data bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,Data bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,Data bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,Data bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,Data bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,Data bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,Data bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,Data bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,Data bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,Data bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,Data bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,Data bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,Data bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,Data bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,Data bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,Data bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,Data bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,Data bit 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,Data bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,Data bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,Data bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,Data bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,Data bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,Data bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,Data bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,Data bit 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,Data bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,Data bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,Data bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,Data bit 0" "Low,High" line.long 0x04 "GDIR,GPIO Direction Register" bitfld.long 0x04 31. " GDIR[31] ,GPIO direction 31 bit" "Input,Output" bitfld.long 0x04 30. " [30] ,GPIO direction 30 bit" "Input,Output" bitfld.long 0x04 29. " [29] ,GPIO direction 29 bit" "Input,Output" bitfld.long 0x04 28. " [28] ,GPIO direction 28 bit" "Input,Output" newline bitfld.long 0x04 27. " [27] ,GPIO direction 27 bit" "Input,Output" bitfld.long 0x04 26. " [26] ,GPIO direction 26 bit" "Input,Output" bitfld.long 0x04 25. " [25] ,GPIO direction 25 bit" "Input,Output" bitfld.long 0x04 24. " [24] ,GPIO direction 24 bit" "Input,Output" newline bitfld.long 0x04 23. " [23] ,GPIO direction 23 bit" "Input,Output" bitfld.long 0x04 22. " [22] ,GPIO direction 22 bit" "Input,Output" bitfld.long 0x04 21. " [21] ,GPIO direction 21 bit" "Input,Output" bitfld.long 0x04 20. " [20] ,GPIO direction 20 bit" "Input,Output" newline bitfld.long 0x04 19. " [19] ,GPIO direction 19 bit" "Input,Output" bitfld.long 0x04 18. " [18] ,GPIO direction 18 bit" "Input,Output" bitfld.long 0x04 17. " [17] ,GPIO direction 17 bit" "Input,Output" bitfld.long 0x04 16. " [16] ,GPIO direction 16 bit" "Input,Output" newline bitfld.long 0x04 15. " [15] ,GPIO direction 15 bit" "Input,Output" bitfld.long 0x04 14. " [14] ,GPIO direction 14 bit" "Input,Output" bitfld.long 0x04 13. " [13] ,GPIO direction 13 bit" "Input,Output" bitfld.long 0x04 12. " [12] ,GPIO direction 12 bit" "Input,Output" newline bitfld.long 0x04 11. " [11] ,GPIO direction 11 bit" "Input,Output" bitfld.long 0x04 10. " [10] ,GPIO direction 10 bit" "Input,Output" bitfld.long 0x04 9. " [9] ,GPIO direction 9 bit" "Input,Output" bitfld.long 0x04 8. " [8] ,GPIO direction 8 bit" "Input,Output" newline bitfld.long 0x04 7. " [7] ,GPIO direction 7 bit" "Input,Output" bitfld.long 0x04 6. " [6] ,GPIO direction 6 bit" "Input,Output" bitfld.long 0x04 5. " [5] ,GPIO direction 5 bit" "Input,Output" bitfld.long 0x04 4. " [4] ,GPIO direction 4 bit" "Input,Output" newline bitfld.long 0x04 3. " [3] ,GPIO direction 3 bit" "Input,Output" bitfld.long 0x04 2. " [2] ,GPIO direction 2 bit" "Input,Output" bitfld.long 0x04 1. " [1] ,GPIO direction 1 bit" "Input,Output" bitfld.long 0x04 0. " [0] ,GPIO direction 0 bit" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO Pad Status Register" bitfld.long 0x00 31. " PSR[31] ,GPIO pad status bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,GPIO pad status bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,GPIO pad status bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,GPIO pad status bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,GPIO pad status bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,GPIO pad status bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,GPIO pad status bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,GPIO pad status bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,GPIO pad status bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,GPIO pad status bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,GPIO pad status bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,GPIO pad status bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,GPIO pad status bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,GPIO pad status bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,GPIO pad status bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,GPIO pad status bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,GPIO pad status bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,GPIO pad status bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,GPIO pad status bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,GPIO pad status bit 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,GPIO pad status bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,GPIO pad status bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,GPIO pad status bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,GPIO pad status bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,GPIO pad status bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,GPIO pad status bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,GPIO pad status bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,GPIO pad status bit 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,GPIO pad status bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,GPIO pad status bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,GPIO pad status bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,GPIO pad status bit 0" "Low,High" group.long 0x0C++0x13 line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1" bitfld.long 0x00 30.--31. " ICR[15] ,Controls the active condition of the interrupt function for GPIO interrupt 15" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 28.--29. " [14] ,Controls the active condition of the interrupt function for GPIO interrupt 14" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 26.--27. " [13] ,Controls the active condition of the interrupt function for GPIO interrupt 13" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 24.--25. " [12] ,Controls the active condition of the interrupt function for GPIO interrupt 12" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 22.--23. " [11] ,Controls the active condition of the interrupt function for GPIO interrupt 11" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 20.--21. " [10] ,Controls the active condition of the interrupt function for GPIO interrupt 10" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 18.--19. " [9] ,Controls the active condition of the interrupt function for GPIO interrupt 9" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 16.--17. " [8] ,Controls the active condition of the interrupt function for GPIO interrupt 8" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 14.--15. " [7] ,Controls the active condition of the interrupt function for GPIO interrupt 7" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 12.--13. " [6] ,Controls the active condition of the interrupt function for GPIO interrupt 6" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 10.--11. " [5] ,Controls the active condition of the interrupt function for GPIO interrupt 5" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 8.--9. " [4] ,Controls the active condition of the interrupt function for GPIO interrupt 4" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 6.--7. " [3] ,Controls the active condition of the interrupt function for GPIO interrupt 3" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 4.--5. " [2] ,Controls the active condition of the interrupt function for GPIO interrupt 2" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 2.--3. " [1] ,Controls the active condition of the interrupt function for GPIO interrupt 1" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 0.--1. " [0] ,Controls the active condition of the interrupt function for GPIO interrupt 0" "Low-level,High-level,Rising-edge,Falling-edge" line.long 0x04 "ICR2,GPIO Interrupt Configuration Register 2" bitfld.long 0x04 30.--31. " [31] ,Controls the active condition of the interrupt function for GPIO interrupt 31" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 28.--29. " [30] ,Controls the active condition of the interrupt function for GPIO interrupt 30" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 26.--27. " [29] ,Controls the active condition of the interrupt function for GPIO interrupt 29" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 24.--25. " [28] ,Controls the active condition of the interrupt function for GPIO interrupt 28" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 22.--23. " [27] ,Controls the active condition of the interrupt function for GPIO interrupt 27" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 20.--21. " [26] ,Controls the active condition of the interrupt function for GPIO interrupt 26" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 18.--19. " [25] ,Controls the active condition of the interrupt function for GPIO interrupt 25" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 16.--17. " [24] ,Controls the active condition of the interrupt function for GPIO interrupt 24" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 14.--15. " [23] ,Controls the active condition of the interrupt function for GPIO interrupt 23" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 12.--13. " [22] ,Controls the active condition of the interrupt function for GPIO interrupt 22" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 10.--11. " [21] ,Controls the active condition of the interrupt function for GPIO interrupt 21" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 8.--9. " [20] ,Controls the active condition of the interrupt function for GPIO interrupt 20" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 6.--7. " [19] ,Controls the active condition of the interrupt function for GPIO interrupt 19" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 4.--5. " [18] ,Controls the active condition of the interrupt function for GPIO interrupt 18" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 2.--3. " [17] ,Controls the active condition of the interrupt function for GPIO interrupt 17" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 0.--1. " [16] ,Controls the active condition of the interrupt function for GPIO interrupt 16" "Low-level,High-level,Rising-edge,Falling-edge" line.long 0x08 "IMR,GPIO Interrupt Mask Register" bitfld.long 0x08 31. " IMR[31] ,Interrupt 31 mask bit" "Disabled,Enabled" bitfld.long 0x08 30. " [30] ,Interrupt 30 mask bit" "Disabled,Enabled" bitfld.long 0x08 29. " [29] ,Interrupt 29 mask bit" "Disabled,Enabled" bitfld.long 0x08 28. " [28] ,Interrupt 28 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 27. " [27] ,Interrupt 27 mask bit" "Disabled,Enabled" bitfld.long 0x08 26. " [26] ,Interrupt 26 mask bit" "Disabled,Enabled" bitfld.long 0x08 25. " [25] ,Interrupt 25 mask bit" "Disabled,Enabled" bitfld.long 0x08 24. " [24] ,Interrupt 24 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 23. " [23] ,Interrupt 23 mask bit" "Disabled,Enabled" bitfld.long 0x08 22. " [22] ,Interrupt 22 mask bit" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Interrupt 21 mask bit" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Interrupt 20 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 19. " [19] ,Interrupt 19 mask bit" "Disabled,Enabled" bitfld.long 0x08 18. " [18] ,Interrupt 18 mask bit" "Disabled,Enabled" bitfld.long 0x08 17. " [17] ,Interrupt 17 mask bit" "Disabled,Enabled" bitfld.long 0x08 16. " [16] ,Interrupt 16 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 15. " [15] ,Interrupt 15 mask bit" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Interrupt 14 mask bit" "Disabled,Enabled" bitfld.long 0x08 13. " [13] ,Interrupt 13 mask bit" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Interrupt 12 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 11. " [11] ,Interrupt 11 mask bit" "Disabled,Enabled" bitfld.long 0x08 10. " [10] ,Interrupt 10 mask bit" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Interrupt 9 mask bit" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Interrupt 8 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Interrupt 7 mask bit" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Interrupt 6 mask bit" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Interrupt 5 mask bit" "Disabled,Enabled" bitfld.long 0x08 4. " [4] ,Interrupt 4 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 3. " [3] ,Interrupt 3 mask bit" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Interrupt 2 mask bit" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Interrupt 1 mask bit" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Interrupt 0 mask bit" "Disabled,Enabled" line.long 0x0C "ISR,GPIO Interrupt Status Register" eventfld.long 0x0C 31. " ISR[31] ,Interrupt 31 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 30. " [30] ,Interrupt 30 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 29. " [29] ,Interrupt 29 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 28. " [28] ,Interrupt 28 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 27. " [27] ,Interrupt 27 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 26. " [26] ,Interrupt 26 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 25. " [25] ,Interrupt 25 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 24. " [24] ,Interrupt 24 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 23. " [23] ,Interrupt 23 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 22. " [22] ,Interrupt 22 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 21. " [21] ,Interrupt 21 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 20. " [20] ,Interrupt 20 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 19. " [19] ,Interrupt 19 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 18. " [18] ,Interrupt 18 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 17. " [17] ,Interrupt 17 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 16. " [16] ,Interrupt 16 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 15. " [15] ,Interrupt 15 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 14. " [14] ,Interrupt 14 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 13. " [13] ,Interrupt 13 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 12. " [12] ,Interrupt 12 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 11. " [11] ,Interrupt 11 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 10. " [10] ,Interrupt 10 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 9. " [9] ,Interrupt 9 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 8. " [8] ,Interrupt 8 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 7. " [7] ,Interrupt 7 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 6. " [6] ,Interrupt 6 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 5. " [5] ,Interrupt 5 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 4. " [4] ,Interrupt 4 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 3. " [3] ,Interrupt 3 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 2. " [2] ,Interrupt 2 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 1. " [1] ,Interrupt 1 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 0. " [0] ,Interrupt 0 status bit" "No interrupt,Interrupt" line.long 0x10 "EDGE_SEL,GPIO Edge Select Register" bitfld.long 0x10 31. " GPIO_EDGE_SEL[31] ,Edge select bit 31" "31 setting,Any edge" bitfld.long 0x10 30. " [30] ,Edge select bit 30" "30 setting,Any edge" bitfld.long 0x10 29. " [29] ,Edge select bit 29" "29 setting,Any edge" bitfld.long 0x10 28. " [28] ,Edge select bit 28" "28 setting,Any edge" newline bitfld.long 0x10 27. " [27] ,Edge select bit 27" "27 setting,Any edge" bitfld.long 0x10 26. " [26] ,Edge select bit 26" "26 setting,Any edge" bitfld.long 0x10 25. " [25] ,Edge select bit 25" "25 setting,Any edge" bitfld.long 0x10 24. " [24] ,Edge select bit 24" "24 setting,Any edge" newline bitfld.long 0x10 23. " [23] ,Edge select bit 23" "23 setting,Any edge" bitfld.long 0x10 22. " [22] ,Edge select bit 22" "22 setting,Any edge" bitfld.long 0x10 21. " [21] ,Edge select bit 21" "21 setting,Any edge" bitfld.long 0x10 20. " [20] ,Edge select bit 20" "20 setting,Any edge" newline bitfld.long 0x10 19. " [19] ,Edge select bit 19" "19 setting,Any edge" bitfld.long 0x10 18. " [18] ,Edge select bit 18" "18 setting,Any edge" bitfld.long 0x10 17. " [17] ,Edge select bit 17" "17 setting,Any edge" bitfld.long 0x10 16. " [16] ,Edge select bit 16" "16 setting,Any edge" newline bitfld.long 0x10 15. " [15] ,Edge select bit 15" "15 setting,Any edge" bitfld.long 0x10 14. " [14] ,Edge select bit 14" "14 setting,Any edge" bitfld.long 0x10 13. " [13] ,Edge select bit 13" "13 setting,Any edge" bitfld.long 0x10 12. " [12] ,Edge select bit 12" "12 setting,Any edge" newline bitfld.long 0x10 11. " [11] ,Edge select bit 11" "11 setting,Any edge" bitfld.long 0x10 10. " [10] ,Edge select bit 10" "10 setting,Any edge" bitfld.long 0x10 9. " [9] ,Edge select bit 9" "9 setting,Any edge" bitfld.long 0x10 8. " [8] ,Edge select bit 8" "8 setting,Any edge" newline bitfld.long 0x10 7. " [7] ,Edge select bit 7" "7 setting,Any edge" bitfld.long 0x10 6. " [6] ,Edge select bit 6" "6 setting,Any edge" bitfld.long 0x10 5. " [5] ,Edge select bit 5" "5 setting,Any edge" bitfld.long 0x10 4. " [4] ,Edge select bit 4" "4 setting,Any edge" newline bitfld.long 0x10 3. " [3] ,Edge select bit 3" "3 setting,Any edge" bitfld.long 0x10 2. " [2] ,Edge select bit 2" "2 setting,Any edge" bitfld.long 0x10 1. " [1] ,Edge select bit 1" "1 setting,Any edge" bitfld.long 0x10 0. " [0] ,Edge select bit 0" "0 setting,Any edge" wgroup.long 0x84++0x0B line.long 0x00 "DR_SET,GPIO Data Register SET Register" bitfld.long 0x00 31. " DR_SET[31] ,Data bit 31 set" "Not set,Set" bitfld.long 0x00 30. " [30] ,Data bit 30 set" "Not set,Set" bitfld.long 0x00 29. " [29] ,Data bit 29 set" "Not set,Set" bitfld.long 0x00 28. " [28] ,Data bit 28 set" "Not set,Set" newline bitfld.long 0x00 27. " [27] ,Data bit 27 set" "Not set,Set" bitfld.long 0x00 26. " [26] ,Data bit 26 set" "Not set,Set" bitfld.long 0x00 25. " [25] ,Data bit 25 set" "Not set,Set" bitfld.long 0x00 24. " [24] ,Data bit 24 set" "Not set,Set" newline bitfld.long 0x00 23. " [23] ,Data bit 23 set" "Not set,Set" bitfld.long 0x00 22. " [22] ,Data bit 22 set" "Not set,Set" bitfld.long 0x00 21. " [21] ,Data bit 21 set" "Not set,Set" bitfld.long 0x00 20. " [20] ,Data bit 20 set" "Not set,Set" newline bitfld.long 0x00 19. " [19] ,Data bit 19 set" "Not set,Set" bitfld.long 0x00 18. " [18] ,Data bit 18 set" "Not set,Set" bitfld.long 0x00 17. " [17] ,Data bit 17 set" "Not set,Set" bitfld.long 0x00 16. " [16] ,Data bit 16 set" "Not set,Set" newline bitfld.long 0x00 15. " [15] ,Data bit 15 set" "Not set,Set" bitfld.long 0x00 14. " [14] ,Data bit 14 set" "Not set,Set" bitfld.long 0x00 13. " [13] ,Data bit 13 set" "Not set,Set" bitfld.long 0x00 12. " [12] ,Data bit 12 set" "Not set,Set" newline bitfld.long 0x00 11. " [11] ,Data bit 11 set" "Not set,Set" bitfld.long 0x00 10. " [10] ,Data bit 10 set" "Not set,Set" bitfld.long 0x00 9. " [9] ,Data bit 9 set" "Not set,Set" bitfld.long 0x00 8. " [8] ,Data bit 8 set" "Not set,Set" newline bitfld.long 0x00 7. " [7] ,Data bit 7 set" "Not set,Set" bitfld.long 0x00 6. " [6] ,Data bit 6 set" "Not set,Set" bitfld.long 0x00 5. " [5] ,Data bit 5 set" "Not set,Set" bitfld.long 0x00 4. " [4] ,Data bit 4 set" "Not set,Set" newline bitfld.long 0x00 3. " [3] ,Data bit 3 set" "Not set,Set" bitfld.long 0x00 2. " [2] ,Data bit 2 set" "Not set,Set" bitfld.long 0x00 1. " [1] ,Data bit 1 set" "Not set,Set" bitfld.long 0x00 0. " [0] ,Data bit 0 set" "Not set,Set" line.long 0x04 "DR_CLEAR,GPIO Data Register CLEAR Register" bitfld.long 0x04 31. " DR_CLEAR[31] ,Data bit 31 clear" "No effect,Clear" bitfld.long 0x04 30. " [30] ,Data bit 30 clear" "No effect,Clear" bitfld.long 0x04 29. " [29] ,Data bit 29 clear" "No effect,Clear" bitfld.long 0x04 28. " [28] ,Data bit 28 clear" "No effect,Clear" newline bitfld.long 0x04 27. " [27] ,Data bit 27 clear" "No effect,Clear" bitfld.long 0x04 26. " [26] ,Data bit 26 clear" "No effect,Clear" bitfld.long 0x04 25. " [25] ,Data bit 25 clear" "No effect,Clear" bitfld.long 0x04 24. " [24] ,Data bit 24 clear" "No effect,Clear" newline bitfld.long 0x04 23. " [23] ,Data bit 23 clear" "No effect,Clear" bitfld.long 0x04 22. " [22] ,Data bit 22 clear" "No effect,Clear" bitfld.long 0x04 21. " [21] ,Data bit 21 clear" "No effect,Clear" bitfld.long 0x04 20. " [20] ,Data bit 20 clear" "No effect,Clear" newline bitfld.long 0x04 19. " [19] ,Data bit 19 clear" "No effect,Clear" bitfld.long 0x04 18. " [18] ,Data bit 18 clear" "No effect,Clear" bitfld.long 0x04 17. " [17] ,Data bit 17 clear" "No effect,Clear" bitfld.long 0x04 16. " [16] ,Data bit 16 clear" "No effect,Clear" newline bitfld.long 0x04 15. " [15] ,Data bit 15 clear" "No effect,Clear" bitfld.long 0x04 14. " [14] ,Data bit 14 clear" "No effect,Clear" bitfld.long 0x04 13. " [13] ,Data bit 13 clear" "No effect,Clear" bitfld.long 0x04 12. " [12] ,Data bit 12 clear" "No effect,Clear" newline bitfld.long 0x04 11. " [11] ,Data bit 11 clear" "No effect,Clear" bitfld.long 0x04 10. " [10] ,Data bit 10 clear" "No effect,Clear" bitfld.long 0x04 9. " [9] ,Data bit 9 clear" "No effect,Clear" bitfld.long 0x04 8. " [8] ,Data bit 8 clear" "No effect,Clear" newline bitfld.long 0x04 7. " [7] ,Data bit 7 clear" "No effect,Clear" bitfld.long 0x04 6. " [6] ,Data bit 6 clear" "No effect,Clear" bitfld.long 0x04 5. " [5] ,Data bit 5 clear" "No effect,Clear" bitfld.long 0x04 4. " [4] ,Data bit 4 clear" "No effect,Clear" newline bitfld.long 0x04 3. " [3] ,Data bit 3 clear" "No effect,Clear" bitfld.long 0x04 2. " [2] ,Data bit 2 clear" "No effect,Clear" bitfld.long 0x04 1. " [1] ,Data bit 1 clear" "No effect,Clear" bitfld.long 0x04 0. " [0] ,Data bit 0 clear" "No effect,Clear" line.long 0x08 "DR_TOGGLE,GPIO Data Register TOGGLE Register" bitfld.long 0x08 31. " DR_TOGGLE[31] ,Data bit 31 toggle" "Not toggled,Toggled" bitfld.long 0x08 30. " [30] ,Data bit 30 toggle" "No effect,Clear" bitfld.long 0x08 29. " [29] ,Data bit 29 toggle" "Not toggled,Toggled" bitfld.long 0x08 28. " [28] ,Data bit 28 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 27. " [27] ,Data bit 27 toggle" "Not toggled,Toggled" bitfld.long 0x08 26. " [26] ,Data bit 26 toggle" "Not toggled,Toggled" bitfld.long 0x08 25. " [25] ,Data bit 25 toggle" "Not toggled,Toggled" bitfld.long 0x08 24. " [24] ,Data bit 24 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 23. " [23] ,Data bit 23 toggle" "Not toggled,Toggled" bitfld.long 0x08 22. " [22] ,Data bit 22 toggle" "Not toggled,Toggled" bitfld.long 0x08 21. " [21] ,Data bit 21 toggle" "Not toggled,Toggled" bitfld.long 0x08 20. " [20] ,Data bit 20 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 19. " [19] ,Data bit 19 toggle" "Not toggled,Toggled" bitfld.long 0x08 18. " [18] ,Data bit 18 toggle" "Not toggled,Toggled" bitfld.long 0x08 17. " [17] ,Data bit 17 toggle" "Not toggled,Toggled" bitfld.long 0x08 16. " [16] ,Data bit 16 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 15. " [15] ,Data bit 15 toggle" "Not toggled,Toggled" bitfld.long 0x08 14. " [14] ,Data bit 14 toggle" "Not toggled,Toggled" bitfld.long 0x08 13. " [13] ,Data bit 13 toggle" "Not toggled,Toggled" bitfld.long 0x08 12. " [12] ,Data bit 12 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 11. " [11] ,Data bit 11 toggle" "Not toggled,Toggled" bitfld.long 0x08 10. " [10] ,Data bit 10 toggle" "Not toggled,Toggled" bitfld.long 0x08 9. " [9] ,Data bit 9 toggle" "Not toggled,Toggled" bitfld.long 0x08 8. " [8] ,Data bit 8 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 7. " [7] ,Data bit 7 toggle" "Not toggled,Toggled" bitfld.long 0x08 6. " [6] ,Data bit 6 toggle" "Not toggled,Toggled" bitfld.long 0x08 5. " [5] ,Data bit 5 toggle" "Not toggled,Toggled" bitfld.long 0x08 4. " [4] ,Data bit 4 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 3. " [3] ,Data bit 3 toggle" "Not toggled,Toggled" bitfld.long 0x08 2. " [2] ,Data bit 2 toggle" "Not toggled,Toggled" bitfld.long 0x08 1. " [1] ,Data bit 1 toggle" "Not toggled,Toggled" bitfld.long 0x08 0. " [0] ,Data bit 0 toggle" "Not toggled,Toggled" width 0x0B tree.end tree "CSR (MIPI-DSI/LVDS Control and Status Registers)" base ad:0x56221000 width 15. group.long 0x00++0x03 line.long 0x00 "LVDS_PHY_CTRL,PHY In LVDS Mode Control Register" bitfld.long 0x00 5.--7. " CCM ,Common mode voltage" ",,,,Default,?..." bitfld.long 0x00 2.--4. " CA ,Driver output current" ",,,,Default,?..." bitfld.long 0x00 1. " RFB ,Rising / falling edge clock selection" "Falling,Rising" bitfld.long 0x00 0. " LVDS_EN ,LVDS TX enable" "Disabled,Enabled" group.long 0x20++0x03 line.long 0x00 "SS_CRTL,SS Control Register" bitfld.long 0x00 3. " CH1_VSYNC_POL ,Channel 1 VSYNC polarity control" "Low active,High active" bitfld.long 0x00 2. " CH1_HSYNC_POL ,channel 1 HSYNC polarity control" "Low active,High active" bitfld.long 0x00 1. " CH0_VSYNC_POL ,Channel 0 VSYNC polarity control" "Low active,High active" bitfld.long 0x00 0. " CH0_HSYNC_POL ,channel 0 HSYNC polarity control" "Low active,High active" group.long 0x30++0x03 line.long 0x00 "ULPS_CTRL,ULPS Control Register" bitfld.long 0x00 0.--4. " TX_ULPS ,Low power control of DSI lanes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x40++0x03 line.long 0x00 "PXL2DPI_CTRL,PXL2DPI Control Register" bitfld.long 0x00 0.--2. " PXL2DPI ,DPI color depth and configuration" "16-bit/Configuration 1,16-bit/Configuration 2,16-bit/Configuration 3,18-bit/Configuration 1,18-bit/Configuration 2,24-bit,?..." group.long 0xE0++0x03 line.long 0x00 "PM_CTRL,Pixel Mapper Control Register" bitfld.long 0x00 28. " CH_SEL ,Channel select" "Channel 0,Channel 1" bitfld.long 0x00 10. " DI1_VS_POLARITY ,Vsync polarity for DI1 interface" "Low active,High active" bitfld.long 0x00 9. " DI0_VS_POLARITY ,Vsync polarity for DI0 interface" "Low active,High active" bitfld.long 0x00 8. " CH1_BIT_MAPPING ,Data mapping to LVDS channel 1" "SPWG,JEIDA" newline bitfld.long 0x00 7. " CH1_DATA_WIDTH ,Data width for LVDS channel 1" "18-bit,24-bit" bitfld.long 0x00 6. " CH0_BIT_MAPPING ,Data mapping to LVDS channel 0" "SPWG,JEIDA" bitfld.long 0x00 5. " CH0_DATA_WIDTH ,Data width for LVDS channel 0" "18-bit,24-bit" bitfld.long 0x00 4. " SPLIT_MODE_EN ,Enable split mode" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " CH1_MODE ,LVDS Channel 1 operation mode" "Disabled,Enabled/DI0,Disabled,Enabled/DI1" bitfld.long 0x00 0.--1. " CH0_MODE ,LVDS Channel 0 operation mode" "Disabled,Enabled/DI0,Disabled,Enabled/DI1" width 0x0B tree.end tree.open "Local Interrupt Steer" tree "Channel 0" base ad:0x56220000 width 10. group.long 0x00++0x03 line.long 0x00 "CHAN0CTL,Channel 0 Control Register" bitfld.long 0x00 4. " CH4 ,Channel 4 control" "Disabled,Enabled" bitfld.long 0x00 3. " CH3 ,Channel 3 control" "Disabled,Enabled" bitfld.long 0x00 2. " CH2 ,Channel 2 control" "Disabled,Enabled" bitfld.long 0x00 1. " CH1 ,Channel 1 control" "Disabled,Enabled" newline bitfld.long 0x00 0. " CH0 ,Channel 0 control" "Disabled,Enabled" group.long 0x08++0x3B line.long 0x00 "MASK1,Interrupt Mask 1 Register" bitfld.long 0x00 22. " MASKFLD[22] ,Mask for VPU_INT_6" "Masked,Unmasked" bitfld.long 0x00 21. " [21] ,Mask for VPU_INT_5" "Masked,Unmasked" bitfld.long 0x00 20. " [20] ,Mask for VPU_INT_4" "Masked,Unmasked" bitfld.long 0x00 19. " [19] ,Mask for VPU_INT_3" "Masked,Unmasked" newline bitfld.long 0x00 18. " [18] ,Mask for VPU_INT_2" "Masked,Unmasked" bitfld.long 0x00 17. " [17] ,Mask for VPU_INT_1" "Masked,Unmasked" bitfld.long 0x00 16. " [16] ,Mask for VPU_INT_0" "Masked,Unmasked" bitfld.long 0x00 11. " [11] ,Mask for SPDIF0_TX_DMA_INT" "Masked,Unmasked" newline bitfld.long 0x00 10. " [10] ,Mask for SPDIF0_TX_MOD_INT" "Masked,Unmasked" bitfld.long 0x00 9. " [9] ,Mask for SPDIF0_RX_DMA_INT" "Masked,Unmasked" bitfld.long 0x00 8. " [8] ,Mask for SPDIF0_RX_MOD_INT" "Masked,Unmasked" bitfld.long 0x00 7. " [7] ,Mask for CAAM_RTIC_INT" "Masked,Unmasked" newline bitfld.long 0x00 6. " [6] ,Mask for CAAM_INT3" "Masked,Unmasked" bitfld.long 0x00 5. " [5] ,Mask for CAAM_INT2" "Masked,Unmasked" bitfld.long 0x00 4. " [4] ,Mask for CAAM_INT1" "Masked,Unmasked" bitfld.long 0x00 3. " [3] ,Mask for CAAM_INT0" "Masked,Unmasked" newline bitfld.long 0x00 2. " [2] ,Mask for SEC_MU3_A_INT" "Masked,Unmasked" bitfld.long 0x00 1. " [1] ,Mask for SEC_MU2_A_INT" "Masked,Unmasked" bitfld.long 0x00 0. " [0] ,Mask for SEC_MU1_A_INT" "Masked,Unmasked" line.long 0x04 "MASK2,Interrupt Mask 2 Register" bitfld.long 0x04 25. " MASKFLD[25] ,Mask for UART3_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 24. " [24] ,Mask for UART3_DMA_RX_INT" "Masked,Unmasked" bitfld.long 0x04 23. " [23] ,Mask for UART2_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 22. " [22] ,Mask for UART2_DMA_RX_INT" "Masked,Unmasked" newline bitfld.long 0x04 21. " [21] ,Mask for UART1_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 20. " [20] ,Mask for UART1_DMA_RX_INT" "Masked,Unmasked" bitfld.long 0x04 19. " [19] ,Mask for UART0_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 18. " [18] ,Mask for UART0_DMA_RX_INT" "Masked,Unmasked" newline bitfld.long 0x04 15. " [15] ,Mask for I2C3_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 14. " [14] ,Mask for I2C3_DMA_RX_INT" "Masked,Unmasked" bitfld.long 0x04 13. " [13] ,Mask for I2C2_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 12. " [12] ,Mask for I2C2_DMA_RX_INT" "Masked,Unmasked" newline bitfld.long 0x04 11. " [11] ,Mask for I2C1_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 10. " [10] ,Mask for I2C1_DMA_RX_INT" "Masked,Unmasked" bitfld.long 0x04 9. " [9] ,Mask for I2C0_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 8. " [8] ,Mask for I2C0_DMA_RX_INT" "Masked,Unmasked" newline bitfld.long 0x04 7. " [7] ,Mask for SPI3_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 6. " [6] ,Mask for SPI3_DMA_RX_INT" "Masked,Unmasked" bitfld.long 0x04 5. " [5] ,Mask for SPI2_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 4. " [4] ,Mask for SPI2_DMA_RX_INT" "Masked,Unmasked" newline bitfld.long 0x04 3. " [3] ,Mask for SPI1_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 2. " [2] ,Mask for SPI1_DMA_RX_INT" "Masked,Unmasked" bitfld.long 0x04 1. " [1] ,Mask for SPI0_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 0. " [0] ,Mask for SPI0_DMA_RX_INT" "Masked,Unmasked" line.long 0x08 "MASK3,Interrupt Mask 3 Register" bitfld.long 0x08 26. " MASKFLD[26] ,Mask for ESAI0_DMA_INT" "Masked,Unmasked" bitfld.long 0x08 25. " [25] ,Mask for ESAI0_MOD_INT" "Masked,Unmasked" bitfld.long 0x08 22. " [22] ,Mask for SPDIF0_TX_INT" "Masked,Unmasked" bitfld.long 0x08 21. " [21] ,Mask for SPDIF0_RX_INT" "Masked,Unmasked" newline bitfld.long 0x08 20. " [20] ,Mask for SAI5_INT" "Masked,Unmasked" bitfld.long 0x08 19. " [19] ,Mask for SAI4_INT" "Masked,Unmasked" bitfld.long 0x08 16. " [16] ,Mask for SAI3_INT" "Masked,Unmasked" bitfld.long 0x08 15. " [15] ,Mask for SAI2_INT" "Masked,Unmasked" newline bitfld.long 0x08 14. " [14] ,Mask for SAI1_INT" "Masked,Unmasked" bitfld.long 0x08 13. " [13] ,Mask for SAI0_INT" "Masked,Unmasked" bitfld.long 0x08 12. " [12] ,Mask for GPT5_INT" "Masked,Unmasked" bitfld.long 0x08 11. " [11] ,Mask for GPT4_INT" "Masked,Unmasked" newline bitfld.long 0x08 10. " [10] ,Mask for GPT3_INT" "Masked,Unmasked" bitfld.long 0x08 9. " [9] ,Mask for GPT2_INT" "Masked,Unmasked" bitfld.long 0x08 8. " [8] ,Mask for GPT1_INT" "Masked,Unmasked" bitfld.long 0x08 7. " [7] ,Mask for GPT0_INT" "Masked,Unmasked" newline bitfld.long 0x08 4. " [4] ,Mask for ESAI0_INT" "Masked,Unmasked" bitfld.long 0x08 3. " [3] ,Mask for DMA1_CH5_INT" "Masked,Unmasked" bitfld.long 0x08 2. " [2] ,Mask for DMA1_CH4_INT" "Masked,Unmasked" bitfld.long 0x08 1. " [1] ,Mask for DMA1_CH3_INT" "Masked,Unmasked" newline bitfld.long 0x08 0. " [0] ,Mask for DMA1_CH2_INT" "Masked,Unmasked" line.long 0x0C "MASK4,Interrupt Mask 4 Register" bitfld.long 0x0C 31. " MASKFLD[31] ,Mask for DMA1_CH1_INT" "Masked,Unmasked" bitfld.long 0x0C 30. " [30] ,Mask for DMA1_CH0_INT" "Masked,Unmasked" bitfld.long 0x0C 29. " [29] ,Mask for ASRC1_INT2" "Masked,Unmasked" bitfld.long 0x0C 28. " [28] ,Mask for ASRC1_INT1" "Masked,Unmasked" newline bitfld.long 0x0C 27. " [27] ,Mask for DMA0_CH5_INT" "Masked,Unmasked" bitfld.long 0x0C 26. " [26] ,Mask for DMA0_CH4_INT" "Masked,Unmasked" bitfld.long 0x0C 25. " [25] ,Mask for DMA0_CH3_INT" "Masked,Unmasked" bitfld.long 0x0C 24. " [24] ,Mask for DMA0_CH2_INT" "Masked,Unmasked" newline bitfld.long 0x0C 23. " [23] ,Mask for DMA0_CH1_INT" "Masked,Unmasked" bitfld.long 0x0C 22. " [22] ,Mask for DMA0_CH0_INT" "Masked,Unmasked" bitfld.long 0x0C 21. " [21] ,Mask for ASRC0_INT2" "Masked,Unmasked" bitfld.long 0x0C 20. " [20] ,Mask for ASRC0_INT1" "Masked,Unmasked" newline bitfld.long 0x0C 19. " [19] ,Mask for DMA1_ERR_INT" "Masked,Unmasked" bitfld.long 0x0C 18. " [18] ,Mask for DMA1_INT" "Masked,Unmasked" bitfld.long 0x0C 17. " [17] ,Mask for DMA0_ERR_INT" "Masked,Unmasked" bitfld.long 0x0C 16. " [16] ,Mask for DMA0_INT" "Masked,Unmasked" newline bitfld.long 0x0C 12. " [12] ,Mask for ADC_DMA_INT" "Masked,Unmasked" bitfld.long 0x0C 11. " [11] ,Mask for FTM1_DMA_INT" "Masked,Unmasked" bitfld.long 0x0C 10. " [10] ,Mask for FTM_DMA_INT" "Masked,Unmasked" bitfld.long 0x0C 9. " [9] ,Mask for FLEXCAN2_DMA_INT" "Masked,Unmasked" newline bitfld.long 0x0C 8. " [8] ,Mask for FLEXCAN1_DMA_INT" "Masked,Unmasked" bitfld.long 0x0C 7. " [7] ,Mask for FLEXCAN0_DMA_INT" "Masked,Unmasked" bitfld.long 0x0C 5. " [5] ,Mask for ADC_MOD_INT" "Masked,Unmasked" bitfld.long 0x0C 4. " [4] ,Mask for FTM1_MOD_INT" "Masked,Unmasked" newline bitfld.long 0x0C 3. " [3] ,Mask for FTM_MOD_INT" "Masked,Unmasked" bitfld.long 0x0C 2. " [2] ,Mask for FLEXCAN2_MOD_INT" "Masked,Unmasked" bitfld.long 0x0C 1. " [1] ,Mask for FLEXCAN1_MOD_INT" "Masked,Unmasked" bitfld.long 0x0C 0. " [0] ,Mask for FLEXCAN0_MOD_INT" "Masked,Unmasked" line.long 0x10 "MASK5,Interrupt Mask 5 Register" bitfld.long 0x10 28. " MASKFLD[28] ,Mask for UART3_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 27. " [27] ,Mask for UART2_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 26. " [26] ,Mask for UART1_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 25. " [25] ,Mask for UART0_MOD_INT" "Masked,Unmasked" newline bitfld.long 0x10 23. " [23] ,Mask for I2C3_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 22. " [22] ,Mask for I2C2_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 21. " [21] ,Mask for I2C1_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 20. " [20] ,Mask for I2C0_MOD_INT" "Masked,Unmasked" newline bitfld.long 0x10 19. " [19] ,Mask for SPI3_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 18. " [18] ,Mask for SPI2_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 17. " [17] ,Mask for SPI1_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 16. " [16] ,Mask for SPI0_MOD_INT" "Masked,Unmasked" newline bitfld.long 0x10 12. " [12] ,Mask for SAI5_DMA_INT" "Masked,Unmasked" bitfld.long 0x10 11. " [11] ,Mask for SAI5_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 10. " [10] ,Mask for SAI4_DMA_INT" "Masked,Unmasked" bitfld.long 0x10 9. " [9] ,Mask for SAI4_MOD_INT" "Masked,Unmasked" newline bitfld.long 0x10 4. " [4] ,Mask for SAI3_DMA_INT" "Masked,Unmasked" bitfld.long 0x10 3. " [3] ,Mask for SAI3_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 0. " [0] ,Mask for INT_OUT" "Masked,Unmasked" line.long 0x14 "MASK6,Interrupt Mask 6 Register" bitfld.long 0x14 31. " MASKFLD[31] ,Mask for SAI2_DMA_INT" "Masked,Unmasked" bitfld.long 0x14 30. " [30] ,Mask for SAI2_MOD_INT" "Masked,Unmasked" bitfld.long 0x14 29. " [29] ,Mask for SAI1_DMA_INT" "Masked,Unmasked" bitfld.long 0x14 28. " [28] ,Mask for SAI1_MOD_INT" "Masked,Unmasked" newline bitfld.long 0x14 27. " [27] ,Mask for SAI0_DMA_INT" "Masked,Unmasked" bitfld.long 0x14 26. " [26] ,Mask for SAI0_MOD_INT" "Masked,Unmasked" bitfld.long 0x14 24. " [24] ,Mask for MJPEG_DEC3_INT" "Masked,Unmasked" bitfld.long 0x14 23. " [23] ,Mask for MJPEG_DEC2_INT" "Masked,Unmasked" newline bitfld.long 0x14 22. " [22] ,Mask for MJPEG_DEC1_INT" "Masked,Unmasked" bitfld.long 0x14 21. " [21] ,Mask for MJPEG_DEC0_INT" "Masked,Unmasked" bitfld.long 0x14 20. " [20] ,Mask for MJPEG_ENC3_INT" "Masked,Unmasked" bitfld.long 0x14 19. " [19] ,Mask for MJPEG_ENC2_INT" "Masked,Unmasked" newline bitfld.long 0x14 18. " [18] ,Mask for MJPEG_ENC1_INT" "Masked,Unmasked" bitfld.long 0x14 17. " [17] ,Mask for MJPEG_ENC0_INT" "Masked,Unmasked" bitfld.long 0x14 16. " [16] ,Mask for PDMA_STREAM7_INT" "Masked,Unmasked" bitfld.long 0x14 15. " [15] ,Mask for PDMA_STREAM6_INT" "Masked,Unmasked" newline bitfld.long 0x14 14. " [14] ,Mask for PDMA_STREAM5_INT" "Masked,Unmasked" bitfld.long 0x14 13. " [13] ,Mask for PDMA_STREAM4_INT" "Masked,Unmasked" bitfld.long 0x14 12. " [12] ,Mask for PDMA_STREAM3_INT" "Masked,Unmasked" bitfld.long 0x14 11. " [11] ,Mask for PDMA_STREAM2_INT" "Masked,Unmasked" newline bitfld.long 0x14 10. " [10] ,Mask for PDMA_STREAM1_INT" "Masked,Unmasked" bitfld.long 0x14 9. " [9] ,Mask for PDMA_STREAM0_INT" "Masked,Unmasked" bitfld.long 0x14 0. " [0] ,Mask for MSI_INT" "Masked,Unmasked" line.long 0x18 "MASK7,Interrupt Mask 7 Register" bitfld.long 0x18 20. " MASKFLD[20] ,Mask for DMA_ERR_INT" "Masked,Unmasked" bitfld.long 0x18 19. " [19] ,Mask for DMA_INT" "Masked,Unmasked" bitfld.long 0x18 18. " [18] ,Mask for APBHDMA" "Masked,Unmasked" bitfld.long 0x18 17. " [17] ,Mask for NAND_GPMI_INT" "Masked,Unmasked" newline bitfld.long 0x18 16. " [16] ,Mask for NAND_BCH_INT" "Masked,Unmasked" bitfld.long 0x18 15. " [15] ,Mask for USB3_INT" "Masked,Unmasked" bitfld.long 0x18 14. " [14] ,Mask for WAKEUP_INT" "Masked,Unmasked" bitfld.long 0x18 13. " [13] ,Mask for UTMI_INT" "Masked,Unmasked" newline bitfld.long 0x18 12. " [12] ,Mask for USB_HOST_INT" "Masked,Unmasked" bitfld.long 0x18 11. " [11] ,Mask for USB_OTG_INT" "Masked,Unmasked" bitfld.long 0x18 10. " [10] ,Mask for MLB_AHB_INT" "Masked,Unmasked" bitfld.long 0x18 9. " [9] ,Mask for MLB_INT" "Masked,Unmasked" newline bitfld.long 0x18 7. " [7] ,Mask for ENET1_TIMER_INT" "Masked,Unmasked" bitfld.long 0x18 6. " [6] ,Mask for ENET1_FRAME0_EVENT_INT" "Masked,Unmasked" bitfld.long 0x18 5. " [5] ,Mask for ENET1_FRAME2_INT" "Masked,Unmasked" bitfld.long 0x18 4. " [4] ,Mask for ENET1_FRAME1_INT" "Masked,Unmasked" newline bitfld.long 0x18 3. " [3] ,Mask for ENET0_TIMER_INT" "Masked,Unmasked" bitfld.long 0x18 2. " [2] ,Mask for ENET0_FRAME0_EVENT_INT" "Masked,Unmasked" bitfld.long 0x18 1. " [1] ,Mask for ENET0_FRAME2_INT" "Masked,Unmasked" bitfld.long 0x18 0. " [0] ,Mask for ENET0_FRAME1_INT" "Masked,Unmasked" line.long 0x1C "MASK8,Interrupt Mask 8 Register" bitfld.long 0x1C 23. " MASKFLD[23] ,Mask for EXTERNAL_DMA_INT_5" "Masked,Unmasked" bitfld.long 0x1C 22. " [22] ,Mask for EXTERNAL_DMA_INT_4" "Masked,Unmasked" bitfld.long 0x1C 21. " [21] ,Mask for EXTERNAL_DMA_INT_3" "Masked,Unmasked" bitfld.long 0x1C 20. " [20] ,Mask for EXTERNAL_DMA_INT_2" "Masked,Unmasked" newline bitfld.long 0x1C 19. " [19] ,Mask for EXTERNAL_DMA_INT_1" "Masked,Unmasked" bitfld.long 0x1C 18. " [18] ,Mask for EXTERNAL_DMA_INT_0" "Masked,Unmasked" bitfld.long 0x1C 16. " [16] ,Mask for ADC_INT" "Masked,Unmasked" bitfld.long 0x1C 15. " [15] ,Mask for FTM1_INT" "Masked,Unmasked" newline bitfld.long 0x1C 14. " [14] ,Mask for FTM_INT" "Masked,Unmasked" bitfld.long 0x1C 13. " [13] ,Mask for FLEXCAN2_INT" "Masked,Unmasked" bitfld.long 0x1C 12. " [12] ,Mask for FLEXCAN1_INT" "Masked,Unmasked" bitfld.long 0x1C 11. " [11] ,Mask for FLEXCAN0_INT" "Masked,Unmasked" newline bitfld.long 0x1C 10. " [10] ,Mask for USDHC2_INT" "Masked,Unmasked" bitfld.long 0x1C 9. " [9] ,Mask for USDHC1_INT" "Masked,Unmasked" bitfld.long 0x1C 8. " [8] ,Mask for EMMC0_INT/USDHC0_INT" "Masked,Unmasked" bitfld.long 0x1C 4. " [4] ,Mask for UART3_INT" "Masked,Unmasked" newline bitfld.long 0x1C 3. " [3] ,Mask for UART2_INT" "Masked,Unmasked" bitfld.long 0x1C 2. " [2] ,Mask for UART1_INT" "Masked,Unmasked" bitfld.long 0x1C 1. " [1] ,Mask for UART0_INT" "Masked,Unmasked" line.long 0x20 "MASK9,Interrupt Mask 9 Register" bitfld.long 0x20 31. " MASKFLD[31] ,Mask for I2C3_INT" "Masked,Unmasked" bitfld.long 0x20 30. " [30] ,Mask for I2C2_INT" "Masked,Unmasked" bitfld.long 0x20 29. " [29] ,Mask for I2C1_INT" "Masked,Unmasked" bitfld.long 0x20 28. " [28] ,Mask for I2C0_INT" "Masked,Unmasked" newline bitfld.long 0x20 27. " [27] ,Mask for SPI3_INT" "Masked,Unmasked" bitfld.long 0x20 26. " [26] ,Mask for SPI2_INT" "Masked,Unmasked" bitfld.long 0x20 25. " [25] ,Mask for SPI1_INT" "Masked,Unmasked" bitfld.long 0x20 24. " [24] ,Mask for SPI0_INT" "Masked,Unmasked" newline bitfld.long 0x20 16. " [16] ,Mask for MU13_INT_B" "Masked,Unmasked" bitfld.long 0x20 15. " [15] ,Mask for MU12_INT_B" "Masked,Unmasked" bitfld.long 0x20 14. " [14] ,Mask for MU11_INT_B" "Masked,Unmasked" bitfld.long 0x20 13. " [13] ,Mask for MU10_INT_B" "Masked,Unmasked" newline bitfld.long 0x20 12. " [12] ,Mask for MU9_INT_B" "Masked,Unmasked" bitfld.long 0x20 11. " [11] ,Mask for MU8_INT_B" "Masked,Unmasked" bitfld.long 0x20 10. " [10] ,Mask for MU7_INT_B" "Masked,Unmasked" bitfld.long 0x20 9. " [9] ,Mask for MU6_INT_B" "Masked,Unmasked" newline bitfld.long 0x20 8. " [8] ,Mask for MU5_INT_B" "Masked,Unmasked" bitfld.long 0x20 0. " [0] ,Mask for MU13_INT_A" "Masked,Unmasked" line.long 0x24 "MASK10,Interrupt Mask 10 Register" bitfld.long 0x24 31. " MASKFLD[31] ,Mask for MU12_INT_A" "Masked,Unmasked" bitfld.long 0x24 30. " [30] ,Mask for MU11_INT_A" "Masked,Unmasked" bitfld.long 0x24 29. " [29] ,Mask for MU10_INT_A" "Masked,Unmasked" bitfld.long 0x24 28. " [28] ,Mask for MU9_INT_A" "Masked,Unmasked" newline bitfld.long 0x24 27. " [27] ,Mask for MU8_INT_A" "Masked,Unmasked" bitfld.long 0x24 26. " [26] ,Mask for MU7_INT_A" "Masked,Unmasked" bitfld.long 0x24 25. " [25] ,Mask for MU6_INT_A" "Masked,Unmasked" bitfld.long 0x24 24. " [24] ,Mask for MU5_INT_A" "Masked,Unmasked" newline bitfld.long 0x24 20. " [20] ,Mask for MU4_INT" "Masked,Unmasked" bitfld.long 0x24 19. " [19] ,Mask for MU3_INT" "Masked,Unmasked" bitfld.long 0x24 18. " [18] ,Mask for MU2_INT" "Masked,Unmasked" bitfld.long 0x24 17. " [17] ,Mask for MU1_INT" "Masked,Unmasked" newline bitfld.long 0x24 16. " [16] ,Mask for MU0_INT" "Masked,Unmasked" line.long 0x28 "MASK11,Interrupt Mask 11 Register" bitfld.long 0x28 15. " MASKFLD[15] ,Mask for GPIO_INT[7]" "Masked,Unmasked" bitfld.long 0x28 14. " [14] ,Mask for GPIO_INT[6]" "Masked,Unmasked" bitfld.long 0x28 13. " [13] ,Mask for GPIO_INT[5]" "Masked,Unmasked" bitfld.long 0x28 12. " [12] ,Mask for GPIO_INT[4]" "Masked,Unmasked" newline bitfld.long 0x28 11. " [11] ,Mask for GPIO_INT[3]" "Masked,Unmasked" bitfld.long 0x28 10. " [10] ,Mask for GPIO_INT[2]" "Masked,Unmasked" bitfld.long 0x28 9. " [9] ,Mask for GPIO_INT[1]" "Masked,Unmasked" bitfld.long 0x28 8. " [8] ,Mask for GPIO_INT[0]" "Masked,Unmasked" newline bitfld.long 0x28 3. " [3] ,Mask for PERF_CNT_INT" "Masked,Unmasked" bitfld.long 0x28 2. " [2] ,Mask for SBR_DONE_INT" "Masked,Unmasked" bitfld.long 0x28 1. " [1] ,Mask for ECC_NCORRECT_INT" "Masked,Unmasked" bitfld.long 0x28 0. " [0] ,Mask for ECC_CORRECT_INT" "Masked,Unmasked" line.long 0x2C "MASK12,Interrupt Mask 12 Register" bitfld.long 0x2C 27. " MASKFLD[27] ,Mask for SYS_COUNT_INT[3]" "Masked,Unmasked" bitfld.long 0x2C 26. " [26] ,Mask for SYS_COUNT_INT[2]" "Masked,Unmasked" bitfld.long 0x2C 25. " [25] ,Mask for SYS_COUNT_INT[1]" "Masked,Unmasked" bitfld.long 0x2C 24. " [24] ,Mask for SYS_COUNT_INT[0]" "Masked,Unmasked" newline bitfld.long 0x2C 23. " [23] ,Mask for INT_OUT[7]" "Masked,Unmasked" bitfld.long 0x2C 22. " [22] ,Mask for INT_OUT[6]" "Masked,Unmasked" bitfld.long 0x2C 21. " [21] ,Mask for INT_OUT[5]" "Masked,Unmasked" bitfld.long 0x2C 20. " [20] ,Mask for INT_OUT[4]" "Masked,Unmasked" newline bitfld.long 0x2C 19. " [19] ,Mask for INT_OUT[3]" "Masked,Unmasked" bitfld.long 0x2C 18. " [18] ,Mask for INT_OUT[2]" "Masked,Unmasked" bitfld.long 0x2C 17. " [17] ,Mask for INT_OUT[1]" "Masked,Unmasked" bitfld.long 0x2C 16. " [16] ,Mask for INT_OUT[0]" "Masked,Unmasked" newline bitfld.long 0x2C 15. " [15] ,Mask for PCIE9_GPIO_WAKEUP[1]" "Masked,Unmasked" bitfld.long 0x2C 14. " [14] ,Mask for PCIE9_GPIO_WAKEUP[0]" "Masked,Unmasked" bitfld.long 0x2C 13. " [13] ,Mask for PCIE0_SMLH_REQ_RST" "Masked,Unmasked" bitfld.long 0x2C 12. " [12] ,Mask for PCIE0_INT_A" "Masked,Unmasked" newline bitfld.long 0x2C 11. " [11] ,Mask for PCIE0_INT_B" "Masked,Unmasked" bitfld.long 0x2C 10. " [10] ,Mask for PCIE0_INT_C" "Masked,Unmasked" bitfld.long 0x2C 9. " [9] ,Mask for PCIE0_INT_D" "Masked,Unmasked" bitfld.long 0x2C 8. " [8] ,Mask for PCIE0_DMA_INT" "Masked,Unmasked" newline bitfld.long 0x2C 7. " [7] ,Mask for PCIE0_CLK_REQ_INT" "Masked,Unmasked" bitfld.long 0x2C 6. " [6] ,Mask for PCIE0_MSI_CTRL_INT" "Masked,Unmasked" bitfld.long 0x2C 5. " [5] ,Mask for PWM7_INT" "Masked,Unmasked" bitfld.long 0x2C 4. " [4] ,Mask for PWM6_INT" "Masked,Unmasked" newline bitfld.long 0x2C 3. " [3] ,Mask for PWM5_INT" "Masked,Unmasked" bitfld.long 0x2C 2. " [2] ,Mask for PWM4_INT" "Masked,Unmasked" bitfld.long 0x2C 1. " [1] ,Mask for PWM3_INT" "Masked,Unmasked" bitfld.long 0x2C 0. " [0] ,Mask for PWM2_INT" "Masked,Unmasked" line.long 0x30 "MASK13,Interrupt Mask 13 Register" bitfld.long 0x30 31. " MASKFLD[31] ,Mask for PWM1_INT" "Masked,Unmasked" bitfld.long 0x30 30. " [30] ,Mask for PWM0_INT" "Masked,Unmasked" bitfld.long 0x30 29. " [29] ,Mask for FLEXSPI1_INT" "Masked,Unmasked" bitfld.long 0x30 28. " [28] ,Mask for FLEXSPI0_INT" "Masked,Unmasked" newline bitfld.long 0x30 21. " [21] ,Mask for KPP0_INT" "Masked,Unmasked" bitfld.long 0x30 20. " [20] ,Mask for GPT4_INT" "Masked,Unmasked" bitfld.long 0x30 19. " [19] ,Mask for GPT3_INT" "Masked,Unmasked" bitfld.long 0x30 18. " [18] ,Mask for GPT2_INT" "Masked,Unmasked" newline bitfld.long 0x30 17. " [17] ,Mask for GPT1_INT" "Masked,Unmasked" bitfld.long 0x30 16. " [16] ,Mask for GPT0_INT" "Masked,Unmasked" bitfld.long 0x30 5. " [5] ,Mask for DMA3_ERR_INT" "Masked,Unmasked" bitfld.long 0x30 4. " [4] ,Mask for DMA3_INT" "Masked,Unmasked" newline bitfld.long 0x30 3. " [3] ,Mask for DMA2_ERR_INT" "Masked,Unmasked" bitfld.long 0x30 2. " [2] ,Mask for DMA2_INT" "Masked,Unmasked" bitfld.long 0x30 0. " [0] ,Mask for XAQ2_INTR" "Masked,Unmasked" line.long 0x34 "MASK14,Interrupt Mask 14 Register" bitfld.long 0x34 31. " MASKFLD[31] ,Mask for LCD_PWM_INT" "Masked,Unmasked" bitfld.long 0x34 30. " [30] ,Mask for LCD_MOD_INT" "Masked,Unmasked" bitfld.long 0x34 28. " [28] ,Mask for INT_OUT" "Masked,Unmasked" bitfld.long 0x34 27. " [27] ,Mask for INT_OUT" "Masked,Unmasked" newline bitfld.long 0x34 20. " [20] ,Mask for INT_OUT[12]" "Masked,Unmasked" bitfld.long 0x34 19. " [19] ,Mask for INT_OUT[11]" "Masked,Unmasked" bitfld.long 0x34 18. " [18] ,Mask for INT_OUT[10]" "Masked,Unmasked" bitfld.long 0x34 17. " [17] ,Mask for INT_OUT[9]" "Masked,Unmasked" newline bitfld.long 0x34 15. " [15] ,Mask for INT_OUT[7]" "Masked,Unmasked" bitfld.long 0x34 14. " [14] ,Mask for INT_OUT[6]" "Masked,Unmasked" bitfld.long 0x34 13. " [13] ,Mask for INT_OUT[5]" "Masked,Unmasked" bitfld.long 0x34 12. " [12] ,Mask for INT_OUT[4]" "Masked,Unmasked" newline bitfld.long 0x34 11. " [11] ,Mask for INT_OUT[3]" "Masked,Unmasked" bitfld.long 0x34 10. " [10] ,Mask for INT_OUT[2]" "Masked,Unmasked" bitfld.long 0x34 9. " [9] ,Mask for INT_OUT[1]" "Masked,Unmasked" bitfld.long 0x34 8. " [8] ,Mask for INT_OUT[0]" "Masked,Unmasked" line.long 0x38 "MASK15,Interrupt Mask 15 Register" bitfld.long 0x38 23. " MASKFLD[23] ,Mask for INT_OUT[7]" "Masked,Unmasked" bitfld.long 0x38 22. " [22] ,Mask for INT_OUT[6]" "Masked,Unmasked" bitfld.long 0x38 21. " [21] ,Mask for INT_OUT[5]" "Masked,Unmasked" bitfld.long 0x38 20. " [20] ,Mask for INT_OUT[4]" "Masked,Unmasked" newline bitfld.long 0x38 19. " [19] ,Mask for INT_OUT[3]" "Masked,Unmasked" bitfld.long 0x38 18. " [18] ,Mask for INT_OUT[2]" "Masked,Unmasked" bitfld.long 0x38 17. " [17] ,Mask for INT_OUT[1]" "Masked,Unmasked" bitfld.long 0x38 16. " [16] ,Mask for INT_OUT[0]" "Masked,Unmasked" newline bitfld.long 0x38 1. " [1] ,Mask for nEXTERRIRQ" "Masked,Unmasked" bitfld.long 0x38 0. " [0] ,Mask for nINTERRIRQ" "Masked,Unmasked" group.long 0x48++0x3B line.long 0x00 "SET1,Interrupt Set 1 Register" bitfld.long 0x00 22. " FORCEFLD[22] ,Force VPU_INT_6" "Normal,Forced" bitfld.long 0x00 21. " [21] ,Force VPU_INT_5" "Normal,Forced" bitfld.long 0x00 20. " [20] ,Force VPU_INT_4" "Normal,Forced" bitfld.long 0x00 19. " [19] ,Force VPU_INT_3" "Normal,Forced" newline bitfld.long 0x00 18. " [18] ,Force VPU_INT_2" "Normal,Forced" bitfld.long 0x00 17. " [17] ,Force VPU_INT_1" "Normal,Forced" bitfld.long 0x00 16. " [16] ,Force VPU_INT_0" "Normal,Forced" bitfld.long 0x00 11. " [11] ,Force SPDIF0_TX_DMA_INT" "Normal,Forced" newline bitfld.long 0x00 10. " [10] ,Force SPDIF0_TX_MOD_INT" "Normal,Forced" bitfld.long 0x00 9. " [9] ,Force SPDIF0_RX_DMA_INT" "Normal,Forced" bitfld.long 0x00 8. " [8] ,Force SPDIF0_RX_MOD_INT" "Normal,Forced" bitfld.long 0x00 7. " [7] ,Force CAAM_RTIC_INT" "Normal,Forced" newline bitfld.long 0x00 6. " [6] ,Force CAAM_INT3" "Normal,Forced" bitfld.long 0x00 5. " [5] ,Force CAAM_INT2" "Normal,Forced" bitfld.long 0x00 4. " [4] ,Force CAAM_INT1" "Normal,Forced" bitfld.long 0x00 3. " [3] ,Force CAAM_INT0" "Normal,Forced" newline bitfld.long 0x00 2. " [2] ,Force SEC_MU3_A_INT" "Normal,Forced" bitfld.long 0x00 1. " [1] ,Force SEC_MU2_A_INT" "Normal,Forced" bitfld.long 0x00 0. " [0] ,Force SEC_MU1_A_INT" "Normal,Forced" line.long 0x04 "SET2,Interrupt Set 2 Register" bitfld.long 0x04 25. " FORCEFLD[25] ,Force UART3_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 24. " [24] ,Force UART3_DMA_RX_INT" "Normal,Forced" bitfld.long 0x04 23. " [23] ,Force UART2_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 22. " [22] ,Force UART2_DMA_RX_INT" "Normal,Forced" newline bitfld.long 0x04 21. " [21] ,Force UART1_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 20. " [20] ,Force UART1_DMA_RX_INT" "Normal,Forced" bitfld.long 0x04 19. " [19] ,Force UART0_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 18. " [18] ,Force UART0_DMA_RX_INT" "Normal,Forced" newline bitfld.long 0x04 15. " [15] ,Force I2C3_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 14. " [14] ,Force I2C3_DMA_RX_INT" "Normal,Forced" bitfld.long 0x04 13. " [13] ,Force I2C2_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 12. " [12] ,Force I2C2_DMA_RX_INT" "Normal,Forced" newline bitfld.long 0x04 11. " [11] ,Force I2C1_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 10. " [10] ,Force I2C1_DMA_RX_INT" "Normal,Forced" bitfld.long 0x04 9. " [9] ,Force I2C0_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 8. " [8] ,Force I2C0_DMA_RX_INT" "Normal,Forced" newline bitfld.long 0x04 7. " [7] ,Force SPI3_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 6. " [6] ,Force SPI3_DMA_RX_INT" "Normal,Forced" bitfld.long 0x04 5. " [5] ,Force SPI2_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 4. " [4] ,Force SPI2_DMA_RX_INT" "Normal,Forced" newline bitfld.long 0x04 3. " [3] ,Force SPI1_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 2. " [2] ,Force SPI1_DMA_RX_INT" "Normal,Forced" bitfld.long 0x04 1. " [1] ,Force SPI0_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 0. " [0] ,Force SPI0_DMA_RX_INT" "Normal,Forced" line.long 0x08 "SET3,Interrupt Set 3 Register" bitfld.long 0x08 26. " FORCEFLD[26] ,Force ESAI0_DMA_INT" "Normal,Forced" bitfld.long 0x08 25. " [25] ,Force ESAI0_MOD_INT" "Normal,Forced" bitfld.long 0x08 22. " [22] ,Force SPDIF0_TX_INT" "Normal,Forced" bitfld.long 0x08 21. " [21] ,Force SPDIF0_RX_INT" "Normal,Forced" newline bitfld.long 0x08 20. " [20] ,Force SAI5_INT" "Normal,Forced" bitfld.long 0x08 19. " [19] ,Force SAI4_INT" "Normal,Forced" bitfld.long 0x08 16. " [16] ,Force SAI3_INT" "Normal,Forced" bitfld.long 0x08 15. " [15] ,Force SAI2_INT" "Normal,Forced" newline bitfld.long 0x08 14. " [14] ,Force SAI1_INT" "Normal,Forced" bitfld.long 0x08 13. " [13] ,Force SAI0_INT" "Normal,Forced" bitfld.long 0x08 12. " [12] ,Force GPT5_INT" "Normal,Forced" bitfld.long 0x08 11. " [11] ,Force GPT4_INT" "Normal,Forced" newline bitfld.long 0x08 10. " [10] ,Force GPT3_INT" "Normal,Forced" bitfld.long 0x08 9. " [9] ,Force GPT2_INT" "Normal,Forced" bitfld.long 0x08 8. " [8] ,Force GPT1_INT" "Normal,Forced" bitfld.long 0x08 7. " [7] ,Force GPT0_INT" "Normal,Forced" newline bitfld.long 0x08 4. " [4] ,Force ESAI0_INT" "Normal,Forced" bitfld.long 0x08 3. " [3] ,Force DMA1_CH5_INT" "Normal,Forced" bitfld.long 0x08 2. " [2] ,Force DMA1_CH4_INT" "Normal,Forced" bitfld.long 0x08 1. " [1] ,Force DMA1_CH3_INT" "Normal,Forced" newline bitfld.long 0x08 0. " [0] ,Force DMA1_CH2_INT" "Normal,Forced" line.long 0x0C "SET4,Interrupt Set 4 Register" bitfld.long 0x0C 31. " FORCEFLD[31] ,Force DMA1_CH1_INT" "Normal,Forced" bitfld.long 0x0C 30. " [30] ,Force DMA1_CH0_INT" "Normal,Forced" bitfld.long 0x0C 29. " [29] ,Force ASRC1_INT2" "Normal,Forced" bitfld.long 0x0C 28. " [28] ,Force ASRC1_INT1" "Normal,Forced" newline bitfld.long 0x0C 27. " [27] ,Force DMA0_CH5_INT" "Normal,Forced" bitfld.long 0x0C 26. " [26] ,Force DMA0_CH4_INT" "Normal,Forced" bitfld.long 0x0C 25. " [25] ,Force DMA0_CH3_INT" "Normal,Forced" bitfld.long 0x0C 24. " [24] ,Force DMA0_CH2_INT" "Normal,Forced" newline bitfld.long 0x0C 23. " [23] ,Force DMA0_CH1_INT" "Normal,Forced" bitfld.long 0x0C 22. " [22] ,Force DMA0_CH0_INT" "Normal,Forced" bitfld.long 0x0C 21. " [21] ,Force ASRC0_INT2" "Normal,Forced" bitfld.long 0x0C 20. " [20] ,Force ASRC0_INT1" "Normal,Forced" newline bitfld.long 0x0C 19. " [19] ,Force DMA1_ERR_INT" "Normal,Forced" bitfld.long 0x0C 18. " [18] ,Force DMA1_INT" "Normal,Forced" bitfld.long 0x0C 17. " [17] ,Force DMA0_ERR_INT" "Normal,Forced" bitfld.long 0x0C 16. " [16] ,Force DMA0_INT" "Normal,Forced" newline bitfld.long 0x0C 12. " [12] ,Force ADC_DMA_INT" "Normal,Forced" bitfld.long 0x0C 11. " [11] ,Force FTM1_DMA_INT" "Normal,Forced" bitfld.long 0x0C 10. " [10] ,Force FTM_DMA_INT" "Normal,Forced" bitfld.long 0x0C 9. " [9] ,Force FLEXCAN2_DMA_INT" "Normal,Forced" newline bitfld.long 0x0C 8. " [8] ,Force FLEXCAN1_DMA_INT" "Normal,Forced" bitfld.long 0x0C 7. " [7] ,Force FLEXCAN0_DMA_INT" "Normal,Forced" bitfld.long 0x0C 5. " [5] ,Force ADC_MOD_INT" "Normal,Forced" bitfld.long 0x0C 4. " [4] ,Force FTM1_MOD_INT" "Normal,Forced" newline bitfld.long 0x0C 3. " [3] ,Force FTM_MOD_INT" "Normal,Forced" bitfld.long 0x0C 2. " [2] ,Force FLEXCAN2_MOD_INT" "Normal,Forced" bitfld.long 0x0C 1. " [1] ,Force FLEXCAN1_MOD_INT" "Normal,Forced" bitfld.long 0x0C 0. " [0] ,Force FLEXCAN0_MOD_INT" "Normal,Forced" line.long 0x10 "SET5,Interrupt Set 5 Register" bitfld.long 0x10 28. " FORCEFLD[28] ,Force UART3_MOD_INT" "Normal,Forced" bitfld.long 0x10 27. " [27] ,Force UART2_MOD_INT" "Normal,Forced" bitfld.long 0x10 26. " [26] ,Force UART1_MOD_INT" "Normal,Forced" bitfld.long 0x10 25. " [25] ,Force UART0_MOD_INT" "Normal,Forced" newline bitfld.long 0x10 23. " [23] ,Force I2C3_MOD_INT" "Normal,Forced" bitfld.long 0x10 22. " [22] ,Force I2C2_MOD_INT" "Normal,Forced" bitfld.long 0x10 21. " [21] ,Force I2C1_MOD_INT" "Normal,Forced" bitfld.long 0x10 20. " [20] ,Force I2C0_MOD_INT" "Normal,Forced" newline bitfld.long 0x10 19. " [19] ,Force SPI3_MOD_INT" "Normal,Forced" bitfld.long 0x10 18. " [18] ,Force SPI2_MOD_INT" "Normal,Forced" bitfld.long 0x10 17. " [17] ,Force SPI1_MOD_INT" "Normal,Forced" bitfld.long 0x10 16. " [16] ,Force SPI0_MOD_INT" "Normal,Forced" newline bitfld.long 0x10 12. " [12] ,Force SAI5_DMA_INT" "Normal,Forced" bitfld.long 0x10 11. " [11] ,Force SAI5_MOD_INT" "Normal,Forced" bitfld.long 0x10 10. " [10] ,Force SAI4_DMA_INT" "Normal,Forced" bitfld.long 0x10 9. " [9] ,Force SAI4_MOD_INT" "Normal,Forced" newline bitfld.long 0x10 4. " [4] ,Force SAI3_DMA_INT" "Normal,Forced" bitfld.long 0x10 3. " [3] ,Force SAI3_MOD_INT" "Normal,Forced" bitfld.long 0x10 0. " [0] ,Force INT_OUT" "Normal,Forced" line.long 0x14 "SET6,Interrupt Set 6 Register" bitfld.long 0x14 31. " FORCEFLD[31] ,Force SAI2_DMA_INT" "Normal,Forced" bitfld.long 0x14 30. " [30] ,Force SAI2_MOD_INT" "Normal,Forced" bitfld.long 0x14 29. " [29] ,Force SAI1_DMA_INT" "Normal,Forced" bitfld.long 0x14 28. " [28] ,Force SAI1_MOD_INT" "Normal,Forced" newline bitfld.long 0x14 27. " [27] ,Force SAI0_DMA_INT" "Normal,Forced" bitfld.long 0x14 26. " [26] ,Force SAI0_MOD_INT" "Normal,Forced" bitfld.long 0x14 24. " [24] ,Force MJPEG_DEC3_INT" "Normal,Forced" bitfld.long 0x14 23. " [23] ,Force MJPEG_DEC2_INT" "Normal,Forced" newline bitfld.long 0x14 22. " [22] ,Force MJPEG_DEC1_INT" "Normal,Forced" bitfld.long 0x14 21. " [21] ,Force MJPEG_DEC0_INT" "Normal,Forced" bitfld.long 0x14 20. " [20] ,Force MJPEG_ENC3_INT" "Normal,Forced" bitfld.long 0x14 19. " [19] ,Force MJPEG_ENC2_INT" "Normal,Forced" newline bitfld.long 0x14 18. " [18] ,Force MJPEG_ENC1_INT" "Normal,Forced" bitfld.long 0x14 17. " [17] ,Force MJPEG_ENC0_INT" "Normal,Forced" bitfld.long 0x14 16. " [16] ,Force PDMA_STREAM7_INT" "Normal,Forced" bitfld.long 0x14 15. " [15] ,Force PDMA_STREAM6_INT" "Normal,Forced" newline bitfld.long 0x14 14. " [14] ,Force PDMA_STREAM5_INT" "Normal,Forced" bitfld.long 0x14 13. " [13] ,Force PDMA_STREAM4_INT" "Normal,Forced" bitfld.long 0x14 12. " [12] ,Force PDMA_STREAM3_INT" "Normal,Forced" bitfld.long 0x14 11. " [11] ,Force PDMA_STREAM2_INT" "Normal,Forced" newline bitfld.long 0x14 10. " [10] ,Force PDMA_STREAM1_INT" "Normal,Forced" bitfld.long 0x14 9. " [9] ,Force PDMA_STREAM0_INT" "Normal,Forced" bitfld.long 0x14 0. " [0] ,Force MSI_INT" "Normal,Forced" line.long 0x18 "SET7,Interrupt Set 7 Register" bitfld.long 0x18 20. " FORCEFLD[20] ,Force DMA_ERR_INT" "Normal,Forced" bitfld.long 0x18 19. " [19] ,Force DMA_INT" "Normal,Forced" bitfld.long 0x18 18. " [18] ,Force APBHDMA" "Normal,Forced" bitfld.long 0x18 17. " [17] ,Force NAND_GPMI_INT" "Normal,Forced" newline bitfld.long 0x18 16. " [16] ,Force NAND_BCH_INT" "Normal,Forced" bitfld.long 0x18 15. " [15] ,Force USB3_INT" "Normal,Forced" bitfld.long 0x18 14. " [14] ,Force WAKEUP_INT" "Normal,Forced" bitfld.long 0x18 13. " [13] ,Force UTMI_INT" "Normal,Forced" newline bitfld.long 0x18 12. " [12] ,Force USB_HOST_INT" "Normal,Forced" bitfld.long 0x18 11. " [11] ,Force USB_OTG_INT" "Normal,Forced" bitfld.long 0x18 10. " [10] ,Force MLB_AHB_INT" "Normal,Forced" bitfld.long 0x18 9. " [9] ,Force MLB_INT" "Normal,Forced" newline bitfld.long 0x18 7. " [7] ,Force ENET1_TIMER_INT" "Normal,Forced" bitfld.long 0x18 6. " [6] ,Force ENET1_FRAME0_EVENT_INT" "Normal,Forced" bitfld.long 0x18 5. " [5] ,Force ENET1_FRAME2_INT" "Normal,Forced" bitfld.long 0x18 4. " [4] ,Force ENET1_FRAME1_INT" "Normal,Forced" newline bitfld.long 0x18 3. " [3] ,Force ENET0_TIMER_INT" "Normal,Forced" bitfld.long 0x18 2. " [2] ,Force ENET0_FRAME0_EVENT_INT" "Normal,Forced" bitfld.long 0x18 1. " [1] ,Force ENET0_FRAME2_INT" "Normal,Forced" bitfld.long 0x18 0. " [0] ,Force ENET0_FRAME1_INT" "Normal,Forced" line.long 0x1C "SET8,Interrupt Set 8 Register" bitfld.long 0x1C 23. " FORCEFLD[23] ,Force EXTERNAL_DMA_INT_5" "Normal,Forced" bitfld.long 0x1C 22. " [22] ,Force EXTERNAL_DMA_INT_4" "Normal,Forced" bitfld.long 0x1C 21. " [21] ,Force EXTERNAL_DMA_INT_3" "Normal,Forced" bitfld.long 0x1C 20. " [20] ,Force EXTERNAL_DMA_INT_2" "Normal,Forced" newline bitfld.long 0x1C 19. " [19] ,Force EXTERNAL_DMA_INT_1" "Normal,Forced" bitfld.long 0x1C 18. " [18] ,Force EXTERNAL_DMA_INT_0" "Normal,Forced" bitfld.long 0x1C 16. " [16] ,Force ADC_INT" "Normal,Forced" bitfld.long 0x1C 15. " [15] ,Force FTM1_INT" "Normal,Forced" newline bitfld.long 0x1C 14. " [14] ,Force FTM_INT" "Normal,Forced" bitfld.long 0x1C 13. " [13] ,Force FLEXCAN2_INT" "Normal,Forced" bitfld.long 0x1C 12. " [12] ,Force FLEXCAN1_INT" "Normal,Forced" bitfld.long 0x1C 11. " [11] ,Force FLEXCAN0_INT" "Normal,Forced" newline bitfld.long 0x1C 10. " [10] ,Force USDHC2_INT" "Normal,Forced" bitfld.long 0x1C 9. " [9] ,Force USDHC1_INT" "Normal,Forced" bitfld.long 0x1C 8. " [8] ,Force EMMC0_INT/USDHC0_INT" "Normal,Forced" bitfld.long 0x1C 4. " [4] ,Force UART3_INT" "Normal,Forced" newline bitfld.long 0x1C 3. " [3] ,Force UART2_INT" "Normal,Forced" bitfld.long 0x1C 2. " [2] ,Force UART1_INT" "Normal,Forced" bitfld.long 0x1C 1. " [1] ,Force UART0_INT" "Normal,Forced" line.long 0x20 "SET9,Interrupt Set 9 Register" bitfld.long 0x20 31. " FORCEFLD[31] ,Force I2C3_INT" "Normal,Forced" bitfld.long 0x20 30. " [30] ,Force I2C2_INT" "Normal,Forced" bitfld.long 0x20 29. " [29] ,Force I2C1_INT" "Normal,Forced" bitfld.long 0x20 28. " [28] ,Force I2C0_INT" "Normal,Forced" newline bitfld.long 0x20 27. " [27] ,Force SPI3_INT" "Normal,Forced" bitfld.long 0x20 26. " [26] ,Force SPI2_INT" "Normal,Forced" bitfld.long 0x20 25. " [25] ,Force SPI1_INT" "Normal,Forced" bitfld.long 0x20 24. " [24] ,Force SPI0_INT" "Normal,Forced" newline bitfld.long 0x20 16. " [16] ,Force MU13_INT_B" "Normal,Forced" bitfld.long 0x20 15. " [15] ,Force MU12_INT_B" "Normal,Forced" bitfld.long 0x20 14. " [14] ,Force MU11_INT_B" "Normal,Forced" bitfld.long 0x20 13. " [13] ,Force MU10_INT_B" "Normal,Forced" newline bitfld.long 0x20 12. " [12] ,Force MU9_INT_B" "Normal,Forced" bitfld.long 0x20 11. " [11] ,Force MU8_INT_B" "Normal,Forced" bitfld.long 0x20 10. " [10] ,Force MU7_INT_B" "Normal,Forced" bitfld.long 0x20 9. " [9] ,Force MU6_INT_B" "Normal,Forced" newline bitfld.long 0x20 8. " [8] ,Force MU5_INT_B" "Normal,Forced" bitfld.long 0x20 0. " [0] ,Force MU13_INT_A" "Normal,Forced" line.long 0x24 "SET10,Interrupt Set 10 Register" bitfld.long 0x24 31. " FORCEFLD[31] ,Force MU12_INT_A" "Normal,Forced" bitfld.long 0x24 30. " [30] ,Force MU11_INT_A" "Normal,Forced" bitfld.long 0x24 29. " [29] ,Force MU10_INT_A" "Normal,Forced" bitfld.long 0x24 28. " [28] ,Force MU9_INT_A" "Normal,Forced" newline bitfld.long 0x24 27. " [27] ,Force MU8_INT_A" "Normal,Forced" bitfld.long 0x24 26. " [26] ,Force MU7_INT_A" "Normal,Forced" bitfld.long 0x24 25. " [25] ,Force MU6_INT_A" "Normal,Forced" bitfld.long 0x24 24. " [24] ,Force MU5_INT_A" "Normal,Forced" newline bitfld.long 0x24 20. " [20] ,Force MU4_INT" "Normal,Forced" bitfld.long 0x24 19. " [19] ,Force MU3_INT" "Normal,Forced" bitfld.long 0x24 18. " [18] ,Force MU2_INT" "Normal,Forced" bitfld.long 0x24 17. " [17] ,Force MU1_INT" "Normal,Forced" newline bitfld.long 0x24 16. " [16] ,Force MU0_INT" "Normal,Forced" line.long 0x28 "SET11,Interrupt Set 11 Register" bitfld.long 0x28 15. " FORCEFLD[15] ,Force GPIO_INT[7]" "Normal,Forced" bitfld.long 0x28 14. " [14] ,Force GPIO_INT[6]" "Normal,Forced" bitfld.long 0x28 13. " [13] ,Force GPIO_INT[5]" "Normal,Forced" bitfld.long 0x28 12. " [12] ,Force GPIO_INT[4]" "Normal,Forced" newline bitfld.long 0x28 11. " [11] ,Force GPIO_INT[3]" "Normal,Forced" bitfld.long 0x28 10. " [10] ,Force GPIO_INT[2]" "Normal,Forced" bitfld.long 0x28 9. " [9] ,Force GPIO_INT[1]" "Normal,Forced" bitfld.long 0x28 8. " [8] ,Force GPIO_INT[0]" "Normal,Forced" newline bitfld.long 0x28 3. " [3] ,Force PERF_CNT_INT" "Normal,Forced" bitfld.long 0x28 2. " [2] ,Force SBR_DONE_INT" "Normal,Forced" bitfld.long 0x28 1. " [1] ,Force ECC_NCORRECT_INT" "Normal,Forced" bitfld.long 0x28 0. " [0] ,Force ECC_CORRECT_INT" "Normal,Forced" line.long 0x2C "SET12,Interrupt Set 12 Register" bitfld.long 0x2C 27. " FORCEFLD[27] ,Force SYS_COUNT_INT[3]" "Normal,Forced" bitfld.long 0x2C 26. " [26] ,Force SYS_COUNT_INT[2]" "Normal,Forced" bitfld.long 0x2C 25. " [25] ,Force SYS_COUNT_INT[1]" "Normal,Forced" bitfld.long 0x2C 24. " [24] ,Force SYS_COUNT_INT[0]" "Normal,Forced" newline bitfld.long 0x2C 23. " [23] ,Force INT_OUT[7]" "Normal,Forced" bitfld.long 0x2C 22. " [22] ,Force INT_OUT[6]" "Normal,Forced" bitfld.long 0x2C 21. " [21] ,Force INT_OUT[5]" "Normal,Forced" bitfld.long 0x2C 20. " [20] ,Force INT_OUT[4]" "Normal,Forced" newline bitfld.long 0x2C 19. " [19] ,Force INT_OUT[3]" "Normal,Forced" bitfld.long 0x2C 18. " [18] ,Force INT_OUT[2]" "Normal,Forced" bitfld.long 0x2C 17. " [17] ,Force INT_OUT[1]" "Normal,Forced" bitfld.long 0x2C 16. " [16] ,Force INT_OUT[0]" "Normal,Forced" newline bitfld.long 0x2C 15. " [15] ,Force PCIE9_GPIO_WAKEUP[1]" "Normal,Forced" bitfld.long 0x2C 14. " [14] ,Force PCIE9_GPIO_WAKEUP[0]" "Normal,Forced" bitfld.long 0x2C 13. " [13] ,Force PCIE0_SMLH_REQ_RST" "Normal,Forced" bitfld.long 0x2C 12. " [12] ,Force PCIE0_INT_A" "Normal,Forced" newline bitfld.long 0x2C 11. " [11] ,Force PCIE0_INT_B" "Normal,Forced" bitfld.long 0x2C 10. " [10] ,Force PCIE0_INT_C" "Normal,Forced" bitfld.long 0x2C 9. " [9] ,Force PCIE0_INT_D" "Normal,Forced" bitfld.long 0x2C 8. " [8] ,Force PCIE0_DMA_INT" "Normal,Forced" newline bitfld.long 0x2C 7. " [7] ,Force PCIE0_CLK_REQ_INT" "Normal,Forced" bitfld.long 0x2C 6. " [6] ,Force PCIE0_MSI_CTRL_INT" "Normal,Forced" bitfld.long 0x2C 5. " [5] ,Force PWM7_INT" "Normal,Forced" bitfld.long 0x2C 4. " [4] ,Force PWM6_INT" "Normal,Forced" newline bitfld.long 0x2C 3. " [3] ,Force PWM5_INT" "Normal,Forced" bitfld.long 0x2C 2. " [2] ,Force PWM4_INT" "Normal,Forced" bitfld.long 0x2C 1. " [1] ,Force PWM3_INT" "Normal,Forced" bitfld.long 0x2C 0. " [0] ,Force PWM2_INT" "Normal,Forced" line.long 0x30 "SET13,Interrupt Set 13 Register" bitfld.long 0x30 31. " FORCEFLD[31] ,Force PWM1_INT" "Normal,Forced" bitfld.long 0x30 30. " [30] ,Force PWM0_INT" "Normal,Forced" bitfld.long 0x30 29. " [29] ,Force FLEXSPI1_INT" "Normal,Forced" bitfld.long 0x30 28. " [28] ,Force FLEXSPI0_INT" "Normal,Forced" newline bitfld.long 0x30 21. " [21] ,Force KPP0_INT" "Normal,Forced" bitfld.long 0x30 20. " [20] ,Force GPT4_INT" "Normal,Forced" bitfld.long 0x30 19. " [19] ,Force GPT3_INT" "Normal,Forced" bitfld.long 0x30 18. " [18] ,Force GPT2_INT" "Normal,Forced" newline bitfld.long 0x30 17. " [17] ,Force GPT1_INT" "Normal,Forced" bitfld.long 0x30 16. " [16] ,Force GPT0_INT" "Normal,Forced" bitfld.long 0x30 5. " [5] ,Force DMA3_ERR_INT" "Normal,Forced" bitfld.long 0x30 4. " [4] ,Force DMA3_INT" "Normal,Forced" newline bitfld.long 0x30 3. " [3] ,Force DMA2_ERR_INT" "Normal,Forced" bitfld.long 0x30 2. " [2] ,Force DMA2_INT" "Normal,Forced" bitfld.long 0x30 0. " [0] ,Force XAQ2_INTR" "Normal,Forced" line.long 0x34 "SET14,Interrupt Set 14 Register" bitfld.long 0x34 31. " FORCEFLD[31] ,Force LCD_PWM_INT" "Normal,Forced" bitfld.long 0x34 30. " [30] ,Force LCD_MOD_INT" "Normal,Forced" bitfld.long 0x34 28. " [28] ,Force INT_OUT" "Normal,Forced" bitfld.long 0x34 27. " [27] ,Force INT_OUT" "Normal,Forced" newline bitfld.long 0x34 20. " [20] ,Force INT_OUT[12]" "Normal,Forced" bitfld.long 0x34 19. " [19] ,Force INT_OUT[11]" "Normal,Forced" bitfld.long 0x34 18. " [18] ,Force INT_OUT[10]" "Normal,Forced" bitfld.long 0x34 17. " [17] ,Force INT_OUT[9]" "Normal,Forced" newline bitfld.long 0x34 15. " [15] ,Force INT_OUT[7]" "Normal,Forced" bitfld.long 0x34 14. " [14] ,Force INT_OUT[6]" "Normal,Forced" bitfld.long 0x34 13. " [13] ,Force INT_OUT[5]" "Normal,Forced" bitfld.long 0x34 12. " [12] ,Force INT_OUT[4]" "Normal,Forced" newline bitfld.long 0x34 11. " [11] ,Force INT_OUT[3]" "Normal,Forced" bitfld.long 0x34 10. " [10] ,Force INT_OUT[2]" "Normal,Forced" bitfld.long 0x34 9. " [9] ,Force INT_OUT[1]" "Normal,Forced" bitfld.long 0x34 8. " [8] ,Force INT_OUT[0]" "Normal,Forced" line.long 0x38 "SET15,Interrupt Set 15 Register" bitfld.long 0x38 23. " FORCEFLD[23] ,Force INT_OUT[7]" "Normal,Forced" bitfld.long 0x38 22. " [22] ,Force INT_OUT[6]" "Normal,Forced" bitfld.long 0x38 21. " [21] ,Force INT_OUT[5]" "Normal,Forced" bitfld.long 0x38 20. " [20] ,Force INT_OUT[4]" "Normal,Forced" newline bitfld.long 0x38 19. " [19] ,Force INT_OUT[3]" "Normal,Forced" bitfld.long 0x38 18. " [18] ,Force INT_OUT[2]" "Normal,Forced" bitfld.long 0x38 17. " [17] ,Force INT_OUT[1]" "Normal,Forced" bitfld.long 0x38 16. " [16] ,Force INT_OUT[0]" "Normal,Forced" newline bitfld.long 0x38 1. " [1] ,Force nEXTERRIRQ" "Normal,Forced" bitfld.long 0x38 0. " [0] ,Force nINTERRIRQ" "Normal,Forced" rgroup.long 0x88++0x3B line.long 0x00 "STATUS1,Interrupt Status 1 Register" bitfld.long 0x00 22. " STATUS[22] ,VPU_INT_6 status" "Not set,Set" bitfld.long 0x00 21. " [21] ,VPU_INT_5 status" "Not set,Set" bitfld.long 0x00 20. " [20] ,VPU_INT_4 status" "Not set,Set" bitfld.long 0x00 19. " [19] ,VPU_INT_3 status" "Not set,Set" newline bitfld.long 0x00 18. " [18] ,VPU_INT_2 status" "Not set,Set" bitfld.long 0x00 17. " [17] ,VPU_INT_1 status" "Not set,Set" bitfld.long 0x00 16. " [16] ,VPU_INT_0 status" "Not set,Set" bitfld.long 0x00 11. " [11] ,SPDIF0_TX_DMA_INT status" "Not set,Set" newline bitfld.long 0x00 10. " [10] ,SPDIF0_TX_MOD_INT status" "Not set,Set" bitfld.long 0x00 9. " [9] ,SPDIF0_RX_DMA_INT status" "Not set,Set" bitfld.long 0x00 8. " [8] ,SPDIF0_RX_MOD_INT status" "Not set,Set" bitfld.long 0x00 7. " [7] ,CAAM_RTIC_INT status" "Not set,Set" newline bitfld.long 0x00 6. " [6] ,CAAM_INT3 status" "Not set,Set" bitfld.long 0x00 5. " [5] ,CAAM_INT2 status" "Not set,Set" bitfld.long 0x00 4. " [4] ,CAAM_INT1 status" "Not set,Set" bitfld.long 0x00 3. " [3] ,CAAM_INT0 status" "Not set,Set" newline bitfld.long 0x00 2. " [2] ,SEC_MU3_A_INT status" "Not set,Set" bitfld.long 0x00 1. " [1] ,SEC_MU2_A_INT status" "Not set,Set" bitfld.long 0x00 0. " [0] ,SEC_MU1_A_INT status" "Not set,Set" line.long 0x04 "STATUS2,Interrupt Status 2 Register" bitfld.long 0x04 25. " STATUS[25] ,UART3_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 24. " [24] ,UART3_DMA_RX_INT status" "Not set,Set" bitfld.long 0x04 23. " [23] ,UART2_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 22. " [22] ,UART2_DMA_RX_INT status" "Not set,Set" newline bitfld.long 0x04 21. " [21] ,UART1_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 20. " [20] ,UART1_DMA_RX_INT status" "Not set,Set" bitfld.long 0x04 19. " [19] ,UART0_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 18. " [18] ,UART0_DMA_RX_INT status" "Not set,Set" newline bitfld.long 0x04 15. " [15] ,I2C3_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 14. " [14] ,I2C3_DMA_RX_INT status" "Not set,Set" bitfld.long 0x04 13. " [13] ,I2C2_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 12. " [12] ,I2C2_DMA_RX_INT status" "Not set,Set" newline bitfld.long 0x04 11. " [11] ,I2C1_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 10. " [10] ,I2C1_DMA_RX_INT status" "Not set,Set" bitfld.long 0x04 9. " [9] ,I2C0_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 8. " [8] ,I2C0_DMA_RX_INT status" "Not set,Set" newline bitfld.long 0x04 7. " [7] ,SPI3_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 6. " [6] ,SPI3_DMA_RX_INT status" "Not set,Set" bitfld.long 0x04 5. " [5] ,SPI2_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 4. " [4] ,SPI2_DMA_RX_INT status" "Not set,Set" newline bitfld.long 0x04 3. " [3] ,SPI1_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 2. " [2] ,SPI1_DMA_RX_INT status" "Not set,Set" bitfld.long 0x04 1. " [1] ,SPI0_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 0. " [0] ,SPI0_DMA_RX_INT status" "Not set,Set" line.long 0x08 "STATUS3,Interrupt Status 3 Register" bitfld.long 0x08 26. " STATUS[26] ,ESAI0_DMA_INT status" "Not set,Set" bitfld.long 0x08 25. " [25] ,ESAI0_MOD_INT status" "Not set,Set" bitfld.long 0x08 22. " [22] ,SPDIF0_TX_INT status" "Not set,Set" bitfld.long 0x08 21. " [21] ,SPDIF0_RX_INT status" "Not set,Set" newline bitfld.long 0x08 20. " [20] ,SAI5_INT status" "Not set,Set" bitfld.long 0x08 19. " [19] ,SAI4_INT status" "Not set,Set" bitfld.long 0x08 16. " [16] ,SAI3_INT status" "Not set,Set" bitfld.long 0x08 15. " [15] ,SAI2_INT status" "Not set,Set" newline bitfld.long 0x08 14. " [14] ,SAI1_INT status" "Not set,Set" bitfld.long 0x08 13. " [13] ,SAI0_INT status" "Not set,Set" bitfld.long 0x08 12. " [12] ,GPT5_INT status" "Not set,Set" bitfld.long 0x08 11. " [11] ,GPT4_INT status" "Not set,Set" newline bitfld.long 0x08 10. " [10] ,GPT3_INT status" "Not set,Set" bitfld.long 0x08 9. " [9] ,GPT2_INT status" "Not set,Set" bitfld.long 0x08 8. " [8] ,GPT1_INT status" "Not set,Set" bitfld.long 0x08 7. " [7] ,GPT0_INT status" "Not set,Set" newline bitfld.long 0x08 4. " [4] ,ESAI0_INT status" "Not set,Set" bitfld.long 0x08 3. " [3] ,DMA1_CH5_INT status" "Not set,Set" bitfld.long 0x08 2. " [2] ,DMA1_CH4_INT status" "Not set,Set" bitfld.long 0x08 1. " [1] ,DMA1_CH3_INT status" "Not set,Set" newline bitfld.long 0x08 0. " [0] ,DMA1_CH2_INT status" "Not set,Set" line.long 0x0C "STATUS4,Interrupt Status 4 Register" bitfld.long 0x0C 31. " STATUS[31] ,DMA1_CH1_INT status" "Not set,Set" bitfld.long 0x0C 30. " [30] ,DMA1_CH0_INT status" "Not set,Set" bitfld.long 0x0C 29. " [29] ,ASRC1_INT2 status" "Not set,Set" bitfld.long 0x0C 28. " [28] ,ASRC1_INT1 status" "Not set,Set" newline bitfld.long 0x0C 27. " [27] ,DMA0_CH5_INT status" "Not set,Set" bitfld.long 0x0C 26. " [26] ,DMA0_CH4_INT status" "Not set,Set" bitfld.long 0x0C 25. " [25] ,DMA0_CH3_INT status" "Not set,Set" bitfld.long 0x0C 24. " [24] ,DMA0_CH2_INT status" "Not set,Set" newline bitfld.long 0x0C 23. " [23] ,DMA0_CH1_INT status" "Not set,Set" bitfld.long 0x0C 22. " [22] ,DMA0_CH0_INT status" "Not set,Set" bitfld.long 0x0C 21. " [21] ,ASRC0_INT2 status" "Not set,Set" bitfld.long 0x0C 20. " [20] ,ASRC0_INT1 status" "Not set,Set" newline bitfld.long 0x0C 19. " [19] ,DMA1_ERR_INT status" "Not set,Set" bitfld.long 0x0C 18. " [18] ,DMA1_INT status" "Not set,Set" bitfld.long 0x0C 17. " [17] ,DMA0_ERR_INT status" "Not set,Set" bitfld.long 0x0C 16. " [16] ,DMA0_INT status" "Not set,Set" newline bitfld.long 0x0C 12. " [12] ,ADC_DMA_INT status" "Not set,Set" bitfld.long 0x0C 11. " [11] ,FTM1_DMA_INT status" "Not set,Set" bitfld.long 0x0C 10. " [10] ,FTM_DMA_INT status" "Not set,Set" bitfld.long 0x0C 9. " [9] ,FLEXCAN2_DMA_INT status" "Not set,Set" newline bitfld.long 0x0C 8. " [8] ,FLEXCAN1_DMA_INT status" "Not set,Set" bitfld.long 0x0C 7. " [7] ,FLEXCAN0_DMA_INT status" "Not set,Set" bitfld.long 0x0C 5. " [5] ,ADC_MOD_INT status" "Not set,Set" bitfld.long 0x0C 4. " [4] ,FTM1_MOD_INT status" "Not set,Set" newline bitfld.long 0x0C 3. " [3] ,FTM_MOD_INT status" "Not set,Set" bitfld.long 0x0C 2. " [2] ,FLEXCAN2_MOD_INT status" "Not set,Set" bitfld.long 0x0C 1. " [1] ,FLEXCAN1_MOD_INT status" "Not set,Set" bitfld.long 0x0C 0. " [0] ,FLEXCAN0_MOD_INT status" "Not set,Set" line.long 0x10 "STATUS5,Interrupt Status 5 Register" bitfld.long 0x10 28. " STATUS[28] ,UART3_MOD_INT status" "Not set,Set" bitfld.long 0x10 27. " [27] ,UART2_MOD_INT status" "Not set,Set" bitfld.long 0x10 26. " [26] ,UART1_MOD_INT status" "Not set,Set" bitfld.long 0x10 25. " [25] ,UART0_MOD_INT status" "Not set,Set" newline bitfld.long 0x10 23. " [23] ,I2C3_MOD_INT status" "Not set,Set" bitfld.long 0x10 22. " [22] ,I2C2_MOD_INT status" "Not set,Set" bitfld.long 0x10 21. " [21] ,I2C1_MOD_INT status" "Not set,Set" bitfld.long 0x10 20. " [20] ,I2C0_MOD_INT status" "Not set,Set" newline bitfld.long 0x10 19. " [19] ,SPI3_MOD_INT status" "Not set,Set" bitfld.long 0x10 18. " [18] ,SPI2_MOD_INT status" "Not set,Set" bitfld.long 0x10 17. " [17] ,SPI1_MOD_INT status" "Not set,Set" bitfld.long 0x10 16. " [16] ,SPI0_MOD_INT status" "Not set,Set" newline bitfld.long 0x10 12. " [12] ,SAI5_DMA_INT status" "Not set,Set" bitfld.long 0x10 11. " [11] ,SAI5_MOD_INT status" "Not set,Set" bitfld.long 0x10 10. " [10] ,SAI4_DMA_INT status" "Not set,Set" bitfld.long 0x10 9. " [9] ,SAI4_MOD_INT status" "Not set,Set" newline bitfld.long 0x10 4. " [4] ,SAI3_DMA_INT status" "Not set,Set" bitfld.long 0x10 3. " [3] ,SAI3_MOD_INT status" "Not set,Set" bitfld.long 0x10 0. " [0] ,INT_OUT status" "Not set,Set" line.long 0x14 "STATUS6,Interrupt Status 6 Register" bitfld.long 0x14 31. " STATUS[31] ,SAI2_DMA_INT status" "Not set,Set" bitfld.long 0x14 30. " [30] ,SAI2_MOD_INT status" "Not set,Set" bitfld.long 0x14 29. " [29] ,SAI1_DMA_INT status" "Not set,Set" bitfld.long 0x14 28. " [28] ,SAI1_MOD_INT status" "Not set,Set" newline bitfld.long 0x14 27. " [27] ,SAI0_DMA_INT status" "Not set,Set" bitfld.long 0x14 26. " [26] ,SAI0_MOD_INT status" "Not set,Set" bitfld.long 0x14 24. " [24] ,MJPEG_DEC3_INT status" "Not set,Set" bitfld.long 0x14 23. " [23] ,MJPEG_DEC2_INT status" "Not set,Set" newline bitfld.long 0x14 22. " [22] ,MJPEG_DEC1_INT status" "Not set,Set" bitfld.long 0x14 21. " [21] ,MJPEG_DEC0_INT status" "Not set,Set" bitfld.long 0x14 20. " [20] ,MJPEG_ENC3_INT status" "Not set,Set" bitfld.long 0x14 19. " [19] ,MJPEG_ENC2_INT status" "Not set,Set" newline bitfld.long 0x14 18. " [18] ,MJPEG_ENC1_INT status" "Not set,Set" bitfld.long 0x14 17. " [17] ,MJPEG_ENC0_INT status" "Not set,Set" bitfld.long 0x14 16. " [16] ,PDMA_STREAM7_INT status" "Not set,Set" bitfld.long 0x14 15. " [15] ,PDMA_STREAM6_INT status" "Not set,Set" newline bitfld.long 0x14 14. " [14] ,PDMA_STREAM5_INT status" "Not set,Set" bitfld.long 0x14 13. " [13] ,PDMA_STREAM4_INT status" "Not set,Set" bitfld.long 0x14 12. " [12] ,PDMA_STREAM3_INT status" "Not set,Set" bitfld.long 0x14 11. " [11] ,PDMA_STREAM2_INT status" "Not set,Set" newline bitfld.long 0x14 10. " [10] ,PDMA_STREAM1_INT status" "Not set,Set" bitfld.long 0x14 9. " [9] ,PDMA_STREAM0_INT status" "Not set,Set" bitfld.long 0x14 0. " [0] ,MSI_INT status" "Not set,Set" line.long 0x18 "STATUS7,Interrupt Status 7 Register" bitfld.long 0x18 20. " STATUS[20] ,DMA_ERR_INT status" "Not set,Set" bitfld.long 0x18 19. " [19] ,DMA_INT status" "Not set,Set" bitfld.long 0x18 18. " [18] ,APBHDMA status" "Not set,Set" bitfld.long 0x18 17. " [17] ,NAND_GPMI_INT status" "Not set,Set" newline bitfld.long 0x18 16. " [16] ,NAND_BCH_INT status" "Not set,Set" bitfld.long 0x18 15. " [15] ,USB3_INT status" "Not set,Set" bitfld.long 0x18 14. " [14] ,WAKEUP_INT status" "Not set,Set" bitfld.long 0x18 13. " [13] ,UTMI_INT status" "Not set,Set" newline bitfld.long 0x18 12. " [12] ,USB_HOST_INT status" "Not set,Set" bitfld.long 0x18 11. " [11] ,USB_OTG_INT status" "Not set,Set" bitfld.long 0x18 10. " [10] ,MLB_AHB_INT status" "Not set,Set" bitfld.long 0x18 9. " [9] ,MLB_INT status" "Not set,Set" newline bitfld.long 0x18 7. " [7] ,ENET1_TIMER_INT status" "Not set,Set" bitfld.long 0x18 6. " [6] ,ENET1_FRAME0_EVENT_INT status" "Not set,Set" bitfld.long 0x18 5. " [5] ,ENET1_FRAME2_INT status" "Not set,Set" bitfld.long 0x18 4. " [4] ,ENET1_FRAME1_INT status" "Not set,Set" newline bitfld.long 0x18 3. " [3] ,ENET0_TIMER_INT status" "Not set,Set" bitfld.long 0x18 2. " [2] ,ENET0_FRAME0_EVENT_INT status" "Not set,Set" bitfld.long 0x18 1. " [1] ,ENET0_FRAME2_INT status" "Not set,Set" bitfld.long 0x18 0. " [0] ,ENET0_FRAME1_INT status" "Not set,Set" line.long 0x1C "STATUS8,Interrupt Status 8 Register" bitfld.long 0x1C 23. " STATUS[23] ,EXTERNAL_DMA_INT_5 status" "Not set,Set" bitfld.long 0x1C 22. " [22] ,EXTERNAL_DMA_INT_4 status" "Not set,Set" bitfld.long 0x1C 21. " [21] ,EXTERNAL_DMA_INT_3 status" "Not set,Set" bitfld.long 0x1C 20. " [20] ,EXTERNAL_DMA_INT_2 status" "Not set,Set" newline bitfld.long 0x1C 19. " [19] ,EXTERNAL_DMA_INT_1 status" "Not set,Set" bitfld.long 0x1C 18. " [18] ,EXTERNAL_DMA_INT_0 status" "Not set,Set" bitfld.long 0x1C 16. " [16] ,ADC_INT status" "Not set,Set" bitfld.long 0x1C 15. " [15] ,FTM1_INT status" "Not set,Set" newline bitfld.long 0x1C 14. " [14] ,FTM_INT status" "Not set,Set" bitfld.long 0x1C 13. " [13] ,FLEXCAN2_INT status" "Not set,Set" bitfld.long 0x1C 12. " [12] ,FLEXCAN1_INT status" "Not set,Set" bitfld.long 0x1C 11. " [11] ,FLEXCAN0_INT status" "Not set,Set" newline bitfld.long 0x1C 10. " [10] ,USDHC2_INT status" "Not set,Set" bitfld.long 0x1C 9. " [9] ,USDHC1_INT status" "Not set,Set" bitfld.long 0x1C 8. " [8] ,EMMC0_INT/USDHC0_INT status" "Not set,Set" bitfld.long 0x1C 4. " [4] ,UART3_INT status" "Not set,Set" newline bitfld.long 0x1C 3. " [3] ,UART2_INT status" "Not set,Set" bitfld.long 0x1C 2. " [2] ,UART1_INT status" "Not set,Set" bitfld.long 0x1C 1. " [1] ,UART0_INT status" "Not set,Set" line.long 0x20 "STATUS9,Interrupt Status 9 Register" bitfld.long 0x20 31. " STATUS[31] ,I2C3_INT status" "Not set,Set" bitfld.long 0x20 30. " [30] ,I2C2_INT status" "Not set,Set" bitfld.long 0x20 29. " [29] ,I2C1_INT status" "Not set,Set" bitfld.long 0x20 28. " [28] ,I2C0_INT status" "Not set,Set" newline bitfld.long 0x20 27. " [27] ,SPI3_INT status" "Not set,Set" bitfld.long 0x20 26. " [26] ,SPI2_INT status" "Not set,Set" bitfld.long 0x20 25. " [25] ,SPI1_INT status" "Not set,Set" bitfld.long 0x20 24. " [24] ,SPI0_INT status" "Not set,Set" newline bitfld.long 0x20 16. " [16] ,MU13_INT_B status" "Not set,Set" bitfld.long 0x20 15. " [15] ,MU12_INT_B status" "Not set,Set" bitfld.long 0x20 14. " [14] ,MU11_INT_B status" "Not set,Set" bitfld.long 0x20 13. " [13] ,MU10_INT_B status" "Not set,Set" newline bitfld.long 0x20 12. " [12] ,MU9_INT_B status" "Not set,Set" bitfld.long 0x20 11. " [11] ,MU8_INT_B status" "Not set,Set" bitfld.long 0x20 10. " [10] ,MU7_INT_B status" "Not set,Set" bitfld.long 0x20 9. " [9] ,MU6_INT_B status" "Not set,Set" newline bitfld.long 0x20 8. " [8] ,MU5_INT_B status" "Not set,Set" bitfld.long 0x20 0. " [0] ,MU13_INT_A status" "Not set,Set" line.long 0x24 "STATUS10,Interrupt Status 10 Register" bitfld.long 0x24 31. " STATUS[31] ,MU12_INT_A status" "Not set,Set" bitfld.long 0x24 30. " [30] ,MU11_INT_A status" "Not set,Set" bitfld.long 0x24 29. " [29] ,MU10_INT_A status" "Not set,Set" bitfld.long 0x24 28. " [28] ,MU9_INT_A status" "Not set,Set" newline bitfld.long 0x24 27. " [27] ,MU8_INT_A status" "Not set,Set" bitfld.long 0x24 26. " [26] ,MU7_INT_A status" "Not set,Set" bitfld.long 0x24 25. " [25] ,MU6_INT_A status" "Not set,Set" bitfld.long 0x24 24. " [24] ,MU5_INT_A status" "Not set,Set" newline bitfld.long 0x24 20. " [20] ,MU4_INT status" "Not set,Set" bitfld.long 0x24 19. " [19] ,MU3_INT status" "Not set,Set" bitfld.long 0x24 18. " [18] ,MU2_INT status" "Not set,Set" bitfld.long 0x24 17. " [17] ,MU1_INT status" "Not set,Set" newline bitfld.long 0x24 16. " [16] ,MU0_INT status" "Not set,Set" line.long 0x28 "STATUS11,Interrupt Status 11 Register" bitfld.long 0x28 15. " STATUS[15] ,GPIO_INT[7] status" "Not set,Set" bitfld.long 0x28 14. " [14] ,GPIO_INT[6] status" "Not set,Set" bitfld.long 0x28 13. " [13] ,GPIO_INT[5] status" "Not set,Set" bitfld.long 0x28 12. " [12] ,GPIO_INT[4] status" "Not set,Set" newline bitfld.long 0x28 11. " [11] ,GPIO_INT[3] status" "Not set,Set" bitfld.long 0x28 10. " [10] ,GPIO_INT[2] status" "Not set,Set" bitfld.long 0x28 9. " [9] ,GPIO_INT[1] status" "Not set,Set" bitfld.long 0x28 8. " [8] ,GPIO_INT[0] status" "Not set,Set" newline bitfld.long 0x28 3. " [3] ,PERF_CNT_INT status" "Not set,Set" bitfld.long 0x28 2. " [2] ,SBR_DONE_INT status" "Not set,Set" bitfld.long 0x28 1. " [1] ,ECC_NCORRECT_INT status" "Not set,Set" bitfld.long 0x28 0. " [0] ,ECC_CORRECT_INT status" "Not set,Set" line.long 0x2C "STATUS12,Interrupt Status 12 Register" bitfld.long 0x2C 27. " STATUS[27] ,SYS_COUNT_INT[3] status" "Not set,Set" bitfld.long 0x2C 26. " [26] ,SYS_COUNT_INT[2] status" "Not set,Set" bitfld.long 0x2C 25. " [25] ,SYS_COUNT_INT[1] status" "Not set,Set" bitfld.long 0x2C 24. " [24] ,SYS_COUNT_INT[0] status" "Not set,Set" newline bitfld.long 0x2C 23. " [23] ,INT_OUT[7] status" "Not set,Set" bitfld.long 0x2C 22. " [22] ,INT_OUT[6] status" "Not set,Set" bitfld.long 0x2C 21. " [21] ,INT_OUT[5] status" "Not set,Set" bitfld.long 0x2C 20. " [20] ,INT_OUT[4] status" "Not set,Set" newline bitfld.long 0x2C 19. " [19] ,INT_OUT[3] status" "Not set,Set" bitfld.long 0x2C 18. " [18] ,INT_OUT[2] status" "Not set,Set" bitfld.long 0x2C 17. " [17] ,INT_OUT[1] status" "Not set,Set" bitfld.long 0x2C 16. " [16] ,INT_OUT[0] status" "Not set,Set" newline bitfld.long 0x2C 15. " [15] ,PCIE9_GPIO_WAKEUP[1] status" "Not set,Set" bitfld.long 0x2C 14. " [14] ,PCIE9_GPIO_WAKEUP[0] status" "Not set,Set" bitfld.long 0x2C 13. " [13] ,PCIE0_SMLH_REQ_RST status" "Not set,Set" bitfld.long 0x2C 12. " [12] ,PCIE0_INT_A status" "Not set,Set" newline bitfld.long 0x2C 11. " [11] ,PCIE0_INT_B status" "Not set,Set" bitfld.long 0x2C 10. " [10] ,PCIE0_INT_C status" "Not set,Set" bitfld.long 0x2C 9. " [9] ,PCIE0_INT_D status" "Not set,Set" bitfld.long 0x2C 8. " [8] ,PCIE0_DMA_INT status" "Not set,Set" newline bitfld.long 0x2C 7. " [7] ,PCIE0_CLK_REQ_INT status" "Not set,Set" bitfld.long 0x2C 6. " [6] ,PCIE0_MSI_CTRL_INT status" "Not set,Set" bitfld.long 0x2C 5. " [5] ,PWM7_INT status" "Not set,Set" bitfld.long 0x2C 4. " [4] ,PWM6_INT status" "Not set,Set" newline bitfld.long 0x2C 3. " [3] ,PWM5_INT status" "Not set,Set" bitfld.long 0x2C 2. " [2] ,PWM4_INT status" "Not set,Set" bitfld.long 0x2C 1. " [1] ,PWM3_INT status" "Not set,Set" bitfld.long 0x2C 0. " [0] ,PWM2_INT status" "Not set,Set" line.long 0x30 "STATUS13,Interrupt Status 13 Register" bitfld.long 0x30 31. " STATUS[31] ,PWM1_INT status" "Not set,Set" bitfld.long 0x30 30. " [30] ,PWM0_INT status" "Not set,Set" bitfld.long 0x30 29. " [29] ,FLEXSPI1_INT status" "Not set,Set" bitfld.long 0x30 28. " [28] ,FLEXSPI0_INT status" "Not set,Set" newline bitfld.long 0x30 21. " [21] ,KPP0_INT status" "Not set,Set" bitfld.long 0x30 20. " [20] ,GPT4_INT status" "Not set,Set" bitfld.long 0x30 19. " [19] ,GPT3_INT status" "Not set,Set" bitfld.long 0x30 18. " [18] ,GPT2_INT status" "Not set,Set" newline bitfld.long 0x30 17. " [17] ,GPT1_INT status" "Not set,Set" bitfld.long 0x30 16. " [16] ,GPT0_INT status" "Not set,Set" bitfld.long 0x30 5. " [5] ,DMA3_ERR_INT status" "Not set,Set" bitfld.long 0x30 4. " [4] ,DMA3_INT status" "Not set,Set" newline bitfld.long 0x30 3. " [3] ,DMA2_ERR_INT status" "Not set,Set" bitfld.long 0x30 2. " [2] ,DMA2_INT status" "Not set,Set" bitfld.long 0x30 0. " [0] ,XAQ2_INTR status" "Not set,Set" line.long 0x34 "STATUS14,Interrupt Status 14 Register" bitfld.long 0x34 31. " STATUS[31] ,LCD_PWM_INT status" "Not set,Set" bitfld.long 0x34 30. " [30] ,LCD_MOD_INT status" "Not set,Set" bitfld.long 0x34 28. " [28] ,INT_OUT status" "Not set,Set" bitfld.long 0x34 27. " [27] ,INT_OUT status" "Not set,Set" newline bitfld.long 0x34 20. " [20] ,INT_OUT[12] status" "Not set,Set" bitfld.long 0x34 19. " [19] ,INT_OUT[11] status" "Not set,Set" bitfld.long 0x34 18. " [18] ,INT_OUT[10] status" "Not set,Set" bitfld.long 0x34 17. " [17] ,INT_OUT[9] status" "Not set,Set" newline bitfld.long 0x34 15. " [15] ,INT_OUT[7] status" "Not set,Set" bitfld.long 0x34 14. " [14] ,INT_OUT[6] status" "Not set,Set" bitfld.long 0x34 13. " [13] ,INT_OUT[5] status" "Not set,Set" bitfld.long 0x34 12. " [12] ,INT_OUT[4] status" "Not set,Set" newline bitfld.long 0x34 11. " [11] ,INT_OUT[3] status" "Not set,Set" bitfld.long 0x34 10. " [10] ,INT_OUT[2] status" "Not set,Set" bitfld.long 0x34 9. " [9] ,INT_OUT[1] status" "Not set,Set" bitfld.long 0x34 8. " [8] ,INT_OUT[0] status" "Not set,Set" line.long 0x38 "STATUS15,Interrupt Status 15 Register" bitfld.long 0x38 23. " STATUS[23] ,INT_OUT[7] status" "Not set,Set" bitfld.long 0x38 22. " [22] ,INT_OUT[6] status" "Not set,Set" bitfld.long 0x38 21. " [21] ,INT_OUT[5] status" "Not set,Set" bitfld.long 0x38 20. " [20] ,INT_OUT[4] status" "Not set,Set" newline bitfld.long 0x38 19. " [19] ,INT_OUT[3] status" "Not set,Set" bitfld.long 0x38 18. " [18] ,INT_OUT[2] status" "Not set,Set" bitfld.long 0x38 17. " [17] ,INT_OUT[1] status" "Not set,Set" bitfld.long 0x38 16. " [16] ,INT_OUT[0] status" "Not set,Set" newline bitfld.long 0x38 1. " [1] ,nEXTERRIRQ status" "Not set,Set" bitfld.long 0x38 0. " [0] ,nINTERRIRQ status" "Not set,Set" group.long 0xC4++0x03 line.long 0x00 "MINTDIS,Master Interrupt Disable Register" bitfld.long 0x00 7. " DISABLE[7] ,Disables interrupts from 511 to 448" "No,Yes" bitfld.long 0x00 6. " [6] ,Disables interrupts from 447 to 384" "No,Yes" bitfld.long 0x00 5. " [5] ,Disables interrupts from 383 to 320" "No,Yes" bitfld.long 0x00 4. " [4] ,Disables interrupts from 319 to 256" "No,Yes" newline bitfld.long 0x00 3. " [3] ,Disables interrupts from 255 to 192" "No,Yes" bitfld.long 0x00 2. " [2] ,Disables interrupts from 191 to 128" "No,Yes" bitfld.long 0x00 1. " [1] ,Disables interrupts from 127 to 64" "No,Yes" bitfld.long 0x00 0. " [0] ,Disables interrupts from 63 to 0" "No,Yes" newline rgroup.long 0xC8++0x03 line.long 0x00 "MSTRSTAT,Master Status Register" bitfld.long 0x00 0. " STATUS ,Status of all interrupts" "Not asserted,At least one interrupt is asserted" width 0x0B tree.end tree.end tree.end tree.open "MIPI DSI/LVDS 1" tree.open "MIPI_LVDS (MIPI-DSI/LVDS Controller)" tree "MIPI_LVDS_DSI_HOST" base ad:0x56248000 width 27. group.long 0x00++0x2B line.long 0x00 "CFG_NUM_LANES,MIPI DSI Host DSI Host Configuration Number Lanes" bitfld.long 0x00 0.--1. " CFG_NUM_LANES ,Number of active lanes that are to be used for transmitting data" "1 lane,2 lanes,3 lanes,4 lanes" line.long 0x04 "CFG_NONCONTINUOUS_CLK,MIPI DSI Host DSI Host Configuration Non-continuous Clock" bitfld.long 0x04 0. " CFG_NONCONTINUOUS_CLK ,Host controller into non-continuous MIPI clock mode" "Continuous,Non-continuous" line.long 0x08 "CFG_T_PRE,MIPI DSI Host DSI Host Configuration T PRE" hexmask.long.byte 0x08 0.--7. 1. " CFG_T_PRE ,Number of byte clock periods that the controller will wait after enabling the clock lane for HS operation before enabling the data lanes for HS operation" line.long 0x0C "CFG_T_POST,MIPI DSI Host DSI Host Configuration T Post" hexmask.long.byte 0x0C 0.--7. 1. " CFG_T_POST ,Number of byte clock periods to wait before putting the clock lane into LP mode after the data lanes have been detected to be in stop state" line.long 0x10 "CFG_TX_GAP,MIPI DSI Host DSI Host Configuration TX GAP" hexmask.long.byte 0x10 0.--7. 1. " CFG_TX_GAP ,Number of byte clock periods that the controller will wait after the clock lane has been put into LP mode before enabling the clock lane for HS mode again" line.long 0x14 "CFG_AUTOINSERT_EOTP,MIPI DSI Host DSI Host Configuration Autoinsert EOTP" bitfld.long 0x14 0. " CFG_AUTOINSERT_EOTP ,Enable the host controller to automatically insert an EoTp short packet when switching from HS to LP" "Not auto-inserted,Auto-inserted" line.long 0x18 "CFG_EXTRA_CMDS_AFTER_EOTP,MIPI DSI Host Controller Register" hexmask.long.byte 0x18 0.--7. 1. " CFG_EXTRA_CMDS_AFTER_EOTP ,Number of extra EOTP packets sent after the end of a packet" line.long 0x1C "CFG_HTX_TO_COUNT,MIPI DSI Host DSI Host Configuration HTX To Count" hexmask.long.tbyte 0x1C 0.--23. 1. " CFG_HTX_TO_COUNT ,Value of the DSI host high speed TX timeout count in clk_byte clock periods" line.long 0x20 "CFG_LRX_H_TO_COUNT,MIPI DSI Host DSI Host Configuration LRX H To Count" hexmask.long.tbyte 0x20 0.--23. 1. " CFG_LRX_H_TO_COUNT ,Value of the DSI host low power RX timeout count in clk_byte clock periods" line.long 0x24 "CFG_BTA_H_TO_COUNT,MIPI DSI Host DSI Host Configuration LRX H To Count" hexmask.long.tbyte 0x24 0.--23. 1. " CFG_BTA_H_TO_COUNT ,Value of the DSI host bus turn around (BTA) timeout in clk_byte clock periods" line.long 0x28 "CFG_TWAKEUP,MIPI DSI Host DSI Host Configuration TWAKEUP" hexmask.long.tbyte 0x28 0.--18. 1. " CFG_TWAKEUP ,Number of clk_esc clock periods to keep a clock or data lane in Mark-1 state after exiting ULPS" rgroup.long 0x2C++0x07 line.long 0x00 "CFG_STATUS_OUT,MIPI DSI Host DSI Host Configuration Status Out" line.long 0x04 "RX_ERROR_STATUS,MIPI DSI Host DSI Host RX Error Status" hexmask.long.word 0x04 0.--10. 1. " RX_ERROR_STATUS ,Status Register for Host receive error detection/ECC errors/CRC errors/timeout indicators" width 0x0B tree.end tree "MIPI_LVDS_DSI_HOST_DPI_INTFC" base ad:0x56248200 width 24. group.long 0x00++0x43 line.long 0x00 "PIXEL_PAYLOAD_SIZE,MIPI DSI Host DPI INTFC DSI Host Configuration DPI Pixel Payload Size" hexmask.long.word 0x00 0.--15. 1. " PIXEL_PAYLOAD_SIZE ,Maximum number of pixels that should be sent as one DSI packet" line.long 0x04 "PIXEL_FIFO_SEND_LEVEL,MIPI DSI Host DPI INTFC DSI Host Configuration DPI Pixel FIFO Send Level" hexmask.long.word 0x04 0.--15. 1. " PIXEL_FIFO_SEND_LEVEL ,In order to optimize DSI utility the DPI bridge buffers a certain number of DPI pixels before initiating a DSI packet" line.long 0x08 "INTERFACE_COLOR_CODING,MIPI DSI Host DPI INTFC DSI Host Configuration DPI Interface Color Coding" bitfld.long 0x08 0.--2. " INTERFACE_COLOR_CODING ,Distribution of RGB bits within the 24-bit d bus" "16-bit configuration 1,16-bit configuration 2,16-bit configuration 3,18-bit configuration 1,18-bit configuration 2,24-bit,?..." line.long 0x0C "PIXEL_FORMAT,MIPI DSI Host DPI INTFC DSI Host Configuration DPI Pixel Format" bitfld.long 0x0C 0.--1. " PIXEL_FORMAT ,DSI packet type of the pixels" "16-bit 1,18-bit 2,18-bit loosely packed,24-bit" line.long 0x10 "VSYNC_POLARITY,MIPI DSI Host DPI INTFC DSI Host Configuration DPI VSYNC Polarity" bitfld.long 0x10 0. " VSYNC_POLARITY ,Polarity of dpi_vsync_input" "Active low,Active high" line.long 0x14 "HSYNC_POLARITY,MIPI DSI Host DPI INTFC DSI Host Configuration DPI HSYNC Polarity" bitfld.long 0x14 0. " HSYNC_POLARITY ,Polarity of dpi_hsync_input" "Active low,Active high" line.long 0x18 "VIDEO_MODE,MIPI DSI Host DPI INTFC DSI Host Configuration DPI Video Mode" bitfld.long 0x18 0.--1. " VIDEO_MODE ,DSI video mode that the host DPI module should generate packets for" "Non-Burst with Sync Pulses,Non-Burst with Sync Events,Burst mode,?..." line.long 0x1C "HFP,MIPI DSI Host DPI INTFC DSI Host Configuration DPI HFP" hexmask.long.word 0x1C 0.--15. 1. " HFP ,DSI packet payload size" line.long 0x20 "HBP,MIPI DSI Host DPI INTFC DSI Host Configuration DPI HBP" hexmask.long.word 0x20 0.--15. 1. " HBP ,DSI packet payload size" line.long 0x24 "HSA,MIPI DSI Host DPI INTFC DSI Host Configuration DPI HSA" hexmask.long.word 0x24 0.--15. 1. " HSA ,DSI packet payload size" line.long 0x28 "ENABLE_MULT_PKTS,MIPI DSI Host DPI INTFC DSI Host Configuration DPI Enable MULT PKTS" bitfld.long 0x28 0. " ENABLE_MULT_PKTS ,Multiple packets per video line" "Single packet,Two packets" line.long 0x2C "VBP,MIPI DSI Host DPI INTFC DSI Host Configuration DPI VBP" hexmask.long.byte 0x2C 0.--7. 1. " VBP ,Number of lines in the vertical back porch" line.long 0x30 "VFP,MIPI DSI Host DPI INTFC DSI Host Configuration DPI VFP" hexmask.long.byte 0x30 0.--7. 1. " VFP ,Number of lines in the vertical front porch" line.long 0x34 "BLLP_MODE,MIPI DSI Host DPI INTF DSI Host Configuration DPI BLLP Mode" bitfld.long 0x34 0. " BLLP_MODE ,Optimize bllp periods to low power mode when possible" "Blanking packets sent during BLLP periods,LP mode used for BLLP periods" line.long 0x38 "USE_NULL_PKT_BLLP,MIPI DSI Host DPI INTFC DSI Host Configuration DPI Use Null PKT BLLP" bitfld.long 0x38 0. " USE_NULL_PKT_BLLP ,Type of blanking packet to be sent during bllp region" "Blanking packet used in BLLP region,Null packet used in BLLP region" line.long 0x3C "VACTIVE,MIPI DSI Host DPI INTFC DSI Host Configuration DPI Vactive" hexmask.long.word 0x3C 0.--13. 1. " VACTIVE ,Number of lines in the vertical active area" line.long 0x40 "VC,MIPI DSI Host DPI INTFC DSI Host Configuration DPI VC" bitfld.long 0x40 0.--1. " VC ,Virtual channel (VC) of packets that will be sent to the receive packet interface" "0,1,2,3" width 0x0B tree.end tree "MIPI_LVDS_DSI_HOST_APB" base ad:0x56248280 width 19. group.long 0x00++0x0B line.long 0x00 "TX_PAYLOAD,MIPI DSI Host APB PKT IF DSI Host TX Payload" line.long 0x04 "PKT_CONTROL,MIPI DSI Host APB PKT IF DSI Host PKT Control" hexmask.long 0x04 0.--26. 1. " PKT_CONTROL ,Tx packet control register" line.long 0x08 "SEND_PACKET,MIPI DSI Host APB PKT IF DSI Host Send Packet" bitfld.long 0x08 0. " SEND_PACKET ,Tx send packet" "Not sent,Sent" rgroup.long 0x0C++0x13 line.long 0x00 "PKT_STATUS,MIPI DSI Host APB PKT IF DSI PKT Status" hexmask.long.word 0x00 0.--8. 1. " PKT_STATUS ,Status of APB to packet interface" line.long 0x04 "PKT_FIFO_WR_LEVEL,MIPI DSI Host APB PKT IF DSI Host PKT FIFO WR Level" hexmask.long.word 0x04 0.--15. 1. " PKT_FIFO_WR_LEVEL ,Write level of APB to pkt interface FIFO" line.long 0x08 "PKT_FIFO_RD_LEVEL,MIPI DSI Host APB PKT IF DSI Host PKT FIFO RD Level" hexmask.long.word 0x08 0.--15. 1. " PKT_FIFO_RD_LEVEL ,Read level of APB to pkt interface FIFO" line.long 0x0C "PKT_RX_PAYLOAD,MIPI DSI Host APB PKT IF DSI Host PKT RX Payload" line.long 0x10 "PKT_RX_PKT_HEADER,MIPI DSI Host APB PKT IF DSI Host PKT RX PKT Header" hexmask.long.tbyte 0x10 0.--23. 1. " PKT_RX_PKT_HEADER ,APB to pkt interface rx packet header" rgroup.long 0x20++0x07 line.long 0x00 "IRQ_STATUS,MIPI DSI Host APB PKT IF DSI Host Interrupt Status" line.long 0x04 "IRQ_STATUS2,MIPI DSI Host APB PKT IF DSI Host Interrupt Status 2" bitfld.long 0x04 0.--2. " IRQ_STATUS2 ,Status of APB to packet interface part 2" "Single bit ECC error,Multi bit ECC error,CRC error,?..." group.long 0x28++0x07 line.long 0x00 "IRQ_MASK,MIPI DSI Host APB PKT IF DSI Host Interrupt Mask" bitfld.long 0x00 31. " MASK[31:0] ,IRQ_STATUS bit 31 mask" "0,1" bitfld.long 0x00 30. ",IRQ_STATUS bit 30 mask" "0,1" bitfld.long 0x00 29. ",IRQ_STATUS bit 29 mask" "0,1" bitfld.long 0x00 28. ",IRQ_STATUS bit 28 mask" "0,1" bitfld.long 0x00 27. ",IRQ_STATUS bit 27 mask" "0,1" bitfld.long 0x00 26. ",IRQ_STATUS bit 26 mask" "0,1" bitfld.long 0x00 25. ",IRQ_STATUS bit 25 mask" "0,1" bitfld.long 0x00 24. ",IRQ_STATUS bit 24 mask" "0,1" bitfld.long 0x00 23. ",IRQ_STATUS bit 23 mask" "0,1" bitfld.long 0x00 22. ",IRQ_STATUS bit 22 mask" "0,1" bitfld.long 0x00 21. ",IRQ_STATUS bit 21 mask" "0,1" bitfld.long 0x00 20. ",IRQ_STATUS bit 20 mask" "0,1" bitfld.long 0x00 19. ",IRQ_STATUS bit 19 mask" "0,1" bitfld.long 0x00 18. ",IRQ_STATUS bit 18 mask" "0,1" bitfld.long 0x00 17. ",IRQ_STATUS bit 17 mask" "0,1" bitfld.long 0x00 16. ",IRQ_STATUS bit 16 mask" "0,1" bitfld.long 0x00 15. ",IRQ_STATUS bit 15 mask" "0,1" bitfld.long 0x00 14. ",IRQ_STATUS bit 14 mask" "0,1" bitfld.long 0x00 13. ",IRQ_STATUS bit 13 mask" "0,1" bitfld.long 0x00 12. ",IRQ_STATUS bit 12 mask" "0,1" bitfld.long 0x00 11. ",IRQ_STATUS bit 11 mask" "0,1" bitfld.long 0x00 10. ",IRQ_STATUS bit 10 mask" "0,1" bitfld.long 0x00 9. ",IRQ_STATUS bit 9 mask" "0,1" bitfld.long 0x00 8. ",IRQ_STATUS bit 8 mask" "0,1" bitfld.long 0x00 7. ",IRQ_STATUS bit 7 mask" "0,1" bitfld.long 0x00 6. ",IRQ_STATUS bit 6 mask" "0,1" bitfld.long 0x00 5. ",IRQ_STATUS bit 5 mask" "0,1" bitfld.long 0x00 4. ",IRQ_STATUS bit 4 mask" "0,1" bitfld.long 0x00 3. ",IRQ_STATUS bit 3 mask" "0,1" bitfld.long 0x00 2. ",IRQ_STATUS bit 2 mask" "0,1" bitfld.long 0x00 1. ",IRQ_STATUS bit 1 mask" "0,1" bitfld.long 0x00 0. ",IRQ_STATUS bit 0 mask" "0,1" line.long 0x04 "IRQ_MASK2,MIPI DSI Host APB PKT IF DSI Host Interrupt Mask 2" bitfld.long 0x04 2. " MASK[2:0] ,IRQ_STATUS2 bit 2 mask" "0,1" bitfld.long 0x04 1. ",IRQ_STATUS2 bit 1 mask" "0,1" bitfld.long 0x04 0. ",IRQ_STATUS2 bit 0 mask" "0,1" width 0x0B tree.end tree "MIPI_LVDS_DSI_HOST_NXP_FDSOI28_DPHY_INTFC" base ad:0x56248300 width 19. group.long 0x00++0x2F line.long 0x00 "PD_TX,DPHY PD_TX Input Control Register" bitfld.long 0x00 0. " PD_TX ,DPHY PD_TX input control" "0,1" line.long 0x04 "M_PRG_HS_PREPARE,DPHY M_PRG_HS_PREPARE Input Register" bitfld.long 0x04 0.--1. " M_PRG_HS_PREPARE ,DPHY M_PRG_HS_PREPARE input" "0,1,2,3" line.long 0x08 "MC_PRG_HS_PREPARE,DPHY MC_PRG_HS_PREPARE Input Register" bitfld.long 0x08 0. " MC_PRG_HS_PREPARE ,DPHY MC_PRG_HS_PREPARE input" "0,1" line.long 0x0C "M_PRG_HS_ZERO,DPHY M_PRG_HS_ZERO Input Register" bitfld.long 0x0C 0.--4. " M_PRG_HS_ZERO ,DPHY M_PRG_HS_ZERO input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "MC_PRG_HS_ZERO,DPHY MC_PRG_HS_ZERO Input Register" bitfld.long 0x10 0.--5. " MC_PRG_HS_ZERO ,DPHY MC_PRG_HS_ZERO input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x14 "M_PRG_HS_TRAIL,DPHY M_PRG_HS_TRAL Input Register" bitfld.long 0x14 0.--3. " M_PRG_HS_TRAIL ,DPHY M_PRG_HS_TRAIL input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "MC_PRG_HS_TRAIL,DPHY MC_PRG_HS_TRAL Input Register" bitfld.long 0x18 0.--3. " M_PRG_HS_TRAIL ,DPHY M_PRG_HS_TRAIL input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x1C "PD_PLL,DPHY PD_PLL Input Register" bitfld.long 0x1C 0. " PD_PLL ,DPHY PD_PLL input" "0,1" line.long 0x20 "TST,DPHY TST Input Register" bitfld.long 0x20 0.--5. " TST ,DPHY TST input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x24 "CN,DPHY CN Input Register" bitfld.long 0x24 0.--4. " CN ,DPHY CN input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x28 "CM,DPHY CM Input Register" hexmask.long.byte 0x28 0.--7. 1. " CM ,DPHY CM input" line.long 0x2C "CO,DPHY CO Input Register" bitfld.long 0x2C 0.--1. " CO ,DPHY CO input" "0,1,2,3" rgroup.long 0x30++0x03 line.long 0x00 "LOCK,DPHY PLL LOCK Output Register" bitfld.long 0x00 0. " LOCK ,DPHY PLL LOCK output" "Unlocked,Locked" group.long 0x34++0x13 line.long 0x00 "LOCK_BYP,DPHY LOCK_BYP Input Register" bitfld.long 0x00 0. " LOCK_BYP ,DPHY LOCK_BYP input" "Unlocked,Locked" line.long 0x04 "TX_RCAL,DPHY RTERM_SEL Input Register" bitfld.long 0x04 0.--1. " TX_RCAL ,DPHY RTERM_SEL input" "0,1,2,3" line.long 0x08 "AUTO_PD_EN,DPHY AUTO_PD_EN Input Register" bitfld.long 0x08 0. " AUTO_PD_EN ,DPHY AUTO_PD_EN input" "Disabled,Enabled" line.long 0x0C "RXLPRP,DPHY RXLPRP Input Register" bitfld.long 0x0C 0.--1. " RXLPRP ,DPHY RXLPRP input" "0,1,2,3" line.long 0x10 "RXCDRP,DPHY RXCDRP Input Register" bitfld.long 0x10 0.--1. " RXCDRP ,DPHY RXCDRP input" "0,1,2,3" width 0x0B tree.end tree.end tree "I2C0 (I2C Controller)" base ad:0x56246000 width 8. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number" line.long 0x04 "PARAM,Parameter Register" bitfld.long 0x04 8.--11. " MRXFIFO ,Master receive FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x04 0.--3. " MTXFIFO ,Master transmit FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" group.long 0x10++0x13 line.long 0x00 "MCR,Master Control Register" bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset" bitfld.long 0x00 3. " DBGEN ,Debug enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " MEN ,Master enable" "Disabled,Enabled" line.long 0x04 "MSR,Master Status Register" rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x04 24. " MBF ,Master busy flag" "Idle,Busy" eventfld.long 0x04 14. " DMF ,Data match flag" "Not received,Received" eventfld.long 0x04 13. " PLTF ,Pin low timeout flag" "Not occurred/disabled,Occurred" newline eventfld.long 0x04 12. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x04 11. " ALF ,Arbitration lost flag" "Not lost,Lost" eventfld.long 0x04 10. " NDF ,NACK detect flag" "Not detected,Detected" eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected" newline eventfld.long 0x04 8. " EPF ,End packet flag" "Not generated/Repeated,Generated/Repeated" rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "MIER,Master Interrupt Enable Register" bitfld.long 0x08 14. " DMIE ,Data match interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " PLTIE ,Pin low timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " FEIE ,FIFO error interrupt disable" "No,Yes" newline bitfld.long 0x08 11. " ALIE ,Arbitration lost interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " NDIE ,NACK detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " EPIE ,End packet interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "MDER,Master DMA Enable Register" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" line.long 0x10 "MCFGR0,Master Configuration Register 0" bitfld.long 0x10 9. " RDMO ,Receive data match only" "Stored,Discarded" bitfld.long 0x10 8. " CIRFIFO ,Circular FIFO enable" "Disabled,Enabled" bitfld.long 0x10 2. " HRSEL ,Host request select" "HREQ pin,Input trigger" newline bitfld.long 0x10 1. " HRPOL ,Host request polarity" "Active low,Active high" bitfld.long 0x10 0. " HREN ,Host request enable" "Disabled,Enabled" newline if (((per.l(ad:0x56246000+0x10))&0x01)==0x01) rgroup.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Disabled,,1st word = MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "SCL,SCL or SDA" newline bitfld.long 0x00 9. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "No effect,Enabled" bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" else group.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Disabled,,1st word = MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "On SCL low too long,On SCL or SDA low too long" newline bitfld.long 0x00 9. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "No effect,Enabled" bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" endif newline if ((((per.l(ad:0x56246000+0x10))&0x01)==0x00)||(((per.l(ad:0x56246000+0x14))&0x1000000)==0x00)) group.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" else rgroup.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" endif if (((per.l(ad:0x56246000+0x10))&0x01)==0x01) rgroup.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x58++0x03 line.long 0x00 "MFCR,Master FIFO Control Register" bitfld.long 0x00 16.--17. " RXWATER ,Receive FIFO watermark" "0,1,2,3" bitfld.long 0x00 0.--1. " TXWATER ,Transmit FIFO watermark" "0,1,2,3" rgroup.long 0x5C++0x03 line.long 0x00 "MFSR,Master FIFO Status Register" bitfld.long 0x00 16.--18. " RXCOUNT ,Receive FIFO count" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " TXCOUNT ,Transmit FIFO count" "0,1,2,3,4,5,6,7" newline wgroup.long 0x60++0x03 line.long 0x00 "MTDR,Master Transmit Data Register" bitfld.long 0x00 8.--10. " CMD ,Command data" "Transmit,Receive,Generate STOP,Receive and discard,START and transmit,START and transmit (NACK returned),START and transmit (high speed mode),START and transmit high speed mode (NACK returned)" newline hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data" newline hgroup.long 0x70++0x03 hide.long 0x00 "MRDR,Master Receive Data Register" in newline group.long 0x110++0x0F line.long 0x00 "SCR,Slave Control Register" bitfld.long 0x00 9. " RRF ,Receive FIFO reset" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Transmit FIFO reset" "No effect,Reset" bitfld.long 0x00 5. " FILTDZ ,Filter doze enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " FILTEN ,Filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " SEN ,Slave enable" "Disabled,Enabled" line.long 0x04 "SSR,Slave Status Register" rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x04 24. " SBF ,Slave busy flag" "Idle,Busy" rbitfld.long 0x04 15. " SARF ,SMBus alert response flag" "Not detected,Detected" rbitfld.long 0x04 14. " GCF ,General call flag" "Not detected,Detected" newline rbitfld.long 0x04 13. " AM1F ,Address match 1 flag" "Not matched,Matched" rbitfld.long 0x04 12. " AM0F ,Address match 0 flag" "Not matched,Matched" eventfld.long 0x04 11. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x04 10. " BEF ,Bit error flag" "No error,Error" newline eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected" eventfld.long 0x04 8. " RSF ,Repeated start flag" "Not detected,Detected" rbitfld.long 0x04 3. " TAF ,Transmit ACK flag" "Not required,Required" rbitfld.long 0x04 2. " AVF ,Address valid flag" "Invalid,Valid" newline rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "SIER,Slave Interrupt Enable Register" bitfld.long 0x08 15. " SARIE ,SMBus alert response interrupt enable" "Disabled,Enabled" bitfld.long 0x08 14. " GCIE ,General call interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " AM1F ,Address match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " AM0IE ,Address match 0 interrupt disable" "No,Yes" newline bitfld.long 0x08 11. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " BEIE ,Bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 8. " RSIE ,Repeated start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " TAIE ,Transmit ACK interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " AVIE ,Address valid interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "SDER,Slave DMA Enable Register" bitfld.long 0x0C 2. " AVDE ,Address valid DMA enable" "Disabled,Enabled" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" newline if (((per.l(ad:0x56246000+0x110))&0x01)==0x01) rgroup.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration match" "0 (7-bit),0 (10-bit),0 (7-bit) / 1 (7-bit),0 (10-bit) / 1 (10-bit),0 (7-bit) / 1 (10-bit),0 (10-bit) / 1 (7-bit),From 0 (7-bit) to 1 (7-bit),From 0 (10-bit) to 1 (10-bit)" bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" bitfld.long 0x00 12. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return data / clear RDF,Return address / clear AVF" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer,On TDR empty" bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration match" "0 (7-bit),0 (10-bit),0 (7-bit) / 1 (7-bit),0 (10-bit) / 1 (10-bit),0 (7-bit) / 1 (10-bit),0 (10-bit) / 1 (7-bit),From 0 (7-bit) to 1 (7-bit),From 0 (10-bit) to 1 (10-bit)" bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" bitfld.long 0x00 12. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return data / clear RDF,Return address / clear AVF" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer,On TDR empty" bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline if (((per.l(ad:0x56246000+0x110))&0x01)==0x01) rgroup.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" else group.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" endif rgroup.long 0x150++0x03 line.long 0x00 "SASR,Slave Address Status Register" bitfld.long 0x00 14. " ANV ,Address invalid" "No,Yes" hexmask.long.word 0x00 0.--10. 0x01 " RADDR ,Received address" if (((per.l(ad:0x56246000+0x124))&0x08)==0x08) group.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,NACK transmit" "ACK,NACK" else rgroup.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,NACK transmit" "ACK,NACK" endif wgroup.long 0x160++0x03 line.long 0x00 "STDR,Slave Transmit Data Register" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data" rgroup.long 0x170++0x03 line.long 0x00 "SRDR,Slave Receive Data Register" bitfld.long 0x00 15. " SOF ,Start of frame" "Not the first data word,First data word" bitfld.long 0x00 14. " RXEMPTY ,RX empty" "Not empty,Empty" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data receive" width 0x0B tree.end tree "PWM (Pulse Width Modulation)" base ad:0x56244000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO water mark (FIFO empty flag set threshold)" ">= 1 empty slot,>= 2 empty slots,>= 3 empty slots,>= 4 empty slots" bitfld.long 0x00 25. " STOPEN ,Stop mode enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait mode enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " DBGEN ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte data swap control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word data swap control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM output configuration" "Set=rollover/Cleared=comparison,Set=comparison/Cleared=rollover,Disconnected,Disconnected" newline bitfld.long 0x00 16.--17. " CLKSRC ,Clock source select" "Off,IPG_CLK,IPG_CLK_HIGHFREQ,IPG_CLK_32K" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter clock prescaler value" bitfld.long 0x00 3. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample repeat" "Once,Twice,Four times,Eight times" newline bitfld.long 0x00 0. " EN ,PWM enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO write error status" "No error,Error" eventfld.long 0x04 5. " CMP ,Compare event status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over event status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO empty status" "Not empty,Empty" newline rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO available" "No available,1 word,2 words,3 words,4 words,?..." line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO empty interrupt enable" "Disabled,Enabled" line.long 0x0C "PWMSAR,PWM Sample Register" hexmask.long.word 0x0C 0.--15. 1. " SAMPLE ,Sample value" line.long 0x10 "PWMPR,PWM Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Period value" rgroup.long 0x14++0x03 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" width 0x0B tree.end tree "GPIO (General Purpose Input/Output)" base ad:0x56242000 width 11. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data Register" bitfld.long 0x00 31. " DR[31] ,Data bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,Data bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,Data bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,Data bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,Data bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,Data bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,Data bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,Data bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,Data bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,Data bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,Data bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,Data bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,Data bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,Data bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,Data bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,Data bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,Data bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,Data bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,Data bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,Data bit 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,Data bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,Data bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,Data bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,Data bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,Data bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,Data bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,Data bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,Data bit 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,Data bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,Data bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,Data bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,Data bit 0" "Low,High" line.long 0x04 "GDIR,GPIO Direction Register" bitfld.long 0x04 31. " GDIR[31] ,GPIO direction 31 bit" "Input,Output" bitfld.long 0x04 30. " [30] ,GPIO direction 30 bit" "Input,Output" bitfld.long 0x04 29. " [29] ,GPIO direction 29 bit" "Input,Output" bitfld.long 0x04 28. " [28] ,GPIO direction 28 bit" "Input,Output" newline bitfld.long 0x04 27. " [27] ,GPIO direction 27 bit" "Input,Output" bitfld.long 0x04 26. " [26] ,GPIO direction 26 bit" "Input,Output" bitfld.long 0x04 25. " [25] ,GPIO direction 25 bit" "Input,Output" bitfld.long 0x04 24. " [24] ,GPIO direction 24 bit" "Input,Output" newline bitfld.long 0x04 23. " [23] ,GPIO direction 23 bit" "Input,Output" bitfld.long 0x04 22. " [22] ,GPIO direction 22 bit" "Input,Output" bitfld.long 0x04 21. " [21] ,GPIO direction 21 bit" "Input,Output" bitfld.long 0x04 20. " [20] ,GPIO direction 20 bit" "Input,Output" newline bitfld.long 0x04 19. " [19] ,GPIO direction 19 bit" "Input,Output" bitfld.long 0x04 18. " [18] ,GPIO direction 18 bit" "Input,Output" bitfld.long 0x04 17. " [17] ,GPIO direction 17 bit" "Input,Output" bitfld.long 0x04 16. " [16] ,GPIO direction 16 bit" "Input,Output" newline bitfld.long 0x04 15. " [15] ,GPIO direction 15 bit" "Input,Output" bitfld.long 0x04 14. " [14] ,GPIO direction 14 bit" "Input,Output" bitfld.long 0x04 13. " [13] ,GPIO direction 13 bit" "Input,Output" bitfld.long 0x04 12. " [12] ,GPIO direction 12 bit" "Input,Output" newline bitfld.long 0x04 11. " [11] ,GPIO direction 11 bit" "Input,Output" bitfld.long 0x04 10. " [10] ,GPIO direction 10 bit" "Input,Output" bitfld.long 0x04 9. " [9] ,GPIO direction 9 bit" "Input,Output" bitfld.long 0x04 8. " [8] ,GPIO direction 8 bit" "Input,Output" newline bitfld.long 0x04 7. " [7] ,GPIO direction 7 bit" "Input,Output" bitfld.long 0x04 6. " [6] ,GPIO direction 6 bit" "Input,Output" bitfld.long 0x04 5. " [5] ,GPIO direction 5 bit" "Input,Output" bitfld.long 0x04 4. " [4] ,GPIO direction 4 bit" "Input,Output" newline bitfld.long 0x04 3. " [3] ,GPIO direction 3 bit" "Input,Output" bitfld.long 0x04 2. " [2] ,GPIO direction 2 bit" "Input,Output" bitfld.long 0x04 1. " [1] ,GPIO direction 1 bit" "Input,Output" bitfld.long 0x04 0. " [0] ,GPIO direction 0 bit" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO Pad Status Register" bitfld.long 0x00 31. " PSR[31] ,GPIO pad status bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,GPIO pad status bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,GPIO pad status bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,GPIO pad status bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,GPIO pad status bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,GPIO pad status bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,GPIO pad status bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,GPIO pad status bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,GPIO pad status bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,GPIO pad status bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,GPIO pad status bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,GPIO pad status bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,GPIO pad status bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,GPIO pad status bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,GPIO pad status bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,GPIO pad status bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,GPIO pad status bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,GPIO pad status bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,GPIO pad status bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,GPIO pad status bit 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,GPIO pad status bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,GPIO pad status bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,GPIO pad status bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,GPIO pad status bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,GPIO pad status bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,GPIO pad status bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,GPIO pad status bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,GPIO pad status bit 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,GPIO pad status bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,GPIO pad status bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,GPIO pad status bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,GPIO pad status bit 0" "Low,High" group.long 0x0C++0x13 line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1" bitfld.long 0x00 30.--31. " ICR[15] ,Controls the active condition of the interrupt function for GPIO interrupt 15" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 28.--29. " [14] ,Controls the active condition of the interrupt function for GPIO interrupt 14" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 26.--27. " [13] ,Controls the active condition of the interrupt function for GPIO interrupt 13" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 24.--25. " [12] ,Controls the active condition of the interrupt function for GPIO interrupt 12" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 22.--23. " [11] ,Controls the active condition of the interrupt function for GPIO interrupt 11" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 20.--21. " [10] ,Controls the active condition of the interrupt function for GPIO interrupt 10" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 18.--19. " [9] ,Controls the active condition of the interrupt function for GPIO interrupt 9" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 16.--17. " [8] ,Controls the active condition of the interrupt function for GPIO interrupt 8" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 14.--15. " [7] ,Controls the active condition of the interrupt function for GPIO interrupt 7" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 12.--13. " [6] ,Controls the active condition of the interrupt function for GPIO interrupt 6" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 10.--11. " [5] ,Controls the active condition of the interrupt function for GPIO interrupt 5" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 8.--9. " [4] ,Controls the active condition of the interrupt function for GPIO interrupt 4" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 6.--7. " [3] ,Controls the active condition of the interrupt function for GPIO interrupt 3" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 4.--5. " [2] ,Controls the active condition of the interrupt function for GPIO interrupt 2" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 2.--3. " [1] ,Controls the active condition of the interrupt function for GPIO interrupt 1" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 0.--1. " [0] ,Controls the active condition of the interrupt function for GPIO interrupt 0" "Low-level,High-level,Rising-edge,Falling-edge" line.long 0x04 "ICR2,GPIO Interrupt Configuration Register 2" bitfld.long 0x04 30.--31. " [31] ,Controls the active condition of the interrupt function for GPIO interrupt 31" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 28.--29. " [30] ,Controls the active condition of the interrupt function for GPIO interrupt 30" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 26.--27. " [29] ,Controls the active condition of the interrupt function for GPIO interrupt 29" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 24.--25. " [28] ,Controls the active condition of the interrupt function for GPIO interrupt 28" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 22.--23. " [27] ,Controls the active condition of the interrupt function for GPIO interrupt 27" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 20.--21. " [26] ,Controls the active condition of the interrupt function for GPIO interrupt 26" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 18.--19. " [25] ,Controls the active condition of the interrupt function for GPIO interrupt 25" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 16.--17. " [24] ,Controls the active condition of the interrupt function for GPIO interrupt 24" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 14.--15. " [23] ,Controls the active condition of the interrupt function for GPIO interrupt 23" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 12.--13. " [22] ,Controls the active condition of the interrupt function for GPIO interrupt 22" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 10.--11. " [21] ,Controls the active condition of the interrupt function for GPIO interrupt 21" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 8.--9. " [20] ,Controls the active condition of the interrupt function for GPIO interrupt 20" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 6.--7. " [19] ,Controls the active condition of the interrupt function for GPIO interrupt 19" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 4.--5. " [18] ,Controls the active condition of the interrupt function for GPIO interrupt 18" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 2.--3. " [17] ,Controls the active condition of the interrupt function for GPIO interrupt 17" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 0.--1. " [16] ,Controls the active condition of the interrupt function for GPIO interrupt 16" "Low-level,High-level,Rising-edge,Falling-edge" line.long 0x08 "IMR,GPIO Interrupt Mask Register" bitfld.long 0x08 31. " IMR[31] ,Interrupt 31 mask bit" "Disabled,Enabled" bitfld.long 0x08 30. " [30] ,Interrupt 30 mask bit" "Disabled,Enabled" bitfld.long 0x08 29. " [29] ,Interrupt 29 mask bit" "Disabled,Enabled" bitfld.long 0x08 28. " [28] ,Interrupt 28 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 27. " [27] ,Interrupt 27 mask bit" "Disabled,Enabled" bitfld.long 0x08 26. " [26] ,Interrupt 26 mask bit" "Disabled,Enabled" bitfld.long 0x08 25. " [25] ,Interrupt 25 mask bit" "Disabled,Enabled" bitfld.long 0x08 24. " [24] ,Interrupt 24 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 23. " [23] ,Interrupt 23 mask bit" "Disabled,Enabled" bitfld.long 0x08 22. " [22] ,Interrupt 22 mask bit" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Interrupt 21 mask bit" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Interrupt 20 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 19. " [19] ,Interrupt 19 mask bit" "Disabled,Enabled" bitfld.long 0x08 18. " [18] ,Interrupt 18 mask bit" "Disabled,Enabled" bitfld.long 0x08 17. " [17] ,Interrupt 17 mask bit" "Disabled,Enabled" bitfld.long 0x08 16. " [16] ,Interrupt 16 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 15. " [15] ,Interrupt 15 mask bit" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Interrupt 14 mask bit" "Disabled,Enabled" bitfld.long 0x08 13. " [13] ,Interrupt 13 mask bit" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Interrupt 12 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 11. " [11] ,Interrupt 11 mask bit" "Disabled,Enabled" bitfld.long 0x08 10. " [10] ,Interrupt 10 mask bit" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Interrupt 9 mask bit" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Interrupt 8 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Interrupt 7 mask bit" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Interrupt 6 mask bit" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Interrupt 5 mask bit" "Disabled,Enabled" bitfld.long 0x08 4. " [4] ,Interrupt 4 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 3. " [3] ,Interrupt 3 mask bit" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Interrupt 2 mask bit" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Interrupt 1 mask bit" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Interrupt 0 mask bit" "Disabled,Enabled" line.long 0x0C "ISR,GPIO Interrupt Status Register" eventfld.long 0x0C 31. " ISR[31] ,Interrupt 31 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 30. " [30] ,Interrupt 30 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 29. " [29] ,Interrupt 29 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 28. " [28] ,Interrupt 28 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 27. " [27] ,Interrupt 27 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 26. " [26] ,Interrupt 26 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 25. " [25] ,Interrupt 25 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 24. " [24] ,Interrupt 24 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 23. " [23] ,Interrupt 23 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 22. " [22] ,Interrupt 22 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 21. " [21] ,Interrupt 21 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 20. " [20] ,Interrupt 20 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 19. " [19] ,Interrupt 19 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 18. " [18] ,Interrupt 18 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 17. " [17] ,Interrupt 17 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 16. " [16] ,Interrupt 16 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 15. " [15] ,Interrupt 15 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 14. " [14] ,Interrupt 14 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 13. " [13] ,Interrupt 13 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 12. " [12] ,Interrupt 12 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 11. " [11] ,Interrupt 11 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 10. " [10] ,Interrupt 10 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 9. " [9] ,Interrupt 9 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 8. " [8] ,Interrupt 8 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 7. " [7] ,Interrupt 7 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 6. " [6] ,Interrupt 6 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 5. " [5] ,Interrupt 5 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 4. " [4] ,Interrupt 4 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 3. " [3] ,Interrupt 3 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 2. " [2] ,Interrupt 2 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 1. " [1] ,Interrupt 1 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 0. " [0] ,Interrupt 0 status bit" "No interrupt,Interrupt" line.long 0x10 "EDGE_SEL,GPIO Edge Select Register" bitfld.long 0x10 31. " GPIO_EDGE_SEL[31] ,Edge select bit 31" "31 setting,Any edge" bitfld.long 0x10 30. " [30] ,Edge select bit 30" "30 setting,Any edge" bitfld.long 0x10 29. " [29] ,Edge select bit 29" "29 setting,Any edge" bitfld.long 0x10 28. " [28] ,Edge select bit 28" "28 setting,Any edge" newline bitfld.long 0x10 27. " [27] ,Edge select bit 27" "27 setting,Any edge" bitfld.long 0x10 26. " [26] ,Edge select bit 26" "26 setting,Any edge" bitfld.long 0x10 25. " [25] ,Edge select bit 25" "25 setting,Any edge" bitfld.long 0x10 24. " [24] ,Edge select bit 24" "24 setting,Any edge" newline bitfld.long 0x10 23. " [23] ,Edge select bit 23" "23 setting,Any edge" bitfld.long 0x10 22. " [22] ,Edge select bit 22" "22 setting,Any edge" bitfld.long 0x10 21. " [21] ,Edge select bit 21" "21 setting,Any edge" bitfld.long 0x10 20. " [20] ,Edge select bit 20" "20 setting,Any edge" newline bitfld.long 0x10 19. " [19] ,Edge select bit 19" "19 setting,Any edge" bitfld.long 0x10 18. " [18] ,Edge select bit 18" "18 setting,Any edge" bitfld.long 0x10 17. " [17] ,Edge select bit 17" "17 setting,Any edge" bitfld.long 0x10 16. " [16] ,Edge select bit 16" "16 setting,Any edge" newline bitfld.long 0x10 15. " [15] ,Edge select bit 15" "15 setting,Any edge" bitfld.long 0x10 14. " [14] ,Edge select bit 14" "14 setting,Any edge" bitfld.long 0x10 13. " [13] ,Edge select bit 13" "13 setting,Any edge" bitfld.long 0x10 12. " [12] ,Edge select bit 12" "12 setting,Any edge" newline bitfld.long 0x10 11. " [11] ,Edge select bit 11" "11 setting,Any edge" bitfld.long 0x10 10. " [10] ,Edge select bit 10" "10 setting,Any edge" bitfld.long 0x10 9. " [9] ,Edge select bit 9" "9 setting,Any edge" bitfld.long 0x10 8. " [8] ,Edge select bit 8" "8 setting,Any edge" newline bitfld.long 0x10 7. " [7] ,Edge select bit 7" "7 setting,Any edge" bitfld.long 0x10 6. " [6] ,Edge select bit 6" "6 setting,Any edge" bitfld.long 0x10 5. " [5] ,Edge select bit 5" "5 setting,Any edge" bitfld.long 0x10 4. " [4] ,Edge select bit 4" "4 setting,Any edge" newline bitfld.long 0x10 3. " [3] ,Edge select bit 3" "3 setting,Any edge" bitfld.long 0x10 2. " [2] ,Edge select bit 2" "2 setting,Any edge" bitfld.long 0x10 1. " [1] ,Edge select bit 1" "1 setting,Any edge" bitfld.long 0x10 0. " [0] ,Edge select bit 0" "0 setting,Any edge" wgroup.long 0x84++0x0B line.long 0x00 "DR_SET,GPIO Data Register SET Register" bitfld.long 0x00 31. " DR_SET[31] ,Data bit 31 set" "Not set,Set" bitfld.long 0x00 30. " [30] ,Data bit 30 set" "Not set,Set" bitfld.long 0x00 29. " [29] ,Data bit 29 set" "Not set,Set" bitfld.long 0x00 28. " [28] ,Data bit 28 set" "Not set,Set" newline bitfld.long 0x00 27. " [27] ,Data bit 27 set" "Not set,Set" bitfld.long 0x00 26. " [26] ,Data bit 26 set" "Not set,Set" bitfld.long 0x00 25. " [25] ,Data bit 25 set" "Not set,Set" bitfld.long 0x00 24. " [24] ,Data bit 24 set" "Not set,Set" newline bitfld.long 0x00 23. " [23] ,Data bit 23 set" "Not set,Set" bitfld.long 0x00 22. " [22] ,Data bit 22 set" "Not set,Set" bitfld.long 0x00 21. " [21] ,Data bit 21 set" "Not set,Set" bitfld.long 0x00 20. " [20] ,Data bit 20 set" "Not set,Set" newline bitfld.long 0x00 19. " [19] ,Data bit 19 set" "Not set,Set" bitfld.long 0x00 18. " [18] ,Data bit 18 set" "Not set,Set" bitfld.long 0x00 17. " [17] ,Data bit 17 set" "Not set,Set" bitfld.long 0x00 16. " [16] ,Data bit 16 set" "Not set,Set" newline bitfld.long 0x00 15. " [15] ,Data bit 15 set" "Not set,Set" bitfld.long 0x00 14. " [14] ,Data bit 14 set" "Not set,Set" bitfld.long 0x00 13. " [13] ,Data bit 13 set" "Not set,Set" bitfld.long 0x00 12. " [12] ,Data bit 12 set" "Not set,Set" newline bitfld.long 0x00 11. " [11] ,Data bit 11 set" "Not set,Set" bitfld.long 0x00 10. " [10] ,Data bit 10 set" "Not set,Set" bitfld.long 0x00 9. " [9] ,Data bit 9 set" "Not set,Set" bitfld.long 0x00 8. " [8] ,Data bit 8 set" "Not set,Set" newline bitfld.long 0x00 7. " [7] ,Data bit 7 set" "Not set,Set" bitfld.long 0x00 6. " [6] ,Data bit 6 set" "Not set,Set" bitfld.long 0x00 5. " [5] ,Data bit 5 set" "Not set,Set" bitfld.long 0x00 4. " [4] ,Data bit 4 set" "Not set,Set" newline bitfld.long 0x00 3. " [3] ,Data bit 3 set" "Not set,Set" bitfld.long 0x00 2. " [2] ,Data bit 2 set" "Not set,Set" bitfld.long 0x00 1. " [1] ,Data bit 1 set" "Not set,Set" bitfld.long 0x00 0. " [0] ,Data bit 0 set" "Not set,Set" line.long 0x04 "DR_CLEAR,GPIO Data Register CLEAR Register" bitfld.long 0x04 31. " DR_CLEAR[31] ,Data bit 31 clear" "No effect,Clear" bitfld.long 0x04 30. " [30] ,Data bit 30 clear" "No effect,Clear" bitfld.long 0x04 29. " [29] ,Data bit 29 clear" "No effect,Clear" bitfld.long 0x04 28. " [28] ,Data bit 28 clear" "No effect,Clear" newline bitfld.long 0x04 27. " [27] ,Data bit 27 clear" "No effect,Clear" bitfld.long 0x04 26. " [26] ,Data bit 26 clear" "No effect,Clear" bitfld.long 0x04 25. " [25] ,Data bit 25 clear" "No effect,Clear" bitfld.long 0x04 24. " [24] ,Data bit 24 clear" "No effect,Clear" newline bitfld.long 0x04 23. " [23] ,Data bit 23 clear" "No effect,Clear" bitfld.long 0x04 22. " [22] ,Data bit 22 clear" "No effect,Clear" bitfld.long 0x04 21. " [21] ,Data bit 21 clear" "No effect,Clear" bitfld.long 0x04 20. " [20] ,Data bit 20 clear" "No effect,Clear" newline bitfld.long 0x04 19. " [19] ,Data bit 19 clear" "No effect,Clear" bitfld.long 0x04 18. " [18] ,Data bit 18 clear" "No effect,Clear" bitfld.long 0x04 17. " [17] ,Data bit 17 clear" "No effect,Clear" bitfld.long 0x04 16. " [16] ,Data bit 16 clear" "No effect,Clear" newline bitfld.long 0x04 15. " [15] ,Data bit 15 clear" "No effect,Clear" bitfld.long 0x04 14. " [14] ,Data bit 14 clear" "No effect,Clear" bitfld.long 0x04 13. " [13] ,Data bit 13 clear" "No effect,Clear" bitfld.long 0x04 12. " [12] ,Data bit 12 clear" "No effect,Clear" newline bitfld.long 0x04 11. " [11] ,Data bit 11 clear" "No effect,Clear" bitfld.long 0x04 10. " [10] ,Data bit 10 clear" "No effect,Clear" bitfld.long 0x04 9. " [9] ,Data bit 9 clear" "No effect,Clear" bitfld.long 0x04 8. " [8] ,Data bit 8 clear" "No effect,Clear" newline bitfld.long 0x04 7. " [7] ,Data bit 7 clear" "No effect,Clear" bitfld.long 0x04 6. " [6] ,Data bit 6 clear" "No effect,Clear" bitfld.long 0x04 5. " [5] ,Data bit 5 clear" "No effect,Clear" bitfld.long 0x04 4. " [4] ,Data bit 4 clear" "No effect,Clear" newline bitfld.long 0x04 3. " [3] ,Data bit 3 clear" "No effect,Clear" bitfld.long 0x04 2. " [2] ,Data bit 2 clear" "No effect,Clear" bitfld.long 0x04 1. " [1] ,Data bit 1 clear" "No effect,Clear" bitfld.long 0x04 0. " [0] ,Data bit 0 clear" "No effect,Clear" line.long 0x08 "DR_TOGGLE,GPIO Data Register TOGGLE Register" bitfld.long 0x08 31. " DR_TOGGLE[31] ,Data bit 31 toggle" "Not toggled,Toggled" bitfld.long 0x08 30. " [30] ,Data bit 30 toggle" "No effect,Clear" bitfld.long 0x08 29. " [29] ,Data bit 29 toggle" "Not toggled,Toggled" bitfld.long 0x08 28. " [28] ,Data bit 28 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 27. " [27] ,Data bit 27 toggle" "Not toggled,Toggled" bitfld.long 0x08 26. " [26] ,Data bit 26 toggle" "Not toggled,Toggled" bitfld.long 0x08 25. " [25] ,Data bit 25 toggle" "Not toggled,Toggled" bitfld.long 0x08 24. " [24] ,Data bit 24 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 23. " [23] ,Data bit 23 toggle" "Not toggled,Toggled" bitfld.long 0x08 22. " [22] ,Data bit 22 toggle" "Not toggled,Toggled" bitfld.long 0x08 21. " [21] ,Data bit 21 toggle" "Not toggled,Toggled" bitfld.long 0x08 20. " [20] ,Data bit 20 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 19. " [19] ,Data bit 19 toggle" "Not toggled,Toggled" bitfld.long 0x08 18. " [18] ,Data bit 18 toggle" "Not toggled,Toggled" bitfld.long 0x08 17. " [17] ,Data bit 17 toggle" "Not toggled,Toggled" bitfld.long 0x08 16. " [16] ,Data bit 16 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 15. " [15] ,Data bit 15 toggle" "Not toggled,Toggled" bitfld.long 0x08 14. " [14] ,Data bit 14 toggle" "Not toggled,Toggled" bitfld.long 0x08 13. " [13] ,Data bit 13 toggle" "Not toggled,Toggled" bitfld.long 0x08 12. " [12] ,Data bit 12 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 11. " [11] ,Data bit 11 toggle" "Not toggled,Toggled" bitfld.long 0x08 10. " [10] ,Data bit 10 toggle" "Not toggled,Toggled" bitfld.long 0x08 9. " [9] ,Data bit 9 toggle" "Not toggled,Toggled" bitfld.long 0x08 8. " [8] ,Data bit 8 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 7. " [7] ,Data bit 7 toggle" "Not toggled,Toggled" bitfld.long 0x08 6. " [6] ,Data bit 6 toggle" "Not toggled,Toggled" bitfld.long 0x08 5. " [5] ,Data bit 5 toggle" "Not toggled,Toggled" bitfld.long 0x08 4. " [4] ,Data bit 4 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 3. " [3] ,Data bit 3 toggle" "Not toggled,Toggled" bitfld.long 0x08 2. " [2] ,Data bit 2 toggle" "Not toggled,Toggled" bitfld.long 0x08 1. " [1] ,Data bit 1 toggle" "Not toggled,Toggled" bitfld.long 0x08 0. " [0] ,Data bit 0 toggle" "Not toggled,Toggled" width 0x0B tree.end tree "CSR (MIPI-DSI/LVDS Control and Status Registers)" base ad:0x56241000 width 15. group.long 0x00++0x03 line.long 0x00 "LVDS_PHY_CTRL,PHY In LVDS Mode Control Register" bitfld.long 0x00 5.--7. " CCM ,Common mode voltage" ",,,,Default,?..." bitfld.long 0x00 2.--4. " CA ,Driver output current" ",,,,Default,?..." bitfld.long 0x00 1. " RFB ,Rising / falling edge clock selection" "Falling,Rising" bitfld.long 0x00 0. " LVDS_EN ,LVDS TX enable" "Disabled,Enabled" group.long 0x20++0x03 line.long 0x00 "SS_CRTL,SS Control Register" bitfld.long 0x00 3. " CH1_VSYNC_POL ,Channel 1 VSYNC polarity control" "Low active,High active" bitfld.long 0x00 2. " CH1_HSYNC_POL ,channel 1 HSYNC polarity control" "Low active,High active" bitfld.long 0x00 1. " CH0_VSYNC_POL ,Channel 0 VSYNC polarity control" "Low active,High active" bitfld.long 0x00 0. " CH0_HSYNC_POL ,channel 0 HSYNC polarity control" "Low active,High active" group.long 0x30++0x03 line.long 0x00 "ULPS_CTRL,ULPS Control Register" bitfld.long 0x00 0.--4. " TX_ULPS ,Low power control of DSI lanes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x40++0x03 line.long 0x00 "PXL2DPI_CTRL,PXL2DPI Control Register" bitfld.long 0x00 0.--2. " PXL2DPI ,DPI color depth and configuration" "16-bit/Configuration 1,16-bit/Configuration 2,16-bit/Configuration 3,18-bit/Configuration 1,18-bit/Configuration 2,24-bit,?..." group.long 0xE0++0x03 line.long 0x00 "PM_CTRL,Pixel Mapper Control Register" bitfld.long 0x00 28. " CH_SEL ,Channel select" "Channel 0,Channel 1" bitfld.long 0x00 10. " DI1_VS_POLARITY ,Vsync polarity for DI1 interface" "Low active,High active" bitfld.long 0x00 9. " DI0_VS_POLARITY ,Vsync polarity for DI0 interface" "Low active,High active" bitfld.long 0x00 8. " CH1_BIT_MAPPING ,Data mapping to LVDS channel 1" "SPWG,JEIDA" newline bitfld.long 0x00 7. " CH1_DATA_WIDTH ,Data width for LVDS channel 1" "18-bit,24-bit" bitfld.long 0x00 6. " CH0_BIT_MAPPING ,Data mapping to LVDS channel 0" "SPWG,JEIDA" bitfld.long 0x00 5. " CH0_DATA_WIDTH ,Data width for LVDS channel 0" "18-bit,24-bit" bitfld.long 0x00 4. " SPLIT_MODE_EN ,Enable split mode" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " CH1_MODE ,LVDS Channel 1 operation mode" "Disabled,Enabled/DI0,Disabled,Enabled/DI1" bitfld.long 0x00 0.--1. " CH0_MODE ,LVDS Channel 0 operation mode" "Disabled,Enabled/DI0,Disabled,Enabled/DI1" width 0x0B tree.end tree.open "Local Interrupt Steer" tree "Channel 0" base ad:0x56240000 width 10. group.long 0x00++0x03 line.long 0x00 "CHAN0CTL,Channel 0 Control Register" bitfld.long 0x00 4. " CH4 ,Channel 4 control" "Disabled,Enabled" bitfld.long 0x00 3. " CH3 ,Channel 3 control" "Disabled,Enabled" bitfld.long 0x00 2. " CH2 ,Channel 2 control" "Disabled,Enabled" bitfld.long 0x00 1. " CH1 ,Channel 1 control" "Disabled,Enabled" newline bitfld.long 0x00 0. " CH0 ,Channel 0 control" "Disabled,Enabled" group.long 0x08++0x3B line.long 0x00 "MASK1,Interrupt Mask 1 Register" bitfld.long 0x00 22. " MASKFLD[22] ,Mask for VPU_INT_6" "Masked,Unmasked" bitfld.long 0x00 21. " [21] ,Mask for VPU_INT_5" "Masked,Unmasked" bitfld.long 0x00 20. " [20] ,Mask for VPU_INT_4" "Masked,Unmasked" bitfld.long 0x00 19. " [19] ,Mask for VPU_INT_3" "Masked,Unmasked" newline bitfld.long 0x00 18. " [18] ,Mask for VPU_INT_2" "Masked,Unmasked" bitfld.long 0x00 17. " [17] ,Mask for VPU_INT_1" "Masked,Unmasked" bitfld.long 0x00 16. " [16] ,Mask for VPU_INT_0" "Masked,Unmasked" bitfld.long 0x00 11. " [11] ,Mask for SPDIF0_TX_DMA_INT" "Masked,Unmasked" newline bitfld.long 0x00 10. " [10] ,Mask for SPDIF0_TX_MOD_INT" "Masked,Unmasked" bitfld.long 0x00 9. " [9] ,Mask for SPDIF0_RX_DMA_INT" "Masked,Unmasked" bitfld.long 0x00 8. " [8] ,Mask for SPDIF0_RX_MOD_INT" "Masked,Unmasked" bitfld.long 0x00 7. " [7] ,Mask for CAAM_RTIC_INT" "Masked,Unmasked" newline bitfld.long 0x00 6. " [6] ,Mask for CAAM_INT3" "Masked,Unmasked" bitfld.long 0x00 5. " [5] ,Mask for CAAM_INT2" "Masked,Unmasked" bitfld.long 0x00 4. " [4] ,Mask for CAAM_INT1" "Masked,Unmasked" bitfld.long 0x00 3. " [3] ,Mask for CAAM_INT0" "Masked,Unmasked" newline bitfld.long 0x00 2. " [2] ,Mask for SEC_MU3_A_INT" "Masked,Unmasked" bitfld.long 0x00 1. " [1] ,Mask for SEC_MU2_A_INT" "Masked,Unmasked" bitfld.long 0x00 0. " [0] ,Mask for SEC_MU1_A_INT" "Masked,Unmasked" line.long 0x04 "MASK2,Interrupt Mask 2 Register" bitfld.long 0x04 25. " MASKFLD[25] ,Mask for UART3_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 24. " [24] ,Mask for UART3_DMA_RX_INT" "Masked,Unmasked" bitfld.long 0x04 23. " [23] ,Mask for UART2_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 22. " [22] ,Mask for UART2_DMA_RX_INT" "Masked,Unmasked" newline bitfld.long 0x04 21. " [21] ,Mask for UART1_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 20. " [20] ,Mask for UART1_DMA_RX_INT" "Masked,Unmasked" bitfld.long 0x04 19. " [19] ,Mask for UART0_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 18. " [18] ,Mask for UART0_DMA_RX_INT" "Masked,Unmasked" newline bitfld.long 0x04 15. " [15] ,Mask for I2C3_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 14. " [14] ,Mask for I2C3_DMA_RX_INT" "Masked,Unmasked" bitfld.long 0x04 13. " [13] ,Mask for I2C2_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 12. " [12] ,Mask for I2C2_DMA_RX_INT" "Masked,Unmasked" newline bitfld.long 0x04 11. " [11] ,Mask for I2C1_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 10. " [10] ,Mask for I2C1_DMA_RX_INT" "Masked,Unmasked" bitfld.long 0x04 9. " [9] ,Mask for I2C0_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 8. " [8] ,Mask for I2C0_DMA_RX_INT" "Masked,Unmasked" newline bitfld.long 0x04 7. " [7] ,Mask for SPI3_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 6. " [6] ,Mask for SPI3_DMA_RX_INT" "Masked,Unmasked" bitfld.long 0x04 5. " [5] ,Mask for SPI2_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 4. " [4] ,Mask for SPI2_DMA_RX_INT" "Masked,Unmasked" newline bitfld.long 0x04 3. " [3] ,Mask for SPI1_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 2. " [2] ,Mask for SPI1_DMA_RX_INT" "Masked,Unmasked" bitfld.long 0x04 1. " [1] ,Mask for SPI0_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 0. " [0] ,Mask for SPI0_DMA_RX_INT" "Masked,Unmasked" line.long 0x08 "MASK3,Interrupt Mask 3 Register" bitfld.long 0x08 26. " MASKFLD[26] ,Mask for ESAI0_DMA_INT" "Masked,Unmasked" bitfld.long 0x08 25. " [25] ,Mask for ESAI0_MOD_INT" "Masked,Unmasked" bitfld.long 0x08 22. " [22] ,Mask for SPDIF0_TX_INT" "Masked,Unmasked" bitfld.long 0x08 21. " [21] ,Mask for SPDIF0_RX_INT" "Masked,Unmasked" newline bitfld.long 0x08 20. " [20] ,Mask for SAI5_INT" "Masked,Unmasked" bitfld.long 0x08 19. " [19] ,Mask for SAI4_INT" "Masked,Unmasked" bitfld.long 0x08 16. " [16] ,Mask for SAI3_INT" "Masked,Unmasked" bitfld.long 0x08 15. " [15] ,Mask for SAI2_INT" "Masked,Unmasked" newline bitfld.long 0x08 14. " [14] ,Mask for SAI1_INT" "Masked,Unmasked" bitfld.long 0x08 13. " [13] ,Mask for SAI0_INT" "Masked,Unmasked" bitfld.long 0x08 12. " [12] ,Mask for GPT5_INT" "Masked,Unmasked" bitfld.long 0x08 11. " [11] ,Mask for GPT4_INT" "Masked,Unmasked" newline bitfld.long 0x08 10. " [10] ,Mask for GPT3_INT" "Masked,Unmasked" bitfld.long 0x08 9. " [9] ,Mask for GPT2_INT" "Masked,Unmasked" bitfld.long 0x08 8. " [8] ,Mask for GPT1_INT" "Masked,Unmasked" bitfld.long 0x08 7. " [7] ,Mask for GPT0_INT" "Masked,Unmasked" newline bitfld.long 0x08 4. " [4] ,Mask for ESAI0_INT" "Masked,Unmasked" bitfld.long 0x08 3. " [3] ,Mask for DMA1_CH5_INT" "Masked,Unmasked" bitfld.long 0x08 2. " [2] ,Mask for DMA1_CH4_INT" "Masked,Unmasked" bitfld.long 0x08 1. " [1] ,Mask for DMA1_CH3_INT" "Masked,Unmasked" newline bitfld.long 0x08 0. " [0] ,Mask for DMA1_CH2_INT" "Masked,Unmasked" line.long 0x0C "MASK4,Interrupt Mask 4 Register" bitfld.long 0x0C 31. " MASKFLD[31] ,Mask for DMA1_CH1_INT" "Masked,Unmasked" bitfld.long 0x0C 30. " [30] ,Mask for DMA1_CH0_INT" "Masked,Unmasked" bitfld.long 0x0C 29. " [29] ,Mask for ASRC1_INT2" "Masked,Unmasked" bitfld.long 0x0C 28. " [28] ,Mask for ASRC1_INT1" "Masked,Unmasked" newline bitfld.long 0x0C 27. " [27] ,Mask for DMA0_CH5_INT" "Masked,Unmasked" bitfld.long 0x0C 26. " [26] ,Mask for DMA0_CH4_INT" "Masked,Unmasked" bitfld.long 0x0C 25. " [25] ,Mask for DMA0_CH3_INT" "Masked,Unmasked" bitfld.long 0x0C 24. " [24] ,Mask for DMA0_CH2_INT" "Masked,Unmasked" newline bitfld.long 0x0C 23. " [23] ,Mask for DMA0_CH1_INT" "Masked,Unmasked" bitfld.long 0x0C 22. " [22] ,Mask for DMA0_CH0_INT" "Masked,Unmasked" bitfld.long 0x0C 21. " [21] ,Mask for ASRC0_INT2" "Masked,Unmasked" bitfld.long 0x0C 20. " [20] ,Mask for ASRC0_INT1" "Masked,Unmasked" newline bitfld.long 0x0C 19. " [19] ,Mask for DMA1_ERR_INT" "Masked,Unmasked" bitfld.long 0x0C 18. " [18] ,Mask for DMA1_INT" "Masked,Unmasked" bitfld.long 0x0C 17. " [17] ,Mask for DMA0_ERR_INT" "Masked,Unmasked" bitfld.long 0x0C 16. " [16] ,Mask for DMA0_INT" "Masked,Unmasked" newline bitfld.long 0x0C 12. " [12] ,Mask for ADC_DMA_INT" "Masked,Unmasked" bitfld.long 0x0C 11. " [11] ,Mask for FTM1_DMA_INT" "Masked,Unmasked" bitfld.long 0x0C 10. " [10] ,Mask for FTM_DMA_INT" "Masked,Unmasked" bitfld.long 0x0C 9. " [9] ,Mask for FLEXCAN2_DMA_INT" "Masked,Unmasked" newline bitfld.long 0x0C 8. " [8] ,Mask for FLEXCAN1_DMA_INT" "Masked,Unmasked" bitfld.long 0x0C 7. " [7] ,Mask for FLEXCAN0_DMA_INT" "Masked,Unmasked" bitfld.long 0x0C 5. " [5] ,Mask for ADC_MOD_INT" "Masked,Unmasked" bitfld.long 0x0C 4. " [4] ,Mask for FTM1_MOD_INT" "Masked,Unmasked" newline bitfld.long 0x0C 3. " [3] ,Mask for FTM_MOD_INT" "Masked,Unmasked" bitfld.long 0x0C 2. " [2] ,Mask for FLEXCAN2_MOD_INT" "Masked,Unmasked" bitfld.long 0x0C 1. " [1] ,Mask for FLEXCAN1_MOD_INT" "Masked,Unmasked" bitfld.long 0x0C 0. " [0] ,Mask for FLEXCAN0_MOD_INT" "Masked,Unmasked" line.long 0x10 "MASK5,Interrupt Mask 5 Register" bitfld.long 0x10 28. " MASKFLD[28] ,Mask for UART3_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 27. " [27] ,Mask for UART2_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 26. " [26] ,Mask for UART1_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 25. " [25] ,Mask for UART0_MOD_INT" "Masked,Unmasked" newline bitfld.long 0x10 23. " [23] ,Mask for I2C3_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 22. " [22] ,Mask for I2C2_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 21. " [21] ,Mask for I2C1_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 20. " [20] ,Mask for I2C0_MOD_INT" "Masked,Unmasked" newline bitfld.long 0x10 19. " [19] ,Mask for SPI3_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 18. " [18] ,Mask for SPI2_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 17. " [17] ,Mask for SPI1_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 16. " [16] ,Mask for SPI0_MOD_INT" "Masked,Unmasked" newline bitfld.long 0x10 12. " [12] ,Mask for SAI5_DMA_INT" "Masked,Unmasked" bitfld.long 0x10 11. " [11] ,Mask for SAI5_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 10. " [10] ,Mask for SAI4_DMA_INT" "Masked,Unmasked" bitfld.long 0x10 9. " [9] ,Mask for SAI4_MOD_INT" "Masked,Unmasked" newline bitfld.long 0x10 4. " [4] ,Mask for SAI3_DMA_INT" "Masked,Unmasked" bitfld.long 0x10 3. " [3] ,Mask for SAI3_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 0. " [0] ,Mask for INT_OUT" "Masked,Unmasked" line.long 0x14 "MASK6,Interrupt Mask 6 Register" bitfld.long 0x14 31. " MASKFLD[31] ,Mask for SAI2_DMA_INT" "Masked,Unmasked" bitfld.long 0x14 30. " [30] ,Mask for SAI2_MOD_INT" "Masked,Unmasked" bitfld.long 0x14 29. " [29] ,Mask for SAI1_DMA_INT" "Masked,Unmasked" bitfld.long 0x14 28. " [28] ,Mask for SAI1_MOD_INT" "Masked,Unmasked" newline bitfld.long 0x14 27. " [27] ,Mask for SAI0_DMA_INT" "Masked,Unmasked" bitfld.long 0x14 26. " [26] ,Mask for SAI0_MOD_INT" "Masked,Unmasked" bitfld.long 0x14 24. " [24] ,Mask for MJPEG_DEC3_INT" "Masked,Unmasked" bitfld.long 0x14 23. " [23] ,Mask for MJPEG_DEC2_INT" "Masked,Unmasked" newline bitfld.long 0x14 22. " [22] ,Mask for MJPEG_DEC1_INT" "Masked,Unmasked" bitfld.long 0x14 21. " [21] ,Mask for MJPEG_DEC0_INT" "Masked,Unmasked" bitfld.long 0x14 20. " [20] ,Mask for MJPEG_ENC3_INT" "Masked,Unmasked" bitfld.long 0x14 19. " [19] ,Mask for MJPEG_ENC2_INT" "Masked,Unmasked" newline bitfld.long 0x14 18. " [18] ,Mask for MJPEG_ENC1_INT" "Masked,Unmasked" bitfld.long 0x14 17. " [17] ,Mask for MJPEG_ENC0_INT" "Masked,Unmasked" bitfld.long 0x14 16. " [16] ,Mask for PDMA_STREAM7_INT" "Masked,Unmasked" bitfld.long 0x14 15. " [15] ,Mask for PDMA_STREAM6_INT" "Masked,Unmasked" newline bitfld.long 0x14 14. " [14] ,Mask for PDMA_STREAM5_INT" "Masked,Unmasked" bitfld.long 0x14 13. " [13] ,Mask for PDMA_STREAM4_INT" "Masked,Unmasked" bitfld.long 0x14 12. " [12] ,Mask for PDMA_STREAM3_INT" "Masked,Unmasked" bitfld.long 0x14 11. " [11] ,Mask for PDMA_STREAM2_INT" "Masked,Unmasked" newline bitfld.long 0x14 10. " [10] ,Mask for PDMA_STREAM1_INT" "Masked,Unmasked" bitfld.long 0x14 9. " [9] ,Mask for PDMA_STREAM0_INT" "Masked,Unmasked" bitfld.long 0x14 0. " [0] ,Mask for MSI_INT" "Masked,Unmasked" line.long 0x18 "MASK7,Interrupt Mask 7 Register" bitfld.long 0x18 20. " MASKFLD[20] ,Mask for DMA_ERR_INT" "Masked,Unmasked" bitfld.long 0x18 19. " [19] ,Mask for DMA_INT" "Masked,Unmasked" bitfld.long 0x18 18. " [18] ,Mask for APBHDMA" "Masked,Unmasked" bitfld.long 0x18 17. " [17] ,Mask for NAND_GPMI_INT" "Masked,Unmasked" newline bitfld.long 0x18 16. " [16] ,Mask for NAND_BCH_INT" "Masked,Unmasked" bitfld.long 0x18 15. " [15] ,Mask for USB3_INT" "Masked,Unmasked" bitfld.long 0x18 14. " [14] ,Mask for WAKEUP_INT" "Masked,Unmasked" bitfld.long 0x18 13. " [13] ,Mask for UTMI_INT" "Masked,Unmasked" newline bitfld.long 0x18 12. " [12] ,Mask for USB_HOST_INT" "Masked,Unmasked" bitfld.long 0x18 11. " [11] ,Mask for USB_OTG_INT" "Masked,Unmasked" bitfld.long 0x18 10. " [10] ,Mask for MLB_AHB_INT" "Masked,Unmasked" bitfld.long 0x18 9. " [9] ,Mask for MLB_INT" "Masked,Unmasked" newline bitfld.long 0x18 7. " [7] ,Mask for ENET1_TIMER_INT" "Masked,Unmasked" bitfld.long 0x18 6. " [6] ,Mask for ENET1_FRAME0_EVENT_INT" "Masked,Unmasked" bitfld.long 0x18 5. " [5] ,Mask for ENET1_FRAME2_INT" "Masked,Unmasked" bitfld.long 0x18 4. " [4] ,Mask for ENET1_FRAME1_INT" "Masked,Unmasked" newline bitfld.long 0x18 3. " [3] ,Mask for ENET0_TIMER_INT" "Masked,Unmasked" bitfld.long 0x18 2. " [2] ,Mask for ENET0_FRAME0_EVENT_INT" "Masked,Unmasked" bitfld.long 0x18 1. " [1] ,Mask for ENET0_FRAME2_INT" "Masked,Unmasked" bitfld.long 0x18 0. " [0] ,Mask for ENET0_FRAME1_INT" "Masked,Unmasked" line.long 0x1C "MASK8,Interrupt Mask 8 Register" bitfld.long 0x1C 23. " MASKFLD[23] ,Mask for EXTERNAL_DMA_INT_5" "Masked,Unmasked" bitfld.long 0x1C 22. " [22] ,Mask for EXTERNAL_DMA_INT_4" "Masked,Unmasked" bitfld.long 0x1C 21. " [21] ,Mask for EXTERNAL_DMA_INT_3" "Masked,Unmasked" bitfld.long 0x1C 20. " [20] ,Mask for EXTERNAL_DMA_INT_2" "Masked,Unmasked" newline bitfld.long 0x1C 19. " [19] ,Mask for EXTERNAL_DMA_INT_1" "Masked,Unmasked" bitfld.long 0x1C 18. " [18] ,Mask for EXTERNAL_DMA_INT_0" "Masked,Unmasked" bitfld.long 0x1C 16. " [16] ,Mask for ADC_INT" "Masked,Unmasked" bitfld.long 0x1C 15. " [15] ,Mask for FTM1_INT" "Masked,Unmasked" newline bitfld.long 0x1C 14. " [14] ,Mask for FTM_INT" "Masked,Unmasked" bitfld.long 0x1C 13. " [13] ,Mask for FLEXCAN2_INT" "Masked,Unmasked" bitfld.long 0x1C 12. " [12] ,Mask for FLEXCAN1_INT" "Masked,Unmasked" bitfld.long 0x1C 11. " [11] ,Mask for FLEXCAN0_INT" "Masked,Unmasked" newline bitfld.long 0x1C 10. " [10] ,Mask for USDHC2_INT" "Masked,Unmasked" bitfld.long 0x1C 9. " [9] ,Mask for USDHC1_INT" "Masked,Unmasked" bitfld.long 0x1C 8. " [8] ,Mask for EMMC0_INT/USDHC0_INT" "Masked,Unmasked" bitfld.long 0x1C 4. " [4] ,Mask for UART3_INT" "Masked,Unmasked" newline bitfld.long 0x1C 3. " [3] ,Mask for UART2_INT" "Masked,Unmasked" bitfld.long 0x1C 2. " [2] ,Mask for UART1_INT" "Masked,Unmasked" bitfld.long 0x1C 1. " [1] ,Mask for UART0_INT" "Masked,Unmasked" line.long 0x20 "MASK9,Interrupt Mask 9 Register" bitfld.long 0x20 31. " MASKFLD[31] ,Mask for I2C3_INT" "Masked,Unmasked" bitfld.long 0x20 30. " [30] ,Mask for I2C2_INT" "Masked,Unmasked" bitfld.long 0x20 29. " [29] ,Mask for I2C1_INT" "Masked,Unmasked" bitfld.long 0x20 28. " [28] ,Mask for I2C0_INT" "Masked,Unmasked" newline bitfld.long 0x20 27. " [27] ,Mask for SPI3_INT" "Masked,Unmasked" bitfld.long 0x20 26. " [26] ,Mask for SPI2_INT" "Masked,Unmasked" bitfld.long 0x20 25. " [25] ,Mask for SPI1_INT" "Masked,Unmasked" bitfld.long 0x20 24. " [24] ,Mask for SPI0_INT" "Masked,Unmasked" newline bitfld.long 0x20 16. " [16] ,Mask for MU13_INT_B" "Masked,Unmasked" bitfld.long 0x20 15. " [15] ,Mask for MU12_INT_B" "Masked,Unmasked" bitfld.long 0x20 14. " [14] ,Mask for MU11_INT_B" "Masked,Unmasked" bitfld.long 0x20 13. " [13] ,Mask for MU10_INT_B" "Masked,Unmasked" newline bitfld.long 0x20 12. " [12] ,Mask for MU9_INT_B" "Masked,Unmasked" bitfld.long 0x20 11. " [11] ,Mask for MU8_INT_B" "Masked,Unmasked" bitfld.long 0x20 10. " [10] ,Mask for MU7_INT_B" "Masked,Unmasked" bitfld.long 0x20 9. " [9] ,Mask for MU6_INT_B" "Masked,Unmasked" newline bitfld.long 0x20 8. " [8] ,Mask for MU5_INT_B" "Masked,Unmasked" bitfld.long 0x20 0. " [0] ,Mask for MU13_INT_A" "Masked,Unmasked" line.long 0x24 "MASK10,Interrupt Mask 10 Register" bitfld.long 0x24 31. " MASKFLD[31] ,Mask for MU12_INT_A" "Masked,Unmasked" bitfld.long 0x24 30. " [30] ,Mask for MU11_INT_A" "Masked,Unmasked" bitfld.long 0x24 29. " [29] ,Mask for MU10_INT_A" "Masked,Unmasked" bitfld.long 0x24 28. " [28] ,Mask for MU9_INT_A" "Masked,Unmasked" newline bitfld.long 0x24 27. " [27] ,Mask for MU8_INT_A" "Masked,Unmasked" bitfld.long 0x24 26. " [26] ,Mask for MU7_INT_A" "Masked,Unmasked" bitfld.long 0x24 25. " [25] ,Mask for MU6_INT_A" "Masked,Unmasked" bitfld.long 0x24 24. " [24] ,Mask for MU5_INT_A" "Masked,Unmasked" newline bitfld.long 0x24 20. " [20] ,Mask for MU4_INT" "Masked,Unmasked" bitfld.long 0x24 19. " [19] ,Mask for MU3_INT" "Masked,Unmasked" bitfld.long 0x24 18. " [18] ,Mask for MU2_INT" "Masked,Unmasked" bitfld.long 0x24 17. " [17] ,Mask for MU1_INT" "Masked,Unmasked" newline bitfld.long 0x24 16. " [16] ,Mask for MU0_INT" "Masked,Unmasked" line.long 0x28 "MASK11,Interrupt Mask 11 Register" bitfld.long 0x28 15. " MASKFLD[15] ,Mask for GPIO_INT[7]" "Masked,Unmasked" bitfld.long 0x28 14. " [14] ,Mask for GPIO_INT[6]" "Masked,Unmasked" bitfld.long 0x28 13. " [13] ,Mask for GPIO_INT[5]" "Masked,Unmasked" bitfld.long 0x28 12. " [12] ,Mask for GPIO_INT[4]" "Masked,Unmasked" newline bitfld.long 0x28 11. " [11] ,Mask for GPIO_INT[3]" "Masked,Unmasked" bitfld.long 0x28 10. " [10] ,Mask for GPIO_INT[2]" "Masked,Unmasked" bitfld.long 0x28 9. " [9] ,Mask for GPIO_INT[1]" "Masked,Unmasked" bitfld.long 0x28 8. " [8] ,Mask for GPIO_INT[0]" "Masked,Unmasked" newline bitfld.long 0x28 3. " [3] ,Mask for PERF_CNT_INT" "Masked,Unmasked" bitfld.long 0x28 2. " [2] ,Mask for SBR_DONE_INT" "Masked,Unmasked" bitfld.long 0x28 1. " [1] ,Mask for ECC_NCORRECT_INT" "Masked,Unmasked" bitfld.long 0x28 0. " [0] ,Mask for ECC_CORRECT_INT" "Masked,Unmasked" line.long 0x2C "MASK12,Interrupt Mask 12 Register" bitfld.long 0x2C 27. " MASKFLD[27] ,Mask for SYS_COUNT_INT[3]" "Masked,Unmasked" bitfld.long 0x2C 26. " [26] ,Mask for SYS_COUNT_INT[2]" "Masked,Unmasked" bitfld.long 0x2C 25. " [25] ,Mask for SYS_COUNT_INT[1]" "Masked,Unmasked" bitfld.long 0x2C 24. " [24] ,Mask for SYS_COUNT_INT[0]" "Masked,Unmasked" newline bitfld.long 0x2C 23. " [23] ,Mask for INT_OUT[7]" "Masked,Unmasked" bitfld.long 0x2C 22. " [22] ,Mask for INT_OUT[6]" "Masked,Unmasked" bitfld.long 0x2C 21. " [21] ,Mask for INT_OUT[5]" "Masked,Unmasked" bitfld.long 0x2C 20. " [20] ,Mask for INT_OUT[4]" "Masked,Unmasked" newline bitfld.long 0x2C 19. " [19] ,Mask for INT_OUT[3]" "Masked,Unmasked" bitfld.long 0x2C 18. " [18] ,Mask for INT_OUT[2]" "Masked,Unmasked" bitfld.long 0x2C 17. " [17] ,Mask for INT_OUT[1]" "Masked,Unmasked" bitfld.long 0x2C 16. " [16] ,Mask for INT_OUT[0]" "Masked,Unmasked" newline bitfld.long 0x2C 15. " [15] ,Mask for PCIE9_GPIO_WAKEUP[1]" "Masked,Unmasked" bitfld.long 0x2C 14. " [14] ,Mask for PCIE9_GPIO_WAKEUP[0]" "Masked,Unmasked" bitfld.long 0x2C 13. " [13] ,Mask for PCIE0_SMLH_REQ_RST" "Masked,Unmasked" bitfld.long 0x2C 12. " [12] ,Mask for PCIE0_INT_A" "Masked,Unmasked" newline bitfld.long 0x2C 11. " [11] ,Mask for PCIE0_INT_B" "Masked,Unmasked" bitfld.long 0x2C 10. " [10] ,Mask for PCIE0_INT_C" "Masked,Unmasked" bitfld.long 0x2C 9. " [9] ,Mask for PCIE0_INT_D" "Masked,Unmasked" bitfld.long 0x2C 8. " [8] ,Mask for PCIE0_DMA_INT" "Masked,Unmasked" newline bitfld.long 0x2C 7. " [7] ,Mask for PCIE0_CLK_REQ_INT" "Masked,Unmasked" bitfld.long 0x2C 6. " [6] ,Mask for PCIE0_MSI_CTRL_INT" "Masked,Unmasked" bitfld.long 0x2C 5. " [5] ,Mask for PWM7_INT" "Masked,Unmasked" bitfld.long 0x2C 4. " [4] ,Mask for PWM6_INT" "Masked,Unmasked" newline bitfld.long 0x2C 3. " [3] ,Mask for PWM5_INT" "Masked,Unmasked" bitfld.long 0x2C 2. " [2] ,Mask for PWM4_INT" "Masked,Unmasked" bitfld.long 0x2C 1. " [1] ,Mask for PWM3_INT" "Masked,Unmasked" bitfld.long 0x2C 0. " [0] ,Mask for PWM2_INT" "Masked,Unmasked" line.long 0x30 "MASK13,Interrupt Mask 13 Register" bitfld.long 0x30 31. " MASKFLD[31] ,Mask for PWM1_INT" "Masked,Unmasked" bitfld.long 0x30 30. " [30] ,Mask for PWM0_INT" "Masked,Unmasked" bitfld.long 0x30 29. " [29] ,Mask for FLEXSPI1_INT" "Masked,Unmasked" bitfld.long 0x30 28. " [28] ,Mask for FLEXSPI0_INT" "Masked,Unmasked" newline bitfld.long 0x30 21. " [21] ,Mask for KPP0_INT" "Masked,Unmasked" bitfld.long 0x30 20. " [20] ,Mask for GPT4_INT" "Masked,Unmasked" bitfld.long 0x30 19. " [19] ,Mask for GPT3_INT" "Masked,Unmasked" bitfld.long 0x30 18. " [18] ,Mask for GPT2_INT" "Masked,Unmasked" newline bitfld.long 0x30 17. " [17] ,Mask for GPT1_INT" "Masked,Unmasked" bitfld.long 0x30 16. " [16] ,Mask for GPT0_INT" "Masked,Unmasked" bitfld.long 0x30 5. " [5] ,Mask for DMA3_ERR_INT" "Masked,Unmasked" bitfld.long 0x30 4. " [4] ,Mask for DMA3_INT" "Masked,Unmasked" newline bitfld.long 0x30 3. " [3] ,Mask for DMA2_ERR_INT" "Masked,Unmasked" bitfld.long 0x30 2. " [2] ,Mask for DMA2_INT" "Masked,Unmasked" bitfld.long 0x30 0. " [0] ,Mask for XAQ2_INTR" "Masked,Unmasked" line.long 0x34 "MASK14,Interrupt Mask 14 Register" bitfld.long 0x34 31. " MASKFLD[31] ,Mask for LCD_PWM_INT" "Masked,Unmasked" bitfld.long 0x34 30. " [30] ,Mask for LCD_MOD_INT" "Masked,Unmasked" bitfld.long 0x34 28. " [28] ,Mask for INT_OUT" "Masked,Unmasked" bitfld.long 0x34 27. " [27] ,Mask for INT_OUT" "Masked,Unmasked" newline bitfld.long 0x34 20. " [20] ,Mask for INT_OUT[12]" "Masked,Unmasked" bitfld.long 0x34 19. " [19] ,Mask for INT_OUT[11]" "Masked,Unmasked" bitfld.long 0x34 18. " [18] ,Mask for INT_OUT[10]" "Masked,Unmasked" bitfld.long 0x34 17. " [17] ,Mask for INT_OUT[9]" "Masked,Unmasked" newline bitfld.long 0x34 15. " [15] ,Mask for INT_OUT[7]" "Masked,Unmasked" bitfld.long 0x34 14. " [14] ,Mask for INT_OUT[6]" "Masked,Unmasked" bitfld.long 0x34 13. " [13] ,Mask for INT_OUT[5]" "Masked,Unmasked" bitfld.long 0x34 12. " [12] ,Mask for INT_OUT[4]" "Masked,Unmasked" newline bitfld.long 0x34 11. " [11] ,Mask for INT_OUT[3]" "Masked,Unmasked" bitfld.long 0x34 10. " [10] ,Mask for INT_OUT[2]" "Masked,Unmasked" bitfld.long 0x34 9. " [9] ,Mask for INT_OUT[1]" "Masked,Unmasked" bitfld.long 0x34 8. " [8] ,Mask for INT_OUT[0]" "Masked,Unmasked" line.long 0x38 "MASK15,Interrupt Mask 15 Register" bitfld.long 0x38 23. " MASKFLD[23] ,Mask for INT_OUT[7]" "Masked,Unmasked" bitfld.long 0x38 22. " [22] ,Mask for INT_OUT[6]" "Masked,Unmasked" bitfld.long 0x38 21. " [21] ,Mask for INT_OUT[5]" "Masked,Unmasked" bitfld.long 0x38 20. " [20] ,Mask for INT_OUT[4]" "Masked,Unmasked" newline bitfld.long 0x38 19. " [19] ,Mask for INT_OUT[3]" "Masked,Unmasked" bitfld.long 0x38 18. " [18] ,Mask for INT_OUT[2]" "Masked,Unmasked" bitfld.long 0x38 17. " [17] ,Mask for INT_OUT[1]" "Masked,Unmasked" bitfld.long 0x38 16. " [16] ,Mask for INT_OUT[0]" "Masked,Unmasked" newline bitfld.long 0x38 1. " [1] ,Mask for nEXTERRIRQ" "Masked,Unmasked" bitfld.long 0x38 0. " [0] ,Mask for nINTERRIRQ" "Masked,Unmasked" group.long 0x48++0x3B line.long 0x00 "SET1,Interrupt Set 1 Register" bitfld.long 0x00 22. " FORCEFLD[22] ,Force VPU_INT_6" "Normal,Forced" bitfld.long 0x00 21. " [21] ,Force VPU_INT_5" "Normal,Forced" bitfld.long 0x00 20. " [20] ,Force VPU_INT_4" "Normal,Forced" bitfld.long 0x00 19. " [19] ,Force VPU_INT_3" "Normal,Forced" newline bitfld.long 0x00 18. " [18] ,Force VPU_INT_2" "Normal,Forced" bitfld.long 0x00 17. " [17] ,Force VPU_INT_1" "Normal,Forced" bitfld.long 0x00 16. " [16] ,Force VPU_INT_0" "Normal,Forced" bitfld.long 0x00 11. " [11] ,Force SPDIF0_TX_DMA_INT" "Normal,Forced" newline bitfld.long 0x00 10. " [10] ,Force SPDIF0_TX_MOD_INT" "Normal,Forced" bitfld.long 0x00 9. " [9] ,Force SPDIF0_RX_DMA_INT" "Normal,Forced" bitfld.long 0x00 8. " [8] ,Force SPDIF0_RX_MOD_INT" "Normal,Forced" bitfld.long 0x00 7. " [7] ,Force CAAM_RTIC_INT" "Normal,Forced" newline bitfld.long 0x00 6. " [6] ,Force CAAM_INT3" "Normal,Forced" bitfld.long 0x00 5. " [5] ,Force CAAM_INT2" "Normal,Forced" bitfld.long 0x00 4. " [4] ,Force CAAM_INT1" "Normal,Forced" bitfld.long 0x00 3. " [3] ,Force CAAM_INT0" "Normal,Forced" newline bitfld.long 0x00 2. " [2] ,Force SEC_MU3_A_INT" "Normal,Forced" bitfld.long 0x00 1. " [1] ,Force SEC_MU2_A_INT" "Normal,Forced" bitfld.long 0x00 0. " [0] ,Force SEC_MU1_A_INT" "Normal,Forced" line.long 0x04 "SET2,Interrupt Set 2 Register" bitfld.long 0x04 25. " FORCEFLD[25] ,Force UART3_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 24. " [24] ,Force UART3_DMA_RX_INT" "Normal,Forced" bitfld.long 0x04 23. " [23] ,Force UART2_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 22. " [22] ,Force UART2_DMA_RX_INT" "Normal,Forced" newline bitfld.long 0x04 21. " [21] ,Force UART1_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 20. " [20] ,Force UART1_DMA_RX_INT" "Normal,Forced" bitfld.long 0x04 19. " [19] ,Force UART0_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 18. " [18] ,Force UART0_DMA_RX_INT" "Normal,Forced" newline bitfld.long 0x04 15. " [15] ,Force I2C3_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 14. " [14] ,Force I2C3_DMA_RX_INT" "Normal,Forced" bitfld.long 0x04 13. " [13] ,Force I2C2_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 12. " [12] ,Force I2C2_DMA_RX_INT" "Normal,Forced" newline bitfld.long 0x04 11. " [11] ,Force I2C1_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 10. " [10] ,Force I2C1_DMA_RX_INT" "Normal,Forced" bitfld.long 0x04 9. " [9] ,Force I2C0_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 8. " [8] ,Force I2C0_DMA_RX_INT" "Normal,Forced" newline bitfld.long 0x04 7. " [7] ,Force SPI3_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 6. " [6] ,Force SPI3_DMA_RX_INT" "Normal,Forced" bitfld.long 0x04 5. " [5] ,Force SPI2_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 4. " [4] ,Force SPI2_DMA_RX_INT" "Normal,Forced" newline bitfld.long 0x04 3. " [3] ,Force SPI1_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 2. " [2] ,Force SPI1_DMA_RX_INT" "Normal,Forced" bitfld.long 0x04 1. " [1] ,Force SPI0_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 0. " [0] ,Force SPI0_DMA_RX_INT" "Normal,Forced" line.long 0x08 "SET3,Interrupt Set 3 Register" bitfld.long 0x08 26. " FORCEFLD[26] ,Force ESAI0_DMA_INT" "Normal,Forced" bitfld.long 0x08 25. " [25] ,Force ESAI0_MOD_INT" "Normal,Forced" bitfld.long 0x08 22. " [22] ,Force SPDIF0_TX_INT" "Normal,Forced" bitfld.long 0x08 21. " [21] ,Force SPDIF0_RX_INT" "Normal,Forced" newline bitfld.long 0x08 20. " [20] ,Force SAI5_INT" "Normal,Forced" bitfld.long 0x08 19. " [19] ,Force SAI4_INT" "Normal,Forced" bitfld.long 0x08 16. " [16] ,Force SAI3_INT" "Normal,Forced" bitfld.long 0x08 15. " [15] ,Force SAI2_INT" "Normal,Forced" newline bitfld.long 0x08 14. " [14] ,Force SAI1_INT" "Normal,Forced" bitfld.long 0x08 13. " [13] ,Force SAI0_INT" "Normal,Forced" bitfld.long 0x08 12. " [12] ,Force GPT5_INT" "Normal,Forced" bitfld.long 0x08 11. " [11] ,Force GPT4_INT" "Normal,Forced" newline bitfld.long 0x08 10. " [10] ,Force GPT3_INT" "Normal,Forced" bitfld.long 0x08 9. " [9] ,Force GPT2_INT" "Normal,Forced" bitfld.long 0x08 8. " [8] ,Force GPT1_INT" "Normal,Forced" bitfld.long 0x08 7. " [7] ,Force GPT0_INT" "Normal,Forced" newline bitfld.long 0x08 4. " [4] ,Force ESAI0_INT" "Normal,Forced" bitfld.long 0x08 3. " [3] ,Force DMA1_CH5_INT" "Normal,Forced" bitfld.long 0x08 2. " [2] ,Force DMA1_CH4_INT" "Normal,Forced" bitfld.long 0x08 1. " [1] ,Force DMA1_CH3_INT" "Normal,Forced" newline bitfld.long 0x08 0. " [0] ,Force DMA1_CH2_INT" "Normal,Forced" line.long 0x0C "SET4,Interrupt Set 4 Register" bitfld.long 0x0C 31. " FORCEFLD[31] ,Force DMA1_CH1_INT" "Normal,Forced" bitfld.long 0x0C 30. " [30] ,Force DMA1_CH0_INT" "Normal,Forced" bitfld.long 0x0C 29. " [29] ,Force ASRC1_INT2" "Normal,Forced" bitfld.long 0x0C 28. " [28] ,Force ASRC1_INT1" "Normal,Forced" newline bitfld.long 0x0C 27. " [27] ,Force DMA0_CH5_INT" "Normal,Forced" bitfld.long 0x0C 26. " [26] ,Force DMA0_CH4_INT" "Normal,Forced" bitfld.long 0x0C 25. " [25] ,Force DMA0_CH3_INT" "Normal,Forced" bitfld.long 0x0C 24. " [24] ,Force DMA0_CH2_INT" "Normal,Forced" newline bitfld.long 0x0C 23. " [23] ,Force DMA0_CH1_INT" "Normal,Forced" bitfld.long 0x0C 22. " [22] ,Force DMA0_CH0_INT" "Normal,Forced" bitfld.long 0x0C 21. " [21] ,Force ASRC0_INT2" "Normal,Forced" bitfld.long 0x0C 20. " [20] ,Force ASRC0_INT1" "Normal,Forced" newline bitfld.long 0x0C 19. " [19] ,Force DMA1_ERR_INT" "Normal,Forced" bitfld.long 0x0C 18. " [18] ,Force DMA1_INT" "Normal,Forced" bitfld.long 0x0C 17. " [17] ,Force DMA0_ERR_INT" "Normal,Forced" bitfld.long 0x0C 16. " [16] ,Force DMA0_INT" "Normal,Forced" newline bitfld.long 0x0C 12. " [12] ,Force ADC_DMA_INT" "Normal,Forced" bitfld.long 0x0C 11. " [11] ,Force FTM1_DMA_INT" "Normal,Forced" bitfld.long 0x0C 10. " [10] ,Force FTM_DMA_INT" "Normal,Forced" bitfld.long 0x0C 9. " [9] ,Force FLEXCAN2_DMA_INT" "Normal,Forced" newline bitfld.long 0x0C 8. " [8] ,Force FLEXCAN1_DMA_INT" "Normal,Forced" bitfld.long 0x0C 7. " [7] ,Force FLEXCAN0_DMA_INT" "Normal,Forced" bitfld.long 0x0C 5. " [5] ,Force ADC_MOD_INT" "Normal,Forced" bitfld.long 0x0C 4. " [4] ,Force FTM1_MOD_INT" "Normal,Forced" newline bitfld.long 0x0C 3. " [3] ,Force FTM_MOD_INT" "Normal,Forced" bitfld.long 0x0C 2. " [2] ,Force FLEXCAN2_MOD_INT" "Normal,Forced" bitfld.long 0x0C 1. " [1] ,Force FLEXCAN1_MOD_INT" "Normal,Forced" bitfld.long 0x0C 0. " [0] ,Force FLEXCAN0_MOD_INT" "Normal,Forced" line.long 0x10 "SET5,Interrupt Set 5 Register" bitfld.long 0x10 28. " FORCEFLD[28] ,Force UART3_MOD_INT" "Normal,Forced" bitfld.long 0x10 27. " [27] ,Force UART2_MOD_INT" "Normal,Forced" bitfld.long 0x10 26. " [26] ,Force UART1_MOD_INT" "Normal,Forced" bitfld.long 0x10 25. " [25] ,Force UART0_MOD_INT" "Normal,Forced" newline bitfld.long 0x10 23. " [23] ,Force I2C3_MOD_INT" "Normal,Forced" bitfld.long 0x10 22. " [22] ,Force I2C2_MOD_INT" "Normal,Forced" bitfld.long 0x10 21. " [21] ,Force I2C1_MOD_INT" "Normal,Forced" bitfld.long 0x10 20. " [20] ,Force I2C0_MOD_INT" "Normal,Forced" newline bitfld.long 0x10 19. " [19] ,Force SPI3_MOD_INT" "Normal,Forced" bitfld.long 0x10 18. " [18] ,Force SPI2_MOD_INT" "Normal,Forced" bitfld.long 0x10 17. " [17] ,Force SPI1_MOD_INT" "Normal,Forced" bitfld.long 0x10 16. " [16] ,Force SPI0_MOD_INT" "Normal,Forced" newline bitfld.long 0x10 12. " [12] ,Force SAI5_DMA_INT" "Normal,Forced" bitfld.long 0x10 11. " [11] ,Force SAI5_MOD_INT" "Normal,Forced" bitfld.long 0x10 10. " [10] ,Force SAI4_DMA_INT" "Normal,Forced" bitfld.long 0x10 9. " [9] ,Force SAI4_MOD_INT" "Normal,Forced" newline bitfld.long 0x10 4. " [4] ,Force SAI3_DMA_INT" "Normal,Forced" bitfld.long 0x10 3. " [3] ,Force SAI3_MOD_INT" "Normal,Forced" bitfld.long 0x10 0. " [0] ,Force INT_OUT" "Normal,Forced" line.long 0x14 "SET6,Interrupt Set 6 Register" bitfld.long 0x14 31. " FORCEFLD[31] ,Force SAI2_DMA_INT" "Normal,Forced" bitfld.long 0x14 30. " [30] ,Force SAI2_MOD_INT" "Normal,Forced" bitfld.long 0x14 29. " [29] ,Force SAI1_DMA_INT" "Normal,Forced" bitfld.long 0x14 28. " [28] ,Force SAI1_MOD_INT" "Normal,Forced" newline bitfld.long 0x14 27. " [27] ,Force SAI0_DMA_INT" "Normal,Forced" bitfld.long 0x14 26. " [26] ,Force SAI0_MOD_INT" "Normal,Forced" bitfld.long 0x14 24. " [24] ,Force MJPEG_DEC3_INT" "Normal,Forced" bitfld.long 0x14 23. " [23] ,Force MJPEG_DEC2_INT" "Normal,Forced" newline bitfld.long 0x14 22. " [22] ,Force MJPEG_DEC1_INT" "Normal,Forced" bitfld.long 0x14 21. " [21] ,Force MJPEG_DEC0_INT" "Normal,Forced" bitfld.long 0x14 20. " [20] ,Force MJPEG_ENC3_INT" "Normal,Forced" bitfld.long 0x14 19. " [19] ,Force MJPEG_ENC2_INT" "Normal,Forced" newline bitfld.long 0x14 18. " [18] ,Force MJPEG_ENC1_INT" "Normal,Forced" bitfld.long 0x14 17. " [17] ,Force MJPEG_ENC0_INT" "Normal,Forced" bitfld.long 0x14 16. " [16] ,Force PDMA_STREAM7_INT" "Normal,Forced" bitfld.long 0x14 15. " [15] ,Force PDMA_STREAM6_INT" "Normal,Forced" newline bitfld.long 0x14 14. " [14] ,Force PDMA_STREAM5_INT" "Normal,Forced" bitfld.long 0x14 13. " [13] ,Force PDMA_STREAM4_INT" "Normal,Forced" bitfld.long 0x14 12. " [12] ,Force PDMA_STREAM3_INT" "Normal,Forced" bitfld.long 0x14 11. " [11] ,Force PDMA_STREAM2_INT" "Normal,Forced" newline bitfld.long 0x14 10. " [10] ,Force PDMA_STREAM1_INT" "Normal,Forced" bitfld.long 0x14 9. " [9] ,Force PDMA_STREAM0_INT" "Normal,Forced" bitfld.long 0x14 0. " [0] ,Force MSI_INT" "Normal,Forced" line.long 0x18 "SET7,Interrupt Set 7 Register" bitfld.long 0x18 20. " FORCEFLD[20] ,Force DMA_ERR_INT" "Normal,Forced" bitfld.long 0x18 19. " [19] ,Force DMA_INT" "Normal,Forced" bitfld.long 0x18 18. " [18] ,Force APBHDMA" "Normal,Forced" bitfld.long 0x18 17. " [17] ,Force NAND_GPMI_INT" "Normal,Forced" newline bitfld.long 0x18 16. " [16] ,Force NAND_BCH_INT" "Normal,Forced" bitfld.long 0x18 15. " [15] ,Force USB3_INT" "Normal,Forced" bitfld.long 0x18 14. " [14] ,Force WAKEUP_INT" "Normal,Forced" bitfld.long 0x18 13. " [13] ,Force UTMI_INT" "Normal,Forced" newline bitfld.long 0x18 12. " [12] ,Force USB_HOST_INT" "Normal,Forced" bitfld.long 0x18 11. " [11] ,Force USB_OTG_INT" "Normal,Forced" bitfld.long 0x18 10. " [10] ,Force MLB_AHB_INT" "Normal,Forced" bitfld.long 0x18 9. " [9] ,Force MLB_INT" "Normal,Forced" newline bitfld.long 0x18 7. " [7] ,Force ENET1_TIMER_INT" "Normal,Forced" bitfld.long 0x18 6. " [6] ,Force ENET1_FRAME0_EVENT_INT" "Normal,Forced" bitfld.long 0x18 5. " [5] ,Force ENET1_FRAME2_INT" "Normal,Forced" bitfld.long 0x18 4. " [4] ,Force ENET1_FRAME1_INT" "Normal,Forced" newline bitfld.long 0x18 3. " [3] ,Force ENET0_TIMER_INT" "Normal,Forced" bitfld.long 0x18 2. " [2] ,Force ENET0_FRAME0_EVENT_INT" "Normal,Forced" bitfld.long 0x18 1. " [1] ,Force ENET0_FRAME2_INT" "Normal,Forced" bitfld.long 0x18 0. " [0] ,Force ENET0_FRAME1_INT" "Normal,Forced" line.long 0x1C "SET8,Interrupt Set 8 Register" bitfld.long 0x1C 23. " FORCEFLD[23] ,Force EXTERNAL_DMA_INT_5" "Normal,Forced" bitfld.long 0x1C 22. " [22] ,Force EXTERNAL_DMA_INT_4" "Normal,Forced" bitfld.long 0x1C 21. " [21] ,Force EXTERNAL_DMA_INT_3" "Normal,Forced" bitfld.long 0x1C 20. " [20] ,Force EXTERNAL_DMA_INT_2" "Normal,Forced" newline bitfld.long 0x1C 19. " [19] ,Force EXTERNAL_DMA_INT_1" "Normal,Forced" bitfld.long 0x1C 18. " [18] ,Force EXTERNAL_DMA_INT_0" "Normal,Forced" bitfld.long 0x1C 16. " [16] ,Force ADC_INT" "Normal,Forced" bitfld.long 0x1C 15. " [15] ,Force FTM1_INT" "Normal,Forced" newline bitfld.long 0x1C 14. " [14] ,Force FTM_INT" "Normal,Forced" bitfld.long 0x1C 13. " [13] ,Force FLEXCAN2_INT" "Normal,Forced" bitfld.long 0x1C 12. " [12] ,Force FLEXCAN1_INT" "Normal,Forced" bitfld.long 0x1C 11. " [11] ,Force FLEXCAN0_INT" "Normal,Forced" newline bitfld.long 0x1C 10. " [10] ,Force USDHC2_INT" "Normal,Forced" bitfld.long 0x1C 9. " [9] ,Force USDHC1_INT" "Normal,Forced" bitfld.long 0x1C 8. " [8] ,Force EMMC0_INT/USDHC0_INT" "Normal,Forced" bitfld.long 0x1C 4. " [4] ,Force UART3_INT" "Normal,Forced" newline bitfld.long 0x1C 3. " [3] ,Force UART2_INT" "Normal,Forced" bitfld.long 0x1C 2. " [2] ,Force UART1_INT" "Normal,Forced" bitfld.long 0x1C 1. " [1] ,Force UART0_INT" "Normal,Forced" line.long 0x20 "SET9,Interrupt Set 9 Register" bitfld.long 0x20 31. " FORCEFLD[31] ,Force I2C3_INT" "Normal,Forced" bitfld.long 0x20 30. " [30] ,Force I2C2_INT" "Normal,Forced" bitfld.long 0x20 29. " [29] ,Force I2C1_INT" "Normal,Forced" bitfld.long 0x20 28. " [28] ,Force I2C0_INT" "Normal,Forced" newline bitfld.long 0x20 27. " [27] ,Force SPI3_INT" "Normal,Forced" bitfld.long 0x20 26. " [26] ,Force SPI2_INT" "Normal,Forced" bitfld.long 0x20 25. " [25] ,Force SPI1_INT" "Normal,Forced" bitfld.long 0x20 24. " [24] ,Force SPI0_INT" "Normal,Forced" newline bitfld.long 0x20 16. " [16] ,Force MU13_INT_B" "Normal,Forced" bitfld.long 0x20 15. " [15] ,Force MU12_INT_B" "Normal,Forced" bitfld.long 0x20 14. " [14] ,Force MU11_INT_B" "Normal,Forced" bitfld.long 0x20 13. " [13] ,Force MU10_INT_B" "Normal,Forced" newline bitfld.long 0x20 12. " [12] ,Force MU9_INT_B" "Normal,Forced" bitfld.long 0x20 11. " [11] ,Force MU8_INT_B" "Normal,Forced" bitfld.long 0x20 10. " [10] ,Force MU7_INT_B" "Normal,Forced" bitfld.long 0x20 9. " [9] ,Force MU6_INT_B" "Normal,Forced" newline bitfld.long 0x20 8. " [8] ,Force MU5_INT_B" "Normal,Forced" bitfld.long 0x20 0. " [0] ,Force MU13_INT_A" "Normal,Forced" line.long 0x24 "SET10,Interrupt Set 10 Register" bitfld.long 0x24 31. " FORCEFLD[31] ,Force MU12_INT_A" "Normal,Forced" bitfld.long 0x24 30. " [30] ,Force MU11_INT_A" "Normal,Forced" bitfld.long 0x24 29. " [29] ,Force MU10_INT_A" "Normal,Forced" bitfld.long 0x24 28. " [28] ,Force MU9_INT_A" "Normal,Forced" newline bitfld.long 0x24 27. " [27] ,Force MU8_INT_A" "Normal,Forced" bitfld.long 0x24 26. " [26] ,Force MU7_INT_A" "Normal,Forced" bitfld.long 0x24 25. " [25] ,Force MU6_INT_A" "Normal,Forced" bitfld.long 0x24 24. " [24] ,Force MU5_INT_A" "Normal,Forced" newline bitfld.long 0x24 20. " [20] ,Force MU4_INT" "Normal,Forced" bitfld.long 0x24 19. " [19] ,Force MU3_INT" "Normal,Forced" bitfld.long 0x24 18. " [18] ,Force MU2_INT" "Normal,Forced" bitfld.long 0x24 17. " [17] ,Force MU1_INT" "Normal,Forced" newline bitfld.long 0x24 16. " [16] ,Force MU0_INT" "Normal,Forced" line.long 0x28 "SET11,Interrupt Set 11 Register" bitfld.long 0x28 15. " FORCEFLD[15] ,Force GPIO_INT[7]" "Normal,Forced" bitfld.long 0x28 14. " [14] ,Force GPIO_INT[6]" "Normal,Forced" bitfld.long 0x28 13. " [13] ,Force GPIO_INT[5]" "Normal,Forced" bitfld.long 0x28 12. " [12] ,Force GPIO_INT[4]" "Normal,Forced" newline bitfld.long 0x28 11. " [11] ,Force GPIO_INT[3]" "Normal,Forced" bitfld.long 0x28 10. " [10] ,Force GPIO_INT[2]" "Normal,Forced" bitfld.long 0x28 9. " [9] ,Force GPIO_INT[1]" "Normal,Forced" bitfld.long 0x28 8. " [8] ,Force GPIO_INT[0]" "Normal,Forced" newline bitfld.long 0x28 3. " [3] ,Force PERF_CNT_INT" "Normal,Forced" bitfld.long 0x28 2. " [2] ,Force SBR_DONE_INT" "Normal,Forced" bitfld.long 0x28 1. " [1] ,Force ECC_NCORRECT_INT" "Normal,Forced" bitfld.long 0x28 0. " [0] ,Force ECC_CORRECT_INT" "Normal,Forced" line.long 0x2C "SET12,Interrupt Set 12 Register" bitfld.long 0x2C 27. " FORCEFLD[27] ,Force SYS_COUNT_INT[3]" "Normal,Forced" bitfld.long 0x2C 26. " [26] ,Force SYS_COUNT_INT[2]" "Normal,Forced" bitfld.long 0x2C 25. " [25] ,Force SYS_COUNT_INT[1]" "Normal,Forced" bitfld.long 0x2C 24. " [24] ,Force SYS_COUNT_INT[0]" "Normal,Forced" newline bitfld.long 0x2C 23. " [23] ,Force INT_OUT[7]" "Normal,Forced" bitfld.long 0x2C 22. " [22] ,Force INT_OUT[6]" "Normal,Forced" bitfld.long 0x2C 21. " [21] ,Force INT_OUT[5]" "Normal,Forced" bitfld.long 0x2C 20. " [20] ,Force INT_OUT[4]" "Normal,Forced" newline bitfld.long 0x2C 19. " [19] ,Force INT_OUT[3]" "Normal,Forced" bitfld.long 0x2C 18. " [18] ,Force INT_OUT[2]" "Normal,Forced" bitfld.long 0x2C 17. " [17] ,Force INT_OUT[1]" "Normal,Forced" bitfld.long 0x2C 16. " [16] ,Force INT_OUT[0]" "Normal,Forced" newline bitfld.long 0x2C 15. " [15] ,Force PCIE9_GPIO_WAKEUP[1]" "Normal,Forced" bitfld.long 0x2C 14. " [14] ,Force PCIE9_GPIO_WAKEUP[0]" "Normal,Forced" bitfld.long 0x2C 13. " [13] ,Force PCIE0_SMLH_REQ_RST" "Normal,Forced" bitfld.long 0x2C 12. " [12] ,Force PCIE0_INT_A" "Normal,Forced" newline bitfld.long 0x2C 11. " [11] ,Force PCIE0_INT_B" "Normal,Forced" bitfld.long 0x2C 10. " [10] ,Force PCIE0_INT_C" "Normal,Forced" bitfld.long 0x2C 9. " [9] ,Force PCIE0_INT_D" "Normal,Forced" bitfld.long 0x2C 8. " [8] ,Force PCIE0_DMA_INT" "Normal,Forced" newline bitfld.long 0x2C 7. " [7] ,Force PCIE0_CLK_REQ_INT" "Normal,Forced" bitfld.long 0x2C 6. " [6] ,Force PCIE0_MSI_CTRL_INT" "Normal,Forced" bitfld.long 0x2C 5. " [5] ,Force PWM7_INT" "Normal,Forced" bitfld.long 0x2C 4. " [4] ,Force PWM6_INT" "Normal,Forced" newline bitfld.long 0x2C 3. " [3] ,Force PWM5_INT" "Normal,Forced" bitfld.long 0x2C 2. " [2] ,Force PWM4_INT" "Normal,Forced" bitfld.long 0x2C 1. " [1] ,Force PWM3_INT" "Normal,Forced" bitfld.long 0x2C 0. " [0] ,Force PWM2_INT" "Normal,Forced" line.long 0x30 "SET13,Interrupt Set 13 Register" bitfld.long 0x30 31. " FORCEFLD[31] ,Force PWM1_INT" "Normal,Forced" bitfld.long 0x30 30. " [30] ,Force PWM0_INT" "Normal,Forced" bitfld.long 0x30 29. " [29] ,Force FLEXSPI1_INT" "Normal,Forced" bitfld.long 0x30 28. " [28] ,Force FLEXSPI0_INT" "Normal,Forced" newline bitfld.long 0x30 21. " [21] ,Force KPP0_INT" "Normal,Forced" bitfld.long 0x30 20. " [20] ,Force GPT4_INT" "Normal,Forced" bitfld.long 0x30 19. " [19] ,Force GPT3_INT" "Normal,Forced" bitfld.long 0x30 18. " [18] ,Force GPT2_INT" "Normal,Forced" newline bitfld.long 0x30 17. " [17] ,Force GPT1_INT" "Normal,Forced" bitfld.long 0x30 16. " [16] ,Force GPT0_INT" "Normal,Forced" bitfld.long 0x30 5. " [5] ,Force DMA3_ERR_INT" "Normal,Forced" bitfld.long 0x30 4. " [4] ,Force DMA3_INT" "Normal,Forced" newline bitfld.long 0x30 3. " [3] ,Force DMA2_ERR_INT" "Normal,Forced" bitfld.long 0x30 2. " [2] ,Force DMA2_INT" "Normal,Forced" bitfld.long 0x30 0. " [0] ,Force XAQ2_INTR" "Normal,Forced" line.long 0x34 "SET14,Interrupt Set 14 Register" bitfld.long 0x34 31. " FORCEFLD[31] ,Force LCD_PWM_INT" "Normal,Forced" bitfld.long 0x34 30. " [30] ,Force LCD_MOD_INT" "Normal,Forced" bitfld.long 0x34 28. " [28] ,Force INT_OUT" "Normal,Forced" bitfld.long 0x34 27. " [27] ,Force INT_OUT" "Normal,Forced" newline bitfld.long 0x34 20. " [20] ,Force INT_OUT[12]" "Normal,Forced" bitfld.long 0x34 19. " [19] ,Force INT_OUT[11]" "Normal,Forced" bitfld.long 0x34 18. " [18] ,Force INT_OUT[10]" "Normal,Forced" bitfld.long 0x34 17. " [17] ,Force INT_OUT[9]" "Normal,Forced" newline bitfld.long 0x34 15. " [15] ,Force INT_OUT[7]" "Normal,Forced" bitfld.long 0x34 14. " [14] ,Force INT_OUT[6]" "Normal,Forced" bitfld.long 0x34 13. " [13] ,Force INT_OUT[5]" "Normal,Forced" bitfld.long 0x34 12. " [12] ,Force INT_OUT[4]" "Normal,Forced" newline bitfld.long 0x34 11. " [11] ,Force INT_OUT[3]" "Normal,Forced" bitfld.long 0x34 10. " [10] ,Force INT_OUT[2]" "Normal,Forced" bitfld.long 0x34 9. " [9] ,Force INT_OUT[1]" "Normal,Forced" bitfld.long 0x34 8. " [8] ,Force INT_OUT[0]" "Normal,Forced" line.long 0x38 "SET15,Interrupt Set 15 Register" bitfld.long 0x38 23. " FORCEFLD[23] ,Force INT_OUT[7]" "Normal,Forced" bitfld.long 0x38 22. " [22] ,Force INT_OUT[6]" "Normal,Forced" bitfld.long 0x38 21. " [21] ,Force INT_OUT[5]" "Normal,Forced" bitfld.long 0x38 20. " [20] ,Force INT_OUT[4]" "Normal,Forced" newline bitfld.long 0x38 19. " [19] ,Force INT_OUT[3]" "Normal,Forced" bitfld.long 0x38 18. " [18] ,Force INT_OUT[2]" "Normal,Forced" bitfld.long 0x38 17. " [17] ,Force INT_OUT[1]" "Normal,Forced" bitfld.long 0x38 16. " [16] ,Force INT_OUT[0]" "Normal,Forced" newline bitfld.long 0x38 1. " [1] ,Force nEXTERRIRQ" "Normal,Forced" bitfld.long 0x38 0. " [0] ,Force nINTERRIRQ" "Normal,Forced" rgroup.long 0x88++0x3B line.long 0x00 "STATUS1,Interrupt Status 1 Register" bitfld.long 0x00 22. " STATUS[22] ,VPU_INT_6 status" "Not set,Set" bitfld.long 0x00 21. " [21] ,VPU_INT_5 status" "Not set,Set" bitfld.long 0x00 20. " [20] ,VPU_INT_4 status" "Not set,Set" bitfld.long 0x00 19. " [19] ,VPU_INT_3 status" "Not set,Set" newline bitfld.long 0x00 18. " [18] ,VPU_INT_2 status" "Not set,Set" bitfld.long 0x00 17. " [17] ,VPU_INT_1 status" "Not set,Set" bitfld.long 0x00 16. " [16] ,VPU_INT_0 status" "Not set,Set" bitfld.long 0x00 11. " [11] ,SPDIF0_TX_DMA_INT status" "Not set,Set" newline bitfld.long 0x00 10. " [10] ,SPDIF0_TX_MOD_INT status" "Not set,Set" bitfld.long 0x00 9. " [9] ,SPDIF0_RX_DMA_INT status" "Not set,Set" bitfld.long 0x00 8. " [8] ,SPDIF0_RX_MOD_INT status" "Not set,Set" bitfld.long 0x00 7. " [7] ,CAAM_RTIC_INT status" "Not set,Set" newline bitfld.long 0x00 6. " [6] ,CAAM_INT3 status" "Not set,Set" bitfld.long 0x00 5. " [5] ,CAAM_INT2 status" "Not set,Set" bitfld.long 0x00 4. " [4] ,CAAM_INT1 status" "Not set,Set" bitfld.long 0x00 3. " [3] ,CAAM_INT0 status" "Not set,Set" newline bitfld.long 0x00 2. " [2] ,SEC_MU3_A_INT status" "Not set,Set" bitfld.long 0x00 1. " [1] ,SEC_MU2_A_INT status" "Not set,Set" bitfld.long 0x00 0. " [0] ,SEC_MU1_A_INT status" "Not set,Set" line.long 0x04 "STATUS2,Interrupt Status 2 Register" bitfld.long 0x04 25. " STATUS[25] ,UART3_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 24. " [24] ,UART3_DMA_RX_INT status" "Not set,Set" bitfld.long 0x04 23. " [23] ,UART2_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 22. " [22] ,UART2_DMA_RX_INT status" "Not set,Set" newline bitfld.long 0x04 21. " [21] ,UART1_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 20. " [20] ,UART1_DMA_RX_INT status" "Not set,Set" bitfld.long 0x04 19. " [19] ,UART0_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 18. " [18] ,UART0_DMA_RX_INT status" "Not set,Set" newline bitfld.long 0x04 15. " [15] ,I2C3_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 14. " [14] ,I2C3_DMA_RX_INT status" "Not set,Set" bitfld.long 0x04 13. " [13] ,I2C2_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 12. " [12] ,I2C2_DMA_RX_INT status" "Not set,Set" newline bitfld.long 0x04 11. " [11] ,I2C1_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 10. " [10] ,I2C1_DMA_RX_INT status" "Not set,Set" bitfld.long 0x04 9. " [9] ,I2C0_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 8. " [8] ,I2C0_DMA_RX_INT status" "Not set,Set" newline bitfld.long 0x04 7. " [7] ,SPI3_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 6. " [6] ,SPI3_DMA_RX_INT status" "Not set,Set" bitfld.long 0x04 5. " [5] ,SPI2_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 4. " [4] ,SPI2_DMA_RX_INT status" "Not set,Set" newline bitfld.long 0x04 3. " [3] ,SPI1_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 2. " [2] ,SPI1_DMA_RX_INT status" "Not set,Set" bitfld.long 0x04 1. " [1] ,SPI0_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 0. " [0] ,SPI0_DMA_RX_INT status" "Not set,Set" line.long 0x08 "STATUS3,Interrupt Status 3 Register" bitfld.long 0x08 26. " STATUS[26] ,ESAI0_DMA_INT status" "Not set,Set" bitfld.long 0x08 25. " [25] ,ESAI0_MOD_INT status" "Not set,Set" bitfld.long 0x08 22. " [22] ,SPDIF0_TX_INT status" "Not set,Set" bitfld.long 0x08 21. " [21] ,SPDIF0_RX_INT status" "Not set,Set" newline bitfld.long 0x08 20. " [20] ,SAI5_INT status" "Not set,Set" bitfld.long 0x08 19. " [19] ,SAI4_INT status" "Not set,Set" bitfld.long 0x08 16. " [16] ,SAI3_INT status" "Not set,Set" bitfld.long 0x08 15. " [15] ,SAI2_INT status" "Not set,Set" newline bitfld.long 0x08 14. " [14] ,SAI1_INT status" "Not set,Set" bitfld.long 0x08 13. " [13] ,SAI0_INT status" "Not set,Set" bitfld.long 0x08 12. " [12] ,GPT5_INT status" "Not set,Set" bitfld.long 0x08 11. " [11] ,GPT4_INT status" "Not set,Set" newline bitfld.long 0x08 10. " [10] ,GPT3_INT status" "Not set,Set" bitfld.long 0x08 9. " [9] ,GPT2_INT status" "Not set,Set" bitfld.long 0x08 8. " [8] ,GPT1_INT status" "Not set,Set" bitfld.long 0x08 7. " [7] ,GPT0_INT status" "Not set,Set" newline bitfld.long 0x08 4. " [4] ,ESAI0_INT status" "Not set,Set" bitfld.long 0x08 3. " [3] ,DMA1_CH5_INT status" "Not set,Set" bitfld.long 0x08 2. " [2] ,DMA1_CH4_INT status" "Not set,Set" bitfld.long 0x08 1. " [1] ,DMA1_CH3_INT status" "Not set,Set" newline bitfld.long 0x08 0. " [0] ,DMA1_CH2_INT status" "Not set,Set" line.long 0x0C "STATUS4,Interrupt Status 4 Register" bitfld.long 0x0C 31. " STATUS[31] ,DMA1_CH1_INT status" "Not set,Set" bitfld.long 0x0C 30. " [30] ,DMA1_CH0_INT status" "Not set,Set" bitfld.long 0x0C 29. " [29] ,ASRC1_INT2 status" "Not set,Set" bitfld.long 0x0C 28. " [28] ,ASRC1_INT1 status" "Not set,Set" newline bitfld.long 0x0C 27. " [27] ,DMA0_CH5_INT status" "Not set,Set" bitfld.long 0x0C 26. " [26] ,DMA0_CH4_INT status" "Not set,Set" bitfld.long 0x0C 25. " [25] ,DMA0_CH3_INT status" "Not set,Set" bitfld.long 0x0C 24. " [24] ,DMA0_CH2_INT status" "Not set,Set" newline bitfld.long 0x0C 23. " [23] ,DMA0_CH1_INT status" "Not set,Set" bitfld.long 0x0C 22. " [22] ,DMA0_CH0_INT status" "Not set,Set" bitfld.long 0x0C 21. " [21] ,ASRC0_INT2 status" "Not set,Set" bitfld.long 0x0C 20. " [20] ,ASRC0_INT1 status" "Not set,Set" newline bitfld.long 0x0C 19. " [19] ,DMA1_ERR_INT status" "Not set,Set" bitfld.long 0x0C 18. " [18] ,DMA1_INT status" "Not set,Set" bitfld.long 0x0C 17. " [17] ,DMA0_ERR_INT status" "Not set,Set" bitfld.long 0x0C 16. " [16] ,DMA0_INT status" "Not set,Set" newline bitfld.long 0x0C 12. " [12] ,ADC_DMA_INT status" "Not set,Set" bitfld.long 0x0C 11. " [11] ,FTM1_DMA_INT status" "Not set,Set" bitfld.long 0x0C 10. " [10] ,FTM_DMA_INT status" "Not set,Set" bitfld.long 0x0C 9. " [9] ,FLEXCAN2_DMA_INT status" "Not set,Set" newline bitfld.long 0x0C 8. " [8] ,FLEXCAN1_DMA_INT status" "Not set,Set" bitfld.long 0x0C 7. " [7] ,FLEXCAN0_DMA_INT status" "Not set,Set" bitfld.long 0x0C 5. " [5] ,ADC_MOD_INT status" "Not set,Set" bitfld.long 0x0C 4. " [4] ,FTM1_MOD_INT status" "Not set,Set" newline bitfld.long 0x0C 3. " [3] ,FTM_MOD_INT status" "Not set,Set" bitfld.long 0x0C 2. " [2] ,FLEXCAN2_MOD_INT status" "Not set,Set" bitfld.long 0x0C 1. " [1] ,FLEXCAN1_MOD_INT status" "Not set,Set" bitfld.long 0x0C 0. " [0] ,FLEXCAN0_MOD_INT status" "Not set,Set" line.long 0x10 "STATUS5,Interrupt Status 5 Register" bitfld.long 0x10 28. " STATUS[28] ,UART3_MOD_INT status" "Not set,Set" bitfld.long 0x10 27. " [27] ,UART2_MOD_INT status" "Not set,Set" bitfld.long 0x10 26. " [26] ,UART1_MOD_INT status" "Not set,Set" bitfld.long 0x10 25. " [25] ,UART0_MOD_INT status" "Not set,Set" newline bitfld.long 0x10 23. " [23] ,I2C3_MOD_INT status" "Not set,Set" bitfld.long 0x10 22. " [22] ,I2C2_MOD_INT status" "Not set,Set" bitfld.long 0x10 21. " [21] ,I2C1_MOD_INT status" "Not set,Set" bitfld.long 0x10 20. " [20] ,I2C0_MOD_INT status" "Not set,Set" newline bitfld.long 0x10 19. " [19] ,SPI3_MOD_INT status" "Not set,Set" bitfld.long 0x10 18. " [18] ,SPI2_MOD_INT status" "Not set,Set" bitfld.long 0x10 17. " [17] ,SPI1_MOD_INT status" "Not set,Set" bitfld.long 0x10 16. " [16] ,SPI0_MOD_INT status" "Not set,Set" newline bitfld.long 0x10 12. " [12] ,SAI5_DMA_INT status" "Not set,Set" bitfld.long 0x10 11. " [11] ,SAI5_MOD_INT status" "Not set,Set" bitfld.long 0x10 10. " [10] ,SAI4_DMA_INT status" "Not set,Set" bitfld.long 0x10 9. " [9] ,SAI4_MOD_INT status" "Not set,Set" newline bitfld.long 0x10 4. " [4] ,SAI3_DMA_INT status" "Not set,Set" bitfld.long 0x10 3. " [3] ,SAI3_MOD_INT status" "Not set,Set" bitfld.long 0x10 0. " [0] ,INT_OUT status" "Not set,Set" line.long 0x14 "STATUS6,Interrupt Status 6 Register" bitfld.long 0x14 31. " STATUS[31] ,SAI2_DMA_INT status" "Not set,Set" bitfld.long 0x14 30. " [30] ,SAI2_MOD_INT status" "Not set,Set" bitfld.long 0x14 29. " [29] ,SAI1_DMA_INT status" "Not set,Set" bitfld.long 0x14 28. " [28] ,SAI1_MOD_INT status" "Not set,Set" newline bitfld.long 0x14 27. " [27] ,SAI0_DMA_INT status" "Not set,Set" bitfld.long 0x14 26. " [26] ,SAI0_MOD_INT status" "Not set,Set" bitfld.long 0x14 24. " [24] ,MJPEG_DEC3_INT status" "Not set,Set" bitfld.long 0x14 23. " [23] ,MJPEG_DEC2_INT status" "Not set,Set" newline bitfld.long 0x14 22. " [22] ,MJPEG_DEC1_INT status" "Not set,Set" bitfld.long 0x14 21. " [21] ,MJPEG_DEC0_INT status" "Not set,Set" bitfld.long 0x14 20. " [20] ,MJPEG_ENC3_INT status" "Not set,Set" bitfld.long 0x14 19. " [19] ,MJPEG_ENC2_INT status" "Not set,Set" newline bitfld.long 0x14 18. " [18] ,MJPEG_ENC1_INT status" "Not set,Set" bitfld.long 0x14 17. " [17] ,MJPEG_ENC0_INT status" "Not set,Set" bitfld.long 0x14 16. " [16] ,PDMA_STREAM7_INT status" "Not set,Set" bitfld.long 0x14 15. " [15] ,PDMA_STREAM6_INT status" "Not set,Set" newline bitfld.long 0x14 14. " [14] ,PDMA_STREAM5_INT status" "Not set,Set" bitfld.long 0x14 13. " [13] ,PDMA_STREAM4_INT status" "Not set,Set" bitfld.long 0x14 12. " [12] ,PDMA_STREAM3_INT status" "Not set,Set" bitfld.long 0x14 11. " [11] ,PDMA_STREAM2_INT status" "Not set,Set" newline bitfld.long 0x14 10. " [10] ,PDMA_STREAM1_INT status" "Not set,Set" bitfld.long 0x14 9. " [9] ,PDMA_STREAM0_INT status" "Not set,Set" bitfld.long 0x14 0. " [0] ,MSI_INT status" "Not set,Set" line.long 0x18 "STATUS7,Interrupt Status 7 Register" bitfld.long 0x18 20. " STATUS[20] ,DMA_ERR_INT status" "Not set,Set" bitfld.long 0x18 19. " [19] ,DMA_INT status" "Not set,Set" bitfld.long 0x18 18. " [18] ,APBHDMA status" "Not set,Set" bitfld.long 0x18 17. " [17] ,NAND_GPMI_INT status" "Not set,Set" newline bitfld.long 0x18 16. " [16] ,NAND_BCH_INT status" "Not set,Set" bitfld.long 0x18 15. " [15] ,USB3_INT status" "Not set,Set" bitfld.long 0x18 14. " [14] ,WAKEUP_INT status" "Not set,Set" bitfld.long 0x18 13. " [13] ,UTMI_INT status" "Not set,Set" newline bitfld.long 0x18 12. " [12] ,USB_HOST_INT status" "Not set,Set" bitfld.long 0x18 11. " [11] ,USB_OTG_INT status" "Not set,Set" bitfld.long 0x18 10. " [10] ,MLB_AHB_INT status" "Not set,Set" bitfld.long 0x18 9. " [9] ,MLB_INT status" "Not set,Set" newline bitfld.long 0x18 7. " [7] ,ENET1_TIMER_INT status" "Not set,Set" bitfld.long 0x18 6. " [6] ,ENET1_FRAME0_EVENT_INT status" "Not set,Set" bitfld.long 0x18 5. " [5] ,ENET1_FRAME2_INT status" "Not set,Set" bitfld.long 0x18 4. " [4] ,ENET1_FRAME1_INT status" "Not set,Set" newline bitfld.long 0x18 3. " [3] ,ENET0_TIMER_INT status" "Not set,Set" bitfld.long 0x18 2. " [2] ,ENET0_FRAME0_EVENT_INT status" "Not set,Set" bitfld.long 0x18 1. " [1] ,ENET0_FRAME2_INT status" "Not set,Set" bitfld.long 0x18 0. " [0] ,ENET0_FRAME1_INT status" "Not set,Set" line.long 0x1C "STATUS8,Interrupt Status 8 Register" bitfld.long 0x1C 23. " STATUS[23] ,EXTERNAL_DMA_INT_5 status" "Not set,Set" bitfld.long 0x1C 22. " [22] ,EXTERNAL_DMA_INT_4 status" "Not set,Set" bitfld.long 0x1C 21. " [21] ,EXTERNAL_DMA_INT_3 status" "Not set,Set" bitfld.long 0x1C 20. " [20] ,EXTERNAL_DMA_INT_2 status" "Not set,Set" newline bitfld.long 0x1C 19. " [19] ,EXTERNAL_DMA_INT_1 status" "Not set,Set" bitfld.long 0x1C 18. " [18] ,EXTERNAL_DMA_INT_0 status" "Not set,Set" bitfld.long 0x1C 16. " [16] ,ADC_INT status" "Not set,Set" bitfld.long 0x1C 15. " [15] ,FTM1_INT status" "Not set,Set" newline bitfld.long 0x1C 14. " [14] ,FTM_INT status" "Not set,Set" bitfld.long 0x1C 13. " [13] ,FLEXCAN2_INT status" "Not set,Set" bitfld.long 0x1C 12. " [12] ,FLEXCAN1_INT status" "Not set,Set" bitfld.long 0x1C 11. " [11] ,FLEXCAN0_INT status" "Not set,Set" newline bitfld.long 0x1C 10. " [10] ,USDHC2_INT status" "Not set,Set" bitfld.long 0x1C 9. " [9] ,USDHC1_INT status" "Not set,Set" bitfld.long 0x1C 8. " [8] ,EMMC0_INT/USDHC0_INT status" "Not set,Set" bitfld.long 0x1C 4. " [4] ,UART3_INT status" "Not set,Set" newline bitfld.long 0x1C 3. " [3] ,UART2_INT status" "Not set,Set" bitfld.long 0x1C 2. " [2] ,UART1_INT status" "Not set,Set" bitfld.long 0x1C 1. " [1] ,UART0_INT status" "Not set,Set" line.long 0x20 "STATUS9,Interrupt Status 9 Register" bitfld.long 0x20 31. " STATUS[31] ,I2C3_INT status" "Not set,Set" bitfld.long 0x20 30. " [30] ,I2C2_INT status" "Not set,Set" bitfld.long 0x20 29. " [29] ,I2C1_INT status" "Not set,Set" bitfld.long 0x20 28. " [28] ,I2C0_INT status" "Not set,Set" newline bitfld.long 0x20 27. " [27] ,SPI3_INT status" "Not set,Set" bitfld.long 0x20 26. " [26] ,SPI2_INT status" "Not set,Set" bitfld.long 0x20 25. " [25] ,SPI1_INT status" "Not set,Set" bitfld.long 0x20 24. " [24] ,SPI0_INT status" "Not set,Set" newline bitfld.long 0x20 16. " [16] ,MU13_INT_B status" "Not set,Set" bitfld.long 0x20 15. " [15] ,MU12_INT_B status" "Not set,Set" bitfld.long 0x20 14. " [14] ,MU11_INT_B status" "Not set,Set" bitfld.long 0x20 13. " [13] ,MU10_INT_B status" "Not set,Set" newline bitfld.long 0x20 12. " [12] ,MU9_INT_B status" "Not set,Set" bitfld.long 0x20 11. " [11] ,MU8_INT_B status" "Not set,Set" bitfld.long 0x20 10. " [10] ,MU7_INT_B status" "Not set,Set" bitfld.long 0x20 9. " [9] ,MU6_INT_B status" "Not set,Set" newline bitfld.long 0x20 8. " [8] ,MU5_INT_B status" "Not set,Set" bitfld.long 0x20 0. " [0] ,MU13_INT_A status" "Not set,Set" line.long 0x24 "STATUS10,Interrupt Status 10 Register" bitfld.long 0x24 31. " STATUS[31] ,MU12_INT_A status" "Not set,Set" bitfld.long 0x24 30. " [30] ,MU11_INT_A status" "Not set,Set" bitfld.long 0x24 29. " [29] ,MU10_INT_A status" "Not set,Set" bitfld.long 0x24 28. " [28] ,MU9_INT_A status" "Not set,Set" newline bitfld.long 0x24 27. " [27] ,MU8_INT_A status" "Not set,Set" bitfld.long 0x24 26. " [26] ,MU7_INT_A status" "Not set,Set" bitfld.long 0x24 25. " [25] ,MU6_INT_A status" "Not set,Set" bitfld.long 0x24 24. " [24] ,MU5_INT_A status" "Not set,Set" newline bitfld.long 0x24 20. " [20] ,MU4_INT status" "Not set,Set" bitfld.long 0x24 19. " [19] ,MU3_INT status" "Not set,Set" bitfld.long 0x24 18. " [18] ,MU2_INT status" "Not set,Set" bitfld.long 0x24 17. " [17] ,MU1_INT status" "Not set,Set" newline bitfld.long 0x24 16. " [16] ,MU0_INT status" "Not set,Set" line.long 0x28 "STATUS11,Interrupt Status 11 Register" bitfld.long 0x28 15. " STATUS[15] ,GPIO_INT[7] status" "Not set,Set" bitfld.long 0x28 14. " [14] ,GPIO_INT[6] status" "Not set,Set" bitfld.long 0x28 13. " [13] ,GPIO_INT[5] status" "Not set,Set" bitfld.long 0x28 12. " [12] ,GPIO_INT[4] status" "Not set,Set" newline bitfld.long 0x28 11. " [11] ,GPIO_INT[3] status" "Not set,Set" bitfld.long 0x28 10. " [10] ,GPIO_INT[2] status" "Not set,Set" bitfld.long 0x28 9. " [9] ,GPIO_INT[1] status" "Not set,Set" bitfld.long 0x28 8. " [8] ,GPIO_INT[0] status" "Not set,Set" newline bitfld.long 0x28 3. " [3] ,PERF_CNT_INT status" "Not set,Set" bitfld.long 0x28 2. " [2] ,SBR_DONE_INT status" "Not set,Set" bitfld.long 0x28 1. " [1] ,ECC_NCORRECT_INT status" "Not set,Set" bitfld.long 0x28 0. " [0] ,ECC_CORRECT_INT status" "Not set,Set" line.long 0x2C "STATUS12,Interrupt Status 12 Register" bitfld.long 0x2C 27. " STATUS[27] ,SYS_COUNT_INT[3] status" "Not set,Set" bitfld.long 0x2C 26. " [26] ,SYS_COUNT_INT[2] status" "Not set,Set" bitfld.long 0x2C 25. " [25] ,SYS_COUNT_INT[1] status" "Not set,Set" bitfld.long 0x2C 24. " [24] ,SYS_COUNT_INT[0] status" "Not set,Set" newline bitfld.long 0x2C 23. " [23] ,INT_OUT[7] status" "Not set,Set" bitfld.long 0x2C 22. " [22] ,INT_OUT[6] status" "Not set,Set" bitfld.long 0x2C 21. " [21] ,INT_OUT[5] status" "Not set,Set" bitfld.long 0x2C 20. " [20] ,INT_OUT[4] status" "Not set,Set" newline bitfld.long 0x2C 19. " [19] ,INT_OUT[3] status" "Not set,Set" bitfld.long 0x2C 18. " [18] ,INT_OUT[2] status" "Not set,Set" bitfld.long 0x2C 17. " [17] ,INT_OUT[1] status" "Not set,Set" bitfld.long 0x2C 16. " [16] ,INT_OUT[0] status" "Not set,Set" newline bitfld.long 0x2C 15. " [15] ,PCIE9_GPIO_WAKEUP[1] status" "Not set,Set" bitfld.long 0x2C 14. " [14] ,PCIE9_GPIO_WAKEUP[0] status" "Not set,Set" bitfld.long 0x2C 13. " [13] ,PCIE0_SMLH_REQ_RST status" "Not set,Set" bitfld.long 0x2C 12. " [12] ,PCIE0_INT_A status" "Not set,Set" newline bitfld.long 0x2C 11. " [11] ,PCIE0_INT_B status" "Not set,Set" bitfld.long 0x2C 10. " [10] ,PCIE0_INT_C status" "Not set,Set" bitfld.long 0x2C 9. " [9] ,PCIE0_INT_D status" "Not set,Set" bitfld.long 0x2C 8. " [8] ,PCIE0_DMA_INT status" "Not set,Set" newline bitfld.long 0x2C 7. " [7] ,PCIE0_CLK_REQ_INT status" "Not set,Set" bitfld.long 0x2C 6. " [6] ,PCIE0_MSI_CTRL_INT status" "Not set,Set" bitfld.long 0x2C 5. " [5] ,PWM7_INT status" "Not set,Set" bitfld.long 0x2C 4. " [4] ,PWM6_INT status" "Not set,Set" newline bitfld.long 0x2C 3. " [3] ,PWM5_INT status" "Not set,Set" bitfld.long 0x2C 2. " [2] ,PWM4_INT status" "Not set,Set" bitfld.long 0x2C 1. " [1] ,PWM3_INT status" "Not set,Set" bitfld.long 0x2C 0. " [0] ,PWM2_INT status" "Not set,Set" line.long 0x30 "STATUS13,Interrupt Status 13 Register" bitfld.long 0x30 31. " STATUS[31] ,PWM1_INT status" "Not set,Set" bitfld.long 0x30 30. " [30] ,PWM0_INT status" "Not set,Set" bitfld.long 0x30 29. " [29] ,FLEXSPI1_INT status" "Not set,Set" bitfld.long 0x30 28. " [28] ,FLEXSPI0_INT status" "Not set,Set" newline bitfld.long 0x30 21. " [21] ,KPP0_INT status" "Not set,Set" bitfld.long 0x30 20. " [20] ,GPT4_INT status" "Not set,Set" bitfld.long 0x30 19. " [19] ,GPT3_INT status" "Not set,Set" bitfld.long 0x30 18. " [18] ,GPT2_INT status" "Not set,Set" newline bitfld.long 0x30 17. " [17] ,GPT1_INT status" "Not set,Set" bitfld.long 0x30 16. " [16] ,GPT0_INT status" "Not set,Set" bitfld.long 0x30 5. " [5] ,DMA3_ERR_INT status" "Not set,Set" bitfld.long 0x30 4. " [4] ,DMA3_INT status" "Not set,Set" newline bitfld.long 0x30 3. " [3] ,DMA2_ERR_INT status" "Not set,Set" bitfld.long 0x30 2. " [2] ,DMA2_INT status" "Not set,Set" bitfld.long 0x30 0. " [0] ,XAQ2_INTR status" "Not set,Set" line.long 0x34 "STATUS14,Interrupt Status 14 Register" bitfld.long 0x34 31. " STATUS[31] ,LCD_PWM_INT status" "Not set,Set" bitfld.long 0x34 30. " [30] ,LCD_MOD_INT status" "Not set,Set" bitfld.long 0x34 28. " [28] ,INT_OUT status" "Not set,Set" bitfld.long 0x34 27. " [27] ,INT_OUT status" "Not set,Set" newline bitfld.long 0x34 20. " [20] ,INT_OUT[12] status" "Not set,Set" bitfld.long 0x34 19. " [19] ,INT_OUT[11] status" "Not set,Set" bitfld.long 0x34 18. " [18] ,INT_OUT[10] status" "Not set,Set" bitfld.long 0x34 17. " [17] ,INT_OUT[9] status" "Not set,Set" newline bitfld.long 0x34 15. " [15] ,INT_OUT[7] status" "Not set,Set" bitfld.long 0x34 14. " [14] ,INT_OUT[6] status" "Not set,Set" bitfld.long 0x34 13. " [13] ,INT_OUT[5] status" "Not set,Set" bitfld.long 0x34 12. " [12] ,INT_OUT[4] status" "Not set,Set" newline bitfld.long 0x34 11. " [11] ,INT_OUT[3] status" "Not set,Set" bitfld.long 0x34 10. " [10] ,INT_OUT[2] status" "Not set,Set" bitfld.long 0x34 9. " [9] ,INT_OUT[1] status" "Not set,Set" bitfld.long 0x34 8. " [8] ,INT_OUT[0] status" "Not set,Set" line.long 0x38 "STATUS15,Interrupt Status 15 Register" bitfld.long 0x38 23. " STATUS[23] ,INT_OUT[7] status" "Not set,Set" bitfld.long 0x38 22. " [22] ,INT_OUT[6] status" "Not set,Set" bitfld.long 0x38 21. " [21] ,INT_OUT[5] status" "Not set,Set" bitfld.long 0x38 20. " [20] ,INT_OUT[4] status" "Not set,Set" newline bitfld.long 0x38 19. " [19] ,INT_OUT[3] status" "Not set,Set" bitfld.long 0x38 18. " [18] ,INT_OUT[2] status" "Not set,Set" bitfld.long 0x38 17. " [17] ,INT_OUT[1] status" "Not set,Set" bitfld.long 0x38 16. " [16] ,INT_OUT[0] status" "Not set,Set" newline bitfld.long 0x38 1. " [1] ,nEXTERRIRQ status" "Not set,Set" bitfld.long 0x38 0. " [0] ,nINTERRIRQ status" "Not set,Set" group.long 0xC4++0x03 line.long 0x00 "MINTDIS,Master Interrupt Disable Register" bitfld.long 0x00 7. " DISABLE[7] ,Disables interrupts from 511 to 448" "No,Yes" bitfld.long 0x00 6. " [6] ,Disables interrupts from 447 to 384" "No,Yes" bitfld.long 0x00 5. " [5] ,Disables interrupts from 383 to 320" "No,Yes" bitfld.long 0x00 4. " [4] ,Disables interrupts from 319 to 256" "No,Yes" newline bitfld.long 0x00 3. " [3] ,Disables interrupts from 255 to 192" "No,Yes" bitfld.long 0x00 2. " [2] ,Disables interrupts from 191 to 128" "No,Yes" bitfld.long 0x00 1. " [1] ,Disables interrupts from 127 to 64" "No,Yes" bitfld.long 0x00 0. " [0] ,Disables interrupts from 63 to 0" "No,Yes" newline rgroup.long 0xC8++0x03 line.long 0x00 "MSTRSTAT,Master Status Register" bitfld.long 0x00 0. " STATUS ,Status of all interrupts" "Not asserted,At least one interrupt is asserted" width 0x0B tree.end tree.end tree.end tree.open "Imaging" ; tree "ISI (Image Sensing Interface)" ; base ad:0x00 ; %include imx8x/isi.ph ; tree.end tree "JPEGENC (JPEG Encoder)" base ad:0x585F0000 width 14. wgroup.long 0x00++0x03 line.long 0x00 "MODE,MODE Control Register" bitfld.long 0x00 8. " AUTOCLR_GO ,Auto clear GO bit enable" "Disabled,Enabled" bitfld.long 0x00 7. " AUTOCLR_CONF ,Auto clear CONF bit enable" "Disabled,Enabled" bitfld.long 0x00 6. " GO ,Low power idle mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " CONF ,Configuration mode enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " EXTSEQ ,Baseline/Extended Sequential mode select" "Baseline,Extended Sequential" bitfld.long 0x00 3. " MS ,Multi-scan JPEG encoding mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " SWR ,Soft reset" "No reset,Reset" bitfld.long 0x00 0. " LP ,Low power mode enable" "Disabled,Enabled" rgroup.long 0x00++0x03 line.long 0x00 "STATUS_0,Status 0 Register" hexmask.long.word 0x00 0.--15. 1. " X ,Image width" wgroup.long 0x04++0x03 line.long 0x00 "CFG_MODE,CFG_MODE Control Register" bitfld.long 0x00 10. " DICOM ,SOF and SOS markers transfer" "No transfer,Transfer" bitfld.long 0x00 9. " COMB_DHT ,Huffman tables transfer" "No transfer,Transfer" bitfld.long 0x00 8. " COMB_DQT ,Quantization tables transfer" "No transfer,Transfer" bitfld.long 0x00 7. " MCOM ,Mask COM" "0,1" newline bitfld.long 0x00 6. " MAPP ,Mask APP" "0,1" bitfld.long 0x00 5. " MDNL ,Mask DNL" "0,1" bitfld.long 0x00 4. " MSOS ,Mask SOS" "0,1" bitfld.long 0x00 3. " MDHT ,Mask DHT" "0,1" newline bitfld.long 0x00 2. " MDQT ,Mask DQT" "0,1" bitfld.long 0x00 1. " MDRI ,Mask DRI" "0,1" bitfld.long 0x00 0. " MSOF0 ,Mask SOF0" "0,1" rgroup.long 0x04++0x03 line.long 0x00 "STATUS_1,Status 1 Register" hexmask.long.word 0x00 0.--15. 1. " Y ,Image height" wgroup.long 0x08++0x03 line.long 0x00 "QUALITY,Quality Register" hexmask.long.byte 0x00 0.--6. 1. " QUALITY ,Quality factor that is applied to the programmed quantization tables" rgroup.long 0x08++0x03 line.long 0x00 "STATUS_2,Status 2 Register" hexmask.long.word 0x00 0.--15. 1. " HMCU ,Number of MCUs in current scan in horizontal direction" rgroup.long 0x0C++0x03 line.long 0x00 "STATUS_3,Status 3 Register" hexmask.long.word 0x00 0.--15. 1. " VMCU ,Number of MCUs in current scan in vertical direction" wgroup.long 0x10++0x03 line.long 0x00 "REC_REGS_SEL,Indirect Status Register Select" bitfld.long 0x00 0.--1. " RC_REGS_SEL ,Indirect status register select" "RC_REGS0->LUMTH/RC_REGS1->CHRTH,RC_REGS0->[31:16] with total truncated bits of luminance blocks/RC_REGS1->[15:0] with total truncated bits of luminance blocks,RC_REGS0->[31:16] with total truncated bits of chrominance blocks/RC_REGS1->[15:0] with total truncated bits of chrominance blocks,?..." rgroup.long 0x10++0x03 line.long 0x00 "STATUS_4,Status 4 Register" hexmask.long.byte 0x00 8.--15. 1. " C0 ,Frame component identifier for scan component 0" bitfld.long 0x00 5.--7. " H0 ,Horizontal sampling for scan component 0" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2.--4. " V0 ,Vertical sampling for scan component 0" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--1. " TQ0 ,Quantization table identifier for scan component 0" "0,1,2,3" wgroup.long 0x14++0x03 line.long 0x00 "LUMTH,LUMTH Register" hexmask.long.word 0x00 0.--15. 1. " LUMTH ,Maximum number of bits threshold used in rate control of luminance DCT blocks" rgroup.long 0x14++0x03 line.long 0x00 "STATUS_5,Status 5 Register" hexmask.long.byte 0x00 8.--15. 1. " C1 ,Frame component identifier for scan component 1" bitfld.long 0x00 5.--7. " H1 ,Horizontal sampling for scan component 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2.--4. " V1 ,Vertical sampling for scan component 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--1. " TQ1 ,Quantization table identifier for scan component 1" "0,1,2,3" wgroup.long 0x18++0x03 line.long 0x00 "CHRTH,CHRTH Register" hexmask.long.word 0x00 0.--15. 1. " CHRTH ,Maximum number of bits threshold used in rate control of chrominance DCT blocks" rgroup.long 0x18++0x03 line.long 0x00 "STATUS_6,Status 6 Register" hexmask.long.byte 0x00 8.--15. 1. " C2 ,Frame component identifier for scan component 2" bitfld.long 0x00 5.--7. " H2 ,Horizontal sampling for scan component 2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2.--4. " V2 ,Vertical sampling for scan component 2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--1. " TQ2 ,Quantization table identifier for scan component 2" "0,1,2,3" group.long 0x1C++0x23 line.long 0x00 "STATUS_7,Status 7 Register" hexmask.long.byte 0x00 8.--15. 1. " C3 ,Frame component identifier for scan component 3" bitfld.long 0x00 5.--7. " H3 ,Horizontal sampling for scan component 3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2.--4. " V3 ,Vertical sampling for scan component 3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--1. " TQ3 ,Quantization table identifier for scan component 3" "0,1,2,3" line.long 0x04 "STATUS_8,Status 8 Register" hexmask.long.byte 0x04 8.--15. 1. " QUALITY ,Programmed QUALITY control register" hexmask.long.byte 0x04 0.--7. 1. " NF ,Number of components per frame" line.long 0x08 "STATUS_9,Status 9 Register" hexmask.long.word 0x08 0.--15. 1. " DRI ,Restart interval" line.long 0x0C "STATUS_10,Status 10 Register" bitfld.long 0x0C 12.--15. " HMAX ,Maximum horizontal sampling factor in frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 8.--11. " VMAX ,Maximum vertical sampling factor in frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " NBMCU ,Number of block per MCU in current scan" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " NS ,Number of components in current scan" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "STATUS_11,Status 11 Register" bitfld.long 0x10 12.--15. " VHS3 ,Number of blocks of 4th component in MCU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 8.--11. " VHS2 ,Number of blocks of 3th component in MCU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 4.--7. " VHS1 ,Number of blocks of 2th component in MCU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 0.--3. " VHS0 ,Number of blocks of 1th component in MCU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "STATUS_12,Status 12 Register" bitfld.long 0x14 11. " SCANACTIVE ,Indicates that core encodes entropy coded scan data" "Not active,Active" bitfld.long 0x14 10. " PIXELIN_RDY ,Pixel input data ready" "Not ready,Ready" bitfld.long 0x14 9. " JPEGIN_RDY ,JPEG stream input data ready" "Not ready,Ready" bitfld.long 0x14 8. " CONFIGERROR ,Configuration error indicator" "No error,Error" newline bitfld.long 0x14 7. " SOF_E ,SOF_E error detector" "No error,Error" bitfld.long 0x14 6. " SOS_E ,SOS_E error detector" "No error,Error" bitfld.long 0x14 5. " DQT_E ,DQT_E error detector" "No error,Error" bitfld.long 0x14 4. " DHT_E ,DHT_E error detector" "No error,Error" newline bitfld.long 0x14 3. " DNL_E ,DNL_E error detector" "No error,Error" bitfld.long 0x14 2. " DRI_E ,DRI_E error detector" "No error,Error" bitfld.long 0x14 1. " APPN_E ,APPN_E error detector" "No error,Error" bitfld.long 0x14 0. " COM_E ,COM_E error detector" "No error,Error" line.long 0x18 "STATUS_13,Status 13 Register" hexmask.long.word 0x18 0.--15. 1. " CFG_MODE ,Programmed CFG MODE control register" line.long 0x1C "STATUS_14,Status 14 Register" hexmask.long.word 0x1C 0.--15. 1. " RC_REGS0 ,JPEG_ENCODER_CTRL_RC_REGS_SEL register reference" line.long 0x20 "STATUS_15,Status 15 Register" hexmask.long.word 0x20 0.--15. 1. " RC_REGS1 ,JPEG_ENCODER_CTRL_RC_REGS_SEL register reference" wgroup.long 0x40++0x03 line.long 0x00 "NOMFRSIZE_LO,Nominal Frame Size Low Register" hexmask.long.word 0x00 0.--15. 1. " NOMFRSIZE_LO ,Nominal frame size low register" rgroup.long 0x40++0x03 line.long 0x00 "STATUS_16,Status 16 Register" hexmask.long.word 0x00 0.--15. 1. " NOMFRSIZE_LO ,Bits[15:0] of programmed nominal frame size in bytes" wgroup.long 0x44++0x03 line.long 0x00 "NOMFRSIZE_HI,Nominal Frame Size High Register" hexmask.long.word 0x00 0.--15. 1. " NOMFRSIZE_HI ,Nominal frame size high register" rgroup.long 0x44++0x03 line.long 0x00 "STATUS_17,Status 17 Register" hexmask.long.word 0x00 0.--15. 1. " NOMFRSIZE_HI ,Bits[31:16] of programmed nominal frame size in bytes" wgroup.long 0x48++0x03 line.long 0x00 "OFBSIZE_LO,Output FIFO Buffer Size Low Register" hexmask.long.word 0x00 0.--15. 1. " OFBSIZE_LO ,Output FIFO buffer size low register" rgroup.long 0x48++0x03 line.long 0x00 "STATUS_18,Status 18 Register" hexmask.long.word 0x00 0.--15. 1. " OFBSIZE_LO ,Bits[15:0] of programmed output FIFO size in bytes" wgroup.long 0x4C++0x03 line.long 0x00 "OFBSIZE_HI,Output FIFO Buffer Size High Register" hexmask.long.word 0x00 0.--15. 1. " OFBSIZE_HI ,Output FIFO buffer size high register" rgroup.long 0x4C++0x03 line.long 0x00 "STATUS_19,Status 19 Register" hexmask.long.word 0x00 0.--15. 1. " OFBSIZE_HI ,Bits[15:0] of programmed output FIFO size in bytes" width 0x0B tree.end tree "JPEGDEC (JPEG Decoder)" base ad:0x585D0000 endian.be width 11. rgroup.long 0x00++0x33 line.long 0x00 "STATUS_0,Status 0 Register" hexmask.long.word 0x00 16.--31. 1. " X ,Image width" line.long 0x04 "STATUS_1,Status 1 Register" hexmask.long.word 0x04 16.--31. 1. " Y ,Image height" line.long 0x08 "STATUS_2,Status 2 Register" hexmask.long.word 0x08 16.--31. 1. " HMCU ,Number of MCUs in current scan in horizontal direction" line.long 0x0C "STATUS_3,Status 3 Register" hexmask.long.word 0x0C 16.--31. 1. " VMCU ,Number of MCUs in current scan in vertical direction" line.long 0x10 "STATUS_4,Status 4 Register" bitfld.long 0x10 30.--31. " TQ0 ,Quantization table identifier for scan component 0" "0,1,2,3" bitfld.long 0x10 27.--29. " V0 ,Vertical sampling for scan component 0" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. " H0 ,Horizontal sampling for scan component 0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 16.--23. 1. " C0 ,Frame component identifier for scan component 0" line.long 0x14 "STATUS_5,Status 5 Register" bitfld.long 0x14 30.--31. " TQ1 ,Quantization table identifier for scan component 1" "0,1,2,3" bitfld.long 0x14 27.--29. " V1 ,Vertical sampling for scan component 1" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. " H1 ,Horizontal sampling for scan component 1" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 16.--23. 1. " C1 ,Frame component identifier for scan component 1" line.long 0x18 "STATUS_6,Status 6 Register" bitfld.long 0x18 30.--31. " TQ2 ,Quantization table identifier for scan component 2" "0,1,2,3" bitfld.long 0x18 27.--29. " V2 ,Vertical sampling for scan component 2" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. " H2 ,Horizontal sampling for scan component 2" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 16.--23. 1. " C2 ,Frame component identifier for scan component 2" line.long 0x1C "STATUS_7,Status 7 Register" bitfld.long 0x1C 30.--31. " TQ3 ,Quantization table identifier for scan component 3" "0,1,2,3" bitfld.long 0x1C 27.--29. " V3 ,Vertical sampling for scan component 3" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 24.--26. " H3 ,Horizontal sampling for scan component 3" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 16.--23. 1. " C3 ,Frame component identifier for scan component 3" line.long 0x20 "STATUS_8,Status 8 Register" hexmask.long.byte 0x20 24.--31. 1. " NF ,Number of components per frame" hexmask.long.byte 0x20 16.--23. 1. " P ,Sample precision" line.long 0x24 "STATUS_9,Status 9 Register" hexmask.long.word 0x24 16.--31. 1. " DRI ,Restart interval" line.long 0x28 "STATUS_10,Status 10 Register" bitfld.long 0x28 28.--31. " NS ,Number of components in current scan" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x28 24.--27. " NBMCU ,Number of block per MCU in current scan" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x28 20.--23. " VMAX ,Maximum vertical sampling factor in frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x28 16.--19. " HMAX ,Maximum horizontal sampling factor in frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x2C "STATUS_11,Status 11 Register" bitfld.long 0x2C 28.--31. " VHS0 ,Number of blocks of 1th component in MCU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x2C 24.--27. " VHS1 ,Number of blocks of 2th component in MCU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x2C 20.--23. " VHS2 ,Number of blocks of 3th component in MCU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x2C 16.--19. " VHS3 ,Number of blocks of 4th component in MCU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x30 "STATUS_12,Status 12 Register" bitfld.long 0x30 31. " COM_E ,COM_E error detector" "No error,Error" bitfld.long 0x30 30. " APPN_E ,APPN_E error detector" "No error,Error" bitfld.long 0x30 29. " DRI_E ,DRI_E error detector" "No error,Error" bitfld.long 0x30 28. " DNL_E ,DNL_E error detector" "No error,Error" newline bitfld.long 0x30 27. " DHT_E ,DHT_E error detector" "No error,Error" bitfld.long 0x30 26. " DQT_E ,DQT_E error detector" "No error,Error" bitfld.long 0x30 25. " SOS_E ,SOS_E error detector" "No error,Error" bitfld.long 0x30 24. " SOF_E ,SOF_E error detector" "No error,Error" group.long 0x34++0x03 line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " LP ,Low power mode enabler" "Disabled,Enabled" bitfld.long 0x00 30. " SWR ,Soft reset" "No reset,Reset" bitfld.long 0x00 29. " GO ,Low power idle mode enabler" "Disabled,Enabled" endian.le width 0x0B tree.end ; tree "JPEGENCWRP (JPEG Encoder Wrapper)" ; base ad:0x00 ; %include imx8x/jpgencwrp.ph ; tree.end ; tree "JPEGDECWRP (JPEG Decoder Wrapper)" ; base ad:0x00 ; %include imx8x/jpgdecwrp.ph ; tree.end tree.end ; tree "Parallel Capture" ; base ad:0x00 ; %include imx8x/pi_ci.ph ; tree.end tree.open "Display Controller 0" tree.open "DPU (Display Processing Unit)" ; tree "Common Control" ; base ad:0x00 ; %include imx8x/comctrl.ph ad:0x00 ; tree.end ; tree "Command Sequencer" ; base ad:0x00+0x400 ; %include imx8x/cmdseq.ph ad:0x00+0x400 ; tree.end ; tree "Pixel Engine Configuration" ; base ad:0x00+0x800 ; %include imx8x/pixeng_cfg.ph ad:0x00+0x800 ; tree.end ; tree "FETCHDECODE9" ; base ad:0x00+0x1000 ; %include imx8x/pixeng_fetchdecode.ph ad:0x00+0x1000 ; tree.end ; tree "FETCHDECODE0" ; base ad:0x00+0x6C00 ; %include imx8x/pixeng_fetchdecode.ph ad:0x00+0x6C00 ; tree.end ; tree "FETCHDECODE1" ; base ad:0x00+0x7800 ; %include imx8x/pixeng_fetchdecode.ph ad:0x00+0x7800 ; tree.end ; tree "FETCHWARP9" ; base ad:0x00+0x1800 ; %include imx8x/pixeng_fetchwarp.ph ad:0x00+0x1800 ; tree.end ; tree "FETCHECO9" ; base ad:0x00+0x1C00 ; %include imx8x/pixeng_fetcheco.ph ad:0x00+0x1C00 ; tree.end ; tree "ROP9" ; base ad:0x00+0x2000 ; %include imx8x/pixeng_rop.ph ad:0x00+0x2000 ; tree.end ; tree "CLUT9" ; base ad:0x00+0x2400 ; %include imx8x/pixeng_clut.ph ad:0x00+0x2400 ; tree.end ; tree "MATRIX9" ; base ad:0x00+0x2C00 ; %include imx8x/pixeng_matrix.ph ad:0x00+0x2C00 ; tree.end ; tree "HSCALER9" ; base ad:0x00+0x3000 ; %include imx8x/pixeng_hscaler.ph ad:0x00+0x3000 ; tree.end ; tree "VSCALER9" ; base ad:0x00+0x3400 ; %include imx8x/pixeng_vscaler.ph ad:0x00+0x3400 ; tree.end ; tree "FILTER9" ; base ad:0x00+0x3800 ; %include imx8x/pixeng_filter.ph ad:0x00+0x3800 ; tree.end ; tree "BLITBLEND9" ; base ad:0x00+0x3C00 ; %include imx8x/pixeng_blitblend.ph ad:0x00+0x3C00 ; tree.end ; tree "STORE9" ; base ad:0x00+0x4000 ; %include imx8x/pixeng_store.ph ad:0x00+0x4000 ; tree.end ; tree "CONSTFRAME0" ; base ad:0x00+0x4400 ; %include imx8x/pixeng_constframe.ph ad:0x00+0x4400 ; tree.end ; tree "EXTDST0" ; base ad:0x00+0x4800 ; %include imx8x/pixeng_extdst.ph ad:0x00+0x4800 ; tree.end ; tree "CONSTFRAME4" ; base ad:0x00+0x4C00 ; %include imx8x/pixeng_constframe.ph ad:0x00+0x4C00 ; tree.end ; tree "EXTDST4" ; base ad:0x00+0x5000 ; %include imx8x/pixeng_extdst.ph ad:0x00+0x5000 ; tree.end ; tree "CONSTFRAME1" ; base ad:0x00+0x5400 ; %include imx8x/pixeng_constframe.ph ad:0x00+0x5400 ; tree.end ; tree "EXTDST1" ; base ad:0x00+0x5800 ; %include imx8x/pixeng_extdst.ph ad:0x00+0x5800 ; tree.end ; tree "CONSTFRAME5" ; base ad:0x00+0x5C00 ; %include imx8x/pixeng_constframe.ph ad:0x00+0x5C00 ; tree.end ; tree "EXTDST5" ; base ad:0x00+0x6000 ; %include imx8x/pixeng_extdst.ph ad:0x00+0x6000 ; tree.end ; tree "FETCHWARP2" ; base ad:0x00+0x6400 ; %include imx8x/pixeng_fetchwarp.ph ad:0x00+0x6400 ; tree.end ; tree "FETCHECO2" ; base ad:0x00+0x6800 ; %include imx8x/pixeng_fetcheco.ph ad:0x00+0x6800 ; tree.end ; tree "FETCHECO0" ; base ad:0x00+0x7400 ; %include imx8x/pixeng_fetcheco.ph ad:0x00+0x7400 ; tree.end ; tree "FETCHECO1" ; base ad:0x00+0x8000 ; %include imx8x/pixeng_fetcheco.ph ad:0x00+0x8000 ; tree.end ; tree "FETCHLAYER0" ; base ad:0x00+0x8400 ; %include imx8x/pixeng_fetchlayer.ph ad:0x00+0x8400 ; tree.end ; tree "MATRIX4" ; base ad:0x00+0x8C00 ; %include imx8x/pixeng_matrix.ph ad:0x00+0x8C00 ; tree.end ; tree "HSCALER4" ; base ad:0x00+0x9000 ; %include imx8x/pixeng_hscaler.ph ad:0x00+0x9000 ; tree.end ; tree "VSCALER4" ; base ad:0x00+0x9400 ; %include imx8x/pixeng_vscaler.ph ad:0x00+0x9400 ; tree.end ; tree "MATRIX5" ; base ad:0x00+0x9800 ; %include imx8x/pixeng_matrix.ph ad:0x00+0x9800 ; tree.end ; tree "HSCALER5" ; base ad:0x00+0x9C00 ; %include imx8x/pixeng_hscaler.ph ad:0x00+0x9C00 ; tree.end ; tree "VSCALER5" ; base ad:0x00+0xA000 ; %include imx8x/pixeng_vscaler.ph ad:0x00+0xA000 ; tree.end ; tree "LAYERBLEND0" ; base ad:0x00+0xA400 ; %include imx8x/pixeng_layerblend.ph ad:0x00+0xA400 ; tree.end ; tree "LAYERBLEND1" ; base ad:0x00+0xA800 ; %include imx8x/pixeng_layerblend.ph ad:0x00+0xA800 ; tree.end ; tree "LAYERBLEND2" ; base ad:0x00+0xAC00 ; %include imx8x/pixeng_layerblend.ph ad:0x00+0xAC00 ; tree.end ; tree "LAYERBLEND3" ; base ad:0x00+0xB000 ; %include imx8x/pixeng_layerblend.ph ad:0x00+0xB000 ; tree.end ; tree "DISENGCFG" ; base ad:0x00+0xB400 ; %include imx8x/diseng_top.ph ad:0x00+0xB400 ; tree.end ; tree "FRAMEGEN0" ; base ad:0x00+0xB800 ; %include imx8x/diseng_framegen.ph ad:0x00+0xB800 ; tree.end ; tree "MATRIX0" ; base ad:0x00+0xBC00 ; %include imx8x/pixeng_matrix.ph ad:0x00+0xBC00 ; tree.end ; tree "GAMMACOR0" ; base ad:0x00+0xC000 ; %include imx8x/pixeng_gammacor.ph ad:0x00+0xC000 ; tree.end ; tree "DITHER0" ; base ad:0x00+0xC400 ; %include imx8x/diseng_dither.ph ad:0x00+0xC400 ; tree.end ; tree "TCON0" ; base ad:0x00+0xC800 ; %include imx8x/tcon.ph ad:0x00+0xC800 ; tree.end ; tree "SIG0" ; base ad:0x00+0xD000 ; %include imx8x/diseng_sig.ph ad:0x00+0xD000 ; tree.end ; tree "FRAMEGEN1" ; base ad:0x00+0xD400 ; %include imx8x/diseng_framegen.ph ad:0x00+0xD400 ; tree.end ; tree "MATRIX1" ; base ad:0x00+0xD800 ; %include imx8x/pixeng_matrix.ph ad:0x00+0xD800 ; tree.end ; tree "GAMMACOR1" ; base ad:0x00+0xDC00 ; %include imx8x/pixeng_gammacor.ph ad:0x00+0xDC00 ; tree.end ; tree "DITHER1" ; base ad:0x00+0xE000 ; %include imx8x/diseng_dither.ph ad:0x00+0xE000 ; tree.end ; tree "TCON1" ; base ad:0x00+0xE400 ; %include imx8x/tcon.ph ad:0x00+0xE400 ; tree.end ; tree "SIG1" ; base ad:0x00+0xEC00 ; %include imx8x/diseng_sig.ph ad:0x00+0xEC00 ; tree.end tree "DPUXPC (AXI Performance Counter)" base ad:0x56180000+0xF000 width 24. group.long 0x00++0x0B line.long 0x00 "CONTROL,Control Register" bitfld.long 0x00 31. " OTCDISABLE ,Disable OTC Counters" "No,Yes" bitfld.long 0x00 30. " INCREMENTMODE ,Enable increment mode for latency measurement" "Disabled,Enabled" bitfld.long 0x00 1.--2. " MODE ,Measurement mode" "Manual measurement end,Timer controlled measurement end,Continuous measurement,?..." bitfld.long 0x00 0. " ENABLE ,Measurement enable" "Disabled,Enabled" line.long 0x04 "TIMER,Timer Register" bitfld.long 0x04 28.--31. " DIVIDER ,Divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x04 0.--27. 1. " LOAD ,Load" line.long 0x08 "MEASUREMENTTIMECONTROL,Measurement Time Control Register" bitfld.long 0x08 31. " MTENABLE ,Measurement time enable" "Disabled,Enabled" hexmask.long.tbyte 0x08 0.--19. 1. " MTDIVIDER ,Measurement time divider" rgroup.long 0x0C++0x0B line.long 0x00 "SW_TAG,SW Tag Register" line.long 0x04 "MEASUREMENTTIME,Measurement Time Register" line.long 0x08 "GLOBAL_COUNTER,Global Counter Register" newline group.long (0x18)++0x03 line.long 0x00 "MU00_SWITCH,MU00 Switch Register" bitfld.long 0x00 0.--3. " MU00_SELECT ,MU00 select" "cmdseq read,cmdseq write,fetchdecode9 read,fetchwarp9 read,fetcheco9 read,fetchwarp2 read,fetcheco2 read,fetchdecode0 read,fetcheco0 read,fetchdecode1 read,fetcheco1 read,fetchlayer0 read,store9 write,?..." rgroup.long (0x18+0x04)++0x13 line.long 0x00 "MU00_DATA_COUNTER,MU00 Data Counter Register" line.long 0x04 "MU00_BUSY_COUNTER,MU00 Busy Counter Register" line.long 0x08 "MU00_TRANSFER_COUNTER,MU00 Transfer Counter Register" line.long 0x0C "MU00_ADDRBUSY_COUNTER,MU00 AddrBusy Counter Register" line.long 0x10 "MU00_LATENCY_COUTNER,MU00 Latency Counter Register" group.long (0x30)++0x03 line.long 0x00 "MU01_SWITCH,MU01 Switch Register" bitfld.long 0x00 0.--3. " MU01_SELECT ,MU01 select" "cmdseq read,cmdseq write,fetchdecode9 read,fetchwarp9 read,fetcheco9 read,fetchwarp2 read,fetcheco2 read,fetchdecode0 read,fetcheco0 read,fetchdecode1 read,fetcheco1 read,fetchlayer0 read,store9 write,?..." rgroup.long (0x30+0x04)++0x13 line.long 0x00 "MU01_DATA_COUNTER,MU01 Data Counter Register" line.long 0x04 "MU01_BUSY_COUNTER,MU01 Busy Counter Register" line.long 0x08 "MU01_TRANSFER_COUNTER,MU01 Transfer Counter Register" line.long 0x0C "MU01_ADDRBUSY_COUNTER,MU01 AddrBusy Counter Register" line.long 0x10 "MU01_LATENCY_COUTNER,MU01 Latency Counter Register" group.long (0x48)++0x03 line.long 0x00 "MU02_SWITCH,MU02 Switch Register" bitfld.long 0x00 0.--3. " MU02_SELECT ,MU02 select" "cmdseq read,cmdseq write,fetchdecode9 read,fetchwarp9 read,fetcheco9 read,fetchwarp2 read,fetcheco2 read,fetchdecode0 read,fetcheco0 read,fetchdecode1 read,fetcheco1 read,fetchlayer0 read,store9 write,?..." rgroup.long (0x48+0x04)++0x13 line.long 0x00 "MU02_DATA_COUNTER,MU02 Data Counter Register" line.long 0x04 "MU02_BUSY_COUNTER,MU02 Busy Counter Register" line.long 0x08 "MU02_TRANSFER_COUNTER,MU02 Transfer Counter Register" line.long 0x0C "MU02_ADDRBUSY_COUNTER,MU02 AddrBusy Counter Register" line.long 0x10 "MU02_LATENCY_COUTNER,MU02 Latency Counter Register" group.long (0x60)++0x03 line.long 0x00 "MU03_SWITCH,MU03 Switch Register" bitfld.long 0x00 0.--3. " MU03_SELECT ,MU03 select" "cmdseq read,cmdseq write,fetchdecode9 read,fetchwarp9 read,fetcheco9 read,fetchwarp2 read,fetcheco2 read,fetchdecode0 read,fetcheco0 read,fetchdecode1 read,fetcheco1 read,fetchlayer0 read,store9 write,?..." rgroup.long (0x60+0x04)++0x13 line.long 0x00 "MU03_DATA_COUNTER,MU03 Data Counter Register" line.long 0x04 "MU03_BUSY_COUNTER,MU03 Busy Counter Register" line.long 0x08 "MU03_TRANSFER_COUNTER,MU03 Transfer Counter Register" line.long 0x0C "MU03_ADDRBUSY_COUNTER,MU03 AddrBusy Counter Register" line.long 0x10 "MU03_LATENCY_COUTNER,MU03 Latency Counter Register" group.long (0x78)++0x03 line.long 0x00 "MU04_SWITCH,MU04 Switch Register" bitfld.long 0x00 0.--3. " MU04_SELECT ,MU04 select" "cmdseq read,cmdseq write,fetchdecode9 read,fetchwarp9 read,fetcheco9 read,fetchwarp2 read,fetcheco2 read,fetchdecode0 read,fetcheco0 read,fetchdecode1 read,fetcheco1 read,fetchlayer0 read,store9 write,?..." rgroup.long (0x78+0x04)++0x13 line.long 0x00 "MU04_DATA_COUNTER,MU04 Data Counter Register" line.long 0x04 "MU04_BUSY_COUNTER,MU04 Busy Counter Register" line.long 0x08 "MU04_TRANSFER_COUNTER,MU04 Transfer Counter Register" line.long 0x0C "MU04_ADDRBUSY_COUNTER,MU04 AddrBusy Counter Register" line.long 0x10 "MU04_LATENCY_COUTNER,MU04 Latency Counter Register" width 0x0B tree.end tree.end tree.open "Local Interrupt Steer" tree "Channel 0" base ad:0x56000000 width 10. group.long 0x00++0x03 line.long 0x00 "CHAN0CTL,Channel 0 Control Register" bitfld.long 0x00 4. " CH4 ,Channel 4 control" "Disabled,Enabled" bitfld.long 0x00 3. " CH3 ,Channel 3 control" "Disabled,Enabled" bitfld.long 0x00 2. " CH2 ,Channel 2 control" "Disabled,Enabled" bitfld.long 0x00 1. " CH1 ,Channel 1 control" "Disabled,Enabled" newline bitfld.long 0x00 0. " CH0 ,Channel 0 control" "Disabled,Enabled" group.long 0x08++0x3B line.long 0x00 "MASK1,Interrupt Mask 1 Register" bitfld.long 0x00 22. " MASKFLD[22] ,Mask for VPU_INT_6" "Masked,Unmasked" bitfld.long 0x00 21. " [21] ,Mask for VPU_INT_5" "Masked,Unmasked" bitfld.long 0x00 20. " [20] ,Mask for VPU_INT_4" "Masked,Unmasked" bitfld.long 0x00 19. " [19] ,Mask for VPU_INT_3" "Masked,Unmasked" newline bitfld.long 0x00 18. " [18] ,Mask for VPU_INT_2" "Masked,Unmasked" bitfld.long 0x00 17. " [17] ,Mask for VPU_INT_1" "Masked,Unmasked" bitfld.long 0x00 16. " [16] ,Mask for VPU_INT_0" "Masked,Unmasked" bitfld.long 0x00 11. " [11] ,Mask for SPDIF0_TX_DMA_INT" "Masked,Unmasked" newline bitfld.long 0x00 10. " [10] ,Mask for SPDIF0_TX_MOD_INT" "Masked,Unmasked" bitfld.long 0x00 9. " [9] ,Mask for SPDIF0_RX_DMA_INT" "Masked,Unmasked" bitfld.long 0x00 8. " [8] ,Mask for SPDIF0_RX_MOD_INT" "Masked,Unmasked" bitfld.long 0x00 7. " [7] ,Mask for CAAM_RTIC_INT" "Masked,Unmasked" newline bitfld.long 0x00 6. " [6] ,Mask for CAAM_INT3" "Masked,Unmasked" bitfld.long 0x00 5. " [5] ,Mask for CAAM_INT2" "Masked,Unmasked" bitfld.long 0x00 4. " [4] ,Mask for CAAM_INT1" "Masked,Unmasked" bitfld.long 0x00 3. " [3] ,Mask for CAAM_INT0" "Masked,Unmasked" newline bitfld.long 0x00 2. " [2] ,Mask for SEC_MU3_A_INT" "Masked,Unmasked" bitfld.long 0x00 1. " [1] ,Mask for SEC_MU2_A_INT" "Masked,Unmasked" bitfld.long 0x00 0. " [0] ,Mask for SEC_MU1_A_INT" "Masked,Unmasked" line.long 0x04 "MASK2,Interrupt Mask 2 Register" bitfld.long 0x04 25. " MASKFLD[25] ,Mask for UART3_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 24. " [24] ,Mask for UART3_DMA_RX_INT" "Masked,Unmasked" bitfld.long 0x04 23. " [23] ,Mask for UART2_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 22. " [22] ,Mask for UART2_DMA_RX_INT" "Masked,Unmasked" newline bitfld.long 0x04 21. " [21] ,Mask for UART1_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 20. " [20] ,Mask for UART1_DMA_RX_INT" "Masked,Unmasked" bitfld.long 0x04 19. " [19] ,Mask for UART0_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 18. " [18] ,Mask for UART0_DMA_RX_INT" "Masked,Unmasked" newline bitfld.long 0x04 15. " [15] ,Mask for I2C3_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 14. " [14] ,Mask for I2C3_DMA_RX_INT" "Masked,Unmasked" bitfld.long 0x04 13. " [13] ,Mask for I2C2_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 12. " [12] ,Mask for I2C2_DMA_RX_INT" "Masked,Unmasked" newline bitfld.long 0x04 11. " [11] ,Mask for I2C1_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 10. " [10] ,Mask for I2C1_DMA_RX_INT" "Masked,Unmasked" bitfld.long 0x04 9. " [9] ,Mask for I2C0_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 8. " [8] ,Mask for I2C0_DMA_RX_INT" "Masked,Unmasked" newline bitfld.long 0x04 7. " [7] ,Mask for SPI3_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 6. " [6] ,Mask for SPI3_DMA_RX_INT" "Masked,Unmasked" bitfld.long 0x04 5. " [5] ,Mask for SPI2_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 4. " [4] ,Mask for SPI2_DMA_RX_INT" "Masked,Unmasked" newline bitfld.long 0x04 3. " [3] ,Mask for SPI1_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 2. " [2] ,Mask for SPI1_DMA_RX_INT" "Masked,Unmasked" bitfld.long 0x04 1. " [1] ,Mask for SPI0_DMA_TX_INT" "Masked,Unmasked" bitfld.long 0x04 0. " [0] ,Mask for SPI0_DMA_RX_INT" "Masked,Unmasked" line.long 0x08 "MASK3,Interrupt Mask 3 Register" bitfld.long 0x08 26. " MASKFLD[26] ,Mask for ESAI0_DMA_INT" "Masked,Unmasked" bitfld.long 0x08 25. " [25] ,Mask for ESAI0_MOD_INT" "Masked,Unmasked" bitfld.long 0x08 22. " [22] ,Mask for SPDIF0_TX_INT" "Masked,Unmasked" bitfld.long 0x08 21. " [21] ,Mask for SPDIF0_RX_INT" "Masked,Unmasked" newline bitfld.long 0x08 20. " [20] ,Mask for SAI5_INT" "Masked,Unmasked" bitfld.long 0x08 19. " [19] ,Mask for SAI4_INT" "Masked,Unmasked" bitfld.long 0x08 16. " [16] ,Mask for SAI3_INT" "Masked,Unmasked" bitfld.long 0x08 15. " [15] ,Mask for SAI2_INT" "Masked,Unmasked" newline bitfld.long 0x08 14. " [14] ,Mask for SAI1_INT" "Masked,Unmasked" bitfld.long 0x08 13. " [13] ,Mask for SAI0_INT" "Masked,Unmasked" bitfld.long 0x08 12. " [12] ,Mask for GPT5_INT" "Masked,Unmasked" bitfld.long 0x08 11. " [11] ,Mask for GPT4_INT" "Masked,Unmasked" newline bitfld.long 0x08 10. " [10] ,Mask for GPT3_INT" "Masked,Unmasked" bitfld.long 0x08 9. " [9] ,Mask for GPT2_INT" "Masked,Unmasked" bitfld.long 0x08 8. " [8] ,Mask for GPT1_INT" "Masked,Unmasked" bitfld.long 0x08 7. " [7] ,Mask for GPT0_INT" "Masked,Unmasked" newline bitfld.long 0x08 4. " [4] ,Mask for ESAI0_INT" "Masked,Unmasked" bitfld.long 0x08 3. " [3] ,Mask for DMA1_CH5_INT" "Masked,Unmasked" bitfld.long 0x08 2. " [2] ,Mask for DMA1_CH4_INT" "Masked,Unmasked" bitfld.long 0x08 1. " [1] ,Mask for DMA1_CH3_INT" "Masked,Unmasked" newline bitfld.long 0x08 0. " [0] ,Mask for DMA1_CH2_INT" "Masked,Unmasked" line.long 0x0C "MASK4,Interrupt Mask 4 Register" bitfld.long 0x0C 31. " MASKFLD[31] ,Mask for DMA1_CH1_INT" "Masked,Unmasked" bitfld.long 0x0C 30. " [30] ,Mask for DMA1_CH0_INT" "Masked,Unmasked" bitfld.long 0x0C 29. " [29] ,Mask for ASRC1_INT2" "Masked,Unmasked" bitfld.long 0x0C 28. " [28] ,Mask for ASRC1_INT1" "Masked,Unmasked" newline bitfld.long 0x0C 27. " [27] ,Mask for DMA0_CH5_INT" "Masked,Unmasked" bitfld.long 0x0C 26. " [26] ,Mask for DMA0_CH4_INT" "Masked,Unmasked" bitfld.long 0x0C 25. " [25] ,Mask for DMA0_CH3_INT" "Masked,Unmasked" bitfld.long 0x0C 24. " [24] ,Mask for DMA0_CH2_INT" "Masked,Unmasked" newline bitfld.long 0x0C 23. " [23] ,Mask for DMA0_CH1_INT" "Masked,Unmasked" bitfld.long 0x0C 22. " [22] ,Mask for DMA0_CH0_INT" "Masked,Unmasked" bitfld.long 0x0C 21. " [21] ,Mask for ASRC0_INT2" "Masked,Unmasked" bitfld.long 0x0C 20. " [20] ,Mask for ASRC0_INT1" "Masked,Unmasked" newline bitfld.long 0x0C 19. " [19] ,Mask for DMA1_ERR_INT" "Masked,Unmasked" bitfld.long 0x0C 18. " [18] ,Mask for DMA1_INT" "Masked,Unmasked" bitfld.long 0x0C 17. " [17] ,Mask for DMA0_ERR_INT" "Masked,Unmasked" bitfld.long 0x0C 16. " [16] ,Mask for DMA0_INT" "Masked,Unmasked" newline bitfld.long 0x0C 12. " [12] ,Mask for ADC_DMA_INT" "Masked,Unmasked" bitfld.long 0x0C 11. " [11] ,Mask for FTM1_DMA_INT" "Masked,Unmasked" bitfld.long 0x0C 10. " [10] ,Mask for FTM_DMA_INT" "Masked,Unmasked" bitfld.long 0x0C 9. " [9] ,Mask for FLEXCAN2_DMA_INT" "Masked,Unmasked" newline bitfld.long 0x0C 8. " [8] ,Mask for FLEXCAN1_DMA_INT" "Masked,Unmasked" bitfld.long 0x0C 7. " [7] ,Mask for FLEXCAN0_DMA_INT" "Masked,Unmasked" bitfld.long 0x0C 5. " [5] ,Mask for ADC_MOD_INT" "Masked,Unmasked" bitfld.long 0x0C 4. " [4] ,Mask for FTM1_MOD_INT" "Masked,Unmasked" newline bitfld.long 0x0C 3. " [3] ,Mask for FTM_MOD_INT" "Masked,Unmasked" bitfld.long 0x0C 2. " [2] ,Mask for FLEXCAN2_MOD_INT" "Masked,Unmasked" bitfld.long 0x0C 1. " [1] ,Mask for FLEXCAN1_MOD_INT" "Masked,Unmasked" bitfld.long 0x0C 0. " [0] ,Mask for FLEXCAN0_MOD_INT" "Masked,Unmasked" line.long 0x10 "MASK5,Interrupt Mask 5 Register" bitfld.long 0x10 28. " MASKFLD[28] ,Mask for UART3_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 27. " [27] ,Mask for UART2_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 26. " [26] ,Mask for UART1_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 25. " [25] ,Mask for UART0_MOD_INT" "Masked,Unmasked" newline bitfld.long 0x10 23. " [23] ,Mask for I2C3_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 22. " [22] ,Mask for I2C2_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 21. " [21] ,Mask for I2C1_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 20. " [20] ,Mask for I2C0_MOD_INT" "Masked,Unmasked" newline bitfld.long 0x10 19. " [19] ,Mask for SPI3_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 18. " [18] ,Mask for SPI2_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 17. " [17] ,Mask for SPI1_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 16. " [16] ,Mask for SPI0_MOD_INT" "Masked,Unmasked" newline bitfld.long 0x10 12. " [12] ,Mask for SAI5_DMA_INT" "Masked,Unmasked" bitfld.long 0x10 11. " [11] ,Mask for SAI5_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 10. " [10] ,Mask for SAI4_DMA_INT" "Masked,Unmasked" bitfld.long 0x10 9. " [9] ,Mask for SAI4_MOD_INT" "Masked,Unmasked" newline bitfld.long 0x10 4. " [4] ,Mask for SAI3_DMA_INT" "Masked,Unmasked" bitfld.long 0x10 3. " [3] ,Mask for SAI3_MOD_INT" "Masked,Unmasked" bitfld.long 0x10 0. " [0] ,Mask for INT_OUT" "Masked,Unmasked" line.long 0x14 "MASK6,Interrupt Mask 6 Register" bitfld.long 0x14 31. " MASKFLD[31] ,Mask for SAI2_DMA_INT" "Masked,Unmasked" bitfld.long 0x14 30. " [30] ,Mask for SAI2_MOD_INT" "Masked,Unmasked" bitfld.long 0x14 29. " [29] ,Mask for SAI1_DMA_INT" "Masked,Unmasked" bitfld.long 0x14 28. " [28] ,Mask for SAI1_MOD_INT" "Masked,Unmasked" newline bitfld.long 0x14 27. " [27] ,Mask for SAI0_DMA_INT" "Masked,Unmasked" bitfld.long 0x14 26. " [26] ,Mask for SAI0_MOD_INT" "Masked,Unmasked" bitfld.long 0x14 24. " [24] ,Mask for MJPEG_DEC3_INT" "Masked,Unmasked" bitfld.long 0x14 23. " [23] ,Mask for MJPEG_DEC2_INT" "Masked,Unmasked" newline bitfld.long 0x14 22. " [22] ,Mask for MJPEG_DEC1_INT" "Masked,Unmasked" bitfld.long 0x14 21. " [21] ,Mask for MJPEG_DEC0_INT" "Masked,Unmasked" bitfld.long 0x14 20. " [20] ,Mask for MJPEG_ENC3_INT" "Masked,Unmasked" bitfld.long 0x14 19. " [19] ,Mask for MJPEG_ENC2_INT" "Masked,Unmasked" newline bitfld.long 0x14 18. " [18] ,Mask for MJPEG_ENC1_INT" "Masked,Unmasked" bitfld.long 0x14 17. " [17] ,Mask for MJPEG_ENC0_INT" "Masked,Unmasked" bitfld.long 0x14 16. " [16] ,Mask for PDMA_STREAM7_INT" "Masked,Unmasked" bitfld.long 0x14 15. " [15] ,Mask for PDMA_STREAM6_INT" "Masked,Unmasked" newline bitfld.long 0x14 14. " [14] ,Mask for PDMA_STREAM5_INT" "Masked,Unmasked" bitfld.long 0x14 13. " [13] ,Mask for PDMA_STREAM4_INT" "Masked,Unmasked" bitfld.long 0x14 12. " [12] ,Mask for PDMA_STREAM3_INT" "Masked,Unmasked" bitfld.long 0x14 11. " [11] ,Mask for PDMA_STREAM2_INT" "Masked,Unmasked" newline bitfld.long 0x14 10. " [10] ,Mask for PDMA_STREAM1_INT" "Masked,Unmasked" bitfld.long 0x14 9. " [9] ,Mask for PDMA_STREAM0_INT" "Masked,Unmasked" bitfld.long 0x14 0. " [0] ,Mask for MSI_INT" "Masked,Unmasked" line.long 0x18 "MASK7,Interrupt Mask 7 Register" bitfld.long 0x18 20. " MASKFLD[20] ,Mask for DMA_ERR_INT" "Masked,Unmasked" bitfld.long 0x18 19. " [19] ,Mask for DMA_INT" "Masked,Unmasked" bitfld.long 0x18 18. " [18] ,Mask for APBHDMA" "Masked,Unmasked" bitfld.long 0x18 17. " [17] ,Mask for NAND_GPMI_INT" "Masked,Unmasked" newline bitfld.long 0x18 16. " [16] ,Mask for NAND_BCH_INT" "Masked,Unmasked" bitfld.long 0x18 15. " [15] ,Mask for USB3_INT" "Masked,Unmasked" bitfld.long 0x18 14. " [14] ,Mask for WAKEUP_INT" "Masked,Unmasked" bitfld.long 0x18 13. " [13] ,Mask for UTMI_INT" "Masked,Unmasked" newline bitfld.long 0x18 12. " [12] ,Mask for USB_HOST_INT" "Masked,Unmasked" bitfld.long 0x18 11. " [11] ,Mask for USB_OTG_INT" "Masked,Unmasked" bitfld.long 0x18 10. " [10] ,Mask for MLB_AHB_INT" "Masked,Unmasked" bitfld.long 0x18 9. " [9] ,Mask for MLB_INT" "Masked,Unmasked" newline bitfld.long 0x18 7. " [7] ,Mask for ENET1_TIMER_INT" "Masked,Unmasked" bitfld.long 0x18 6. " [6] ,Mask for ENET1_FRAME0_EVENT_INT" "Masked,Unmasked" bitfld.long 0x18 5. " [5] ,Mask for ENET1_FRAME2_INT" "Masked,Unmasked" bitfld.long 0x18 4. " [4] ,Mask for ENET1_FRAME1_INT" "Masked,Unmasked" newline bitfld.long 0x18 3. " [3] ,Mask for ENET0_TIMER_INT" "Masked,Unmasked" bitfld.long 0x18 2. " [2] ,Mask for ENET0_FRAME0_EVENT_INT" "Masked,Unmasked" bitfld.long 0x18 1. " [1] ,Mask for ENET0_FRAME2_INT" "Masked,Unmasked" bitfld.long 0x18 0. " [0] ,Mask for ENET0_FRAME1_INT" "Masked,Unmasked" line.long 0x1C "MASK8,Interrupt Mask 8 Register" bitfld.long 0x1C 23. " MASKFLD[23] ,Mask for EXTERNAL_DMA_INT_5" "Masked,Unmasked" bitfld.long 0x1C 22. " [22] ,Mask for EXTERNAL_DMA_INT_4" "Masked,Unmasked" bitfld.long 0x1C 21. " [21] ,Mask for EXTERNAL_DMA_INT_3" "Masked,Unmasked" bitfld.long 0x1C 20. " [20] ,Mask for EXTERNAL_DMA_INT_2" "Masked,Unmasked" newline bitfld.long 0x1C 19. " [19] ,Mask for EXTERNAL_DMA_INT_1" "Masked,Unmasked" bitfld.long 0x1C 18. " [18] ,Mask for EXTERNAL_DMA_INT_0" "Masked,Unmasked" bitfld.long 0x1C 16. " [16] ,Mask for ADC_INT" "Masked,Unmasked" bitfld.long 0x1C 15. " [15] ,Mask for FTM1_INT" "Masked,Unmasked" newline bitfld.long 0x1C 14. " [14] ,Mask for FTM_INT" "Masked,Unmasked" bitfld.long 0x1C 13. " [13] ,Mask for FLEXCAN2_INT" "Masked,Unmasked" bitfld.long 0x1C 12. " [12] ,Mask for FLEXCAN1_INT" "Masked,Unmasked" bitfld.long 0x1C 11. " [11] ,Mask for FLEXCAN0_INT" "Masked,Unmasked" newline bitfld.long 0x1C 10. " [10] ,Mask for USDHC2_INT" "Masked,Unmasked" bitfld.long 0x1C 9. " [9] ,Mask for USDHC1_INT" "Masked,Unmasked" bitfld.long 0x1C 8. " [8] ,Mask for EMMC0_INT/USDHC0_INT" "Masked,Unmasked" bitfld.long 0x1C 4. " [4] ,Mask for UART3_INT" "Masked,Unmasked" newline bitfld.long 0x1C 3. " [3] ,Mask for UART2_INT" "Masked,Unmasked" bitfld.long 0x1C 2. " [2] ,Mask for UART1_INT" "Masked,Unmasked" bitfld.long 0x1C 1. " [1] ,Mask for UART0_INT" "Masked,Unmasked" line.long 0x20 "MASK9,Interrupt Mask 9 Register" bitfld.long 0x20 31. " MASKFLD[31] ,Mask for I2C3_INT" "Masked,Unmasked" bitfld.long 0x20 30. " [30] ,Mask for I2C2_INT" "Masked,Unmasked" bitfld.long 0x20 29. " [29] ,Mask for I2C1_INT" "Masked,Unmasked" bitfld.long 0x20 28. " [28] ,Mask for I2C0_INT" "Masked,Unmasked" newline bitfld.long 0x20 27. " [27] ,Mask for SPI3_INT" "Masked,Unmasked" bitfld.long 0x20 26. " [26] ,Mask for SPI2_INT" "Masked,Unmasked" bitfld.long 0x20 25. " [25] ,Mask for SPI1_INT" "Masked,Unmasked" bitfld.long 0x20 24. " [24] ,Mask for SPI0_INT" "Masked,Unmasked" newline bitfld.long 0x20 16. " [16] ,Mask for MU13_INT_B" "Masked,Unmasked" bitfld.long 0x20 15. " [15] ,Mask for MU12_INT_B" "Masked,Unmasked" bitfld.long 0x20 14. " [14] ,Mask for MU11_INT_B" "Masked,Unmasked" bitfld.long 0x20 13. " [13] ,Mask for MU10_INT_B" "Masked,Unmasked" newline bitfld.long 0x20 12. " [12] ,Mask for MU9_INT_B" "Masked,Unmasked" bitfld.long 0x20 11. " [11] ,Mask for MU8_INT_B" "Masked,Unmasked" bitfld.long 0x20 10. " [10] ,Mask for MU7_INT_B" "Masked,Unmasked" bitfld.long 0x20 9. " [9] ,Mask for MU6_INT_B" "Masked,Unmasked" newline bitfld.long 0x20 8. " [8] ,Mask for MU5_INT_B" "Masked,Unmasked" bitfld.long 0x20 0. " [0] ,Mask for MU13_INT_A" "Masked,Unmasked" line.long 0x24 "MASK10,Interrupt Mask 10 Register" bitfld.long 0x24 31. " MASKFLD[31] ,Mask for MU12_INT_A" "Masked,Unmasked" bitfld.long 0x24 30. " [30] ,Mask for MU11_INT_A" "Masked,Unmasked" bitfld.long 0x24 29. " [29] ,Mask for MU10_INT_A" "Masked,Unmasked" bitfld.long 0x24 28. " [28] ,Mask for MU9_INT_A" "Masked,Unmasked" newline bitfld.long 0x24 27. " [27] ,Mask for MU8_INT_A" "Masked,Unmasked" bitfld.long 0x24 26. " [26] ,Mask for MU7_INT_A" "Masked,Unmasked" bitfld.long 0x24 25. " [25] ,Mask for MU6_INT_A" "Masked,Unmasked" bitfld.long 0x24 24. " [24] ,Mask for MU5_INT_A" "Masked,Unmasked" newline bitfld.long 0x24 20. " [20] ,Mask for MU4_INT" "Masked,Unmasked" bitfld.long 0x24 19. " [19] ,Mask for MU3_INT" "Masked,Unmasked" bitfld.long 0x24 18. " [18] ,Mask for MU2_INT" "Masked,Unmasked" bitfld.long 0x24 17. " [17] ,Mask for MU1_INT" "Masked,Unmasked" newline bitfld.long 0x24 16. " [16] ,Mask for MU0_INT" "Masked,Unmasked" line.long 0x28 "MASK11,Interrupt Mask 11 Register" bitfld.long 0x28 15. " MASKFLD[15] ,Mask for GPIO_INT[7]" "Masked,Unmasked" bitfld.long 0x28 14. " [14] ,Mask for GPIO_INT[6]" "Masked,Unmasked" bitfld.long 0x28 13. " [13] ,Mask for GPIO_INT[5]" "Masked,Unmasked" bitfld.long 0x28 12. " [12] ,Mask for GPIO_INT[4]" "Masked,Unmasked" newline bitfld.long 0x28 11. " [11] ,Mask for GPIO_INT[3]" "Masked,Unmasked" bitfld.long 0x28 10. " [10] ,Mask for GPIO_INT[2]" "Masked,Unmasked" bitfld.long 0x28 9. " [9] ,Mask for GPIO_INT[1]" "Masked,Unmasked" bitfld.long 0x28 8. " [8] ,Mask for GPIO_INT[0]" "Masked,Unmasked" newline bitfld.long 0x28 3. " [3] ,Mask for PERF_CNT_INT" "Masked,Unmasked" bitfld.long 0x28 2. " [2] ,Mask for SBR_DONE_INT" "Masked,Unmasked" bitfld.long 0x28 1. " [1] ,Mask for ECC_NCORRECT_INT" "Masked,Unmasked" bitfld.long 0x28 0. " [0] ,Mask for ECC_CORRECT_INT" "Masked,Unmasked" line.long 0x2C "MASK12,Interrupt Mask 12 Register" bitfld.long 0x2C 27. " MASKFLD[27] ,Mask for SYS_COUNT_INT[3]" "Masked,Unmasked" bitfld.long 0x2C 26. " [26] ,Mask for SYS_COUNT_INT[2]" "Masked,Unmasked" bitfld.long 0x2C 25. " [25] ,Mask for SYS_COUNT_INT[1]" "Masked,Unmasked" bitfld.long 0x2C 24. " [24] ,Mask for SYS_COUNT_INT[0]" "Masked,Unmasked" newline bitfld.long 0x2C 23. " [23] ,Mask for INT_OUT[7]" "Masked,Unmasked" bitfld.long 0x2C 22. " [22] ,Mask for INT_OUT[6]" "Masked,Unmasked" bitfld.long 0x2C 21. " [21] ,Mask for INT_OUT[5]" "Masked,Unmasked" bitfld.long 0x2C 20. " [20] ,Mask for INT_OUT[4]" "Masked,Unmasked" newline bitfld.long 0x2C 19. " [19] ,Mask for INT_OUT[3]" "Masked,Unmasked" bitfld.long 0x2C 18. " [18] ,Mask for INT_OUT[2]" "Masked,Unmasked" bitfld.long 0x2C 17. " [17] ,Mask for INT_OUT[1]" "Masked,Unmasked" bitfld.long 0x2C 16. " [16] ,Mask for INT_OUT[0]" "Masked,Unmasked" newline bitfld.long 0x2C 15. " [15] ,Mask for PCIE9_GPIO_WAKEUP[1]" "Masked,Unmasked" bitfld.long 0x2C 14. " [14] ,Mask for PCIE9_GPIO_WAKEUP[0]" "Masked,Unmasked" bitfld.long 0x2C 13. " [13] ,Mask for PCIE0_SMLH_REQ_RST" "Masked,Unmasked" bitfld.long 0x2C 12. " [12] ,Mask for PCIE0_INT_A" "Masked,Unmasked" newline bitfld.long 0x2C 11. " [11] ,Mask for PCIE0_INT_B" "Masked,Unmasked" bitfld.long 0x2C 10. " [10] ,Mask for PCIE0_INT_C" "Masked,Unmasked" bitfld.long 0x2C 9. " [9] ,Mask for PCIE0_INT_D" "Masked,Unmasked" bitfld.long 0x2C 8. " [8] ,Mask for PCIE0_DMA_INT" "Masked,Unmasked" newline bitfld.long 0x2C 7. " [7] ,Mask for PCIE0_CLK_REQ_INT" "Masked,Unmasked" bitfld.long 0x2C 6. " [6] ,Mask for PCIE0_MSI_CTRL_INT" "Masked,Unmasked" bitfld.long 0x2C 5. " [5] ,Mask for PWM7_INT" "Masked,Unmasked" bitfld.long 0x2C 4. " [4] ,Mask for PWM6_INT" "Masked,Unmasked" newline bitfld.long 0x2C 3. " [3] ,Mask for PWM5_INT" "Masked,Unmasked" bitfld.long 0x2C 2. " [2] ,Mask for PWM4_INT" "Masked,Unmasked" bitfld.long 0x2C 1. " [1] ,Mask for PWM3_INT" "Masked,Unmasked" bitfld.long 0x2C 0. " [0] ,Mask for PWM2_INT" "Masked,Unmasked" line.long 0x30 "MASK13,Interrupt Mask 13 Register" bitfld.long 0x30 31. " MASKFLD[31] ,Mask for PWM1_INT" "Masked,Unmasked" bitfld.long 0x30 30. " [30] ,Mask for PWM0_INT" "Masked,Unmasked" bitfld.long 0x30 29. " [29] ,Mask for FLEXSPI1_INT" "Masked,Unmasked" bitfld.long 0x30 28. " [28] ,Mask for FLEXSPI0_INT" "Masked,Unmasked" newline bitfld.long 0x30 21. " [21] ,Mask for KPP0_INT" "Masked,Unmasked" bitfld.long 0x30 20. " [20] ,Mask for GPT4_INT" "Masked,Unmasked" bitfld.long 0x30 19. " [19] ,Mask for GPT3_INT" "Masked,Unmasked" bitfld.long 0x30 18. " [18] ,Mask for GPT2_INT" "Masked,Unmasked" newline bitfld.long 0x30 17. " [17] ,Mask for GPT1_INT" "Masked,Unmasked" bitfld.long 0x30 16. " [16] ,Mask for GPT0_INT" "Masked,Unmasked" bitfld.long 0x30 5. " [5] ,Mask for DMA3_ERR_INT" "Masked,Unmasked" bitfld.long 0x30 4. " [4] ,Mask for DMA3_INT" "Masked,Unmasked" newline bitfld.long 0x30 3. " [3] ,Mask for DMA2_ERR_INT" "Masked,Unmasked" bitfld.long 0x30 2. " [2] ,Mask for DMA2_INT" "Masked,Unmasked" bitfld.long 0x30 0. " [0] ,Mask for XAQ2_INTR" "Masked,Unmasked" line.long 0x34 "MASK14,Interrupt Mask 14 Register" bitfld.long 0x34 31. " MASKFLD[31] ,Mask for LCD_PWM_INT" "Masked,Unmasked" bitfld.long 0x34 30. " [30] ,Mask for LCD_MOD_INT" "Masked,Unmasked" bitfld.long 0x34 28. " [28] ,Mask for INT_OUT" "Masked,Unmasked" bitfld.long 0x34 27. " [27] ,Mask for INT_OUT" "Masked,Unmasked" newline bitfld.long 0x34 20. " [20] ,Mask for INT_OUT[12]" "Masked,Unmasked" bitfld.long 0x34 19. " [19] ,Mask for INT_OUT[11]" "Masked,Unmasked" bitfld.long 0x34 18. " [18] ,Mask for INT_OUT[10]" "Masked,Unmasked" bitfld.long 0x34 17. " [17] ,Mask for INT_OUT[9]" "Masked,Unmasked" newline bitfld.long 0x34 15. " [15] ,Mask for INT_OUT[7]" "Masked,Unmasked" bitfld.long 0x34 14. " [14] ,Mask for INT_OUT[6]" "Masked,Unmasked" bitfld.long 0x34 13. " [13] ,Mask for INT_OUT[5]" "Masked,Unmasked" bitfld.long 0x34 12. " [12] ,Mask for INT_OUT[4]" "Masked,Unmasked" newline bitfld.long 0x34 11. " [11] ,Mask for INT_OUT[3]" "Masked,Unmasked" bitfld.long 0x34 10. " [10] ,Mask for INT_OUT[2]" "Masked,Unmasked" bitfld.long 0x34 9. " [9] ,Mask for INT_OUT[1]" "Masked,Unmasked" bitfld.long 0x34 8. " [8] ,Mask for INT_OUT[0]" "Masked,Unmasked" line.long 0x38 "MASK15,Interrupt Mask 15 Register" bitfld.long 0x38 23. " MASKFLD[23] ,Mask for INT_OUT[7]" "Masked,Unmasked" bitfld.long 0x38 22. " [22] ,Mask for INT_OUT[6]" "Masked,Unmasked" bitfld.long 0x38 21. " [21] ,Mask for INT_OUT[5]" "Masked,Unmasked" bitfld.long 0x38 20. " [20] ,Mask for INT_OUT[4]" "Masked,Unmasked" newline bitfld.long 0x38 19. " [19] ,Mask for INT_OUT[3]" "Masked,Unmasked" bitfld.long 0x38 18. " [18] ,Mask for INT_OUT[2]" "Masked,Unmasked" bitfld.long 0x38 17. " [17] ,Mask for INT_OUT[1]" "Masked,Unmasked" bitfld.long 0x38 16. " [16] ,Mask for INT_OUT[0]" "Masked,Unmasked" newline bitfld.long 0x38 1. " [1] ,Mask for nEXTERRIRQ" "Masked,Unmasked" bitfld.long 0x38 0. " [0] ,Mask for nINTERRIRQ" "Masked,Unmasked" group.long 0x48++0x3B line.long 0x00 "SET1,Interrupt Set 1 Register" bitfld.long 0x00 22. " FORCEFLD[22] ,Force VPU_INT_6" "Normal,Forced" bitfld.long 0x00 21. " [21] ,Force VPU_INT_5" "Normal,Forced" bitfld.long 0x00 20. " [20] ,Force VPU_INT_4" "Normal,Forced" bitfld.long 0x00 19. " [19] ,Force VPU_INT_3" "Normal,Forced" newline bitfld.long 0x00 18. " [18] ,Force VPU_INT_2" "Normal,Forced" bitfld.long 0x00 17. " [17] ,Force VPU_INT_1" "Normal,Forced" bitfld.long 0x00 16. " [16] ,Force VPU_INT_0" "Normal,Forced" bitfld.long 0x00 11. " [11] ,Force SPDIF0_TX_DMA_INT" "Normal,Forced" newline bitfld.long 0x00 10. " [10] ,Force SPDIF0_TX_MOD_INT" "Normal,Forced" bitfld.long 0x00 9. " [9] ,Force SPDIF0_RX_DMA_INT" "Normal,Forced" bitfld.long 0x00 8. " [8] ,Force SPDIF0_RX_MOD_INT" "Normal,Forced" bitfld.long 0x00 7. " [7] ,Force CAAM_RTIC_INT" "Normal,Forced" newline bitfld.long 0x00 6. " [6] ,Force CAAM_INT3" "Normal,Forced" bitfld.long 0x00 5. " [5] ,Force CAAM_INT2" "Normal,Forced" bitfld.long 0x00 4. " [4] ,Force CAAM_INT1" "Normal,Forced" bitfld.long 0x00 3. " [3] ,Force CAAM_INT0" "Normal,Forced" newline bitfld.long 0x00 2. " [2] ,Force SEC_MU3_A_INT" "Normal,Forced" bitfld.long 0x00 1. " [1] ,Force SEC_MU2_A_INT" "Normal,Forced" bitfld.long 0x00 0. " [0] ,Force SEC_MU1_A_INT" "Normal,Forced" line.long 0x04 "SET2,Interrupt Set 2 Register" bitfld.long 0x04 25. " FORCEFLD[25] ,Force UART3_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 24. " [24] ,Force UART3_DMA_RX_INT" "Normal,Forced" bitfld.long 0x04 23. " [23] ,Force UART2_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 22. " [22] ,Force UART2_DMA_RX_INT" "Normal,Forced" newline bitfld.long 0x04 21. " [21] ,Force UART1_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 20. " [20] ,Force UART1_DMA_RX_INT" "Normal,Forced" bitfld.long 0x04 19. " [19] ,Force UART0_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 18. " [18] ,Force UART0_DMA_RX_INT" "Normal,Forced" newline bitfld.long 0x04 15. " [15] ,Force I2C3_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 14. " [14] ,Force I2C3_DMA_RX_INT" "Normal,Forced" bitfld.long 0x04 13. " [13] ,Force I2C2_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 12. " [12] ,Force I2C2_DMA_RX_INT" "Normal,Forced" newline bitfld.long 0x04 11. " [11] ,Force I2C1_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 10. " [10] ,Force I2C1_DMA_RX_INT" "Normal,Forced" bitfld.long 0x04 9. " [9] ,Force I2C0_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 8. " [8] ,Force I2C0_DMA_RX_INT" "Normal,Forced" newline bitfld.long 0x04 7. " [7] ,Force SPI3_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 6. " [6] ,Force SPI3_DMA_RX_INT" "Normal,Forced" bitfld.long 0x04 5. " [5] ,Force SPI2_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 4. " [4] ,Force SPI2_DMA_RX_INT" "Normal,Forced" newline bitfld.long 0x04 3. " [3] ,Force SPI1_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 2. " [2] ,Force SPI1_DMA_RX_INT" "Normal,Forced" bitfld.long 0x04 1. " [1] ,Force SPI0_DMA_TX_INT" "Normal,Forced" bitfld.long 0x04 0. " [0] ,Force SPI0_DMA_RX_INT" "Normal,Forced" line.long 0x08 "SET3,Interrupt Set 3 Register" bitfld.long 0x08 26. " FORCEFLD[26] ,Force ESAI0_DMA_INT" "Normal,Forced" bitfld.long 0x08 25. " [25] ,Force ESAI0_MOD_INT" "Normal,Forced" bitfld.long 0x08 22. " [22] ,Force SPDIF0_TX_INT" "Normal,Forced" bitfld.long 0x08 21. " [21] ,Force SPDIF0_RX_INT" "Normal,Forced" newline bitfld.long 0x08 20. " [20] ,Force SAI5_INT" "Normal,Forced" bitfld.long 0x08 19. " [19] ,Force SAI4_INT" "Normal,Forced" bitfld.long 0x08 16. " [16] ,Force SAI3_INT" "Normal,Forced" bitfld.long 0x08 15. " [15] ,Force SAI2_INT" "Normal,Forced" newline bitfld.long 0x08 14. " [14] ,Force SAI1_INT" "Normal,Forced" bitfld.long 0x08 13. " [13] ,Force SAI0_INT" "Normal,Forced" bitfld.long 0x08 12. " [12] ,Force GPT5_INT" "Normal,Forced" bitfld.long 0x08 11. " [11] ,Force GPT4_INT" "Normal,Forced" newline bitfld.long 0x08 10. " [10] ,Force GPT3_INT" "Normal,Forced" bitfld.long 0x08 9. " [9] ,Force GPT2_INT" "Normal,Forced" bitfld.long 0x08 8. " [8] ,Force GPT1_INT" "Normal,Forced" bitfld.long 0x08 7. " [7] ,Force GPT0_INT" "Normal,Forced" newline bitfld.long 0x08 4. " [4] ,Force ESAI0_INT" "Normal,Forced" bitfld.long 0x08 3. " [3] ,Force DMA1_CH5_INT" "Normal,Forced" bitfld.long 0x08 2. " [2] ,Force DMA1_CH4_INT" "Normal,Forced" bitfld.long 0x08 1. " [1] ,Force DMA1_CH3_INT" "Normal,Forced" newline bitfld.long 0x08 0. " [0] ,Force DMA1_CH2_INT" "Normal,Forced" line.long 0x0C "SET4,Interrupt Set 4 Register" bitfld.long 0x0C 31. " FORCEFLD[31] ,Force DMA1_CH1_INT" "Normal,Forced" bitfld.long 0x0C 30. " [30] ,Force DMA1_CH0_INT" "Normal,Forced" bitfld.long 0x0C 29. " [29] ,Force ASRC1_INT2" "Normal,Forced" bitfld.long 0x0C 28. " [28] ,Force ASRC1_INT1" "Normal,Forced" newline bitfld.long 0x0C 27. " [27] ,Force DMA0_CH5_INT" "Normal,Forced" bitfld.long 0x0C 26. " [26] ,Force DMA0_CH4_INT" "Normal,Forced" bitfld.long 0x0C 25. " [25] ,Force DMA0_CH3_INT" "Normal,Forced" bitfld.long 0x0C 24. " [24] ,Force DMA0_CH2_INT" "Normal,Forced" newline bitfld.long 0x0C 23. " [23] ,Force DMA0_CH1_INT" "Normal,Forced" bitfld.long 0x0C 22. " [22] ,Force DMA0_CH0_INT" "Normal,Forced" bitfld.long 0x0C 21. " [21] ,Force ASRC0_INT2" "Normal,Forced" bitfld.long 0x0C 20. " [20] ,Force ASRC0_INT1" "Normal,Forced" newline bitfld.long 0x0C 19. " [19] ,Force DMA1_ERR_INT" "Normal,Forced" bitfld.long 0x0C 18. " [18] ,Force DMA1_INT" "Normal,Forced" bitfld.long 0x0C 17. " [17] ,Force DMA0_ERR_INT" "Normal,Forced" bitfld.long 0x0C 16. " [16] ,Force DMA0_INT" "Normal,Forced" newline bitfld.long 0x0C 12. " [12] ,Force ADC_DMA_INT" "Normal,Forced" bitfld.long 0x0C 11. " [11] ,Force FTM1_DMA_INT" "Normal,Forced" bitfld.long 0x0C 10. " [10] ,Force FTM_DMA_INT" "Normal,Forced" bitfld.long 0x0C 9. " [9] ,Force FLEXCAN2_DMA_INT" "Normal,Forced" newline bitfld.long 0x0C 8. " [8] ,Force FLEXCAN1_DMA_INT" "Normal,Forced" bitfld.long 0x0C 7. " [7] ,Force FLEXCAN0_DMA_INT" "Normal,Forced" bitfld.long 0x0C 5. " [5] ,Force ADC_MOD_INT" "Normal,Forced" bitfld.long 0x0C 4. " [4] ,Force FTM1_MOD_INT" "Normal,Forced" newline bitfld.long 0x0C 3. " [3] ,Force FTM_MOD_INT" "Normal,Forced" bitfld.long 0x0C 2. " [2] ,Force FLEXCAN2_MOD_INT" "Normal,Forced" bitfld.long 0x0C 1. " [1] ,Force FLEXCAN1_MOD_INT" "Normal,Forced" bitfld.long 0x0C 0. " [0] ,Force FLEXCAN0_MOD_INT" "Normal,Forced" line.long 0x10 "SET5,Interrupt Set 5 Register" bitfld.long 0x10 28. " FORCEFLD[28] ,Force UART3_MOD_INT" "Normal,Forced" bitfld.long 0x10 27. " [27] ,Force UART2_MOD_INT" "Normal,Forced" bitfld.long 0x10 26. " [26] ,Force UART1_MOD_INT" "Normal,Forced" bitfld.long 0x10 25. " [25] ,Force UART0_MOD_INT" "Normal,Forced" newline bitfld.long 0x10 23. " [23] ,Force I2C3_MOD_INT" "Normal,Forced" bitfld.long 0x10 22. " [22] ,Force I2C2_MOD_INT" "Normal,Forced" bitfld.long 0x10 21. " [21] ,Force I2C1_MOD_INT" "Normal,Forced" bitfld.long 0x10 20. " [20] ,Force I2C0_MOD_INT" "Normal,Forced" newline bitfld.long 0x10 19. " [19] ,Force SPI3_MOD_INT" "Normal,Forced" bitfld.long 0x10 18. " [18] ,Force SPI2_MOD_INT" "Normal,Forced" bitfld.long 0x10 17. " [17] ,Force SPI1_MOD_INT" "Normal,Forced" bitfld.long 0x10 16. " [16] ,Force SPI0_MOD_INT" "Normal,Forced" newline bitfld.long 0x10 12. " [12] ,Force SAI5_DMA_INT" "Normal,Forced" bitfld.long 0x10 11. " [11] ,Force SAI5_MOD_INT" "Normal,Forced" bitfld.long 0x10 10. " [10] ,Force SAI4_DMA_INT" "Normal,Forced" bitfld.long 0x10 9. " [9] ,Force SAI4_MOD_INT" "Normal,Forced" newline bitfld.long 0x10 4. " [4] ,Force SAI3_DMA_INT" "Normal,Forced" bitfld.long 0x10 3. " [3] ,Force SAI3_MOD_INT" "Normal,Forced" bitfld.long 0x10 0. " [0] ,Force INT_OUT" "Normal,Forced" line.long 0x14 "SET6,Interrupt Set 6 Register" bitfld.long 0x14 31. " FORCEFLD[31] ,Force SAI2_DMA_INT" "Normal,Forced" bitfld.long 0x14 30. " [30] ,Force SAI2_MOD_INT" "Normal,Forced" bitfld.long 0x14 29. " [29] ,Force SAI1_DMA_INT" "Normal,Forced" bitfld.long 0x14 28. " [28] ,Force SAI1_MOD_INT" "Normal,Forced" newline bitfld.long 0x14 27. " [27] ,Force SAI0_DMA_INT" "Normal,Forced" bitfld.long 0x14 26. " [26] ,Force SAI0_MOD_INT" "Normal,Forced" bitfld.long 0x14 24. " [24] ,Force MJPEG_DEC3_INT" "Normal,Forced" bitfld.long 0x14 23. " [23] ,Force MJPEG_DEC2_INT" "Normal,Forced" newline bitfld.long 0x14 22. " [22] ,Force MJPEG_DEC1_INT" "Normal,Forced" bitfld.long 0x14 21. " [21] ,Force MJPEG_DEC0_INT" "Normal,Forced" bitfld.long 0x14 20. " [20] ,Force MJPEG_ENC3_INT" "Normal,Forced" bitfld.long 0x14 19. " [19] ,Force MJPEG_ENC2_INT" "Normal,Forced" newline bitfld.long 0x14 18. " [18] ,Force MJPEG_ENC1_INT" "Normal,Forced" bitfld.long 0x14 17. " [17] ,Force MJPEG_ENC0_INT" "Normal,Forced" bitfld.long 0x14 16. " [16] ,Force PDMA_STREAM7_INT" "Normal,Forced" bitfld.long 0x14 15. " [15] ,Force PDMA_STREAM6_INT" "Normal,Forced" newline bitfld.long 0x14 14. " [14] ,Force PDMA_STREAM5_INT" "Normal,Forced" bitfld.long 0x14 13. " [13] ,Force PDMA_STREAM4_INT" "Normal,Forced" bitfld.long 0x14 12. " [12] ,Force PDMA_STREAM3_INT" "Normal,Forced" bitfld.long 0x14 11. " [11] ,Force PDMA_STREAM2_INT" "Normal,Forced" newline bitfld.long 0x14 10. " [10] ,Force PDMA_STREAM1_INT" "Normal,Forced" bitfld.long 0x14 9. " [9] ,Force PDMA_STREAM0_INT" "Normal,Forced" bitfld.long 0x14 0. " [0] ,Force MSI_INT" "Normal,Forced" line.long 0x18 "SET7,Interrupt Set 7 Register" bitfld.long 0x18 20. " FORCEFLD[20] ,Force DMA_ERR_INT" "Normal,Forced" bitfld.long 0x18 19. " [19] ,Force DMA_INT" "Normal,Forced" bitfld.long 0x18 18. " [18] ,Force APBHDMA" "Normal,Forced" bitfld.long 0x18 17. " [17] ,Force NAND_GPMI_INT" "Normal,Forced" newline bitfld.long 0x18 16. " [16] ,Force NAND_BCH_INT" "Normal,Forced" bitfld.long 0x18 15. " [15] ,Force USB3_INT" "Normal,Forced" bitfld.long 0x18 14. " [14] ,Force WAKEUP_INT" "Normal,Forced" bitfld.long 0x18 13. " [13] ,Force UTMI_INT" "Normal,Forced" newline bitfld.long 0x18 12. " [12] ,Force USB_HOST_INT" "Normal,Forced" bitfld.long 0x18 11. " [11] ,Force USB_OTG_INT" "Normal,Forced" bitfld.long 0x18 10. " [10] ,Force MLB_AHB_INT" "Normal,Forced" bitfld.long 0x18 9. " [9] ,Force MLB_INT" "Normal,Forced" newline bitfld.long 0x18 7. " [7] ,Force ENET1_TIMER_INT" "Normal,Forced" bitfld.long 0x18 6. " [6] ,Force ENET1_FRAME0_EVENT_INT" "Normal,Forced" bitfld.long 0x18 5. " [5] ,Force ENET1_FRAME2_INT" "Normal,Forced" bitfld.long 0x18 4. " [4] ,Force ENET1_FRAME1_INT" "Normal,Forced" newline bitfld.long 0x18 3. " [3] ,Force ENET0_TIMER_INT" "Normal,Forced" bitfld.long 0x18 2. " [2] ,Force ENET0_FRAME0_EVENT_INT" "Normal,Forced" bitfld.long 0x18 1. " [1] ,Force ENET0_FRAME2_INT" "Normal,Forced" bitfld.long 0x18 0. " [0] ,Force ENET0_FRAME1_INT" "Normal,Forced" line.long 0x1C "SET8,Interrupt Set 8 Register" bitfld.long 0x1C 23. " FORCEFLD[23] ,Force EXTERNAL_DMA_INT_5" "Normal,Forced" bitfld.long 0x1C 22. " [22] ,Force EXTERNAL_DMA_INT_4" "Normal,Forced" bitfld.long 0x1C 21. " [21] ,Force EXTERNAL_DMA_INT_3" "Normal,Forced" bitfld.long 0x1C 20. " [20] ,Force EXTERNAL_DMA_INT_2" "Normal,Forced" newline bitfld.long 0x1C 19. " [19] ,Force EXTERNAL_DMA_INT_1" "Normal,Forced" bitfld.long 0x1C 18. " [18] ,Force EXTERNAL_DMA_INT_0" "Normal,Forced" bitfld.long 0x1C 16. " [16] ,Force ADC_INT" "Normal,Forced" bitfld.long 0x1C 15. " [15] ,Force FTM1_INT" "Normal,Forced" newline bitfld.long 0x1C 14. " [14] ,Force FTM_INT" "Normal,Forced" bitfld.long 0x1C 13. " [13] ,Force FLEXCAN2_INT" "Normal,Forced" bitfld.long 0x1C 12. " [12] ,Force FLEXCAN1_INT" "Normal,Forced" bitfld.long 0x1C 11. " [11] ,Force FLEXCAN0_INT" "Normal,Forced" newline bitfld.long 0x1C 10. " [10] ,Force USDHC2_INT" "Normal,Forced" bitfld.long 0x1C 9. " [9] ,Force USDHC1_INT" "Normal,Forced" bitfld.long 0x1C 8. " [8] ,Force EMMC0_INT/USDHC0_INT" "Normal,Forced" bitfld.long 0x1C 4. " [4] ,Force UART3_INT" "Normal,Forced" newline bitfld.long 0x1C 3. " [3] ,Force UART2_INT" "Normal,Forced" bitfld.long 0x1C 2. " [2] ,Force UART1_INT" "Normal,Forced" bitfld.long 0x1C 1. " [1] ,Force UART0_INT" "Normal,Forced" line.long 0x20 "SET9,Interrupt Set 9 Register" bitfld.long 0x20 31. " FORCEFLD[31] ,Force I2C3_INT" "Normal,Forced" bitfld.long 0x20 30. " [30] ,Force I2C2_INT" "Normal,Forced" bitfld.long 0x20 29. " [29] ,Force I2C1_INT" "Normal,Forced" bitfld.long 0x20 28. " [28] ,Force I2C0_INT" "Normal,Forced" newline bitfld.long 0x20 27. " [27] ,Force SPI3_INT" "Normal,Forced" bitfld.long 0x20 26. " [26] ,Force SPI2_INT" "Normal,Forced" bitfld.long 0x20 25. " [25] ,Force SPI1_INT" "Normal,Forced" bitfld.long 0x20 24. " [24] ,Force SPI0_INT" "Normal,Forced" newline bitfld.long 0x20 16. " [16] ,Force MU13_INT_B" "Normal,Forced" bitfld.long 0x20 15. " [15] ,Force MU12_INT_B" "Normal,Forced" bitfld.long 0x20 14. " [14] ,Force MU11_INT_B" "Normal,Forced" bitfld.long 0x20 13. " [13] ,Force MU10_INT_B" "Normal,Forced" newline bitfld.long 0x20 12. " [12] ,Force MU9_INT_B" "Normal,Forced" bitfld.long 0x20 11. " [11] ,Force MU8_INT_B" "Normal,Forced" bitfld.long 0x20 10. " [10] ,Force MU7_INT_B" "Normal,Forced" bitfld.long 0x20 9. " [9] ,Force MU6_INT_B" "Normal,Forced" newline bitfld.long 0x20 8. " [8] ,Force MU5_INT_B" "Normal,Forced" bitfld.long 0x20 0. " [0] ,Force MU13_INT_A" "Normal,Forced" line.long 0x24 "SET10,Interrupt Set 10 Register" bitfld.long 0x24 31. " FORCEFLD[31] ,Force MU12_INT_A" "Normal,Forced" bitfld.long 0x24 30. " [30] ,Force MU11_INT_A" "Normal,Forced" bitfld.long 0x24 29. " [29] ,Force MU10_INT_A" "Normal,Forced" bitfld.long 0x24 28. " [28] ,Force MU9_INT_A" "Normal,Forced" newline bitfld.long 0x24 27. " [27] ,Force MU8_INT_A" "Normal,Forced" bitfld.long 0x24 26. " [26] ,Force MU7_INT_A" "Normal,Forced" bitfld.long 0x24 25. " [25] ,Force MU6_INT_A" "Normal,Forced" bitfld.long 0x24 24. " [24] ,Force MU5_INT_A" "Normal,Forced" newline bitfld.long 0x24 20. " [20] ,Force MU4_INT" "Normal,Forced" bitfld.long 0x24 19. " [19] ,Force MU3_INT" "Normal,Forced" bitfld.long 0x24 18. " [18] ,Force MU2_INT" "Normal,Forced" bitfld.long 0x24 17. " [17] ,Force MU1_INT" "Normal,Forced" newline bitfld.long 0x24 16. " [16] ,Force MU0_INT" "Normal,Forced" line.long 0x28 "SET11,Interrupt Set 11 Register" bitfld.long 0x28 15. " FORCEFLD[15] ,Force GPIO_INT[7]" "Normal,Forced" bitfld.long 0x28 14. " [14] ,Force GPIO_INT[6]" "Normal,Forced" bitfld.long 0x28 13. " [13] ,Force GPIO_INT[5]" "Normal,Forced" bitfld.long 0x28 12. " [12] ,Force GPIO_INT[4]" "Normal,Forced" newline bitfld.long 0x28 11. " [11] ,Force GPIO_INT[3]" "Normal,Forced" bitfld.long 0x28 10. " [10] ,Force GPIO_INT[2]" "Normal,Forced" bitfld.long 0x28 9. " [9] ,Force GPIO_INT[1]" "Normal,Forced" bitfld.long 0x28 8. " [8] ,Force GPIO_INT[0]" "Normal,Forced" newline bitfld.long 0x28 3. " [3] ,Force PERF_CNT_INT" "Normal,Forced" bitfld.long 0x28 2. " [2] ,Force SBR_DONE_INT" "Normal,Forced" bitfld.long 0x28 1. " [1] ,Force ECC_NCORRECT_INT" "Normal,Forced" bitfld.long 0x28 0. " [0] ,Force ECC_CORRECT_INT" "Normal,Forced" line.long 0x2C "SET12,Interrupt Set 12 Register" bitfld.long 0x2C 27. " FORCEFLD[27] ,Force SYS_COUNT_INT[3]" "Normal,Forced" bitfld.long 0x2C 26. " [26] ,Force SYS_COUNT_INT[2]" "Normal,Forced" bitfld.long 0x2C 25. " [25] ,Force SYS_COUNT_INT[1]" "Normal,Forced" bitfld.long 0x2C 24. " [24] ,Force SYS_COUNT_INT[0]" "Normal,Forced" newline bitfld.long 0x2C 23. " [23] ,Force INT_OUT[7]" "Normal,Forced" bitfld.long 0x2C 22. " [22] ,Force INT_OUT[6]" "Normal,Forced" bitfld.long 0x2C 21. " [21] ,Force INT_OUT[5]" "Normal,Forced" bitfld.long 0x2C 20. " [20] ,Force INT_OUT[4]" "Normal,Forced" newline bitfld.long 0x2C 19. " [19] ,Force INT_OUT[3]" "Normal,Forced" bitfld.long 0x2C 18. " [18] ,Force INT_OUT[2]" "Normal,Forced" bitfld.long 0x2C 17. " [17] ,Force INT_OUT[1]" "Normal,Forced" bitfld.long 0x2C 16. " [16] ,Force INT_OUT[0]" "Normal,Forced" newline bitfld.long 0x2C 15. " [15] ,Force PCIE9_GPIO_WAKEUP[1]" "Normal,Forced" bitfld.long 0x2C 14. " [14] ,Force PCIE9_GPIO_WAKEUP[0]" "Normal,Forced" bitfld.long 0x2C 13. " [13] ,Force PCIE0_SMLH_REQ_RST" "Normal,Forced" bitfld.long 0x2C 12. " [12] ,Force PCIE0_INT_A" "Normal,Forced" newline bitfld.long 0x2C 11. " [11] ,Force PCIE0_INT_B" "Normal,Forced" bitfld.long 0x2C 10. " [10] ,Force PCIE0_INT_C" "Normal,Forced" bitfld.long 0x2C 9. " [9] ,Force PCIE0_INT_D" "Normal,Forced" bitfld.long 0x2C 8. " [8] ,Force PCIE0_DMA_INT" "Normal,Forced" newline bitfld.long 0x2C 7. " [7] ,Force PCIE0_CLK_REQ_INT" "Normal,Forced" bitfld.long 0x2C 6. " [6] ,Force PCIE0_MSI_CTRL_INT" "Normal,Forced" bitfld.long 0x2C 5. " [5] ,Force PWM7_INT" "Normal,Forced" bitfld.long 0x2C 4. " [4] ,Force PWM6_INT" "Normal,Forced" newline bitfld.long 0x2C 3. " [3] ,Force PWM5_INT" "Normal,Forced" bitfld.long 0x2C 2. " [2] ,Force PWM4_INT" "Normal,Forced" bitfld.long 0x2C 1. " [1] ,Force PWM3_INT" "Normal,Forced" bitfld.long 0x2C 0. " [0] ,Force PWM2_INT" "Normal,Forced" line.long 0x30 "SET13,Interrupt Set 13 Register" bitfld.long 0x30 31. " FORCEFLD[31] ,Force PWM1_INT" "Normal,Forced" bitfld.long 0x30 30. " [30] ,Force PWM0_INT" "Normal,Forced" bitfld.long 0x30 29. " [29] ,Force FLEXSPI1_INT" "Normal,Forced" bitfld.long 0x30 28. " [28] ,Force FLEXSPI0_INT" "Normal,Forced" newline bitfld.long 0x30 21. " [21] ,Force KPP0_INT" "Normal,Forced" bitfld.long 0x30 20. " [20] ,Force GPT4_INT" "Normal,Forced" bitfld.long 0x30 19. " [19] ,Force GPT3_INT" "Normal,Forced" bitfld.long 0x30 18. " [18] ,Force GPT2_INT" "Normal,Forced" newline bitfld.long 0x30 17. " [17] ,Force GPT1_INT" "Normal,Forced" bitfld.long 0x30 16. " [16] ,Force GPT0_INT" "Normal,Forced" bitfld.long 0x30 5. " [5] ,Force DMA3_ERR_INT" "Normal,Forced" bitfld.long 0x30 4. " [4] ,Force DMA3_INT" "Normal,Forced" newline bitfld.long 0x30 3. " [3] ,Force DMA2_ERR_INT" "Normal,Forced" bitfld.long 0x30 2. " [2] ,Force DMA2_INT" "Normal,Forced" bitfld.long 0x30 0. " [0] ,Force XAQ2_INTR" "Normal,Forced" line.long 0x34 "SET14,Interrupt Set 14 Register" bitfld.long 0x34 31. " FORCEFLD[31] ,Force LCD_PWM_INT" "Normal,Forced" bitfld.long 0x34 30. " [30] ,Force LCD_MOD_INT" "Normal,Forced" bitfld.long 0x34 28. " [28] ,Force INT_OUT" "Normal,Forced" bitfld.long 0x34 27. " [27] ,Force INT_OUT" "Normal,Forced" newline bitfld.long 0x34 20. " [20] ,Force INT_OUT[12]" "Normal,Forced" bitfld.long 0x34 19. " [19] ,Force INT_OUT[11]" "Normal,Forced" bitfld.long 0x34 18. " [18] ,Force INT_OUT[10]" "Normal,Forced" bitfld.long 0x34 17. " [17] ,Force INT_OUT[9]" "Normal,Forced" newline bitfld.long 0x34 15. " [15] ,Force INT_OUT[7]" "Normal,Forced" bitfld.long 0x34 14. " [14] ,Force INT_OUT[6]" "Normal,Forced" bitfld.long 0x34 13. " [13] ,Force INT_OUT[5]" "Normal,Forced" bitfld.long 0x34 12. " [12] ,Force INT_OUT[4]" "Normal,Forced" newline bitfld.long 0x34 11. " [11] ,Force INT_OUT[3]" "Normal,Forced" bitfld.long 0x34 10. " [10] ,Force INT_OUT[2]" "Normal,Forced" bitfld.long 0x34 9. " [9] ,Force INT_OUT[1]" "Normal,Forced" bitfld.long 0x34 8. " [8] ,Force INT_OUT[0]" "Normal,Forced" line.long 0x38 "SET15,Interrupt Set 15 Register" bitfld.long 0x38 23. " FORCEFLD[23] ,Force INT_OUT[7]" "Normal,Forced" bitfld.long 0x38 22. " [22] ,Force INT_OUT[6]" "Normal,Forced" bitfld.long 0x38 21. " [21] ,Force INT_OUT[5]" "Normal,Forced" bitfld.long 0x38 20. " [20] ,Force INT_OUT[4]" "Normal,Forced" newline bitfld.long 0x38 19. " [19] ,Force INT_OUT[3]" "Normal,Forced" bitfld.long 0x38 18. " [18] ,Force INT_OUT[2]" "Normal,Forced" bitfld.long 0x38 17. " [17] ,Force INT_OUT[1]" "Normal,Forced" bitfld.long 0x38 16. " [16] ,Force INT_OUT[0]" "Normal,Forced" newline bitfld.long 0x38 1. " [1] ,Force nEXTERRIRQ" "Normal,Forced" bitfld.long 0x38 0. " [0] ,Force nINTERRIRQ" "Normal,Forced" rgroup.long 0x88++0x3B line.long 0x00 "STATUS1,Interrupt Status 1 Register" bitfld.long 0x00 22. " STATUS[22] ,VPU_INT_6 status" "Not set,Set" bitfld.long 0x00 21. " [21] ,VPU_INT_5 status" "Not set,Set" bitfld.long 0x00 20. " [20] ,VPU_INT_4 status" "Not set,Set" bitfld.long 0x00 19. " [19] ,VPU_INT_3 status" "Not set,Set" newline bitfld.long 0x00 18. " [18] ,VPU_INT_2 status" "Not set,Set" bitfld.long 0x00 17. " [17] ,VPU_INT_1 status" "Not set,Set" bitfld.long 0x00 16. " [16] ,VPU_INT_0 status" "Not set,Set" bitfld.long 0x00 11. " [11] ,SPDIF0_TX_DMA_INT status" "Not set,Set" newline bitfld.long 0x00 10. " [10] ,SPDIF0_TX_MOD_INT status" "Not set,Set" bitfld.long 0x00 9. " [9] ,SPDIF0_RX_DMA_INT status" "Not set,Set" bitfld.long 0x00 8. " [8] ,SPDIF0_RX_MOD_INT status" "Not set,Set" bitfld.long 0x00 7. " [7] ,CAAM_RTIC_INT status" "Not set,Set" newline bitfld.long 0x00 6. " [6] ,CAAM_INT3 status" "Not set,Set" bitfld.long 0x00 5. " [5] ,CAAM_INT2 status" "Not set,Set" bitfld.long 0x00 4. " [4] ,CAAM_INT1 status" "Not set,Set" bitfld.long 0x00 3. " [3] ,CAAM_INT0 status" "Not set,Set" newline bitfld.long 0x00 2. " [2] ,SEC_MU3_A_INT status" "Not set,Set" bitfld.long 0x00 1. " [1] ,SEC_MU2_A_INT status" "Not set,Set" bitfld.long 0x00 0. " [0] ,SEC_MU1_A_INT status" "Not set,Set" line.long 0x04 "STATUS2,Interrupt Status 2 Register" bitfld.long 0x04 25. " STATUS[25] ,UART3_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 24. " [24] ,UART3_DMA_RX_INT status" "Not set,Set" bitfld.long 0x04 23. " [23] ,UART2_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 22. " [22] ,UART2_DMA_RX_INT status" "Not set,Set" newline bitfld.long 0x04 21. " [21] ,UART1_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 20. " [20] ,UART1_DMA_RX_INT status" "Not set,Set" bitfld.long 0x04 19. " [19] ,UART0_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 18. " [18] ,UART0_DMA_RX_INT status" "Not set,Set" newline bitfld.long 0x04 15. " [15] ,I2C3_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 14. " [14] ,I2C3_DMA_RX_INT status" "Not set,Set" bitfld.long 0x04 13. " [13] ,I2C2_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 12. " [12] ,I2C2_DMA_RX_INT status" "Not set,Set" newline bitfld.long 0x04 11. " [11] ,I2C1_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 10. " [10] ,I2C1_DMA_RX_INT status" "Not set,Set" bitfld.long 0x04 9. " [9] ,I2C0_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 8. " [8] ,I2C0_DMA_RX_INT status" "Not set,Set" newline bitfld.long 0x04 7. " [7] ,SPI3_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 6. " [6] ,SPI3_DMA_RX_INT status" "Not set,Set" bitfld.long 0x04 5. " [5] ,SPI2_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 4. " [4] ,SPI2_DMA_RX_INT status" "Not set,Set" newline bitfld.long 0x04 3. " [3] ,SPI1_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 2. " [2] ,SPI1_DMA_RX_INT status" "Not set,Set" bitfld.long 0x04 1. " [1] ,SPI0_DMA_TX_INT status" "Not set,Set" bitfld.long 0x04 0. " [0] ,SPI0_DMA_RX_INT status" "Not set,Set" line.long 0x08 "STATUS3,Interrupt Status 3 Register" bitfld.long 0x08 26. " STATUS[26] ,ESAI0_DMA_INT status" "Not set,Set" bitfld.long 0x08 25. " [25] ,ESAI0_MOD_INT status" "Not set,Set" bitfld.long 0x08 22. " [22] ,SPDIF0_TX_INT status" "Not set,Set" bitfld.long 0x08 21. " [21] ,SPDIF0_RX_INT status" "Not set,Set" newline bitfld.long 0x08 20. " [20] ,SAI5_INT status" "Not set,Set" bitfld.long 0x08 19. " [19] ,SAI4_INT status" "Not set,Set" bitfld.long 0x08 16. " [16] ,SAI3_INT status" "Not set,Set" bitfld.long 0x08 15. " [15] ,SAI2_INT status" "Not set,Set" newline bitfld.long 0x08 14. " [14] ,SAI1_INT status" "Not set,Set" bitfld.long 0x08 13. " [13] ,SAI0_INT status" "Not set,Set" bitfld.long 0x08 12. " [12] ,GPT5_INT status" "Not set,Set" bitfld.long 0x08 11. " [11] ,GPT4_INT status" "Not set,Set" newline bitfld.long 0x08 10. " [10] ,GPT3_INT status" "Not set,Set" bitfld.long 0x08 9. " [9] ,GPT2_INT status" "Not set,Set" bitfld.long 0x08 8. " [8] ,GPT1_INT status" "Not set,Set" bitfld.long 0x08 7. " [7] ,GPT0_INT status" "Not set,Set" newline bitfld.long 0x08 4. " [4] ,ESAI0_INT status" "Not set,Set" bitfld.long 0x08 3. " [3] ,DMA1_CH5_INT status" "Not set,Set" bitfld.long 0x08 2. " [2] ,DMA1_CH4_INT status" "Not set,Set" bitfld.long 0x08 1. " [1] ,DMA1_CH3_INT status" "Not set,Set" newline bitfld.long 0x08 0. " [0] ,DMA1_CH2_INT status" "Not set,Set" line.long 0x0C "STATUS4,Interrupt Status 4 Register" bitfld.long 0x0C 31. " STATUS[31] ,DMA1_CH1_INT status" "Not set,Set" bitfld.long 0x0C 30. " [30] ,DMA1_CH0_INT status" "Not set,Set" bitfld.long 0x0C 29. " [29] ,ASRC1_INT2 status" "Not set,Set" bitfld.long 0x0C 28. " [28] ,ASRC1_INT1 status" "Not set,Set" newline bitfld.long 0x0C 27. " [27] ,DMA0_CH5_INT status" "Not set,Set" bitfld.long 0x0C 26. " [26] ,DMA0_CH4_INT status" "Not set,Set" bitfld.long 0x0C 25. " [25] ,DMA0_CH3_INT status" "Not set,Set" bitfld.long 0x0C 24. " [24] ,DMA0_CH2_INT status" "Not set,Set" newline bitfld.long 0x0C 23. " [23] ,DMA0_CH1_INT status" "Not set,Set" bitfld.long 0x0C 22. " [22] ,DMA0_CH0_INT status" "Not set,Set" bitfld.long 0x0C 21. " [21] ,ASRC0_INT2 status" "Not set,Set" bitfld.long 0x0C 20. " [20] ,ASRC0_INT1 status" "Not set,Set" newline bitfld.long 0x0C 19. " [19] ,DMA1_ERR_INT status" "Not set,Set" bitfld.long 0x0C 18. " [18] ,DMA1_INT status" "Not set,Set" bitfld.long 0x0C 17. " [17] ,DMA0_ERR_INT status" "Not set,Set" bitfld.long 0x0C 16. " [16] ,DMA0_INT status" "Not set,Set" newline bitfld.long 0x0C 12. " [12] ,ADC_DMA_INT status" "Not set,Set" bitfld.long 0x0C 11. " [11] ,FTM1_DMA_INT status" "Not set,Set" bitfld.long 0x0C 10. " [10] ,FTM_DMA_INT status" "Not set,Set" bitfld.long 0x0C 9. " [9] ,FLEXCAN2_DMA_INT status" "Not set,Set" newline bitfld.long 0x0C 8. " [8] ,FLEXCAN1_DMA_INT status" "Not set,Set" bitfld.long 0x0C 7. " [7] ,FLEXCAN0_DMA_INT status" "Not set,Set" bitfld.long 0x0C 5. " [5] ,ADC_MOD_INT status" "Not set,Set" bitfld.long 0x0C 4. " [4] ,FTM1_MOD_INT status" "Not set,Set" newline bitfld.long 0x0C 3. " [3] ,FTM_MOD_INT status" "Not set,Set" bitfld.long 0x0C 2. " [2] ,FLEXCAN2_MOD_INT status" "Not set,Set" bitfld.long 0x0C 1. " [1] ,FLEXCAN1_MOD_INT status" "Not set,Set" bitfld.long 0x0C 0. " [0] ,FLEXCAN0_MOD_INT status" "Not set,Set" line.long 0x10 "STATUS5,Interrupt Status 5 Register" bitfld.long 0x10 28. " STATUS[28] ,UART3_MOD_INT status" "Not set,Set" bitfld.long 0x10 27. " [27] ,UART2_MOD_INT status" "Not set,Set" bitfld.long 0x10 26. " [26] ,UART1_MOD_INT status" "Not set,Set" bitfld.long 0x10 25. " [25] ,UART0_MOD_INT status" "Not set,Set" newline bitfld.long 0x10 23. " [23] ,I2C3_MOD_INT status" "Not set,Set" bitfld.long 0x10 22. " [22] ,I2C2_MOD_INT status" "Not set,Set" bitfld.long 0x10 21. " [21] ,I2C1_MOD_INT status" "Not set,Set" bitfld.long 0x10 20. " [20] ,I2C0_MOD_INT status" "Not set,Set" newline bitfld.long 0x10 19. " [19] ,SPI3_MOD_INT status" "Not set,Set" bitfld.long 0x10 18. " [18] ,SPI2_MOD_INT status" "Not set,Set" bitfld.long 0x10 17. " [17] ,SPI1_MOD_INT status" "Not set,Set" bitfld.long 0x10 16. " [16] ,SPI0_MOD_INT status" "Not set,Set" newline bitfld.long 0x10 12. " [12] ,SAI5_DMA_INT status" "Not set,Set" bitfld.long 0x10 11. " [11] ,SAI5_MOD_INT status" "Not set,Set" bitfld.long 0x10 10. " [10] ,SAI4_DMA_INT status" "Not set,Set" bitfld.long 0x10 9. " [9] ,SAI4_MOD_INT status" "Not set,Set" newline bitfld.long 0x10 4. " [4] ,SAI3_DMA_INT status" "Not set,Set" bitfld.long 0x10 3. " [3] ,SAI3_MOD_INT status" "Not set,Set" bitfld.long 0x10 0. " [0] ,INT_OUT status" "Not set,Set" line.long 0x14 "STATUS6,Interrupt Status 6 Register" bitfld.long 0x14 31. " STATUS[31] ,SAI2_DMA_INT status" "Not set,Set" bitfld.long 0x14 30. " [30] ,SAI2_MOD_INT status" "Not set,Set" bitfld.long 0x14 29. " [29] ,SAI1_DMA_INT status" "Not set,Set" bitfld.long 0x14 28. " [28] ,SAI1_MOD_INT status" "Not set,Set" newline bitfld.long 0x14 27. " [27] ,SAI0_DMA_INT status" "Not set,Set" bitfld.long 0x14 26. " [26] ,SAI0_MOD_INT status" "Not set,Set" bitfld.long 0x14 24. " [24] ,MJPEG_DEC3_INT status" "Not set,Set" bitfld.long 0x14 23. " [23] ,MJPEG_DEC2_INT status" "Not set,Set" newline bitfld.long 0x14 22. " [22] ,MJPEG_DEC1_INT status" "Not set,Set" bitfld.long 0x14 21. " [21] ,MJPEG_DEC0_INT status" "Not set,Set" bitfld.long 0x14 20. " [20] ,MJPEG_ENC3_INT status" "Not set,Set" bitfld.long 0x14 19. " [19] ,MJPEG_ENC2_INT status" "Not set,Set" newline bitfld.long 0x14 18. " [18] ,MJPEG_ENC1_INT status" "Not set,Set" bitfld.long 0x14 17. " [17] ,MJPEG_ENC0_INT status" "Not set,Set" bitfld.long 0x14 16. " [16] ,PDMA_STREAM7_INT status" "Not set,Set" bitfld.long 0x14 15. " [15] ,PDMA_STREAM6_INT status" "Not set,Set" newline bitfld.long 0x14 14. " [14] ,PDMA_STREAM5_INT status" "Not set,Set" bitfld.long 0x14 13. " [13] ,PDMA_STREAM4_INT status" "Not set,Set" bitfld.long 0x14 12. " [12] ,PDMA_STREAM3_INT status" "Not set,Set" bitfld.long 0x14 11. " [11] ,PDMA_STREAM2_INT status" "Not set,Set" newline bitfld.long 0x14 10. " [10] ,PDMA_STREAM1_INT status" "Not set,Set" bitfld.long 0x14 9. " [9] ,PDMA_STREAM0_INT status" "Not set,Set" bitfld.long 0x14 0. " [0] ,MSI_INT status" "Not set,Set" line.long 0x18 "STATUS7,Interrupt Status 7 Register" bitfld.long 0x18 20. " STATUS[20] ,DMA_ERR_INT status" "Not set,Set" bitfld.long 0x18 19. " [19] ,DMA_INT status" "Not set,Set" bitfld.long 0x18 18. " [18] ,APBHDMA status" "Not set,Set" bitfld.long 0x18 17. " [17] ,NAND_GPMI_INT status" "Not set,Set" newline bitfld.long 0x18 16. " [16] ,NAND_BCH_INT status" "Not set,Set" bitfld.long 0x18 15. " [15] ,USB3_INT status" "Not set,Set" bitfld.long 0x18 14. " [14] ,WAKEUP_INT status" "Not set,Set" bitfld.long 0x18 13. " [13] ,UTMI_INT status" "Not set,Set" newline bitfld.long 0x18 12. " [12] ,USB_HOST_INT status" "Not set,Set" bitfld.long 0x18 11. " [11] ,USB_OTG_INT status" "Not set,Set" bitfld.long 0x18 10. " [10] ,MLB_AHB_INT status" "Not set,Set" bitfld.long 0x18 9. " [9] ,MLB_INT status" "Not set,Set" newline bitfld.long 0x18 7. " [7] ,ENET1_TIMER_INT status" "Not set,Set" bitfld.long 0x18 6. " [6] ,ENET1_FRAME0_EVENT_INT status" "Not set,Set" bitfld.long 0x18 5. " [5] ,ENET1_FRAME2_INT status" "Not set,Set" bitfld.long 0x18 4. " [4] ,ENET1_FRAME1_INT status" "Not set,Set" newline bitfld.long 0x18 3. " [3] ,ENET0_TIMER_INT status" "Not set,Set" bitfld.long 0x18 2. " [2] ,ENET0_FRAME0_EVENT_INT status" "Not set,Set" bitfld.long 0x18 1. " [1] ,ENET0_FRAME2_INT status" "Not set,Set" bitfld.long 0x18 0. " [0] ,ENET0_FRAME1_INT status" "Not set,Set" line.long 0x1C "STATUS8,Interrupt Status 8 Register" bitfld.long 0x1C 23. " STATUS[23] ,EXTERNAL_DMA_INT_5 status" "Not set,Set" bitfld.long 0x1C 22. " [22] ,EXTERNAL_DMA_INT_4 status" "Not set,Set" bitfld.long 0x1C 21. " [21] ,EXTERNAL_DMA_INT_3 status" "Not set,Set" bitfld.long 0x1C 20. " [20] ,EXTERNAL_DMA_INT_2 status" "Not set,Set" newline bitfld.long 0x1C 19. " [19] ,EXTERNAL_DMA_INT_1 status" "Not set,Set" bitfld.long 0x1C 18. " [18] ,EXTERNAL_DMA_INT_0 status" "Not set,Set" bitfld.long 0x1C 16. " [16] ,ADC_INT status" "Not set,Set" bitfld.long 0x1C 15. " [15] ,FTM1_INT status" "Not set,Set" newline bitfld.long 0x1C 14. " [14] ,FTM_INT status" "Not set,Set" bitfld.long 0x1C 13. " [13] ,FLEXCAN2_INT status" "Not set,Set" bitfld.long 0x1C 12. " [12] ,FLEXCAN1_INT status" "Not set,Set" bitfld.long 0x1C 11. " [11] ,FLEXCAN0_INT status" "Not set,Set" newline bitfld.long 0x1C 10. " [10] ,USDHC2_INT status" "Not set,Set" bitfld.long 0x1C 9. " [9] ,USDHC1_INT status" "Not set,Set" bitfld.long 0x1C 8. " [8] ,EMMC0_INT/USDHC0_INT status" "Not set,Set" bitfld.long 0x1C 4. " [4] ,UART3_INT status" "Not set,Set" newline bitfld.long 0x1C 3. " [3] ,UART2_INT status" "Not set,Set" bitfld.long 0x1C 2. " [2] ,UART1_INT status" "Not set,Set" bitfld.long 0x1C 1. " [1] ,UART0_INT status" "Not set,Set" line.long 0x20 "STATUS9,Interrupt Status 9 Register" bitfld.long 0x20 31. " STATUS[31] ,I2C3_INT status" "Not set,Set" bitfld.long 0x20 30. " [30] ,I2C2_INT status" "Not set,Set" bitfld.long 0x20 29. " [29] ,I2C1_INT status" "Not set,Set" bitfld.long 0x20 28. " [28] ,I2C0_INT status" "Not set,Set" newline bitfld.long 0x20 27. " [27] ,SPI3_INT status" "Not set,Set" bitfld.long 0x20 26. " [26] ,SPI2_INT status" "Not set,Set" bitfld.long 0x20 25. " [25] ,SPI1_INT status" "Not set,Set" bitfld.long 0x20 24. " [24] ,SPI0_INT status" "Not set,Set" newline bitfld.long 0x20 16. " [16] ,MU13_INT_B status" "Not set,Set" bitfld.long 0x20 15. " [15] ,MU12_INT_B status" "Not set,Set" bitfld.long 0x20 14. " [14] ,MU11_INT_B status" "Not set,Set" bitfld.long 0x20 13. " [13] ,MU10_INT_B status" "Not set,Set" newline bitfld.long 0x20 12. " [12] ,MU9_INT_B status" "Not set,Set" bitfld.long 0x20 11. " [11] ,MU8_INT_B status" "Not set,Set" bitfld.long 0x20 10. " [10] ,MU7_INT_B status" "Not set,Set" bitfld.long 0x20 9. " [9] ,MU6_INT_B status" "Not set,Set" newline bitfld.long 0x20 8. " [8] ,MU5_INT_B status" "Not set,Set" bitfld.long 0x20 0. " [0] ,MU13_INT_A status" "Not set,Set" line.long 0x24 "STATUS10,Interrupt Status 10 Register" bitfld.long 0x24 31. " STATUS[31] ,MU12_INT_A status" "Not set,Set" bitfld.long 0x24 30. " [30] ,MU11_INT_A status" "Not set,Set" bitfld.long 0x24 29. " [29] ,MU10_INT_A status" "Not set,Set" bitfld.long 0x24 28. " [28] ,MU9_INT_A status" "Not set,Set" newline bitfld.long 0x24 27. " [27] ,MU8_INT_A status" "Not set,Set" bitfld.long 0x24 26. " [26] ,MU7_INT_A status" "Not set,Set" bitfld.long 0x24 25. " [25] ,MU6_INT_A status" "Not set,Set" bitfld.long 0x24 24. " [24] ,MU5_INT_A status" "Not set,Set" newline bitfld.long 0x24 20. " [20] ,MU4_INT status" "Not set,Set" bitfld.long 0x24 19. " [19] ,MU3_INT status" "Not set,Set" bitfld.long 0x24 18. " [18] ,MU2_INT status" "Not set,Set" bitfld.long 0x24 17. " [17] ,MU1_INT status" "Not set,Set" newline bitfld.long 0x24 16. " [16] ,MU0_INT status" "Not set,Set" line.long 0x28 "STATUS11,Interrupt Status 11 Register" bitfld.long 0x28 15. " STATUS[15] ,GPIO_INT[7] status" "Not set,Set" bitfld.long 0x28 14. " [14] ,GPIO_INT[6] status" "Not set,Set" bitfld.long 0x28 13. " [13] ,GPIO_INT[5] status" "Not set,Set" bitfld.long 0x28 12. " [12] ,GPIO_INT[4] status" "Not set,Set" newline bitfld.long 0x28 11. " [11] ,GPIO_INT[3] status" "Not set,Set" bitfld.long 0x28 10. " [10] ,GPIO_INT[2] status" "Not set,Set" bitfld.long 0x28 9. " [9] ,GPIO_INT[1] status" "Not set,Set" bitfld.long 0x28 8. " [8] ,GPIO_INT[0] status" "Not set,Set" newline bitfld.long 0x28 3. " [3] ,PERF_CNT_INT status" "Not set,Set" bitfld.long 0x28 2. " [2] ,SBR_DONE_INT status" "Not set,Set" bitfld.long 0x28 1. " [1] ,ECC_NCORRECT_INT status" "Not set,Set" bitfld.long 0x28 0. " [0] ,ECC_CORRECT_INT status" "Not set,Set" line.long 0x2C "STATUS12,Interrupt Status 12 Register" bitfld.long 0x2C 27. " STATUS[27] ,SYS_COUNT_INT[3] status" "Not set,Set" bitfld.long 0x2C 26. " [26] ,SYS_COUNT_INT[2] status" "Not set,Set" bitfld.long 0x2C 25. " [25] ,SYS_COUNT_INT[1] status" "Not set,Set" bitfld.long 0x2C 24. " [24] ,SYS_COUNT_INT[0] status" "Not set,Set" newline bitfld.long 0x2C 23. " [23] ,INT_OUT[7] status" "Not set,Set" bitfld.long 0x2C 22. " [22] ,INT_OUT[6] status" "Not set,Set" bitfld.long 0x2C 21. " [21] ,INT_OUT[5] status" "Not set,Set" bitfld.long 0x2C 20. " [20] ,INT_OUT[4] status" "Not set,Set" newline bitfld.long 0x2C 19. " [19] ,INT_OUT[3] status" "Not set,Set" bitfld.long 0x2C 18. " [18] ,INT_OUT[2] status" "Not set,Set" bitfld.long 0x2C 17. " [17] ,INT_OUT[1] status" "Not set,Set" bitfld.long 0x2C 16. " [16] ,INT_OUT[0] status" "Not set,Set" newline bitfld.long 0x2C 15. " [15] ,PCIE9_GPIO_WAKEUP[1] status" "Not set,Set" bitfld.long 0x2C 14. " [14] ,PCIE9_GPIO_WAKEUP[0] status" "Not set,Set" bitfld.long 0x2C 13. " [13] ,PCIE0_SMLH_REQ_RST status" "Not set,Set" bitfld.long 0x2C 12. " [12] ,PCIE0_INT_A status" "Not set,Set" newline bitfld.long 0x2C 11. " [11] ,PCIE0_INT_B status" "Not set,Set" bitfld.long 0x2C 10. " [10] ,PCIE0_INT_C status" "Not set,Set" bitfld.long 0x2C 9. " [9] ,PCIE0_INT_D status" "Not set,Set" bitfld.long 0x2C 8. " [8] ,PCIE0_DMA_INT status" "Not set,Set" newline bitfld.long 0x2C 7. " [7] ,PCIE0_CLK_REQ_INT status" "Not set,Set" bitfld.long 0x2C 6. " [6] ,PCIE0_MSI_CTRL_INT status" "Not set,Set" bitfld.long 0x2C 5. " [5] ,PWM7_INT status" "Not set,Set" bitfld.long 0x2C 4. " [4] ,PWM6_INT status" "Not set,Set" newline bitfld.long 0x2C 3. " [3] ,PWM5_INT status" "Not set,Set" bitfld.long 0x2C 2. " [2] ,PWM4_INT status" "Not set,Set" bitfld.long 0x2C 1. " [1] ,PWM3_INT status" "Not set,Set" bitfld.long 0x2C 0. " [0] ,PWM2_INT status" "Not set,Set" line.long 0x30 "STATUS13,Interrupt Status 13 Register" bitfld.long 0x30 31. " STATUS[31] ,PWM1_INT status" "Not set,Set" bitfld.long 0x30 30. " [30] ,PWM0_INT status" "Not set,Set" bitfld.long 0x30 29. " [29] ,FLEXSPI1_INT status" "Not set,Set" bitfld.long 0x30 28. " [28] ,FLEXSPI0_INT status" "Not set,Set" newline bitfld.long 0x30 21. " [21] ,KPP0_INT status" "Not set,Set" bitfld.long 0x30 20. " [20] ,GPT4_INT status" "Not set,Set" bitfld.long 0x30 19. " [19] ,GPT3_INT status" "Not set,Set" bitfld.long 0x30 18. " [18] ,GPT2_INT status" "Not set,Set" newline bitfld.long 0x30 17. " [17] ,GPT1_INT status" "Not set,Set" bitfld.long 0x30 16. " [16] ,GPT0_INT status" "Not set,Set" bitfld.long 0x30 5. " [5] ,DMA3_ERR_INT status" "Not set,Set" bitfld.long 0x30 4. " [4] ,DMA3_INT status" "Not set,Set" newline bitfld.long 0x30 3. " [3] ,DMA2_ERR_INT status" "Not set,Set" bitfld.long 0x30 2. " [2] ,DMA2_INT status" "Not set,Set" bitfld.long 0x30 0. " [0] ,XAQ2_INTR status" "Not set,Set" line.long 0x34 "STATUS14,Interrupt Status 14 Register" bitfld.long 0x34 31. " STATUS[31] ,LCD_PWM_INT status" "Not set,Set" bitfld.long 0x34 30. " [30] ,LCD_MOD_INT status" "Not set,Set" bitfld.long 0x34 28. " [28] ,INT_OUT status" "Not set,Set" bitfld.long 0x34 27. " [27] ,INT_OUT status" "Not set,Set" newline bitfld.long 0x34 20. " [20] ,INT_OUT[12] status" "Not set,Set" bitfld.long 0x34 19. " [19] ,INT_OUT[11] status" "Not set,Set" bitfld.long 0x34 18. " [18] ,INT_OUT[10] status" "Not set,Set" bitfld.long 0x34 17. " [17] ,INT_OUT[9] status" "Not set,Set" newline bitfld.long 0x34 15. " [15] ,INT_OUT[7] status" "Not set,Set" bitfld.long 0x34 14. " [14] ,INT_OUT[6] status" "Not set,Set" bitfld.long 0x34 13. " [13] ,INT_OUT[5] status" "Not set,Set" bitfld.long 0x34 12. " [12] ,INT_OUT[4] status" "Not set,Set" newline bitfld.long 0x34 11. " [11] ,INT_OUT[3] status" "Not set,Set" bitfld.long 0x34 10. " [10] ,INT_OUT[2] status" "Not set,Set" bitfld.long 0x34 9. " [9] ,INT_OUT[1] status" "Not set,Set" bitfld.long 0x34 8. " [8] ,INT_OUT[0] status" "Not set,Set" line.long 0x38 "STATUS15,Interrupt Status 15 Register" bitfld.long 0x38 23. " STATUS[23] ,INT_OUT[7] status" "Not set,Set" bitfld.long 0x38 22. " [22] ,INT_OUT[6] status" "Not set,Set" bitfld.long 0x38 21. " [21] ,INT_OUT[5] status" "Not set,Set" bitfld.long 0x38 20. " [20] ,INT_OUT[4] status" "Not set,Set" newline bitfld.long 0x38 19. " [19] ,INT_OUT[3] status" "Not set,Set" bitfld.long 0x38 18. " [18] ,INT_OUT[2] status" "Not set,Set" bitfld.long 0x38 17. " [17] ,INT_OUT[1] status" "Not set,Set" bitfld.long 0x38 16. " [16] ,INT_OUT[0] status" "Not set,Set" newline bitfld.long 0x38 1. " [1] ,nEXTERRIRQ status" "Not set,Set" bitfld.long 0x38 0. " [0] ,nINTERRIRQ status" "Not set,Set" group.long 0xC4++0x03 line.long 0x00 "MINTDIS,Master Interrupt Disable Register" bitfld.long 0x00 7. " DISABLE[7] ,Disables interrupts from 511 to 448" "No,Yes" bitfld.long 0x00 6. " [6] ,Disables interrupts from 447 to 384" "No,Yes" bitfld.long 0x00 5. " [5] ,Disables interrupts from 383 to 320" "No,Yes" bitfld.long 0x00 4. " [4] ,Disables interrupts from 319 to 256" "No,Yes" newline bitfld.long 0x00 3. " [3] ,Disables interrupts from 255 to 192" "No,Yes" bitfld.long 0x00 2. " [2] ,Disables interrupts from 191 to 128" "No,Yes" bitfld.long 0x00 1. " [1] ,Disables interrupts from 127 to 64" "No,Yes" bitfld.long 0x00 0. " [0] ,Disables interrupts from 63 to 0" "No,Yes" newline rgroup.long 0xC8++0x03 line.long 0x00 "MSTRSTAT,Master Status Register" bitfld.long 0x00 0. " STATUS ,Status of all interrupts" "Not asserted,At least one interrupt is asserted" width 0x0B tree.end tree.end tree "PC (Pixel Combiner)" base ad:0x56020000 width 14. group.long 0x00++0x2F line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 22. " DISP1_BYPASS ,Display1 bypassed" "Not bypassed,Bypassed" bitfld.long 0x00 19.--21. " DISP1_PIX_DATA_FORMAT ,Display1 pixel data format" "RGB/YUV444,YUV422,YUV420,Two RGB stream,?..." bitfld.long 0x00 16.--18. " DISP0_PIX_DATA_FORMAT ,Display1 pixel data format" "RGB/YUV444,YUV422,YUV420,Two RGB stream,?..." bitfld.long 0x00 15. " DISP1_DVALID_POLARITY ,Display1 data enable polarity" "Negative,Positive" newline bitfld.long 0x00 14. " DISP1_VSYNC_POLARITY ,Display1 VSYNC polarity" "Negative,Positive" bitfld.long 0x00 13. " DISP1_HSYNC_POLARITY ,Display1 HSYNC polarity" "Negative,Positive" bitfld.long 0x00 7.--12. " SKIP_NUMBER ,Skipped pixels to eliminate the edge effects of scaling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 6. " SKIP_MODE ,Skip mode" "Unaligned,Aligned" newline bitfld.long 0x00 5. " VSYNC_MASK_ENABLE ,VSYNC mask function enable" "Disabled,Enabled" bitfld.long 0x00 4. " DISP0_DVALID_POLARITY ,Data enable polarity" "Low,High" bitfld.long 0x00 3. " DISP0_VSYNC_POLARITY ,Vsync polarity" "Low,High" bitfld.long 0x00 2. " DISP0_HSYNC_POLARITY ,Hsync polarity" "Low,High" newline bitfld.long 0x00 1. " DISP0_BYPASS ,Displa0 bypass" "Not bypassed,Bypassed" bitfld.long 0x00 0. " ENABLE ,Pixel combine function enable" "Disabled,Enabled" line.long 0x04 "CTRL_SET,Control Set Register" bitfld.long 0x04 22. " DISP1_BYPASS ,Display1 bypassed" "Not bypassed,Bypassed" bitfld.long 0x04 19.--21. " DISP1_PIX_DATA_FORMAT ,Display1 pixel data format" "RGB/YUV444,YUV422,YUV420,Two RGB stream,?..." bitfld.long 0x04 16.--18. " DISP0_PIX_DATA_FORMAT ,Display1 pixel data format" "RGB/YUV444,YUV422,YUV420,Two RGB stream,?..." bitfld.long 0x04 15. " DISP1_DVALID_POLARITY ,Display1 data enable polarity" "Negative,Positive" newline bitfld.long 0x04 14. " DISP1_VSYNC_POLARITY ,Display1 VSYNC polarity" "Negative,Positive" bitfld.long 0x04 13. " DISP1_HSYNC_POLARITY ,Display1 HSYNC polarity" "Negative,Positive" bitfld.long 0x04 7.--12. " SKIP_NUMBER ,Skipped pixels to eliminate the edge effects of scaling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 6. " SKIP_MODE ,Skip mode" "Unaligned,Aligned" newline bitfld.long 0x04 5. " VSYNC_MASK_ENABLE ,VSYNC mask function enable" "Disabled,Enabled" bitfld.long 0x04 4. " DISP0_DVALID_POLARITY ,Data enable polarity" "Low,High" bitfld.long 0x04 3. " DISP0_VSYNC_POLARITY ,Vsync polarity" "Low,High" bitfld.long 0x04 2. " DISP0_HSYNC_POLARITY ,Hsync polarity" "Low,High" newline bitfld.long 0x04 1. " DISP0_BYPASS ,Displa0 bypass" "Not bypassed,Bypassed" bitfld.long 0x04 0. " ENABLE ,Pixel combine function enable" "Disabled,Enabled" line.long 0x08 "CTRL_CLR,Control Clear Register" bitfld.long 0x08 22. " DISP1_BYPASS ,Display1 bypassed" "Not bypassed,Bypassed" bitfld.long 0x08 19.--21. " DISP1_PIX_DATA_FORMAT ,Display1 pixel data format" "RGB/YUV444,YUV422,YUV420,Two RGB stream,?..." bitfld.long 0x08 16.--18. " DISP0_PIX_DATA_FORMAT ,Display1 pixel data format" "RGB/YUV444,YUV422,YUV420,Two RGB stream,?..." bitfld.long 0x08 15. " DISP1_DVALID_POLARITY ,Display1 data enable polarity" "Negative,Positive" newline bitfld.long 0x08 14. " DISP1_VSYNC_POLARITY ,Display1 VSYNC polarity" "Negative,Positive" bitfld.long 0x08 13. " DISP1_HSYNC_POLARITY ,Display1 HSYNC polarity" "Negative,Positive" bitfld.long 0x08 7.--12. " SKIP_NUMBER ,Skipped pixels to eliminate the edge effects of scaling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 6. " SKIP_MODE ,Skip mode" "Unaligned,Aligned" newline bitfld.long 0x08 5. " VSYNC_MASK_ENABLE ,VSYNC mask function enable" "Disabled,Enabled" bitfld.long 0x08 4. " DISP0_DVALID_POLARITY ,Data enable polarity" "Low,High" bitfld.long 0x08 3. " DISP0_VSYNC_POLARITY ,Vsync polarity" "Low,High" bitfld.long 0x08 2. " DISP0_HSYNC_POLARITY ,Hsync polarity" "Low,High" newline bitfld.long 0x08 1. " DISP0_BYPASS ,Displa0 bypass" "Not bypassed,Bypassed" bitfld.long 0x08 0. " ENABLE ,Pixel combine function enable" "Disabled,Enabled" line.long 0x0C "CTRL_TOG,Control TOG Register" bitfld.long 0x0C 22. " DISP1_BYPASS ,Display1 bypassed" "Not bypassed,Bypassed" bitfld.long 0x0C 19.--21. " DISP1_PIX_DATA_FORMAT ,Display1 pixel data format" "RGB/YUV444,YUV422,YUV420,Two RGB stream,?..." bitfld.long 0x0C 16.--18. " DISP0_PIX_DATA_FORMAT ,Display1 pixel data format" "RGB/YUV444,YUV422,YUV420,Two RGB stream,?..." bitfld.long 0x0C 15. " DISP1_DVALID_POLARITY ,Display1 data enable polarity" "Negative,Positive" newline bitfld.long 0x0C 14. " DISP1_VSYNC_POLARITY ,Display1 VSYNC polarity" "Negative,Positive" bitfld.long 0x0C 13. " DISP1_HSYNC_POLARITY ,Display1 HSYNC polarity" "Negative,Positive" bitfld.long 0x0C 7.--12. " SKIP_NUMBER ,Skipped pixels to eliminate the edge effects of scaling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 6. " SKIP_MODE ,Skip mode" "Unaligned,Aligned" newline bitfld.long 0x0C 5. " VSYNC_MASK_ENABLE ,VSYNC mask function enable" "Disabled,Enabled" bitfld.long 0x0C 4. " DISP0_DVALID_POLARITY ,Data enable polarity" "Low,High" bitfld.long 0x0C 3. " DISP0_VSYNC_POLARITY ,Vsync polarity" "Low,High" bitfld.long 0x0C 2. " DISP0_HSYNC_POLARITY ,Hsync polarity" "Low,High" newline bitfld.long 0x0C 1. " DISP0_BYPASS ,Displa0 bypass" "Not bypassed,Bypassed" bitfld.long 0x0C 0. " ENABLE ,Pixel combine function enable" "Disabled,Enabled" line.long 0x10 "BUF_PARA,Buffer Parameter Register" hexmask.long.word 0x10 0.--10. 1. " BUF_ACTIVE_DEPTH ,Buffer active depth" line.long 0x14 "BUF_PARA_SET,Buffer Parameter Set Register" hexmask.long.word 0x14 0.--10. 1. " BUF_ACTIVE_DEPTH ,Buffer active depth" line.long 0x18 "BUF_PARA_CLR,Buffer Parameter Clear Register" hexmask.long.word 0x18 0.--10. 1. " BUF_ACTIVE_DEPTH ,Buffer active depth" line.long 0x1C "BUF_PARA_TOG,Buffer Parameter TOG Register" hexmask.long.word 0x1C 0.--10. 1. " BUF_ACTIVE_DEPTH ,Buffer active depth" line.long 0x20 "SW_RESET,Software Reset Register" bitfld.long 0x20 2. " DISP1_SW_RESET ,Display1 software reset control" "No reset,Reset" bitfld.long 0x20 1. " DISP0_SW_RESET ,Display0 software reset control" "No reset,Reset" bitfld.long 0x20 0. " PC_SW_RESET ,Pixel combiner software reset control" "No reset,Reset" line.long 0x24 "SW_RESET_SET,Software Reset Set Register" bitfld.long 0x24 2. " DISP1_SW_RESET ,Display1 software reset control" "No reset,Reset" bitfld.long 0x24 1. " DISP0_SW_RESET ,Display0 software reset control" "No reset,Reset" bitfld.long 0x24 0. " PC_SW_RESET ,Pixel combiner software reset control" "No reset,Reset" line.long 0x28 "SW_RESET_CLR,Software Reset Clear Register" bitfld.long 0x28 2. " DISP1_SW_RESET ,Display1 software reset control" "No reset,Reset" bitfld.long 0x28 1. " DISP0_SW_RESET ,Display0 software reset control" "No reset,Reset" bitfld.long 0x28 0. " PC_SW_RESET ,Pixel combiner software reset control" "No reset,Reset" line.long 0x2C "SW_RESET_TOG,Software Reset TOG Register" bitfld.long 0x2C 2. " DISP1_SW_RESET ,Display1 software reset control" "No reset,Reset" bitfld.long 0x2C 1. " DISP0_SW_RESET ,Display0 software reset control" "No reset,Reset" bitfld.long 0x2C 0. " PC_SW_RESET ,Pixel combiner software reset control" "No reset,Reset" width 0x0B tree.end tree "LTS (Linear Tile Store)" base ad:0x56030000 width 18. group.long 0x00++0x7F line.long 0x00 "CTRL_SET/CLR,Control Set/Clear Register" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " SFTRST ,LTS clocking (normal operation) disable" "No,Yes" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " CLKGATE ,Gate clocks to the block" "Not gated,Gated" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " ENABLE ,LTS operation with specified parameters enable" "Disabled,Enabled" line.long 0x0C "CTRL_TOG,Control TOG Register" bitfld.long 0x0C 31. " SFTRST ,LTS clocking (normal operation) disable" "No,Yes" bitfld.long 0x0C 30. " CLKGATE ,Gate clocks to the block" "Not gated,Gated" bitfld.long 0x0C 0. " ENABLE ,LTS operation with specified parameters enable" "Disabled,Enabled" line.long 0x10 "IRQ_MASK_SET/CLR,IRQ Mask Set/Clear Register" setclrfld.long 0x10 3. 0x14 3. 0x18 3. " M_AXI_ERR_EN ,LTS engine M_AXI error interrupt detection enable" "Disabled,Enabled" setclrfld.long 0x10 2. 0x14 2. 0x18 2. " S_AXI_ERR_EN ,LTS engine S_AXI error interrupt detection enable" "Disabled,Enabled" setclrfld.long 0x10 1. 0x14 1. 0x18 1. " LTS_DONE_IRQ_EN ,LTS engine done interrupt detection enable" "Disabled,Enabled" setclrfld.long 0x10 0. 0x14 0. 0x18 0. " LTS_START_IRQ_EN ,LTS engine start interrupt detection enable" "Disabled,Enabled" line.long 0x1C "IRQ_MASK_TOG,IRQ Mask TOG Register" bitfld.long 0x1C 3. " M_AXI_ERR_EN ,LTS engine M_AXI error interrupt detection enable" "Disabled,Enabled" bitfld.long 0x1C 2. " S_AXI_ERR_EN ,LTS engine S_AXI error interrupt detection enable" "Disabled,Enabled" bitfld.long 0x1C 1. " LTS_DONE_IRQ_EN ,LTS engine done interrupt detection enable" "Disabled,Enabled" bitfld.long 0x1C 0. " LTS_START_IRQ_EN ,LTS engine start interrupt detection enable" "Disabled,Enabled" line.long 0x20 "IRQ_STAT_SET/CLR,IRQ State Set/Clear Register" setclrfld.long 0x20 3. 0x24 3. 0x28 3. " M_AXI_ERROR ,LTS engine M_AXI error interrupt detection enable" "Disabled,Enabled" setclrfld.long 0x20 2. 0x24 2. 0x28 2. " S_AXI_ERROR ,LTS engine S_AXI error interrupt detection enable" "Disabled,Enabled" setclrfld.long 0x20 1. 0x24 1. 0x28 1. " LTS_DONE_IRQ ,LTS engine done interrupt detection enable" "Disabled,Enabled" setclrfld.long 0x20 0. 0x24 0. 0x28 0. " LTS_START_IRQ ,LTS engine start interrupt detection enable" "Disabled,Enabled" line.long 0x2C "IRQ_STAT_TOG,IRQ State TOG Register" bitfld.long 0x2C 3. " M_AXI_ERROR ,LTS engine M_AXI error interrupt detection enable" "Disabled,Enabled" bitfld.long 0x2C 2. " S_AXI_ERROR ,LTS engine S_AXI error interrupt detection enable" "Disabled,Enabled" bitfld.long 0x2C 1. " LTS_DONE_IRQ ,LTS engine done interrupt detection enable" "Disabled,Enabled" bitfld.long 0x2C 0. " LTS_START_IRQ ,LTS engine start interrupt detection enable" "Disabled,Enabled" line.long 0x30 "BUF,BUF Base Address Register" line.long 0x34 "BUF_SET,Base Address Set Register" line.long 0x38 "BUF_CLR,Base Address Clear Register" line.long 0x3C "BUF_TOG,Base Address TOG Register" line.long 0x40 "BUS_CTRL_SET/CLR,Bus Control Set/Clear Register" setclrfld.long 0x40 16. 0x44 16. 0x48 16. " AXI_LEN ,Burst length used on AXI interface" "8,16" setclrfld.long 0x40 0. 0x44 0. 0x48 0. " TILE_FORMAT ,Tile format output [bit pixels]" "32,16" line.long 0x4C "BUS_TOG,Bus Control TOG Register" bitfld.long 0x4C 16. " AXI_LEN ,Burst length used on AXI interface" "8,16" bitfld.long 0x4C 0. " TILE_FORMAT ,Tile format output [bit pixels]" "32,16" line.long 0x50 "SIZE,Size Control Register" hexmask.long.word 0x50 16.--29. 1. " HEIGHT ,Height" hexmask.long.word 0x50 0.--13. 1. " WIDTH ,Width" line.long 0x54 "SIZE_SET,Size Control Set Register" hexmask.long.word 0x54 16.--29. 1. " HEIGHT ,Height" hexmask.long.word 0x54 0.--13. 1. " WIDTH ,Width" line.long 0x58 "SIZE_CLR,Size Control Clear Register" hexmask.long.word 0x58 16.--29. 1. " HEIGHT ,Height" hexmask.long.word 0x58 0.--13. 1. " WIDTH ,Width" line.long 0x5C "SIZE_TOG,Size Control TOG Register" hexmask.long.word 0x5C 16.--29. 1. " HEIGHT ,Height" hexmask.long.word 0x5C 0.--13. 1. " WIDTH ,Width" line.long 0x60 "OFFSET,Offset Control Register" hexmask.long.word 0x60 16.--30. 0x01 " Y_OFFSET ,Buffer horizontal offset(X)" hexmask.long.word 0x60 0.--14. 0x01 " X_OFFSET ,Buffer vertical offset(Y)" line.long 0x64 "OFFSET_SET,Offset Control Set Register" hexmask.long.word 0x64 16.--30. 0x01 " Y_OFFSET ,Buffer horizontal offset(X)" hexmask.long.word 0x64 0.--14. 0x01 " X_OFFSET ,Buffer vertical offset(Y)" line.long 0x68 "OFFSET_CLR,Offset Control Clear Register" hexmask.long.word 0x68 16.--30. 0x01 " Y_OFFSET ,Buffer horizontal offset(X)" hexmask.long.word 0x68 0.--14. 0x01 " X_OFFSET ,Buffer vertical offset(Y)" line.long 0x6C "OFFSET_TOG,Offset Control TOG Register" hexmask.long.word 0x6C 16.--30. 0x01 " Y_OFFSET ,Buffer horizontal offset(X)" hexmask.long.word 0x6C 0.--14. 0x01 " X_OFFSET ,Buffer vertical offset(Y)" line.long 0x70 "PITCH,Pitch Control Register" line.long 0x74 "PITCH_SET,Pitch Control Set Register" line.long 0x78 "PITCH_CLR,Pitch Control Clear Register" line.long 0x7C "PITCH_TOG,Pitch Control TOG Register" rgroup.long 0x80++0x0F line.long 0x00 "VERSION,Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,RTL major version value" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,RTL minor version value" hexmask.long.word 0x00 0.--15. 1. " STEP ,RTL step version value" line.long 0x04 "VERSION_SET,Version Set Register" hexmask.long.byte 0x04 24.--31. 1. " MAJOR ,RTL major version value" hexmask.long.byte 0x04 16.--23. 1. " MINOR ,RTL minor version value" hexmask.long.word 0x04 0.--15. 1. " STEP ,RTL step version value" line.long 0x08 "VERSION_CLR,Version Clear Register" hexmask.long.byte 0x08 24.--31. 1. " MAJOR ,RTL major version value" hexmask.long.byte 0x08 16.--23. 1. " MINOR ,RTL minor version value" hexmask.long.word 0x08 0.--15. 1. " STEP ,RTL step version value" line.long 0x0C "VERSION_TOG,Version TOG Register" hexmask.long.byte 0x0C 24.--31. 1. " MAJOR ,RTL major version value" hexmask.long.byte 0x0C 16.--23. 1. " MINOR ,RTL minor version value" hexmask.long.word 0x0C 0.--15. 1. " STEP ,RTL step version value" group.long 0x90++0x0F line.long 0x00 "DEBUG_CTRL,Debug Control Register" bitfld.long 0x00 0.--3. " SELECT ,LTS debug register index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DEBUG_CTRL_SET,Debug Control Set Register" bitfld.long 0x04 0.--3. " SELECT ,LTS debug register index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DEBUG_CTRL_CLR,Debug Control Clear Register" bitfld.long 0x08 0.--3. " SELECT ,LTS debug register index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "DEBUG_CTRL_TOG,Debug Control TOG Register" bitfld.long 0x0C 0.--3. " SELECT ,LTS debug register index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xA0++0x0F line.long 0x00 "DEBUG,Debug Data Register" line.long 0x04 "DEBUG_SET,Debug Data Set Register" line.long 0x08 "DEBUG_CLR,Debug Data Clear Register" line.long 0x0C "DEBUG_TOG,Debug Data TOG Register" width 0x0B tree.end tree.open "DPR0 (Display Prefetch Resolve 0)" tree "Channel 0" base ad:0x560D0000 width 30. group.long 0x00++0x0F line.long 0x00 "SYSTEM_CTRL0_SET/CLR,System Control Set/Clear Register" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " BCMD2AXI_MSTR_ID_CTRL ,BUSCMD to AXI master ID control" "Unique,Same" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " SW_SHADOW_LOAD_SEL ,Software shadow load select" "Hardware signal,SHADOW_LOAD_EN" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " SHADOW_LOAD_EN ,Shadow load enable" "Disabled,Enabled" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " REPEAT_EN ,Repeat enable" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SOFT_RESET ,Soft reset" "No reset,Reset" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RUN_EN ,Run enable" "Disabled,Enabled" line.long 0x0C "SYSTEM_CTRL0_TOG,System Control TOG Register" bitfld.long 0x0C 16. " BCMD2AXI_MSTR_ID_CTRL ,BUSCMD to AXI master ID control" "Unique,Same" bitfld.long 0x0C 4. " SW_SHADOW_LOAD_SEL ,Software shadow load select" "Hardware signal,SHADOW_LOAD_EN" newline bitfld.long 0x0C 3. " SHADOW_LOAD_EN ,Shadow load enable" "Disabled,Enabled" bitfld.long 0x0C 2. " REPEAT_EN ,Repeat enable" "Disabled,Enabled" newline bitfld.long 0x0C 1. " SOFT_RESET ,Soft reset" "No reset,Reset" bitfld.long 0x0C 0. " RUN_EN ,Run enable" "Disabled,Enabled" group.long 0x20++0x0F line.long 0x00 "IRQ_MASK_SET/CLR,Interrupt Mask Set/Clear Register" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready IRQ error mask" "No error,Error" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready IRQ error mask" "No error,Error" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow IRQ mask" "No interrupt,Interrupt" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow IRQ mask" "No interrupt,Interrupt" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " IRQ_AXI_READ_ERROR ,AXI read error IRQ mask" "No interrupt,Interrupt" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " IRQ_DPR_SHADOW_LOADED_MASK ,DPR shadow loaded IRQ mask" "No interrupt,Interrupt" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " IRQ_DPR_RUN ,DPR run IRQ mask" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " IRQ_DPR_CTRL_DONE ,DPR control done IRQ mask" "No interrupt,Interrupt" line.long 0x0C "IRQ_MASK_TOG,Interrupt Mask TOG Register" bitfld.long 0x0C 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready IRQ error mask" "No interrupt,Interrupt" bitfld.long 0x0C 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready IRQ error mask" "No interrupt,Interrupt" newline bitfld.long 0x0C 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow IRQ mask" "No interrupt,Interrupt" bitfld.long 0x0C 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow IRQ mask" "No interrupt,Interrupt" newline bitfld.long 0x0C 3. " IRQ_AXI_READ_ERROR ,AXI read error IRQ mask" "No interrupt,Interrupt" bitfld.long 0x0C 2. " IRQ_DPR_SHADOW_LOADED_MASK ,DPR shadow loaded IRQ mask" "No interrupt,Interrupt" newline bitfld.long 0x0C 1. " IRQ_DPR_RUN ,DPR run IRQ mask" "No interrupt,Interrupt" bitfld.long 0x0C 0. " IRQ_DPR_CTRL_DONE ,DPR control done IRQ mask" "No interrupt,Interrupt" rgroup.long 0x30++0x0F line.long 0x00 "IRQ_MASK_STATUS_SET/CLR,Masked IRQ Status Set/Clear Register" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer error masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer error masked IRQ" "No interrupt,Interrupt" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow masked IRQ" "No interrupt,Interrupt" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " IRQ_AXI_READ_ERROR ,AXI read error masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " IRQ_DPR_SHADOW_LOADED ,DPR shadow loaded masked IRQ" "No interrupt,Interrupt" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " IRQ_DPR_RUN ,DPR run masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " IRQ_DPR_CTRL_DONE ,DPR control done masked IRQ" "No interrupt,Interrupt" line.long 0x0C "IRQ_MASK_STATUS_TOG,Masked IRQ Status TOG Register" bitfld.long 0x0C 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer error masked IRQ" "No interrupt,Interrupt" bitfld.long 0x0C 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer error masked IRQ" "No interrupt,Interrupt" newline bitfld.long 0x0C 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow masked IRQ" "No interrupt,Interrupt" bitfld.long 0x0C 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow masked IRQ" "No interrupt,Interrupt" newline bitfld.long 0x0C 3. " IRQ_AXI_READ_ERROR ,AXI read error masked IRQ" "No interrupt,Interrupt" bitfld.long 0x0C 2. " IRQ_DPR_SHADOW_LOADED ,DPR shadow loaded masked IRQ" "No interrupt,Interrupt" newline bitfld.long 0x0C 1. " IRQ_DPR_RUN ,DPR run masked IRQ" "No interrupt,Interrupt" bitfld.long 0x0C 0. " IRQ_DPR_CTRL_DONE ,DPR control done masked IRQ" "No interrupt,Interrupt" group.long 0x40++0x1F line.long 0x00 "IRQ_NONMASK_STATUS,Non-Masked IRQ Status Register" eventfld.long 0x00 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready error non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x00 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x00 3. " IRQ_AXI_READ_ERROR ,AXI read error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 2. " IRQ_DPR_SHADOW_LOADED_NMSTAT ,DPR shadow loaded non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x00 1. " IRQ_DPR_RUN ,DPR run non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 0. " IRQ_DPR_CTRL_DONE ,DPR control done non-masked IRQ" "No interrupt,Interrupt" line.long 0x04 "IRQ_NONMASK_STATUS_SET,Non-Masked IRQ Status Set Register" eventfld.long 0x04 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x04 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready error non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x04 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x04 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x04 3. " IRQ_AXI_READ_ERROR ,AXI read error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x04 2. " IRQ_DPR_SHADOW_LOADED_NMSTAT ,DPR shadow loaded non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x04 1. " IRQ_DPR_RUN ,DPR run non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x04 0. " IRQ_DPR_CTRL_DONE ,DPR control done non-masked IRQ" "No interrupt,Interrupt" line.long 0x08 "IRQ_NONMASK_STATUS_CLR,Non-Masked IRQ Status Clear Register" eventfld.long 0x08 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x08 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready error non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x08 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x08 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x08 3. " IRQ_AXI_READ_ERROR ,AXI read error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x08 2. " IRQ_DPR_SHADOW_LOADED_NMSTAT ,DPR shadow loaded non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x08 1. " IRQ_DPR_RUN ,DPR run non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x08 0. " IRQ_DPR_CTRL_DONE ,DPR control done non-masked IRQ" "No interrupt,Interrupt" line.long 0x0C "IRQ_NONMASK_STATUS_TOG,Non-Masked IRQ Status TOG Register" eventfld.long 0x0C 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x0C 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready error non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x0C 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x0C 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x0C 3. " IRQ_AXI_READ_ERROR ,AXI read error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x0C 2. " IRQ_DPR_SHADOW_LOADED_NMSTAT ,DPR shadow loaded non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x0C 1. " IRQ_DPR_RUN ,DPR run non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x0C 0. " IRQ_DPR_CTRL_DONE ,DPR control done non-masked IRQ" "No interrupt,Interrupt" newline line.long 0x10 "MODE_CTRL0,Mode Control Register" bitfld.long 0x10 16.--17. " A_COMP_SEL ,Alpha component byte select" "0,1,2,3" bitfld.long 0x10 14.--15. " R_COMP_SEL ,Red component byte select" "0,1,2,3" bitfld.long 0x10 12.--13. " G_COMP_SEL ,Green component byte select" "0,1,2,3" bitfld.long 0x10 10.--11. " B_COMP_SEL ,Blue component byte select" "0,1,2,3" newline bitfld.long 0x10 9. " PIX_UV_SWAP ,Pixel UV swap" "UV,VU" bitfld.long 0x10 8. " PIX_LUMA_UV_SWAP ,Pixel luma/UV position swap" "YUYV,UYVY" bitfld.long 0x10 6.--7. " PIX_SIZE ,Pixel size [bits]" "8,16,32,?..." bitfld.long 0x10 5. " COMP_2PLANE_EN ,Component 2-plane enable" "Disabled,Enabled" newline bitfld.long 0x10 4. " YUV_EN ,YUV enable" "Disabled,Enabled" bitfld.long 0x10 2.--3. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU" bitfld.long 0x10 1. " RTR_4LINE_BUF_EN ,RTRAM lines per buffer" "8,4" bitfld.long 0x10 0. " RTR_3BUF_EN ,RTRAM buffer implementation" "2,3" line.long 0x14 "MODE_CTRL0_SET,Mode Control Set Register" bitfld.long 0x14 16.--17. " A_COMP_SEL ,Alpha component byte select" "0,1,2,3" bitfld.long 0x14 14.--15. " R_COMP_SEL ,Red component byte select" "0,1,2,3" bitfld.long 0x14 12.--13. " G_COMP_SEL ,Green component byte select" "0,1,2,3" bitfld.long 0x14 10.--11. " B_COMP_SEL ,Blue component byte select" "0,1,2,3" newline bitfld.long 0x14 9. " PIX_UV_SWAP ,Pixel UV swap" "UV,VU" bitfld.long 0x14 8. " PIX_LUMA_UV_SWAP ,Pixel luma/UV position swap" "YUYV,UYVY" bitfld.long 0x14 6.--7. " PIX_SIZE ,Pixel size [bits]" "8,16,32,?..." bitfld.long 0x14 5. " COMP_2PLANE_EN ,Component 2-plane enable" "Disabled,Enabled" newline bitfld.long 0x14 4. " YUV_EN ,YUV enable" "Disabled,Enabled" bitfld.long 0x14 2.--3. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU" bitfld.long 0x14 1. " RTR_4LINE_BUF_EN ,RTRAM lines per buffer" "8,4" bitfld.long 0x14 0. " RTR_3BUF_EN ,RTRAM buffer implementation" "2,3" line.long 0x18 "MODE_CTRL0_CLR,Mode Control Clear Register" bitfld.long 0x18 16.--17. " A_COMP_SEL ,Alpha component byte select" "0,1,2,3" bitfld.long 0x18 14.--15. " R_COMP_SEL ,Red component byte select" "0,1,2,3" bitfld.long 0x18 12.--13. " G_COMP_SEL ,Green component byte select" "0,1,2,3" bitfld.long 0x18 10.--11. " B_COMP_SEL ,Blue component byte select" "0,1,2,3" newline bitfld.long 0x18 9. " PIX_UV_SWAP ,Pixel UV swap" "UV,VU" bitfld.long 0x18 8. " PIX_LUMA_UV_SWAP ,Pixel luma/UV position swap" "YUYV,UYVY" bitfld.long 0x18 6.--7. " PIX_SIZE ,Pixel size [bits]" "8,16,32,?..." bitfld.long 0x18 5. " COMP_2PLANE_EN ,Component 2-plane enable" "Disabled,Enabled" newline bitfld.long 0x18 4. " YUV_EN ,YUV enable" "Disabled,Enabled" bitfld.long 0x18 2.--3. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU" bitfld.long 0x18 1. " RTR_4LINE_BUF_EN ,RTRAM lines per buffer" "8,4" bitfld.long 0x18 0. " RTR_3BUF_EN ,RTRAM buffer implementation" "2,3" line.long 0x1C "MODE_CTRL0_TOG,Mode Control TOG Register" bitfld.long 0x1C 16.--17. " A_COMP_SEL ,Alpha component byte select" "0,1,2,3" bitfld.long 0x1C 14.--15. " R_COMP_SEL ,Red component byte select" "0,1,2,3" bitfld.long 0x1C 12.--13. " G_COMP_SEL ,Green component byte select" "0,1,2,3" bitfld.long 0x1C 10.--11. " B_COMP_SEL ,Blue component byte select" "0,1,2,3" newline bitfld.long 0x1C 9. " PIX_UV_SWAP ,Pixel UV swap" "UV,VU" bitfld.long 0x1C 8. " PIX_LUMA_UV_SWAP ,Pixel luma/UV position swap" "YUYV,UYVY" bitfld.long 0x1C 6.--7. " PIX_SIZE ,Pixel size [bits]" "8,16,32,?..." bitfld.long 0x1C 5. " COMP_2PLANE_EN ,Component 2-plane enable" "Disabled,Enabled" newline bitfld.long 0x1C 4. " YUV_EN ,YUV enable" "Disabled,Enabled" bitfld.long 0x1C 2.--3. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU" bitfld.long 0x1C 1. " RTR_4LINE_BUF_EN ,RTRAM lines per buffer" "8,4" bitfld.long 0x1C 0. " RTR_3BUF_EN ,RTRAM buffer implementation" "2,3" group.long 0x70++0x0F line.long 0x00 "FRAME_CTRL0,Frame Control Register" hexmask.long.word 0x00 16.--31. 1. " PITCH ,Image pitch" bitfld.long 0x00 4. " ROT_FLIP_OR_DER_EN ,Rotation horizontal/vertical flip order" "Rotate-flip,Flip-rotate" bitfld.long 0x00 2.--3. " ROT_ENC ,Encoded rotation [degrees]" "0,90,180,270" bitfld.long 0x00 1. " VFLIP_EN ,Vertical flip enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " HFLIP_EN ,Horizontal flip enable" "Disabled,Enabled" line.long 0x04 "FRAME_CTRL0_SET,Frame Control Set Register" hexmask.long.word 0x04 16.--31. 1. " PITCH ,Image pitch" bitfld.long 0x04 4. " ROT_FLIP_OR_DER_EN ,Rotation horizontal/vertical flip order" "Rotate-flip,Flip-rotate" bitfld.long 0x04 2.--3. " ROT_ENC ,Encoded rotation [degrees]" "0,90,180,270" bitfld.long 0x04 1. " VFLIP_EN ,Vertical flip enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " HFLIP_EN ,Horizontal flip enable" "Disabled,Enabled" line.long 0x08 "FRAME_CTRL0_CLR,Frame Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " PITCH ,Image pitch" bitfld.long 0x08 4. " ROT_FLIP_OR_DER_EN ,Rotation horizontal/vertical flip order" "Rotate-flip,Flip-rotate" bitfld.long 0x08 2.--3. " ROT_ENC ,Encoded rotation [degrees]" "0,90,180,270" bitfld.long 0x08 1. " VFLIP_EN ,Vertical flip enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " HFLIP_EN ,Horizontal flip enable" "Disabled,Enabled" line.long 0x0C "FRAME_CTRL0_TOG,Frame Control TOG Register" hexmask.long.word 0x0C 16.--31. 1. " PITCH ,Image pitch" bitfld.long 0x0C 4. " ROT_FLIP_OR_DER_EN ,Rotation horizontal/vertical flip order" "Rotate-flip,Flip-rotate" bitfld.long 0x0C 2.--3. " ROT_ENC ,Encoded rotation [degrees]" "0,90,180,270" bitfld.long 0x0C 1. " VFLIP_EN ,Vertical flip enable" "Disabled,Enabled" newline bitfld.long 0x0C 0. " HFLIP_EN ,Horizontal flip enable" "Disabled,Enabled" if (((per.l(ad:0x560D0000+0x50)&0x0C)==0x08)&&((per.l(ad:0x560D0000+0x50)&0xC0)==0x80)) group.long 0x90++0x0F line.long 0x00 "FRAME_1P_CTRL0,Frame 1-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x04 "FRAME_1P_CTRL0_SET,Frame 1-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x08 "FRAME_1P_CTRL0_CLR,Frame 1-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x0C "FRAME_1P_CTRL0_TOG,Frame 1-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." elif (((per.l(ad:0x560D0000+0x50)&0x0C)==0x0C)||((per.l(ad:0x560D0000+0x50)&0x0C)==0x08)&&((per.l(ad:0x560D0000+0x50)&0xC0)==0x40)||((per.l(ad:0x560D0000+0x70)&0x0C)==0x04)||((per.l(ad:0x560D0000+0x70)&0x0C)==0x0C)) group.long 0x90++0x0F line.long 0x00 "FRAME_1P_CTRL0,Frame 1-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x04 "FRAME_1P_CTRL0_SET,Frame 1-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x08 "FRAME_1P_CTRL0_CLR,Frame 1-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x0C "FRAME_1P_CTRL0_TOG,Frame 1-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." else group.long 0x90++0x0F line.long 0x00 "FRAME_1P_CTRL0,Frame 1-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x04 "FRAME_1P_CTRL0_SET,Frame 1-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x08 "FRAME_1P_CTRL0_CLR,Frame 1-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x0C "FRAME_1P_CTRL0_TOG,Frame 1-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." endif group.long 0xA0++0x2F line.long 0x00 "FRAME_1P_PIX_X_CTRL,Frame 1-Plane Pix X Control Register" hexmask.long.word 0x00 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x04 "FRAME_1P_PIX_X_CTRL_SET,Frame 1-Plane Pix X Control Set Register" hexmask.long.word 0x04 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x08 "FRAME_1P_PIX_X_CTRL_CLR,Frame 1-Plane Pix X Control Clear Register" hexmask.long.word 0x08 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x0C "FRAME_1P_PIX_X_CTRL_TOG,Frame 1-Plane Pix X Control TOG Register" hexmask.long.word 0x0C 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x10 "FRAME_1P_PIX_Y_CTRL,Frame 1-Plane Pix Y Control Register" hexmask.long.word 0x10 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x14 "FRAME_1P_PIX_Y_CTRL_SET,Frame 1-Plane Pix Y Control Set Register" hexmask.long.word 0x14 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x18 "FRAME_1P_PIX_Y_CTRL_CLR,Frame 1-Plane Pix Y Control Clear Register" hexmask.long.word 0x18 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x1C "FRAME_1P_PIX_Y_CTRL_TOG,Frame 1-Plane Pix Y Control TOG Register" hexmask.long.word 0x1C 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x20 "FRAME_1P_BASE_ADDR_CTRL0,Frame 1-Plane Base Address Control Register" line.long 0x24 "FRAME_1P_BASE_ADDR_CTRL0_SET,Frame 1-Plane Base Address Control Set Register" line.long 0x28 "FRAME_1P_BASE_ADDR_CTRL0_CLR,Frame 1-Plane Base Address Control Clear Register" line.long 0x2C "FRAME_1P_BASE_ADDR_CTRL0_TOG,Frame 1-Plane Base Address Control TOG Register" if (((per.l(ad:0x560D0000+0x50)&0x0C)==0x08)&&((per.l(ad:0x560D0000+0x50)&0xC0)==0x80)) group.long 0xE0++0x0F line.long 0x00 "FRAME_2P_CTRL0,Frame 2-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x04 "FRAME_2P_CTRL0_SET,Frame 2-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x08 "FRAME_2P_CTRL0_CLR,Frame 2-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x0C "FRAME_2P_CTRL0_TOG,Frame 2-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." elif (((per.l(ad:0x560D0000+0x50)&0x0C)==0x0C)||((per.l(ad:0x560D0000+0x50)&0x0C)==0x08)&&((per.l(ad:0x560D0000+0x50)&0xC0)==0x40)||((per.l(ad:0x560D0000+0x70)&0x0C)==0x04)||((per.l(ad:0x560D0000+0x70)&0x0C)==0x0C)) group.long 0xE0++0x0F line.long 0x00 "FRAME_2P_CTRL0,Frame 2-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x04 "FRAME_2P_CTRL0_SET,Frame 2-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x08 "FRAME_2P_CTRL0_CLR,Frame 2-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x0C "FRAME_2P_CTRL0_TOG,Frame 2-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." else group.long 0xE0++0x0F line.long 0x00 "FRAME_2P_CTRL0,Frame 2-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x04 "FRAME_2P_CTRL0_SET,Frame 2-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x08 "FRAME_2P_CTRL0_CLR,Frame 2-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x0C "FRAME_2P_CTRL0_TOG,Frame 2-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." endif group.long 0xF0++0x2F line.long 0x00 "FRAME_PIX_X_ULC_CTRL,Frame Pixel X Upper Left Coordinate Control Register" hexmask.long.word 0x00 0.--15. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" line.long 0x04 "FRAME_PIX_X_ULC_CTRL_SET,Frame Pixel X Upper Left Coordinate Set Control Register" hexmask.long.word 0x04 0.--15. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" line.long 0x08 "FRAME_PIX_X_ULC_CTRL_CLR,Frame Pixel X Upper Left Coordinate Clear Control Register" hexmask.long.word 0x08 0.--15. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" line.long 0x0C "FRAME_PIX_X_ULC_CTRL_TOG,Frame Pixel X Upper Left Coordinate TOG Control Register" hexmask.long.word 0x0C 0.--15. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" line.long 0x10 "FRAME_PIX_Y_ULC_CTRL,Frame Pixel Y Upper Left Coordinate Control Register" hexmask.long.word 0x10 0.--15. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y" line.long 0x14 "FRAME_PIX_Y_ULC_CTRL_SET,Frame Pixel Y Upper Left Coordinate Control Set Register" hexmask.long.word 0x14 0.--15. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y" line.long 0x18 "FRAME_PIX_Y_ULC_CTRL_CLR,Frame Pixel Y Upper Left Coordinate Control Clear Register" hexmask.long.word 0x18 0.--15. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y" line.long 0x1C "FRAME_PIX_Y_ULC_CTRL_TOG,Frame Pixel Y Upper Left Coordinate Control TOG Register" hexmask.long.word 0x1C 0.--15. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y" line.long 0x20 "FRAME_2P_BASE_ADDR_CTRL0,Frame 2-Plane Base Address Control Register" line.long 0x24 "FRAME_2P_BASE_ADDR_CTRL0_SET,Frame 2-Plane Base Address Control Set Register" line.long 0x28 "FRAME_2P_BASE_ADDR_CTRL0_CLR,Frame 2-Plane Base Address Control Clear Register" line.long 0x2C "FRAME_2P_BASE_ADDR_CTRL0_TOG,Frame 2-Plane Base Address Control TOG Register" group.long 0x130++0x0F line.long 0x00 "STATUS_CTRL0,Status Control Register" bitfld.long 0x00 16.--18. " STATUS_SRC_SEL ,Status source select" "DPR_CTRL,Prefetch YRGB/Y,Response YRGB/Y,Prefetch UV,Response UV,?..." bitfld.long 0x00 0.--2. " STATUS_MUX_SEL ,Status mux select" "0,1,2,3,4,5,6,7" line.long 0x04 "STATUS_CTRL0_SET,Status Control Set Register" bitfld.long 0x04 16.--18. " STATUS_SRC_SEL ,Status source select" "DPR_CTRL,Prefetch YRGB/Y,Response YRGB/Y,Prefetch UV,Response UV,?..." bitfld.long 0x04 0.--2. " STATUS_MUX_SEL ,Status mux select" "0,1,2,3,4,5,6,7" line.long 0x08 "STATUS_CTRL0_CLR,Status Control Clear Register" bitfld.long 0x08 16.--18. " STATUS_SRC_SEL ,Status source select" "DPR_CTRL,Prefetch YRGB/Y,Response YRGB/Y,Prefetch UV,Response UV,?..." bitfld.long 0x08 0.--2. " STATUS_MUX_SEL ,Status mux select" "0,1,2,3,4,5,6,7" line.long 0x0C "STATUS_CTRL0_TOG,Status Control TOG Register" bitfld.long 0x0C 16.--18. " STATUS_SRC_SEL ,Status source select" "DPR_CTRL,Prefetch YRGB/Y,Response YRGB/Y,Prefetch UV,Response UV,?..." bitfld.long 0x0C 0.--2. " STATUS_MUX_SEL ,Status mux select" "0,1,2,3,4,5,6,7" newline rgroup.long 0x140++0x0F line.long 0x00 "STATUS_CTRL1_SET/CLR,Status Control Set/Clear Register" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " STATUS[31] ,Internal DPR status/debug signal bit 31" "0,1" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [30] ,Internal DPR status/debug signal bit 30" "0,1" setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,Internal DPR status/debug signal bit 29" "0,1" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,Internal DPR status/debug signal bit 28" "0,1" setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,Internal DPR status/debug signal bit 27" "0,1" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,Internal DPR status/debug signal bit 26" "0,1" setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,Internal DPR status/debug signal bit 25" "0,1" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,Internal DPR status/debug signal bit 24" "0,1" setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,Internal DPR status/debug signal bit 23" "0,1" setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,Internal DPR status/debug signal bit 22" "0,1" setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,Internal DPR status/debug signal bit 21" "0,1" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,Internal DPR status/debug signal bit 20" "0,1" setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,Internal DPR status/debug signal bit 19" "0,1" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,Internal DPR status/debug signal bit 18" "0,1" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,Internal DPR status/debug signal bit 17" "0,1" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,Internal DPR status/debug signal bit 16" "0,1" newline setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,Internal DPR status/debug signal bit 15" "0,1" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,Internal DPR status/debug signal bit 14" "0,1" setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,Internal DPR status/debug signal bit 13" "0,1" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,Internal DPR status/debug signal bit 12" "0,1" setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,Internal DPR status/debug signal bit 11" "0,1" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,Internal DPR status/debug signal bit 10" "0,1" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,Internal DPR status/debug signal bit 9" "0,1" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,Internal DPR status/debug signal bit 8" "0,1" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,Internal DPR status/debug signal bit 7" "0,1" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,Internal DPR status/debug signal bit 6" "0,1" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,Internal DPR status/debug signal bit 5" "0,1" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,Internal DPR status/debug signal bit 4" "0,1" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Internal DPR status/debug signal bit 3" "0,1" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Internal DPR status/debug signal bit 2" "0,1" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Internal DPR status/debug signal bit 1" "0,1" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Internal DPR status/debug signal bit 0" "0,1" line.long 0x0C "STATUS_CTRL1_TOG,Status Control TOG Register" bitfld.long 0x0C 31. " STATUS[31] ,Internal DPR status/debug signal bit 31" "0,1" bitfld.long 0x0C 30. " [30] ,Internal DPR status/debug signal bit 30" "0,1" bitfld.long 0x0C 29. " [29] ,Internal DPR status/debug signal bit 29" "0,1" bitfld.long 0x0C 28. " [28] ,Internal DPR status/debug signal bit 28" "0,1" bitfld.long 0x0C 27. " [27] ,Internal DPR status/debug signal bit 27" "0,1" bitfld.long 0x0C 26. " [26] ,Internal DPR status/debug signal bit 26" "0,1" bitfld.long 0x0C 25. " [25] ,Internal DPR status/debug signal bit 25" "0,1" bitfld.long 0x0C 24. " [24] ,Internal DPR status/debug signal bit 24" "0,1" bitfld.long 0x0C 23. " [23] ,Internal DPR status/debug signal bit 23" "0,1" bitfld.long 0x0C 22. " [22] ,Internal DPR status/debug signal bit 22" "0,1" bitfld.long 0x0C 21. " [21] ,Internal DPR status/debug signal bit 21" "0,1" bitfld.long 0x0C 20. " [20] ,Internal DPR status/debug signal bit 20" "0,1" bitfld.long 0x0C 19. " [19] ,Internal DPR status/debug signal bit 19" "0,1" bitfld.long 0x0C 18. " [18] ,Internal DPR status/debug signal bit 18" "0,1" bitfld.long 0x0C 17. " [17] ,Internal DPR status/debug signal bit 17" "0,1" bitfld.long 0x0C 16. " [16] ,Internal DPR status/debug signal bit 16" "0,1" newline bitfld.long 0x0C 15. " [15] ,Internal DPR status/debug signal bit 15" "0,1" bitfld.long 0x0C 14. " [14] ,Internal DPR status/debug signal bit 14" "0,1" bitfld.long 0x0C 13. " [13] ,Internal DPR status/debug signal bit 13" "0,1" bitfld.long 0x0C 12. " [12] ,Internal DPR status/debug signal bit 12" "0,1" bitfld.long 0x0C 11. " [11] ,Internal DPR status/debug signal bit 11" "0,1" bitfld.long 0x0C 10. " [10] ,Internal DPR status/debug signal bit 10" "0,1" bitfld.long 0x0C 9. " [9] ,Internal DPR status/debug signal bit 9" "0,1" bitfld.long 0x0C 8. " [8] ,Internal DPR status/debug signal bit 8" "0,1" bitfld.long 0x0C 7. " [7] ,Internal DPR status/debug signal bit 7" "0,1" bitfld.long 0x0C 6. " [6] ,Internal DPR status/debug signal bit 6" "0,1" bitfld.long 0x0C 5. " [5] ,Internal DPR status/debug signal bit 5" "0,1" bitfld.long 0x0C 4. " [4] ,Internal DPR status/debug signal bit 4" "0,1" bitfld.long 0x0C 3. " [3] ,Internal DPR status/debug signal bit 3" "0,1" bitfld.long 0x0C 2. " [2] ,Internal DPR status/debug signal bit 2" "0,1" bitfld.long 0x0C 1. " [1] ,Internal DPR status/debug signal bit 1" "0,1" bitfld.long 0x0C 0. " [0] ,Internal DPR status/debug signal bit 0" "0,1" newline group.long 0x200++0x0F line.long 0x00 "RTRAM_CTRL0,RTRAM Control Register" bitfld.long 0x00 7. " ABORT_SEL ,Abort select" "STALL,ABORT" bitfld.long 0x00 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " NUM_ROWS_ACTIVE ,Number of rows active" "0-4,0-6(all)" line.long 0x04 "RTRAM_CTRL0_SET,RTRAM Control Set Register" bitfld.long 0x04 7. " ABORT_SEL ,Abort select" "STALL,ABORT" bitfld.long 0x04 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x04 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0. " NUM_ROWS_ACTIVE ,Number of rows active" "0-4,0-6(all)" line.long 0x08 "RTRAM_CTRL0_CLR,RTRAM Control Clear Register" bitfld.long 0x08 7. " ABORT_SEL ,Abort select" "STALL,ABORT" bitfld.long 0x08 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x08 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. " NUM_ROWS_ACTIVE ,Number of rows active" "0-4,0-6(all)" line.long 0x0C "RTRAM_CTRL0_TOG,RTRAM Control TOG Register" bitfld.long 0x0C 7. " ABORT_SEL ,Abort select" "STALL,ABORT" bitfld.long 0x0C 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0. " NUM_ROWS_ACTIVE ,Number of rows active" "0-4,0-6(all)" width 0x0B tree.end tree "Channel 1" base ad:0x560E0000 width 30. group.long 0x00++0x0F line.long 0x00 "SYSTEM_CTRL0_SET/CLR,System Control Set/Clear Register" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " BCMD2AXI_MSTR_ID_CTRL ,BUSCMD to AXI master ID control" "Unique,Same" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " SW_SHADOW_LOAD_SEL ,Software shadow load select" "Hardware signal,SHADOW_LOAD_EN" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " SHADOW_LOAD_EN ,Shadow load enable" "Disabled,Enabled" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " REPEAT_EN ,Repeat enable" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SOFT_RESET ,Soft reset" "No reset,Reset" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RUN_EN ,Run enable" "Disabled,Enabled" line.long 0x0C "SYSTEM_CTRL0_TOG,System Control TOG Register" bitfld.long 0x0C 16. " BCMD2AXI_MSTR_ID_CTRL ,BUSCMD to AXI master ID control" "Unique,Same" bitfld.long 0x0C 4. " SW_SHADOW_LOAD_SEL ,Software shadow load select" "Hardware signal,SHADOW_LOAD_EN" newline bitfld.long 0x0C 3. " SHADOW_LOAD_EN ,Shadow load enable" "Disabled,Enabled" bitfld.long 0x0C 2. " REPEAT_EN ,Repeat enable" "Disabled,Enabled" newline bitfld.long 0x0C 1. " SOFT_RESET ,Soft reset" "No reset,Reset" bitfld.long 0x0C 0. " RUN_EN ,Run enable" "Disabled,Enabled" group.long 0x20++0x0F line.long 0x00 "IRQ_MASK_SET/CLR,Interrupt Mask Set/Clear Register" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready IRQ error mask" "No error,Error" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready IRQ error mask" "No error,Error" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow IRQ mask" "No interrupt,Interrupt" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow IRQ mask" "No interrupt,Interrupt" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " IRQ_AXI_READ_ERROR ,AXI read error IRQ mask" "No interrupt,Interrupt" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " IRQ_DPR_SHADOW_LOADED_MASK ,DPR shadow loaded IRQ mask" "No interrupt,Interrupt" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " IRQ_DPR_RUN ,DPR run IRQ mask" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " IRQ_DPR_CTRL_DONE ,DPR control done IRQ mask" "No interrupt,Interrupt" line.long 0x0C "IRQ_MASK_TOG,Interrupt Mask TOG Register" bitfld.long 0x0C 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready IRQ error mask" "No interrupt,Interrupt" bitfld.long 0x0C 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready IRQ error mask" "No interrupt,Interrupt" newline bitfld.long 0x0C 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow IRQ mask" "No interrupt,Interrupt" bitfld.long 0x0C 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow IRQ mask" "No interrupt,Interrupt" newline bitfld.long 0x0C 3. " IRQ_AXI_READ_ERROR ,AXI read error IRQ mask" "No interrupt,Interrupt" bitfld.long 0x0C 2. " IRQ_DPR_SHADOW_LOADED_MASK ,DPR shadow loaded IRQ mask" "No interrupt,Interrupt" newline bitfld.long 0x0C 1. " IRQ_DPR_RUN ,DPR run IRQ mask" "No interrupt,Interrupt" bitfld.long 0x0C 0. " IRQ_DPR_CTRL_DONE ,DPR control done IRQ mask" "No interrupt,Interrupt" rgroup.long 0x30++0x0F line.long 0x00 "IRQ_MASK_STATUS_SET/CLR,Masked IRQ Status Set/Clear Register" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer error masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer error masked IRQ" "No interrupt,Interrupt" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow masked IRQ" "No interrupt,Interrupt" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " IRQ_AXI_READ_ERROR ,AXI read error masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " IRQ_DPR_SHADOW_LOADED ,DPR shadow loaded masked IRQ" "No interrupt,Interrupt" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " IRQ_DPR_RUN ,DPR run masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " IRQ_DPR_CTRL_DONE ,DPR control done masked IRQ" "No interrupt,Interrupt" line.long 0x0C "IRQ_MASK_STATUS_TOG,Masked IRQ Status TOG Register" bitfld.long 0x0C 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer error masked IRQ" "No interrupt,Interrupt" bitfld.long 0x0C 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer error masked IRQ" "No interrupt,Interrupt" newline bitfld.long 0x0C 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow masked IRQ" "No interrupt,Interrupt" bitfld.long 0x0C 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow masked IRQ" "No interrupt,Interrupt" newline bitfld.long 0x0C 3. " IRQ_AXI_READ_ERROR ,AXI read error masked IRQ" "No interrupt,Interrupt" bitfld.long 0x0C 2. " IRQ_DPR_SHADOW_LOADED ,DPR shadow loaded masked IRQ" "No interrupt,Interrupt" newline bitfld.long 0x0C 1. " IRQ_DPR_RUN ,DPR run masked IRQ" "No interrupt,Interrupt" bitfld.long 0x0C 0. " IRQ_DPR_CTRL_DONE ,DPR control done masked IRQ" "No interrupt,Interrupt" group.long 0x40++0x1F line.long 0x00 "IRQ_NONMASK_STATUS,Non-Masked IRQ Status Register" eventfld.long 0x00 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready error non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x00 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x00 3. " IRQ_AXI_READ_ERROR ,AXI read error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 2. " IRQ_DPR_SHADOW_LOADED_NMSTAT ,DPR shadow loaded non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x00 1. " IRQ_DPR_RUN ,DPR run non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 0. " IRQ_DPR_CTRL_DONE ,DPR control done non-masked IRQ" "No interrupt,Interrupt" line.long 0x04 "IRQ_NONMASK_STATUS_SET,Non-Masked IRQ Status Set Register" eventfld.long 0x04 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x04 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready error non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x04 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x04 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x04 3. " IRQ_AXI_READ_ERROR ,AXI read error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x04 2. " IRQ_DPR_SHADOW_LOADED_NMSTAT ,DPR shadow loaded non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x04 1. " IRQ_DPR_RUN ,DPR run non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x04 0. " IRQ_DPR_CTRL_DONE ,DPR control done non-masked IRQ" "No interrupt,Interrupt" line.long 0x08 "IRQ_NONMASK_STATUS_CLR,Non-Masked IRQ Status Clear Register" eventfld.long 0x08 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x08 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready error non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x08 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x08 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x08 3. " IRQ_AXI_READ_ERROR ,AXI read error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x08 2. " IRQ_DPR_SHADOW_LOADED_NMSTAT ,DPR shadow loaded non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x08 1. " IRQ_DPR_RUN ,DPR run non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x08 0. " IRQ_DPR_CTRL_DONE ,DPR control done non-masked IRQ" "No interrupt,Interrupt" line.long 0x0C "IRQ_NONMASK_STATUS_TOG,Non-Masked IRQ Status TOG Register" eventfld.long 0x0C 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x0C 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready error non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x0C 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x0C 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x0C 3. " IRQ_AXI_READ_ERROR ,AXI read error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x0C 2. " IRQ_DPR_SHADOW_LOADED_NMSTAT ,DPR shadow loaded non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x0C 1. " IRQ_DPR_RUN ,DPR run non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x0C 0. " IRQ_DPR_CTRL_DONE ,DPR control done non-masked IRQ" "No interrupt,Interrupt" newline line.long 0x10 "MODE_CTRL0,Mode Control Register" bitfld.long 0x10 16.--17. " A_COMP_SEL ,Alpha component byte select" "0,1,2,3" bitfld.long 0x10 14.--15. " R_COMP_SEL ,Red component byte select" "0,1,2,3" bitfld.long 0x10 12.--13. " G_COMP_SEL ,Green component byte select" "0,1,2,3" bitfld.long 0x10 10.--11. " B_COMP_SEL ,Blue component byte select" "0,1,2,3" newline bitfld.long 0x10 9. " PIX_UV_SWAP ,Pixel UV swap" "UV,VU" bitfld.long 0x10 8. " PIX_LUMA_UV_SWAP ,Pixel luma/UV position swap" "YUYV,UYVY" bitfld.long 0x10 6.--7. " PIX_SIZE ,Pixel size [bits]" "8,16,32,?..." bitfld.long 0x10 5. " COMP_2PLANE_EN ,Component 2-plane enable" "Disabled,Enabled" newline bitfld.long 0x10 4. " YUV_EN ,YUV enable" "Disabled,Enabled" bitfld.long 0x10 2.--3. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU" bitfld.long 0x10 1. " RTR_4LINE_BUF_EN ,RTRAM lines per buffer" "8,4" bitfld.long 0x10 0. " RTR_3BUF_EN ,RTRAM buffer implementation" "2,3" line.long 0x14 "MODE_CTRL0_SET,Mode Control Set Register" bitfld.long 0x14 16.--17. " A_COMP_SEL ,Alpha component byte select" "0,1,2,3" bitfld.long 0x14 14.--15. " R_COMP_SEL ,Red component byte select" "0,1,2,3" bitfld.long 0x14 12.--13. " G_COMP_SEL ,Green component byte select" "0,1,2,3" bitfld.long 0x14 10.--11. " B_COMP_SEL ,Blue component byte select" "0,1,2,3" newline bitfld.long 0x14 9. " PIX_UV_SWAP ,Pixel UV swap" "UV,VU" bitfld.long 0x14 8. " PIX_LUMA_UV_SWAP ,Pixel luma/UV position swap" "YUYV,UYVY" bitfld.long 0x14 6.--7. " PIX_SIZE ,Pixel size [bits]" "8,16,32,?..." bitfld.long 0x14 5. " COMP_2PLANE_EN ,Component 2-plane enable" "Disabled,Enabled" newline bitfld.long 0x14 4. " YUV_EN ,YUV enable" "Disabled,Enabled" bitfld.long 0x14 2.--3. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU" bitfld.long 0x14 1. " RTR_4LINE_BUF_EN ,RTRAM lines per buffer" "8,4" bitfld.long 0x14 0. " RTR_3BUF_EN ,RTRAM buffer implementation" "2,3" line.long 0x18 "MODE_CTRL0_CLR,Mode Control Clear Register" bitfld.long 0x18 16.--17. " A_COMP_SEL ,Alpha component byte select" "0,1,2,3" bitfld.long 0x18 14.--15. " R_COMP_SEL ,Red component byte select" "0,1,2,3" bitfld.long 0x18 12.--13. " G_COMP_SEL ,Green component byte select" "0,1,2,3" bitfld.long 0x18 10.--11. " B_COMP_SEL ,Blue component byte select" "0,1,2,3" newline bitfld.long 0x18 9. " PIX_UV_SWAP ,Pixel UV swap" "UV,VU" bitfld.long 0x18 8. " PIX_LUMA_UV_SWAP ,Pixel luma/UV position swap" "YUYV,UYVY" bitfld.long 0x18 6.--7. " PIX_SIZE ,Pixel size [bits]" "8,16,32,?..." bitfld.long 0x18 5. " COMP_2PLANE_EN ,Component 2-plane enable" "Disabled,Enabled" newline bitfld.long 0x18 4. " YUV_EN ,YUV enable" "Disabled,Enabled" bitfld.long 0x18 2.--3. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU" bitfld.long 0x18 1. " RTR_4LINE_BUF_EN ,RTRAM lines per buffer" "8,4" bitfld.long 0x18 0. " RTR_3BUF_EN ,RTRAM buffer implementation" "2,3" line.long 0x1C "MODE_CTRL0_TOG,Mode Control TOG Register" bitfld.long 0x1C 16.--17. " A_COMP_SEL ,Alpha component byte select" "0,1,2,3" bitfld.long 0x1C 14.--15. " R_COMP_SEL ,Red component byte select" "0,1,2,3" bitfld.long 0x1C 12.--13. " G_COMP_SEL ,Green component byte select" "0,1,2,3" bitfld.long 0x1C 10.--11. " B_COMP_SEL ,Blue component byte select" "0,1,2,3" newline bitfld.long 0x1C 9. " PIX_UV_SWAP ,Pixel UV swap" "UV,VU" bitfld.long 0x1C 8. " PIX_LUMA_UV_SWAP ,Pixel luma/UV position swap" "YUYV,UYVY" bitfld.long 0x1C 6.--7. " PIX_SIZE ,Pixel size [bits]" "8,16,32,?..." bitfld.long 0x1C 5. " COMP_2PLANE_EN ,Component 2-plane enable" "Disabled,Enabled" newline bitfld.long 0x1C 4. " YUV_EN ,YUV enable" "Disabled,Enabled" bitfld.long 0x1C 2.--3. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU" bitfld.long 0x1C 1. " RTR_4LINE_BUF_EN ,RTRAM lines per buffer" "8,4" bitfld.long 0x1C 0. " RTR_3BUF_EN ,RTRAM buffer implementation" "2,3" group.long 0x70++0x0F line.long 0x00 "FRAME_CTRL0,Frame Control Register" hexmask.long.word 0x00 16.--31. 1. " PITCH ,Image pitch" bitfld.long 0x00 4. " ROT_FLIP_OR_DER_EN ,Rotation horizontal/vertical flip order" "Rotate-flip,Flip-rotate" bitfld.long 0x00 2.--3. " ROT_ENC ,Encoded rotation [degrees]" "0,90,180,270" bitfld.long 0x00 1. " VFLIP_EN ,Vertical flip enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " HFLIP_EN ,Horizontal flip enable" "Disabled,Enabled" line.long 0x04 "FRAME_CTRL0_SET,Frame Control Set Register" hexmask.long.word 0x04 16.--31. 1. " PITCH ,Image pitch" bitfld.long 0x04 4. " ROT_FLIP_OR_DER_EN ,Rotation horizontal/vertical flip order" "Rotate-flip,Flip-rotate" bitfld.long 0x04 2.--3. " ROT_ENC ,Encoded rotation [degrees]" "0,90,180,270" bitfld.long 0x04 1. " VFLIP_EN ,Vertical flip enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " HFLIP_EN ,Horizontal flip enable" "Disabled,Enabled" line.long 0x08 "FRAME_CTRL0_CLR,Frame Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " PITCH ,Image pitch" bitfld.long 0x08 4. " ROT_FLIP_OR_DER_EN ,Rotation horizontal/vertical flip order" "Rotate-flip,Flip-rotate" bitfld.long 0x08 2.--3. " ROT_ENC ,Encoded rotation [degrees]" "0,90,180,270" bitfld.long 0x08 1. " VFLIP_EN ,Vertical flip enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " HFLIP_EN ,Horizontal flip enable" "Disabled,Enabled" line.long 0x0C "FRAME_CTRL0_TOG,Frame Control TOG Register" hexmask.long.word 0x0C 16.--31. 1. " PITCH ,Image pitch" bitfld.long 0x0C 4. " ROT_FLIP_OR_DER_EN ,Rotation horizontal/vertical flip order" "Rotate-flip,Flip-rotate" bitfld.long 0x0C 2.--3. " ROT_ENC ,Encoded rotation [degrees]" "0,90,180,270" bitfld.long 0x0C 1. " VFLIP_EN ,Vertical flip enable" "Disabled,Enabled" newline bitfld.long 0x0C 0. " HFLIP_EN ,Horizontal flip enable" "Disabled,Enabled" if (((per.l(ad:0x560E0000+0x50)&0x0C)==0x08)&&((per.l(ad:0x560E0000+0x50)&0xC0)==0x80)) group.long 0x90++0x0F line.long 0x00 "FRAME_1P_CTRL0,Frame 1-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x04 "FRAME_1P_CTRL0_SET,Frame 1-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x08 "FRAME_1P_CTRL0_CLR,Frame 1-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x0C "FRAME_1P_CTRL0_TOG,Frame 1-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." elif (((per.l(ad:0x560E0000+0x50)&0x0C)==0x0C)||((per.l(ad:0x560E0000+0x50)&0x0C)==0x08)&&((per.l(ad:0x560E0000+0x50)&0xC0)==0x40)||((per.l(ad:0x560E0000+0x70)&0x0C)==0x04)||((per.l(ad:0x560E0000+0x70)&0x0C)==0x0C)) group.long 0x90++0x0F line.long 0x00 "FRAME_1P_CTRL0,Frame 1-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x04 "FRAME_1P_CTRL0_SET,Frame 1-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x08 "FRAME_1P_CTRL0_CLR,Frame 1-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x0C "FRAME_1P_CTRL0_TOG,Frame 1-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." else group.long 0x90++0x0F line.long 0x00 "FRAME_1P_CTRL0,Frame 1-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x04 "FRAME_1P_CTRL0_SET,Frame 1-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x08 "FRAME_1P_CTRL0_CLR,Frame 1-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x0C "FRAME_1P_CTRL0_TOG,Frame 1-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." endif group.long 0xA0++0x2F line.long 0x00 "FRAME_1P_PIX_X_CTRL,Frame 1-Plane Pix X Control Register" hexmask.long.word 0x00 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x04 "FRAME_1P_PIX_X_CTRL_SET,Frame 1-Plane Pix X Control Set Register" hexmask.long.word 0x04 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x08 "FRAME_1P_PIX_X_CTRL_CLR,Frame 1-Plane Pix X Control Clear Register" hexmask.long.word 0x08 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x0C "FRAME_1P_PIX_X_CTRL_TOG,Frame 1-Plane Pix X Control TOG Register" hexmask.long.word 0x0C 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x10 "FRAME_1P_PIX_Y_CTRL,Frame 1-Plane Pix Y Control Register" hexmask.long.word 0x10 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x14 "FRAME_1P_PIX_Y_CTRL_SET,Frame 1-Plane Pix Y Control Set Register" hexmask.long.word 0x14 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x18 "FRAME_1P_PIX_Y_CTRL_CLR,Frame 1-Plane Pix Y Control Clear Register" hexmask.long.word 0x18 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x1C "FRAME_1P_PIX_Y_CTRL_TOG,Frame 1-Plane Pix Y Control TOG Register" hexmask.long.word 0x1C 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x20 "FRAME_1P_BASE_ADDR_CTRL0,Frame 1-Plane Base Address Control Register" line.long 0x24 "FRAME_1P_BASE_ADDR_CTRL0_SET,Frame 1-Plane Base Address Control Set Register" line.long 0x28 "FRAME_1P_BASE_ADDR_CTRL0_CLR,Frame 1-Plane Base Address Control Clear Register" line.long 0x2C "FRAME_1P_BASE_ADDR_CTRL0_TOG,Frame 1-Plane Base Address Control TOG Register" if (((per.l(ad:0x560E0000+0x50)&0x0C)==0x08)&&((per.l(ad:0x560E0000+0x50)&0xC0)==0x80)) group.long 0xE0++0x0F line.long 0x00 "FRAME_2P_CTRL0,Frame 2-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x04 "FRAME_2P_CTRL0_SET,Frame 2-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x08 "FRAME_2P_CTRL0_CLR,Frame 2-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x0C "FRAME_2P_CTRL0_TOG,Frame 2-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." elif (((per.l(ad:0x560E0000+0x50)&0x0C)==0x0C)||((per.l(ad:0x560E0000+0x50)&0x0C)==0x08)&&((per.l(ad:0x560E0000+0x50)&0xC0)==0x40)||((per.l(ad:0x560E0000+0x70)&0x0C)==0x04)||((per.l(ad:0x560E0000+0x70)&0x0C)==0x0C)) group.long 0xE0++0x0F line.long 0x00 "FRAME_2P_CTRL0,Frame 2-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x04 "FRAME_2P_CTRL0_SET,Frame 2-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x08 "FRAME_2P_CTRL0_CLR,Frame 2-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x0C "FRAME_2P_CTRL0_TOG,Frame 2-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." else group.long 0xE0++0x0F line.long 0x00 "FRAME_2P_CTRL0,Frame 2-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x04 "FRAME_2P_CTRL0_SET,Frame 2-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x08 "FRAME_2P_CTRL0_CLR,Frame 2-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x0C "FRAME_2P_CTRL0_TOG,Frame 2-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." endif group.long 0xF0++0x2F line.long 0x00 "FRAME_PIX_X_ULC_CTRL,Frame Pixel X Upper Left Coordinate Control Register" hexmask.long.word 0x00 0.--15. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" line.long 0x04 "FRAME_PIX_X_ULC_CTRL_SET,Frame Pixel X Upper Left Coordinate Set Control Register" hexmask.long.word 0x04 0.--15. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" line.long 0x08 "FRAME_PIX_X_ULC_CTRL_CLR,Frame Pixel X Upper Left Coordinate Clear Control Register" hexmask.long.word 0x08 0.--15. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" line.long 0x0C "FRAME_PIX_X_ULC_CTRL_TOG,Frame Pixel X Upper Left Coordinate TOG Control Register" hexmask.long.word 0x0C 0.--15. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" line.long 0x10 "FRAME_PIX_Y_ULC_CTRL,Frame Pixel Y Upper Left Coordinate Control Register" hexmask.long.word 0x10 0.--15. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y" line.long 0x14 "FRAME_PIX_Y_ULC_CTRL_SET,Frame Pixel Y Upper Left Coordinate Control Set Register" hexmask.long.word 0x14 0.--15. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y" line.long 0x18 "FRAME_PIX_Y_ULC_CTRL_CLR,Frame Pixel Y Upper Left Coordinate Control Clear Register" hexmask.long.word 0x18 0.--15. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y" line.long 0x1C "FRAME_PIX_Y_ULC_CTRL_TOG,Frame Pixel Y Upper Left Coordinate Control TOG Register" hexmask.long.word 0x1C 0.--15. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y" line.long 0x20 "FRAME_2P_BASE_ADDR_CTRL0,Frame 2-Plane Base Address Control Register" line.long 0x24 "FRAME_2P_BASE_ADDR_CTRL0_SET,Frame 2-Plane Base Address Control Set Register" line.long 0x28 "FRAME_2P_BASE_ADDR_CTRL0_CLR,Frame 2-Plane Base Address Control Clear Register" line.long 0x2C "FRAME_2P_BASE_ADDR_CTRL0_TOG,Frame 2-Plane Base Address Control TOG Register" group.long 0x130++0x0F line.long 0x00 "STATUS_CTRL0,Status Control Register" bitfld.long 0x00 16.--18. " STATUS_SRC_SEL ,Status source select" "DPR_CTRL,Prefetch YRGB/Y,Response YRGB/Y,Prefetch UV,Response UV,?..." bitfld.long 0x00 0.--2. " STATUS_MUX_SEL ,Status mux select" "0,1,2,3,4,5,6,7" line.long 0x04 "STATUS_CTRL0_SET,Status Control Set Register" bitfld.long 0x04 16.--18. " STATUS_SRC_SEL ,Status source select" "DPR_CTRL,Prefetch YRGB/Y,Response YRGB/Y,Prefetch UV,Response UV,?..." bitfld.long 0x04 0.--2. " STATUS_MUX_SEL ,Status mux select" "0,1,2,3,4,5,6,7" line.long 0x08 "STATUS_CTRL0_CLR,Status Control Clear Register" bitfld.long 0x08 16.--18. " STATUS_SRC_SEL ,Status source select" "DPR_CTRL,Prefetch YRGB/Y,Response YRGB/Y,Prefetch UV,Response UV,?..." bitfld.long 0x08 0.--2. " STATUS_MUX_SEL ,Status mux select" "0,1,2,3,4,5,6,7" line.long 0x0C "STATUS_CTRL0_TOG,Status Control TOG Register" bitfld.long 0x0C 16.--18. " STATUS_SRC_SEL ,Status source select" "DPR_CTRL,Prefetch YRGB/Y,Response YRGB/Y,Prefetch UV,Response UV,?..." bitfld.long 0x0C 0.--2. " STATUS_MUX_SEL ,Status mux select" "0,1,2,3,4,5,6,7" newline rgroup.long 0x140++0x0F line.long 0x00 "STATUS_CTRL1_SET/CLR,Status Control Set/Clear Register" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " STATUS[31] ,Internal DPR status/debug signal bit 31" "0,1" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [30] ,Internal DPR status/debug signal bit 30" "0,1" setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,Internal DPR status/debug signal bit 29" "0,1" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,Internal DPR status/debug signal bit 28" "0,1" setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,Internal DPR status/debug signal bit 27" "0,1" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,Internal DPR status/debug signal bit 26" "0,1" setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,Internal DPR status/debug signal bit 25" "0,1" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,Internal DPR status/debug signal bit 24" "0,1" setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,Internal DPR status/debug signal bit 23" "0,1" setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,Internal DPR status/debug signal bit 22" "0,1" setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,Internal DPR status/debug signal bit 21" "0,1" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,Internal DPR status/debug signal bit 20" "0,1" setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,Internal DPR status/debug signal bit 19" "0,1" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,Internal DPR status/debug signal bit 18" "0,1" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,Internal DPR status/debug signal bit 17" "0,1" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,Internal DPR status/debug signal bit 16" "0,1" newline setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,Internal DPR status/debug signal bit 15" "0,1" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,Internal DPR status/debug signal bit 14" "0,1" setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,Internal DPR status/debug signal bit 13" "0,1" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,Internal DPR status/debug signal bit 12" "0,1" setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,Internal DPR status/debug signal bit 11" "0,1" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,Internal DPR status/debug signal bit 10" "0,1" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,Internal DPR status/debug signal bit 9" "0,1" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,Internal DPR status/debug signal bit 8" "0,1" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,Internal DPR status/debug signal bit 7" "0,1" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,Internal DPR status/debug signal bit 6" "0,1" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,Internal DPR status/debug signal bit 5" "0,1" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,Internal DPR status/debug signal bit 4" "0,1" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Internal DPR status/debug signal bit 3" "0,1" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Internal DPR status/debug signal bit 2" "0,1" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Internal DPR status/debug signal bit 1" "0,1" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Internal DPR status/debug signal bit 0" "0,1" line.long 0x0C "STATUS_CTRL1_TOG,Status Control TOG Register" bitfld.long 0x0C 31. " STATUS[31] ,Internal DPR status/debug signal bit 31" "0,1" bitfld.long 0x0C 30. " [30] ,Internal DPR status/debug signal bit 30" "0,1" bitfld.long 0x0C 29. " [29] ,Internal DPR status/debug signal bit 29" "0,1" bitfld.long 0x0C 28. " [28] ,Internal DPR status/debug signal bit 28" "0,1" bitfld.long 0x0C 27. " [27] ,Internal DPR status/debug signal bit 27" "0,1" bitfld.long 0x0C 26. " [26] ,Internal DPR status/debug signal bit 26" "0,1" bitfld.long 0x0C 25. " [25] ,Internal DPR status/debug signal bit 25" "0,1" bitfld.long 0x0C 24. " [24] ,Internal DPR status/debug signal bit 24" "0,1" bitfld.long 0x0C 23. " [23] ,Internal DPR status/debug signal bit 23" "0,1" bitfld.long 0x0C 22. " [22] ,Internal DPR status/debug signal bit 22" "0,1" bitfld.long 0x0C 21. " [21] ,Internal DPR status/debug signal bit 21" "0,1" bitfld.long 0x0C 20. " [20] ,Internal DPR status/debug signal bit 20" "0,1" bitfld.long 0x0C 19. " [19] ,Internal DPR status/debug signal bit 19" "0,1" bitfld.long 0x0C 18. " [18] ,Internal DPR status/debug signal bit 18" "0,1" bitfld.long 0x0C 17. " [17] ,Internal DPR status/debug signal bit 17" "0,1" bitfld.long 0x0C 16. " [16] ,Internal DPR status/debug signal bit 16" "0,1" newline bitfld.long 0x0C 15. " [15] ,Internal DPR status/debug signal bit 15" "0,1" bitfld.long 0x0C 14. " [14] ,Internal DPR status/debug signal bit 14" "0,1" bitfld.long 0x0C 13. " [13] ,Internal DPR status/debug signal bit 13" "0,1" bitfld.long 0x0C 12. " [12] ,Internal DPR status/debug signal bit 12" "0,1" bitfld.long 0x0C 11. " [11] ,Internal DPR status/debug signal bit 11" "0,1" bitfld.long 0x0C 10. " [10] ,Internal DPR status/debug signal bit 10" "0,1" bitfld.long 0x0C 9. " [9] ,Internal DPR status/debug signal bit 9" "0,1" bitfld.long 0x0C 8. " [8] ,Internal DPR status/debug signal bit 8" "0,1" bitfld.long 0x0C 7. " [7] ,Internal DPR status/debug signal bit 7" "0,1" bitfld.long 0x0C 6. " [6] ,Internal DPR status/debug signal bit 6" "0,1" bitfld.long 0x0C 5. " [5] ,Internal DPR status/debug signal bit 5" "0,1" bitfld.long 0x0C 4. " [4] ,Internal DPR status/debug signal bit 4" "0,1" bitfld.long 0x0C 3. " [3] ,Internal DPR status/debug signal bit 3" "0,1" bitfld.long 0x0C 2. " [2] ,Internal DPR status/debug signal bit 2" "0,1" bitfld.long 0x0C 1. " [1] ,Internal DPR status/debug signal bit 1" "0,1" bitfld.long 0x0C 0. " [0] ,Internal DPR status/debug signal bit 0" "0,1" newline group.long 0x200++0x0F line.long 0x00 "RTRAM_CTRL0,RTRAM Control Register" bitfld.long 0x00 7. " ABORT_SEL ,Abort select" "STALL,ABORT" bitfld.long 0x00 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " NUM_ROWS_ACTIVE ,Number of rows active" "0-4,0-6(all)" line.long 0x04 "RTRAM_CTRL0_SET,RTRAM Control Set Register" bitfld.long 0x04 7. " ABORT_SEL ,Abort select" "STALL,ABORT" bitfld.long 0x04 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x04 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0. " NUM_ROWS_ACTIVE ,Number of rows active" "0-4,0-6(all)" line.long 0x08 "RTRAM_CTRL0_CLR,RTRAM Control Clear Register" bitfld.long 0x08 7. " ABORT_SEL ,Abort select" "STALL,ABORT" bitfld.long 0x08 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x08 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. " NUM_ROWS_ACTIVE ,Number of rows active" "0-4,0-6(all)" line.long 0x0C "RTRAM_CTRL0_TOG,RTRAM Control TOG Register" bitfld.long 0x0C 7. " ABORT_SEL ,Abort select" "STALL,ABORT" bitfld.long 0x0C 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0. " NUM_ROWS_ACTIVE ,Number of rows active" "0-4,0-6(all)" width 0x0B tree.end tree "Channel 2" base ad:0x560F0000 width 30. group.long 0x00++0x0F line.long 0x00 "SYSTEM_CTRL0_SET/CLR,System Control Set/Clear Register" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " BCMD2AXI_MSTR_ID_CTRL ,BUSCMD to AXI master ID control" "Unique,Same" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " SW_SHADOW_LOAD_SEL ,Software shadow load select" "Hardware signal,SHADOW_LOAD_EN" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " SHADOW_LOAD_EN ,Shadow load enable" "Disabled,Enabled" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " REPEAT_EN ,Repeat enable" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SOFT_RESET ,Soft reset" "No reset,Reset" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RUN_EN ,Run enable" "Disabled,Enabled" line.long 0x0C "SYSTEM_CTRL0_TOG,System Control TOG Register" bitfld.long 0x0C 16. " BCMD2AXI_MSTR_ID_CTRL ,BUSCMD to AXI master ID control" "Unique,Same" bitfld.long 0x0C 4. " SW_SHADOW_LOAD_SEL ,Software shadow load select" "Hardware signal,SHADOW_LOAD_EN" newline bitfld.long 0x0C 3. " SHADOW_LOAD_EN ,Shadow load enable" "Disabled,Enabled" bitfld.long 0x0C 2. " REPEAT_EN ,Repeat enable" "Disabled,Enabled" newline bitfld.long 0x0C 1. " SOFT_RESET ,Soft reset" "No reset,Reset" bitfld.long 0x0C 0. " RUN_EN ,Run enable" "Disabled,Enabled" group.long 0x20++0x0F line.long 0x00 "IRQ_MASK_SET/CLR,Interrupt Mask Set/Clear Register" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready IRQ error mask" "No error,Error" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready IRQ error mask" "No error,Error" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow IRQ mask" "No interrupt,Interrupt" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow IRQ mask" "No interrupt,Interrupt" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " IRQ_AXI_READ_ERROR ,AXI read error IRQ mask" "No interrupt,Interrupt" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " IRQ_DPR_SHADOW_LOADED_MASK ,DPR shadow loaded IRQ mask" "No interrupt,Interrupt" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " IRQ_DPR_RUN ,DPR run IRQ mask" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " IRQ_DPR_CTRL_DONE ,DPR control done IRQ mask" "No interrupt,Interrupt" line.long 0x0C "IRQ_MASK_TOG,Interrupt Mask TOG Register" bitfld.long 0x0C 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready IRQ error mask" "No interrupt,Interrupt" bitfld.long 0x0C 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready IRQ error mask" "No interrupt,Interrupt" newline bitfld.long 0x0C 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow IRQ mask" "No interrupt,Interrupt" bitfld.long 0x0C 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow IRQ mask" "No interrupt,Interrupt" newline bitfld.long 0x0C 3. " IRQ_AXI_READ_ERROR ,AXI read error IRQ mask" "No interrupt,Interrupt" bitfld.long 0x0C 2. " IRQ_DPR_SHADOW_LOADED_MASK ,DPR shadow loaded IRQ mask" "No interrupt,Interrupt" newline bitfld.long 0x0C 1. " IRQ_DPR_RUN ,DPR run IRQ mask" "No interrupt,Interrupt" bitfld.long 0x0C 0. " IRQ_DPR_CTRL_DONE ,DPR control done IRQ mask" "No interrupt,Interrupt" rgroup.long 0x30++0x0F line.long 0x00 "IRQ_MASK_STATUS_SET/CLR,Masked IRQ Status Set/Clear Register" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer error masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer error masked IRQ" "No interrupt,Interrupt" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow masked IRQ" "No interrupt,Interrupt" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " IRQ_AXI_READ_ERROR ,AXI read error masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " IRQ_DPR_SHADOW_LOADED ,DPR shadow loaded masked IRQ" "No interrupt,Interrupt" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " IRQ_DPR_RUN ,DPR run masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " IRQ_DPR_CTRL_DONE ,DPR control done masked IRQ" "No interrupt,Interrupt" line.long 0x0C "IRQ_MASK_STATUS_TOG,Masked IRQ Status TOG Register" bitfld.long 0x0C 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer error masked IRQ" "No interrupt,Interrupt" bitfld.long 0x0C 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer error masked IRQ" "No interrupt,Interrupt" newline bitfld.long 0x0C 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow masked IRQ" "No interrupt,Interrupt" bitfld.long 0x0C 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow masked IRQ" "No interrupt,Interrupt" newline bitfld.long 0x0C 3. " IRQ_AXI_READ_ERROR ,AXI read error masked IRQ" "No interrupt,Interrupt" bitfld.long 0x0C 2. " IRQ_DPR_SHADOW_LOADED ,DPR shadow loaded masked IRQ" "No interrupt,Interrupt" newline bitfld.long 0x0C 1. " IRQ_DPR_RUN ,DPR run masked IRQ" "No interrupt,Interrupt" bitfld.long 0x0C 0. " IRQ_DPR_CTRL_DONE ,DPR control done masked IRQ" "No interrupt,Interrupt" group.long 0x40++0x1F line.long 0x00 "IRQ_NONMASK_STATUS,Non-Masked IRQ Status Register" eventfld.long 0x00 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready error non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x00 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x00 3. " IRQ_AXI_READ_ERROR ,AXI read error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 2. " IRQ_DPR_SHADOW_LOADED_NMSTAT ,DPR shadow loaded non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x00 1. " IRQ_DPR_RUN ,DPR run non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 0. " IRQ_DPR_CTRL_DONE ,DPR control done non-masked IRQ" "No interrupt,Interrupt" line.long 0x04 "IRQ_NONMASK_STATUS_SET,Non-Masked IRQ Status Set Register" eventfld.long 0x04 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x04 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready error non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x04 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x04 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x04 3. " IRQ_AXI_READ_ERROR ,AXI read error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x04 2. " IRQ_DPR_SHADOW_LOADED_NMSTAT ,DPR shadow loaded non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x04 1. " IRQ_DPR_RUN ,DPR run non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x04 0. " IRQ_DPR_CTRL_DONE ,DPR control done non-masked IRQ" "No interrupt,Interrupt" line.long 0x08 "IRQ_NONMASK_STATUS_CLR,Non-Masked IRQ Status Clear Register" eventfld.long 0x08 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x08 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready error non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x08 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x08 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x08 3. " IRQ_AXI_READ_ERROR ,AXI read error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x08 2. " IRQ_DPR_SHADOW_LOADED_NMSTAT ,DPR shadow loaded non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x08 1. " IRQ_DPR_RUN ,DPR run non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x08 0. " IRQ_DPR_CTRL_DONE ,DPR control done non-masked IRQ" "No interrupt,Interrupt" line.long 0x0C "IRQ_NONMASK_STATUS_TOG,Non-Masked IRQ Status TOG Register" eventfld.long 0x0C 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x0C 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready error non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x0C 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x0C 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x0C 3. " IRQ_AXI_READ_ERROR ,AXI read error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x0C 2. " IRQ_DPR_SHADOW_LOADED_NMSTAT ,DPR shadow loaded non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x0C 1. " IRQ_DPR_RUN ,DPR run non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x0C 0. " IRQ_DPR_CTRL_DONE ,DPR control done non-masked IRQ" "No interrupt,Interrupt" newline line.long 0x10 "MODE_CTRL0,Mode Control Register" bitfld.long 0x10 16.--17. " A_COMP_SEL ,Alpha component byte select" "0,1,2,3" bitfld.long 0x10 14.--15. " R_COMP_SEL ,Red component byte select" "0,1,2,3" bitfld.long 0x10 12.--13. " G_COMP_SEL ,Green component byte select" "0,1,2,3" bitfld.long 0x10 10.--11. " B_COMP_SEL ,Blue component byte select" "0,1,2,3" newline bitfld.long 0x10 9. " PIX_UV_SWAP ,Pixel UV swap" "UV,VU" bitfld.long 0x10 8. " PIX_LUMA_UV_SWAP ,Pixel luma/UV position swap" "YUYV,UYVY" bitfld.long 0x10 6.--7. " PIX_SIZE ,Pixel size [bits]" "8,16,32,?..." bitfld.long 0x10 5. " COMP_2PLANE_EN ,Component 2-plane enable" "Disabled,Enabled" newline bitfld.long 0x10 4. " YUV_EN ,YUV enable" "Disabled,Enabled" bitfld.long 0x10 2.--3. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU" bitfld.long 0x10 1. " RTR_4LINE_BUF_EN ,RTRAM lines per buffer" "8,4" bitfld.long 0x10 0. " RTR_3BUF_EN ,RTRAM buffer implementation" "2,3" line.long 0x14 "MODE_CTRL0_SET,Mode Control Set Register" bitfld.long 0x14 16.--17. " A_COMP_SEL ,Alpha component byte select" "0,1,2,3" bitfld.long 0x14 14.--15. " R_COMP_SEL ,Red component byte select" "0,1,2,3" bitfld.long 0x14 12.--13. " G_COMP_SEL ,Green component byte select" "0,1,2,3" bitfld.long 0x14 10.--11. " B_COMP_SEL ,Blue component byte select" "0,1,2,3" newline bitfld.long 0x14 9. " PIX_UV_SWAP ,Pixel UV swap" "UV,VU" bitfld.long 0x14 8. " PIX_LUMA_UV_SWAP ,Pixel luma/UV position swap" "YUYV,UYVY" bitfld.long 0x14 6.--7. " PIX_SIZE ,Pixel size [bits]" "8,16,32,?..." bitfld.long 0x14 5. " COMP_2PLANE_EN ,Component 2-plane enable" "Disabled,Enabled" newline bitfld.long 0x14 4. " YUV_EN ,YUV enable" "Disabled,Enabled" bitfld.long 0x14 2.--3. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU" bitfld.long 0x14 1. " RTR_4LINE_BUF_EN ,RTRAM lines per buffer" "8,4" bitfld.long 0x14 0. " RTR_3BUF_EN ,RTRAM buffer implementation" "2,3" line.long 0x18 "MODE_CTRL0_CLR,Mode Control Clear Register" bitfld.long 0x18 16.--17. " A_COMP_SEL ,Alpha component byte select" "0,1,2,3" bitfld.long 0x18 14.--15. " R_COMP_SEL ,Red component byte select" "0,1,2,3" bitfld.long 0x18 12.--13. " G_COMP_SEL ,Green component byte select" "0,1,2,3" bitfld.long 0x18 10.--11. " B_COMP_SEL ,Blue component byte select" "0,1,2,3" newline bitfld.long 0x18 9. " PIX_UV_SWAP ,Pixel UV swap" "UV,VU" bitfld.long 0x18 8. " PIX_LUMA_UV_SWAP ,Pixel luma/UV position swap" "YUYV,UYVY" bitfld.long 0x18 6.--7. " PIX_SIZE ,Pixel size [bits]" "8,16,32,?..." bitfld.long 0x18 5. " COMP_2PLANE_EN ,Component 2-plane enable" "Disabled,Enabled" newline bitfld.long 0x18 4. " YUV_EN ,YUV enable" "Disabled,Enabled" bitfld.long 0x18 2.--3. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU" bitfld.long 0x18 1. " RTR_4LINE_BUF_EN ,RTRAM lines per buffer" "8,4" bitfld.long 0x18 0. " RTR_3BUF_EN ,RTRAM buffer implementation" "2,3" line.long 0x1C "MODE_CTRL0_TOG,Mode Control TOG Register" bitfld.long 0x1C 16.--17. " A_COMP_SEL ,Alpha component byte select" "0,1,2,3" bitfld.long 0x1C 14.--15. " R_COMP_SEL ,Red component byte select" "0,1,2,3" bitfld.long 0x1C 12.--13. " G_COMP_SEL ,Green component byte select" "0,1,2,3" bitfld.long 0x1C 10.--11. " B_COMP_SEL ,Blue component byte select" "0,1,2,3" newline bitfld.long 0x1C 9. " PIX_UV_SWAP ,Pixel UV swap" "UV,VU" bitfld.long 0x1C 8. " PIX_LUMA_UV_SWAP ,Pixel luma/UV position swap" "YUYV,UYVY" bitfld.long 0x1C 6.--7. " PIX_SIZE ,Pixel size [bits]" "8,16,32,?..." bitfld.long 0x1C 5. " COMP_2PLANE_EN ,Component 2-plane enable" "Disabled,Enabled" newline bitfld.long 0x1C 4. " YUV_EN ,YUV enable" "Disabled,Enabled" bitfld.long 0x1C 2.--3. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU" bitfld.long 0x1C 1. " RTR_4LINE_BUF_EN ,RTRAM lines per buffer" "8,4" bitfld.long 0x1C 0. " RTR_3BUF_EN ,RTRAM buffer implementation" "2,3" group.long 0x70++0x0F line.long 0x00 "FRAME_CTRL0,Frame Control Register" hexmask.long.word 0x00 16.--31. 1. " PITCH ,Image pitch" bitfld.long 0x00 4. " ROT_FLIP_OR_DER_EN ,Rotation horizontal/vertical flip order" "Rotate-flip,Flip-rotate" bitfld.long 0x00 2.--3. " ROT_ENC ,Encoded rotation [degrees]" "0,90,180,270" bitfld.long 0x00 1. " VFLIP_EN ,Vertical flip enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " HFLIP_EN ,Horizontal flip enable" "Disabled,Enabled" line.long 0x04 "FRAME_CTRL0_SET,Frame Control Set Register" hexmask.long.word 0x04 16.--31. 1. " PITCH ,Image pitch" bitfld.long 0x04 4. " ROT_FLIP_OR_DER_EN ,Rotation horizontal/vertical flip order" "Rotate-flip,Flip-rotate" bitfld.long 0x04 2.--3. " ROT_ENC ,Encoded rotation [degrees]" "0,90,180,270" bitfld.long 0x04 1. " VFLIP_EN ,Vertical flip enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " HFLIP_EN ,Horizontal flip enable" "Disabled,Enabled" line.long 0x08 "FRAME_CTRL0_CLR,Frame Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " PITCH ,Image pitch" bitfld.long 0x08 4. " ROT_FLIP_OR_DER_EN ,Rotation horizontal/vertical flip order" "Rotate-flip,Flip-rotate" bitfld.long 0x08 2.--3. " ROT_ENC ,Encoded rotation [degrees]" "0,90,180,270" bitfld.long 0x08 1. " VFLIP_EN ,Vertical flip enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " HFLIP_EN ,Horizontal flip enable" "Disabled,Enabled" line.long 0x0C "FRAME_CTRL0_TOG,Frame Control TOG Register" hexmask.long.word 0x0C 16.--31. 1. " PITCH ,Image pitch" bitfld.long 0x0C 4. " ROT_FLIP_OR_DER_EN ,Rotation horizontal/vertical flip order" "Rotate-flip,Flip-rotate" bitfld.long 0x0C 2.--3. " ROT_ENC ,Encoded rotation [degrees]" "0,90,180,270" bitfld.long 0x0C 1. " VFLIP_EN ,Vertical flip enable" "Disabled,Enabled" newline bitfld.long 0x0C 0. " HFLIP_EN ,Horizontal flip enable" "Disabled,Enabled" if (((per.l(ad:0x560F0000+0x50)&0x0C)==0x08)&&((per.l(ad:0x560F0000+0x50)&0xC0)==0x80)) group.long 0x90++0x0F line.long 0x00 "FRAME_1P_CTRL0,Frame 1-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x04 "FRAME_1P_CTRL0_SET,Frame 1-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x08 "FRAME_1P_CTRL0_CLR,Frame 1-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x0C "FRAME_1P_CTRL0_TOG,Frame 1-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." elif (((per.l(ad:0x560F0000+0x50)&0x0C)==0x0C)||((per.l(ad:0x560F0000+0x50)&0x0C)==0x08)&&((per.l(ad:0x560F0000+0x50)&0xC0)==0x40)||((per.l(ad:0x560F0000+0x70)&0x0C)==0x04)||((per.l(ad:0x560F0000+0x70)&0x0C)==0x0C)) group.long 0x90++0x0F line.long 0x00 "FRAME_1P_CTRL0,Frame 1-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x04 "FRAME_1P_CTRL0_SET,Frame 1-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x08 "FRAME_1P_CTRL0_CLR,Frame 1-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x0C "FRAME_1P_CTRL0_TOG,Frame 1-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." else group.long 0x90++0x0F line.long 0x00 "FRAME_1P_CTRL0,Frame 1-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x04 "FRAME_1P_CTRL0_SET,Frame 1-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x08 "FRAME_1P_CTRL0_CLR,Frame 1-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x0C "FRAME_1P_CTRL0_TOG,Frame 1-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." endif group.long 0xA0++0x2F line.long 0x00 "FRAME_1P_PIX_X_CTRL,Frame 1-Plane Pix X Control Register" hexmask.long.word 0x00 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x04 "FRAME_1P_PIX_X_CTRL_SET,Frame 1-Plane Pix X Control Set Register" hexmask.long.word 0x04 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x08 "FRAME_1P_PIX_X_CTRL_CLR,Frame 1-Plane Pix X Control Clear Register" hexmask.long.word 0x08 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x0C "FRAME_1P_PIX_X_CTRL_TOG,Frame 1-Plane Pix X Control TOG Register" hexmask.long.word 0x0C 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x10 "FRAME_1P_PIX_Y_CTRL,Frame 1-Plane Pix Y Control Register" hexmask.long.word 0x10 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x14 "FRAME_1P_PIX_Y_CTRL_SET,Frame 1-Plane Pix Y Control Set Register" hexmask.long.word 0x14 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x18 "FRAME_1P_PIX_Y_CTRL_CLR,Frame 1-Plane Pix Y Control Clear Register" hexmask.long.word 0x18 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x1C "FRAME_1P_PIX_Y_CTRL_TOG,Frame 1-Plane Pix Y Control TOG Register" hexmask.long.word 0x1C 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x20 "FRAME_1P_BASE_ADDR_CTRL0,Frame 1-Plane Base Address Control Register" line.long 0x24 "FRAME_1P_BASE_ADDR_CTRL0_SET,Frame 1-Plane Base Address Control Set Register" line.long 0x28 "FRAME_1P_BASE_ADDR_CTRL0_CLR,Frame 1-Plane Base Address Control Clear Register" line.long 0x2C "FRAME_1P_BASE_ADDR_CTRL0_TOG,Frame 1-Plane Base Address Control TOG Register" if (((per.l(ad:0x560F0000+0x50)&0x0C)==0x08)&&((per.l(ad:0x560F0000+0x50)&0xC0)==0x80)) group.long 0xE0++0x0F line.long 0x00 "FRAME_2P_CTRL0,Frame 2-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x04 "FRAME_2P_CTRL0_SET,Frame 2-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x08 "FRAME_2P_CTRL0_CLR,Frame 2-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x0C "FRAME_2P_CTRL0_TOG,Frame 2-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." elif (((per.l(ad:0x560F0000+0x50)&0x0C)==0x0C)||((per.l(ad:0x560F0000+0x50)&0x0C)==0x08)&&((per.l(ad:0x560F0000+0x50)&0xC0)==0x40)||((per.l(ad:0x560F0000+0x70)&0x0C)==0x04)||((per.l(ad:0x560F0000+0x70)&0x0C)==0x0C)) group.long 0xE0++0x0F line.long 0x00 "FRAME_2P_CTRL0,Frame 2-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x04 "FRAME_2P_CTRL0_SET,Frame 2-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x08 "FRAME_2P_CTRL0_CLR,Frame 2-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x0C "FRAME_2P_CTRL0_TOG,Frame 2-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." else group.long 0xE0++0x0F line.long 0x00 "FRAME_2P_CTRL0,Frame 2-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x04 "FRAME_2P_CTRL0_SET,Frame 2-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x08 "FRAME_2P_CTRL0_CLR,Frame 2-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x0C "FRAME_2P_CTRL0_TOG,Frame 2-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." endif group.long 0xF0++0x2F line.long 0x00 "FRAME_PIX_X_ULC_CTRL,Frame Pixel X Upper Left Coordinate Control Register" hexmask.long.word 0x00 0.--15. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" line.long 0x04 "FRAME_PIX_X_ULC_CTRL_SET,Frame Pixel X Upper Left Coordinate Set Control Register" hexmask.long.word 0x04 0.--15. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" line.long 0x08 "FRAME_PIX_X_ULC_CTRL_CLR,Frame Pixel X Upper Left Coordinate Clear Control Register" hexmask.long.word 0x08 0.--15. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" line.long 0x0C "FRAME_PIX_X_ULC_CTRL_TOG,Frame Pixel X Upper Left Coordinate TOG Control Register" hexmask.long.word 0x0C 0.--15. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" line.long 0x10 "FRAME_PIX_Y_ULC_CTRL,Frame Pixel Y Upper Left Coordinate Control Register" hexmask.long.word 0x10 0.--15. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y" line.long 0x14 "FRAME_PIX_Y_ULC_CTRL_SET,Frame Pixel Y Upper Left Coordinate Control Set Register" hexmask.long.word 0x14 0.--15. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y" line.long 0x18 "FRAME_PIX_Y_ULC_CTRL_CLR,Frame Pixel Y Upper Left Coordinate Control Clear Register" hexmask.long.word 0x18 0.--15. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y" line.long 0x1C "FRAME_PIX_Y_ULC_CTRL_TOG,Frame Pixel Y Upper Left Coordinate Control TOG Register" hexmask.long.word 0x1C 0.--15. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y" line.long 0x20 "FRAME_2P_BASE_ADDR_CTRL0,Frame 2-Plane Base Address Control Register" line.long 0x24 "FRAME_2P_BASE_ADDR_CTRL0_SET,Frame 2-Plane Base Address Control Set Register" line.long 0x28 "FRAME_2P_BASE_ADDR_CTRL0_CLR,Frame 2-Plane Base Address Control Clear Register" line.long 0x2C "FRAME_2P_BASE_ADDR_CTRL0_TOG,Frame 2-Plane Base Address Control TOG Register" group.long 0x130++0x0F line.long 0x00 "STATUS_CTRL0,Status Control Register" bitfld.long 0x00 16.--18. " STATUS_SRC_SEL ,Status source select" "DPR_CTRL,Prefetch YRGB/Y,Response YRGB/Y,Prefetch UV,Response UV,?..." bitfld.long 0x00 0.--2. " STATUS_MUX_SEL ,Status mux select" "0,1,2,3,4,5,6,7" line.long 0x04 "STATUS_CTRL0_SET,Status Control Set Register" bitfld.long 0x04 16.--18. " STATUS_SRC_SEL ,Status source select" "DPR_CTRL,Prefetch YRGB/Y,Response YRGB/Y,Prefetch UV,Response UV,?..." bitfld.long 0x04 0.--2. " STATUS_MUX_SEL ,Status mux select" "0,1,2,3,4,5,6,7" line.long 0x08 "STATUS_CTRL0_CLR,Status Control Clear Register" bitfld.long 0x08 16.--18. " STATUS_SRC_SEL ,Status source select" "DPR_CTRL,Prefetch YRGB/Y,Response YRGB/Y,Prefetch UV,Response UV,?..." bitfld.long 0x08 0.--2. " STATUS_MUX_SEL ,Status mux select" "0,1,2,3,4,5,6,7" line.long 0x0C "STATUS_CTRL0_TOG,Status Control TOG Register" bitfld.long 0x0C 16.--18. " STATUS_SRC_SEL ,Status source select" "DPR_CTRL,Prefetch YRGB/Y,Response YRGB/Y,Prefetch UV,Response UV,?..." bitfld.long 0x0C 0.--2. " STATUS_MUX_SEL ,Status mux select" "0,1,2,3,4,5,6,7" newline rgroup.long 0x140++0x0F line.long 0x00 "STATUS_CTRL1_SET/CLR,Status Control Set/Clear Register" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " STATUS[31] ,Internal DPR status/debug signal bit 31" "0,1" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [30] ,Internal DPR status/debug signal bit 30" "0,1" setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,Internal DPR status/debug signal bit 29" "0,1" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,Internal DPR status/debug signal bit 28" "0,1" setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,Internal DPR status/debug signal bit 27" "0,1" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,Internal DPR status/debug signal bit 26" "0,1" setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,Internal DPR status/debug signal bit 25" "0,1" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,Internal DPR status/debug signal bit 24" "0,1" setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,Internal DPR status/debug signal bit 23" "0,1" setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,Internal DPR status/debug signal bit 22" "0,1" setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,Internal DPR status/debug signal bit 21" "0,1" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,Internal DPR status/debug signal bit 20" "0,1" setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,Internal DPR status/debug signal bit 19" "0,1" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,Internal DPR status/debug signal bit 18" "0,1" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,Internal DPR status/debug signal bit 17" "0,1" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,Internal DPR status/debug signal bit 16" "0,1" newline setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,Internal DPR status/debug signal bit 15" "0,1" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,Internal DPR status/debug signal bit 14" "0,1" setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,Internal DPR status/debug signal bit 13" "0,1" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,Internal DPR status/debug signal bit 12" "0,1" setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,Internal DPR status/debug signal bit 11" "0,1" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,Internal DPR status/debug signal bit 10" "0,1" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,Internal DPR status/debug signal bit 9" "0,1" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,Internal DPR status/debug signal bit 8" "0,1" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,Internal DPR status/debug signal bit 7" "0,1" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,Internal DPR status/debug signal bit 6" "0,1" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,Internal DPR status/debug signal bit 5" "0,1" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,Internal DPR status/debug signal bit 4" "0,1" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Internal DPR status/debug signal bit 3" "0,1" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Internal DPR status/debug signal bit 2" "0,1" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Internal DPR status/debug signal bit 1" "0,1" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Internal DPR status/debug signal bit 0" "0,1" line.long 0x0C "STATUS_CTRL1_TOG,Status Control TOG Register" bitfld.long 0x0C 31. " STATUS[31] ,Internal DPR status/debug signal bit 31" "0,1" bitfld.long 0x0C 30. " [30] ,Internal DPR status/debug signal bit 30" "0,1" bitfld.long 0x0C 29. " [29] ,Internal DPR status/debug signal bit 29" "0,1" bitfld.long 0x0C 28. " [28] ,Internal DPR status/debug signal bit 28" "0,1" bitfld.long 0x0C 27. " [27] ,Internal DPR status/debug signal bit 27" "0,1" bitfld.long 0x0C 26. " [26] ,Internal DPR status/debug signal bit 26" "0,1" bitfld.long 0x0C 25. " [25] ,Internal DPR status/debug signal bit 25" "0,1" bitfld.long 0x0C 24. " [24] ,Internal DPR status/debug signal bit 24" "0,1" bitfld.long 0x0C 23. " [23] ,Internal DPR status/debug signal bit 23" "0,1" bitfld.long 0x0C 22. " [22] ,Internal DPR status/debug signal bit 22" "0,1" bitfld.long 0x0C 21. " [21] ,Internal DPR status/debug signal bit 21" "0,1" bitfld.long 0x0C 20. " [20] ,Internal DPR status/debug signal bit 20" "0,1" bitfld.long 0x0C 19. " [19] ,Internal DPR status/debug signal bit 19" "0,1" bitfld.long 0x0C 18. " [18] ,Internal DPR status/debug signal bit 18" "0,1" bitfld.long 0x0C 17. " [17] ,Internal DPR status/debug signal bit 17" "0,1" bitfld.long 0x0C 16. " [16] ,Internal DPR status/debug signal bit 16" "0,1" newline bitfld.long 0x0C 15. " [15] ,Internal DPR status/debug signal bit 15" "0,1" bitfld.long 0x0C 14. " [14] ,Internal DPR status/debug signal bit 14" "0,1" bitfld.long 0x0C 13. " [13] ,Internal DPR status/debug signal bit 13" "0,1" bitfld.long 0x0C 12. " [12] ,Internal DPR status/debug signal bit 12" "0,1" bitfld.long 0x0C 11. " [11] ,Internal DPR status/debug signal bit 11" "0,1" bitfld.long 0x0C 10. " [10] ,Internal DPR status/debug signal bit 10" "0,1" bitfld.long 0x0C 9. " [9] ,Internal DPR status/debug signal bit 9" "0,1" bitfld.long 0x0C 8. " [8] ,Internal DPR status/debug signal bit 8" "0,1" bitfld.long 0x0C 7. " [7] ,Internal DPR status/debug signal bit 7" "0,1" bitfld.long 0x0C 6. " [6] ,Internal DPR status/debug signal bit 6" "0,1" bitfld.long 0x0C 5. " [5] ,Internal DPR status/debug signal bit 5" "0,1" bitfld.long 0x0C 4. " [4] ,Internal DPR status/debug signal bit 4" "0,1" bitfld.long 0x0C 3. " [3] ,Internal DPR status/debug signal bit 3" "0,1" bitfld.long 0x0C 2. " [2] ,Internal DPR status/debug signal bit 2" "0,1" bitfld.long 0x0C 1. " [1] ,Internal DPR status/debug signal bit 1" "0,1" bitfld.long 0x0C 0. " [0] ,Internal DPR status/debug signal bit 0" "0,1" newline group.long 0x200++0x0F line.long 0x00 "RTRAM_CTRL0,RTRAM Control Register" bitfld.long 0x00 7. " ABORT_SEL ,Abort select" "STALL,ABORT" bitfld.long 0x00 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " NUM_ROWS_ACTIVE ,Number of rows active" "0-4,0-6(all)" line.long 0x04 "RTRAM_CTRL0_SET,RTRAM Control Set Register" bitfld.long 0x04 7. " ABORT_SEL ,Abort select" "STALL,ABORT" bitfld.long 0x04 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x04 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0. " NUM_ROWS_ACTIVE ,Number of rows active" "0-4,0-6(all)" line.long 0x08 "RTRAM_CTRL0_CLR,RTRAM Control Clear Register" bitfld.long 0x08 7. " ABORT_SEL ,Abort select" "STALL,ABORT" bitfld.long 0x08 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x08 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. " NUM_ROWS_ACTIVE ,Number of rows active" "0-4,0-6(all)" line.long 0x0C "RTRAM_CTRL0_TOG,RTRAM Control TOG Register" bitfld.long 0x0C 7. " ABORT_SEL ,Abort select" "STALL,ABORT" bitfld.long 0x0C 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0. " NUM_ROWS_ACTIVE ,Number of rows active" "0-4,0-6(all)" width 0x0B tree.end tree.end tree.open "DPR1 (Display Prefetch Resolve 1)" tree "Channel 0" base ad:0x56100000 width 30. group.long 0x00++0x0F line.long 0x00 "SYSTEM_CTRL0_SET/CLR,System Control Set/Clear Register" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " BCMD2AXI_MSTR_ID_CTRL ,BUSCMD to AXI master ID control" "Unique,Same" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " SW_SHADOW_LOAD_SEL ,Software shadow load select" "Hardware signal,SHADOW_LOAD_EN" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " SHADOW_LOAD_EN ,Shadow load enable" "Disabled,Enabled" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " REPEAT_EN ,Repeat enable" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SOFT_RESET ,Soft reset" "No reset,Reset" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RUN_EN ,Run enable" "Disabled,Enabled" line.long 0x0C "SYSTEM_CTRL0_TOG,System Control TOG Register" bitfld.long 0x0C 16. " BCMD2AXI_MSTR_ID_CTRL ,BUSCMD to AXI master ID control" "Unique,Same" bitfld.long 0x0C 4. " SW_SHADOW_LOAD_SEL ,Software shadow load select" "Hardware signal,SHADOW_LOAD_EN" newline bitfld.long 0x0C 3. " SHADOW_LOAD_EN ,Shadow load enable" "Disabled,Enabled" bitfld.long 0x0C 2. " REPEAT_EN ,Repeat enable" "Disabled,Enabled" newline bitfld.long 0x0C 1. " SOFT_RESET ,Soft reset" "No reset,Reset" bitfld.long 0x0C 0. " RUN_EN ,Run enable" "Disabled,Enabled" group.long 0x20++0x0F line.long 0x00 "IRQ_MASK_SET/CLR,Interrupt Mask Set/Clear Register" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready IRQ error mask" "No error,Error" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready IRQ error mask" "No error,Error" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow IRQ mask" "No interrupt,Interrupt" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow IRQ mask" "No interrupt,Interrupt" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " IRQ_AXI_READ_ERROR ,AXI read error IRQ mask" "No interrupt,Interrupt" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " IRQ_DPR_SHADOW_LOADED_MASK ,DPR shadow loaded IRQ mask" "No interrupt,Interrupt" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " IRQ_DPR_RUN ,DPR run IRQ mask" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " IRQ_DPR_CTRL_DONE ,DPR control done IRQ mask" "No interrupt,Interrupt" line.long 0x0C "IRQ_MASK_TOG,Interrupt Mask TOG Register" bitfld.long 0x0C 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready IRQ error mask" "No interrupt,Interrupt" bitfld.long 0x0C 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready IRQ error mask" "No interrupt,Interrupt" newline bitfld.long 0x0C 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow IRQ mask" "No interrupt,Interrupt" bitfld.long 0x0C 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow IRQ mask" "No interrupt,Interrupt" newline bitfld.long 0x0C 3. " IRQ_AXI_READ_ERROR ,AXI read error IRQ mask" "No interrupt,Interrupt" bitfld.long 0x0C 2. " IRQ_DPR_SHADOW_LOADED_MASK ,DPR shadow loaded IRQ mask" "No interrupt,Interrupt" newline bitfld.long 0x0C 1. " IRQ_DPR_RUN ,DPR run IRQ mask" "No interrupt,Interrupt" bitfld.long 0x0C 0. " IRQ_DPR_CTRL_DONE ,DPR control done IRQ mask" "No interrupt,Interrupt" rgroup.long 0x30++0x0F line.long 0x00 "IRQ_MASK_STATUS_SET/CLR,Masked IRQ Status Set/Clear Register" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer error masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer error masked IRQ" "No interrupt,Interrupt" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow masked IRQ" "No interrupt,Interrupt" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " IRQ_AXI_READ_ERROR ,AXI read error masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " IRQ_DPR_SHADOW_LOADED ,DPR shadow loaded masked IRQ" "No interrupt,Interrupt" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " IRQ_DPR_RUN ,DPR run masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " IRQ_DPR_CTRL_DONE ,DPR control done masked IRQ" "No interrupt,Interrupt" line.long 0x0C "IRQ_MASK_STATUS_TOG,Masked IRQ Status TOG Register" bitfld.long 0x0C 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer error masked IRQ" "No interrupt,Interrupt" bitfld.long 0x0C 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer error masked IRQ" "No interrupt,Interrupt" newline bitfld.long 0x0C 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow masked IRQ" "No interrupt,Interrupt" bitfld.long 0x0C 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow masked IRQ" "No interrupt,Interrupt" newline bitfld.long 0x0C 3. " IRQ_AXI_READ_ERROR ,AXI read error masked IRQ" "No interrupt,Interrupt" bitfld.long 0x0C 2. " IRQ_DPR_SHADOW_LOADED ,DPR shadow loaded masked IRQ" "No interrupt,Interrupt" newline bitfld.long 0x0C 1. " IRQ_DPR_RUN ,DPR run masked IRQ" "No interrupt,Interrupt" bitfld.long 0x0C 0. " IRQ_DPR_CTRL_DONE ,DPR control done masked IRQ" "No interrupt,Interrupt" group.long 0x40++0x1F line.long 0x00 "IRQ_NONMASK_STATUS,Non-Masked IRQ Status Register" eventfld.long 0x00 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready error non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x00 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x00 3. " IRQ_AXI_READ_ERROR ,AXI read error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 2. " IRQ_DPR_SHADOW_LOADED_NMSTAT ,DPR shadow loaded non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x00 1. " IRQ_DPR_RUN ,DPR run non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 0. " IRQ_DPR_CTRL_DONE ,DPR control done non-masked IRQ" "No interrupt,Interrupt" line.long 0x04 "IRQ_NONMASK_STATUS_SET,Non-Masked IRQ Status Set Register" eventfld.long 0x04 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x04 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready error non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x04 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x04 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x04 3. " IRQ_AXI_READ_ERROR ,AXI read error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x04 2. " IRQ_DPR_SHADOW_LOADED_NMSTAT ,DPR shadow loaded non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x04 1. " IRQ_DPR_RUN ,DPR run non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x04 0. " IRQ_DPR_CTRL_DONE ,DPR control done non-masked IRQ" "No interrupt,Interrupt" line.long 0x08 "IRQ_NONMASK_STATUS_CLR,Non-Masked IRQ Status Clear Register" eventfld.long 0x08 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x08 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready error non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x08 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x08 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x08 3. " IRQ_AXI_READ_ERROR ,AXI read error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x08 2. " IRQ_DPR_SHADOW_LOADED_NMSTAT ,DPR shadow loaded non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x08 1. " IRQ_DPR_RUN ,DPR run non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x08 0. " IRQ_DPR_CTRL_DONE ,DPR control done non-masked IRQ" "No interrupt,Interrupt" line.long 0x0C "IRQ_NONMASK_STATUS_TOG,Non-Masked IRQ Status TOG Register" eventfld.long 0x0C 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x0C 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready error non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x0C 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x0C 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x0C 3. " IRQ_AXI_READ_ERROR ,AXI read error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x0C 2. " IRQ_DPR_SHADOW_LOADED_NMSTAT ,DPR shadow loaded non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x0C 1. " IRQ_DPR_RUN ,DPR run non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x0C 0. " IRQ_DPR_CTRL_DONE ,DPR control done non-masked IRQ" "No interrupt,Interrupt" newline line.long 0x10 "MODE_CTRL0,Mode Control Register" bitfld.long 0x10 16.--17. " A_COMP_SEL ,Alpha component byte select" "0,1,2,3" bitfld.long 0x10 14.--15. " R_COMP_SEL ,Red component byte select" "0,1,2,3" bitfld.long 0x10 12.--13. " G_COMP_SEL ,Green component byte select" "0,1,2,3" bitfld.long 0x10 10.--11. " B_COMP_SEL ,Blue component byte select" "0,1,2,3" newline bitfld.long 0x10 9. " PIX_UV_SWAP ,Pixel UV swap" "UV,VU" bitfld.long 0x10 8. " PIX_LUMA_UV_SWAP ,Pixel luma/UV position swap" "YUYV,UYVY" bitfld.long 0x10 6.--7. " PIX_SIZE ,Pixel size [bits]" "8,16,32,?..." bitfld.long 0x10 5. " COMP_2PLANE_EN ,Component 2-plane enable" "Disabled,Enabled" newline bitfld.long 0x10 4. " YUV_EN ,YUV enable" "Disabled,Enabled" bitfld.long 0x10 2.--3. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU" bitfld.long 0x10 1. " RTR_4LINE_BUF_EN ,RTRAM lines per buffer" "8,4" bitfld.long 0x10 0. " RTR_3BUF_EN ,RTRAM buffer implementation" "2,3" line.long 0x14 "MODE_CTRL0_SET,Mode Control Set Register" bitfld.long 0x14 16.--17. " A_COMP_SEL ,Alpha component byte select" "0,1,2,3" bitfld.long 0x14 14.--15. " R_COMP_SEL ,Red component byte select" "0,1,2,3" bitfld.long 0x14 12.--13. " G_COMP_SEL ,Green component byte select" "0,1,2,3" bitfld.long 0x14 10.--11. " B_COMP_SEL ,Blue component byte select" "0,1,2,3" newline bitfld.long 0x14 9. " PIX_UV_SWAP ,Pixel UV swap" "UV,VU" bitfld.long 0x14 8. " PIX_LUMA_UV_SWAP ,Pixel luma/UV position swap" "YUYV,UYVY" bitfld.long 0x14 6.--7. " PIX_SIZE ,Pixel size [bits]" "8,16,32,?..." bitfld.long 0x14 5. " COMP_2PLANE_EN ,Component 2-plane enable" "Disabled,Enabled" newline bitfld.long 0x14 4. " YUV_EN ,YUV enable" "Disabled,Enabled" bitfld.long 0x14 2.--3. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU" bitfld.long 0x14 1. " RTR_4LINE_BUF_EN ,RTRAM lines per buffer" "8,4" bitfld.long 0x14 0. " RTR_3BUF_EN ,RTRAM buffer implementation" "2,3" line.long 0x18 "MODE_CTRL0_CLR,Mode Control Clear Register" bitfld.long 0x18 16.--17. " A_COMP_SEL ,Alpha component byte select" "0,1,2,3" bitfld.long 0x18 14.--15. " R_COMP_SEL ,Red component byte select" "0,1,2,3" bitfld.long 0x18 12.--13. " G_COMP_SEL ,Green component byte select" "0,1,2,3" bitfld.long 0x18 10.--11. " B_COMP_SEL ,Blue component byte select" "0,1,2,3" newline bitfld.long 0x18 9. " PIX_UV_SWAP ,Pixel UV swap" "UV,VU" bitfld.long 0x18 8. " PIX_LUMA_UV_SWAP ,Pixel luma/UV position swap" "YUYV,UYVY" bitfld.long 0x18 6.--7. " PIX_SIZE ,Pixel size [bits]" "8,16,32,?..." bitfld.long 0x18 5. " COMP_2PLANE_EN ,Component 2-plane enable" "Disabled,Enabled" newline bitfld.long 0x18 4. " YUV_EN ,YUV enable" "Disabled,Enabled" bitfld.long 0x18 2.--3. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU" bitfld.long 0x18 1. " RTR_4LINE_BUF_EN ,RTRAM lines per buffer" "8,4" bitfld.long 0x18 0. " RTR_3BUF_EN ,RTRAM buffer implementation" "2,3" line.long 0x1C "MODE_CTRL0_TOG,Mode Control TOG Register" bitfld.long 0x1C 16.--17. " A_COMP_SEL ,Alpha component byte select" "0,1,2,3" bitfld.long 0x1C 14.--15. " R_COMP_SEL ,Red component byte select" "0,1,2,3" bitfld.long 0x1C 12.--13. " G_COMP_SEL ,Green component byte select" "0,1,2,3" bitfld.long 0x1C 10.--11. " B_COMP_SEL ,Blue component byte select" "0,1,2,3" newline bitfld.long 0x1C 9. " PIX_UV_SWAP ,Pixel UV swap" "UV,VU" bitfld.long 0x1C 8. " PIX_LUMA_UV_SWAP ,Pixel luma/UV position swap" "YUYV,UYVY" bitfld.long 0x1C 6.--7. " PIX_SIZE ,Pixel size [bits]" "8,16,32,?..." bitfld.long 0x1C 5. " COMP_2PLANE_EN ,Component 2-plane enable" "Disabled,Enabled" newline bitfld.long 0x1C 4. " YUV_EN ,YUV enable" "Disabled,Enabled" bitfld.long 0x1C 2.--3. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU" bitfld.long 0x1C 1. " RTR_4LINE_BUF_EN ,RTRAM lines per buffer" "8,4" bitfld.long 0x1C 0. " RTR_3BUF_EN ,RTRAM buffer implementation" "2,3" group.long 0x70++0x0F line.long 0x00 "FRAME_CTRL0,Frame Control Register" hexmask.long.word 0x00 16.--31. 1. " PITCH ,Image pitch" bitfld.long 0x00 4. " ROT_FLIP_OR_DER_EN ,Rotation horizontal/vertical flip order" "Rotate-flip,Flip-rotate" bitfld.long 0x00 2.--3. " ROT_ENC ,Encoded rotation [degrees]" "0,90,180,270" bitfld.long 0x00 1. " VFLIP_EN ,Vertical flip enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " HFLIP_EN ,Horizontal flip enable" "Disabled,Enabled" line.long 0x04 "FRAME_CTRL0_SET,Frame Control Set Register" hexmask.long.word 0x04 16.--31. 1. " PITCH ,Image pitch" bitfld.long 0x04 4. " ROT_FLIP_OR_DER_EN ,Rotation horizontal/vertical flip order" "Rotate-flip,Flip-rotate" bitfld.long 0x04 2.--3. " ROT_ENC ,Encoded rotation [degrees]" "0,90,180,270" bitfld.long 0x04 1. " VFLIP_EN ,Vertical flip enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " HFLIP_EN ,Horizontal flip enable" "Disabled,Enabled" line.long 0x08 "FRAME_CTRL0_CLR,Frame Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " PITCH ,Image pitch" bitfld.long 0x08 4. " ROT_FLIP_OR_DER_EN ,Rotation horizontal/vertical flip order" "Rotate-flip,Flip-rotate" bitfld.long 0x08 2.--3. " ROT_ENC ,Encoded rotation [degrees]" "0,90,180,270" bitfld.long 0x08 1. " VFLIP_EN ,Vertical flip enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " HFLIP_EN ,Horizontal flip enable" "Disabled,Enabled" line.long 0x0C "FRAME_CTRL0_TOG,Frame Control TOG Register" hexmask.long.word 0x0C 16.--31. 1. " PITCH ,Image pitch" bitfld.long 0x0C 4. " ROT_FLIP_OR_DER_EN ,Rotation horizontal/vertical flip order" "Rotate-flip,Flip-rotate" bitfld.long 0x0C 2.--3. " ROT_ENC ,Encoded rotation [degrees]" "0,90,180,270" bitfld.long 0x0C 1. " VFLIP_EN ,Vertical flip enable" "Disabled,Enabled" newline bitfld.long 0x0C 0. " HFLIP_EN ,Horizontal flip enable" "Disabled,Enabled" if (((per.l(ad:0x56100000+0x50)&0x0C)==0x08)&&((per.l(ad:0x56100000+0x50)&0xC0)==0x80)) group.long 0x90++0x0F line.long 0x00 "FRAME_1P_CTRL0,Frame 1-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x04 "FRAME_1P_CTRL0_SET,Frame 1-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x08 "FRAME_1P_CTRL0_CLR,Frame 1-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x0C "FRAME_1P_CTRL0_TOG,Frame 1-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." elif (((per.l(ad:0x56100000+0x50)&0x0C)==0x0C)||((per.l(ad:0x56100000+0x50)&0x0C)==0x08)&&((per.l(ad:0x56100000+0x50)&0xC0)==0x40)||((per.l(ad:0x56100000+0x70)&0x0C)==0x04)||((per.l(ad:0x56100000+0x70)&0x0C)==0x0C)) group.long 0x90++0x0F line.long 0x00 "FRAME_1P_CTRL0,Frame 1-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x04 "FRAME_1P_CTRL0_SET,Frame 1-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x08 "FRAME_1P_CTRL0_CLR,Frame 1-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x0C "FRAME_1P_CTRL0_TOG,Frame 1-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." else group.long 0x90++0x0F line.long 0x00 "FRAME_1P_CTRL0,Frame 1-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x04 "FRAME_1P_CTRL0_SET,Frame 1-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x08 "FRAME_1P_CTRL0_CLR,Frame 1-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x0C "FRAME_1P_CTRL0_TOG,Frame 1-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." endif group.long 0xA0++0x2F line.long 0x00 "FRAME_1P_PIX_X_CTRL,Frame 1-Plane Pix X Control Register" hexmask.long.word 0x00 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x04 "FRAME_1P_PIX_X_CTRL_SET,Frame 1-Plane Pix X Control Set Register" hexmask.long.word 0x04 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x08 "FRAME_1P_PIX_X_CTRL_CLR,Frame 1-Plane Pix X Control Clear Register" hexmask.long.word 0x08 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x0C "FRAME_1P_PIX_X_CTRL_TOG,Frame 1-Plane Pix X Control TOG Register" hexmask.long.word 0x0C 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x10 "FRAME_1P_PIX_Y_CTRL,Frame 1-Plane Pix Y Control Register" hexmask.long.word 0x10 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x14 "FRAME_1P_PIX_Y_CTRL_SET,Frame 1-Plane Pix Y Control Set Register" hexmask.long.word 0x14 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x18 "FRAME_1P_PIX_Y_CTRL_CLR,Frame 1-Plane Pix Y Control Clear Register" hexmask.long.word 0x18 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x1C "FRAME_1P_PIX_Y_CTRL_TOG,Frame 1-Plane Pix Y Control TOG Register" hexmask.long.word 0x1C 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x20 "FRAME_1P_BASE_ADDR_CTRL0,Frame 1-Plane Base Address Control Register" line.long 0x24 "FRAME_1P_BASE_ADDR_CTRL0_SET,Frame 1-Plane Base Address Control Set Register" line.long 0x28 "FRAME_1P_BASE_ADDR_CTRL0_CLR,Frame 1-Plane Base Address Control Clear Register" line.long 0x2C "FRAME_1P_BASE_ADDR_CTRL0_TOG,Frame 1-Plane Base Address Control TOG Register" if (((per.l(ad:0x56100000+0x50)&0x0C)==0x08)&&((per.l(ad:0x56100000+0x50)&0xC0)==0x80)) group.long 0xE0++0x0F line.long 0x00 "FRAME_2P_CTRL0,Frame 2-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x04 "FRAME_2P_CTRL0_SET,Frame 2-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x08 "FRAME_2P_CTRL0_CLR,Frame 2-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x0C "FRAME_2P_CTRL0_TOG,Frame 2-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." elif (((per.l(ad:0x56100000+0x50)&0x0C)==0x0C)||((per.l(ad:0x56100000+0x50)&0x0C)==0x08)&&((per.l(ad:0x56100000+0x50)&0xC0)==0x40)||((per.l(ad:0x56100000+0x70)&0x0C)==0x04)||((per.l(ad:0x56100000+0x70)&0x0C)==0x0C)) group.long 0xE0++0x0F line.long 0x00 "FRAME_2P_CTRL0,Frame 2-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x04 "FRAME_2P_CTRL0_SET,Frame 2-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x08 "FRAME_2P_CTRL0_CLR,Frame 2-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x0C "FRAME_2P_CTRL0_TOG,Frame 2-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." else group.long 0xE0++0x0F line.long 0x00 "FRAME_2P_CTRL0,Frame 2-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x04 "FRAME_2P_CTRL0_SET,Frame 2-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x08 "FRAME_2P_CTRL0_CLR,Frame 2-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x0C "FRAME_2P_CTRL0_TOG,Frame 2-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." endif group.long 0xF0++0x2F line.long 0x00 "FRAME_PIX_X_ULC_CTRL,Frame Pixel X Upper Left Coordinate Control Register" hexmask.long.word 0x00 0.--15. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" line.long 0x04 "FRAME_PIX_X_ULC_CTRL_SET,Frame Pixel X Upper Left Coordinate Set Control Register" hexmask.long.word 0x04 0.--15. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" line.long 0x08 "FRAME_PIX_X_ULC_CTRL_CLR,Frame Pixel X Upper Left Coordinate Clear Control Register" hexmask.long.word 0x08 0.--15. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" line.long 0x0C "FRAME_PIX_X_ULC_CTRL_TOG,Frame Pixel X Upper Left Coordinate TOG Control Register" hexmask.long.word 0x0C 0.--15. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" line.long 0x10 "FRAME_PIX_Y_ULC_CTRL,Frame Pixel Y Upper Left Coordinate Control Register" hexmask.long.word 0x10 0.--15. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y" line.long 0x14 "FRAME_PIX_Y_ULC_CTRL_SET,Frame Pixel Y Upper Left Coordinate Control Set Register" hexmask.long.word 0x14 0.--15. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y" line.long 0x18 "FRAME_PIX_Y_ULC_CTRL_CLR,Frame Pixel Y Upper Left Coordinate Control Clear Register" hexmask.long.word 0x18 0.--15. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y" line.long 0x1C "FRAME_PIX_Y_ULC_CTRL_TOG,Frame Pixel Y Upper Left Coordinate Control TOG Register" hexmask.long.word 0x1C 0.--15. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y" line.long 0x20 "FRAME_2P_BASE_ADDR_CTRL0,Frame 2-Plane Base Address Control Register" line.long 0x24 "FRAME_2P_BASE_ADDR_CTRL0_SET,Frame 2-Plane Base Address Control Set Register" line.long 0x28 "FRAME_2P_BASE_ADDR_CTRL0_CLR,Frame 2-Plane Base Address Control Clear Register" line.long 0x2C "FRAME_2P_BASE_ADDR_CTRL0_TOG,Frame 2-Plane Base Address Control TOG Register" group.long 0x130++0x0F line.long 0x00 "STATUS_CTRL0,Status Control Register" bitfld.long 0x00 16.--18. " STATUS_SRC_SEL ,Status source select" "DPR_CTRL,Prefetch YRGB/Y,Response YRGB/Y,Prefetch UV,Response UV,?..." bitfld.long 0x00 0.--2. " STATUS_MUX_SEL ,Status mux select" "0,1,2,3,4,5,6,7" line.long 0x04 "STATUS_CTRL0_SET,Status Control Set Register" bitfld.long 0x04 16.--18. " STATUS_SRC_SEL ,Status source select" "DPR_CTRL,Prefetch YRGB/Y,Response YRGB/Y,Prefetch UV,Response UV,?..." bitfld.long 0x04 0.--2. " STATUS_MUX_SEL ,Status mux select" "0,1,2,3,4,5,6,7" line.long 0x08 "STATUS_CTRL0_CLR,Status Control Clear Register" bitfld.long 0x08 16.--18. " STATUS_SRC_SEL ,Status source select" "DPR_CTRL,Prefetch YRGB/Y,Response YRGB/Y,Prefetch UV,Response UV,?..." bitfld.long 0x08 0.--2. " STATUS_MUX_SEL ,Status mux select" "0,1,2,3,4,5,6,7" line.long 0x0C "STATUS_CTRL0_TOG,Status Control TOG Register" bitfld.long 0x0C 16.--18. " STATUS_SRC_SEL ,Status source select" "DPR_CTRL,Prefetch YRGB/Y,Response YRGB/Y,Prefetch UV,Response UV,?..." bitfld.long 0x0C 0.--2. " STATUS_MUX_SEL ,Status mux select" "0,1,2,3,4,5,6,7" newline rgroup.long 0x140++0x0F line.long 0x00 "STATUS_CTRL1_SET/CLR,Status Control Set/Clear Register" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " STATUS[31] ,Internal DPR status/debug signal bit 31" "0,1" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [30] ,Internal DPR status/debug signal bit 30" "0,1" setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,Internal DPR status/debug signal bit 29" "0,1" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,Internal DPR status/debug signal bit 28" "0,1" setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,Internal DPR status/debug signal bit 27" "0,1" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,Internal DPR status/debug signal bit 26" "0,1" setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,Internal DPR status/debug signal bit 25" "0,1" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,Internal DPR status/debug signal bit 24" "0,1" setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,Internal DPR status/debug signal bit 23" "0,1" setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,Internal DPR status/debug signal bit 22" "0,1" setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,Internal DPR status/debug signal bit 21" "0,1" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,Internal DPR status/debug signal bit 20" "0,1" setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,Internal DPR status/debug signal bit 19" "0,1" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,Internal DPR status/debug signal bit 18" "0,1" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,Internal DPR status/debug signal bit 17" "0,1" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,Internal DPR status/debug signal bit 16" "0,1" newline setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,Internal DPR status/debug signal bit 15" "0,1" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,Internal DPR status/debug signal bit 14" "0,1" setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,Internal DPR status/debug signal bit 13" "0,1" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,Internal DPR status/debug signal bit 12" "0,1" setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,Internal DPR status/debug signal bit 11" "0,1" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,Internal DPR status/debug signal bit 10" "0,1" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,Internal DPR status/debug signal bit 9" "0,1" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,Internal DPR status/debug signal bit 8" "0,1" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,Internal DPR status/debug signal bit 7" "0,1" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,Internal DPR status/debug signal bit 6" "0,1" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,Internal DPR status/debug signal bit 5" "0,1" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,Internal DPR status/debug signal bit 4" "0,1" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Internal DPR status/debug signal bit 3" "0,1" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Internal DPR status/debug signal bit 2" "0,1" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Internal DPR status/debug signal bit 1" "0,1" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Internal DPR status/debug signal bit 0" "0,1" line.long 0x0C "STATUS_CTRL1_TOG,Status Control TOG Register" bitfld.long 0x0C 31. " STATUS[31] ,Internal DPR status/debug signal bit 31" "0,1" bitfld.long 0x0C 30. " [30] ,Internal DPR status/debug signal bit 30" "0,1" bitfld.long 0x0C 29. " [29] ,Internal DPR status/debug signal bit 29" "0,1" bitfld.long 0x0C 28. " [28] ,Internal DPR status/debug signal bit 28" "0,1" bitfld.long 0x0C 27. " [27] ,Internal DPR status/debug signal bit 27" "0,1" bitfld.long 0x0C 26. " [26] ,Internal DPR status/debug signal bit 26" "0,1" bitfld.long 0x0C 25. " [25] ,Internal DPR status/debug signal bit 25" "0,1" bitfld.long 0x0C 24. " [24] ,Internal DPR status/debug signal bit 24" "0,1" bitfld.long 0x0C 23. " [23] ,Internal DPR status/debug signal bit 23" "0,1" bitfld.long 0x0C 22. " [22] ,Internal DPR status/debug signal bit 22" "0,1" bitfld.long 0x0C 21. " [21] ,Internal DPR status/debug signal bit 21" "0,1" bitfld.long 0x0C 20. " [20] ,Internal DPR status/debug signal bit 20" "0,1" bitfld.long 0x0C 19. " [19] ,Internal DPR status/debug signal bit 19" "0,1" bitfld.long 0x0C 18. " [18] ,Internal DPR status/debug signal bit 18" "0,1" bitfld.long 0x0C 17. " [17] ,Internal DPR status/debug signal bit 17" "0,1" bitfld.long 0x0C 16. " [16] ,Internal DPR status/debug signal bit 16" "0,1" newline bitfld.long 0x0C 15. " [15] ,Internal DPR status/debug signal bit 15" "0,1" bitfld.long 0x0C 14. " [14] ,Internal DPR status/debug signal bit 14" "0,1" bitfld.long 0x0C 13. " [13] ,Internal DPR status/debug signal bit 13" "0,1" bitfld.long 0x0C 12. " [12] ,Internal DPR status/debug signal bit 12" "0,1" bitfld.long 0x0C 11. " [11] ,Internal DPR status/debug signal bit 11" "0,1" bitfld.long 0x0C 10. " [10] ,Internal DPR status/debug signal bit 10" "0,1" bitfld.long 0x0C 9. " [9] ,Internal DPR status/debug signal bit 9" "0,1" bitfld.long 0x0C 8. " [8] ,Internal DPR status/debug signal bit 8" "0,1" bitfld.long 0x0C 7. " [7] ,Internal DPR status/debug signal bit 7" "0,1" bitfld.long 0x0C 6. " [6] ,Internal DPR status/debug signal bit 6" "0,1" bitfld.long 0x0C 5. " [5] ,Internal DPR status/debug signal bit 5" "0,1" bitfld.long 0x0C 4. " [4] ,Internal DPR status/debug signal bit 4" "0,1" bitfld.long 0x0C 3. " [3] ,Internal DPR status/debug signal bit 3" "0,1" bitfld.long 0x0C 2. " [2] ,Internal DPR status/debug signal bit 2" "0,1" bitfld.long 0x0C 1. " [1] ,Internal DPR status/debug signal bit 1" "0,1" bitfld.long 0x0C 0. " [0] ,Internal DPR status/debug signal bit 0" "0,1" newline group.long 0x200++0x0F line.long 0x00 "RTRAM_CTRL0,RTRAM Control Register" bitfld.long 0x00 7. " ABORT_SEL ,Abort select" "STALL,ABORT" bitfld.long 0x00 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " NUM_ROWS_ACTIVE ,Number of rows active" "0-4,0-6(all)" line.long 0x04 "RTRAM_CTRL0_SET,RTRAM Control Set Register" bitfld.long 0x04 7. " ABORT_SEL ,Abort select" "STALL,ABORT" bitfld.long 0x04 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x04 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0. " NUM_ROWS_ACTIVE ,Number of rows active" "0-4,0-6(all)" line.long 0x08 "RTRAM_CTRL0_CLR,RTRAM Control Clear Register" bitfld.long 0x08 7. " ABORT_SEL ,Abort select" "STALL,ABORT" bitfld.long 0x08 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x08 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. " NUM_ROWS_ACTIVE ,Number of rows active" "0-4,0-6(all)" line.long 0x0C "RTRAM_CTRL0_TOG,RTRAM Control TOG Register" bitfld.long 0x0C 7. " ABORT_SEL ,Abort select" "STALL,ABORT" bitfld.long 0x0C 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0. " NUM_ROWS_ACTIVE ,Number of rows active" "0-4,0-6(all)" width 0x0B tree.end tree "Channel 1" base ad:0x56110000 width 30. group.long 0x00++0x0F line.long 0x00 "SYSTEM_CTRL0_SET/CLR,System Control Set/Clear Register" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " BCMD2AXI_MSTR_ID_CTRL ,BUSCMD to AXI master ID control" "Unique,Same" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " SW_SHADOW_LOAD_SEL ,Software shadow load select" "Hardware signal,SHADOW_LOAD_EN" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " SHADOW_LOAD_EN ,Shadow load enable" "Disabled,Enabled" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " REPEAT_EN ,Repeat enable" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SOFT_RESET ,Soft reset" "No reset,Reset" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RUN_EN ,Run enable" "Disabled,Enabled" line.long 0x0C "SYSTEM_CTRL0_TOG,System Control TOG Register" bitfld.long 0x0C 16. " BCMD2AXI_MSTR_ID_CTRL ,BUSCMD to AXI master ID control" "Unique,Same" bitfld.long 0x0C 4. " SW_SHADOW_LOAD_SEL ,Software shadow load select" "Hardware signal,SHADOW_LOAD_EN" newline bitfld.long 0x0C 3. " SHADOW_LOAD_EN ,Shadow load enable" "Disabled,Enabled" bitfld.long 0x0C 2. " REPEAT_EN ,Repeat enable" "Disabled,Enabled" newline bitfld.long 0x0C 1. " SOFT_RESET ,Soft reset" "No reset,Reset" bitfld.long 0x0C 0. " RUN_EN ,Run enable" "Disabled,Enabled" group.long 0x20++0x0F line.long 0x00 "IRQ_MASK_SET/CLR,Interrupt Mask Set/Clear Register" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready IRQ error mask" "No error,Error" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready IRQ error mask" "No error,Error" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow IRQ mask" "No interrupt,Interrupt" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow IRQ mask" "No interrupt,Interrupt" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " IRQ_AXI_READ_ERROR ,AXI read error IRQ mask" "No interrupt,Interrupt" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " IRQ_DPR_SHADOW_LOADED_MASK ,DPR shadow loaded IRQ mask" "No interrupt,Interrupt" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " IRQ_DPR_RUN ,DPR run IRQ mask" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " IRQ_DPR_CTRL_DONE ,DPR control done IRQ mask" "No interrupt,Interrupt" line.long 0x0C "IRQ_MASK_TOG,Interrupt Mask TOG Register" bitfld.long 0x0C 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready IRQ error mask" "No interrupt,Interrupt" bitfld.long 0x0C 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready IRQ error mask" "No interrupt,Interrupt" newline bitfld.long 0x0C 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow IRQ mask" "No interrupt,Interrupt" bitfld.long 0x0C 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow IRQ mask" "No interrupt,Interrupt" newline bitfld.long 0x0C 3. " IRQ_AXI_READ_ERROR ,AXI read error IRQ mask" "No interrupt,Interrupt" bitfld.long 0x0C 2. " IRQ_DPR_SHADOW_LOADED_MASK ,DPR shadow loaded IRQ mask" "No interrupt,Interrupt" newline bitfld.long 0x0C 1. " IRQ_DPR_RUN ,DPR run IRQ mask" "No interrupt,Interrupt" bitfld.long 0x0C 0. " IRQ_DPR_CTRL_DONE ,DPR control done IRQ mask" "No interrupt,Interrupt" rgroup.long 0x30++0x0F line.long 0x00 "IRQ_MASK_STATUS_SET/CLR,Masked IRQ Status Set/Clear Register" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer error masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer error masked IRQ" "No interrupt,Interrupt" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow masked IRQ" "No interrupt,Interrupt" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " IRQ_AXI_READ_ERROR ,AXI read error masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " IRQ_DPR_SHADOW_LOADED ,DPR shadow loaded masked IRQ" "No interrupt,Interrupt" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " IRQ_DPR_RUN ,DPR run masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " IRQ_DPR_CTRL_DONE ,DPR control done masked IRQ" "No interrupt,Interrupt" line.long 0x0C "IRQ_MASK_STATUS_TOG,Masked IRQ Status TOG Register" bitfld.long 0x0C 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer error masked IRQ" "No interrupt,Interrupt" bitfld.long 0x0C 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer error masked IRQ" "No interrupt,Interrupt" newline bitfld.long 0x0C 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow masked IRQ" "No interrupt,Interrupt" bitfld.long 0x0C 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow masked IRQ" "No interrupt,Interrupt" newline bitfld.long 0x0C 3. " IRQ_AXI_READ_ERROR ,AXI read error masked IRQ" "No interrupt,Interrupt" bitfld.long 0x0C 2. " IRQ_DPR_SHADOW_LOADED ,DPR shadow loaded masked IRQ" "No interrupt,Interrupt" newline bitfld.long 0x0C 1. " IRQ_DPR_RUN ,DPR run masked IRQ" "No interrupt,Interrupt" bitfld.long 0x0C 0. " IRQ_DPR_CTRL_DONE ,DPR control done masked IRQ" "No interrupt,Interrupt" group.long 0x40++0x1F line.long 0x00 "IRQ_NONMASK_STATUS,Non-Masked IRQ Status Register" eventfld.long 0x00 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready error non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x00 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x00 3. " IRQ_AXI_READ_ERROR ,AXI read error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 2. " IRQ_DPR_SHADOW_LOADED_NMSTAT ,DPR shadow loaded non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x00 1. " IRQ_DPR_RUN ,DPR run non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 0. " IRQ_DPR_CTRL_DONE ,DPR control done non-masked IRQ" "No interrupt,Interrupt" line.long 0x04 "IRQ_NONMASK_STATUS_SET,Non-Masked IRQ Status Set Register" eventfld.long 0x04 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x04 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready error non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x04 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x04 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x04 3. " IRQ_AXI_READ_ERROR ,AXI read error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x04 2. " IRQ_DPR_SHADOW_LOADED_NMSTAT ,DPR shadow loaded non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x04 1. " IRQ_DPR_RUN ,DPR run non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x04 0. " IRQ_DPR_CTRL_DONE ,DPR control done non-masked IRQ" "No interrupt,Interrupt" line.long 0x08 "IRQ_NONMASK_STATUS_CLR,Non-Masked IRQ Status Clear Register" eventfld.long 0x08 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x08 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready error non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x08 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x08 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x08 3. " IRQ_AXI_READ_ERROR ,AXI read error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x08 2. " IRQ_DPR_SHADOW_LOADED_NMSTAT ,DPR shadow loaded non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x08 1. " IRQ_DPR_RUN ,DPR run non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x08 0. " IRQ_DPR_CTRL_DONE ,DPR control done non-masked IRQ" "No interrupt,Interrupt" line.long 0x0C "IRQ_NONMASK_STATUS_TOG,Non-Masked IRQ Status TOG Register" eventfld.long 0x0C 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x0C 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready error non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x0C 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x0C 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x0C 3. " IRQ_AXI_READ_ERROR ,AXI read error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x0C 2. " IRQ_DPR_SHADOW_LOADED_NMSTAT ,DPR shadow loaded non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x0C 1. " IRQ_DPR_RUN ,DPR run non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x0C 0. " IRQ_DPR_CTRL_DONE ,DPR control done non-masked IRQ" "No interrupt,Interrupt" newline line.long 0x10 "MODE_CTRL0,Mode Control Register" bitfld.long 0x10 16.--17. " A_COMP_SEL ,Alpha component byte select" "0,1,2,3" bitfld.long 0x10 14.--15. " R_COMP_SEL ,Red component byte select" "0,1,2,3" bitfld.long 0x10 12.--13. " G_COMP_SEL ,Green component byte select" "0,1,2,3" bitfld.long 0x10 10.--11. " B_COMP_SEL ,Blue component byte select" "0,1,2,3" newline bitfld.long 0x10 9. " PIX_UV_SWAP ,Pixel UV swap" "UV,VU" bitfld.long 0x10 8. " PIX_LUMA_UV_SWAP ,Pixel luma/UV position swap" "YUYV,UYVY" bitfld.long 0x10 6.--7. " PIX_SIZE ,Pixel size [bits]" "8,16,32,?..." bitfld.long 0x10 5. " COMP_2PLANE_EN ,Component 2-plane enable" "Disabled,Enabled" newline bitfld.long 0x10 4. " YUV_EN ,YUV enable" "Disabled,Enabled" bitfld.long 0x10 2.--3. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU" bitfld.long 0x10 1. " RTR_4LINE_BUF_EN ,RTRAM lines per buffer" "8,4" bitfld.long 0x10 0. " RTR_3BUF_EN ,RTRAM buffer implementation" "2,3" line.long 0x14 "MODE_CTRL0_SET,Mode Control Set Register" bitfld.long 0x14 16.--17. " A_COMP_SEL ,Alpha component byte select" "0,1,2,3" bitfld.long 0x14 14.--15. " R_COMP_SEL ,Red component byte select" "0,1,2,3" bitfld.long 0x14 12.--13. " G_COMP_SEL ,Green component byte select" "0,1,2,3" bitfld.long 0x14 10.--11. " B_COMP_SEL ,Blue component byte select" "0,1,2,3" newline bitfld.long 0x14 9. " PIX_UV_SWAP ,Pixel UV swap" "UV,VU" bitfld.long 0x14 8. " PIX_LUMA_UV_SWAP ,Pixel luma/UV position swap" "YUYV,UYVY" bitfld.long 0x14 6.--7. " PIX_SIZE ,Pixel size [bits]" "8,16,32,?..." bitfld.long 0x14 5. " COMP_2PLANE_EN ,Component 2-plane enable" "Disabled,Enabled" newline bitfld.long 0x14 4. " YUV_EN ,YUV enable" "Disabled,Enabled" bitfld.long 0x14 2.--3. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU" bitfld.long 0x14 1. " RTR_4LINE_BUF_EN ,RTRAM lines per buffer" "8,4" bitfld.long 0x14 0. " RTR_3BUF_EN ,RTRAM buffer implementation" "2,3" line.long 0x18 "MODE_CTRL0_CLR,Mode Control Clear Register" bitfld.long 0x18 16.--17. " A_COMP_SEL ,Alpha component byte select" "0,1,2,3" bitfld.long 0x18 14.--15. " R_COMP_SEL ,Red component byte select" "0,1,2,3" bitfld.long 0x18 12.--13. " G_COMP_SEL ,Green component byte select" "0,1,2,3" bitfld.long 0x18 10.--11. " B_COMP_SEL ,Blue component byte select" "0,1,2,3" newline bitfld.long 0x18 9. " PIX_UV_SWAP ,Pixel UV swap" "UV,VU" bitfld.long 0x18 8. " PIX_LUMA_UV_SWAP ,Pixel luma/UV position swap" "YUYV,UYVY" bitfld.long 0x18 6.--7. " PIX_SIZE ,Pixel size [bits]" "8,16,32,?..." bitfld.long 0x18 5. " COMP_2PLANE_EN ,Component 2-plane enable" "Disabled,Enabled" newline bitfld.long 0x18 4. " YUV_EN ,YUV enable" "Disabled,Enabled" bitfld.long 0x18 2.--3. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU" bitfld.long 0x18 1. " RTR_4LINE_BUF_EN ,RTRAM lines per buffer" "8,4" bitfld.long 0x18 0. " RTR_3BUF_EN ,RTRAM buffer implementation" "2,3" line.long 0x1C "MODE_CTRL0_TOG,Mode Control TOG Register" bitfld.long 0x1C 16.--17. " A_COMP_SEL ,Alpha component byte select" "0,1,2,3" bitfld.long 0x1C 14.--15. " R_COMP_SEL ,Red component byte select" "0,1,2,3" bitfld.long 0x1C 12.--13. " G_COMP_SEL ,Green component byte select" "0,1,2,3" bitfld.long 0x1C 10.--11. " B_COMP_SEL ,Blue component byte select" "0,1,2,3" newline bitfld.long 0x1C 9. " PIX_UV_SWAP ,Pixel UV swap" "UV,VU" bitfld.long 0x1C 8. " PIX_LUMA_UV_SWAP ,Pixel luma/UV position swap" "YUYV,UYVY" bitfld.long 0x1C 6.--7. " PIX_SIZE ,Pixel size [bits]" "8,16,32,?..." bitfld.long 0x1C 5. " COMP_2PLANE_EN ,Component 2-plane enable" "Disabled,Enabled" newline bitfld.long 0x1C 4. " YUV_EN ,YUV enable" "Disabled,Enabled" bitfld.long 0x1C 2.--3. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU" bitfld.long 0x1C 1. " RTR_4LINE_BUF_EN ,RTRAM lines per buffer" "8,4" bitfld.long 0x1C 0. " RTR_3BUF_EN ,RTRAM buffer implementation" "2,3" group.long 0x70++0x0F line.long 0x00 "FRAME_CTRL0,Frame Control Register" hexmask.long.word 0x00 16.--31. 1. " PITCH ,Image pitch" bitfld.long 0x00 4. " ROT_FLIP_OR_DER_EN ,Rotation horizontal/vertical flip order" "Rotate-flip,Flip-rotate" bitfld.long 0x00 2.--3. " ROT_ENC ,Encoded rotation [degrees]" "0,90,180,270" bitfld.long 0x00 1. " VFLIP_EN ,Vertical flip enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " HFLIP_EN ,Horizontal flip enable" "Disabled,Enabled" line.long 0x04 "FRAME_CTRL0_SET,Frame Control Set Register" hexmask.long.word 0x04 16.--31. 1. " PITCH ,Image pitch" bitfld.long 0x04 4. " ROT_FLIP_OR_DER_EN ,Rotation horizontal/vertical flip order" "Rotate-flip,Flip-rotate" bitfld.long 0x04 2.--3. " ROT_ENC ,Encoded rotation [degrees]" "0,90,180,270" bitfld.long 0x04 1. " VFLIP_EN ,Vertical flip enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " HFLIP_EN ,Horizontal flip enable" "Disabled,Enabled" line.long 0x08 "FRAME_CTRL0_CLR,Frame Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " PITCH ,Image pitch" bitfld.long 0x08 4. " ROT_FLIP_OR_DER_EN ,Rotation horizontal/vertical flip order" "Rotate-flip,Flip-rotate" bitfld.long 0x08 2.--3. " ROT_ENC ,Encoded rotation [degrees]" "0,90,180,270" bitfld.long 0x08 1. " VFLIP_EN ,Vertical flip enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " HFLIP_EN ,Horizontal flip enable" "Disabled,Enabled" line.long 0x0C "FRAME_CTRL0_TOG,Frame Control TOG Register" hexmask.long.word 0x0C 16.--31. 1. " PITCH ,Image pitch" bitfld.long 0x0C 4. " ROT_FLIP_OR_DER_EN ,Rotation horizontal/vertical flip order" "Rotate-flip,Flip-rotate" bitfld.long 0x0C 2.--3. " ROT_ENC ,Encoded rotation [degrees]" "0,90,180,270" bitfld.long 0x0C 1. " VFLIP_EN ,Vertical flip enable" "Disabled,Enabled" newline bitfld.long 0x0C 0. " HFLIP_EN ,Horizontal flip enable" "Disabled,Enabled" if (((per.l(ad:0x56110000+0x50)&0x0C)==0x08)&&((per.l(ad:0x56110000+0x50)&0xC0)==0x80)) group.long 0x90++0x0F line.long 0x00 "FRAME_1P_CTRL0,Frame 1-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x04 "FRAME_1P_CTRL0_SET,Frame 1-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x08 "FRAME_1P_CTRL0_CLR,Frame 1-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x0C "FRAME_1P_CTRL0_TOG,Frame 1-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." elif (((per.l(ad:0x56110000+0x50)&0x0C)==0x0C)||((per.l(ad:0x56110000+0x50)&0x0C)==0x08)&&((per.l(ad:0x56110000+0x50)&0xC0)==0x40)||((per.l(ad:0x56110000+0x70)&0x0C)==0x04)||((per.l(ad:0x56110000+0x70)&0x0C)==0x0C)) group.long 0x90++0x0F line.long 0x00 "FRAME_1P_CTRL0,Frame 1-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x04 "FRAME_1P_CTRL0_SET,Frame 1-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x08 "FRAME_1P_CTRL0_CLR,Frame 1-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x0C "FRAME_1P_CTRL0_TOG,Frame 1-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." else group.long 0x90++0x0F line.long 0x00 "FRAME_1P_CTRL0,Frame 1-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x04 "FRAME_1P_CTRL0_SET,Frame 1-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x08 "FRAME_1P_CTRL0_CLR,Frame 1-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x0C "FRAME_1P_CTRL0_TOG,Frame 1-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." endif group.long 0xA0++0x2F line.long 0x00 "FRAME_1P_PIX_X_CTRL,Frame 1-Plane Pix X Control Register" hexmask.long.word 0x00 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x04 "FRAME_1P_PIX_X_CTRL_SET,Frame 1-Plane Pix X Control Set Register" hexmask.long.word 0x04 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x08 "FRAME_1P_PIX_X_CTRL_CLR,Frame 1-Plane Pix X Control Clear Register" hexmask.long.word 0x08 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x0C "FRAME_1P_PIX_X_CTRL_TOG,Frame 1-Plane Pix X Control TOG Register" hexmask.long.word 0x0C 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x10 "FRAME_1P_PIX_Y_CTRL,Frame 1-Plane Pix Y Control Register" hexmask.long.word 0x10 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x14 "FRAME_1P_PIX_Y_CTRL_SET,Frame 1-Plane Pix Y Control Set Register" hexmask.long.word 0x14 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x18 "FRAME_1P_PIX_Y_CTRL_CLR,Frame 1-Plane Pix Y Control Clear Register" hexmask.long.word 0x18 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x1C "FRAME_1P_PIX_Y_CTRL_TOG,Frame 1-Plane Pix Y Control TOG Register" hexmask.long.word 0x1C 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x20 "FRAME_1P_BASE_ADDR_CTRL0,Frame 1-Plane Base Address Control Register" line.long 0x24 "FRAME_1P_BASE_ADDR_CTRL0_SET,Frame 1-Plane Base Address Control Set Register" line.long 0x28 "FRAME_1P_BASE_ADDR_CTRL0_CLR,Frame 1-Plane Base Address Control Clear Register" line.long 0x2C "FRAME_1P_BASE_ADDR_CTRL0_TOG,Frame 1-Plane Base Address Control TOG Register" if (((per.l(ad:0x56110000+0x50)&0x0C)==0x08)&&((per.l(ad:0x56110000+0x50)&0xC0)==0x80)) group.long 0xE0++0x0F line.long 0x00 "FRAME_2P_CTRL0,Frame 2-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x04 "FRAME_2P_CTRL0_SET,Frame 2-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x08 "FRAME_2P_CTRL0_CLR,Frame 2-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x0C "FRAME_2P_CTRL0_TOG,Frame 2-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." elif (((per.l(ad:0x56110000+0x50)&0x0C)==0x0C)||((per.l(ad:0x56110000+0x50)&0x0C)==0x08)&&((per.l(ad:0x56110000+0x50)&0xC0)==0x40)||((per.l(ad:0x56110000+0x70)&0x0C)==0x04)||((per.l(ad:0x56110000+0x70)&0x0C)==0x0C)) group.long 0xE0++0x0F line.long 0x00 "FRAME_2P_CTRL0,Frame 2-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x04 "FRAME_2P_CTRL0_SET,Frame 2-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x08 "FRAME_2P_CTRL0_CLR,Frame 2-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x0C "FRAME_2P_CTRL0_TOG,Frame 2-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." else group.long 0xE0++0x0F line.long 0x00 "FRAME_2P_CTRL0,Frame 2-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x04 "FRAME_2P_CTRL0_SET,Frame 2-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x08 "FRAME_2P_CTRL0_CLR,Frame 2-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x0C "FRAME_2P_CTRL0_TOG,Frame 2-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." endif group.long 0xF0++0x2F line.long 0x00 "FRAME_PIX_X_ULC_CTRL,Frame Pixel X Upper Left Coordinate Control Register" hexmask.long.word 0x00 0.--15. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" line.long 0x04 "FRAME_PIX_X_ULC_CTRL_SET,Frame Pixel X Upper Left Coordinate Set Control Register" hexmask.long.word 0x04 0.--15. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" line.long 0x08 "FRAME_PIX_X_ULC_CTRL_CLR,Frame Pixel X Upper Left Coordinate Clear Control Register" hexmask.long.word 0x08 0.--15. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" line.long 0x0C "FRAME_PIX_X_ULC_CTRL_TOG,Frame Pixel X Upper Left Coordinate TOG Control Register" hexmask.long.word 0x0C 0.--15. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" line.long 0x10 "FRAME_PIX_Y_ULC_CTRL,Frame Pixel Y Upper Left Coordinate Control Register" hexmask.long.word 0x10 0.--15. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y" line.long 0x14 "FRAME_PIX_Y_ULC_CTRL_SET,Frame Pixel Y Upper Left Coordinate Control Set Register" hexmask.long.word 0x14 0.--15. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y" line.long 0x18 "FRAME_PIX_Y_ULC_CTRL_CLR,Frame Pixel Y Upper Left Coordinate Control Clear Register" hexmask.long.word 0x18 0.--15. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y" line.long 0x1C "FRAME_PIX_Y_ULC_CTRL_TOG,Frame Pixel Y Upper Left Coordinate Control TOG Register" hexmask.long.word 0x1C 0.--15. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y" line.long 0x20 "FRAME_2P_BASE_ADDR_CTRL0,Frame 2-Plane Base Address Control Register" line.long 0x24 "FRAME_2P_BASE_ADDR_CTRL0_SET,Frame 2-Plane Base Address Control Set Register" line.long 0x28 "FRAME_2P_BASE_ADDR_CTRL0_CLR,Frame 2-Plane Base Address Control Clear Register" line.long 0x2C "FRAME_2P_BASE_ADDR_CTRL0_TOG,Frame 2-Plane Base Address Control TOG Register" group.long 0x130++0x0F line.long 0x00 "STATUS_CTRL0,Status Control Register" bitfld.long 0x00 16.--18. " STATUS_SRC_SEL ,Status source select" "DPR_CTRL,Prefetch YRGB/Y,Response YRGB/Y,Prefetch UV,Response UV,?..." bitfld.long 0x00 0.--2. " STATUS_MUX_SEL ,Status mux select" "0,1,2,3,4,5,6,7" line.long 0x04 "STATUS_CTRL0_SET,Status Control Set Register" bitfld.long 0x04 16.--18. " STATUS_SRC_SEL ,Status source select" "DPR_CTRL,Prefetch YRGB/Y,Response YRGB/Y,Prefetch UV,Response UV,?..." bitfld.long 0x04 0.--2. " STATUS_MUX_SEL ,Status mux select" "0,1,2,3,4,5,6,7" line.long 0x08 "STATUS_CTRL0_CLR,Status Control Clear Register" bitfld.long 0x08 16.--18. " STATUS_SRC_SEL ,Status source select" "DPR_CTRL,Prefetch YRGB/Y,Response YRGB/Y,Prefetch UV,Response UV,?..." bitfld.long 0x08 0.--2. " STATUS_MUX_SEL ,Status mux select" "0,1,2,3,4,5,6,7" line.long 0x0C "STATUS_CTRL0_TOG,Status Control TOG Register" bitfld.long 0x0C 16.--18. " STATUS_SRC_SEL ,Status source select" "DPR_CTRL,Prefetch YRGB/Y,Response YRGB/Y,Prefetch UV,Response UV,?..." bitfld.long 0x0C 0.--2. " STATUS_MUX_SEL ,Status mux select" "0,1,2,3,4,5,6,7" newline rgroup.long 0x140++0x0F line.long 0x00 "STATUS_CTRL1_SET/CLR,Status Control Set/Clear Register" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " STATUS[31] ,Internal DPR status/debug signal bit 31" "0,1" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [30] ,Internal DPR status/debug signal bit 30" "0,1" setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,Internal DPR status/debug signal bit 29" "0,1" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,Internal DPR status/debug signal bit 28" "0,1" setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,Internal DPR status/debug signal bit 27" "0,1" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,Internal DPR status/debug signal bit 26" "0,1" setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,Internal DPR status/debug signal bit 25" "0,1" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,Internal DPR status/debug signal bit 24" "0,1" setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,Internal DPR status/debug signal bit 23" "0,1" setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,Internal DPR status/debug signal bit 22" "0,1" setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,Internal DPR status/debug signal bit 21" "0,1" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,Internal DPR status/debug signal bit 20" "0,1" setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,Internal DPR status/debug signal bit 19" "0,1" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,Internal DPR status/debug signal bit 18" "0,1" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,Internal DPR status/debug signal bit 17" "0,1" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,Internal DPR status/debug signal bit 16" "0,1" newline setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,Internal DPR status/debug signal bit 15" "0,1" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,Internal DPR status/debug signal bit 14" "0,1" setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,Internal DPR status/debug signal bit 13" "0,1" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,Internal DPR status/debug signal bit 12" "0,1" setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,Internal DPR status/debug signal bit 11" "0,1" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,Internal DPR status/debug signal bit 10" "0,1" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,Internal DPR status/debug signal bit 9" "0,1" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,Internal DPR status/debug signal bit 8" "0,1" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,Internal DPR status/debug signal bit 7" "0,1" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,Internal DPR status/debug signal bit 6" "0,1" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,Internal DPR status/debug signal bit 5" "0,1" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,Internal DPR status/debug signal bit 4" "0,1" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Internal DPR status/debug signal bit 3" "0,1" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Internal DPR status/debug signal bit 2" "0,1" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Internal DPR status/debug signal bit 1" "0,1" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Internal DPR status/debug signal bit 0" "0,1" line.long 0x0C "STATUS_CTRL1_TOG,Status Control TOG Register" bitfld.long 0x0C 31. " STATUS[31] ,Internal DPR status/debug signal bit 31" "0,1" bitfld.long 0x0C 30. " [30] ,Internal DPR status/debug signal bit 30" "0,1" bitfld.long 0x0C 29. " [29] ,Internal DPR status/debug signal bit 29" "0,1" bitfld.long 0x0C 28. " [28] ,Internal DPR status/debug signal bit 28" "0,1" bitfld.long 0x0C 27. " [27] ,Internal DPR status/debug signal bit 27" "0,1" bitfld.long 0x0C 26. " [26] ,Internal DPR status/debug signal bit 26" "0,1" bitfld.long 0x0C 25. " [25] ,Internal DPR status/debug signal bit 25" "0,1" bitfld.long 0x0C 24. " [24] ,Internal DPR status/debug signal bit 24" "0,1" bitfld.long 0x0C 23. " [23] ,Internal DPR status/debug signal bit 23" "0,1" bitfld.long 0x0C 22. " [22] ,Internal DPR status/debug signal bit 22" "0,1" bitfld.long 0x0C 21. " [21] ,Internal DPR status/debug signal bit 21" "0,1" bitfld.long 0x0C 20. " [20] ,Internal DPR status/debug signal bit 20" "0,1" bitfld.long 0x0C 19. " [19] ,Internal DPR status/debug signal bit 19" "0,1" bitfld.long 0x0C 18. " [18] ,Internal DPR status/debug signal bit 18" "0,1" bitfld.long 0x0C 17. " [17] ,Internal DPR status/debug signal bit 17" "0,1" bitfld.long 0x0C 16. " [16] ,Internal DPR status/debug signal bit 16" "0,1" newline bitfld.long 0x0C 15. " [15] ,Internal DPR status/debug signal bit 15" "0,1" bitfld.long 0x0C 14. " [14] ,Internal DPR status/debug signal bit 14" "0,1" bitfld.long 0x0C 13. " [13] ,Internal DPR status/debug signal bit 13" "0,1" bitfld.long 0x0C 12. " [12] ,Internal DPR status/debug signal bit 12" "0,1" bitfld.long 0x0C 11. " [11] ,Internal DPR status/debug signal bit 11" "0,1" bitfld.long 0x0C 10. " [10] ,Internal DPR status/debug signal bit 10" "0,1" bitfld.long 0x0C 9. " [9] ,Internal DPR status/debug signal bit 9" "0,1" bitfld.long 0x0C 8. " [8] ,Internal DPR status/debug signal bit 8" "0,1" bitfld.long 0x0C 7. " [7] ,Internal DPR status/debug signal bit 7" "0,1" bitfld.long 0x0C 6. " [6] ,Internal DPR status/debug signal bit 6" "0,1" bitfld.long 0x0C 5. " [5] ,Internal DPR status/debug signal bit 5" "0,1" bitfld.long 0x0C 4. " [4] ,Internal DPR status/debug signal bit 4" "0,1" bitfld.long 0x0C 3. " [3] ,Internal DPR status/debug signal bit 3" "0,1" bitfld.long 0x0C 2. " [2] ,Internal DPR status/debug signal bit 2" "0,1" bitfld.long 0x0C 1. " [1] ,Internal DPR status/debug signal bit 1" "0,1" bitfld.long 0x0C 0. " [0] ,Internal DPR status/debug signal bit 0" "0,1" newline group.long 0x200++0x0F line.long 0x00 "RTRAM_CTRL0,RTRAM Control Register" bitfld.long 0x00 7. " ABORT_SEL ,Abort select" "STALL,ABORT" bitfld.long 0x00 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " NUM_ROWS_ACTIVE ,Number of rows active" "0-4,0-6(all)" line.long 0x04 "RTRAM_CTRL0_SET,RTRAM Control Set Register" bitfld.long 0x04 7. " ABORT_SEL ,Abort select" "STALL,ABORT" bitfld.long 0x04 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x04 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0. " NUM_ROWS_ACTIVE ,Number of rows active" "0-4,0-6(all)" line.long 0x08 "RTRAM_CTRL0_CLR,RTRAM Control Clear Register" bitfld.long 0x08 7. " ABORT_SEL ,Abort select" "STALL,ABORT" bitfld.long 0x08 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x08 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. " NUM_ROWS_ACTIVE ,Number of rows active" "0-4,0-6(all)" line.long 0x0C "RTRAM_CTRL0_TOG,RTRAM Control TOG Register" bitfld.long 0x0C 7. " ABORT_SEL ,Abort select" "STALL,ABORT" bitfld.long 0x0C 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0. " NUM_ROWS_ACTIVE ,Number of rows active" "0-4,0-6(all)" width 0x0B tree.end tree "Channel 2" base ad:0x56120000 width 30. group.long 0x00++0x0F line.long 0x00 "SYSTEM_CTRL0_SET/CLR,System Control Set/Clear Register" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " BCMD2AXI_MSTR_ID_CTRL ,BUSCMD to AXI master ID control" "Unique,Same" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " SW_SHADOW_LOAD_SEL ,Software shadow load select" "Hardware signal,SHADOW_LOAD_EN" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " SHADOW_LOAD_EN ,Shadow load enable" "Disabled,Enabled" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " REPEAT_EN ,Repeat enable" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SOFT_RESET ,Soft reset" "No reset,Reset" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RUN_EN ,Run enable" "Disabled,Enabled" line.long 0x0C "SYSTEM_CTRL0_TOG,System Control TOG Register" bitfld.long 0x0C 16. " BCMD2AXI_MSTR_ID_CTRL ,BUSCMD to AXI master ID control" "Unique,Same" bitfld.long 0x0C 4. " SW_SHADOW_LOAD_SEL ,Software shadow load select" "Hardware signal,SHADOW_LOAD_EN" newline bitfld.long 0x0C 3. " SHADOW_LOAD_EN ,Shadow load enable" "Disabled,Enabled" bitfld.long 0x0C 2. " REPEAT_EN ,Repeat enable" "Disabled,Enabled" newline bitfld.long 0x0C 1. " SOFT_RESET ,Soft reset" "No reset,Reset" bitfld.long 0x0C 0. " RUN_EN ,Run enable" "Disabled,Enabled" group.long 0x20++0x0F line.long 0x00 "IRQ_MASK_SET/CLR,Interrupt Mask Set/Clear Register" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready IRQ error mask" "No error,Error" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready IRQ error mask" "No error,Error" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow IRQ mask" "No interrupt,Interrupt" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow IRQ mask" "No interrupt,Interrupt" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " IRQ_AXI_READ_ERROR ,AXI read error IRQ mask" "No interrupt,Interrupt" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " IRQ_DPR_SHADOW_LOADED_MASK ,DPR shadow loaded IRQ mask" "No interrupt,Interrupt" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " IRQ_DPR_RUN ,DPR run IRQ mask" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " IRQ_DPR_CTRL_DONE ,DPR control done IRQ mask" "No interrupt,Interrupt" line.long 0x0C "IRQ_MASK_TOG,Interrupt Mask TOG Register" bitfld.long 0x0C 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready IRQ error mask" "No interrupt,Interrupt" bitfld.long 0x0C 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready IRQ error mask" "No interrupt,Interrupt" newline bitfld.long 0x0C 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow IRQ mask" "No interrupt,Interrupt" bitfld.long 0x0C 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow IRQ mask" "No interrupt,Interrupt" newline bitfld.long 0x0C 3. " IRQ_AXI_READ_ERROR ,AXI read error IRQ mask" "No interrupt,Interrupt" bitfld.long 0x0C 2. " IRQ_DPR_SHADOW_LOADED_MASK ,DPR shadow loaded IRQ mask" "No interrupt,Interrupt" newline bitfld.long 0x0C 1. " IRQ_DPR_RUN ,DPR run IRQ mask" "No interrupt,Interrupt" bitfld.long 0x0C 0. " IRQ_DPR_CTRL_DONE ,DPR control done IRQ mask" "No interrupt,Interrupt" rgroup.long 0x30++0x0F line.long 0x00 "IRQ_MASK_STATUS_SET/CLR,Masked IRQ Status Set/Clear Register" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer error masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer error masked IRQ" "No interrupt,Interrupt" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow masked IRQ" "No interrupt,Interrupt" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " IRQ_AXI_READ_ERROR ,AXI read error masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " IRQ_DPR_SHADOW_LOADED ,DPR shadow loaded masked IRQ" "No interrupt,Interrupt" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " IRQ_DPR_RUN ,DPR run masked IRQ" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " IRQ_DPR_CTRL_DONE ,DPR control done masked IRQ" "No interrupt,Interrupt" line.long 0x0C "IRQ_MASK_STATUS_TOG,Masked IRQ Status TOG Register" bitfld.long 0x0C 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer error masked IRQ" "No interrupt,Interrupt" bitfld.long 0x0C 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer error masked IRQ" "No interrupt,Interrupt" newline bitfld.long 0x0C 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow masked IRQ" "No interrupt,Interrupt" bitfld.long 0x0C 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow masked IRQ" "No interrupt,Interrupt" newline bitfld.long 0x0C 3. " IRQ_AXI_READ_ERROR ,AXI read error masked IRQ" "No interrupt,Interrupt" bitfld.long 0x0C 2. " IRQ_DPR_SHADOW_LOADED ,DPR shadow loaded masked IRQ" "No interrupt,Interrupt" newline bitfld.long 0x0C 1. " IRQ_DPR_RUN ,DPR run masked IRQ" "No interrupt,Interrupt" bitfld.long 0x0C 0. " IRQ_DPR_CTRL_DONE ,DPR control done masked IRQ" "No interrupt,Interrupt" group.long 0x40++0x1F line.long 0x00 "IRQ_NONMASK_STATUS,Non-Masked IRQ Status Register" eventfld.long 0x00 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready error non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x00 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x00 3. " IRQ_AXI_READ_ERROR ,AXI read error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 2. " IRQ_DPR_SHADOW_LOADED_NMSTAT ,DPR shadow loaded non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x00 1. " IRQ_DPR_RUN ,DPR run non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x00 0. " IRQ_DPR_CTRL_DONE ,DPR control done non-masked IRQ" "No interrupt,Interrupt" line.long 0x04 "IRQ_NONMASK_STATUS_SET,Non-Masked IRQ Status Set Register" eventfld.long 0x04 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x04 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready error non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x04 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x04 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x04 3. " IRQ_AXI_READ_ERROR ,AXI read error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x04 2. " IRQ_DPR_SHADOW_LOADED_NMSTAT ,DPR shadow loaded non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x04 1. " IRQ_DPR_RUN ,DPR run non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x04 0. " IRQ_DPR_CTRL_DONE ,DPR control done non-masked IRQ" "No interrupt,Interrupt" line.long 0x08 "IRQ_NONMASK_STATUS_CLR,Non-Masked IRQ Status Clear Register" eventfld.long 0x08 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x08 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready error non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x08 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x08 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x08 3. " IRQ_AXI_READ_ERROR ,AXI read error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x08 2. " IRQ_DPR_SHADOW_LOADED_NMSTAT ,DPR shadow loaded non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x08 1. " IRQ_DPR_RUN ,DPR run non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x08 0. " IRQ_DPR_CTRL_DONE ,DPR control done non-masked IRQ" "No interrupt,Interrupt" line.long 0x0C "IRQ_NONMASK_STATUS_TOG,Non-Masked IRQ Status TOG Register" eventfld.long 0x0C 7. " DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR ,DPR to RTRAM FIFO load UV buffer ready error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x0C 6. " DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR ,DPR to RTRAM FIFO load YRGB buffer ready error non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x0C 5. " DPR2RTR_UV_FIFO_OVFL ,DPR to RTRAM UV FIFO overflow non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x0C 4. " DPR2RTR_YRGB_FIFO_OVFL ,DPR to RTRAM YRGB FIFO overflow non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x0C 3. " IRQ_AXI_READ_ERROR ,AXI read error non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x0C 2. " IRQ_DPR_SHADOW_LOADED_NMSTAT ,DPR shadow loaded non-masked IRQ" "No interrupt,Interrupt" newline eventfld.long 0x0C 1. " IRQ_DPR_RUN ,DPR run non-masked IRQ" "No interrupt,Interrupt" eventfld.long 0x0C 0. " IRQ_DPR_CTRL_DONE ,DPR control done non-masked IRQ" "No interrupt,Interrupt" newline line.long 0x10 "MODE_CTRL0,Mode Control Register" bitfld.long 0x10 16.--17. " A_COMP_SEL ,Alpha component byte select" "0,1,2,3" bitfld.long 0x10 14.--15. " R_COMP_SEL ,Red component byte select" "0,1,2,3" bitfld.long 0x10 12.--13. " G_COMP_SEL ,Green component byte select" "0,1,2,3" bitfld.long 0x10 10.--11. " B_COMP_SEL ,Blue component byte select" "0,1,2,3" newline bitfld.long 0x10 9. " PIX_UV_SWAP ,Pixel UV swap" "UV,VU" bitfld.long 0x10 8. " PIX_LUMA_UV_SWAP ,Pixel luma/UV position swap" "YUYV,UYVY" bitfld.long 0x10 6.--7. " PIX_SIZE ,Pixel size [bits]" "8,16,32,?..." bitfld.long 0x10 5. " COMP_2PLANE_EN ,Component 2-plane enable" "Disabled,Enabled" newline bitfld.long 0x10 4. " YUV_EN ,YUV enable" "Disabled,Enabled" bitfld.long 0x10 2.--3. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU" bitfld.long 0x10 1. " RTR_4LINE_BUF_EN ,RTRAM lines per buffer" "8,4" bitfld.long 0x10 0. " RTR_3BUF_EN ,RTRAM buffer implementation" "2,3" line.long 0x14 "MODE_CTRL0_SET,Mode Control Set Register" bitfld.long 0x14 16.--17. " A_COMP_SEL ,Alpha component byte select" "0,1,2,3" bitfld.long 0x14 14.--15. " R_COMP_SEL ,Red component byte select" "0,1,2,3" bitfld.long 0x14 12.--13. " G_COMP_SEL ,Green component byte select" "0,1,2,3" bitfld.long 0x14 10.--11. " B_COMP_SEL ,Blue component byte select" "0,1,2,3" newline bitfld.long 0x14 9. " PIX_UV_SWAP ,Pixel UV swap" "UV,VU" bitfld.long 0x14 8. " PIX_LUMA_UV_SWAP ,Pixel luma/UV position swap" "YUYV,UYVY" bitfld.long 0x14 6.--7. " PIX_SIZE ,Pixel size [bits]" "8,16,32,?..." bitfld.long 0x14 5. " COMP_2PLANE_EN ,Component 2-plane enable" "Disabled,Enabled" newline bitfld.long 0x14 4. " YUV_EN ,YUV enable" "Disabled,Enabled" bitfld.long 0x14 2.--3. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU" bitfld.long 0x14 1. " RTR_4LINE_BUF_EN ,RTRAM lines per buffer" "8,4" bitfld.long 0x14 0. " RTR_3BUF_EN ,RTRAM buffer implementation" "2,3" line.long 0x18 "MODE_CTRL0_CLR,Mode Control Clear Register" bitfld.long 0x18 16.--17. " A_COMP_SEL ,Alpha component byte select" "0,1,2,3" bitfld.long 0x18 14.--15. " R_COMP_SEL ,Red component byte select" "0,1,2,3" bitfld.long 0x18 12.--13. " G_COMP_SEL ,Green component byte select" "0,1,2,3" bitfld.long 0x18 10.--11. " B_COMP_SEL ,Blue component byte select" "0,1,2,3" newline bitfld.long 0x18 9. " PIX_UV_SWAP ,Pixel UV swap" "UV,VU" bitfld.long 0x18 8. " PIX_LUMA_UV_SWAP ,Pixel luma/UV position swap" "YUYV,UYVY" bitfld.long 0x18 6.--7. " PIX_SIZE ,Pixel size [bits]" "8,16,32,?..." bitfld.long 0x18 5. " COMP_2PLANE_EN ,Component 2-plane enable" "Disabled,Enabled" newline bitfld.long 0x18 4. " YUV_EN ,YUV enable" "Disabled,Enabled" bitfld.long 0x18 2.--3. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU" bitfld.long 0x18 1. " RTR_4LINE_BUF_EN ,RTRAM lines per buffer" "8,4" bitfld.long 0x18 0. " RTR_3BUF_EN ,RTRAM buffer implementation" "2,3" line.long 0x1C "MODE_CTRL0_TOG,Mode Control TOG Register" bitfld.long 0x1C 16.--17. " A_COMP_SEL ,Alpha component byte select" "0,1,2,3" bitfld.long 0x1C 14.--15. " R_COMP_SEL ,Red component byte select" "0,1,2,3" bitfld.long 0x1C 12.--13. " G_COMP_SEL ,Green component byte select" "0,1,2,3" bitfld.long 0x1C 10.--11. " B_COMP_SEL ,Blue component byte select" "0,1,2,3" newline bitfld.long 0x1C 9. " PIX_UV_SWAP ,Pixel UV swap" "UV,VU" bitfld.long 0x1C 8. " PIX_LUMA_UV_SWAP ,Pixel luma/UV position swap" "YUYV,UYVY" bitfld.long 0x1C 6.--7. " PIX_SIZE ,Pixel size [bits]" "8,16,32,?..." bitfld.long 0x1C 5. " COMP_2PLANE_EN ,Component 2-plane enable" "Disabled,Enabled" newline bitfld.long 0x1C 4. " YUV_EN ,YUV enable" "Disabled,Enabled" bitfld.long 0x1C 2.--3. " TILE_TYPE ,Tile type" "Linear,GPU standard,GPU super,VPU" bitfld.long 0x1C 1. " RTR_4LINE_BUF_EN ,RTRAM lines per buffer" "8,4" bitfld.long 0x1C 0. " RTR_3BUF_EN ,RTRAM buffer implementation" "2,3" group.long 0x70++0x0F line.long 0x00 "FRAME_CTRL0,Frame Control Register" hexmask.long.word 0x00 16.--31. 1. " PITCH ,Image pitch" bitfld.long 0x00 4. " ROT_FLIP_OR_DER_EN ,Rotation horizontal/vertical flip order" "Rotate-flip,Flip-rotate" bitfld.long 0x00 2.--3. " ROT_ENC ,Encoded rotation [degrees]" "0,90,180,270" bitfld.long 0x00 1. " VFLIP_EN ,Vertical flip enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " HFLIP_EN ,Horizontal flip enable" "Disabled,Enabled" line.long 0x04 "FRAME_CTRL0_SET,Frame Control Set Register" hexmask.long.word 0x04 16.--31. 1. " PITCH ,Image pitch" bitfld.long 0x04 4. " ROT_FLIP_OR_DER_EN ,Rotation horizontal/vertical flip order" "Rotate-flip,Flip-rotate" bitfld.long 0x04 2.--3. " ROT_ENC ,Encoded rotation [degrees]" "0,90,180,270" bitfld.long 0x04 1. " VFLIP_EN ,Vertical flip enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " HFLIP_EN ,Horizontal flip enable" "Disabled,Enabled" line.long 0x08 "FRAME_CTRL0_CLR,Frame Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " PITCH ,Image pitch" bitfld.long 0x08 4. " ROT_FLIP_OR_DER_EN ,Rotation horizontal/vertical flip order" "Rotate-flip,Flip-rotate" bitfld.long 0x08 2.--3. " ROT_ENC ,Encoded rotation [degrees]" "0,90,180,270" bitfld.long 0x08 1. " VFLIP_EN ,Vertical flip enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " HFLIP_EN ,Horizontal flip enable" "Disabled,Enabled" line.long 0x0C "FRAME_CTRL0_TOG,Frame Control TOG Register" hexmask.long.word 0x0C 16.--31. 1. " PITCH ,Image pitch" bitfld.long 0x0C 4. " ROT_FLIP_OR_DER_EN ,Rotation horizontal/vertical flip order" "Rotate-flip,Flip-rotate" bitfld.long 0x0C 2.--3. " ROT_ENC ,Encoded rotation [degrees]" "0,90,180,270" bitfld.long 0x0C 1. " VFLIP_EN ,Vertical flip enable" "Disabled,Enabled" newline bitfld.long 0x0C 0. " HFLIP_EN ,Horizontal flip enable" "Disabled,Enabled" if (((per.l(ad:0x56120000+0x50)&0x0C)==0x08)&&((per.l(ad:0x56120000+0x50)&0xC0)==0x80)) group.long 0x90++0x0F line.long 0x00 "FRAME_1P_CTRL0,Frame 1-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x04 "FRAME_1P_CTRL0_SET,Frame 1-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x08 "FRAME_1P_CTRL0_CLR,Frame 1-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x0C "FRAME_1P_CTRL0_TOG,Frame 1-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." elif (((per.l(ad:0x56120000+0x50)&0x0C)==0x0C)||((per.l(ad:0x56120000+0x50)&0x0C)==0x08)&&((per.l(ad:0x56120000+0x50)&0xC0)==0x40)||((per.l(ad:0x56120000+0x70)&0x0C)==0x04)||((per.l(ad:0x56120000+0x70)&0x0C)==0x0C)) group.long 0x90++0x0F line.long 0x00 "FRAME_1P_CTRL0,Frame 1-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x04 "FRAME_1P_CTRL0_SET,Frame 1-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x08 "FRAME_1P_CTRL0_CLR,Frame 1-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x0C "FRAME_1P_CTRL0_TOG,Frame 1-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." else group.long 0x90++0x0F line.long 0x00 "FRAME_1P_CTRL0,Frame 1-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x04 "FRAME_1P_CTRL0_SET,Frame 1-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x08 "FRAME_1P_CTRL0_CLR,Frame 1-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x0C "FRAME_1P_CTRL0_TOG,Frame 1-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." endif group.long 0xA0++0x2F line.long 0x00 "FRAME_1P_PIX_X_CTRL,Frame 1-Plane Pix X Control Register" hexmask.long.word 0x00 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x04 "FRAME_1P_PIX_X_CTRL_SET,Frame 1-Plane Pix X Control Set Register" hexmask.long.word 0x04 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x08 "FRAME_1P_PIX_X_CTRL_CLR,Frame 1-Plane Pix X Control Clear Register" hexmask.long.word 0x08 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x0C "FRAME_1P_PIX_X_CTRL_TOG,Frame 1-Plane Pix X Control TOG Register" hexmask.long.word 0x0C 0.--15. 1. " NUM_X_PIX_WIDE ,Number of pixels wide in X-direction" line.long 0x10 "FRAME_1P_PIX_Y_CTRL,Frame 1-Plane Pix Y Control Register" hexmask.long.word 0x10 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x14 "FRAME_1P_PIX_Y_CTRL_SET,Frame 1-Plane Pix Y Control Set Register" hexmask.long.word 0x14 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x18 "FRAME_1P_PIX_Y_CTRL_CLR,Frame 1-Plane Pix Y Control Clear Register" hexmask.long.word 0x18 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x1C "FRAME_1P_PIX_Y_CTRL_TOG,Frame 1-Plane Pix Y Control TOG Register" hexmask.long.word 0x1C 0.--15. 1. " NUM_Y_PIX_HIGH ,Number of pixels high in Y-direction" line.long 0x20 "FRAME_1P_BASE_ADDR_CTRL0,Frame 1-Plane Base Address Control Register" line.long 0x24 "FRAME_1P_BASE_ADDR_CTRL0_SET,Frame 1-Plane Base Address Control Set Register" line.long 0x28 "FRAME_1P_BASE_ADDR_CTRL0_CLR,Frame 1-Plane Base Address Control Clear Register" line.long 0x2C "FRAME_1P_BASE_ADDR_CTRL0_TOG,Frame 1-Plane Base Address Control TOG Register" if (((per.l(ad:0x56120000+0x50)&0x0C)==0x08)&&((per.l(ad:0x56120000+0x50)&0xC0)==0x80)) group.long 0xE0++0x0F line.long 0x00 "FRAME_2P_CTRL0,Frame 2-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x04 "FRAME_2P_CTRL0_SET,Frame 2-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x08 "FRAME_2P_CTRL0_CLR,Frame 2-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." line.long 0x0C "FRAME_2P_CTRL0_TOG,Frame 2-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,?..." elif (((per.l(ad:0x56120000+0x50)&0x0C)==0x0C)||((per.l(ad:0x56120000+0x50)&0x0C)==0x08)&&((per.l(ad:0x56120000+0x50)&0xC0)==0x40)||((per.l(ad:0x56120000+0x70)&0x0C)==0x04)||((per.l(ad:0x56120000+0x70)&0x0C)==0x0C)) group.long 0xE0++0x0F line.long 0x00 "FRAME_2P_CTRL0,Frame 2-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x04 "FRAME_2P_CTRL0_SET,Frame 2-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x08 "FRAME_2P_CTRL0_CLR,Frame 2-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." line.long 0x0C "FRAME_2P_CTRL0_TOG,Frame 2-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,?..." else group.long 0xE0++0x0F line.long 0x00 "FRAME_2P_CTRL0,Frame 2-Plane Control Register" bitfld.long 0x00 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x04 "FRAME_2P_CTRL0_SET,Frame 2-Plane Control Set Register" bitfld.long 0x04 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x08 "FRAME_2P_CTRL0_CLR,Frame 2-Plane Control Clear Register" bitfld.long 0x08 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." line.long 0x0C "FRAME_2P_CTRL0_TOG,Frame 2-Plane Control TOG Register" bitfld.long 0x0C 0.--2. " MAX_BYTES_PREQ ,Max bytes per request" "64,128,256,512,1024,2048,4096,?..." endif group.long 0xF0++0x2F line.long 0x00 "FRAME_PIX_X_ULC_CTRL,Frame Pixel X Upper Left Coordinate Control Register" hexmask.long.word 0x00 0.--15. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" line.long 0x04 "FRAME_PIX_X_ULC_CTRL_SET,Frame Pixel X Upper Left Coordinate Set Control Register" hexmask.long.word 0x04 0.--15. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" line.long 0x08 "FRAME_PIX_X_ULC_CTRL_CLR,Frame Pixel X Upper Left Coordinate Clear Control Register" hexmask.long.word 0x08 0.--15. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" line.long 0x0C "FRAME_PIX_X_ULC_CTRL_TOG,Frame Pixel X Upper Left Coordinate TOG Control Register" hexmask.long.word 0x0C 0.--15. 1. " CROP_ULC_X ,Starting coordinate of cropped image X" line.long 0x10 "FRAME_PIX_Y_ULC_CTRL,Frame Pixel Y Upper Left Coordinate Control Register" hexmask.long.word 0x10 0.--15. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y" line.long 0x14 "FRAME_PIX_Y_ULC_CTRL_SET,Frame Pixel Y Upper Left Coordinate Control Set Register" hexmask.long.word 0x14 0.--15. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y" line.long 0x18 "FRAME_PIX_Y_ULC_CTRL_CLR,Frame Pixel Y Upper Left Coordinate Control Clear Register" hexmask.long.word 0x18 0.--15. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y" line.long 0x1C "FRAME_PIX_Y_ULC_CTRL_TOG,Frame Pixel Y Upper Left Coordinate Control TOG Register" hexmask.long.word 0x1C 0.--15. 1. " CROP_ULC_Y ,Starting coordinate of cropped image Y" line.long 0x20 "FRAME_2P_BASE_ADDR_CTRL0,Frame 2-Plane Base Address Control Register" line.long 0x24 "FRAME_2P_BASE_ADDR_CTRL0_SET,Frame 2-Plane Base Address Control Set Register" line.long 0x28 "FRAME_2P_BASE_ADDR_CTRL0_CLR,Frame 2-Plane Base Address Control Clear Register" line.long 0x2C "FRAME_2P_BASE_ADDR_CTRL0_TOG,Frame 2-Plane Base Address Control TOG Register" group.long 0x130++0x0F line.long 0x00 "STATUS_CTRL0,Status Control Register" bitfld.long 0x00 16.--18. " STATUS_SRC_SEL ,Status source select" "DPR_CTRL,Prefetch YRGB/Y,Response YRGB/Y,Prefetch UV,Response UV,?..." bitfld.long 0x00 0.--2. " STATUS_MUX_SEL ,Status mux select" "0,1,2,3,4,5,6,7" line.long 0x04 "STATUS_CTRL0_SET,Status Control Set Register" bitfld.long 0x04 16.--18. " STATUS_SRC_SEL ,Status source select" "DPR_CTRL,Prefetch YRGB/Y,Response YRGB/Y,Prefetch UV,Response UV,?..." bitfld.long 0x04 0.--2. " STATUS_MUX_SEL ,Status mux select" "0,1,2,3,4,5,6,7" line.long 0x08 "STATUS_CTRL0_CLR,Status Control Clear Register" bitfld.long 0x08 16.--18. " STATUS_SRC_SEL ,Status source select" "DPR_CTRL,Prefetch YRGB/Y,Response YRGB/Y,Prefetch UV,Response UV,?..." bitfld.long 0x08 0.--2. " STATUS_MUX_SEL ,Status mux select" "0,1,2,3,4,5,6,7" line.long 0x0C "STATUS_CTRL0_TOG,Status Control TOG Register" bitfld.long 0x0C 16.--18. " STATUS_SRC_SEL ,Status source select" "DPR_CTRL,Prefetch YRGB/Y,Response YRGB/Y,Prefetch UV,Response UV,?..." bitfld.long 0x0C 0.--2. " STATUS_MUX_SEL ,Status mux select" "0,1,2,3,4,5,6,7" newline rgroup.long 0x140++0x0F line.long 0x00 "STATUS_CTRL1_SET/CLR,Status Control Set/Clear Register" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " STATUS[31] ,Internal DPR status/debug signal bit 31" "0,1" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [30] ,Internal DPR status/debug signal bit 30" "0,1" setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,Internal DPR status/debug signal bit 29" "0,1" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,Internal DPR status/debug signal bit 28" "0,1" setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,Internal DPR status/debug signal bit 27" "0,1" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,Internal DPR status/debug signal bit 26" "0,1" setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,Internal DPR status/debug signal bit 25" "0,1" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,Internal DPR status/debug signal bit 24" "0,1" setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,Internal DPR status/debug signal bit 23" "0,1" setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,Internal DPR status/debug signal bit 22" "0,1" setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,Internal DPR status/debug signal bit 21" "0,1" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,Internal DPR status/debug signal bit 20" "0,1" setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,Internal DPR status/debug signal bit 19" "0,1" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,Internal DPR status/debug signal bit 18" "0,1" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,Internal DPR status/debug signal bit 17" "0,1" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,Internal DPR status/debug signal bit 16" "0,1" newline setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,Internal DPR status/debug signal bit 15" "0,1" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,Internal DPR status/debug signal bit 14" "0,1" setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,Internal DPR status/debug signal bit 13" "0,1" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,Internal DPR status/debug signal bit 12" "0,1" setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,Internal DPR status/debug signal bit 11" "0,1" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,Internal DPR status/debug signal bit 10" "0,1" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,Internal DPR status/debug signal bit 9" "0,1" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,Internal DPR status/debug signal bit 8" "0,1" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,Internal DPR status/debug signal bit 7" "0,1" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,Internal DPR status/debug signal bit 6" "0,1" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,Internal DPR status/debug signal bit 5" "0,1" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,Internal DPR status/debug signal bit 4" "0,1" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Internal DPR status/debug signal bit 3" "0,1" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Internal DPR status/debug signal bit 2" "0,1" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Internal DPR status/debug signal bit 1" "0,1" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Internal DPR status/debug signal bit 0" "0,1" line.long 0x0C "STATUS_CTRL1_TOG,Status Control TOG Register" bitfld.long 0x0C 31. " STATUS[31] ,Internal DPR status/debug signal bit 31" "0,1" bitfld.long 0x0C 30. " [30] ,Internal DPR status/debug signal bit 30" "0,1" bitfld.long 0x0C 29. " [29] ,Internal DPR status/debug signal bit 29" "0,1" bitfld.long 0x0C 28. " [28] ,Internal DPR status/debug signal bit 28" "0,1" bitfld.long 0x0C 27. " [27] ,Internal DPR status/debug signal bit 27" "0,1" bitfld.long 0x0C 26. " [26] ,Internal DPR status/debug signal bit 26" "0,1" bitfld.long 0x0C 25. " [25] ,Internal DPR status/debug signal bit 25" "0,1" bitfld.long 0x0C 24. " [24] ,Internal DPR status/debug signal bit 24" "0,1" bitfld.long 0x0C 23. " [23] ,Internal DPR status/debug signal bit 23" "0,1" bitfld.long 0x0C 22. " [22] ,Internal DPR status/debug signal bit 22" "0,1" bitfld.long 0x0C 21. " [21] ,Internal DPR status/debug signal bit 21" "0,1" bitfld.long 0x0C 20. " [20] ,Internal DPR status/debug signal bit 20" "0,1" bitfld.long 0x0C 19. " [19] ,Internal DPR status/debug signal bit 19" "0,1" bitfld.long 0x0C 18. " [18] ,Internal DPR status/debug signal bit 18" "0,1" bitfld.long 0x0C 17. " [17] ,Internal DPR status/debug signal bit 17" "0,1" bitfld.long 0x0C 16. " [16] ,Internal DPR status/debug signal bit 16" "0,1" newline bitfld.long 0x0C 15. " [15] ,Internal DPR status/debug signal bit 15" "0,1" bitfld.long 0x0C 14. " [14] ,Internal DPR status/debug signal bit 14" "0,1" bitfld.long 0x0C 13. " [13] ,Internal DPR status/debug signal bit 13" "0,1" bitfld.long 0x0C 12. " [12] ,Internal DPR status/debug signal bit 12" "0,1" bitfld.long 0x0C 11. " [11] ,Internal DPR status/debug signal bit 11" "0,1" bitfld.long 0x0C 10. " [10] ,Internal DPR status/debug signal bit 10" "0,1" bitfld.long 0x0C 9. " [9] ,Internal DPR status/debug signal bit 9" "0,1" bitfld.long 0x0C 8. " [8] ,Internal DPR status/debug signal bit 8" "0,1" bitfld.long 0x0C 7. " [7] ,Internal DPR status/debug signal bit 7" "0,1" bitfld.long 0x0C 6. " [6] ,Internal DPR status/debug signal bit 6" "0,1" bitfld.long 0x0C 5. " [5] ,Internal DPR status/debug signal bit 5" "0,1" bitfld.long 0x0C 4. " [4] ,Internal DPR status/debug signal bit 4" "0,1" bitfld.long 0x0C 3. " [3] ,Internal DPR status/debug signal bit 3" "0,1" bitfld.long 0x0C 2. " [2] ,Internal DPR status/debug signal bit 2" "0,1" bitfld.long 0x0C 1. " [1] ,Internal DPR status/debug signal bit 1" "0,1" bitfld.long 0x0C 0. " [0] ,Internal DPR status/debug signal bit 0" "0,1" newline group.long 0x200++0x0F line.long 0x00 "RTRAM_CTRL0,RTRAM Control Register" bitfld.long 0x00 7. " ABORT_SEL ,Abort select" "STALL,ABORT" bitfld.long 0x00 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " NUM_ROWS_ACTIVE ,Number of rows active" "0-4,0-6(all)" line.long 0x04 "RTRAM_CTRL0_SET,RTRAM Control Set Register" bitfld.long 0x04 7. " ABORT_SEL ,Abort select" "STALL,ABORT" bitfld.long 0x04 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x04 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0. " NUM_ROWS_ACTIVE ,Number of rows active" "0-4,0-6(all)" line.long 0x08 "RTRAM_CTRL0_CLR,RTRAM Control Clear Register" bitfld.long 0x08 7. " ABORT_SEL ,Abort select" "STALL,ABORT" bitfld.long 0x08 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x08 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. " NUM_ROWS_ACTIVE ,Number of rows active" "0-4,0-6(all)" line.long 0x0C "RTRAM_CTRL0_TOG,RTRAM Control TOG Register" bitfld.long 0x0C 7. " ABORT_SEL ,Abort select" "STALL,ABORT" bitfld.long 0x0C 4.--6. " THRES_LOW ,Threshold low" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 1.--3. " THRES_HIGH ,Threshold high" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0. " NUM_ROWS_ACTIVE ,Number of rows active" "0-4,0-6(all)" width 0x0B tree.end tree.end tree "PRG0 (Prefetch Resolve Gasket 0)" base ad:0x56040000 width 16. group.long 0x00++0x0F line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x00 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x00 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x00 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x00 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x00 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x00 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" line.long 0x04 "CTRL_SET,Control Set Register" bitfld.long 0x04 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x04 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x04 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x04 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x04 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x04 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x04 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" line.long 0x08 "CTRL_CLR,Control Clear Register" bitfld.long 0x08 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x08 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x08 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x08 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x08 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x08 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x08 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x08 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" line.long 0x0C "CTRL_TOG,Control TOG Register" bitfld.long 0x0C 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x0C 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x0C 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x0C 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x0C 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x0C 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x0C 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x0C 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" rgroup.long 0x10++0x0F line.long 0x00 "STATUS,Status Register" bitfld.long 0x00 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x00 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" line.long 0x04 "STATUS_SET,Status Set Register" bitfld.long 0x04 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x04 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" line.long 0x08 "STATUS_CLR,Status Clear Register" bitfld.long 0x08 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x08 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" line.long 0x0C "STATUS_TOG,Status TOG Register" bitfld.long 0x0C 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x0C 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" group.long 0x20++0x3F line.long 0x00 "REG_UPDATE,REG Update Register" bitfld.long 0x00 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x04 "REG_UPDATE_SET,REG Update Set Register" bitfld.long 0x04 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x08 "REG_UPDATE_CLR,REG Update Clear Register" bitfld.long 0x08 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x0C "REG_UPDATE_TOG,REG Update TOG Register" bitfld.long 0x0C 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x10 "STRIDE,Stride Register" hexmask.long.word 0x10 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x14 "STRIDE_SET,Stride Set Register" hexmask.long.word 0x14 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x18 "STRIDE_CLR,Stride Clear Register" hexmask.long.word 0x18 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x1C "STRIDE_TOG,Stride TOG Register" hexmask.long.word 0x1C 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x20 "HEIGHT,Height Register" hexmask.long.word 0x20 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x24 "HEIGHT_SET,Height Set Register" hexmask.long.word 0x24 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x28 "HEIGHT_CLR,Height Clear Register" hexmask.long.word 0x28 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x2C "HEIGHT_TOG,Height TOG Register" hexmask.long.word 0x2C 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x30 "BADDR,Base Address Register" line.long 0x34 "BADDR_SET,Base Address Set Register" line.long 0x38 "BADDR_CLR,Base Address Clear Register" line.long 0x3C "BADDR_TOG,Base Address TOG Register" if ((per.l(ad:0x56040000)&0x10)==0x00) group.long 0x60++0x0F line.long 0x00 "OFFSET,Offset Address Register" bitfld.long 0x00 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." line.long 0x04 "OFFSET_SET,Offset Address Set Register" bitfld.long 0x04 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." line.long 0x08 "OFFSET_CLR,Offset Address Clear Register" bitfld.long 0x08 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." line.long 0x0C "OFFSET_TOG,Offset Address TOG Register" bitfld.long 0x0C 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." else group.long 0x60++0x0F line.long 0x00 "OFFSET,Offset Address Register" bitfld.long 0x00 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" line.long 0x04 "OFFSET_SET,Offset Address Set Register" bitfld.long 0x04 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" line.long 0x08 "OFFSET_CLR,Offset Address Clear Register" bitfld.long 0x08 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" line.long 0x0C "OFFSET_TOG,Offset Address TOG Register" bitfld.long 0x0C 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" endif group.long 0x70++0x0F line.long 0x00 "WIDTH,Width Register" hexmask.long.word 0x00 0.--15. 1. " WIDTH ,Read frame width" line.long 0x04 "WIDTH_SET,Width Set Register" hexmask.long.word 0x04 0.--15. 1. " WIDTH ,Read frame width" line.long 0x08 "WIDTH_CLR,Width Clear Register" hexmask.long.word 0x08 0.--15. 1. " WIDTH ,Read frame width" line.long 0x0C "WIDTH_TOG,Width TOG Register" hexmask.long.word 0x0C 0.--15. 1. " WIDTH ,Read frame width" width 0x0B tree.end tree "PRG1 (Prefetch Resolve Gasket 1)" base ad:0x56050000 width 16. group.long 0x00++0x0F line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x00 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x00 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x00 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x00 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x00 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x00 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" line.long 0x04 "CTRL_SET,Control Set Register" bitfld.long 0x04 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x04 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x04 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x04 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x04 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x04 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x04 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" line.long 0x08 "CTRL_CLR,Control Clear Register" bitfld.long 0x08 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x08 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x08 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x08 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x08 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x08 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x08 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x08 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" line.long 0x0C "CTRL_TOG,Control TOG Register" bitfld.long 0x0C 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x0C 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x0C 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x0C 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x0C 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x0C 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x0C 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x0C 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" rgroup.long 0x10++0x0F line.long 0x00 "STATUS,Status Register" bitfld.long 0x00 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x00 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" line.long 0x04 "STATUS_SET,Status Set Register" bitfld.long 0x04 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x04 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" line.long 0x08 "STATUS_CLR,Status Clear Register" bitfld.long 0x08 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x08 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" line.long 0x0C "STATUS_TOG,Status TOG Register" bitfld.long 0x0C 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x0C 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" group.long 0x20++0x3F line.long 0x00 "REG_UPDATE,REG Update Register" bitfld.long 0x00 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x04 "REG_UPDATE_SET,REG Update Set Register" bitfld.long 0x04 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x08 "REG_UPDATE_CLR,REG Update Clear Register" bitfld.long 0x08 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x0C "REG_UPDATE_TOG,REG Update TOG Register" bitfld.long 0x0C 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x10 "STRIDE,Stride Register" hexmask.long.word 0x10 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x14 "STRIDE_SET,Stride Set Register" hexmask.long.word 0x14 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x18 "STRIDE_CLR,Stride Clear Register" hexmask.long.word 0x18 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x1C "STRIDE_TOG,Stride TOG Register" hexmask.long.word 0x1C 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x20 "HEIGHT,Height Register" hexmask.long.word 0x20 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x24 "HEIGHT_SET,Height Set Register" hexmask.long.word 0x24 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x28 "HEIGHT_CLR,Height Clear Register" hexmask.long.word 0x28 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x2C "HEIGHT_TOG,Height TOG Register" hexmask.long.word 0x2C 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x30 "BADDR,Base Address Register" line.long 0x34 "BADDR_SET,Base Address Set Register" line.long 0x38 "BADDR_CLR,Base Address Clear Register" line.long 0x3C "BADDR_TOG,Base Address TOG Register" if ((per.l(ad:0x56050000)&0x10)==0x00) group.long 0x60++0x0F line.long 0x00 "OFFSET,Offset Address Register" bitfld.long 0x00 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." line.long 0x04 "OFFSET_SET,Offset Address Set Register" bitfld.long 0x04 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." line.long 0x08 "OFFSET_CLR,Offset Address Clear Register" bitfld.long 0x08 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." line.long 0x0C "OFFSET_TOG,Offset Address TOG Register" bitfld.long 0x0C 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." else group.long 0x60++0x0F line.long 0x00 "OFFSET,Offset Address Register" bitfld.long 0x00 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" line.long 0x04 "OFFSET_SET,Offset Address Set Register" bitfld.long 0x04 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" line.long 0x08 "OFFSET_CLR,Offset Address Clear Register" bitfld.long 0x08 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" line.long 0x0C "OFFSET_TOG,Offset Address TOG Register" bitfld.long 0x0C 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" endif group.long 0x70++0x0F line.long 0x00 "WIDTH,Width Register" hexmask.long.word 0x00 0.--15. 1. " WIDTH ,Read frame width" line.long 0x04 "WIDTH_SET,Width Set Register" hexmask.long.word 0x04 0.--15. 1. " WIDTH ,Read frame width" line.long 0x08 "WIDTH_CLR,Width Clear Register" hexmask.long.word 0x08 0.--15. 1. " WIDTH ,Read frame width" line.long 0x0C "WIDTH_TOG,Width TOG Register" hexmask.long.word 0x0C 0.--15. 1. " WIDTH ,Read frame width" width 0x0B tree.end tree "PRG2 (Prefetch Resolve Gasket 2)" base ad:0x56060000 width 16. group.long 0x00++0x0F line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x00 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x00 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x00 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x00 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x00 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x00 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" line.long 0x04 "CTRL_SET,Control Set Register" bitfld.long 0x04 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x04 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x04 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x04 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x04 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x04 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x04 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" line.long 0x08 "CTRL_CLR,Control Clear Register" bitfld.long 0x08 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x08 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x08 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x08 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x08 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x08 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x08 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x08 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" line.long 0x0C "CTRL_TOG,Control TOG Register" bitfld.long 0x0C 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x0C 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x0C 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x0C 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x0C 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x0C 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x0C 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x0C 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" rgroup.long 0x10++0x0F line.long 0x00 "STATUS,Status Register" bitfld.long 0x00 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x00 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" line.long 0x04 "STATUS_SET,Status Set Register" bitfld.long 0x04 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x04 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" line.long 0x08 "STATUS_CLR,Status Clear Register" bitfld.long 0x08 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x08 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" line.long 0x0C "STATUS_TOG,Status TOG Register" bitfld.long 0x0C 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x0C 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" group.long 0x20++0x3F line.long 0x00 "REG_UPDATE,REG Update Register" bitfld.long 0x00 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x04 "REG_UPDATE_SET,REG Update Set Register" bitfld.long 0x04 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x08 "REG_UPDATE_CLR,REG Update Clear Register" bitfld.long 0x08 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x0C "REG_UPDATE_TOG,REG Update TOG Register" bitfld.long 0x0C 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x10 "STRIDE,Stride Register" hexmask.long.word 0x10 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x14 "STRIDE_SET,Stride Set Register" hexmask.long.word 0x14 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x18 "STRIDE_CLR,Stride Clear Register" hexmask.long.word 0x18 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x1C "STRIDE_TOG,Stride TOG Register" hexmask.long.word 0x1C 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x20 "HEIGHT,Height Register" hexmask.long.word 0x20 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x24 "HEIGHT_SET,Height Set Register" hexmask.long.word 0x24 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x28 "HEIGHT_CLR,Height Clear Register" hexmask.long.word 0x28 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x2C "HEIGHT_TOG,Height TOG Register" hexmask.long.word 0x2C 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x30 "BADDR,Base Address Register" line.long 0x34 "BADDR_SET,Base Address Set Register" line.long 0x38 "BADDR_CLR,Base Address Clear Register" line.long 0x3C "BADDR_TOG,Base Address TOG Register" if ((per.l(ad:0x56060000)&0x10)==0x00) group.long 0x60++0x0F line.long 0x00 "OFFSET,Offset Address Register" bitfld.long 0x00 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." line.long 0x04 "OFFSET_SET,Offset Address Set Register" bitfld.long 0x04 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." line.long 0x08 "OFFSET_CLR,Offset Address Clear Register" bitfld.long 0x08 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." line.long 0x0C "OFFSET_TOG,Offset Address TOG Register" bitfld.long 0x0C 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." else group.long 0x60++0x0F line.long 0x00 "OFFSET,Offset Address Register" bitfld.long 0x00 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" line.long 0x04 "OFFSET_SET,Offset Address Set Register" bitfld.long 0x04 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" line.long 0x08 "OFFSET_CLR,Offset Address Clear Register" bitfld.long 0x08 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" line.long 0x0C "OFFSET_TOG,Offset Address TOG Register" bitfld.long 0x0C 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" endif group.long 0x70++0x0F line.long 0x00 "WIDTH,Width Register" hexmask.long.word 0x00 0.--15. 1. " WIDTH ,Read frame width" line.long 0x04 "WIDTH_SET,Width Set Register" hexmask.long.word 0x04 0.--15. 1. " WIDTH ,Read frame width" line.long 0x08 "WIDTH_CLR,Width Clear Register" hexmask.long.word 0x08 0.--15. 1. " WIDTH ,Read frame width" line.long 0x0C "WIDTH_TOG,Width TOG Register" hexmask.long.word 0x0C 0.--15. 1. " WIDTH ,Read frame width" width 0x0B tree.end tree "PRG3 (Prefetch Resolve Gasket 3)" base ad:0x56070000 width 16. group.long 0x00++0x0F line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x00 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x00 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x00 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x00 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x00 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x00 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" line.long 0x04 "CTRL_SET,Control Set Register" bitfld.long 0x04 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x04 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x04 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x04 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x04 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x04 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x04 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" line.long 0x08 "CTRL_CLR,Control Clear Register" bitfld.long 0x08 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x08 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x08 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x08 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x08 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x08 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x08 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x08 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" line.long 0x0C "CTRL_TOG,Control TOG Register" bitfld.long 0x0C 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x0C 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x0C 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x0C 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x0C 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x0C 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x0C 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x0C 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" rgroup.long 0x10++0x0F line.long 0x00 "STATUS,Status Register" bitfld.long 0x00 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x00 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" line.long 0x04 "STATUS_SET,Status Set Register" bitfld.long 0x04 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x04 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" line.long 0x08 "STATUS_CLR,Status Clear Register" bitfld.long 0x08 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x08 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" line.long 0x0C "STATUS_TOG,Status TOG Register" bitfld.long 0x0C 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x0C 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" group.long 0x20++0x3F line.long 0x00 "REG_UPDATE,REG Update Register" bitfld.long 0x00 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x04 "REG_UPDATE_SET,REG Update Set Register" bitfld.long 0x04 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x08 "REG_UPDATE_CLR,REG Update Clear Register" bitfld.long 0x08 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x0C "REG_UPDATE_TOG,REG Update TOG Register" bitfld.long 0x0C 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x10 "STRIDE,Stride Register" hexmask.long.word 0x10 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x14 "STRIDE_SET,Stride Set Register" hexmask.long.word 0x14 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x18 "STRIDE_CLR,Stride Clear Register" hexmask.long.word 0x18 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x1C "STRIDE_TOG,Stride TOG Register" hexmask.long.word 0x1C 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x20 "HEIGHT,Height Register" hexmask.long.word 0x20 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x24 "HEIGHT_SET,Height Set Register" hexmask.long.word 0x24 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x28 "HEIGHT_CLR,Height Clear Register" hexmask.long.word 0x28 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x2C "HEIGHT_TOG,Height TOG Register" hexmask.long.word 0x2C 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x30 "BADDR,Base Address Register" line.long 0x34 "BADDR_SET,Base Address Set Register" line.long 0x38 "BADDR_CLR,Base Address Clear Register" line.long 0x3C "BADDR_TOG,Base Address TOG Register" if ((per.l(ad:0x56070000)&0x10)==0x00) group.long 0x60++0x0F line.long 0x00 "OFFSET,Offset Address Register" bitfld.long 0x00 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." line.long 0x04 "OFFSET_SET,Offset Address Set Register" bitfld.long 0x04 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." line.long 0x08 "OFFSET_CLR,Offset Address Clear Register" bitfld.long 0x08 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." line.long 0x0C "OFFSET_TOG,Offset Address TOG Register" bitfld.long 0x0C 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." else group.long 0x60++0x0F line.long 0x00 "OFFSET,Offset Address Register" bitfld.long 0x00 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" line.long 0x04 "OFFSET_SET,Offset Address Set Register" bitfld.long 0x04 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" line.long 0x08 "OFFSET_CLR,Offset Address Clear Register" bitfld.long 0x08 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" line.long 0x0C "OFFSET_TOG,Offset Address TOG Register" bitfld.long 0x0C 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" endif group.long 0x70++0x0F line.long 0x00 "WIDTH,Width Register" hexmask.long.word 0x00 0.--15. 1. " WIDTH ,Read frame width" line.long 0x04 "WIDTH_SET,Width Set Register" hexmask.long.word 0x04 0.--15. 1. " WIDTH ,Read frame width" line.long 0x08 "WIDTH_CLR,Width Clear Register" hexmask.long.word 0x08 0.--15. 1. " WIDTH ,Read frame width" line.long 0x0C "WIDTH_TOG,Width TOG Register" hexmask.long.word 0x0C 0.--15. 1. " WIDTH ,Read frame width" width 0x0B tree.end tree "PRG4 (Prefetch Resolve Gasket 4)" base ad:0x56080000 width 16. group.long 0x00++0x0F line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x00 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x00 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x00 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x00 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x00 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x00 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" line.long 0x04 "CTRL_SET,Control Set Register" bitfld.long 0x04 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x04 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x04 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x04 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x04 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x04 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x04 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" line.long 0x08 "CTRL_CLR,Control Clear Register" bitfld.long 0x08 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x08 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x08 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x08 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x08 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x08 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x08 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x08 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" line.long 0x0C "CTRL_TOG,Control TOG Register" bitfld.long 0x0C 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x0C 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x0C 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x0C 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x0C 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x0C 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x0C 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x0C 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" rgroup.long 0x10++0x0F line.long 0x00 "STATUS,Status Register" bitfld.long 0x00 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x00 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" line.long 0x04 "STATUS_SET,Status Set Register" bitfld.long 0x04 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x04 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" line.long 0x08 "STATUS_CLR,Status Clear Register" bitfld.long 0x08 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x08 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" line.long 0x0C "STATUS_TOG,Status TOG Register" bitfld.long 0x0C 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x0C 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" group.long 0x20++0x3F line.long 0x00 "REG_UPDATE,REG Update Register" bitfld.long 0x00 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x04 "REG_UPDATE_SET,REG Update Set Register" bitfld.long 0x04 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x08 "REG_UPDATE_CLR,REG Update Clear Register" bitfld.long 0x08 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x0C "REG_UPDATE_TOG,REG Update TOG Register" bitfld.long 0x0C 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x10 "STRIDE,Stride Register" hexmask.long.word 0x10 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x14 "STRIDE_SET,Stride Set Register" hexmask.long.word 0x14 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x18 "STRIDE_CLR,Stride Clear Register" hexmask.long.word 0x18 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x1C "STRIDE_TOG,Stride TOG Register" hexmask.long.word 0x1C 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x20 "HEIGHT,Height Register" hexmask.long.word 0x20 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x24 "HEIGHT_SET,Height Set Register" hexmask.long.word 0x24 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x28 "HEIGHT_CLR,Height Clear Register" hexmask.long.word 0x28 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x2C "HEIGHT_TOG,Height TOG Register" hexmask.long.word 0x2C 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x30 "BADDR,Base Address Register" line.long 0x34 "BADDR_SET,Base Address Set Register" line.long 0x38 "BADDR_CLR,Base Address Clear Register" line.long 0x3C "BADDR_TOG,Base Address TOG Register" if ((per.l(ad:0x56080000)&0x10)==0x00) group.long 0x60++0x0F line.long 0x00 "OFFSET,Offset Address Register" bitfld.long 0x00 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." line.long 0x04 "OFFSET_SET,Offset Address Set Register" bitfld.long 0x04 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." line.long 0x08 "OFFSET_CLR,Offset Address Clear Register" bitfld.long 0x08 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." line.long 0x0C "OFFSET_TOG,Offset Address TOG Register" bitfld.long 0x0C 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." else group.long 0x60++0x0F line.long 0x00 "OFFSET,Offset Address Register" bitfld.long 0x00 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" line.long 0x04 "OFFSET_SET,Offset Address Set Register" bitfld.long 0x04 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" line.long 0x08 "OFFSET_CLR,Offset Address Clear Register" bitfld.long 0x08 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" line.long 0x0C "OFFSET_TOG,Offset Address TOG Register" bitfld.long 0x0C 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" endif group.long 0x70++0x0F line.long 0x00 "WIDTH,Width Register" hexmask.long.word 0x00 0.--15. 1. " WIDTH ,Read frame width" line.long 0x04 "WIDTH_SET,Width Set Register" hexmask.long.word 0x04 0.--15. 1. " WIDTH ,Read frame width" line.long 0x08 "WIDTH_CLR,Width Clear Register" hexmask.long.word 0x08 0.--15. 1. " WIDTH ,Read frame width" line.long 0x0C "WIDTH_TOG,Width TOG Register" hexmask.long.word 0x0C 0.--15. 1. " WIDTH ,Read frame width" width 0x0B tree.end tree "PRG5 (Prefetch Resolve Gasket 5)" base ad:0x56090000 width 16. group.long 0x00++0x0F line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x00 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x00 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x00 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x00 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x00 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x00 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" line.long 0x04 "CTRL_SET,Control Set Register" bitfld.long 0x04 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x04 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x04 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x04 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x04 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x04 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x04 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" line.long 0x08 "CTRL_CLR,Control Clear Register" bitfld.long 0x08 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x08 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x08 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x08 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x08 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x08 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x08 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x08 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" line.long 0x0C "CTRL_TOG,Control TOG Register" bitfld.long 0x0C 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x0C 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x0C 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x0C 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x0C 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x0C 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x0C 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x0C 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" rgroup.long 0x10++0x0F line.long 0x00 "STATUS,Status Register" bitfld.long 0x00 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x00 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" line.long 0x04 "STATUS_SET,Status Set Register" bitfld.long 0x04 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x04 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" line.long 0x08 "STATUS_CLR,Status Clear Register" bitfld.long 0x08 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x08 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" line.long 0x0C "STATUS_TOG,Status TOG Register" bitfld.long 0x0C 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x0C 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" group.long 0x20++0x3F line.long 0x00 "REG_UPDATE,REG Update Register" bitfld.long 0x00 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x04 "REG_UPDATE_SET,REG Update Set Register" bitfld.long 0x04 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x08 "REG_UPDATE_CLR,REG Update Clear Register" bitfld.long 0x08 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x0C "REG_UPDATE_TOG,REG Update TOG Register" bitfld.long 0x0C 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x10 "STRIDE,Stride Register" hexmask.long.word 0x10 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x14 "STRIDE_SET,Stride Set Register" hexmask.long.word 0x14 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x18 "STRIDE_CLR,Stride Clear Register" hexmask.long.word 0x18 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x1C "STRIDE_TOG,Stride TOG Register" hexmask.long.word 0x1C 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x20 "HEIGHT,Height Register" hexmask.long.word 0x20 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x24 "HEIGHT_SET,Height Set Register" hexmask.long.word 0x24 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x28 "HEIGHT_CLR,Height Clear Register" hexmask.long.word 0x28 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x2C "HEIGHT_TOG,Height TOG Register" hexmask.long.word 0x2C 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x30 "BADDR,Base Address Register" line.long 0x34 "BADDR_SET,Base Address Set Register" line.long 0x38 "BADDR_CLR,Base Address Clear Register" line.long 0x3C "BADDR_TOG,Base Address TOG Register" if ((per.l(ad:0x56090000)&0x10)==0x00) group.long 0x60++0x0F line.long 0x00 "OFFSET,Offset Address Register" bitfld.long 0x00 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." line.long 0x04 "OFFSET_SET,Offset Address Set Register" bitfld.long 0x04 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." line.long 0x08 "OFFSET_CLR,Offset Address Clear Register" bitfld.long 0x08 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." line.long 0x0C "OFFSET_TOG,Offset Address TOG Register" bitfld.long 0x0C 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." else group.long 0x60++0x0F line.long 0x00 "OFFSET,Offset Address Register" bitfld.long 0x00 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" line.long 0x04 "OFFSET_SET,Offset Address Set Register" bitfld.long 0x04 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" line.long 0x08 "OFFSET_CLR,Offset Address Clear Register" bitfld.long 0x08 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" line.long 0x0C "OFFSET_TOG,Offset Address TOG Register" bitfld.long 0x0C 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" endif group.long 0x70++0x0F line.long 0x00 "WIDTH,Width Register" hexmask.long.word 0x00 0.--15. 1. " WIDTH ,Read frame width" line.long 0x04 "WIDTH_SET,Width Set Register" hexmask.long.word 0x04 0.--15. 1. " WIDTH ,Read frame width" line.long 0x08 "WIDTH_CLR,Width Clear Register" hexmask.long.word 0x08 0.--15. 1. " WIDTH ,Read frame width" line.long 0x0C "WIDTH_TOG,Width TOG Register" hexmask.long.word 0x0C 0.--15. 1. " WIDTH ,Read frame width" width 0x0B tree.end tree "PRG6 (Prefetch Resolve Gasket 6)" base ad:0x560A0000 width 16. group.long 0x00++0x0F line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x00 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x00 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x00 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x00 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x00 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x00 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" line.long 0x04 "CTRL_SET,Control Set Register" bitfld.long 0x04 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x04 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x04 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x04 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x04 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x04 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x04 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" line.long 0x08 "CTRL_CLR,Control Clear Register" bitfld.long 0x08 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x08 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x08 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x08 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x08 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x08 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x08 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x08 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" line.long 0x0C "CTRL_TOG,Control TOG Register" bitfld.long 0x0C 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x0C 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x0C 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x0C 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x0C 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x0C 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x0C 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x0C 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" rgroup.long 0x10++0x0F line.long 0x00 "STATUS,Status Register" bitfld.long 0x00 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x00 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" line.long 0x04 "STATUS_SET,Status Set Register" bitfld.long 0x04 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x04 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" line.long 0x08 "STATUS_CLR,Status Clear Register" bitfld.long 0x08 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x08 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" line.long 0x0C "STATUS_TOG,Status TOG Register" bitfld.long 0x0C 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x0C 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" group.long 0x20++0x3F line.long 0x00 "REG_UPDATE,REG Update Register" bitfld.long 0x00 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x04 "REG_UPDATE_SET,REG Update Set Register" bitfld.long 0x04 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x08 "REG_UPDATE_CLR,REG Update Clear Register" bitfld.long 0x08 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x0C "REG_UPDATE_TOG,REG Update TOG Register" bitfld.long 0x0C 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x10 "STRIDE,Stride Register" hexmask.long.word 0x10 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x14 "STRIDE_SET,Stride Set Register" hexmask.long.word 0x14 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x18 "STRIDE_CLR,Stride Clear Register" hexmask.long.word 0x18 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x1C "STRIDE_TOG,Stride TOG Register" hexmask.long.word 0x1C 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x20 "HEIGHT,Height Register" hexmask.long.word 0x20 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x24 "HEIGHT_SET,Height Set Register" hexmask.long.word 0x24 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x28 "HEIGHT_CLR,Height Clear Register" hexmask.long.word 0x28 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x2C "HEIGHT_TOG,Height TOG Register" hexmask.long.word 0x2C 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x30 "BADDR,Base Address Register" line.long 0x34 "BADDR_SET,Base Address Set Register" line.long 0x38 "BADDR_CLR,Base Address Clear Register" line.long 0x3C "BADDR_TOG,Base Address TOG Register" if ((per.l(ad:0x560A0000)&0x10)==0x00) group.long 0x60++0x0F line.long 0x00 "OFFSET,Offset Address Register" bitfld.long 0x00 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." line.long 0x04 "OFFSET_SET,Offset Address Set Register" bitfld.long 0x04 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." line.long 0x08 "OFFSET_CLR,Offset Address Clear Register" bitfld.long 0x08 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." line.long 0x0C "OFFSET_TOG,Offset Address TOG Register" bitfld.long 0x0C 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." else group.long 0x60++0x0F line.long 0x00 "OFFSET,Offset Address Register" bitfld.long 0x00 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" line.long 0x04 "OFFSET_SET,Offset Address Set Register" bitfld.long 0x04 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" line.long 0x08 "OFFSET_CLR,Offset Address Clear Register" bitfld.long 0x08 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" line.long 0x0C "OFFSET_TOG,Offset Address TOG Register" bitfld.long 0x0C 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" endif group.long 0x70++0x0F line.long 0x00 "WIDTH,Width Register" hexmask.long.word 0x00 0.--15. 1. " WIDTH ,Read frame width" line.long 0x04 "WIDTH_SET,Width Set Register" hexmask.long.word 0x04 0.--15. 1. " WIDTH ,Read frame width" line.long 0x08 "WIDTH_CLR,Width Clear Register" hexmask.long.word 0x08 0.--15. 1. " WIDTH ,Read frame width" line.long 0x0C "WIDTH_TOG,Width TOG Register" hexmask.long.word 0x0C 0.--15. 1. " WIDTH ,Read frame width" width 0x0B tree.end tree "PRG7 (Prefetch Resolve Gasket 7)" base ad:0x560B0000 width 16. group.long 0x00++0x0F line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x00 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x00 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x00 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x00 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x00 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x00 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" line.long 0x04 "CTRL_SET,Control Set Register" bitfld.long 0x04 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x04 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x04 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x04 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x04 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x04 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x04 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" line.long 0x08 "CTRL_CLR,Control Clear Register" bitfld.long 0x08 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x08 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x08 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x08 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x08 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x08 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x08 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x08 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" line.long 0x0C "CTRL_TOG,Control TOG Register" bitfld.long 0x0C 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x0C 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x0C 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x0C 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x0C 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x0C 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x0C 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x0C 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" rgroup.long 0x10++0x0F line.long 0x00 "STATUS,Status Register" bitfld.long 0x00 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x00 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" line.long 0x04 "STATUS_SET,Status Set Register" bitfld.long 0x04 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x04 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" line.long 0x08 "STATUS_CLR,Status Clear Register" bitfld.long 0x08 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x08 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" line.long 0x0C "STATUS_TOG,Status TOG Register" bitfld.long 0x0C 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x0C 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" group.long 0x20++0x3F line.long 0x00 "REG_UPDATE,REG Update Register" bitfld.long 0x00 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x04 "REG_UPDATE_SET,REG Update Set Register" bitfld.long 0x04 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x08 "REG_UPDATE_CLR,REG Update Clear Register" bitfld.long 0x08 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x0C "REG_UPDATE_TOG,REG Update TOG Register" bitfld.long 0x0C 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x10 "STRIDE,Stride Register" hexmask.long.word 0x10 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x14 "STRIDE_SET,Stride Set Register" hexmask.long.word 0x14 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x18 "STRIDE_CLR,Stride Clear Register" hexmask.long.word 0x18 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x1C "STRIDE_TOG,Stride TOG Register" hexmask.long.word 0x1C 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x20 "HEIGHT,Height Register" hexmask.long.word 0x20 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x24 "HEIGHT_SET,Height Set Register" hexmask.long.word 0x24 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x28 "HEIGHT_CLR,Height Clear Register" hexmask.long.word 0x28 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x2C "HEIGHT_TOG,Height TOG Register" hexmask.long.word 0x2C 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x30 "BADDR,Base Address Register" line.long 0x34 "BADDR_SET,Base Address Set Register" line.long 0x38 "BADDR_CLR,Base Address Clear Register" line.long 0x3C "BADDR_TOG,Base Address TOG Register" if ((per.l(ad:0x560B0000)&0x10)==0x00) group.long 0x60++0x0F line.long 0x00 "OFFSET,Offset Address Register" bitfld.long 0x00 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." line.long 0x04 "OFFSET_SET,Offset Address Set Register" bitfld.long 0x04 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." line.long 0x08 "OFFSET_CLR,Offset Address Clear Register" bitfld.long 0x08 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." line.long 0x0C "OFFSET_TOG,Offset Address TOG Register" bitfld.long 0x0C 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." else group.long 0x60++0x0F line.long 0x00 "OFFSET,Offset Address Register" bitfld.long 0x00 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" line.long 0x04 "OFFSET_SET,Offset Address Set Register" bitfld.long 0x04 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" line.long 0x08 "OFFSET_CLR,Offset Address Clear Register" bitfld.long 0x08 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" line.long 0x0C "OFFSET_TOG,Offset Address TOG Register" bitfld.long 0x0C 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" endif group.long 0x70++0x0F line.long 0x00 "WIDTH,Width Register" hexmask.long.word 0x00 0.--15. 1. " WIDTH ,Read frame width" line.long 0x04 "WIDTH_SET,Width Set Register" hexmask.long.word 0x04 0.--15. 1. " WIDTH ,Read frame width" line.long 0x08 "WIDTH_CLR,Width Clear Register" hexmask.long.word 0x08 0.--15. 1. " WIDTH ,Read frame width" line.long 0x0C "WIDTH_TOG,Width TOG Register" hexmask.long.word 0x0C 0.--15. 1. " WIDTH ,Read frame width" width 0x0B tree.end tree "PRG8 (Prefetch Resolve Gasket 8)" base ad:0x560C0000 width 16. group.long 0x00++0x0F line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x00 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x00 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x00 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x00 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x00 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x00 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" line.long 0x04 "CTRL_SET,Control Set Register" bitfld.long 0x04 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x04 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x04 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x04 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x04 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x04 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x04 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" line.long 0x08 "CTRL_CLR,Control Clear Register" bitfld.long 0x08 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x08 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x08 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x08 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x08 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x08 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x08 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x08 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" line.long 0x0C "CTRL_TOG,Control TOG Register" bitfld.long 0x0C 31. " SHADOW_EN ,Shadow register enable" "Disabled,Enabled" bitfld.long 0x0C 30. " SOFTRST ,Software reset" "No reset,Reset" bitfld.long 0x0C 16.--17. " DES_DATA_TYPE ,Destination data type" "32bpp,24bpp,16bpp,8bpp" bitfld.long 0x0C 5. " SHADOW_LOAD_MODE ,Shadow load mode" "EOF,CTX_ENABLE" bitfld.long 0x0C 4. " HANDSHAKE_MODE ,Handshake mode [lines]" "4,8" bitfld.long 0x0C 3. " UV_EN ,U/V buffer enable" "Disabled,Enabled" newline bitfld.long 0x0C 2. " SC_DATA_TYPE ,Source data type [bits per component]" "8,10" bitfld.long 0x0C 0. " BYPASS ,PRG bypass" "Remap to OCRAM,Bypass" rgroup.long 0x10++0x0F line.long 0x00 "STATUS,Status Register" bitfld.long 0x00 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x00 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" line.long 0x04 "STATUS_SET,Status Set Register" bitfld.long 0x04 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x04 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" line.long 0x08 "STATUS_CLR,Status Clear Register" bitfld.long 0x08 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x08 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" line.long 0x0C "STATUS_TOG,Status TOG Register" bitfld.long 0x0C 1. " BUFFER_VALID_B ,RTRAM buffer B status" "Not filled,Filled" bitfld.long 0x0C 0. " BUFFER_VALID_A ,RTRAM buffer A status" "Not filled,Filled" group.long 0x20++0x3F line.long 0x00 "REG_UPDATE,REG Update Register" bitfld.long 0x00 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x04 "REG_UPDATE_SET,REG Update Set Register" bitfld.long 0x04 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x08 "REG_UPDATE_CLR,REG Update Clear Register" bitfld.long 0x08 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x0C "REG_UPDATE_TOG,REG Update TOG Register" bitfld.long 0x0C 0. " REG_UPDATE ,Update all register bits to shadow register" "Not updated,Updated" line.long 0x10 "STRIDE,Stride Register" hexmask.long.word 0x10 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x14 "STRIDE_SET,Stride Set Register" hexmask.long.word 0x14 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x18 "STRIDE_CLR,Stride Clear Register" hexmask.long.word 0x18 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x1C "STRIDE_TOG,Stride TOG Register" hexmask.long.word 0x1C 0.--15. 1. " STRIDE ,Frame buffer width" line.long 0x20 "HEIGHT,Height Register" hexmask.long.word 0x20 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x24 "HEIGHT_SET,Height Set Register" hexmask.long.word 0x24 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x28 "HEIGHT_CLR,Height Clear Register" hexmask.long.word 0x28 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x2C "HEIGHT_TOG,Height TOG Register" hexmask.long.word 0x2C 0.--15. 1. " HEIGHT ,Pixels number in one column of channel frame" line.long 0x30 "BADDR,Base Address Register" line.long 0x34 "BADDR_SET,Base Address Set Register" line.long 0x38 "BADDR_CLR,Base Address Clear Register" line.long 0x3C "BADDR_TOG,Base Address TOG Register" if ((per.l(ad:0x560C0000)&0x10)==0x00) group.long 0x60++0x0F line.long 0x00 "OFFSET,Offset Address Register" bitfld.long 0x00 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." line.long 0x04 "OFFSET_SET,Offset Address Set Register" bitfld.long 0x04 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." line.long 0x08 "OFFSET_CLR,Offset Address Clear Register" bitfld.long 0x08 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." line.long 0x0C "OFFSET_TOG,Offset Address TOG Register" bitfld.long 0x0C 16.--18. " Y ,Offset line crop" "0,1,2,3,?..." else group.long 0x60++0x0F line.long 0x00 "OFFSET,Offset Address Register" bitfld.long 0x00 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" line.long 0x04 "OFFSET_SET,Offset Address Set Register" bitfld.long 0x04 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" line.long 0x08 "OFFSET_CLR,Offset Address Clear Register" bitfld.long 0x08 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" line.long 0x0C "OFFSET_TOG,Offset Address TOG Register" bitfld.long 0x0C 16.--18. " Y ,Offset line crop" "0,1,2,3,4,5,6,7" endif group.long 0x70++0x0F line.long 0x00 "WIDTH,Width Register" hexmask.long.word 0x00 0.--15. 1. " WIDTH ,Read frame width" line.long 0x04 "WIDTH_SET,Width Set Register" hexmask.long.word 0x04 0.--15. 1. " WIDTH ,Read frame width" line.long 0x08 "WIDTH_CLR,Width Clear Register" hexmask.long.word 0x08 0.--15. 1. " WIDTH ,Read frame width" line.long 0x0C "WIDTH_TOG,Width TOG Register" hexmask.long.word 0x0C 0.--15. 1. " WIDTH ,Read frame width" width 0x0B tree.end tree.end tree.open "MIPI DSI/LVDS 0" tree "LPI2C (Low Power Inter-Integrated Circuit)" base ad:0x56226000 width 8. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number" line.long 0x04 "PARAM,Parameter Register" bitfld.long 0x04 8.--11. " MRXFIFO ,Master receive FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x04 0.--3. " MTXFIFO ,Master transmit FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" group.long 0x10++0x13 line.long 0x00 "MCR,Master Control Register" bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset" bitfld.long 0x00 3. " DBGEN ,Debug enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " MEN ,Master enable" "Disabled,Enabled" line.long 0x04 "MSR,Master Status Register" rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x04 24. " MBF ,Master busy flag" "Idle,Busy" eventfld.long 0x04 14. " DMF ,Data match flag" "Not received,Received" eventfld.long 0x04 13. " PLTF ,Pin low timeout flag" "Not occurred/disabled,Occurred" newline eventfld.long 0x04 12. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x04 11. " ALF ,Arbitration lost flag" "Not lost,Lost" eventfld.long 0x04 10. " NDF ,NACK detect flag" "Not detected,Detected" eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected" newline eventfld.long 0x04 8. " EPF ,End packet flag" "Not generated/Repeated,Generated/Repeated" rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "MIER,Master Interrupt Enable Register" bitfld.long 0x08 14. " DMIE ,Data match interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " PLTIE ,Pin low timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " FEIE ,FIFO error interrupt disable" "No,Yes" newline bitfld.long 0x08 11. " ALIE ,Arbitration lost interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " NDIE ,NACK detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " EPIE ,End packet interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "MDER,Master DMA Enable Register" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" line.long 0x10 "MCFGR0,Master Configuration Register 0" bitfld.long 0x10 9. " RDMO ,Receive data match only" "Stored,Discarded" bitfld.long 0x10 8. " CIRFIFO ,Circular FIFO enable" "Disabled,Enabled" bitfld.long 0x10 2. " HRSEL ,Host request select" "HREQ pin,Input trigger" newline bitfld.long 0x10 1. " HRPOL ,Host request polarity" "Active low,Active high" bitfld.long 0x10 0. " HREN ,Host request enable" "Disabled,Enabled" newline if (((per.l(ad:0x56226000+0x10))&0x01)==0x01) rgroup.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Disabled,,1st word = MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "SCL,SCL or SDA" newline bitfld.long 0x00 9. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "No effect,Enabled" bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" else group.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Disabled,,1st word = MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "On SCL low too long,On SCL or SDA low too long" newline bitfld.long 0x00 9. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "No effect,Enabled" bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" endif newline if ((((per.l(ad:0x56226000+0x10))&0x01)==0x00)||(((per.l(ad:0x56226000+0x14))&0x1000000)==0x00)) group.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" else rgroup.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" endif if (((per.l(ad:0x56226000+0x10))&0x01)==0x01) rgroup.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x58++0x03 line.long 0x00 "MFCR,Master FIFO Control Register" bitfld.long 0x00 16.--17. " RXWATER ,Receive FIFO watermark" "0,1,2,3" bitfld.long 0x00 0.--1. " TXWATER ,Transmit FIFO watermark" "0,1,2,3" rgroup.long 0x5C++0x03 line.long 0x00 "MFSR,Master FIFO Status Register" bitfld.long 0x00 16.--18. " RXCOUNT ,Receive FIFO count" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " TXCOUNT ,Transmit FIFO count" "0,1,2,3,4,5,6,7" newline wgroup.long 0x60++0x03 line.long 0x00 "MTDR,Master Transmit Data Register" bitfld.long 0x00 8.--10. " CMD ,Command data" "Transmit,Receive,Generate STOP,Receive and discard,START and transmit,START and transmit (NACK returned),START and transmit (high speed mode),START and transmit high speed mode (NACK returned)" newline hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data" newline hgroup.long 0x70++0x03 hide.long 0x00 "MRDR,Master Receive Data Register" in newline group.long 0x110++0x0F line.long 0x00 "SCR,Slave Control Register" bitfld.long 0x00 9. " RRF ,Receive FIFO reset" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Transmit FIFO reset" "No effect,Reset" bitfld.long 0x00 5. " FILTDZ ,Filter doze enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " FILTEN ,Filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " SEN ,Slave enable" "Disabled,Enabled" line.long 0x04 "SSR,Slave Status Register" rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x04 24. " SBF ,Slave busy flag" "Idle,Busy" rbitfld.long 0x04 15. " SARF ,SMBus alert response flag" "Not detected,Detected" rbitfld.long 0x04 14. " GCF ,General call flag" "Not detected,Detected" newline rbitfld.long 0x04 13. " AM1F ,Address match 1 flag" "Not matched,Matched" rbitfld.long 0x04 12. " AM0F ,Address match 0 flag" "Not matched,Matched" eventfld.long 0x04 11. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x04 10. " BEF ,Bit error flag" "No error,Error" newline eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected" eventfld.long 0x04 8. " RSF ,Repeated start flag" "Not detected,Detected" rbitfld.long 0x04 3. " TAF ,Transmit ACK flag" "Not required,Required" rbitfld.long 0x04 2. " AVF ,Address valid flag" "Invalid,Valid" newline rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "SIER,Slave Interrupt Enable Register" bitfld.long 0x08 15. " SARIE ,SMBus alert response interrupt enable" "Disabled,Enabled" bitfld.long 0x08 14. " GCIE ,General call interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " AM1F ,Address match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " AM0IE ,Address match 0 interrupt disable" "No,Yes" newline bitfld.long 0x08 11. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " BEIE ,Bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 8. " RSIE ,Repeated start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " TAIE ,Transmit ACK interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " AVIE ,Address valid interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "SDER,Slave DMA Enable Register" bitfld.long 0x0C 2. " AVDE ,Address valid DMA enable" "Disabled,Enabled" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" newline if (((per.l(ad:0x56226000+0x110))&0x01)==0x01) rgroup.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration match" "0 (7-bit),0 (10-bit),0 (7-bit) / 1 (7-bit),0 (10-bit) / 1 (10-bit),0 (7-bit) / 1 (10-bit),0 (10-bit) / 1 (7-bit),From 0 (7-bit) to 1 (7-bit),From 0 (10-bit) to 1 (10-bit)" bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" bitfld.long 0x00 12. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return data / clear RDF,Return address / clear AVF" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer,On TDR empty" bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration match" "0 (7-bit),0 (10-bit),0 (7-bit) / 1 (7-bit),0 (10-bit) / 1 (10-bit),0 (7-bit) / 1 (10-bit),0 (10-bit) / 1 (7-bit),From 0 (7-bit) to 1 (7-bit),From 0 (10-bit) to 1 (10-bit)" bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" bitfld.long 0x00 12. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return data / clear RDF,Return address / clear AVF" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer,On TDR empty" bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline if (((per.l(ad:0x56226000+0x110))&0x01)==0x01) rgroup.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" else group.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" endif rgroup.long 0x150++0x03 line.long 0x00 "SASR,Slave Address Status Register" bitfld.long 0x00 14. " ANV ,Address invalid" "No,Yes" hexmask.long.word 0x00 0.--10. 0x01 " RADDR ,Received address" if (((per.l(ad:0x56226000+0x124))&0x08)==0x08) group.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,NACK transmit" "ACK,NACK" else rgroup.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,NACK transmit" "ACK,NACK" endif wgroup.long 0x160++0x03 line.long 0x00 "STDR,Slave Transmit Data Register" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data" rgroup.long 0x170++0x03 line.long 0x00 "SRDR,Slave Receive Data Register" bitfld.long 0x00 15. " SOF ,Start of frame" "Not the first data word,First data word" bitfld.long 0x00 14. " RXEMPTY ,RX empty" "Not empty,Empty" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data receive" width 0x0B tree.end tree "PWM (Pulse Width Modulation)" base ad:0x56224000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO water mark (FIFO empty flag set threshold)" ">= 1 empty slot,>= 2 empty slots,>= 3 empty slots,>= 4 empty slots" bitfld.long 0x00 25. " STOPEN ,Stop mode enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait mode enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " DBGEN ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte data swap control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word data swap control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM output configuration" "Set=rollover/Cleared=comparison,Set=comparison/Cleared=rollover,Disconnected,Disconnected" newline bitfld.long 0x00 16.--17. " CLKSRC ,Clock source select" "Off,IPG_CLK,IPG_CLK_HIGHFREQ,IPG_CLK_32K" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter clock prescaler value" bitfld.long 0x00 3. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample repeat" "Once,Twice,Four times,Eight times" newline bitfld.long 0x00 0. " EN ,PWM enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO write error status" "No error,Error" eventfld.long 0x04 5. " CMP ,Compare event status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over event status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO empty status" "Not empty,Empty" newline rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO available" "No available,1 word,2 words,3 words,4 words,?..." line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO empty interrupt enable" "Disabled,Enabled" line.long 0x0C "PWMSAR,PWM Sample Register" hexmask.long.word 0x0C 0.--15. 1. " SAMPLE ,Sample value" line.long 0x10 "PWMPR,PWM Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Period value" rgroup.long 0x14++0x03 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" width 0x0B tree.end tree "GPIO (General Purpose Input/Output)" base ad:0x56222000 width 11. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data Register" bitfld.long 0x00 31. " DR[31] ,Data bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,Data bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,Data bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,Data bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,Data bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,Data bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,Data bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,Data bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,Data bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,Data bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,Data bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,Data bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,Data bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,Data bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,Data bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,Data bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,Data bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,Data bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,Data bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,Data bit 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,Data bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,Data bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,Data bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,Data bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,Data bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,Data bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,Data bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,Data bit 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,Data bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,Data bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,Data bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,Data bit 0" "Low,High" line.long 0x04 "GDIR,GPIO Direction Register" bitfld.long 0x04 31. " GDIR[31] ,GPIO direction 31 bit" "Input,Output" bitfld.long 0x04 30. " [30] ,GPIO direction 30 bit" "Input,Output" bitfld.long 0x04 29. " [29] ,GPIO direction 29 bit" "Input,Output" bitfld.long 0x04 28. " [28] ,GPIO direction 28 bit" "Input,Output" newline bitfld.long 0x04 27. " [27] ,GPIO direction 27 bit" "Input,Output" bitfld.long 0x04 26. " [26] ,GPIO direction 26 bit" "Input,Output" bitfld.long 0x04 25. " [25] ,GPIO direction 25 bit" "Input,Output" bitfld.long 0x04 24. " [24] ,GPIO direction 24 bit" "Input,Output" newline bitfld.long 0x04 23. " [23] ,GPIO direction 23 bit" "Input,Output" bitfld.long 0x04 22. " [22] ,GPIO direction 22 bit" "Input,Output" bitfld.long 0x04 21. " [21] ,GPIO direction 21 bit" "Input,Output" bitfld.long 0x04 20. " [20] ,GPIO direction 20 bit" "Input,Output" newline bitfld.long 0x04 19. " [19] ,GPIO direction 19 bit" "Input,Output" bitfld.long 0x04 18. " [18] ,GPIO direction 18 bit" "Input,Output" bitfld.long 0x04 17. " [17] ,GPIO direction 17 bit" "Input,Output" bitfld.long 0x04 16. " [16] ,GPIO direction 16 bit" "Input,Output" newline bitfld.long 0x04 15. " [15] ,GPIO direction 15 bit" "Input,Output" bitfld.long 0x04 14. " [14] ,GPIO direction 14 bit" "Input,Output" bitfld.long 0x04 13. " [13] ,GPIO direction 13 bit" "Input,Output" bitfld.long 0x04 12. " [12] ,GPIO direction 12 bit" "Input,Output" newline bitfld.long 0x04 11. " [11] ,GPIO direction 11 bit" "Input,Output" bitfld.long 0x04 10. " [10] ,GPIO direction 10 bit" "Input,Output" bitfld.long 0x04 9. " [9] ,GPIO direction 9 bit" "Input,Output" bitfld.long 0x04 8. " [8] ,GPIO direction 8 bit" "Input,Output" newline bitfld.long 0x04 7. " [7] ,GPIO direction 7 bit" "Input,Output" bitfld.long 0x04 6. " [6] ,GPIO direction 6 bit" "Input,Output" bitfld.long 0x04 5. " [5] ,GPIO direction 5 bit" "Input,Output" bitfld.long 0x04 4. " [4] ,GPIO direction 4 bit" "Input,Output" newline bitfld.long 0x04 3. " [3] ,GPIO direction 3 bit" "Input,Output" bitfld.long 0x04 2. " [2] ,GPIO direction 2 bit" "Input,Output" bitfld.long 0x04 1. " [1] ,GPIO direction 1 bit" "Input,Output" bitfld.long 0x04 0. " [0] ,GPIO direction 0 bit" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO Pad Status Register" bitfld.long 0x00 31. " PSR[31] ,GPIO pad status bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,GPIO pad status bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,GPIO pad status bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,GPIO pad status bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,GPIO pad status bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,GPIO pad status bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,GPIO pad status bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,GPIO pad status bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,GPIO pad status bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,GPIO pad status bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,GPIO pad status bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,GPIO pad status bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,GPIO pad status bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,GPIO pad status bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,GPIO pad status bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,GPIO pad status bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,GPIO pad status bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,GPIO pad status bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,GPIO pad status bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,GPIO pad status bit 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,GPIO pad status bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,GPIO pad status bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,GPIO pad status bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,GPIO pad status bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,GPIO pad status bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,GPIO pad status bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,GPIO pad status bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,GPIO pad status bit 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,GPIO pad status bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,GPIO pad status bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,GPIO pad status bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,GPIO pad status bit 0" "Low,High" group.long 0x0C++0x13 line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1" bitfld.long 0x00 30.--31. " ICR[15] ,Controls the active condition of the interrupt function for GPIO interrupt 15" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 28.--29. " [14] ,Controls the active condition of the interrupt function for GPIO interrupt 14" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 26.--27. " [13] ,Controls the active condition of the interrupt function for GPIO interrupt 13" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 24.--25. " [12] ,Controls the active condition of the interrupt function for GPIO interrupt 12" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 22.--23. " [11] ,Controls the active condition of the interrupt function for GPIO interrupt 11" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 20.--21. " [10] ,Controls the active condition of the interrupt function for GPIO interrupt 10" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 18.--19. " [9] ,Controls the active condition of the interrupt function for GPIO interrupt 9" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 16.--17. " [8] ,Controls the active condition of the interrupt function for GPIO interrupt 8" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 14.--15. " [7] ,Controls the active condition of the interrupt function for GPIO interrupt 7" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 12.--13. " [6] ,Controls the active condition of the interrupt function for GPIO interrupt 6" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 10.--11. " [5] ,Controls the active condition of the interrupt function for GPIO interrupt 5" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 8.--9. " [4] ,Controls the active condition of the interrupt function for GPIO interrupt 4" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 6.--7. " [3] ,Controls the active condition of the interrupt function for GPIO interrupt 3" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 4.--5. " [2] ,Controls the active condition of the interrupt function for GPIO interrupt 2" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 2.--3. " [1] ,Controls the active condition of the interrupt function for GPIO interrupt 1" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 0.--1. " [0] ,Controls the active condition of the interrupt function for GPIO interrupt 0" "Low-level,High-level,Rising-edge,Falling-edge" line.long 0x04 "ICR2,GPIO Interrupt Configuration Register 2" bitfld.long 0x04 30.--31. " [31] ,Controls the active condition of the interrupt function for GPIO interrupt 31" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 28.--29. " [30] ,Controls the active condition of the interrupt function for GPIO interrupt 30" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 26.--27. " [29] ,Controls the active condition of the interrupt function for GPIO interrupt 29" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 24.--25. " [28] ,Controls the active condition of the interrupt function for GPIO interrupt 28" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 22.--23. " [27] ,Controls the active condition of the interrupt function for GPIO interrupt 27" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 20.--21. " [26] ,Controls the active condition of the interrupt function for GPIO interrupt 26" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 18.--19. " [25] ,Controls the active condition of the interrupt function for GPIO interrupt 25" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 16.--17. " [24] ,Controls the active condition of the interrupt function for GPIO interrupt 24" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 14.--15. " [23] ,Controls the active condition of the interrupt function for GPIO interrupt 23" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 12.--13. " [22] ,Controls the active condition of the interrupt function for GPIO interrupt 22" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 10.--11. " [21] ,Controls the active condition of the interrupt function for GPIO interrupt 21" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 8.--9. " [20] ,Controls the active condition of the interrupt function for GPIO interrupt 20" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 6.--7. " [19] ,Controls the active condition of the interrupt function for GPIO interrupt 19" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 4.--5. " [18] ,Controls the active condition of the interrupt function for GPIO interrupt 18" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 2.--3. " [17] ,Controls the active condition of the interrupt function for GPIO interrupt 17" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 0.--1. " [16] ,Controls the active condition of the interrupt function for GPIO interrupt 16" "Low-level,High-level,Rising-edge,Falling-edge" line.long 0x08 "IMR,GPIO Interrupt Mask Register" bitfld.long 0x08 31. " IMR[31] ,Interrupt 31 mask bit" "Disabled,Enabled" bitfld.long 0x08 30. " [30] ,Interrupt 30 mask bit" "Disabled,Enabled" bitfld.long 0x08 29. " [29] ,Interrupt 29 mask bit" "Disabled,Enabled" bitfld.long 0x08 28. " [28] ,Interrupt 28 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 27. " [27] ,Interrupt 27 mask bit" "Disabled,Enabled" bitfld.long 0x08 26. " [26] ,Interrupt 26 mask bit" "Disabled,Enabled" bitfld.long 0x08 25. " [25] ,Interrupt 25 mask bit" "Disabled,Enabled" bitfld.long 0x08 24. " [24] ,Interrupt 24 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 23. " [23] ,Interrupt 23 mask bit" "Disabled,Enabled" bitfld.long 0x08 22. " [22] ,Interrupt 22 mask bit" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Interrupt 21 mask bit" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Interrupt 20 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 19. " [19] ,Interrupt 19 mask bit" "Disabled,Enabled" bitfld.long 0x08 18. " [18] ,Interrupt 18 mask bit" "Disabled,Enabled" bitfld.long 0x08 17. " [17] ,Interrupt 17 mask bit" "Disabled,Enabled" bitfld.long 0x08 16. " [16] ,Interrupt 16 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 15. " [15] ,Interrupt 15 mask bit" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Interrupt 14 mask bit" "Disabled,Enabled" bitfld.long 0x08 13. " [13] ,Interrupt 13 mask bit" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Interrupt 12 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 11. " [11] ,Interrupt 11 mask bit" "Disabled,Enabled" bitfld.long 0x08 10. " [10] ,Interrupt 10 mask bit" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Interrupt 9 mask bit" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Interrupt 8 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Interrupt 7 mask bit" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Interrupt 6 mask bit" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Interrupt 5 mask bit" "Disabled,Enabled" bitfld.long 0x08 4. " [4] ,Interrupt 4 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 3. " [3] ,Interrupt 3 mask bit" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Interrupt 2 mask bit" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Interrupt 1 mask bit" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Interrupt 0 mask bit" "Disabled,Enabled" line.long 0x0C "ISR,GPIO Interrupt Status Register" eventfld.long 0x0C 31. " ISR[31] ,Interrupt 31 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 30. " [30] ,Interrupt 30 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 29. " [29] ,Interrupt 29 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 28. " [28] ,Interrupt 28 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 27. " [27] ,Interrupt 27 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 26. " [26] ,Interrupt 26 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 25. " [25] ,Interrupt 25 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 24. " [24] ,Interrupt 24 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 23. " [23] ,Interrupt 23 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 22. " [22] ,Interrupt 22 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 21. " [21] ,Interrupt 21 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 20. " [20] ,Interrupt 20 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 19. " [19] ,Interrupt 19 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 18. " [18] ,Interrupt 18 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 17. " [17] ,Interrupt 17 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 16. " [16] ,Interrupt 16 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 15. " [15] ,Interrupt 15 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 14. " [14] ,Interrupt 14 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 13. " [13] ,Interrupt 13 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 12. " [12] ,Interrupt 12 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 11. " [11] ,Interrupt 11 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 10. " [10] ,Interrupt 10 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 9. " [9] ,Interrupt 9 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 8. " [8] ,Interrupt 8 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 7. " [7] ,Interrupt 7 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 6. " [6] ,Interrupt 6 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 5. " [5] ,Interrupt 5 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 4. " [4] ,Interrupt 4 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 3. " [3] ,Interrupt 3 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 2. " [2] ,Interrupt 2 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 1. " [1] ,Interrupt 1 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 0. " [0] ,Interrupt 0 status bit" "No interrupt,Interrupt" line.long 0x10 "EDGE_SEL,GPIO Edge Select Register" bitfld.long 0x10 31. " GPIO_EDGE_SEL[31] ,Edge select bit 31" "31 setting,Any edge" bitfld.long 0x10 30. " [30] ,Edge select bit 30" "30 setting,Any edge" bitfld.long 0x10 29. " [29] ,Edge select bit 29" "29 setting,Any edge" bitfld.long 0x10 28. " [28] ,Edge select bit 28" "28 setting,Any edge" newline bitfld.long 0x10 27. " [27] ,Edge select bit 27" "27 setting,Any edge" bitfld.long 0x10 26. " [26] ,Edge select bit 26" "26 setting,Any edge" bitfld.long 0x10 25. " [25] ,Edge select bit 25" "25 setting,Any edge" bitfld.long 0x10 24. " [24] ,Edge select bit 24" "24 setting,Any edge" newline bitfld.long 0x10 23. " [23] ,Edge select bit 23" "23 setting,Any edge" bitfld.long 0x10 22. " [22] ,Edge select bit 22" "22 setting,Any edge" bitfld.long 0x10 21. " [21] ,Edge select bit 21" "21 setting,Any edge" bitfld.long 0x10 20. " [20] ,Edge select bit 20" "20 setting,Any edge" newline bitfld.long 0x10 19. " [19] ,Edge select bit 19" "19 setting,Any edge" bitfld.long 0x10 18. " [18] ,Edge select bit 18" "18 setting,Any edge" bitfld.long 0x10 17. " [17] ,Edge select bit 17" "17 setting,Any edge" bitfld.long 0x10 16. " [16] ,Edge select bit 16" "16 setting,Any edge" newline bitfld.long 0x10 15. " [15] ,Edge select bit 15" "15 setting,Any edge" bitfld.long 0x10 14. " [14] ,Edge select bit 14" "14 setting,Any edge" bitfld.long 0x10 13. " [13] ,Edge select bit 13" "13 setting,Any edge" bitfld.long 0x10 12. " [12] ,Edge select bit 12" "12 setting,Any edge" newline bitfld.long 0x10 11. " [11] ,Edge select bit 11" "11 setting,Any edge" bitfld.long 0x10 10. " [10] ,Edge select bit 10" "10 setting,Any edge" bitfld.long 0x10 9. " [9] ,Edge select bit 9" "9 setting,Any edge" bitfld.long 0x10 8. " [8] ,Edge select bit 8" "8 setting,Any edge" newline bitfld.long 0x10 7. " [7] ,Edge select bit 7" "7 setting,Any edge" bitfld.long 0x10 6. " [6] ,Edge select bit 6" "6 setting,Any edge" bitfld.long 0x10 5. " [5] ,Edge select bit 5" "5 setting,Any edge" bitfld.long 0x10 4. " [4] ,Edge select bit 4" "4 setting,Any edge" newline bitfld.long 0x10 3. " [3] ,Edge select bit 3" "3 setting,Any edge" bitfld.long 0x10 2. " [2] ,Edge select bit 2" "2 setting,Any edge" bitfld.long 0x10 1. " [1] ,Edge select bit 1" "1 setting,Any edge" bitfld.long 0x10 0. " [0] ,Edge select bit 0" "0 setting,Any edge" wgroup.long 0x84++0x0B line.long 0x00 "DR_SET,GPIO Data Register SET Register" bitfld.long 0x00 31. " DR_SET[31] ,Data bit 31 set" "Not set,Set" bitfld.long 0x00 30. " [30] ,Data bit 30 set" "Not set,Set" bitfld.long 0x00 29. " [29] ,Data bit 29 set" "Not set,Set" bitfld.long 0x00 28. " [28] ,Data bit 28 set" "Not set,Set" newline bitfld.long 0x00 27. " [27] ,Data bit 27 set" "Not set,Set" bitfld.long 0x00 26. " [26] ,Data bit 26 set" "Not set,Set" bitfld.long 0x00 25. " [25] ,Data bit 25 set" "Not set,Set" bitfld.long 0x00 24. " [24] ,Data bit 24 set" "Not set,Set" newline bitfld.long 0x00 23. " [23] ,Data bit 23 set" "Not set,Set" bitfld.long 0x00 22. " [22] ,Data bit 22 set" "Not set,Set" bitfld.long 0x00 21. " [21] ,Data bit 21 set" "Not set,Set" bitfld.long 0x00 20. " [20] ,Data bit 20 set" "Not set,Set" newline bitfld.long 0x00 19. " [19] ,Data bit 19 set" "Not set,Set" bitfld.long 0x00 18. " [18] ,Data bit 18 set" "Not set,Set" bitfld.long 0x00 17. " [17] ,Data bit 17 set" "Not set,Set" bitfld.long 0x00 16. " [16] ,Data bit 16 set" "Not set,Set" newline bitfld.long 0x00 15. " [15] ,Data bit 15 set" "Not set,Set" bitfld.long 0x00 14. " [14] ,Data bit 14 set" "Not set,Set" bitfld.long 0x00 13. " [13] ,Data bit 13 set" "Not set,Set" bitfld.long 0x00 12. " [12] ,Data bit 12 set" "Not set,Set" newline bitfld.long 0x00 11. " [11] ,Data bit 11 set" "Not set,Set" bitfld.long 0x00 10. " [10] ,Data bit 10 set" "Not set,Set" bitfld.long 0x00 9. " [9] ,Data bit 9 set" "Not set,Set" bitfld.long 0x00 8. " [8] ,Data bit 8 set" "Not set,Set" newline bitfld.long 0x00 7. " [7] ,Data bit 7 set" "Not set,Set" bitfld.long 0x00 6. " [6] ,Data bit 6 set" "Not set,Set" bitfld.long 0x00 5. " [5] ,Data bit 5 set" "Not set,Set" bitfld.long 0x00 4. " [4] ,Data bit 4 set" "Not set,Set" newline bitfld.long 0x00 3. " [3] ,Data bit 3 set" "Not set,Set" bitfld.long 0x00 2. " [2] ,Data bit 2 set" "Not set,Set" bitfld.long 0x00 1. " [1] ,Data bit 1 set" "Not set,Set" bitfld.long 0x00 0. " [0] ,Data bit 0 set" "Not set,Set" line.long 0x04 "DR_CLEAR,GPIO Data Register CLEAR Register" bitfld.long 0x04 31. " DR_CLEAR[31] ,Data bit 31 clear" "No effect,Clear" bitfld.long 0x04 30. " [30] ,Data bit 30 clear" "No effect,Clear" bitfld.long 0x04 29. " [29] ,Data bit 29 clear" "No effect,Clear" bitfld.long 0x04 28. " [28] ,Data bit 28 clear" "No effect,Clear" newline bitfld.long 0x04 27. " [27] ,Data bit 27 clear" "No effect,Clear" bitfld.long 0x04 26. " [26] ,Data bit 26 clear" "No effect,Clear" bitfld.long 0x04 25. " [25] ,Data bit 25 clear" "No effect,Clear" bitfld.long 0x04 24. " [24] ,Data bit 24 clear" "No effect,Clear" newline bitfld.long 0x04 23. " [23] ,Data bit 23 clear" "No effect,Clear" bitfld.long 0x04 22. " [22] ,Data bit 22 clear" "No effect,Clear" bitfld.long 0x04 21. " [21] ,Data bit 21 clear" "No effect,Clear" bitfld.long 0x04 20. " [20] ,Data bit 20 clear" "No effect,Clear" newline bitfld.long 0x04 19. " [19] ,Data bit 19 clear" "No effect,Clear" bitfld.long 0x04 18. " [18] ,Data bit 18 clear" "No effect,Clear" bitfld.long 0x04 17. " [17] ,Data bit 17 clear" "No effect,Clear" bitfld.long 0x04 16. " [16] ,Data bit 16 clear" "No effect,Clear" newline bitfld.long 0x04 15. " [15] ,Data bit 15 clear" "No effect,Clear" bitfld.long 0x04 14. " [14] ,Data bit 14 clear" "No effect,Clear" bitfld.long 0x04 13. " [13] ,Data bit 13 clear" "No effect,Clear" bitfld.long 0x04 12. " [12] ,Data bit 12 clear" "No effect,Clear" newline bitfld.long 0x04 11. " [11] ,Data bit 11 clear" "No effect,Clear" bitfld.long 0x04 10. " [10] ,Data bit 10 clear" "No effect,Clear" bitfld.long 0x04 9. " [9] ,Data bit 9 clear" "No effect,Clear" bitfld.long 0x04 8. " [8] ,Data bit 8 clear" "No effect,Clear" newline bitfld.long 0x04 7. " [7] ,Data bit 7 clear" "No effect,Clear" bitfld.long 0x04 6. " [6] ,Data bit 6 clear" "No effect,Clear" bitfld.long 0x04 5. " [5] ,Data bit 5 clear" "No effect,Clear" bitfld.long 0x04 4. " [4] ,Data bit 4 clear" "No effect,Clear" newline bitfld.long 0x04 3. " [3] ,Data bit 3 clear" "No effect,Clear" bitfld.long 0x04 2. " [2] ,Data bit 2 clear" "No effect,Clear" bitfld.long 0x04 1. " [1] ,Data bit 1 clear" "No effect,Clear" bitfld.long 0x04 0. " [0] ,Data bit 0 clear" "No effect,Clear" line.long 0x08 "DR_TOGGLE,GPIO Data Register TOGGLE Register" bitfld.long 0x08 31. " DR_TOGGLE[31] ,Data bit 31 toggle" "Not toggled,Toggled" bitfld.long 0x08 30. " [30] ,Data bit 30 toggle" "No effect,Clear" bitfld.long 0x08 29. " [29] ,Data bit 29 toggle" "Not toggled,Toggled" bitfld.long 0x08 28. " [28] ,Data bit 28 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 27. " [27] ,Data bit 27 toggle" "Not toggled,Toggled" bitfld.long 0x08 26. " [26] ,Data bit 26 toggle" "Not toggled,Toggled" bitfld.long 0x08 25. " [25] ,Data bit 25 toggle" "Not toggled,Toggled" bitfld.long 0x08 24. " [24] ,Data bit 24 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 23. " [23] ,Data bit 23 toggle" "Not toggled,Toggled" bitfld.long 0x08 22. " [22] ,Data bit 22 toggle" "Not toggled,Toggled" bitfld.long 0x08 21. " [21] ,Data bit 21 toggle" "Not toggled,Toggled" bitfld.long 0x08 20. " [20] ,Data bit 20 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 19. " [19] ,Data bit 19 toggle" "Not toggled,Toggled" bitfld.long 0x08 18. " [18] ,Data bit 18 toggle" "Not toggled,Toggled" bitfld.long 0x08 17. " [17] ,Data bit 17 toggle" "Not toggled,Toggled" bitfld.long 0x08 16. " [16] ,Data bit 16 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 15. " [15] ,Data bit 15 toggle" "Not toggled,Toggled" bitfld.long 0x08 14. " [14] ,Data bit 14 toggle" "Not toggled,Toggled" bitfld.long 0x08 13. " [13] ,Data bit 13 toggle" "Not toggled,Toggled" bitfld.long 0x08 12. " [12] ,Data bit 12 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 11. " [11] ,Data bit 11 toggle" "Not toggled,Toggled" bitfld.long 0x08 10. " [10] ,Data bit 10 toggle" "Not toggled,Toggled" bitfld.long 0x08 9. " [9] ,Data bit 9 toggle" "Not toggled,Toggled" bitfld.long 0x08 8. " [8] ,Data bit 8 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 7. " [7] ,Data bit 7 toggle" "Not toggled,Toggled" bitfld.long 0x08 6. " [6] ,Data bit 6 toggle" "Not toggled,Toggled" bitfld.long 0x08 5. " [5] ,Data bit 5 toggle" "Not toggled,Toggled" bitfld.long 0x08 4. " [4] ,Data bit 4 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 3. " [3] ,Data bit 3 toggle" "Not toggled,Toggled" bitfld.long 0x08 2. " [2] ,Data bit 2 toggle" "Not toggled,Toggled" bitfld.long 0x08 1. " [1] ,Data bit 1 toggle" "Not toggled,Toggled" bitfld.long 0x08 0. " [0] ,Data bit 0 toggle" "Not toggled,Toggled" width 0x0B tree.end tree.end tree.open "MIPI DSI/LVDS 1" tree "LPI2C (Low Power Inter-Integrated Circuit)" base ad:0x56246000 width 8. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number" line.long 0x04 "PARAM,Parameter Register" bitfld.long 0x04 8.--11. " MRXFIFO ,Master receive FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x04 0.--3. " MTXFIFO ,Master transmit FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" group.long 0x10++0x13 line.long 0x00 "MCR,Master Control Register" bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset" bitfld.long 0x00 3. " DBGEN ,Debug enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " MEN ,Master enable" "Disabled,Enabled" line.long 0x04 "MSR,Master Status Register" rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x04 24. " MBF ,Master busy flag" "Idle,Busy" eventfld.long 0x04 14. " DMF ,Data match flag" "Not received,Received" eventfld.long 0x04 13. " PLTF ,Pin low timeout flag" "Not occurred/disabled,Occurred" newline eventfld.long 0x04 12. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x04 11. " ALF ,Arbitration lost flag" "Not lost,Lost" eventfld.long 0x04 10. " NDF ,NACK detect flag" "Not detected,Detected" eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected" newline eventfld.long 0x04 8. " EPF ,End packet flag" "Not generated/Repeated,Generated/Repeated" rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "MIER,Master Interrupt Enable Register" bitfld.long 0x08 14. " DMIE ,Data match interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " PLTIE ,Pin low timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " FEIE ,FIFO error interrupt disable" "No,Yes" newline bitfld.long 0x08 11. " ALIE ,Arbitration lost interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " NDIE ,NACK detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " EPIE ,End packet interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "MDER,Master DMA Enable Register" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" line.long 0x10 "MCFGR0,Master Configuration Register 0" bitfld.long 0x10 9. " RDMO ,Receive data match only" "Stored,Discarded" bitfld.long 0x10 8. " CIRFIFO ,Circular FIFO enable" "Disabled,Enabled" bitfld.long 0x10 2. " HRSEL ,Host request select" "HREQ pin,Input trigger" newline bitfld.long 0x10 1. " HRPOL ,Host request polarity" "Active low,Active high" bitfld.long 0x10 0. " HREN ,Host request enable" "Disabled,Enabled" newline if (((per.l(ad:0x56246000+0x10))&0x01)==0x01) rgroup.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Disabled,,1st word = MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "SCL,SCL or SDA" newline bitfld.long 0x00 9. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "No effect,Enabled" bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" else group.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Disabled,,1st word = MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "On SCL low too long,On SCL or SDA low too long" newline bitfld.long 0x00 9. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "No effect,Enabled" bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" endif newline if ((((per.l(ad:0x56246000+0x10))&0x01)==0x00)||(((per.l(ad:0x56246000+0x14))&0x1000000)==0x00)) group.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" else rgroup.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" endif if (((per.l(ad:0x56246000+0x10))&0x01)==0x01) rgroup.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x58++0x03 line.long 0x00 "MFCR,Master FIFO Control Register" bitfld.long 0x00 16.--17. " RXWATER ,Receive FIFO watermark" "0,1,2,3" bitfld.long 0x00 0.--1. " TXWATER ,Transmit FIFO watermark" "0,1,2,3" rgroup.long 0x5C++0x03 line.long 0x00 "MFSR,Master FIFO Status Register" bitfld.long 0x00 16.--18. " RXCOUNT ,Receive FIFO count" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " TXCOUNT ,Transmit FIFO count" "0,1,2,3,4,5,6,7" newline wgroup.long 0x60++0x03 line.long 0x00 "MTDR,Master Transmit Data Register" bitfld.long 0x00 8.--10. " CMD ,Command data" "Transmit,Receive,Generate STOP,Receive and discard,START and transmit,START and transmit (NACK returned),START and transmit (high speed mode),START and transmit high speed mode (NACK returned)" newline hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data" newline hgroup.long 0x70++0x03 hide.long 0x00 "MRDR,Master Receive Data Register" in newline group.long 0x110++0x0F line.long 0x00 "SCR,Slave Control Register" bitfld.long 0x00 9. " RRF ,Receive FIFO reset" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Transmit FIFO reset" "No effect,Reset" bitfld.long 0x00 5. " FILTDZ ,Filter doze enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " FILTEN ,Filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " SEN ,Slave enable" "Disabled,Enabled" line.long 0x04 "SSR,Slave Status Register" rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x04 24. " SBF ,Slave busy flag" "Idle,Busy" rbitfld.long 0x04 15. " SARF ,SMBus alert response flag" "Not detected,Detected" rbitfld.long 0x04 14. " GCF ,General call flag" "Not detected,Detected" newline rbitfld.long 0x04 13. " AM1F ,Address match 1 flag" "Not matched,Matched" rbitfld.long 0x04 12. " AM0F ,Address match 0 flag" "Not matched,Matched" eventfld.long 0x04 11. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x04 10. " BEF ,Bit error flag" "No error,Error" newline eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected" eventfld.long 0x04 8. " RSF ,Repeated start flag" "Not detected,Detected" rbitfld.long 0x04 3. " TAF ,Transmit ACK flag" "Not required,Required" rbitfld.long 0x04 2. " AVF ,Address valid flag" "Invalid,Valid" newline rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "SIER,Slave Interrupt Enable Register" bitfld.long 0x08 15. " SARIE ,SMBus alert response interrupt enable" "Disabled,Enabled" bitfld.long 0x08 14. " GCIE ,General call interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " AM1F ,Address match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " AM0IE ,Address match 0 interrupt disable" "No,Yes" newline bitfld.long 0x08 11. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " BEIE ,Bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 8. " RSIE ,Repeated start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " TAIE ,Transmit ACK interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " AVIE ,Address valid interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "SDER,Slave DMA Enable Register" bitfld.long 0x0C 2. " AVDE ,Address valid DMA enable" "Disabled,Enabled" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" newline if (((per.l(ad:0x56246000+0x110))&0x01)==0x01) rgroup.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration match" "0 (7-bit),0 (10-bit),0 (7-bit) / 1 (7-bit),0 (10-bit) / 1 (10-bit),0 (7-bit) / 1 (10-bit),0 (10-bit) / 1 (7-bit),From 0 (7-bit) to 1 (7-bit),From 0 (10-bit) to 1 (10-bit)" bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" bitfld.long 0x00 12. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return data / clear RDF,Return address / clear AVF" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer,On TDR empty" bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration match" "0 (7-bit),0 (10-bit),0 (7-bit) / 1 (7-bit),0 (10-bit) / 1 (10-bit),0 (7-bit) / 1 (10-bit),0 (10-bit) / 1 (7-bit),From 0 (7-bit) to 1 (7-bit),From 0 (10-bit) to 1 (10-bit)" bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" bitfld.long 0x00 12. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return data / clear RDF,Return address / clear AVF" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer,On TDR empty" bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline if (((per.l(ad:0x56246000+0x110))&0x01)==0x01) rgroup.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" else group.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" endif rgroup.long 0x150++0x03 line.long 0x00 "SASR,Slave Address Status Register" bitfld.long 0x00 14. " ANV ,Address invalid" "No,Yes" hexmask.long.word 0x00 0.--10. 0x01 " RADDR ,Received address" if (((per.l(ad:0x56246000+0x124))&0x08)==0x08) group.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,NACK transmit" "ACK,NACK" else rgroup.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,NACK transmit" "ACK,NACK" endif wgroup.long 0x160++0x03 line.long 0x00 "STDR,Slave Transmit Data Register" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data" rgroup.long 0x170++0x03 line.long 0x00 "SRDR,Slave Receive Data Register" bitfld.long 0x00 15. " SOF ,Start of frame" "Not the first data word,First data word" bitfld.long 0x00 14. " RXEMPTY ,RX empty" "Not empty,Empty" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data receive" width 0x0B tree.end tree "PWM (Pulse Width Modulation)" base ad:0x56244000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO water mark (FIFO empty flag set threshold)" ">= 1 empty slot,>= 2 empty slots,>= 3 empty slots,>= 4 empty slots" bitfld.long 0x00 25. " STOPEN ,Stop mode enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait mode enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " DBGEN ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte data swap control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word data swap control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM output configuration" "Set=rollover/Cleared=comparison,Set=comparison/Cleared=rollover,Disconnected,Disconnected" newline bitfld.long 0x00 16.--17. " CLKSRC ,Clock source select" "Off,IPG_CLK,IPG_CLK_HIGHFREQ,IPG_CLK_32K" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter clock prescaler value" bitfld.long 0x00 3. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample repeat" "Once,Twice,Four times,Eight times" newline bitfld.long 0x00 0. " EN ,PWM enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO write error status" "No error,Error" eventfld.long 0x04 5. " CMP ,Compare event status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over event status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO empty status" "Not empty,Empty" newline rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO available" "No available,1 word,2 words,3 words,4 words,?..." line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO empty interrupt enable" "Disabled,Enabled" line.long 0x0C "PWMSAR,PWM Sample Register" hexmask.long.word 0x0C 0.--15. 1. " SAMPLE ,Sample value" line.long 0x10 "PWMPR,PWM Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Period value" rgroup.long 0x14++0x03 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" width 0x0B tree.end tree "GPIO (General Purpose Input/Output)" base ad:0x56242000 width 11. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data Register" bitfld.long 0x00 31. " DR[31] ,Data bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,Data bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,Data bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,Data bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,Data bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,Data bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,Data bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,Data bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,Data bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,Data bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,Data bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,Data bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,Data bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,Data bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,Data bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,Data bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,Data bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,Data bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,Data bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,Data bit 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,Data bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,Data bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,Data bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,Data bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,Data bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,Data bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,Data bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,Data bit 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,Data bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,Data bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,Data bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,Data bit 0" "Low,High" line.long 0x04 "GDIR,GPIO Direction Register" bitfld.long 0x04 31. " GDIR[31] ,GPIO direction 31 bit" "Input,Output" bitfld.long 0x04 30. " [30] ,GPIO direction 30 bit" "Input,Output" bitfld.long 0x04 29. " [29] ,GPIO direction 29 bit" "Input,Output" bitfld.long 0x04 28. " [28] ,GPIO direction 28 bit" "Input,Output" newline bitfld.long 0x04 27. " [27] ,GPIO direction 27 bit" "Input,Output" bitfld.long 0x04 26. " [26] ,GPIO direction 26 bit" "Input,Output" bitfld.long 0x04 25. " [25] ,GPIO direction 25 bit" "Input,Output" bitfld.long 0x04 24. " [24] ,GPIO direction 24 bit" "Input,Output" newline bitfld.long 0x04 23. " [23] ,GPIO direction 23 bit" "Input,Output" bitfld.long 0x04 22. " [22] ,GPIO direction 22 bit" "Input,Output" bitfld.long 0x04 21. " [21] ,GPIO direction 21 bit" "Input,Output" bitfld.long 0x04 20. " [20] ,GPIO direction 20 bit" "Input,Output" newline bitfld.long 0x04 19. " [19] ,GPIO direction 19 bit" "Input,Output" bitfld.long 0x04 18. " [18] ,GPIO direction 18 bit" "Input,Output" bitfld.long 0x04 17. " [17] ,GPIO direction 17 bit" "Input,Output" bitfld.long 0x04 16. " [16] ,GPIO direction 16 bit" "Input,Output" newline bitfld.long 0x04 15. " [15] ,GPIO direction 15 bit" "Input,Output" bitfld.long 0x04 14. " [14] ,GPIO direction 14 bit" "Input,Output" bitfld.long 0x04 13. " [13] ,GPIO direction 13 bit" "Input,Output" bitfld.long 0x04 12. " [12] ,GPIO direction 12 bit" "Input,Output" newline bitfld.long 0x04 11. " [11] ,GPIO direction 11 bit" "Input,Output" bitfld.long 0x04 10. " [10] ,GPIO direction 10 bit" "Input,Output" bitfld.long 0x04 9. " [9] ,GPIO direction 9 bit" "Input,Output" bitfld.long 0x04 8. " [8] ,GPIO direction 8 bit" "Input,Output" newline bitfld.long 0x04 7. " [7] ,GPIO direction 7 bit" "Input,Output" bitfld.long 0x04 6. " [6] ,GPIO direction 6 bit" "Input,Output" bitfld.long 0x04 5. " [5] ,GPIO direction 5 bit" "Input,Output" bitfld.long 0x04 4. " [4] ,GPIO direction 4 bit" "Input,Output" newline bitfld.long 0x04 3. " [3] ,GPIO direction 3 bit" "Input,Output" bitfld.long 0x04 2. " [2] ,GPIO direction 2 bit" "Input,Output" bitfld.long 0x04 1. " [1] ,GPIO direction 1 bit" "Input,Output" bitfld.long 0x04 0. " [0] ,GPIO direction 0 bit" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO Pad Status Register" bitfld.long 0x00 31. " PSR[31] ,GPIO pad status bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,GPIO pad status bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,GPIO pad status bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,GPIO pad status bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,GPIO pad status bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,GPIO pad status bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,GPIO pad status bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,GPIO pad status bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,GPIO pad status bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,GPIO pad status bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,GPIO pad status bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,GPIO pad status bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,GPIO pad status bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,GPIO pad status bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,GPIO pad status bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,GPIO pad status bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,GPIO pad status bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,GPIO pad status bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,GPIO pad status bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,GPIO pad status bit 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,GPIO pad status bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,GPIO pad status bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,GPIO pad status bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,GPIO pad status bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,GPIO pad status bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,GPIO pad status bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,GPIO pad status bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,GPIO pad status bit 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,GPIO pad status bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,GPIO pad status bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,GPIO pad status bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,GPIO pad status bit 0" "Low,High" group.long 0x0C++0x13 line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1" bitfld.long 0x00 30.--31. " ICR[15] ,Controls the active condition of the interrupt function for GPIO interrupt 15" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 28.--29. " [14] ,Controls the active condition of the interrupt function for GPIO interrupt 14" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 26.--27. " [13] ,Controls the active condition of the interrupt function for GPIO interrupt 13" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 24.--25. " [12] ,Controls the active condition of the interrupt function for GPIO interrupt 12" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 22.--23. " [11] ,Controls the active condition of the interrupt function for GPIO interrupt 11" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 20.--21. " [10] ,Controls the active condition of the interrupt function for GPIO interrupt 10" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 18.--19. " [9] ,Controls the active condition of the interrupt function for GPIO interrupt 9" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 16.--17. " [8] ,Controls the active condition of the interrupt function for GPIO interrupt 8" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 14.--15. " [7] ,Controls the active condition of the interrupt function for GPIO interrupt 7" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 12.--13. " [6] ,Controls the active condition of the interrupt function for GPIO interrupt 6" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 10.--11. " [5] ,Controls the active condition of the interrupt function for GPIO interrupt 5" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 8.--9. " [4] ,Controls the active condition of the interrupt function for GPIO interrupt 4" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 6.--7. " [3] ,Controls the active condition of the interrupt function for GPIO interrupt 3" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 4.--5. " [2] ,Controls the active condition of the interrupt function for GPIO interrupt 2" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 2.--3. " [1] ,Controls the active condition of the interrupt function for GPIO interrupt 1" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 0.--1. " [0] ,Controls the active condition of the interrupt function for GPIO interrupt 0" "Low-level,High-level,Rising-edge,Falling-edge" line.long 0x04 "ICR2,GPIO Interrupt Configuration Register 2" bitfld.long 0x04 30.--31. " [31] ,Controls the active condition of the interrupt function for GPIO interrupt 31" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 28.--29. " [30] ,Controls the active condition of the interrupt function for GPIO interrupt 30" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 26.--27. " [29] ,Controls the active condition of the interrupt function for GPIO interrupt 29" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 24.--25. " [28] ,Controls the active condition of the interrupt function for GPIO interrupt 28" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 22.--23. " [27] ,Controls the active condition of the interrupt function for GPIO interrupt 27" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 20.--21. " [26] ,Controls the active condition of the interrupt function for GPIO interrupt 26" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 18.--19. " [25] ,Controls the active condition of the interrupt function for GPIO interrupt 25" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 16.--17. " [24] ,Controls the active condition of the interrupt function for GPIO interrupt 24" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 14.--15. " [23] ,Controls the active condition of the interrupt function for GPIO interrupt 23" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 12.--13. " [22] ,Controls the active condition of the interrupt function for GPIO interrupt 22" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 10.--11. " [21] ,Controls the active condition of the interrupt function for GPIO interrupt 21" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 8.--9. " [20] ,Controls the active condition of the interrupt function for GPIO interrupt 20" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 6.--7. " [19] ,Controls the active condition of the interrupt function for GPIO interrupt 19" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 4.--5. " [18] ,Controls the active condition of the interrupt function for GPIO interrupt 18" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 2.--3. " [17] ,Controls the active condition of the interrupt function for GPIO interrupt 17" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 0.--1. " [16] ,Controls the active condition of the interrupt function for GPIO interrupt 16" "Low-level,High-level,Rising-edge,Falling-edge" line.long 0x08 "IMR,GPIO Interrupt Mask Register" bitfld.long 0x08 31. " IMR[31] ,Interrupt 31 mask bit" "Disabled,Enabled" bitfld.long 0x08 30. " [30] ,Interrupt 30 mask bit" "Disabled,Enabled" bitfld.long 0x08 29. " [29] ,Interrupt 29 mask bit" "Disabled,Enabled" bitfld.long 0x08 28. " [28] ,Interrupt 28 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 27. " [27] ,Interrupt 27 mask bit" "Disabled,Enabled" bitfld.long 0x08 26. " [26] ,Interrupt 26 mask bit" "Disabled,Enabled" bitfld.long 0x08 25. " [25] ,Interrupt 25 mask bit" "Disabled,Enabled" bitfld.long 0x08 24. " [24] ,Interrupt 24 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 23. " [23] ,Interrupt 23 mask bit" "Disabled,Enabled" bitfld.long 0x08 22. " [22] ,Interrupt 22 mask bit" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Interrupt 21 mask bit" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Interrupt 20 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 19. " [19] ,Interrupt 19 mask bit" "Disabled,Enabled" bitfld.long 0x08 18. " [18] ,Interrupt 18 mask bit" "Disabled,Enabled" bitfld.long 0x08 17. " [17] ,Interrupt 17 mask bit" "Disabled,Enabled" bitfld.long 0x08 16. " [16] ,Interrupt 16 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 15. " [15] ,Interrupt 15 mask bit" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Interrupt 14 mask bit" "Disabled,Enabled" bitfld.long 0x08 13. " [13] ,Interrupt 13 mask bit" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Interrupt 12 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 11. " [11] ,Interrupt 11 mask bit" "Disabled,Enabled" bitfld.long 0x08 10. " [10] ,Interrupt 10 mask bit" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Interrupt 9 mask bit" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Interrupt 8 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Interrupt 7 mask bit" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Interrupt 6 mask bit" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Interrupt 5 mask bit" "Disabled,Enabled" bitfld.long 0x08 4. " [4] ,Interrupt 4 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 3. " [3] ,Interrupt 3 mask bit" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Interrupt 2 mask bit" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Interrupt 1 mask bit" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Interrupt 0 mask bit" "Disabled,Enabled" line.long 0x0C "ISR,GPIO Interrupt Status Register" eventfld.long 0x0C 31. " ISR[31] ,Interrupt 31 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 30. " [30] ,Interrupt 30 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 29. " [29] ,Interrupt 29 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 28. " [28] ,Interrupt 28 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 27. " [27] ,Interrupt 27 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 26. " [26] ,Interrupt 26 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 25. " [25] ,Interrupt 25 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 24. " [24] ,Interrupt 24 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 23. " [23] ,Interrupt 23 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 22. " [22] ,Interrupt 22 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 21. " [21] ,Interrupt 21 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 20. " [20] ,Interrupt 20 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 19. " [19] ,Interrupt 19 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 18. " [18] ,Interrupt 18 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 17. " [17] ,Interrupt 17 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 16. " [16] ,Interrupt 16 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 15. " [15] ,Interrupt 15 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 14. " [14] ,Interrupt 14 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 13. " [13] ,Interrupt 13 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 12. " [12] ,Interrupt 12 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 11. " [11] ,Interrupt 11 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 10. " [10] ,Interrupt 10 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 9. " [9] ,Interrupt 9 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 8. " [8] ,Interrupt 8 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 7. " [7] ,Interrupt 7 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 6. " [6] ,Interrupt 6 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 5. " [5] ,Interrupt 5 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 4. " [4] ,Interrupt 4 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 3. " [3] ,Interrupt 3 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 2. " [2] ,Interrupt 2 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 1. " [1] ,Interrupt 1 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 0. " [0] ,Interrupt 0 status bit" "No interrupt,Interrupt" line.long 0x10 "EDGE_SEL,GPIO Edge Select Register" bitfld.long 0x10 31. " GPIO_EDGE_SEL[31] ,Edge select bit 31" "31 setting,Any edge" bitfld.long 0x10 30. " [30] ,Edge select bit 30" "30 setting,Any edge" bitfld.long 0x10 29. " [29] ,Edge select bit 29" "29 setting,Any edge" bitfld.long 0x10 28. " [28] ,Edge select bit 28" "28 setting,Any edge" newline bitfld.long 0x10 27. " [27] ,Edge select bit 27" "27 setting,Any edge" bitfld.long 0x10 26. " [26] ,Edge select bit 26" "26 setting,Any edge" bitfld.long 0x10 25. " [25] ,Edge select bit 25" "25 setting,Any edge" bitfld.long 0x10 24. " [24] ,Edge select bit 24" "24 setting,Any edge" newline bitfld.long 0x10 23. " [23] ,Edge select bit 23" "23 setting,Any edge" bitfld.long 0x10 22. " [22] ,Edge select bit 22" "22 setting,Any edge" bitfld.long 0x10 21. " [21] ,Edge select bit 21" "21 setting,Any edge" bitfld.long 0x10 20. " [20] ,Edge select bit 20" "20 setting,Any edge" newline bitfld.long 0x10 19. " [19] ,Edge select bit 19" "19 setting,Any edge" bitfld.long 0x10 18. " [18] ,Edge select bit 18" "18 setting,Any edge" bitfld.long 0x10 17. " [17] ,Edge select bit 17" "17 setting,Any edge" bitfld.long 0x10 16. " [16] ,Edge select bit 16" "16 setting,Any edge" newline bitfld.long 0x10 15. " [15] ,Edge select bit 15" "15 setting,Any edge" bitfld.long 0x10 14. " [14] ,Edge select bit 14" "14 setting,Any edge" bitfld.long 0x10 13. " [13] ,Edge select bit 13" "13 setting,Any edge" bitfld.long 0x10 12. " [12] ,Edge select bit 12" "12 setting,Any edge" newline bitfld.long 0x10 11. " [11] ,Edge select bit 11" "11 setting,Any edge" bitfld.long 0x10 10. " [10] ,Edge select bit 10" "10 setting,Any edge" bitfld.long 0x10 9. " [9] ,Edge select bit 9" "9 setting,Any edge" bitfld.long 0x10 8. " [8] ,Edge select bit 8" "8 setting,Any edge" newline bitfld.long 0x10 7. " [7] ,Edge select bit 7" "7 setting,Any edge" bitfld.long 0x10 6. " [6] ,Edge select bit 6" "6 setting,Any edge" bitfld.long 0x10 5. " [5] ,Edge select bit 5" "5 setting,Any edge" bitfld.long 0x10 4. " [4] ,Edge select bit 4" "4 setting,Any edge" newline bitfld.long 0x10 3. " [3] ,Edge select bit 3" "3 setting,Any edge" bitfld.long 0x10 2. " [2] ,Edge select bit 2" "2 setting,Any edge" bitfld.long 0x10 1. " [1] ,Edge select bit 1" "1 setting,Any edge" bitfld.long 0x10 0. " [0] ,Edge select bit 0" "0 setting,Any edge" wgroup.long 0x84++0x0B line.long 0x00 "DR_SET,GPIO Data Register SET Register" bitfld.long 0x00 31. " DR_SET[31] ,Data bit 31 set" "Not set,Set" bitfld.long 0x00 30. " [30] ,Data bit 30 set" "Not set,Set" bitfld.long 0x00 29. " [29] ,Data bit 29 set" "Not set,Set" bitfld.long 0x00 28. " [28] ,Data bit 28 set" "Not set,Set" newline bitfld.long 0x00 27. " [27] ,Data bit 27 set" "Not set,Set" bitfld.long 0x00 26. " [26] ,Data bit 26 set" "Not set,Set" bitfld.long 0x00 25. " [25] ,Data bit 25 set" "Not set,Set" bitfld.long 0x00 24. " [24] ,Data bit 24 set" "Not set,Set" newline bitfld.long 0x00 23. " [23] ,Data bit 23 set" "Not set,Set" bitfld.long 0x00 22. " [22] ,Data bit 22 set" "Not set,Set" bitfld.long 0x00 21. " [21] ,Data bit 21 set" "Not set,Set" bitfld.long 0x00 20. " [20] ,Data bit 20 set" "Not set,Set" newline bitfld.long 0x00 19. " [19] ,Data bit 19 set" "Not set,Set" bitfld.long 0x00 18. " [18] ,Data bit 18 set" "Not set,Set" bitfld.long 0x00 17. " [17] ,Data bit 17 set" "Not set,Set" bitfld.long 0x00 16. " [16] ,Data bit 16 set" "Not set,Set" newline bitfld.long 0x00 15. " [15] ,Data bit 15 set" "Not set,Set" bitfld.long 0x00 14. " [14] ,Data bit 14 set" "Not set,Set" bitfld.long 0x00 13. " [13] ,Data bit 13 set" "Not set,Set" bitfld.long 0x00 12. " [12] ,Data bit 12 set" "Not set,Set" newline bitfld.long 0x00 11. " [11] ,Data bit 11 set" "Not set,Set" bitfld.long 0x00 10. " [10] ,Data bit 10 set" "Not set,Set" bitfld.long 0x00 9. " [9] ,Data bit 9 set" "Not set,Set" bitfld.long 0x00 8. " [8] ,Data bit 8 set" "Not set,Set" newline bitfld.long 0x00 7. " [7] ,Data bit 7 set" "Not set,Set" bitfld.long 0x00 6. " [6] ,Data bit 6 set" "Not set,Set" bitfld.long 0x00 5. " [5] ,Data bit 5 set" "Not set,Set" bitfld.long 0x00 4. " [4] ,Data bit 4 set" "Not set,Set" newline bitfld.long 0x00 3. " [3] ,Data bit 3 set" "Not set,Set" bitfld.long 0x00 2. " [2] ,Data bit 2 set" "Not set,Set" bitfld.long 0x00 1. " [1] ,Data bit 1 set" "Not set,Set" bitfld.long 0x00 0. " [0] ,Data bit 0 set" "Not set,Set" line.long 0x04 "DR_CLEAR,GPIO Data Register CLEAR Register" bitfld.long 0x04 31. " DR_CLEAR[31] ,Data bit 31 clear" "No effect,Clear" bitfld.long 0x04 30. " [30] ,Data bit 30 clear" "No effect,Clear" bitfld.long 0x04 29. " [29] ,Data bit 29 clear" "No effect,Clear" bitfld.long 0x04 28. " [28] ,Data bit 28 clear" "No effect,Clear" newline bitfld.long 0x04 27. " [27] ,Data bit 27 clear" "No effect,Clear" bitfld.long 0x04 26. " [26] ,Data bit 26 clear" "No effect,Clear" bitfld.long 0x04 25. " [25] ,Data bit 25 clear" "No effect,Clear" bitfld.long 0x04 24. " [24] ,Data bit 24 clear" "No effect,Clear" newline bitfld.long 0x04 23. " [23] ,Data bit 23 clear" "No effect,Clear" bitfld.long 0x04 22. " [22] ,Data bit 22 clear" "No effect,Clear" bitfld.long 0x04 21. " [21] ,Data bit 21 clear" "No effect,Clear" bitfld.long 0x04 20. " [20] ,Data bit 20 clear" "No effect,Clear" newline bitfld.long 0x04 19. " [19] ,Data bit 19 clear" "No effect,Clear" bitfld.long 0x04 18. " [18] ,Data bit 18 clear" "No effect,Clear" bitfld.long 0x04 17. " [17] ,Data bit 17 clear" "No effect,Clear" bitfld.long 0x04 16. " [16] ,Data bit 16 clear" "No effect,Clear" newline bitfld.long 0x04 15. " [15] ,Data bit 15 clear" "No effect,Clear" bitfld.long 0x04 14. " [14] ,Data bit 14 clear" "No effect,Clear" bitfld.long 0x04 13. " [13] ,Data bit 13 clear" "No effect,Clear" bitfld.long 0x04 12. " [12] ,Data bit 12 clear" "No effect,Clear" newline bitfld.long 0x04 11. " [11] ,Data bit 11 clear" "No effect,Clear" bitfld.long 0x04 10. " [10] ,Data bit 10 clear" "No effect,Clear" bitfld.long 0x04 9. " [9] ,Data bit 9 clear" "No effect,Clear" bitfld.long 0x04 8. " [8] ,Data bit 8 clear" "No effect,Clear" newline bitfld.long 0x04 7. " [7] ,Data bit 7 clear" "No effect,Clear" bitfld.long 0x04 6. " [6] ,Data bit 6 clear" "No effect,Clear" bitfld.long 0x04 5. " [5] ,Data bit 5 clear" "No effect,Clear" bitfld.long 0x04 4. " [4] ,Data bit 4 clear" "No effect,Clear" newline bitfld.long 0x04 3. " [3] ,Data bit 3 clear" "No effect,Clear" bitfld.long 0x04 2. " [2] ,Data bit 2 clear" "No effect,Clear" bitfld.long 0x04 1. " [1] ,Data bit 1 clear" "No effect,Clear" bitfld.long 0x04 0. " [0] ,Data bit 0 clear" "No effect,Clear" line.long 0x08 "DR_TOGGLE,GPIO Data Register TOGGLE Register" bitfld.long 0x08 31. " DR_TOGGLE[31] ,Data bit 31 toggle" "Not toggled,Toggled" bitfld.long 0x08 30. " [30] ,Data bit 30 toggle" "No effect,Clear" bitfld.long 0x08 29. " [29] ,Data bit 29 toggle" "Not toggled,Toggled" bitfld.long 0x08 28. " [28] ,Data bit 28 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 27. " [27] ,Data bit 27 toggle" "Not toggled,Toggled" bitfld.long 0x08 26. " [26] ,Data bit 26 toggle" "Not toggled,Toggled" bitfld.long 0x08 25. " [25] ,Data bit 25 toggle" "Not toggled,Toggled" bitfld.long 0x08 24. " [24] ,Data bit 24 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 23. " [23] ,Data bit 23 toggle" "Not toggled,Toggled" bitfld.long 0x08 22. " [22] ,Data bit 22 toggle" "Not toggled,Toggled" bitfld.long 0x08 21. " [21] ,Data bit 21 toggle" "Not toggled,Toggled" bitfld.long 0x08 20. " [20] ,Data bit 20 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 19. " [19] ,Data bit 19 toggle" "Not toggled,Toggled" bitfld.long 0x08 18. " [18] ,Data bit 18 toggle" "Not toggled,Toggled" bitfld.long 0x08 17. " [17] ,Data bit 17 toggle" "Not toggled,Toggled" bitfld.long 0x08 16. " [16] ,Data bit 16 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 15. " [15] ,Data bit 15 toggle" "Not toggled,Toggled" bitfld.long 0x08 14. " [14] ,Data bit 14 toggle" "Not toggled,Toggled" bitfld.long 0x08 13. " [13] ,Data bit 13 toggle" "Not toggled,Toggled" bitfld.long 0x08 12. " [12] ,Data bit 12 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 11. " [11] ,Data bit 11 toggle" "Not toggled,Toggled" bitfld.long 0x08 10. " [10] ,Data bit 10 toggle" "Not toggled,Toggled" bitfld.long 0x08 9. " [9] ,Data bit 9 toggle" "Not toggled,Toggled" bitfld.long 0x08 8. " [8] ,Data bit 8 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 7. " [7] ,Data bit 7 toggle" "Not toggled,Toggled" bitfld.long 0x08 6. " [6] ,Data bit 6 toggle" "Not toggled,Toggled" bitfld.long 0x08 5. " [5] ,Data bit 5 toggle" "Not toggled,Toggled" bitfld.long 0x08 4. " [4] ,Data bit 4 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 3. " [3] ,Data bit 3 toggle" "Not toggled,Toggled" bitfld.long 0x08 2. " [2] ,Data bit 2 toggle" "Not toggled,Toggled" bitfld.long 0x08 1. " [1] ,Data bit 1 toggle" "Not toggled,Toggled" bitfld.long 0x08 0. " [0] ,Data bit 0 toggle" "Not toggled,Toggled" width 0x0B tree.end tree.end tree.end tree.open "Audio" tree "ACM (Audio Clock Mux)" base ad:0x59000000 width 15. group.long 0xE00000++0x03 line.long 0x00 "AUD_CLK0,ACM_AUD_CLK0 Register" bitfld.long 0x00 0.--4 " SEL ,Select" "ADMA_SLSLICE2,ADMA_SLSLICE3,EXT_AUD_MCLK0,EXT_AUD_MCLK1,ESAI0_RX_CLK,ESAI0_RX_HF_CLKK,ESAI0_TX_CLK,ESAI0_TX_HF_CLK,SPDIF0_RX,SAI0_RX_BCLK,SAI0_TX_BCLK,SAI1_RX_BCLK,SAI1_TX_BCLK,SAI2_RX_BCLK,SAI3_RX_BCLK,?..." group.long 0xE10000++0x03 line.long 0x00 "AUD_CLK1,ACM_AUD_CLK1 Register" bitfld.long 0x00 0.--4 " SEL ,Select" "ADMA_SLSLICE2,ADMA_SLSLICE3,EXT_AUD_MCLK0,EXT_AUD_MCLK1,ESAI0_RX_CLK,ESAI0_RX_HF_CLKK,ESAI0_TX_CLK,ESAI0_TX_HF_CLK,SPDIF0_RX,SAI0_RX_BCLK,SAI0_TX_BCLK,SAI1_RX_BCLK,SAI1_TX_BCLK,SAI2_RX_BCLK,SAI3_RX_BCLK,?..." group.long 0xE20000++0x03 line.long 0x00 "MCLKOUT0,ACM_MCLKOUT0 Register" bitfld.long 0x00 0.--2. " SEL ,Select" "ADMA_SLSLICE2,ADMA_SLSLICE3,,,SPDIF0_RX,,,SAI4_RX_BCLK" group.long 0xE30000++0x03 line.long 0x00 "MCLKOUT1,ACM_MCLKOUT1 Register" bitfld.long 0x00 0.--2. " SEL ,Select" "ADMA_SLSLICE2,ADMA_SLSLICE3,,,SPDIF0_RX,,,SAI4_RX_BCLK" group.long 0xE60000++0x03 line.long 0x00 "ESAI0_CLK,ACM_ESAI0_CLK Register" bitfld.long 0x00 0.--1. " SEL ,Select" "AUD_PLL_DIV_CLK0,AUD_PLL_DIV_CLK1,AUD_CLK0,AUD_CLK1" group.long 0xE80000++0x03 line.long 0x00 "GPT0_CLK,ACM_GPT0_CLK Register" bitfld.long 0x00 0.--2. " SEL ,Select" "AUD_PLL_DIV_CLK0,AUD_PLL_DIV_CLK1,AUD_CLK0,AUD_CLK1,24M_REF_CLK,?..." group.long 0xE90000++0x03 line.long 0x00 "GPT1_CLK,ACM_GPT1_CLK Register" bitfld.long 0x00 0.--2. " SEL ,Select" "AUD_PLL_DIV_CLK0,AUD_PLL_DIV_CLK1,AUD_CLK0,AUD_CLK1,24M_REF_CLK,?..." group.long 0xEA0000++0x03 line.long 0x00 "GPT2_CLK,ACM_GPT2_CLK Register" bitfld.long 0x00 0.--2. " SEL ,Select" "AUD_PLL_DIV_CLK0,AUD_PLL_DIV_CLK1,AUD_CLK0,AUD_CLK1,24M_REF_CLK,?..." group.long 0xEB0000++0x03 line.long 0x00 "GPT3_CLK,ACM_GPT3_CLK Register" bitfld.long 0x00 0.--2. " SEL ,Select" "AUD_PLL_DIV_CLK0,AUD_PLL_DIV_CLK1,AUD_CLK0,AUD_CLK1,24M_REF_CLK,?..." group.long 0xEC0000++0x03 line.long 0x00 "GPT4_CLK,ACM_GPT4_CLK Register" bitfld.long 0x00 0.--2. " SEL ,Select" "AUD_PLL_DIV_CLK0,AUD_PLL_DIV_CLK1,AUD_CLK0,AUD_CLK1,24M_REF_CLK,?..." group.long 0xED0000++0x03 line.long 0x00 "GPT5_CLK,ACM_GPT5_CLK Register" bitfld.long 0x00 0.--2. " SEL ,Select" "AUD_PLL_DIV_CLK0,AUD_PLL_DIV_CLK1,AUD_CLK0,AUD_CLK1,24M_REF_CLK,?..." group.long 0xEE0000++0x03 line.long 0x00 "SAI0_MCLK,ACM_SAI0_MCLK Register" bitfld.long 0x00 0.--2. " SEL ,Select" "AUD_PLL_DIV_CLK0,AUD_PLL_DIV_CLK1,AUD_CLK0,AUD_CLK1,24M_REF_CLK,?..." group.long 0xEF0000++0x03 line.long 0x00 "SAI1_MCLK,ACM_SAI1_MCLK Register" bitfld.long 0x00 0.--2. " SEL ,Select" "AUD_PLL_DIV_CLK0,AUD_PLL_DIV_CLK1,AUD_CLK0,AUD_CLK1,24M_REF_CLK,?..." group.long 0xF00000++0x03 line.long 0x00 "SAI2_MCLK,ACM_SAI2_MCLK Register" bitfld.long 0x00 0.--2. " SEL ,Select" "AUD_PLL_DIV_CLK0,AUD_PLL_DIV_CLK1,AUD_CLK0,AUD_CLK1,24M_REF_CLK,?..." group.long 0xF10000++0x03 line.long 0x00 "SAI3_MCLK,ACM_SAI3_MCLK Register" bitfld.long 0x00 0.--2. " SEL ,Select" "AUD_PLL_DIV_CLK0,AUD_PLL_DIV_CLK1,AUD_CLK0,AUD_CLK1,24M_REF_CLK,?..." group.long 0xF40000++0x07 line.long 0x00 "SAI0_MCLK,SAI0_MCLK Register" bitfld.long 0x00 0.--1. " SEL ,Select" "AUD_PLL_DIV_CLK0,AUD_PLL_DIV_CLK1,AUD_CLK0,AUD_CLK1" line.long 0x04 "SAI1_MCLK,SAI1_MCLK Register" bitfld.long 0x04 0.--1. " SEL ,Select" "AUD_PLL_DIV_CLK0,AUD_PLL_DIV_CLK1,AUD_CLK0,AUD_CLK1" group.long 0xFA0000++0x03 line.long 0x00 "SPDIF0_TX_CLK,ACM_SPDIF0_TX_CLK Register" bitfld.long 0x00 0.--1. " SEL ,Select" "AUD_PLL_DIV_CLK0,AUD_PLL_DIV_CLK1,AUD_CLK0,AUD_CLK1" group.long 0xFC0000++0x03 line.long 0x00 "MQS_HMCLK_CLK,ACM_MQS_HMCLK_CLK Register" bitfld.long 0x00 0.--1. " SEL ,Select" "AUD_PLL_DIV_CLK0,AUD_PLL_DIV_CLK1,AUD_CLK0,AUD_CLK1" width 0x0B tree.end tree "ADC (Analog-to-Digital Converter)" base ad:0x5A880000 width 9. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" bitfld.long 0x00 10. " CALOFSI ,Calibration offset function implemented" "Not implemented,Implemented" bitfld.long 0x00 9. " IADCKI ,Internal ADC clock implemented" "Not implemented,Implemented" newline bitfld.long 0x00 8. " VR1RNGI ,Voltage reference 1 range control bit implemented" "Not implemented,Implemented" bitfld.long 0x00 4.--6. " CSW ,Channel scale width" "Not supported,1-bit CSCALE,,,,,6-bit CSCALE,?..." bitfld.long 0x00 3. " MVI ,Multi vref implemented" "Single,Multiple" bitfld.long 0x00 1. " DIFFEN ,Differential supported" "Not supported,Supported" newline bitfld.long 0x00 0. " RES ,Resolution" "13-bit differential/12-bit,16-bit differential/15-bit" line.long 0x04 "PARAM,Parameter Register" hexmask.long.byte 0x04 24.--31. 1. " CMD_NUM ,Command buffer number" hexmask.long.byte 0x04 16.--23. 1. " CV_NUM ,Compare value number" hexmask.long.byte 0x04 8.--15. 1. " FIFOSIZE ,Result FIFO depth" hexmask.long.byte 0x04 0.--7. 1. " TRIG_NUM ,Trigger number" group.long 0x10++0x03 line.long 0x00 "CTRL,ADC Control Register" bitfld.long 0x00 8. " RSTFIFO ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 2. " DOZEN ,Reset FIFO" "No,Yes" bitfld.long 0x00 1. " RST ,Software reset" "Not reset,Reset" bitfld.long 0x00 0. " ADCEN ,ADC enable" "Disabled,Enabled" rgroup.long 0x14++0x03 line.long 0x00 "STAT,ADC Status Register" bitfld.long 0x00 24.--27. " CMDACT ,Command active" "No command,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--18. " TRGACT ,Trigger active" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8. " ADC_ACTIVE ,ADC active" "Idle,Active" bitfld.long 0x00 1. " FOF ,Result FIFO overflow flag" "Not occurred,Occurred" newline bitfld.long 0x00 0. " RDY ,Result FIFO ready flag" "Not occurred,Occurred" group.long 0x18++0x07 line.long 0x00 "IE,Interrupt Enable Register" bitfld.long 0x00 1. " FOFIE ,Result FIFO overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " FWMIE ,Result FIFO overflow interrupt enable" "Disabled,Enabled" line.long 0x04 "DE,DMA Enable Register" bitfld.long 0x04 0. " FWMDE ,FIFO watermark DMA enable" "Disabled,Enabled" if (((per.l(ad:0x5A880000+0x10))&0x01)==0x01) rgroup.long 0x20++0x07 line.long 0x00 "CFG,ADC Configuration Register" bitfld.long 0x00 28. " PWREN ,ADC analog pre-enable" "Enabled (conversions are active),Pre-enabled" hexmask.long.byte 0x00 16.--23. 1. " PUDLY ,Power up delay" bitfld.long 0x00 6.--7. " REFSEL ,Voltage reference selection" "Option 1,Option 2,Option 3,?..." bitfld.long 0x00 4.--5. " PWRSEL ,Power configuration select" "Level 1,Level 2,Level 3,Level 4" newline bitfld.long 0x00 0. " TPRICTRL ,ADC trigger priority control" "Aborted,Completed" line.long 0x04 "PAUSE,ADC Pause Register" bitfld.long 0x04 31. " PAUSEEN ,PAUSE option enable" "Disabled,Enabled" hexmask.long.word 0x04 0.--8. 1. " PAUSEDLY ,Pause delay" else group.long 0x20++0x07 line.long 0x00 "CFG,ADC Configuration Register" bitfld.long 0x00 28. " PWREN ,ADC analog pre-enable" "Enabled (conversions are active),Pre-enabled" hexmask.long.byte 0x00 16.--23. 1. " PUDLY ,Power up delay" bitfld.long 0x00 6.--7. " REFSEL ,Voltage reference selection" "Option 1,Option 2,Option 3,?..." bitfld.long 0x00 4.--5. " PWRSEL ,Power configuration select" "Level 1,Level 2,Level 3,Level 4" newline bitfld.long 0x00 0. " TPRICTRL ,ADC trigger priority control" "Aborted,Completed" line.long 0x04 "PAUSE,ADC Pause Register" bitfld.long 0x04 31. " PAUSEEN ,PAUSE option enable" "Disabled,Enabled" hexmask.long.word 0x04 0.--8. 1. " PAUSEDLY ,Pause delay" endif group.long 0x30++0x03 line.long 0x00 "FCTRL,ADC FIFO Control Register" bitfld.long 0x00 16.--19. " FWMARK ,Watermark level selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--4. " FCOUNT ,Result FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x5A880000+0x10))&0x01)==0x01) hgroup.long 0x34++0x03 hide.long 0x00 "SWTRIG,Software Trigger Register" else wgroup.long 0x34++0x03 line.long 0x00 "SWTRIG,Software Trigger Register" bitfld.long 0x00 7. " SWT[7] ,Software trigger 7 event" "Not generated,Generated" bitfld.long 0x00 6. " [6] ,Software trigger 6 event" "Not generated,Generated" bitfld.long 0x00 5. " [5] ,Software trigger 5 event" "Not generated,Generated" bitfld.long 0x00 4. " [4] ,Software trigger 4 event" "Not generated,Generated" newline bitfld.long 0x00 3. " [3] ,Software trigger 3 event" "Not generated,Generated" bitfld.long 0x00 2. " [2] ,Software trigger 2 event" "Not generated,Generated" bitfld.long 0x00 1. " [1] ,Software trigger 1 event" "Not generated,Generated" bitfld.long 0x00 0. " [0] ,Software trigger 0 event" "Not generated,Generated" endif group.long 0xC0++0x03 line.long 0x00 "TCTRL0,Trigger Control Register" bitfld.long 0x00 24.--27. " TCMD ,Trigger command select" "Invalid,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " TDLY ,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--10. " TPRI ,Trigger priority setting" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" bitfld.long 0x00 0. " HTEN ,Trigger enable" "Disabled,Enabled" group.long 0xC4++0x03 line.long 0x00 "TCTRL1,Trigger Control Register" bitfld.long 0x00 24.--27. " TCMD ,Trigger command select" "Invalid,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " TDLY ,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--10. " TPRI ,Trigger priority setting" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" bitfld.long 0x00 0. " HTEN ,Trigger enable" "Disabled,Enabled" group.long 0xC8++0x03 line.long 0x00 "TCTRL2,Trigger Control Register" bitfld.long 0x00 24.--27. " TCMD ,Trigger command select" "Invalid,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " TDLY ,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--10. " TPRI ,Trigger priority setting" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" bitfld.long 0x00 0. " HTEN ,Trigger enable" "Disabled,Enabled" group.long 0xCC++0x03 line.long 0x00 "TCTRL3,Trigger Control Register" bitfld.long 0x00 24.--27. " TCMD ,Trigger command select" "Invalid,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " TDLY ,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--10. " TPRI ,Trigger priority setting" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" bitfld.long 0x00 0. " HTEN ,Trigger enable" "Disabled,Enabled" group.long 0xD0++0x03 line.long 0x00 "TCTRL4,Trigger Control Register" bitfld.long 0x00 24.--27. " TCMD ,Trigger command select" "Invalid,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " TDLY ,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--10. " TPRI ,Trigger priority setting" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" bitfld.long 0x00 0. " HTEN ,Trigger enable" "Disabled,Enabled" group.long 0xD4++0x03 line.long 0x00 "TCTRL5,Trigger Control Register" bitfld.long 0x00 24.--27. " TCMD ,Trigger command select" "Invalid,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " TDLY ,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--10. " TPRI ,Trigger priority setting" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" bitfld.long 0x00 0. " HTEN ,Trigger enable" "Disabled,Enabled" group.long 0xD8++0x03 line.long 0x00 "TCTRL6,Trigger Control Register" bitfld.long 0x00 24.--27. " TCMD ,Trigger command select" "Invalid,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " TDLY ,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--10. " TPRI ,Trigger priority setting" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" bitfld.long 0x00 0. " HTEN ,Trigger enable" "Disabled,Enabled" group.long 0xDC++0x03 line.long 0x00 "TCTRL7,Trigger Control Register" bitfld.long 0x00 24.--27. " TCMD ,Trigger command select" "Invalid,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " TDLY ,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--10. " TPRI ,Trigger priority setting" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" bitfld.long 0x00 0. " HTEN ,Trigger enable" "Disabled,Enabled" group.long 0xF8++0x03 line.long 0x00 "CMDL1,ADC Command Low Buffer Register" bitfld.long 0x00 13. " CSCALE ,Channel scale" "Analog,Full" bitfld.long 0x00 6. " DIFF ,Differential mode enable" "Single-ended,Differential" bitfld.long 0x00 5. " ABSEL ,A-side vs. B-side select" "A-side,B-side" bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "CH0A or CH0B,CH1A or CH1B,CH2A or CH2B,CH3A or CH3B,CH4A or CH4B,CH5A or CH5B,CH6A or CH6B,CH7A or CH7B,CH8A or CH8B,CH9A or CH9B,CH10A or CH10B,CH11A or CH11B,CH12A or CH12B,CH13A or CH13B,CH14A or CH14B,CH15A or CH15B,CH16A or CH16B,C17A or CH17B,CH18A or CH18B,CH19A or CH19B,CH20A or CH20B,CH21A or CH21B,CH22A or CH22B,CH23A or CH23B,CH24A or CH24B,CH25A or CH25B,CH26A or CH26B,CH27A or CH27B,CH28A or CH28B,CH29A or CH29B,CH30A or CH30B,CH31A or CH31B" group.long 0x100++0x03 line.long 0x00 "CMDL2,ADC Command Low Buffer Register" bitfld.long 0x00 13. " CSCALE ,Channel scale" "Analog,Full" bitfld.long 0x00 6. " DIFF ,Differential mode enable" "Single-ended,Differential" bitfld.long 0x00 5. " ABSEL ,A-side vs. B-side select" "A-side,B-side" bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "CH0A or CH0B,CH1A or CH1B,CH2A or CH2B,CH3A or CH3B,CH4A or CH4B,CH5A or CH5B,CH6A or CH6B,CH7A or CH7B,CH8A or CH8B,CH9A or CH9B,CH10A or CH10B,CH11A or CH11B,CH12A or CH12B,CH13A or CH13B,CH14A or CH14B,CH15A or CH15B,CH16A or CH16B,C17A or CH17B,CH18A or CH18B,CH19A or CH19B,CH20A or CH20B,CH21A or CH21B,CH22A or CH22B,CH23A or CH23B,CH24A or CH24B,CH25A or CH25B,CH26A or CH26B,CH27A or CH27B,CH28A or CH28B,CH29A or CH29B,CH30A or CH30B,CH31A or CH31B" group.long 0x108++0x03 line.long 0x00 "CMDL3,ADC Command Low Buffer Register" bitfld.long 0x00 13. " CSCALE ,Channel scale" "Analog,Full" bitfld.long 0x00 6. " DIFF ,Differential mode enable" "Single-ended,Differential" bitfld.long 0x00 5. " ABSEL ,A-side vs. B-side select" "A-side,B-side" bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "CH0A or CH0B,CH1A or CH1B,CH2A or CH2B,CH3A or CH3B,CH4A or CH4B,CH5A or CH5B,CH6A or CH6B,CH7A or CH7B,CH8A or CH8B,CH9A or CH9B,CH10A or CH10B,CH11A or CH11B,CH12A or CH12B,CH13A or CH13B,CH14A or CH14B,CH15A or CH15B,CH16A or CH16B,C17A or CH17B,CH18A or CH18B,CH19A or CH19B,CH20A or CH20B,CH21A or CH21B,CH22A or CH22B,CH23A or CH23B,CH24A or CH24B,CH25A or CH25B,CH26A or CH26B,CH27A or CH27B,CH28A or CH28B,CH29A or CH29B,CH30A or CH30B,CH31A or CH31B" group.long 0x110++0x03 line.long 0x00 "CMDL4,ADC Command Low Buffer Register" bitfld.long 0x00 13. " CSCALE ,Channel scale" "Analog,Full" bitfld.long 0x00 6. " DIFF ,Differential mode enable" "Single-ended,Differential" bitfld.long 0x00 5. " ABSEL ,A-side vs. B-side select" "A-side,B-side" bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "CH0A or CH0B,CH1A or CH1B,CH2A or CH2B,CH3A or CH3B,CH4A or CH4B,CH5A or CH5B,CH6A or CH6B,CH7A or CH7B,CH8A or CH8B,CH9A or CH9B,CH10A or CH10B,CH11A or CH11B,CH12A or CH12B,CH13A or CH13B,CH14A or CH14B,CH15A or CH15B,CH16A or CH16B,C17A or CH17B,CH18A or CH18B,CH19A or CH19B,CH20A or CH20B,CH21A or CH21B,CH22A or CH22B,CH23A or CH23B,CH24A or CH24B,CH25A or CH25B,CH26A or CH26B,CH27A or CH27B,CH28A or CH28B,CH29A or CH29B,CH30A or CH30B,CH31A or CH31B" group.long 0x118++0x03 line.long 0x00 "CMDL5,ADC Command Low Buffer Register" bitfld.long 0x00 13. " CSCALE ,Channel scale" "Analog,Full" bitfld.long 0x00 6. " DIFF ,Differential mode enable" "Single-ended,Differential" bitfld.long 0x00 5. " ABSEL ,A-side vs. B-side select" "A-side,B-side" bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "CH0A or CH0B,CH1A or CH1B,CH2A or CH2B,CH3A or CH3B,CH4A or CH4B,CH5A or CH5B,CH6A or CH6B,CH7A or CH7B,CH8A or CH8B,CH9A or CH9B,CH10A or CH10B,CH11A or CH11B,CH12A or CH12B,CH13A or CH13B,CH14A or CH14B,CH15A or CH15B,CH16A or CH16B,C17A or CH17B,CH18A or CH18B,CH19A or CH19B,CH20A or CH20B,CH21A or CH21B,CH22A or CH22B,CH23A or CH23B,CH24A or CH24B,CH25A or CH25B,CH26A or CH26B,CH27A or CH27B,CH28A or CH28B,CH29A or CH29B,CH30A or CH30B,CH31A or CH31B" group.long 0x120++0x03 line.long 0x00 "CMDL6,ADC Command Low Buffer Register" bitfld.long 0x00 13. " CSCALE ,Channel scale" "Analog,Full" bitfld.long 0x00 6. " DIFF ,Differential mode enable" "Single-ended,Differential" bitfld.long 0x00 5. " ABSEL ,A-side vs. B-side select" "A-side,B-side" bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "CH0A or CH0B,CH1A or CH1B,CH2A or CH2B,CH3A or CH3B,CH4A or CH4B,CH5A or CH5B,CH6A or CH6B,CH7A or CH7B,CH8A or CH8B,CH9A or CH9B,CH10A or CH10B,CH11A or CH11B,CH12A or CH12B,CH13A or CH13B,CH14A or CH14B,CH15A or CH15B,CH16A or CH16B,C17A or CH17B,CH18A or CH18B,CH19A or CH19B,CH20A or CH20B,CH21A or CH21B,CH22A or CH22B,CH23A or CH23B,CH24A or CH24B,CH25A or CH25B,CH26A or CH26B,CH27A or CH27B,CH28A or CH28B,CH29A or CH29B,CH30A or CH30B,CH31A or CH31B" group.long 0x128++0x03 line.long 0x00 "CMDL7,ADC Command Low Buffer Register" bitfld.long 0x00 13. " CSCALE ,Channel scale" "Analog,Full" bitfld.long 0x00 6. " DIFF ,Differential mode enable" "Single-ended,Differential" bitfld.long 0x00 5. " ABSEL ,A-side vs. B-side select" "A-side,B-side" bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "CH0A or CH0B,CH1A or CH1B,CH2A or CH2B,CH3A or CH3B,CH4A or CH4B,CH5A or CH5B,CH6A or CH6B,CH7A or CH7B,CH8A or CH8B,CH9A or CH9B,CH10A or CH10B,CH11A or CH11B,CH12A or CH12B,CH13A or CH13B,CH14A or CH14B,CH15A or CH15B,CH16A or CH16B,C17A or CH17B,CH18A or CH18B,CH19A or CH19B,CH20A or CH20B,CH21A or CH21B,CH22A or CH22B,CH23A or CH23B,CH24A or CH24B,CH25A or CH25B,CH26A or CH26B,CH27A or CH27B,CH28A or CH28B,CH29A or CH29B,CH30A or CH30B,CH31A or CH31B" group.long 0x130++0x03 line.long 0x00 "CMDL8,ADC Command Low Buffer Register" bitfld.long 0x00 13. " CSCALE ,Channel scale" "Analog,Full" bitfld.long 0x00 6. " DIFF ,Differential mode enable" "Single-ended,Differential" bitfld.long 0x00 5. " ABSEL ,A-side vs. B-side select" "A-side,B-side" bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "CH0A or CH0B,CH1A or CH1B,CH2A or CH2B,CH3A or CH3B,CH4A or CH4B,CH5A or CH5B,CH6A or CH6B,CH7A or CH7B,CH8A or CH8B,CH9A or CH9B,CH10A or CH10B,CH11A or CH11B,CH12A or CH12B,CH13A or CH13B,CH14A or CH14B,CH15A or CH15B,CH16A or CH16B,C17A or CH17B,CH18A or CH18B,CH19A or CH19B,CH20A or CH20B,CH21A or CH21B,CH22A or CH22B,CH23A or CH23B,CH24A or CH24B,CH25A or CH25B,CH26A or CH26B,CH27A or CH27B,CH28A or CH28B,CH29A or CH29B,CH30A or CH30B,CH31A or CH31B" group.long 0x138++0x03 line.long 0x00 "CMDL9,ADC Command Low Buffer Register" bitfld.long 0x00 13. " CSCALE ,Channel scale" "Analog,Full" bitfld.long 0x00 6. " DIFF ,Differential mode enable" "Single-ended,Differential" bitfld.long 0x00 5. " ABSEL ,A-side vs. B-side select" "A-side,B-side" bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "CH0A or CH0B,CH1A or CH1B,CH2A or CH2B,CH3A or CH3B,CH4A or CH4B,CH5A or CH5B,CH6A or CH6B,CH7A or CH7B,CH8A or CH8B,CH9A or CH9B,CH10A or CH10B,CH11A or CH11B,CH12A or CH12B,CH13A or CH13B,CH14A or CH14B,CH15A or CH15B,CH16A or CH16B,C17A or CH17B,CH18A or CH18B,CH19A or CH19B,CH20A or CH20B,CH21A or CH21B,CH22A or CH22B,CH23A or CH23B,CH24A or CH24B,CH25A or CH25B,CH26A or CH26B,CH27A or CH27B,CH28A or CH28B,CH29A or CH29B,CH30A or CH30B,CH31A or CH31B" group.long 0x140++0x03 line.long 0x00 "CMDL10,ADC Command Low Buffer Register" bitfld.long 0x00 13. " CSCALE ,Channel scale" "Analog,Full" bitfld.long 0x00 6. " DIFF ,Differential mode enable" "Single-ended,Differential" bitfld.long 0x00 5. " ABSEL ,A-side vs. B-side select" "A-side,B-side" bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "CH0A or CH0B,CH1A or CH1B,CH2A or CH2B,CH3A or CH3B,CH4A or CH4B,CH5A or CH5B,CH6A or CH6B,CH7A or CH7B,CH8A or CH8B,CH9A or CH9B,CH10A or CH10B,CH11A or CH11B,CH12A or CH12B,CH13A or CH13B,CH14A or CH14B,CH15A or CH15B,CH16A or CH16B,C17A or CH17B,CH18A or CH18B,CH19A or CH19B,CH20A or CH20B,CH21A or CH21B,CH22A or CH22B,CH23A or CH23B,CH24A or CH24B,CH25A or CH25B,CH26A or CH26B,CH27A or CH27B,CH28A or CH28B,CH29A or CH29B,CH30A or CH30B,CH31A or CH31B" group.long 0x148++0x03 line.long 0x00 "CMDL11,ADC Command Low Buffer Register" bitfld.long 0x00 13. " CSCALE ,Channel scale" "Analog,Full" bitfld.long 0x00 6. " DIFF ,Differential mode enable" "Single-ended,Differential" bitfld.long 0x00 5. " ABSEL ,A-side vs. B-side select" "A-side,B-side" bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "CH0A or CH0B,CH1A or CH1B,CH2A or CH2B,CH3A or CH3B,CH4A or CH4B,CH5A or CH5B,CH6A or CH6B,CH7A or CH7B,CH8A or CH8B,CH9A or CH9B,CH10A or CH10B,CH11A or CH11B,CH12A or CH12B,CH13A or CH13B,CH14A or CH14B,CH15A or CH15B,CH16A or CH16B,C17A or CH17B,CH18A or CH18B,CH19A or CH19B,CH20A or CH20B,CH21A or CH21B,CH22A or CH22B,CH23A or CH23B,CH24A or CH24B,CH25A or CH25B,CH26A or CH26B,CH27A or CH27B,CH28A or CH28B,CH29A or CH29B,CH30A or CH30B,CH31A or CH31B" group.long 0x150++0x03 line.long 0x00 "CMDL12,ADC Command Low Buffer Register" bitfld.long 0x00 13. " CSCALE ,Channel scale" "Analog,Full" bitfld.long 0x00 6. " DIFF ,Differential mode enable" "Single-ended,Differential" bitfld.long 0x00 5. " ABSEL ,A-side vs. B-side select" "A-side,B-side" bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "CH0A or CH0B,CH1A or CH1B,CH2A or CH2B,CH3A or CH3B,CH4A or CH4B,CH5A or CH5B,CH6A or CH6B,CH7A or CH7B,CH8A or CH8B,CH9A or CH9B,CH10A or CH10B,CH11A or CH11B,CH12A or CH12B,CH13A or CH13B,CH14A or CH14B,CH15A or CH15B,CH16A or CH16B,C17A or CH17B,CH18A or CH18B,CH19A or CH19B,CH20A or CH20B,CH21A or CH21B,CH22A or CH22B,CH23A or CH23B,CH24A or CH24B,CH25A or CH25B,CH26A or CH26B,CH27A or CH27B,CH28A or CH28B,CH29A or CH29B,CH30A or CH30B,CH31A or CH31B" group.long 0x158++0x03 line.long 0x00 "CMDL13,ADC Command Low Buffer Register" bitfld.long 0x00 13. " CSCALE ,Channel scale" "Analog,Full" bitfld.long 0x00 6. " DIFF ,Differential mode enable" "Single-ended,Differential" bitfld.long 0x00 5. " ABSEL ,A-side vs. B-side select" "A-side,B-side" bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "CH0A or CH0B,CH1A or CH1B,CH2A or CH2B,CH3A or CH3B,CH4A or CH4B,CH5A or CH5B,CH6A or CH6B,CH7A or CH7B,CH8A or CH8B,CH9A or CH9B,CH10A or CH10B,CH11A or CH11B,CH12A or CH12B,CH13A or CH13B,CH14A or CH14B,CH15A or CH15B,CH16A or CH16B,C17A or CH17B,CH18A or CH18B,CH19A or CH19B,CH20A or CH20B,CH21A or CH21B,CH22A or CH22B,CH23A or CH23B,CH24A or CH24B,CH25A or CH25B,CH26A or CH26B,CH27A or CH27B,CH28A or CH28B,CH29A or CH29B,CH30A or CH30B,CH31A or CH31B" group.long 0x160++0x03 line.long 0x00 "CMDL14,ADC Command Low Buffer Register" bitfld.long 0x00 13. " CSCALE ,Channel scale" "Analog,Full" bitfld.long 0x00 6. " DIFF ,Differential mode enable" "Single-ended,Differential" bitfld.long 0x00 5. " ABSEL ,A-side vs. B-side select" "A-side,B-side" bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "CH0A or CH0B,CH1A or CH1B,CH2A or CH2B,CH3A or CH3B,CH4A or CH4B,CH5A or CH5B,CH6A or CH6B,CH7A or CH7B,CH8A or CH8B,CH9A or CH9B,CH10A or CH10B,CH11A or CH11B,CH12A or CH12B,CH13A or CH13B,CH14A or CH14B,CH15A or CH15B,CH16A or CH16B,C17A or CH17B,CH18A or CH18B,CH19A or CH19B,CH20A or CH20B,CH21A or CH21B,CH22A or CH22B,CH23A or CH23B,CH24A or CH24B,CH25A or CH25B,CH26A or CH26B,CH27A or CH27B,CH28A or CH28B,CH29A or CH29B,CH30A or CH30B,CH31A or CH31B" group.long 0x168++0x03 line.long 0x00 "CMDL15,ADC Command Low Buffer Register" bitfld.long 0x00 13. " CSCALE ,Channel scale" "Analog,Full" bitfld.long 0x00 6. " DIFF ,Differential mode enable" "Single-ended,Differential" bitfld.long 0x00 5. " ABSEL ,A-side vs. B-side select" "A-side,B-side" bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "CH0A or CH0B,CH1A or CH1B,CH2A or CH2B,CH3A or CH3B,CH4A or CH4B,CH5A or CH5B,CH6A or CH6B,CH7A or CH7B,CH8A or CH8B,CH9A or CH9B,CH10A or CH10B,CH11A or CH11B,CH12A or CH12B,CH13A or CH13B,CH14A or CH14B,CH15A or CH15B,CH16A or CH16B,C17A or CH17B,CH18A or CH18B,CH19A or CH19B,CH20A or CH20B,CH21A or CH21B,CH22A or CH22B,CH23A or CH23B,CH24A or CH24B,CH25A or CH25B,CH26A or CH26B,CH27A or CH27B,CH28A or CH28B,CH29A or CH29B,CH30A or CH30B,CH31A or CH31B" group.long 0xFC++0x03 line.long 0x00 "CMDH1,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. " NEXT ,Next command select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " LOOP ,Loop count select" "Looping disabled,Loop 2 times,Loop 3 times,Loop 4 times,Loop 5 times,Loop 6 times,Loop 7 times,Loop 8 times,Loop 9 times,Loop 10 times,Loop 11 times,Loop 12 times,Loop 13 times,Loop 14 times,Loop 15 times,Loop 16 times" bitfld.long 0x00 12.--14. " AVGS ,Hardware average select" "Single,2,4,8,16,32,64,128" bitfld.long 0x00 8.--10. " STS ,Sample time select" "3,5,7,11,19,35,67,131" newline bitfld.long 0x00 7. " LWI ,Loop with increment" "Disabled,Enabled" bitfld.long 0x00 0.--1. " CMPEN ,Compare function enable" "Disabled,,Enabled/Store on true,Enabled/Repeat channel acquisition" group.long 0x104++0x03 line.long 0x00 "CMDH2,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. " NEXT ,Next command select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " LOOP ,Loop count select" "Looping disabled,Loop 2 times,Loop 3 times,Loop 4 times,Loop 5 times,Loop 6 times,Loop 7 times,Loop 8 times,Loop 9 times,Loop 10 times,Loop 11 times,Loop 12 times,Loop 13 times,Loop 14 times,Loop 15 times,Loop 16 times" bitfld.long 0x00 12.--14. " AVGS ,Hardware average select" "Single,2,4,8,16,32,64,128" bitfld.long 0x00 8.--10. " STS ,Sample time select" "3,5,7,11,19,35,67,131" newline bitfld.long 0x00 7. " LWI ,Loop with increment" "Disabled,Enabled" bitfld.long 0x00 0.--1. " CMPEN ,Compare function enable" "Disabled,,Enabled/Store on true,Enabled/Repeat channel acquisition" group.long 0x10C++0x03 line.long 0x00 "CMDH3,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. " NEXT ,Next command select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " LOOP ,Loop count select" "Looping disabled,Loop 2 times,Loop 3 times,Loop 4 times,Loop 5 times,Loop 6 times,Loop 7 times,Loop 8 times,Loop 9 times,Loop 10 times,Loop 11 times,Loop 12 times,Loop 13 times,Loop 14 times,Loop 15 times,Loop 16 times" bitfld.long 0x00 12.--14. " AVGS ,Hardware average select" "Single,2,4,8,16,32,64,128" bitfld.long 0x00 8.--10. " STS ,Sample time select" "3,5,7,11,19,35,67,131" newline bitfld.long 0x00 7. " LWI ,Loop with increment" "Disabled,Enabled" bitfld.long 0x00 0.--1. " CMPEN ,Compare function enable" "Disabled,,Enabled/Store on true,Enabled/Repeat channel acquisition" group.long 0x114++0x03 line.long 0x00 "CMDH4,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. " NEXT ,Next command select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " LOOP ,Loop count select" "Looping disabled,Loop 2 times,Loop 3 times,Loop 4 times,Loop 5 times,Loop 6 times,Loop 7 times,Loop 8 times,Loop 9 times,Loop 10 times,Loop 11 times,Loop 12 times,Loop 13 times,Loop 14 times,Loop 15 times,Loop 16 times" bitfld.long 0x00 12.--14. " AVGS ,Hardware average select" "Single,2,4,8,16,32,64,128" bitfld.long 0x00 8.--10. " STS ,Sample time select" "3,5,7,11,19,35,67,131" newline bitfld.long 0x00 7. " LWI ,Loop with increment" "Disabled,Enabled" bitfld.long 0x00 0.--1. " CMPEN ,Compare function enable" "Disabled,,Enabled/Store on true,Enabled/Repeat channel acquisition" group.long 0x114++0x03 line.long 0x00 "CMDH5,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. " NEXT ,Next command select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " LOOP ,Loop count select" "Looping disabled,Loop 2 times,Loop 3 times,Loop 4 times,Loop 5 times,Loop 6 times,Loop 7 times,Loop 8 times,Loop 9 times,Loop 10 times,Loop 11 times,Loop 12 times,Loop 13 times,Loop 14 times,Loop 15 times,Loop 16 times" bitfld.long 0x00 12.--14. " AVGS ,Hardware average select" "Single,2,4,8,16,32,64,128" bitfld.long 0x00 8.--10. " STS ,Sample time select" "3,5,7,11,19,35,67,131" newline bitfld.long 0x00 7. " LWI ,Loop with increment" "Disabled,Enabled" group.long 0x11C++0x03 line.long 0x00 "CMDH6,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. " NEXT ,Next command select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " LOOP ,Loop count select" "Looping disabled,Loop 2 times,Loop 3 times,Loop 4 times,Loop 5 times,Loop 6 times,Loop 7 times,Loop 8 times,Loop 9 times,Loop 10 times,Loop 11 times,Loop 12 times,Loop 13 times,Loop 14 times,Loop 15 times,Loop 16 times" bitfld.long 0x00 12.--14. " AVGS ,Hardware average select" "Single,2,4,8,16,32,64,128" bitfld.long 0x00 8.--10. " STS ,Sample time select" "3,5,7,11,19,35,67,131" newline bitfld.long 0x00 7. " LWI ,Loop with increment" "Disabled,Enabled" group.long 0x124++0x03 line.long 0x00 "CMDH7,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. " NEXT ,Next command select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " LOOP ,Loop count select" "Looping disabled,Loop 2 times,Loop 3 times,Loop 4 times,Loop 5 times,Loop 6 times,Loop 7 times,Loop 8 times,Loop 9 times,Loop 10 times,Loop 11 times,Loop 12 times,Loop 13 times,Loop 14 times,Loop 15 times,Loop 16 times" bitfld.long 0x00 12.--14. " AVGS ,Hardware average select" "Single,2,4,8,16,32,64,128" bitfld.long 0x00 8.--10. " STS ,Sample time select" "3,5,7,11,19,35,67,131" newline bitfld.long 0x00 7. " LWI ,Loop with increment" "Disabled,Enabled" group.long 0x12C++0x03 line.long 0x00 "CMDH8,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. " NEXT ,Next command select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " LOOP ,Loop count select" "Looping disabled,Loop 2 times,Loop 3 times,Loop 4 times,Loop 5 times,Loop 6 times,Loop 7 times,Loop 8 times,Loop 9 times,Loop 10 times,Loop 11 times,Loop 12 times,Loop 13 times,Loop 14 times,Loop 15 times,Loop 16 times" bitfld.long 0x00 12.--14. " AVGS ,Hardware average select" "Single,2,4,8,16,32,64,128" bitfld.long 0x00 8.--10. " STS ,Sample time select" "3,5,7,11,19,35,67,131" newline bitfld.long 0x00 7. " LWI ,Loop with increment" "Disabled,Enabled" group.long 0x134++0x03 line.long 0x00 "CMDH9,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. " NEXT ,Next command select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " LOOP ,Loop count select" "Looping disabled,Loop 2 times,Loop 3 times,Loop 4 times,Loop 5 times,Loop 6 times,Loop 7 times,Loop 8 times,Loop 9 times,Loop 10 times,Loop 11 times,Loop 12 times,Loop 13 times,Loop 14 times,Loop 15 times,Loop 16 times" bitfld.long 0x00 12.--14. " AVGS ,Hardware average select" "Single,2,4,8,16,32,64,128" bitfld.long 0x00 8.--10. " STS ,Sample time select" "3,5,7,11,19,35,67,131" newline bitfld.long 0x00 7. " LWI ,Loop with increment" "Disabled,Enabled" group.long 0x13C++0x03 line.long 0x00 "CMDH10,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. " NEXT ,Next command select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " LOOP ,Loop count select" "Looping disabled,Loop 2 times,Loop 3 times,Loop 4 times,Loop 5 times,Loop 6 times,Loop 7 times,Loop 8 times,Loop 9 times,Loop 10 times,Loop 11 times,Loop 12 times,Loop 13 times,Loop 14 times,Loop 15 times,Loop 16 times" bitfld.long 0x00 12.--14. " AVGS ,Hardware average select" "Single,2,4,8,16,32,64,128" bitfld.long 0x00 8.--10. " STS ,Sample time select" "3,5,7,11,19,35,67,131" newline bitfld.long 0x00 7. " LWI ,Loop with increment" "Disabled,Enabled" group.long 0x144++0x03 line.long 0x00 "CMDH11,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. " NEXT ,Next command select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " LOOP ,Loop count select" "Looping disabled,Loop 2 times,Loop 3 times,Loop 4 times,Loop 5 times,Loop 6 times,Loop 7 times,Loop 8 times,Loop 9 times,Loop 10 times,Loop 11 times,Loop 12 times,Loop 13 times,Loop 14 times,Loop 15 times,Loop 16 times" bitfld.long 0x00 12.--14. " AVGS ,Hardware average select" "Single,2,4,8,16,32,64,128" bitfld.long 0x00 8.--10. " STS ,Sample time select" "3,5,7,11,19,35,67,131" newline bitfld.long 0x00 7. " LWI ,Loop with increment" "Disabled,Enabled" group.long 0x14C++0x03 line.long 0x00 "CMDH12,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. " NEXT ,Next command select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " LOOP ,Loop count select" "Looping disabled,Loop 2 times,Loop 3 times,Loop 4 times,Loop 5 times,Loop 6 times,Loop 7 times,Loop 8 times,Loop 9 times,Loop 10 times,Loop 11 times,Loop 12 times,Loop 13 times,Loop 14 times,Loop 15 times,Loop 16 times" bitfld.long 0x00 12.--14. " AVGS ,Hardware average select" "Single,2,4,8,16,32,64,128" bitfld.long 0x00 8.--10. " STS ,Sample time select" "3,5,7,11,19,35,67,131" newline bitfld.long 0x00 7. " LWI ,Loop with increment" "Disabled,Enabled" group.long 0x154++0x03 line.long 0x00 "CMDH13,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. " NEXT ,Next command select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " LOOP ,Loop count select" "Looping disabled,Loop 2 times,Loop 3 times,Loop 4 times,Loop 5 times,Loop 6 times,Loop 7 times,Loop 8 times,Loop 9 times,Loop 10 times,Loop 11 times,Loop 12 times,Loop 13 times,Loop 14 times,Loop 15 times,Loop 16 times" bitfld.long 0x00 12.--14. " AVGS ,Hardware average select" "Single,2,4,8,16,32,64,128" bitfld.long 0x00 8.--10. " STS ,Sample time select" "3,5,7,11,19,35,67,131" newline bitfld.long 0x00 7. " LWI ,Loop with increment" "Disabled,Enabled" group.long 0x15C++0x03 line.long 0x00 "CMDH14,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. " NEXT ,Next command select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " LOOP ,Loop count select" "Looping disabled,Loop 2 times,Loop 3 times,Loop 4 times,Loop 5 times,Loop 6 times,Loop 7 times,Loop 8 times,Loop 9 times,Loop 10 times,Loop 11 times,Loop 12 times,Loop 13 times,Loop 14 times,Loop 15 times,Loop 16 times" bitfld.long 0x00 12.--14. " AVGS ,Hardware average select" "Single,2,4,8,16,32,64,128" bitfld.long 0x00 8.--10. " STS ,Sample time select" "3,5,7,11,19,35,67,131" newline bitfld.long 0x00 7. " LWI ,Loop with increment" "Disabled,Enabled" group.long 0x164++0x03 line.long 0x00 "CMDH15,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. " NEXT ,Next command select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " LOOP ,Loop count select" "Looping disabled,Loop 2 times,Loop 3 times,Loop 4 times,Loop 5 times,Loop 6 times,Loop 7 times,Loop 8 times,Loop 9 times,Loop 10 times,Loop 11 times,Loop 12 times,Loop 13 times,Loop 14 times,Loop 15 times,Loop 16 times" bitfld.long 0x00 12.--14. " AVGS ,Hardware average select" "Single,2,4,8,16,32,64,128" bitfld.long 0x00 8.--10. " STS ,Sample time select" "3,5,7,11,19,35,67,131" newline bitfld.long 0x00 7. " LWI ,Loop with increment" "Disabled,Enabled" group.long 0x1FC++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 16.--31. 1. " CVH ,Compare value high" hexmask.long.word 0x00 0.--15. 1. " CVL ,Compare value low" group.long 0x200++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 16.--31. 1. " CVH ,Compare value high" hexmask.long.word 0x00 0.--15. 1. " CVL ,Compare value low" group.long 0x204++0x03 line.long 0x00 "CV3,Compare Value Register" hexmask.long.word 0x00 16.--31. 1. " CVH ,Compare value high" hexmask.long.word 0x00 0.--15. 1. " CVL ,Compare value low" group.long 0x208++0x03 line.long 0x00 "CV4,Compare Value Register" hexmask.long.word 0x00 16.--31. 1. " CVH ,Compare value high" hexmask.long.word 0x00 0.--15. 1. " CVL ,Compare value low" group.long 0x300++0x03 line.long 0x00 "RESFIFO,ADC Data Result FIFO Register" bitfld.long 0x00 31. " VALID ,FIFO entry is valid" "Invalid,Valid" bitfld.long 0x00 24.--27. " CMDSRC ,Command buffer source" "Invalid,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " LOOPCNT ,Loop count value" "Initial,2nd,3rd,4th,5th,6th,7th,8th,9th,10th,11th,12th,13th,14th,15th,16th" bitfld.long 0x00 16.--18. " TSRC ,Trigger source" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 0.--15. 1. " D ,Data result" width 0x0B tree.end tree.open "ASRC (Asynchronous Sample Rate Converter)" tree "ASRC0" base ad:0x59000000 width 10. if ((((per.l(ad:0x59000000+0x00))&0x6000)==0x6000)&&(((per.l(ad:0x59000000+0x00))&0x18000)==0x18000)&&(((per.l(ad:0x59000000+0x00))&0x60000)==0x60000)) group.long 0x00++0x03 line.long 0x00 "ASRCTR,Control Register" newline bitfld.long 0x00 17.--18. " USRC_IDRC ,Ideal ratio use for pair C" "Not used,Not used,Internal measured ratio,Ideal ratio" bitfld.long 0x00 15.--16. " USRB_IDRB ,Ideal ratio use for pair B" "Not used,Not used,Internal ratio,Ideal ratio" bitfld.long 0x00 13.--14. " USRA_IDRA ,Ideal ratio use for pair B" "Not used,Not used,Internal ratio,Ideal ratio" newline bitfld.long 0x00 4. " SRST ,Software reset" "No reset,Reset" bitfld.long 0x00 3. " ASREC ,ASRC enable C" "Disabled,Enabled" bitfld.long 0x00 2. " ASREB ,ASRC enable B" "Disabled,Enabled" newline bitfld.long 0x00 1. " ASREA ,ASRC enable A" "Disabled,Enabled" bitfld.long 0x00 0. " ASRCEN ,ASRC enable" "Disabled,Enabled" elif ((((per.l(ad:0x59000000+0x00))&0x6000)==0x6000)&&(((per.l(ad:0x59000000+0x00))&0x18000)==0x18000)&&(((per.l(ad:0x59000000+0x00))&0x60000)!=0x60000)) group.long 0x00++0x03 line.long 0x00 "ASRCTR,Control Register" bitfld.long 0x00 22. " ATSC ,ASRC pair C automatic selection for processing options" "Disabled,Enabled" newline bitfld.long 0x00 17.--18. " USRC_IDRC ,Ideal ratio use for pair C" "Not used,Not used,Internal measured ratio,Ideal ratio" bitfld.long 0x00 15.--16. " USRB_IDRB ,Ideal ratio use for pair B" "Not used,Not used,Internal ratio,Ideal ratio" bitfld.long 0x00 13.--14. " USRA_IDRA ,Ideal ratio use for pair B" "Not used,Not used,Internal ratio,Ideal ratio" newline bitfld.long 0x00 4. " SRST ,Software reset" "No reset,Reset" bitfld.long 0x00 3. " ASREC ,ASRC enable C" "Disabled,Enabled" bitfld.long 0x00 2. " ASREB ,ASRC enable B" "Disabled,Enabled" newline bitfld.long 0x00 1. " ASREA ,ASRC enable A" "Disabled,Enabled" bitfld.long 0x00 0. " ASRCEN ,ASRC enable" "Disabled,Enabled" elif ((((per.l(ad:0x59000000+0x00))&0x6000)==0x6000)&&(((per.l(ad:0x59000000+0x00))&0x18000)!=0x18000)&&(((per.l(ad:0x59000000+0x00))&0x60000)==0x60000)) group.long 0x00++0x03 line.long 0x00 "ASRCTR,Control Register" bitfld.long 0x00 21. " ATSB ,ASRC pair B automatic selection for processing options" "Disabled,Enabled" newline bitfld.long 0x00 17.--18. " USRC_IDRC ,Ideal ratio use for pair C" "Not used,Not used,Internal measured ratio,Ideal ratio" bitfld.long 0x00 15.--16. " USRB_IDRB ,Ideal ratio use for pair B" "Not used,Not used,Internal ratio,Ideal ratio" bitfld.long 0x00 13.--14. " USRA_IDRA ,Ideal ratio use for pair B" "Not used,Not used,Internal ratio,Ideal ratio" newline bitfld.long 0x00 4. " SRST ,Software reset" "No reset,Reset" bitfld.long 0x00 3. " ASREC ,ASRC enable C" "Disabled,Enabled" bitfld.long 0x00 2. " ASREB ,ASRC enable B" "Disabled,Enabled" newline bitfld.long 0x00 1. " ASREA ,ASRC enable A" "Disabled,Enabled" bitfld.long 0x00 0. " ASRCEN ,ASRC enable" "Disabled,Enabled" elif ((((per.l(ad:0x59000000+0x00))&0x6000)==0x6000)&&(((per.l(ad:0x59000000+0x00))&0x18000)!=0x18000)&&(((per.l(ad:0x59000000+0x00))&0x60000)!=0x60000)) group.long 0x00++0x03 line.long 0x00 "ASRCTR,Control Register" bitfld.long 0x00 22. " ATSC ,ASRC pair C automatic selection for processing options" "Disabled,Enabled" bitfld.long 0x00 21. " ATSB ,ASRC pair B automatic selection for processing options" "Disabled,Enabled" newline bitfld.long 0x00 17.--18. " USRC_IDRC ,Ideal ratio use for pair C" "Not used,Not used,Internal measured ratio,Ideal ratio" bitfld.long 0x00 15.--16. " USRB_IDRB ,Ideal ratio use for pair B" "Not used,Not used,Internal ratio,Ideal ratio" bitfld.long 0x00 13.--14. " USRA_IDRA ,Ideal ratio use for pair B" "Not used,Not used,Internal ratio,Ideal ratio" newline bitfld.long 0x00 4. " SRST ,Software reset" "No reset,Reset" bitfld.long 0x00 3. " ASREC ,ASRC enable C" "Disabled,Enabled" bitfld.long 0x00 2. " ASREB ,ASRC enable B" "Disabled,Enabled" newline bitfld.long 0x00 1. " ASREA ,ASRC enable A" "Disabled,Enabled" bitfld.long 0x00 0. " ASRCEN ,ASRC enable" "Disabled,Enabled" elif ((((per.l(ad:0x59000000+0x00))&0x6000)!=0x6000)&&(((per.l(ad:0x59000000+0x00))&0x18000)==0x18000)&&(((per.l(ad:0x59000000+0x00))&0x60000)==0x60000)) group.long 0x00++0x03 line.long 0x00 "ASRCTR,Control Register" bitfld.long 0x00 20. " ATSA ,ASRC pair A automatic selection for processing options" "Disabled,Enabled" newline bitfld.long 0x00 17.--18. " USRC_IDRC ,Ideal ratio use for pair C" "Not used,Not used,Internal measured ratio,Ideal ratio" bitfld.long 0x00 15.--16. " USRB_IDRB ,Ideal ratio use for pair B" "Not used,Not used,Internal ratio,Ideal ratio" bitfld.long 0x00 13.--14. " USRA_IDRA ,Ideal ratio use for pair B" "Not used,Not used,Internal ratio,Ideal ratio" newline bitfld.long 0x00 4. " SRST ,Software reset" "No reset,Reset" bitfld.long 0x00 3. " ASREC ,ASRC enable C" "Disabled,Enabled" bitfld.long 0x00 2. " ASREB ,ASRC enable B" "Disabled,Enabled" newline bitfld.long 0x00 1. " ASREA ,ASRC enable A" "Disabled,Enabled" bitfld.long 0x00 0. " ASRCEN ,ASRC enable" "Disabled,Enabled" elif ((((per.l(ad:0x59000000+0x00))&0x6000)!=0x6000)&&(((per.l(ad:0x59000000+0x00))&0x18000)==0x18000)&&(((per.l(ad:0x59000000+0x00))&0x60000)!=0x60000)) group.long 0x00++0x03 line.long 0x00 "ASRCTR,Control Register" bitfld.long 0x00 22. " ATSC ,ASRC pair C automatic selection for processing options" "Disabled,Enabled" textfld " " bitfld.long 0x00 20. " ATSA ,ASRC pair A automatic selection for processing options" "Disabled,Enabled" newline bitfld.long 0x00 17.--18. " USRC_IDRC ,Ideal ratio use for pair C" "Not used,Not used,Internal measured ratio,Ideal ratio" bitfld.long 0x00 15.--16. " USRB_IDRB ,Ideal ratio use for pair B" "Not used,Not used,Internal ratio,Ideal ratio" bitfld.long 0x00 13.--14. " USRA_IDRA ,Ideal ratio use for pair B" "Not used,Not used,Internal ratio,Ideal ratio" newline bitfld.long 0x00 4. " SRST ,Software reset" "No reset,Reset" bitfld.long 0x00 3. " ASREC ,ASRC enable C" "Disabled,Enabled" bitfld.long 0x00 2. " ASREB ,ASRC enable B" "Disabled,Enabled" newline bitfld.long 0x00 1. " ASREA ,ASRC enable A" "Disabled,Enabled" bitfld.long 0x00 0. " ASRCEN ,ASRC enable" "Disabled,Enabled" elif ((((per.l(ad:0x59000000+0x00))&0x6000)!=0x6000)&&(((per.l(ad:0x59000000+0x00))&0x18000)!=0x18000)&&(((per.l(ad:0x59000000+0x00))&0x60000)==0x60000)) group.long 0x00++0x03 line.long 0x00 "ASRCTR,Control Register" bitfld.long 0x00 21. " ATSB ,ASRC pair B automatic selection for processing options" "Disabled,Enabled" bitfld.long 0x00 20. " ATSA ,ASRC pair A automatic selection for processing options" "Disabled,Enabled" newline bitfld.long 0x00 17.--18. " USRC_IDRC ,Ideal ratio use for pair C" "Not used,Not used,Internal measured ratio,Ideal ratio" bitfld.long 0x00 15.--16. " USRB_IDRB ,Ideal ratio use for pair B" "Not used,Not used,Internal ratio,Ideal ratio" bitfld.long 0x00 13.--14. " USRA_IDRA ,Ideal ratio use for pair B" "Not used,Not used,Internal ratio,Ideal ratio" newline bitfld.long 0x00 4. " SRST ,Software reset" "No reset,Reset" bitfld.long 0x00 3. " ASREC ,ASRC enable C" "Disabled,Enabled" bitfld.long 0x00 2. " ASREB ,ASRC enable B" "Disabled,Enabled" newline bitfld.long 0x00 1. " ASREA ,ASRC enable A" "Disabled,Enabled" bitfld.long 0x00 0. " ASRCEN ,ASRC enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "ASRCTR,Control Register" bitfld.long 0x00 22. " ATSC ,ASRC pair C automatic selection for processing options" "Disabled,Enabled" bitfld.long 0x00 21. " ATSB ,ASRC pair B automatic selection for processing options" "Disabled,Enabled" bitfld.long 0x00 20. " ATSA ,ASRC pair A automatic selection for processing options" "Disabled,Enabled" newline bitfld.long 0x00 17.--18. " USRC_IDRC ,Ideal ratio use for pair C" "Not used,Not used,Internal measured ratio,Ideal ratio" bitfld.long 0x00 15.--16. " USRB_IDRB ,Ideal ratio use for pair B" "Not used,Not used,Internal ratio,Ideal ratio" bitfld.long 0x00 13.--14. " USRA_IDRA ,Ideal ratio use for pair B" "Not used,Not used,Internal ratio,Ideal ratio" newline bitfld.long 0x00 4. " SRST ,Software reset" "No reset,Reset" bitfld.long 0x00 3. " ASREC ,ASRC enable C" "Disabled,Enabled" bitfld.long 0x00 2. " ASREB ,ASRC enable B" "Disabled,Enabled" newline bitfld.long 0x00 1. " ASREA ,ASRC enable A" "Disabled,Enabled" bitfld.long 0x00 0. " ASRCEN ,ASRC enable" "Disabled,Enabled" endif group.long 0x04++0x03 line.long 0x00 "ASRIER,Interrupt Enable Register" bitfld.long 0x00 7. " AFPWE ,FP in wait state interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " AOLIE ,Overload interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " ADOEC ,Data output C interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " ADOEB ,Data output B interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " ADOEA ,Data output A interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " ADIEC ,Data input C interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " ADIEB ,Data input B interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " ADIEA ,Data input A interrupt enable" "Disabled,Enabled" group.long 0x0C++0x13 line.long 0x00 "ASRCNCR,Channel Number Configuration Register" bitfld.long 0x00 8.--11. " ANCC ,Number of C channels" "0,1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x00 4.--7. " ANCB ,Number of B channels" "0,1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x00 0.--3. " ANCA ,Number of A channels" "0,1,2,3,4,5,6,7,8,9,10,?..." line.long 0x04 "ASRCFG,Filter Configuration Status Register" rbitfld.long 0x04 23. " INIRQC ,Initialization for conversion pair C serve" "Not served,Served" rbitfld.long 0x04 22. " INIRQB ,Initialization for conversion pair B serve" "Not served,Served" rbitfld.long 0x04 21. " INIRQA ,Initialization for conversion pair A serve" "Not served,Served" bitfld.long 0x04 20. " NDPRC ,Conversion pair C parameters select" "Default,RAM" newline bitfld.long 0x04 19. " NDPRB ,Conversion pair B parameters select" "Default,RAM" bitfld.long 0x04 18. " NDPRA ,Conversion pair A parameters select" "Default,RAM" bitfld.long 0x04 16.--17. " POSTMODC ,Post-processing configuration for conversion pair C" "Upsampling-by-2,Direct-connection,Downsampling-by-2,?..." bitfld.long 0x04 14.--15. " PREMODC ,Pre-processing configuration for conversion pair C" "Upsampling-by-2,Direct-connection,Downsampling-by-2,Passthrough" newline bitfld.long 0x04 12.--13. " POSTMODB ,Post-processing configuration for conversion pair B" "Upsampling-by-2,Direct-connection,Downsampling-by-2,?..." bitfld.long 0x04 10.--11. " PREMODB ,Pre-processing configuration for conversion pair B" "Upsampling-by-2,Direct-connection,Downsampling-by-2,Passthrough" bitfld.long 0x04 8.--9. " POSTMODA ,Post-processing configuration for conversion pair A" "Upsampling-by-2,Direct-connection,Downsampling-by-2,?..." bitfld.long 0x04 6.--7. " PREMODA ,Pre-processing configuration for conversion pair A" "Upsampling-by-2,Direct-connection,Downsampling-by-2,Passthrough" line.long 0x08 "ASRCSR,Clock Source Register" bitfld.long 0x08 20.--23. " AOCSC ,Output clock source C" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,Disabled" bitfld.long 0x08 16.--19. " AOCSB ,Output clock source B" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,Disabled" bitfld.long 0x08 12.--15. " AOCSA ,Output clock source A" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,Disabled" bitfld.long 0x08 8.--11. " AICSC ,Input clock source C" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,Disabled" newline bitfld.long 0x08 4.--7. " AICSB ,Input clock source B" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,Disabled" bitfld.long 0x08 0.--3. " AICSA ,Input clock source A" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,Disabled" line.long 0x0C "ASRCDR1,Clock Divider Register 1" bitfld.long 0x0C 21.--23. " AOCDB ,Output clock divider B" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 18.--20. " AOCPB ,Output clock prescaler B" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.long 0x0C 15.--17. " AOCDA ,Output clock divider A" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 12.--14. " AOCPA ,Output clock prescaler A" "/1,/2,/4,/8,/16,/32,/64,/128" newline bitfld.long 0x0C 9.--11. " AICDB ,Input clock divider B" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 6.--8. " AICPB ,Input clock prescaler B" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.long 0x0C 3.--5. " AICDA ,Input clock divider A" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--2. " AICPA ,Input clock prescaler A" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x10 "ASRCDR2,Clock Divider Register 2" bitfld.long 0x10 9.--11. " AOCDC ,Output clock divider C" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x10 6.--8. " AOCPC ,Output clock prescaler C" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.long 0x10 3.--5. " AICDC ,Input clock divider C" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x10 0.--2. " AICPC ,Input clock prescaler C" "/1,/2,/4,/8,/16,/32,/64,/128" rgroup.long 0x20++0x03 line.long 0x00 "ASRSTR,Status Register" bitfld.long 0x00 21. " DSLCNT ,DSL counter input to FIFO ready" "In process,Stored" bitfld.long 0x00 20. " ATQOL ,Task queue FIFO overload" "Not overloaded,Overloaded" bitfld.long 0x00 19. " AOOLC ,Pair C output task overload" "Not overloaded,Overloaded" bitfld.long 0x00 18. " AOOLB ,Pair B output task overload" "Not overloaded,Overloaded" newline bitfld.long 0x00 17. " AOOLA ,Pair A output task overload" "Not overloaded,Overloaded" bitfld.long 0x00 16. " AIOLC ,Pair C input task overload" "Not overloaded,Overloaded" bitfld.long 0x00 15. " AIOLB ,Pair B input task overload" "Not overloaded,Overloaded" bitfld.long 0x00 14. " AIOLA ,Pair A input task overload" "Not overloaded,Overloaded" newline bitfld.long 0x00 13. " AODOC ,Output data buffer C overflow" "No overflow,Overflow" bitfld.long 0x00 12. " AODOB ,Output data buffer B overflow" "No overflow,Overflow" bitfld.long 0x00 11. " AODOA ,Output data buffer A overflow" "No overflow,Overflow" bitfld.long 0x00 10. " AIDUC ,Input data buffer C underflow" "No underflow,Underflow" newline bitfld.long 0x00 9. " AIDUB ,Input data buffer B underflow" "No underflow,Underflow" bitfld.long 0x00 8. " AIDUA ,Input data buffer A underflow" "No underflow,Underflow" bitfld.long 0x00 7. " FPWT ,FP is in wait states" "Not wait state,Wait state" bitfld.long 0x00 6. " AOLE ,Overload error flag" "No error,Error" newline bitfld.long 0x00 5. " AODFC ,Number of data in output data buffer C is greater than threshold" "Less/Equal,Greater" bitfld.long 0x00 4. " AODFB ,Number of data in output data buffer B is greater than threshold" "Less/Equal,Greater" bitfld.long 0x00 3. " AODFA ,Number of data in output data buffer A is greater than threshold" "Less/Equal,Greater" bitfld.long 0x00 2. " AIDEC ,Number of data in input data buffer C is less than threshold" "Greater/Equal,Less" newline bitfld.long 0x00 1. " AIDEB ,Number of data in input data buffer B is less than threshold" "Greater/Equal,Less" bitfld.long 0x00 0. " AIDEA ,Number of data in input data buffer A is less than threshold" "Greater/Equal,Less" group.long 0x40++0x03 line.long 0x00 "ASRPM1,Parameter Register 1" hexmask.long.tbyte 0x00 0.--23. 1. " PARAMETER_VALUE ,Parameter value" group.long 0x44++0x03 line.long 0x00 "ASRPM2,Parameter Register 2" hexmask.long.tbyte 0x00 0.--23. 1. " PARAMETER_VALUE ,Parameter value" group.long 0x48++0x03 line.long 0x00 "ASRPM3,Parameter Register 3" hexmask.long.tbyte 0x00 0.--23. 1. " PARAMETER_VALUE ,Parameter value" group.long 0x4C++0x03 line.long 0x00 "ASRPM4,Parameter Register 4" hexmask.long.tbyte 0x00 0.--23. 1. " PARAMETER_VALUE ,Parameter value" group.long 0x50++0x03 line.long 0x00 "ASRPM5,Parameter Register 5" hexmask.long.tbyte 0x00 0.--23. 1. " PARAMETER_VALUE ,Parameter value" group.long 0x54++0x03 line.long 0x00 "ASRTFR1,Task Queue FIFO Register 1" hexmask.long.byte 0x00 13.--19. 1. " TF_FILL ,Current number of entries in task queue FIFO" hexmask.long.word 0x00 6.--12. 0x40 " TF_BASE ,Base address for task queue FIFO" group.long 0x5C++0x03 line.long 0x00 "ASRCCR,Channel Counter Register" bitfld.long 0x00 20.--23. " ACOC ,The channel counter for pair C's output FIFO" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 16.--19. " ACOB ,The channel counter for pair B's output FIFO" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " ACOA ,The channel counter for pair A's output FIFO" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 8.--11. " ACIC ,The channel counter for pair C's input FIFO" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 4.--7. " ACIB ,The channel counter for pair B's input FIFO" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 0.--3. " ACIA ,The channel counter for pair A's input FIFO" "0,1,2,3,4,5,6,7,8,9,?..." wgroup.long 0x60++0x03 line.long 0x00 "ASRDIA,Data Input Register For Pair A" hexmask.long.tbyte 0x00 0.--23. 1. " DATA ,Audio data input" rgroup.long (0x60+0x04)++0x03 line.long 0x00 "ASRDOA,Data Output Register For Pair A" hexmask.long.tbyte 0x00 0.--23. 1. " DATA ,Audio data output" wgroup.long 0x68++0x03 line.long 0x00 "ASRDIB,Data Input Register For Pair B" hexmask.long.tbyte 0x00 0.--23. 1. " DATA ,Audio data input" rgroup.long (0x68+0x04)++0x03 line.long 0x00 "ASRDOB,Data Output Register For Pair B" hexmask.long.tbyte 0x00 0.--23. 1. " DATA ,Audio data output" wgroup.long 0x70++0x03 line.long 0x00 "ASRDIC,Data Input Register For Pair C" hexmask.long.tbyte 0x00 0.--23. 1. " DATA ,Audio data input" rgroup.long (0x70+0x04)++0x03 line.long 0x00 "ASRDOC,Data Output Register For Pair C" hexmask.long.tbyte 0x00 0.--23. 1. " DATA ,Audio data output" group.long 0x80++0x1F line.long 0x00 "ASRIDRHA,Ideal Ratio For Pair A-High Part Register" hexmask.long.byte 0x00 0.--7. 1. " IDRATIOA_H ,IDRATIOA high part of ideal ratio value for pair A" line.long 0x04 "ASRIDRLA,Ideal Ratio For Pair A -Low Part Register" hexmask.long.tbyte 0x04 0.--23. 1. " IDRATIOA_L ,IDRATIOA low part of ideal ratio value for pair A" line.long 0x08 "ASRIDRHB,ASRC Ideal Ratio For Pair B-High Part Register" hexmask.long.byte 0x08 0.--7. 1. " IDRATIOB_H ,IDRATIOB high part of ideal ratio value for pair B" line.long 0x0C "ASRIDRLB,Ideal Ratio For Pair B-Low Part Register" hexmask.long.tbyte 0x0C 0.--23. 1. " IDRATIOB_L ,IDRATIOB low part of ideal ratio value for pair B" line.long 0x10 "ASRIDRHC,Ideal Ratio For Pair C-High Part Register" hexmask.long.byte 0x10 0.--7. 1. " IDRATIOC_H ,IDRATIOC high part of ideal ratio value for pair C" line.long 0x14 "ASRIDRLC,Ideal Ratio For Pair C-Low Part Register" hexmask.long.tbyte 0x14 0.--23. 1. " IDRATIOC_L ,IDRATIOC low part of ideal ratio value for pair C" line.long 0x18 "ASR76K,76kHz Period In Terms Of ASRC Processing Clock Register" hexmask.long.tbyte 0x18 0.--16. 1. " ASR76K ,Value for the period of the 76kHz sampling clock" line.long 0x1C "ASR56K,56kHz Period In Terms Of ASRC Processing Clock Register" hexmask.long.tbyte 0x1C 0.--16. 1. " ASR56K ,Value for the period of the 56kHz sampling clock" group.long 0xA0++0x03 line.long 0x00 "ASRMCRA,Misc Control Register For Pair A" bitfld.long 0x00 23. " ZEROBUFA ,Buffer zeroize disable" "No,Yes" bitfld.long 0x00 22. " EXTTHRSHA ,External thresholds enable for FIFO control of pair A" "Disabled,Enabled" bitfld.long 0x00 21. " BUFSTALLA ,Stall pair A conversion in case of buffer near empty/full condition" "Disabled,Enabled" bitfld.long 0x00 20. " BYPASSPOLYA ,Bypass polyphase filtering for pair A" "Disabled,Enabled" newline bitfld.long 0x00 12.--17. " OUTFIFO_THRESHOLDA ,The threshold for pair A's output FIFO per channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. " RSYNIFA ,Re-sync input FIFO channel counter force bit" "Not forced,Forced" bitfld.long 0x00 10. " RSYNOFA ,Re-sync output FIFO channel counter force bit" "Not forced,Forced" bitfld.long 0x00 0.--5. " INFIFO_THRESHOLDA ,The threshold for pair A's input FIFO per channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xA0+0x04)++0x03 line.long 0x00 "ASRFSTA,FIFO Status Register For Pair A" bitfld.long 0x00 23. " OAFA ,Output FIFO is near full for pair A" "No,Yes" hexmask.long.byte 0x00 12.--18. 1. " OUTFIFO_FILLA ,The fillings for pair A's output FIFO per channel" bitfld.long 0x00 11. " IAEA ,Input FIFO is near empty for pair A" "No,Yes" hexmask.long.byte 0x00 0.--6. 1. " INFIFO_FILLA ,The fillings for pair A's input FIFO per channel" group.long 0xA8++0x03 line.long 0x00 "ASRMCRB,Misc Control Register For Pair B" bitfld.long 0x00 23. " ZEROBUFB ,Buffer zeroize disable" "No,Yes" bitfld.long 0x00 22. " EXTTHRSHB ,External thresholds enable for FIFO control of pair B" "Disabled,Enabled" bitfld.long 0x00 21. " BUFSTALLB ,Stall pair B conversion in case of buffer near empty/full condition" "Disabled,Enabled" bitfld.long 0x00 20. " BYPASSPOLYB ,Bypass polyphase filtering for pair B" "Disabled,Enabled" newline bitfld.long 0x00 12.--17. " OUTFIFO_THRESHOLDB ,The threshold for pair B's output FIFO per channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. " RSYNIFB ,Re-sync input FIFO channel counter force bit" "Not forced,Forced" bitfld.long 0x00 10. " RSYNOFB ,Re-sync output FIFO channel counter force bit" "Not forced,Forced" bitfld.long 0x00 0.--5. " INFIFO_THRESHOLDB ,The threshold for pair B's input FIFO per channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xA8+0x04)++0x03 line.long 0x00 "ASRFSTB,FIFO Status Register For Pair B" bitfld.long 0x00 23. " OAFB ,Output FIFO is near full for pair B" "No,Yes" hexmask.long.byte 0x00 12.--18. 1. " OUTFIFO_FILLB ,The fillings for pair B's output FIFO per channel" bitfld.long 0x00 11. " IAEB ,Input FIFO is near empty for pair B" "No,Yes" hexmask.long.byte 0x00 0.--6. 1. " INFIFO_FILLB ,The fillings for pair B's input FIFO per channel" group.long 0xB0++0x03 line.long 0x00 "ASRMCRC,Misc Control Register For Pair C" bitfld.long 0x00 23. " ZEROBUFC ,Buffer zeroize disable" "No,Yes" bitfld.long 0x00 22. " EXTTHRSHC ,External thresholds enable for FIFO control of pair C" "Disabled,Enabled" bitfld.long 0x00 21. " BUFSTALLC ,Stall pair C conversion in case of buffer near empty/full condition" "Disabled,Enabled" bitfld.long 0x00 20. " BYPASSPOLYC ,Bypass polyphase filtering for pair C" "Disabled,Enabled" newline bitfld.long 0x00 12.--17. " OUTFIFO_THRESHOLDC ,The threshold for pair C's output FIFO per channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. " RSYNIFC ,Re-sync input FIFO channel counter force bit" "Not forced,Forced" bitfld.long 0x00 10. " RSYNOFC ,Re-sync output FIFO channel counter force bit" "Not forced,Forced" bitfld.long 0x00 0.--5. " INFIFO_THRESHOLDC ,The threshold for pair C's input FIFO per channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xB0+0x04)++0x03 line.long 0x00 "ASRFSTC,FIFO Status Register For Pair C" bitfld.long 0x00 23. " OAFC ,Output FIFO is near full for pair C" "No,Yes" hexmask.long.byte 0x00 12.--18. 1. " OUTFIFO_FILLC ,The fillings for pair C's output FIFO per channel" bitfld.long 0x00 11. " IAEC ,Input FIFO is near empty for pair C" "No,Yes" hexmask.long.byte 0x00 0.--6. 1. " INFIFO_FILLC ,The fillings for pair C's input FIFO per channel" group.long 0xC0++0x03 line.long 0x00 "ASRMCR1A,Misc Control Register 1 For Pair A" bitfld.long 0x00 9.--11. " IWD ,Data width of the input FIFO" "24-bit,16-bit,8-bit,?..." bitfld.long 0x00 8. " IMSB ,Data alignment (input FIFO)" "LSB,MSB" bitfld.long 0x00 2. " OMSB ,Data alignment (output FIFO)" "LSB,MSB" bitfld.long 0x00 1. " OSGN ,Sign extension option (output FIFO)" "Disabled,Enabled" newline bitfld.long 0x00 0. " OW16 ,Bit width option (output FIFO)" "24-bit,16-bit" group.long 0xC4++0x03 line.long 0x00 "ASRMCR1B,Misc Control Register 1 For Pair B" bitfld.long 0x00 9.--11. " IWD ,Data width of the input FIFO" "24-bit,16-bit,8-bit,?..." bitfld.long 0x00 8. " IMSB ,Data alignment (input FIFO)" "LSB,MSB" bitfld.long 0x00 2. " OMSB ,Data alignment (output FIFO)" "LSB,MSB" bitfld.long 0x00 1. " OSGN ,Sign extension option (output FIFO)" "Disabled,Enabled" newline bitfld.long 0x00 0. " OW16 ,Bit width option (output FIFO)" "24-bit,16-bit" group.long 0xC8++0x03 line.long 0x00 "ASRMCR1C,Misc Control Register 1 For Pair C" bitfld.long 0x00 9.--11. " IWD ,Data width of the input FIFO" "24-bit,16-bit,8-bit,?..." bitfld.long 0x00 8. " IMSB ,Data alignment (input FIFO)" "LSB,MSB" bitfld.long 0x00 2. " OMSB ,Data alignment (output FIFO)" "LSB,MSB" bitfld.long 0x00 1. " OSGN ,Sign extension option (output FIFO)" "Disabled,Enabled" newline bitfld.long 0x00 0. " OW16 ,Bit width option (output FIFO)" "24-bit,16-bit" width 0x0B tree.end tree "ASRC1" base ad:0x59800000 width 10. if ((((per.l(ad:0x59800000+0x00))&0x6000)==0x6000)&&(((per.l(ad:0x59800000+0x00))&0x18000)==0x18000)&&(((per.l(ad:0x59800000+0x00))&0x60000)==0x60000)) group.long 0x00++0x03 line.long 0x00 "ASRCTR,Control Register" newline bitfld.long 0x00 17.--18. " USRC_IDRC ,Ideal ratio use for pair C" "Not used,Not used,Internal measured ratio,Ideal ratio" bitfld.long 0x00 15.--16. " USRB_IDRB ,Ideal ratio use for pair B" "Not used,Not used,Internal ratio,Ideal ratio" bitfld.long 0x00 13.--14. " USRA_IDRA ,Ideal ratio use for pair B" "Not used,Not used,Internal ratio,Ideal ratio" newline bitfld.long 0x00 4. " SRST ,Software reset" "No reset,Reset" bitfld.long 0x00 3. " ASREC ,ASRC enable C" "Disabled,Enabled" bitfld.long 0x00 2. " ASREB ,ASRC enable B" "Disabled,Enabled" newline bitfld.long 0x00 1. " ASREA ,ASRC enable A" "Disabled,Enabled" bitfld.long 0x00 0. " ASRCEN ,ASRC enable" "Disabled,Enabled" elif ((((per.l(ad:0x59800000+0x00))&0x6000)==0x6000)&&(((per.l(ad:0x59800000+0x00))&0x18000)==0x18000)&&(((per.l(ad:0x59800000+0x00))&0x60000)!=0x60000)) group.long 0x00++0x03 line.long 0x00 "ASRCTR,Control Register" bitfld.long 0x00 22. " ATSC ,ASRC pair C automatic selection for processing options" "Disabled,Enabled" newline bitfld.long 0x00 17.--18. " USRC_IDRC ,Ideal ratio use for pair C" "Not used,Not used,Internal measured ratio,Ideal ratio" bitfld.long 0x00 15.--16. " USRB_IDRB ,Ideal ratio use for pair B" "Not used,Not used,Internal ratio,Ideal ratio" bitfld.long 0x00 13.--14. " USRA_IDRA ,Ideal ratio use for pair B" "Not used,Not used,Internal ratio,Ideal ratio" newline bitfld.long 0x00 4. " SRST ,Software reset" "No reset,Reset" bitfld.long 0x00 3. " ASREC ,ASRC enable C" "Disabled,Enabled" bitfld.long 0x00 2. " ASREB ,ASRC enable B" "Disabled,Enabled" newline bitfld.long 0x00 1. " ASREA ,ASRC enable A" "Disabled,Enabled" bitfld.long 0x00 0. " ASRCEN ,ASRC enable" "Disabled,Enabled" elif ((((per.l(ad:0x59800000+0x00))&0x6000)==0x6000)&&(((per.l(ad:0x59800000+0x00))&0x18000)!=0x18000)&&(((per.l(ad:0x59800000+0x00))&0x60000)==0x60000)) group.long 0x00++0x03 line.long 0x00 "ASRCTR,Control Register" bitfld.long 0x00 21. " ATSB ,ASRC pair B automatic selection for processing options" "Disabled,Enabled" newline bitfld.long 0x00 17.--18. " USRC_IDRC ,Ideal ratio use for pair C" "Not used,Not used,Internal measured ratio,Ideal ratio" bitfld.long 0x00 15.--16. " USRB_IDRB ,Ideal ratio use for pair B" "Not used,Not used,Internal ratio,Ideal ratio" bitfld.long 0x00 13.--14. " USRA_IDRA ,Ideal ratio use for pair B" "Not used,Not used,Internal ratio,Ideal ratio" newline bitfld.long 0x00 4. " SRST ,Software reset" "No reset,Reset" bitfld.long 0x00 3. " ASREC ,ASRC enable C" "Disabled,Enabled" bitfld.long 0x00 2. " ASREB ,ASRC enable B" "Disabled,Enabled" newline bitfld.long 0x00 1. " ASREA ,ASRC enable A" "Disabled,Enabled" bitfld.long 0x00 0. " ASRCEN ,ASRC enable" "Disabled,Enabled" elif ((((per.l(ad:0x59800000+0x00))&0x6000)==0x6000)&&(((per.l(ad:0x59800000+0x00))&0x18000)!=0x18000)&&(((per.l(ad:0x59800000+0x00))&0x60000)!=0x60000)) group.long 0x00++0x03 line.long 0x00 "ASRCTR,Control Register" bitfld.long 0x00 22. " ATSC ,ASRC pair C automatic selection for processing options" "Disabled,Enabled" bitfld.long 0x00 21. " ATSB ,ASRC pair B automatic selection for processing options" "Disabled,Enabled" newline bitfld.long 0x00 17.--18. " USRC_IDRC ,Ideal ratio use for pair C" "Not used,Not used,Internal measured ratio,Ideal ratio" bitfld.long 0x00 15.--16. " USRB_IDRB ,Ideal ratio use for pair B" "Not used,Not used,Internal ratio,Ideal ratio" bitfld.long 0x00 13.--14. " USRA_IDRA ,Ideal ratio use for pair B" "Not used,Not used,Internal ratio,Ideal ratio" newline bitfld.long 0x00 4. " SRST ,Software reset" "No reset,Reset" bitfld.long 0x00 3. " ASREC ,ASRC enable C" "Disabled,Enabled" bitfld.long 0x00 2. " ASREB ,ASRC enable B" "Disabled,Enabled" newline bitfld.long 0x00 1. " ASREA ,ASRC enable A" "Disabled,Enabled" bitfld.long 0x00 0. " ASRCEN ,ASRC enable" "Disabled,Enabled" elif ((((per.l(ad:0x59800000+0x00))&0x6000)!=0x6000)&&(((per.l(ad:0x59800000+0x00))&0x18000)==0x18000)&&(((per.l(ad:0x59800000+0x00))&0x60000)==0x60000)) group.long 0x00++0x03 line.long 0x00 "ASRCTR,Control Register" bitfld.long 0x00 20. " ATSA ,ASRC pair A automatic selection for processing options" "Disabled,Enabled" newline bitfld.long 0x00 17.--18. " USRC_IDRC ,Ideal ratio use for pair C" "Not used,Not used,Internal measured ratio,Ideal ratio" bitfld.long 0x00 15.--16. " USRB_IDRB ,Ideal ratio use for pair B" "Not used,Not used,Internal ratio,Ideal ratio" bitfld.long 0x00 13.--14. " USRA_IDRA ,Ideal ratio use for pair B" "Not used,Not used,Internal ratio,Ideal ratio" newline bitfld.long 0x00 4. " SRST ,Software reset" "No reset,Reset" bitfld.long 0x00 3. " ASREC ,ASRC enable C" "Disabled,Enabled" bitfld.long 0x00 2. " ASREB ,ASRC enable B" "Disabled,Enabled" newline bitfld.long 0x00 1. " ASREA ,ASRC enable A" "Disabled,Enabled" bitfld.long 0x00 0. " ASRCEN ,ASRC enable" "Disabled,Enabled" elif ((((per.l(ad:0x59800000+0x00))&0x6000)!=0x6000)&&(((per.l(ad:0x59800000+0x00))&0x18000)==0x18000)&&(((per.l(ad:0x59800000+0x00))&0x60000)!=0x60000)) group.long 0x00++0x03 line.long 0x00 "ASRCTR,Control Register" bitfld.long 0x00 22. " ATSC ,ASRC pair C automatic selection for processing options" "Disabled,Enabled" textfld " " bitfld.long 0x00 20. " ATSA ,ASRC pair A automatic selection for processing options" "Disabled,Enabled" newline bitfld.long 0x00 17.--18. " USRC_IDRC ,Ideal ratio use for pair C" "Not used,Not used,Internal measured ratio,Ideal ratio" bitfld.long 0x00 15.--16. " USRB_IDRB ,Ideal ratio use for pair B" "Not used,Not used,Internal ratio,Ideal ratio" bitfld.long 0x00 13.--14. " USRA_IDRA ,Ideal ratio use for pair B" "Not used,Not used,Internal ratio,Ideal ratio" newline bitfld.long 0x00 4. " SRST ,Software reset" "No reset,Reset" bitfld.long 0x00 3. " ASREC ,ASRC enable C" "Disabled,Enabled" bitfld.long 0x00 2. " ASREB ,ASRC enable B" "Disabled,Enabled" newline bitfld.long 0x00 1. " ASREA ,ASRC enable A" "Disabled,Enabled" bitfld.long 0x00 0. " ASRCEN ,ASRC enable" "Disabled,Enabled" elif ((((per.l(ad:0x59800000+0x00))&0x6000)!=0x6000)&&(((per.l(ad:0x59800000+0x00))&0x18000)!=0x18000)&&(((per.l(ad:0x59800000+0x00))&0x60000)==0x60000)) group.long 0x00++0x03 line.long 0x00 "ASRCTR,Control Register" bitfld.long 0x00 21. " ATSB ,ASRC pair B automatic selection for processing options" "Disabled,Enabled" bitfld.long 0x00 20. " ATSA ,ASRC pair A automatic selection for processing options" "Disabled,Enabled" newline bitfld.long 0x00 17.--18. " USRC_IDRC ,Ideal ratio use for pair C" "Not used,Not used,Internal measured ratio,Ideal ratio" bitfld.long 0x00 15.--16. " USRB_IDRB ,Ideal ratio use for pair B" "Not used,Not used,Internal ratio,Ideal ratio" bitfld.long 0x00 13.--14. " USRA_IDRA ,Ideal ratio use for pair B" "Not used,Not used,Internal ratio,Ideal ratio" newline bitfld.long 0x00 4. " SRST ,Software reset" "No reset,Reset" bitfld.long 0x00 3. " ASREC ,ASRC enable C" "Disabled,Enabled" bitfld.long 0x00 2. " ASREB ,ASRC enable B" "Disabled,Enabled" newline bitfld.long 0x00 1. " ASREA ,ASRC enable A" "Disabled,Enabled" bitfld.long 0x00 0. " ASRCEN ,ASRC enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "ASRCTR,Control Register" bitfld.long 0x00 22. " ATSC ,ASRC pair C automatic selection for processing options" "Disabled,Enabled" bitfld.long 0x00 21. " ATSB ,ASRC pair B automatic selection for processing options" "Disabled,Enabled" bitfld.long 0x00 20. " ATSA ,ASRC pair A automatic selection for processing options" "Disabled,Enabled" newline bitfld.long 0x00 17.--18. " USRC_IDRC ,Ideal ratio use for pair C" "Not used,Not used,Internal measured ratio,Ideal ratio" bitfld.long 0x00 15.--16. " USRB_IDRB ,Ideal ratio use for pair B" "Not used,Not used,Internal ratio,Ideal ratio" bitfld.long 0x00 13.--14. " USRA_IDRA ,Ideal ratio use for pair B" "Not used,Not used,Internal ratio,Ideal ratio" newline bitfld.long 0x00 4. " SRST ,Software reset" "No reset,Reset" bitfld.long 0x00 3. " ASREC ,ASRC enable C" "Disabled,Enabled" bitfld.long 0x00 2. " ASREB ,ASRC enable B" "Disabled,Enabled" newline bitfld.long 0x00 1. " ASREA ,ASRC enable A" "Disabled,Enabled" bitfld.long 0x00 0. " ASRCEN ,ASRC enable" "Disabled,Enabled" endif group.long 0x04++0x03 line.long 0x00 "ASRIER,Interrupt Enable Register" bitfld.long 0x00 7. " AFPWE ,FP in wait state interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " AOLIE ,Overload interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " ADOEC ,Data output C interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " ADOEB ,Data output B interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " ADOEA ,Data output A interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " ADIEC ,Data input C interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " ADIEB ,Data input B interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " ADIEA ,Data input A interrupt enable" "Disabled,Enabled" group.long 0x0C++0x13 line.long 0x00 "ASRCNCR,Channel Number Configuration Register" bitfld.long 0x00 8.--11. " ANCC ,Number of C channels" "0,1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x00 4.--7. " ANCB ,Number of B channels" "0,1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x00 0.--3. " ANCA ,Number of A channels" "0,1,2,3,4,5,6,7,8,9,10,?..." line.long 0x04 "ASRCFG,Filter Configuration Status Register" rbitfld.long 0x04 23. " INIRQC ,Initialization for conversion pair C serve" "Not served,Served" rbitfld.long 0x04 22. " INIRQB ,Initialization for conversion pair B serve" "Not served,Served" rbitfld.long 0x04 21. " INIRQA ,Initialization for conversion pair A serve" "Not served,Served" bitfld.long 0x04 20. " NDPRC ,Conversion pair C parameters select" "Default,RAM" newline bitfld.long 0x04 19. " NDPRB ,Conversion pair B parameters select" "Default,RAM" bitfld.long 0x04 18. " NDPRA ,Conversion pair A parameters select" "Default,RAM" bitfld.long 0x04 16.--17. " POSTMODC ,Post-processing configuration for conversion pair C" "Upsampling-by-2,Direct-connection,Downsampling-by-2,?..." bitfld.long 0x04 14.--15. " PREMODC ,Pre-processing configuration for conversion pair C" "Upsampling-by-2,Direct-connection,Downsampling-by-2,Passthrough" newline bitfld.long 0x04 12.--13. " POSTMODB ,Post-processing configuration for conversion pair B" "Upsampling-by-2,Direct-connection,Downsampling-by-2,?..." bitfld.long 0x04 10.--11. " PREMODB ,Pre-processing configuration for conversion pair B" "Upsampling-by-2,Direct-connection,Downsampling-by-2,Passthrough" bitfld.long 0x04 8.--9. " POSTMODA ,Post-processing configuration for conversion pair A" "Upsampling-by-2,Direct-connection,Downsampling-by-2,?..." bitfld.long 0x04 6.--7. " PREMODA ,Pre-processing configuration for conversion pair A" "Upsampling-by-2,Direct-connection,Downsampling-by-2,Passthrough" line.long 0x08 "ASRCSR,Clock Source Register" bitfld.long 0x08 20.--23. " AOCSC ,Output clock source C" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,Disabled" bitfld.long 0x08 16.--19. " AOCSB ,Output clock source B" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,Disabled" bitfld.long 0x08 12.--15. " AOCSA ,Output clock source A" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,Disabled" bitfld.long 0x08 8.--11. " AICSC ,Input clock source C" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,Disabled" newline bitfld.long 0x08 4.--7. " AICSB ,Input clock source B" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,Disabled" bitfld.long 0x08 0.--3. " AICSA ,Input clock source A" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,Disabled" line.long 0x0C "ASRCDR1,Clock Divider Register 1" bitfld.long 0x0C 21.--23. " AOCDB ,Output clock divider B" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 18.--20. " AOCPB ,Output clock prescaler B" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.long 0x0C 15.--17. " AOCDA ,Output clock divider A" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 12.--14. " AOCPA ,Output clock prescaler A" "/1,/2,/4,/8,/16,/32,/64,/128" newline bitfld.long 0x0C 9.--11. " AICDB ,Input clock divider B" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 6.--8. " AICPB ,Input clock prescaler B" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.long 0x0C 3.--5. " AICDA ,Input clock divider A" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x0C 0.--2. " AICPA ,Input clock prescaler A" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x10 "ASRCDR2,Clock Divider Register 2" bitfld.long 0x10 9.--11. " AOCDC ,Output clock divider C" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x10 6.--8. " AOCPC ,Output clock prescaler C" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.long 0x10 3.--5. " AICDC ,Input clock divider C" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x10 0.--2. " AICPC ,Input clock prescaler C" "/1,/2,/4,/8,/16,/32,/64,/128" rgroup.long 0x20++0x03 line.long 0x00 "ASRSTR,Status Register" bitfld.long 0x00 21. " DSLCNT ,DSL counter input to FIFO ready" "In process,Stored" bitfld.long 0x00 20. " ATQOL ,Task queue FIFO overload" "Not overloaded,Overloaded" bitfld.long 0x00 19. " AOOLC ,Pair C output task overload" "Not overloaded,Overloaded" bitfld.long 0x00 18. " AOOLB ,Pair B output task overload" "Not overloaded,Overloaded" newline bitfld.long 0x00 17. " AOOLA ,Pair A output task overload" "Not overloaded,Overloaded" bitfld.long 0x00 16. " AIOLC ,Pair C input task overload" "Not overloaded,Overloaded" bitfld.long 0x00 15. " AIOLB ,Pair B input task overload" "Not overloaded,Overloaded" bitfld.long 0x00 14. " AIOLA ,Pair A input task overload" "Not overloaded,Overloaded" newline bitfld.long 0x00 13. " AODOC ,Output data buffer C overflow" "No overflow,Overflow" bitfld.long 0x00 12. " AODOB ,Output data buffer B overflow" "No overflow,Overflow" bitfld.long 0x00 11. " AODOA ,Output data buffer A overflow" "No overflow,Overflow" bitfld.long 0x00 10. " AIDUC ,Input data buffer C underflow" "No underflow,Underflow" newline bitfld.long 0x00 9. " AIDUB ,Input data buffer B underflow" "No underflow,Underflow" bitfld.long 0x00 8. " AIDUA ,Input data buffer A underflow" "No underflow,Underflow" bitfld.long 0x00 7. " FPWT ,FP is in wait states" "Not wait state,Wait state" bitfld.long 0x00 6. " AOLE ,Overload error flag" "No error,Error" newline bitfld.long 0x00 5. " AODFC ,Number of data in output data buffer C is greater than threshold" "Less/Equal,Greater" bitfld.long 0x00 4. " AODFB ,Number of data in output data buffer B is greater than threshold" "Less/Equal,Greater" bitfld.long 0x00 3. " AODFA ,Number of data in output data buffer A is greater than threshold" "Less/Equal,Greater" bitfld.long 0x00 2. " AIDEC ,Number of data in input data buffer C is less than threshold" "Greater/Equal,Less" newline bitfld.long 0x00 1. " AIDEB ,Number of data in input data buffer B is less than threshold" "Greater/Equal,Less" bitfld.long 0x00 0. " AIDEA ,Number of data in input data buffer A is less than threshold" "Greater/Equal,Less" group.long 0x40++0x03 line.long 0x00 "ASRPM1,Parameter Register 1" hexmask.long.tbyte 0x00 0.--23. 1. " PARAMETER_VALUE ,Parameter value" group.long 0x44++0x03 line.long 0x00 "ASRPM2,Parameter Register 2" hexmask.long.tbyte 0x00 0.--23. 1. " PARAMETER_VALUE ,Parameter value" group.long 0x48++0x03 line.long 0x00 "ASRPM3,Parameter Register 3" hexmask.long.tbyte 0x00 0.--23. 1. " PARAMETER_VALUE ,Parameter value" group.long 0x4C++0x03 line.long 0x00 "ASRPM4,Parameter Register 4" hexmask.long.tbyte 0x00 0.--23. 1. " PARAMETER_VALUE ,Parameter value" group.long 0x50++0x03 line.long 0x00 "ASRPM5,Parameter Register 5" hexmask.long.tbyte 0x00 0.--23. 1. " PARAMETER_VALUE ,Parameter value" group.long 0x54++0x03 line.long 0x00 "ASRTFR1,Task Queue FIFO Register 1" hexmask.long.byte 0x00 13.--19. 1. " TF_FILL ,Current number of entries in task queue FIFO" hexmask.long.word 0x00 6.--12. 0x40 " TF_BASE ,Base address for task queue FIFO" group.long 0x5C++0x03 line.long 0x00 "ASRCCR,Channel Counter Register" bitfld.long 0x00 20.--23. " ACOC ,The channel counter for pair C's output FIFO" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 16.--19. " ACOB ,The channel counter for pair B's output FIFO" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " ACOA ,The channel counter for pair A's output FIFO" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 8.--11. " ACIC ,The channel counter for pair C's input FIFO" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 4.--7. " ACIB ,The channel counter for pair B's input FIFO" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 0.--3. " ACIA ,The channel counter for pair A's input FIFO" "0,1,2,3,4,5,6,7,8,9,?..." wgroup.long 0x60++0x03 line.long 0x00 "ASRDIA,Data Input Register For Pair A" hexmask.long.tbyte 0x00 0.--23. 1. " DATA ,Audio data input" rgroup.long (0x60+0x04)++0x03 line.long 0x00 "ASRDOA,Data Output Register For Pair A" hexmask.long.tbyte 0x00 0.--23. 1. " DATA ,Audio data output" wgroup.long 0x68++0x03 line.long 0x00 "ASRDIB,Data Input Register For Pair B" hexmask.long.tbyte 0x00 0.--23. 1. " DATA ,Audio data input" rgroup.long (0x68+0x04)++0x03 line.long 0x00 "ASRDOB,Data Output Register For Pair B" hexmask.long.tbyte 0x00 0.--23. 1. " DATA ,Audio data output" wgroup.long 0x70++0x03 line.long 0x00 "ASRDIC,Data Input Register For Pair C" hexmask.long.tbyte 0x00 0.--23. 1. " DATA ,Audio data input" rgroup.long (0x70+0x04)++0x03 line.long 0x00 "ASRDOC,Data Output Register For Pair C" hexmask.long.tbyte 0x00 0.--23. 1. " DATA ,Audio data output" group.long 0x80++0x1F line.long 0x00 "ASRIDRHA,Ideal Ratio For Pair A-High Part Register" hexmask.long.byte 0x00 0.--7. 1. " IDRATIOA_H ,IDRATIOA high part of ideal ratio value for pair A" line.long 0x04 "ASRIDRLA,Ideal Ratio For Pair A -Low Part Register" hexmask.long.tbyte 0x04 0.--23. 1. " IDRATIOA_L ,IDRATIOA low part of ideal ratio value for pair A" line.long 0x08 "ASRIDRHB,ASRC Ideal Ratio For Pair B-High Part Register" hexmask.long.byte 0x08 0.--7. 1. " IDRATIOB_H ,IDRATIOB high part of ideal ratio value for pair B" line.long 0x0C "ASRIDRLB,Ideal Ratio For Pair B-Low Part Register" hexmask.long.tbyte 0x0C 0.--23. 1. " IDRATIOB_L ,IDRATIOB low part of ideal ratio value for pair B" line.long 0x10 "ASRIDRHC,Ideal Ratio For Pair C-High Part Register" hexmask.long.byte 0x10 0.--7. 1. " IDRATIOC_H ,IDRATIOC high part of ideal ratio value for pair C" line.long 0x14 "ASRIDRLC,Ideal Ratio For Pair C-Low Part Register" hexmask.long.tbyte 0x14 0.--23. 1. " IDRATIOC_L ,IDRATIOC low part of ideal ratio value for pair C" line.long 0x18 "ASR76K,76kHz Period In Terms Of ASRC Processing Clock Register" hexmask.long.tbyte 0x18 0.--16. 1. " ASR76K ,Value for the period of the 76kHz sampling clock" line.long 0x1C "ASR56K,56kHz Period In Terms Of ASRC Processing Clock Register" hexmask.long.tbyte 0x1C 0.--16. 1. " ASR56K ,Value for the period of the 56kHz sampling clock" group.long 0xA0++0x03 line.long 0x00 "ASRMCRA,Misc Control Register For Pair A" bitfld.long 0x00 23. " ZEROBUFA ,Buffer zeroize disable" "No,Yes" bitfld.long 0x00 22. " EXTTHRSHA ,External thresholds enable for FIFO control of pair A" "Disabled,Enabled" bitfld.long 0x00 21. " BUFSTALLA ,Stall pair A conversion in case of buffer near empty/full condition" "Disabled,Enabled" bitfld.long 0x00 20. " BYPASSPOLYA ,Bypass polyphase filtering for pair A" "Disabled,Enabled" newline bitfld.long 0x00 12.--17. " OUTFIFO_THRESHOLDA ,The threshold for pair A's output FIFO per channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. " RSYNIFA ,Re-sync input FIFO channel counter force bit" "Not forced,Forced" bitfld.long 0x00 10. " RSYNOFA ,Re-sync output FIFO channel counter force bit" "Not forced,Forced" bitfld.long 0x00 0.--5. " INFIFO_THRESHOLDA ,The threshold for pair A's input FIFO per channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xA0+0x04)++0x03 line.long 0x00 "ASRFSTA,FIFO Status Register For Pair A" bitfld.long 0x00 23. " OAFA ,Output FIFO is near full for pair A" "No,Yes" hexmask.long.byte 0x00 12.--18. 1. " OUTFIFO_FILLA ,The fillings for pair A's output FIFO per channel" bitfld.long 0x00 11. " IAEA ,Input FIFO is near empty for pair A" "No,Yes" hexmask.long.byte 0x00 0.--6. 1. " INFIFO_FILLA ,The fillings for pair A's input FIFO per channel" group.long 0xA8++0x03 line.long 0x00 "ASRMCRB,Misc Control Register For Pair B" bitfld.long 0x00 23. " ZEROBUFB ,Buffer zeroize disable" "No,Yes" bitfld.long 0x00 22. " EXTTHRSHB ,External thresholds enable for FIFO control of pair B" "Disabled,Enabled" bitfld.long 0x00 21. " BUFSTALLB ,Stall pair B conversion in case of buffer near empty/full condition" "Disabled,Enabled" bitfld.long 0x00 20. " BYPASSPOLYB ,Bypass polyphase filtering for pair B" "Disabled,Enabled" newline bitfld.long 0x00 12.--17. " OUTFIFO_THRESHOLDB ,The threshold for pair B's output FIFO per channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. " RSYNIFB ,Re-sync input FIFO channel counter force bit" "Not forced,Forced" bitfld.long 0x00 10. " RSYNOFB ,Re-sync output FIFO channel counter force bit" "Not forced,Forced" bitfld.long 0x00 0.--5. " INFIFO_THRESHOLDB ,The threshold for pair B's input FIFO per channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xA8+0x04)++0x03 line.long 0x00 "ASRFSTB,FIFO Status Register For Pair B" bitfld.long 0x00 23. " OAFB ,Output FIFO is near full for pair B" "No,Yes" hexmask.long.byte 0x00 12.--18. 1. " OUTFIFO_FILLB ,The fillings for pair B's output FIFO per channel" bitfld.long 0x00 11. " IAEB ,Input FIFO is near empty for pair B" "No,Yes" hexmask.long.byte 0x00 0.--6. 1. " INFIFO_FILLB ,The fillings for pair B's input FIFO per channel" group.long 0xB0++0x03 line.long 0x00 "ASRMCRC,Misc Control Register For Pair C" bitfld.long 0x00 23. " ZEROBUFC ,Buffer zeroize disable" "No,Yes" bitfld.long 0x00 22. " EXTTHRSHC ,External thresholds enable for FIFO control of pair C" "Disabled,Enabled" bitfld.long 0x00 21. " BUFSTALLC ,Stall pair C conversion in case of buffer near empty/full condition" "Disabled,Enabled" bitfld.long 0x00 20. " BYPASSPOLYC ,Bypass polyphase filtering for pair C" "Disabled,Enabled" newline bitfld.long 0x00 12.--17. " OUTFIFO_THRESHOLDC ,The threshold for pair C's output FIFO per channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. " RSYNIFC ,Re-sync input FIFO channel counter force bit" "Not forced,Forced" bitfld.long 0x00 10. " RSYNOFC ,Re-sync output FIFO channel counter force bit" "Not forced,Forced" bitfld.long 0x00 0.--5. " INFIFO_THRESHOLDC ,The threshold for pair C's input FIFO per channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long (0xB0+0x04)++0x03 line.long 0x00 "ASRFSTC,FIFO Status Register For Pair C" bitfld.long 0x00 23. " OAFC ,Output FIFO is near full for pair C" "No,Yes" hexmask.long.byte 0x00 12.--18. 1. " OUTFIFO_FILLC ,The fillings for pair C's output FIFO per channel" bitfld.long 0x00 11. " IAEC ,Input FIFO is near empty for pair C" "No,Yes" hexmask.long.byte 0x00 0.--6. 1. " INFIFO_FILLC ,The fillings for pair C's input FIFO per channel" group.long 0xC0++0x03 line.long 0x00 "ASRMCR1A,Misc Control Register 1 For Pair A" bitfld.long 0x00 9.--11. " IWD ,Data width of the input FIFO" "24-bit,16-bit,8-bit,?..." bitfld.long 0x00 8. " IMSB ,Data alignment (input FIFO)" "LSB,MSB" bitfld.long 0x00 2. " OMSB ,Data alignment (output FIFO)" "LSB,MSB" bitfld.long 0x00 1. " OSGN ,Sign extension option (output FIFO)" "Disabled,Enabled" newline bitfld.long 0x00 0. " OW16 ,Bit width option (output FIFO)" "24-bit,16-bit" group.long 0xC4++0x03 line.long 0x00 "ASRMCR1B,Misc Control Register 1 For Pair B" bitfld.long 0x00 9.--11. " IWD ,Data width of the input FIFO" "24-bit,16-bit,8-bit,?..." bitfld.long 0x00 8. " IMSB ,Data alignment (input FIFO)" "LSB,MSB" bitfld.long 0x00 2. " OMSB ,Data alignment (output FIFO)" "LSB,MSB" bitfld.long 0x00 1. " OSGN ,Sign extension option (output FIFO)" "Disabled,Enabled" newline bitfld.long 0x00 0. " OW16 ,Bit width option (output FIFO)" "24-bit,16-bit" group.long 0xC8++0x03 line.long 0x00 "ASRMCR1C,Misc Control Register 1 For Pair C" bitfld.long 0x00 9.--11. " IWD ,Data width of the input FIFO" "24-bit,16-bit,8-bit,?..." bitfld.long 0x00 8. " IMSB ,Data alignment (input FIFO)" "LSB,MSB" bitfld.long 0x00 2. " OMSB ,Data alignment (output FIFO)" "LSB,MSB" bitfld.long 0x00 1. " OSGN ,Sign extension option (output FIFO)" "Disabled,Enabled" newline bitfld.long 0x00 0. " OW16 ,Bit width option (output FIFO)" "24-bit,16-bit" width 0x0B tree.end tree.end tree "AUDMIX (Audio Mixer)" base ad:0x59840000 width 11. group.long 0x200++0x03 line.long 0x00 "CTR,Mixer Control Register" bitfld.long 0x00 10. " SYNCSRC ,Sync mode clock source" "TDM 1,TDM 2" bitfld.long 0x00 9. " SYNCMODE ,Sync mode configuration enable" "Disabled,Enabled" bitfld.long 0x00 8. " MASKCKDF ,Clock frequency difference error mask" "Not masked,Masked" bitfld.long 0x00 7. " MASKRTDF ,Frame rate difference error mask" "Not masked,Masked" newline bitfld.long 0x00 6. " OUTCKPOL ,Polarity of bit clock of TDM out interface" "Positive edge,Negative edge" bitfld.long 0x00 3.--5. " OUTWIDTH ,Audio sample width in TDM outgoing frame" "16 bit,18 bit,20 bit,24 bit,32 bit,32 bit,32 bit,32 bit" bitfld.long 0x00 1.--2. " OUTSRC ,Output source selection" "Disabled,TDM 1,TDM 2,Mixed" bitfld.long 0x00 0. " MIXCLK ,Mixing clock source selection" "TDM 1 clock,TDM 2 clock" rgroup.long 0x204++0x03 line.long 0x00 "STR,Mixer Status Register" bitfld.long 0x00 2.--3. " MIXSTAT ,Mixer status" "DISABLED,TDM_1,TDM_2,MIXED" bitfld.long 0x00 1. " CLKDIFF ,Bit clock difference" "Matched,Mismatched" bitfld.long 0x00 0. " RATEDIFF ,Rate difference" "Matched,Mismatched" group.long (0x200+0x08)++0x13 line.long 0x00 "ATCR0,Attenuation Control Register 0" hexmask.long.word 0x00 2.--13. 1. " ATSTPDIV ,Step divider" bitfld.long 0x00 1. " AT_UPDN ,Attenuation direction" "Downward,Upward" bitfld.long 0x00 0. " AT_EN ,Attenuation enable" "Disabled,Enabled" line.long 0x04 "ATIVAL0,Attenuation Initial value Register 0" hexmask.long.tbyte 0x04 0.--17. 1. " ATINTVAL ,Attenuation initial value" line.long 0x08 "ATSTPUP0,Attenuation step up factor Register 0" hexmask.long.tbyte 0x08 0.--17. 1. " ATSTEPUP ,Attenuation step up factor" line.long 0x0C "ATSTPDN0,Attenuation step down factor Register" hexmask.long.tbyte 0x0C 0.--17. 1. " ATSTEPDN ,Attenuation step down factor" line.long 0x10 "ATSTPTGT0,Attenuation step target Register" hexmask.long.tbyte 0x10 0.--17. 1. " ATSTPTG ,Attenuation step target value" rgroup.long (0x200+0x1C)++0x07 line.long 0x00 "ATTNVAL0,Attenuation Value Register 0" hexmask.long.tbyte 0x00 0.--17. 1. " ATCURVAL ,Current value of attenuation" line.long 0x04 "ATSTP0,Attenuation step number Register 0" hexmask.long.tbyte 0x04 0.--17. 1. " STPCTR ,Step counter value" group.long (0x220+0x08)++0x13 line.long 0x00 "ATCR1,Attenuation Control Register 1" hexmask.long.word 0x00 2.--13. 1. " ATSTPDIV ,Step divider" bitfld.long 0x00 1. " AT_UPDN ,Attenuation direction" "Downward,Upward" bitfld.long 0x00 0. " AT_EN ,Attenuation enable" "Disabled,Enabled" line.long 0x04 "ATIVAL1,Attenuation Initial value Register 1" hexmask.long.tbyte 0x04 0.--17. 1. " ATINTVAL ,Attenuation initial value" line.long 0x08 "ATSTPUP1,Attenuation step up factor Register 1" hexmask.long.tbyte 0x08 0.--17. 1. " ATSTEPUP ,Attenuation step up factor" line.long 0x0C "ATSTPDN1,Attenuation step down factor Register" hexmask.long.tbyte 0x0C 0.--17. 1. " ATSTEPDN ,Attenuation step down factor" line.long 0x10 "ATSTPTGT1,Attenuation step target Register" hexmask.long.tbyte 0x10 0.--17. 1. " ATSTPTG ,Attenuation step target value" rgroup.long (0x220+0x1C)++0x07 line.long 0x00 "ATTNVAL1,Attenuation Value Register 1" hexmask.long.tbyte 0x00 0.--17. 1. " ATCURVAL ,Current value of attenuation" line.long 0x04 "ATSTP1,Attenuation step number Register 1" hexmask.long.tbyte 0x04 0.--17. 1. " STPCTR ,Step counter value" width 0x0B tree.end tree.open "eDMA (Enhanced Direct Memory Access)" tree.open "eDMA0" tree "MP (Management Page)" base ad:0x591F0000 width 12. group.long 0x00++0x03 line.long 0x00 "CSR,Management Page Control Register" rbitfld.long 0x00 31. " ACTIVE ,DMA active status" "Idle,Executing" rbitfld.long 0x00 24.--28. " ACTIVE_ID ,Active channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 9. " CX ,Cancel transfer" "Not canceled,Canceled" bitfld.long 0x00 8. " ECX ,Cancel transfer with error" "Not canceled,Canceled" newline bitfld.long 0x00 7. " GMRC ,Global master ID replication control" "Disabled,Enabled" bitfld.long 0x00 6. " GCLC ,Global channel linking control" "Disabled,Enabled" bitfld.long 0x00 5. " HALT ,Halt DMA operations" "Not halted,Halted" bitfld.long 0x00 4. " HAE ,Halt after error" "Not halted,Halted" newline bitfld.long 0x00 2. " ERCA ,Channel arbitration select" "Fixed priority,Round robin" bitfld.long 0x00 1. " EDBG ,DMA operation in debug mode" "Continue,Stall" rgroup.long 0x04++0x0B line.long 0x00 "ES,Management Page Error Status Register" bitfld.long 0x00 31. " VLD ,Valid" "No error,Error" bitfld.long 0x00 24.--28. " ERRCHN ,Error channel number or canceled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 9. " UCE ,Uncorrectable TCD error during channel execution" "No error,Error" bitfld.long 0x00 8. " ECX ,Transfer canceled" "Not canceled,Canceled" newline bitfld.long 0x00 7. " SAE ,Source address error" "No error,Error" bitfld.long 0x00 6. " SOE ,Source offset error" "No error,Error" bitfld.long 0x00 5. " DAE ,Destination address error" "No error,Error" bitfld.long 0x00 4. " DOE ,Destination offset error" "No error,Error" newline bitfld.long 0x00 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" bitfld.long 0x00 2. " SGE ,Scatter/gather configuration error" "No error,Error" bitfld.long 0x00 1. " SBE ,Source bus error" "No error,Error" bitfld.long 0x00 0. " DBE ,Destination bus error" "No error,Error" line.long 0x04 "INT,Management Page Interrupt Request Status Register" bitfld.long 0x04 31. " INT[31] ,Interrupt request status for channel 31" "Not requested,Requested" bitfld.long 0x04 30. " [30] ,Interrupt request status for channel 30" "Not requested,Requested" bitfld.long 0x04 29. " [29] ,Interrupt request status for channel 29" "Not requested,Requested" bitfld.long 0x04 28. " [28] ,Interrupt request status for channel 28" "Not requested,Requested" newline bitfld.long 0x04 27. " [27] ,Interrupt request status for channel 27" "Not requested,Requested" bitfld.long 0x04 26. " [26] ,Interrupt request status for channel 26" "Not requested,Requested" bitfld.long 0x04 25. " [25] ,Interrupt request status for channel 25" "Not requested,Requested" bitfld.long 0x04 24. " [24] ,Interrupt request status for channel 24" "Not requested,Requested" newline bitfld.long 0x04 23. " [23] ,Interrupt request status for channel 23" "Not requested,Requested" bitfld.long 0x04 22. " [22] ,Interrupt request status for channel 22" "Not requested,Requested" bitfld.long 0x04 21. " [21] ,Interrupt request status for channel 21" "Not requested,Requested" bitfld.long 0x04 20. " [20] ,Interrupt request status for channel 20" "Not requested,Requested" newline bitfld.long 0x04 19. " [19] ,Interrupt request status for channel 19" "Not requested,Requested" bitfld.long 0x04 18. " [18] ,Interrupt request status for channel 18" "Not requested,Requested" bitfld.long 0x04 17. " [17] ,Interrupt request status for channel 17" "Not requested,Requested" bitfld.long 0x04 16. " [16] ,Interrupt request status for channel 16" "Not requested,Requested" newline bitfld.long 0x04 15. " [15] ,Interrupt request status for channel 15" "Not requested,Requested" bitfld.long 0x04 14. " [14] ,Interrupt request status for channel 14" "Not requested,Requested" bitfld.long 0x04 13. " [13] ,Interrupt request status for channel 13" "Not requested,Requested" bitfld.long 0x04 12. " [12] ,Interrupt request status for channel 12" "Not requested,Requested" newline bitfld.long 0x04 11. " [11] ,Interrupt request status for channel 11" "Not requested,Requested" bitfld.long 0x04 10. " [10] ,Interrupt request status for channel 10" "Not requested,Requested" bitfld.long 0x04 9. " [9] ,Interrupt request status for channel 9" "Not requested,Requested" bitfld.long 0x04 8. " [8] ,Interrupt request status for channel 8" "Not requested,Requested" newline bitfld.long 0x04 7. " [7] ,Interrupt request status for channel 7" "Not requested,Requested" bitfld.long 0x04 6. " [6] ,Interrupt request status for channel 6" "Not requested,Requested" bitfld.long 0x04 5. " [5] ,Interrupt request status for channel 5" "Not requested,Requested" bitfld.long 0x04 4. " [4] ,Interrupt request status for channel 4" "Not requested,Requested" newline bitfld.long 0x04 3. " [3] ,Interrupt request status for channel 3" "Not requested,Requested" bitfld.long 0x04 2. " [2] ,Interrupt request status for channel 2" "Not requested,Requested" bitfld.long 0x04 1. " [1] ,Interrupt request status for channel 1" "Not requested,Requested" bitfld.long 0x04 0. " [0] ,Interrupt request status for channel 0" "Not requested,Requested" line.long 0x08 "HRS,Management Page Hardware Request Status Register" bitfld.long 0x08 31. " HRS[31] ,Hardware request status for channel 31" "Not requested,Requested" bitfld.long 0x08 30. " [30] ,Hardware request status for channel 30" "Not requested,Requested" bitfld.long 0x08 29. " [29] ,Hardware request status for channel 29" "Not requested,Requested" bitfld.long 0x08 28. " [28] ,Hardware request status for channel 28" "Not requested,Requested" newline bitfld.long 0x08 27. " [27] ,Hardware request status for channel 27" "Not requested,Requested" bitfld.long 0x08 26. " [26] ,Hardware request status for channel 26" "Not requested,Requested" bitfld.long 0x08 25. " [25] ,Hardware request status for channel 25" "Not requested,Requested" bitfld.long 0x08 24. " [24] ,Hardware request status for channel 24" "Not requested,Requested" newline bitfld.long 0x08 23. " [23] ,Hardware request status for channel 23" "Not requested,Requested" bitfld.long 0x08 22. " [22] ,Hardware request status for channel 22" "Not requested,Requested" bitfld.long 0x08 21. " [21] ,Hardware request status for channel 21" "Not requested,Requested" bitfld.long 0x08 20. " [20] ,Hardware request status for channel 20" "Not requested,Requested" newline bitfld.long 0x08 19. " [19] ,Hardware request status for channel 19" "Not requested,Requested" bitfld.long 0x08 18. " [18] ,Hardware request status for channel 18" "Not requested,Requested" bitfld.long 0x08 17. " [17] ,Hardware request status for channel 17" "Not requested,Requested" bitfld.long 0x08 16. " [16] ,Hardware request status for channel 16" "Not requested,Requested" newline bitfld.long 0x08 15. " [15] ,Hardware request status for channel 15" "Not requested,Requested" bitfld.long 0x08 14. " [14] ,Hardware request status for channel 14" "Not requested,Requested" bitfld.long 0x08 13. " [13] ,Hardware request status for channel 13" "Not requested,Requested" bitfld.long 0x08 12. " [12] ,Hardware request status for channel 12" "Not requested,Requested" newline bitfld.long 0x08 11. " [11] ,Hardware request status for channel 11" "Not requested,Requested" bitfld.long 0x08 10. " [10] ,Hardware request status for channel 10" "Not requested,Requested" bitfld.long 0x08 9. " [9] ,Hardware request status for channel 9" "Not requested,Requested" bitfld.long 0x08 8. " [8] ,Hardware request status for channel 8" "Not requested,Requested" newline bitfld.long 0x08 7. " [7] ,Hardware request status for channel 7" "Not requested,Requested" bitfld.long 0x08 6. " [6] ,Hardware request status for channel 6" "Not requested,Requested" bitfld.long 0x08 5. " [5] ,Hardware request status for channel 5" "Not requested,Requested" bitfld.long 0x08 4. " [4] ,Hardware request status for channel 4" "Not requested,Requested" newline bitfld.long 0x08 3. " [3] ,Hardware request status for channel 3" "Not requested,Requested" bitfld.long 0x08 2. " [2] ,Hardware request status for channel 2" "Not requested,Requested" bitfld.long 0x08 1. " [1] ,Hardware request status for channel 1" "Not requested,Requested" bitfld.long 0x08 0. " [0] ,Hardware request status for channel 0" "Not requested,Requested" newline group.long 0x100++0x03 line.long 0x00 "CH0_GRPRI,Channel 0 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x104++0x03 line.long 0x00 "CH1_GRPRI,Channel 1 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x108++0x03 line.long 0x00 "CH2_GRPRI,Channel 2 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x10C++0x03 line.long 0x00 "CH3_GRPRI,Channel 3 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x110++0x03 line.long 0x00 "CH4_GRPRI,Channel 4 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x114++0x03 line.long 0x00 "CH5_GRPRI,Channel 5 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x118++0x03 line.long 0x00 "CH6_GRPRI,Channel 6 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x11C++0x03 line.long 0x00 "CH7_GRPRI,Channel 7 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x120++0x03 line.long 0x00 "CH8_GRPRI,Channel 8 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x124++0x03 line.long 0x00 "CH9_GRPRI,Channel 9 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x128++0x03 line.long 0x00 "CH10_GRPRI,Channel 10 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x12C++0x03 line.long 0x00 "CH11_GRPRI,Channel 11 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x130++0x03 line.long 0x00 "CH12_GRPRI,Channel 12 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x134++0x03 line.long 0x00 "CH13_GRPRI,Channel 13 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x138++0x03 line.long 0x00 "CH14_GRPRI,Channel 14 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x13C++0x03 line.long 0x00 "CH15_GRPRI,Channel 15 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x140++0x03 line.long 0x00 "CH16_GRPRI,Channel 16 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x144++0x03 line.long 0x00 "CH17_GRPRI,Channel 17 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x148++0x03 line.long 0x00 "CH18_GRPRI,Channel 18 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x14C++0x03 line.long 0x00 "CH19_GRPRI,Channel 19 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x150++0x03 line.long 0x00 "CH20_GRPRI,Channel 20 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x154++0x03 line.long 0x00 "CH21_GRPRI,Channel 21 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x158++0x03 line.long 0x00 "CH22_GRPRI,Channel 22 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 22" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x15C++0x03 line.long 0x00 "CH23_GRPRI,Channel 23 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 23" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x160++0x03 line.long 0x00 "CH24_GRPRI,Channel 24 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x164++0x03 line.long 0x00 "CH25_GRPRI,Channel 25 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 25" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x168++0x03 line.long 0x00 "CH26_GRPRI,Channel 26 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 26" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x16C++0x03 line.long 0x00 "CH27_GRPRI,Channel 27 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x170++0x03 line.long 0x00 "CH28_GRPRI,Channel 28 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 28" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x174++0x03 line.long 0x00 "CH29_GRPRI,Channel 29 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 29" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x178++0x03 line.long 0x00 "CH30_GRPRI,Channel 30 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 30" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x17C++0x03 line.long 0x00 "CH31_GRPRI,Channel 31 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree.open "TCD (Transfer Control Descriptor)" tree "Channel 0" base ad:0x59200000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59200000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59200000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59200000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 1" base ad:0x59210000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59210000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59210000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59210000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 2" base ad:0x59220000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59220000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59220000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59220000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 3" base ad:0x59230000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59230000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59230000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59230000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 4" base ad:0x59240000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59240000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59240000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59240000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 5" base ad:0x59250000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59250000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59250000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59250000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 6" base ad:0x59260000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59260000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59260000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59260000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 7" base ad:0x59270000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59270000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59270000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59270000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 8" base ad:0x59280000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59280000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59280000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59280000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 9" base ad:0x59290000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59290000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59290000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59290000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 10" base ad:0x592A0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x592A0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x592A0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x592A0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 11" base ad:0x592B0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x592B0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x592B0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x592B0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 12" base ad:0x592C0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x592C0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x592C0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x592C0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 13" base ad:0x592D0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x592D0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x592D0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x592D0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 14" base ad:0x592E0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x592E0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x592E0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x592E0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 15" base ad:0x592F0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x592F0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x592F0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x592F0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 16" base ad:0x59300000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59300000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59300000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59300000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 17" base ad:0x59310000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59310000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59310000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59310000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 18" base ad:0x59320000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59320000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59320000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59320000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 19" base ad:0x59330000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59330000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59330000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59330000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 20" base ad:0x59340000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59340000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59340000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59340000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 21" base ad:0x59350000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59350000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59350000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59350000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 22" base ad:0x59360000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59360000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59360000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59360000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 23" base ad:0x59370000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59370000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59370000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59370000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 24" base ad:0x59380000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59380000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59380000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59380000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 25" base ad:0x59390000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59390000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59390000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59390000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 26" base ad:0x593A0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x593A0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x593A0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x593A0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 27" base ad:0x593B0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x593B0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x593B0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x593B0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 28" base ad:0x593C0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x593C0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x593C0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x593C0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 29" base ad:0x593D0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x593D0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x593D0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x593D0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 30" base ad:0x593E0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x593E0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x593E0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x593E0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 31" base ad:0x593F0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x593F0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x593F0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x593F0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree.end tree.end tree.open "eDMA1" tree "MP (Management Page)" base ad:0x599F0000 width 12. group.long 0x00++0x03 line.long 0x00 "CSR,Management Page Control Register" rbitfld.long 0x00 31. " ACTIVE ,DMA active status" "Idle,Executing" rbitfld.long 0x00 24.--28. " ACTIVE_ID ,Active channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 9. " CX ,Cancel transfer" "Not canceled,Canceled" bitfld.long 0x00 8. " ECX ,Cancel transfer with error" "Not canceled,Canceled" newline bitfld.long 0x00 7. " GMRC ,Global master ID replication control" "Disabled,Enabled" bitfld.long 0x00 6. " GCLC ,Global channel linking control" "Disabled,Enabled" bitfld.long 0x00 5. " HALT ,Halt DMA operations" "Not halted,Halted" bitfld.long 0x00 4. " HAE ,Halt after error" "Not halted,Halted" newline bitfld.long 0x00 2. " ERCA ,Channel arbitration select" "Fixed priority,Round robin" bitfld.long 0x00 1. " EDBG ,DMA operation in debug mode" "Continue,Stall" rgroup.long 0x04++0x0B line.long 0x00 "ES,Management Page Error Status Register" bitfld.long 0x00 31. " VLD ,Valid" "No error,Error" bitfld.long 0x00 24.--28. " ERRCHN ,Error channel number or canceled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 9. " UCE ,Uncorrectable TCD error during channel execution" "No error,Error" bitfld.long 0x00 8. " ECX ,Transfer canceled" "Not canceled,Canceled" newline bitfld.long 0x00 7. " SAE ,Source address error" "No error,Error" bitfld.long 0x00 6. " SOE ,Source offset error" "No error,Error" bitfld.long 0x00 5. " DAE ,Destination address error" "No error,Error" bitfld.long 0x00 4. " DOE ,Destination offset error" "No error,Error" newline bitfld.long 0x00 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" bitfld.long 0x00 2. " SGE ,Scatter/gather configuration error" "No error,Error" bitfld.long 0x00 1. " SBE ,Source bus error" "No error,Error" bitfld.long 0x00 0. " DBE ,Destination bus error" "No error,Error" line.long 0x04 "INT,Management Page Interrupt Request Status Register" bitfld.long 0x04 31. " INT[31] ,Interrupt request status for channel 31" "Not requested,Requested" bitfld.long 0x04 30. " [30] ,Interrupt request status for channel 30" "Not requested,Requested" bitfld.long 0x04 29. " [29] ,Interrupt request status for channel 29" "Not requested,Requested" bitfld.long 0x04 28. " [28] ,Interrupt request status for channel 28" "Not requested,Requested" newline bitfld.long 0x04 27. " [27] ,Interrupt request status for channel 27" "Not requested,Requested" bitfld.long 0x04 26. " [26] ,Interrupt request status for channel 26" "Not requested,Requested" bitfld.long 0x04 25. " [25] ,Interrupt request status for channel 25" "Not requested,Requested" bitfld.long 0x04 24. " [24] ,Interrupt request status for channel 24" "Not requested,Requested" newline bitfld.long 0x04 23. " [23] ,Interrupt request status for channel 23" "Not requested,Requested" bitfld.long 0x04 22. " [22] ,Interrupt request status for channel 22" "Not requested,Requested" bitfld.long 0x04 21. " [21] ,Interrupt request status for channel 21" "Not requested,Requested" bitfld.long 0x04 20. " [20] ,Interrupt request status for channel 20" "Not requested,Requested" newline bitfld.long 0x04 19. " [19] ,Interrupt request status for channel 19" "Not requested,Requested" bitfld.long 0x04 18. " [18] ,Interrupt request status for channel 18" "Not requested,Requested" bitfld.long 0x04 17. " [17] ,Interrupt request status for channel 17" "Not requested,Requested" bitfld.long 0x04 16. " [16] ,Interrupt request status for channel 16" "Not requested,Requested" newline bitfld.long 0x04 15. " [15] ,Interrupt request status for channel 15" "Not requested,Requested" bitfld.long 0x04 14. " [14] ,Interrupt request status for channel 14" "Not requested,Requested" bitfld.long 0x04 13. " [13] ,Interrupt request status for channel 13" "Not requested,Requested" bitfld.long 0x04 12. " [12] ,Interrupt request status for channel 12" "Not requested,Requested" newline bitfld.long 0x04 11. " [11] ,Interrupt request status for channel 11" "Not requested,Requested" bitfld.long 0x04 10. " [10] ,Interrupt request status for channel 10" "Not requested,Requested" bitfld.long 0x04 9. " [9] ,Interrupt request status for channel 9" "Not requested,Requested" bitfld.long 0x04 8. " [8] ,Interrupt request status for channel 8" "Not requested,Requested" newline bitfld.long 0x04 7. " [7] ,Interrupt request status for channel 7" "Not requested,Requested" bitfld.long 0x04 6. " [6] ,Interrupt request status for channel 6" "Not requested,Requested" bitfld.long 0x04 5. " [5] ,Interrupt request status for channel 5" "Not requested,Requested" bitfld.long 0x04 4. " [4] ,Interrupt request status for channel 4" "Not requested,Requested" newline bitfld.long 0x04 3. " [3] ,Interrupt request status for channel 3" "Not requested,Requested" bitfld.long 0x04 2. " [2] ,Interrupt request status for channel 2" "Not requested,Requested" bitfld.long 0x04 1. " [1] ,Interrupt request status for channel 1" "Not requested,Requested" bitfld.long 0x04 0. " [0] ,Interrupt request status for channel 0" "Not requested,Requested" line.long 0x08 "HRS,Management Page Hardware Request Status Register" bitfld.long 0x08 31. " HRS[31] ,Hardware request status for channel 31" "Not requested,Requested" bitfld.long 0x08 30. " [30] ,Hardware request status for channel 30" "Not requested,Requested" bitfld.long 0x08 29. " [29] ,Hardware request status for channel 29" "Not requested,Requested" bitfld.long 0x08 28. " [28] ,Hardware request status for channel 28" "Not requested,Requested" newline bitfld.long 0x08 27. " [27] ,Hardware request status for channel 27" "Not requested,Requested" bitfld.long 0x08 26. " [26] ,Hardware request status for channel 26" "Not requested,Requested" bitfld.long 0x08 25. " [25] ,Hardware request status for channel 25" "Not requested,Requested" bitfld.long 0x08 24. " [24] ,Hardware request status for channel 24" "Not requested,Requested" newline bitfld.long 0x08 23. " [23] ,Hardware request status for channel 23" "Not requested,Requested" bitfld.long 0x08 22. " [22] ,Hardware request status for channel 22" "Not requested,Requested" bitfld.long 0x08 21. " [21] ,Hardware request status for channel 21" "Not requested,Requested" bitfld.long 0x08 20. " [20] ,Hardware request status for channel 20" "Not requested,Requested" newline bitfld.long 0x08 19. " [19] ,Hardware request status for channel 19" "Not requested,Requested" bitfld.long 0x08 18. " [18] ,Hardware request status for channel 18" "Not requested,Requested" bitfld.long 0x08 17. " [17] ,Hardware request status for channel 17" "Not requested,Requested" bitfld.long 0x08 16. " [16] ,Hardware request status for channel 16" "Not requested,Requested" newline bitfld.long 0x08 15. " [15] ,Hardware request status for channel 15" "Not requested,Requested" bitfld.long 0x08 14. " [14] ,Hardware request status for channel 14" "Not requested,Requested" bitfld.long 0x08 13. " [13] ,Hardware request status for channel 13" "Not requested,Requested" bitfld.long 0x08 12. " [12] ,Hardware request status for channel 12" "Not requested,Requested" newline bitfld.long 0x08 11. " [11] ,Hardware request status for channel 11" "Not requested,Requested" bitfld.long 0x08 10. " [10] ,Hardware request status for channel 10" "Not requested,Requested" bitfld.long 0x08 9. " [9] ,Hardware request status for channel 9" "Not requested,Requested" bitfld.long 0x08 8. " [8] ,Hardware request status for channel 8" "Not requested,Requested" newline bitfld.long 0x08 7. " [7] ,Hardware request status for channel 7" "Not requested,Requested" bitfld.long 0x08 6. " [6] ,Hardware request status for channel 6" "Not requested,Requested" bitfld.long 0x08 5. " [5] ,Hardware request status for channel 5" "Not requested,Requested" bitfld.long 0x08 4. " [4] ,Hardware request status for channel 4" "Not requested,Requested" newline bitfld.long 0x08 3. " [3] ,Hardware request status for channel 3" "Not requested,Requested" bitfld.long 0x08 2. " [2] ,Hardware request status for channel 2" "Not requested,Requested" bitfld.long 0x08 1. " [1] ,Hardware request status for channel 1" "Not requested,Requested" bitfld.long 0x08 0. " [0] ,Hardware request status for channel 0" "Not requested,Requested" newline group.long 0x100++0x03 line.long 0x00 "CH0_GRPRI,Channel 0 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x104++0x03 line.long 0x00 "CH1_GRPRI,Channel 1 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x108++0x03 line.long 0x00 "CH2_GRPRI,Channel 2 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x10C++0x03 line.long 0x00 "CH3_GRPRI,Channel 3 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x110++0x03 line.long 0x00 "CH4_GRPRI,Channel 4 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x114++0x03 line.long 0x00 "CH5_GRPRI,Channel 5 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x118++0x03 line.long 0x00 "CH6_GRPRI,Channel 6 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x11C++0x03 line.long 0x00 "CH7_GRPRI,Channel 7 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x120++0x03 line.long 0x00 "CH8_GRPRI,Channel 8 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x124++0x03 line.long 0x00 "CH9_GRPRI,Channel 9 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x128++0x03 line.long 0x00 "CH10_GRPRI,Channel 10 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x12C++0x03 line.long 0x00 "CH11_GRPRI,Channel 11 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x130++0x03 line.long 0x00 "CH12_GRPRI,Channel 12 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x134++0x03 line.long 0x00 "CH13_GRPRI,Channel 13 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x138++0x03 line.long 0x00 "CH14_GRPRI,Channel 14 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x13C++0x03 line.long 0x00 "CH15_GRPRI,Channel 15 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree.open "TCD (Transfer Control Descriptor)" tree "Channel 0" base ad:0x59A00000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59A00000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59A00000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59A00000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 1" base ad:0x59A10000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59A10000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59A10000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59A10000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 2" base ad:0x59A20000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59A20000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59A20000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59A20000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 3" base ad:0x59A30000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59A30000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59A30000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59A30000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 4" base ad:0x59A40000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59A40000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59A40000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59A40000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 5" base ad:0x59A50000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59A50000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59A50000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59A50000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 6" base ad:0x59A60000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59A60000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59A60000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59A60000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 7" base ad:0x59A70000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59A70000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59A70000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59A70000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 8" base ad:0x59A80000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59A80000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59A80000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59A80000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 9" base ad:0x59A90000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59A90000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59A90000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59A90000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 10" base ad:0x59AA0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59AA0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59AA0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59AA0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 11" base ad:0x59AB0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59AB0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59AB0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59AB0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 12" base ad:0x59AC0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59AC0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59AC0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59AC0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 13" base ad:0x59AD0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59AD0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59AD0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59AD0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 14" base ad:0x59AE0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59AE0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59AE0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59AE0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 15" base ad:0x59AF0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x59AF0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x59AF0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x59AF0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree.end tree.end tree.open "eDMA2" tree "MP (Management Page)" base ad:0x5A1F0000 width 12. group.long 0x00++0x03 line.long 0x00 "CSR,Management Page Control Register" rbitfld.long 0x00 31. " ACTIVE ,DMA active status" "Idle,Executing" rbitfld.long 0x00 24.--28. " ACTIVE_ID ,Active channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 9. " CX ,Cancel transfer" "Not canceled,Canceled" bitfld.long 0x00 8. " ECX ,Cancel transfer with error" "Not canceled,Canceled" newline bitfld.long 0x00 7. " GMRC ,Global master ID replication control" "Disabled,Enabled" bitfld.long 0x00 6. " GCLC ,Global channel linking control" "Disabled,Enabled" bitfld.long 0x00 5. " HALT ,Halt DMA operations" "Not halted,Halted" bitfld.long 0x00 4. " HAE ,Halt after error" "Not halted,Halted" newline bitfld.long 0x00 2. " ERCA ,Channel arbitration select" "Fixed priority,Round robin" bitfld.long 0x00 1. " EDBG ,DMA operation in debug mode" "Continue,Stall" rgroup.long 0x04++0x0B line.long 0x00 "ES,Management Page Error Status Register" bitfld.long 0x00 31. " VLD ,Valid" "No error,Error" bitfld.long 0x00 24.--28. " ERRCHN ,Error channel number or canceled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 9. " UCE ,Uncorrectable TCD error during channel execution" "No error,Error" bitfld.long 0x00 8. " ECX ,Transfer canceled" "Not canceled,Canceled" newline bitfld.long 0x00 7. " SAE ,Source address error" "No error,Error" bitfld.long 0x00 6. " SOE ,Source offset error" "No error,Error" bitfld.long 0x00 5. " DAE ,Destination address error" "No error,Error" bitfld.long 0x00 4. " DOE ,Destination offset error" "No error,Error" newline bitfld.long 0x00 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" bitfld.long 0x00 2. " SGE ,Scatter/gather configuration error" "No error,Error" bitfld.long 0x00 1. " SBE ,Source bus error" "No error,Error" bitfld.long 0x00 0. " DBE ,Destination bus error" "No error,Error" line.long 0x04 "INT,Management Page Interrupt Request Status Register" bitfld.long 0x04 31. " INT[31] ,Interrupt request status for channel 31" "Not requested,Requested" bitfld.long 0x04 30. " [30] ,Interrupt request status for channel 30" "Not requested,Requested" bitfld.long 0x04 29. " [29] ,Interrupt request status for channel 29" "Not requested,Requested" bitfld.long 0x04 28. " [28] ,Interrupt request status for channel 28" "Not requested,Requested" newline bitfld.long 0x04 27. " [27] ,Interrupt request status for channel 27" "Not requested,Requested" bitfld.long 0x04 26. " [26] ,Interrupt request status for channel 26" "Not requested,Requested" bitfld.long 0x04 25. " [25] ,Interrupt request status for channel 25" "Not requested,Requested" bitfld.long 0x04 24. " [24] ,Interrupt request status for channel 24" "Not requested,Requested" newline bitfld.long 0x04 23. " [23] ,Interrupt request status for channel 23" "Not requested,Requested" bitfld.long 0x04 22. " [22] ,Interrupt request status for channel 22" "Not requested,Requested" bitfld.long 0x04 21. " [21] ,Interrupt request status for channel 21" "Not requested,Requested" bitfld.long 0x04 20. " [20] ,Interrupt request status for channel 20" "Not requested,Requested" newline bitfld.long 0x04 19. " [19] ,Interrupt request status for channel 19" "Not requested,Requested" bitfld.long 0x04 18. " [18] ,Interrupt request status for channel 18" "Not requested,Requested" bitfld.long 0x04 17. " [17] ,Interrupt request status for channel 17" "Not requested,Requested" bitfld.long 0x04 16. " [16] ,Interrupt request status for channel 16" "Not requested,Requested" newline bitfld.long 0x04 15. " [15] ,Interrupt request status for channel 15" "Not requested,Requested" bitfld.long 0x04 14. " [14] ,Interrupt request status for channel 14" "Not requested,Requested" bitfld.long 0x04 13. " [13] ,Interrupt request status for channel 13" "Not requested,Requested" bitfld.long 0x04 12. " [12] ,Interrupt request status for channel 12" "Not requested,Requested" newline bitfld.long 0x04 11. " [11] ,Interrupt request status for channel 11" "Not requested,Requested" bitfld.long 0x04 10. " [10] ,Interrupt request status for channel 10" "Not requested,Requested" bitfld.long 0x04 9. " [9] ,Interrupt request status for channel 9" "Not requested,Requested" bitfld.long 0x04 8. " [8] ,Interrupt request status for channel 8" "Not requested,Requested" newline bitfld.long 0x04 7. " [7] ,Interrupt request status for channel 7" "Not requested,Requested" bitfld.long 0x04 6. " [6] ,Interrupt request status for channel 6" "Not requested,Requested" bitfld.long 0x04 5. " [5] ,Interrupt request status for channel 5" "Not requested,Requested" bitfld.long 0x04 4. " [4] ,Interrupt request status for channel 4" "Not requested,Requested" newline bitfld.long 0x04 3. " [3] ,Interrupt request status for channel 3" "Not requested,Requested" bitfld.long 0x04 2. " [2] ,Interrupt request status for channel 2" "Not requested,Requested" bitfld.long 0x04 1. " [1] ,Interrupt request status for channel 1" "Not requested,Requested" bitfld.long 0x04 0. " [0] ,Interrupt request status for channel 0" "Not requested,Requested" line.long 0x08 "HRS,Management Page Hardware Request Status Register" bitfld.long 0x08 31. " HRS[31] ,Hardware request status for channel 31" "Not requested,Requested" bitfld.long 0x08 30. " [30] ,Hardware request status for channel 30" "Not requested,Requested" bitfld.long 0x08 29. " [29] ,Hardware request status for channel 29" "Not requested,Requested" bitfld.long 0x08 28. " [28] ,Hardware request status for channel 28" "Not requested,Requested" newline bitfld.long 0x08 27. " [27] ,Hardware request status for channel 27" "Not requested,Requested" bitfld.long 0x08 26. " [26] ,Hardware request status for channel 26" "Not requested,Requested" bitfld.long 0x08 25. " [25] ,Hardware request status for channel 25" "Not requested,Requested" bitfld.long 0x08 24. " [24] ,Hardware request status for channel 24" "Not requested,Requested" newline bitfld.long 0x08 23. " [23] ,Hardware request status for channel 23" "Not requested,Requested" bitfld.long 0x08 22. " [22] ,Hardware request status for channel 22" "Not requested,Requested" bitfld.long 0x08 21. " [21] ,Hardware request status for channel 21" "Not requested,Requested" bitfld.long 0x08 20. " [20] ,Hardware request status for channel 20" "Not requested,Requested" newline bitfld.long 0x08 19. " [19] ,Hardware request status for channel 19" "Not requested,Requested" bitfld.long 0x08 18. " [18] ,Hardware request status for channel 18" "Not requested,Requested" bitfld.long 0x08 17. " [17] ,Hardware request status for channel 17" "Not requested,Requested" bitfld.long 0x08 16. " [16] ,Hardware request status for channel 16" "Not requested,Requested" newline bitfld.long 0x08 15. " [15] ,Hardware request status for channel 15" "Not requested,Requested" bitfld.long 0x08 14. " [14] ,Hardware request status for channel 14" "Not requested,Requested" bitfld.long 0x08 13. " [13] ,Hardware request status for channel 13" "Not requested,Requested" bitfld.long 0x08 12. " [12] ,Hardware request status for channel 12" "Not requested,Requested" newline bitfld.long 0x08 11. " [11] ,Hardware request status for channel 11" "Not requested,Requested" bitfld.long 0x08 10. " [10] ,Hardware request status for channel 10" "Not requested,Requested" bitfld.long 0x08 9. " [9] ,Hardware request status for channel 9" "Not requested,Requested" bitfld.long 0x08 8. " [8] ,Hardware request status for channel 8" "Not requested,Requested" newline bitfld.long 0x08 7. " [7] ,Hardware request status for channel 7" "Not requested,Requested" bitfld.long 0x08 6. " [6] ,Hardware request status for channel 6" "Not requested,Requested" bitfld.long 0x08 5. " [5] ,Hardware request status for channel 5" "Not requested,Requested" bitfld.long 0x08 4. " [4] ,Hardware request status for channel 4" "Not requested,Requested" newline bitfld.long 0x08 3. " [3] ,Hardware request status for channel 3" "Not requested,Requested" bitfld.long 0x08 2. " [2] ,Hardware request status for channel 2" "Not requested,Requested" bitfld.long 0x08 1. " [1] ,Hardware request status for channel 1" "Not requested,Requested" bitfld.long 0x08 0. " [0] ,Hardware request status for channel 0" "Not requested,Requested" newline group.long 0x100++0x03 line.long 0x00 "CH0_GRPRI,Channel 0 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x104++0x03 line.long 0x00 "CH1_GRPRI,Channel 1 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x108++0x03 line.long 0x00 "CH2_GRPRI,Channel 2 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x10C++0x03 line.long 0x00 "CH3_GRPRI,Channel 3 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x110++0x03 line.long 0x00 "CH4_GRPRI,Channel 4 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x114++0x03 line.long 0x00 "CH5_GRPRI,Channel 5 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x118++0x03 line.long 0x00 "CH6_GRPRI,Channel 6 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x11C++0x03 line.long 0x00 "CH7_GRPRI,Channel 7 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x120++0x03 line.long 0x00 "CH8_GRPRI,Channel 8 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x124++0x03 line.long 0x00 "CH9_GRPRI,Channel 9 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x128++0x03 line.long 0x00 "CH10_GRPRI,Channel 10 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x12C++0x03 line.long 0x00 "CH11_GRPRI,Channel 11 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x130++0x03 line.long 0x00 "CH12_GRPRI,Channel 12 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x134++0x03 line.long 0x00 "CH13_GRPRI,Channel 13 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x138++0x03 line.long 0x00 "CH14_GRPRI,Channel 14 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x13C++0x03 line.long 0x00 "CH15_GRPRI,Channel 15 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x140++0x03 line.long 0x00 "CH16_GRPRI,Channel 16 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x144++0x03 line.long 0x00 "CH17_GRPRI,Channel 17 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x148++0x03 line.long 0x00 "CH18_GRPRI,Channel 18 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x14C++0x03 line.long 0x00 "CH19_GRPRI,Channel 19 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x150++0x03 line.long 0x00 "CH20_GRPRI,Channel 20 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x154++0x03 line.long 0x00 "CH21_GRPRI,Channel 21 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x158++0x03 line.long 0x00 "CH22_GRPRI,Channel 22 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 22" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x15C++0x03 line.long 0x00 "CH23_GRPRI,Channel 23 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 23" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x160++0x03 line.long 0x00 "CH24_GRPRI,Channel 24 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x164++0x03 line.long 0x00 "CH25_GRPRI,Channel 25 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 25" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x168++0x03 line.long 0x00 "CH26_GRPRI,Channel 26 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 26" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x16C++0x03 line.long 0x00 "CH27_GRPRI,Channel 27 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x170++0x03 line.long 0x00 "CH28_GRPRI,Channel 28 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 28" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x174++0x03 line.long 0x00 "CH29_GRPRI,Channel 29 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 29" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x178++0x03 line.long 0x00 "CH30_GRPRI,Channel 30 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 30" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x17C++0x03 line.long 0x00 "CH31_GRPRI,Channel 31 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree.open "TCD (Transfer Control Descriptor)" tree "Channel 0" base ad:0x5A200000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5A200000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5A200000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5A200000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 1" base ad:0x5A210000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5A210000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5A210000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5A210000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 2" base ad:0x5A220000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5A220000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5A220000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5A220000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 3" base ad:0x5A230000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5A230000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5A230000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5A230000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 4" base ad:0x5A240000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5A240000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5A240000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5A240000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 5" base ad:0x5A250000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5A250000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5A250000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5A250000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 6" base ad:0x5A260000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5A260000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5A260000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5A260000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 7" base ad:0x5A270000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5A270000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5A270000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5A270000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 8" base ad:0x5A280000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5A280000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5A280000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5A280000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 9" base ad:0x5A290000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5A290000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5A290000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5A290000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 10" base ad:0x5A2A0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5A2A0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5A2A0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5A2A0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 11" base ad:0x5A2B0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5A2B0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5A2B0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5A2B0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 12" base ad:0x5A2C0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5A2C0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5A2C0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5A2C0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 13" base ad:0x5A2D0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5A2D0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5A2D0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5A2D0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 14" base ad:0x5A2E0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5A2E0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5A2E0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5A2E0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 15" base ad:0x5A2F0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5A2F0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5A2F0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5A2F0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 16" base ad:0x5A300000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5A300000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5A300000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5A300000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 17" base ad:0x5A310000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5A310000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5A310000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5A310000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 18" base ad:0x5A320000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5A320000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5A320000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5A320000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 19" base ad:0x5A330000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5A330000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5A330000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5A330000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 20" base ad:0x5A340000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5A340000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5A340000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5A340000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 21" base ad:0x5A350000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5A350000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5A350000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5A350000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 22" base ad:0x5A360000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5A360000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5A360000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5A360000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 23" base ad:0x5A370000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5A370000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5A370000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5A370000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 24" base ad:0x5A380000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5A380000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5A380000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5A380000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 25" base ad:0x5A390000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5A390000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5A390000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5A390000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 26" base ad:0x5A3A0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5A3A0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5A3A0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5A3A0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 27" base ad:0x5A3B0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5A3B0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5A3B0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5A3B0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 28" base ad:0x5A3C0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5A3C0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5A3C0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5A3C0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 29" base ad:0x5A3D0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5A3D0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5A3D0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5A3D0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 30" base ad:0x5A3E0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5A3E0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5A3E0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5A3E0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 31" base ad:0x5A3F0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5A3F0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5A3F0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5A3F0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree.end tree.end tree.open "eDMA3" tree "MP (Management Page)" base ad:0x5A9F0000 width 12. group.long 0x00++0x03 line.long 0x00 "CSR,Management Page Control Register" rbitfld.long 0x00 31. " ACTIVE ,DMA active status" "Idle,Executing" rbitfld.long 0x00 24.--28. " ACTIVE_ID ,Active channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 9. " CX ,Cancel transfer" "Not canceled,Canceled" bitfld.long 0x00 8. " ECX ,Cancel transfer with error" "Not canceled,Canceled" newline bitfld.long 0x00 7. " GMRC ,Global master ID replication control" "Disabled,Enabled" bitfld.long 0x00 6. " GCLC ,Global channel linking control" "Disabled,Enabled" bitfld.long 0x00 5. " HALT ,Halt DMA operations" "Not halted,Halted" bitfld.long 0x00 4. " HAE ,Halt after error" "Not halted,Halted" newline bitfld.long 0x00 2. " ERCA ,Channel arbitration select" "Fixed priority,Round robin" bitfld.long 0x00 1. " EDBG ,DMA operation in debug mode" "Continue,Stall" rgroup.long 0x04++0x0B line.long 0x00 "ES,Management Page Error Status Register" bitfld.long 0x00 31. " VLD ,Valid" "No error,Error" bitfld.long 0x00 24.--28. " ERRCHN ,Error channel number or canceled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 9. " UCE ,Uncorrectable TCD error during channel execution" "No error,Error" bitfld.long 0x00 8. " ECX ,Transfer canceled" "Not canceled,Canceled" newline bitfld.long 0x00 7. " SAE ,Source address error" "No error,Error" bitfld.long 0x00 6. " SOE ,Source offset error" "No error,Error" bitfld.long 0x00 5. " DAE ,Destination address error" "No error,Error" bitfld.long 0x00 4. " DOE ,Destination offset error" "No error,Error" newline bitfld.long 0x00 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" bitfld.long 0x00 2. " SGE ,Scatter/gather configuration error" "No error,Error" bitfld.long 0x00 1. " SBE ,Source bus error" "No error,Error" bitfld.long 0x00 0. " DBE ,Destination bus error" "No error,Error" line.long 0x04 "INT,Management Page Interrupt Request Status Register" bitfld.long 0x04 31. " INT[31] ,Interrupt request status for channel 31" "Not requested,Requested" bitfld.long 0x04 30. " [30] ,Interrupt request status for channel 30" "Not requested,Requested" bitfld.long 0x04 29. " [29] ,Interrupt request status for channel 29" "Not requested,Requested" bitfld.long 0x04 28. " [28] ,Interrupt request status for channel 28" "Not requested,Requested" newline bitfld.long 0x04 27. " [27] ,Interrupt request status for channel 27" "Not requested,Requested" bitfld.long 0x04 26. " [26] ,Interrupt request status for channel 26" "Not requested,Requested" bitfld.long 0x04 25. " [25] ,Interrupt request status for channel 25" "Not requested,Requested" bitfld.long 0x04 24. " [24] ,Interrupt request status for channel 24" "Not requested,Requested" newline bitfld.long 0x04 23. " [23] ,Interrupt request status for channel 23" "Not requested,Requested" bitfld.long 0x04 22. " [22] ,Interrupt request status for channel 22" "Not requested,Requested" bitfld.long 0x04 21. " [21] ,Interrupt request status for channel 21" "Not requested,Requested" bitfld.long 0x04 20. " [20] ,Interrupt request status for channel 20" "Not requested,Requested" newline bitfld.long 0x04 19. " [19] ,Interrupt request status for channel 19" "Not requested,Requested" bitfld.long 0x04 18. " [18] ,Interrupt request status for channel 18" "Not requested,Requested" bitfld.long 0x04 17. " [17] ,Interrupt request status for channel 17" "Not requested,Requested" bitfld.long 0x04 16. " [16] ,Interrupt request status for channel 16" "Not requested,Requested" newline bitfld.long 0x04 15. " [15] ,Interrupt request status for channel 15" "Not requested,Requested" bitfld.long 0x04 14. " [14] ,Interrupt request status for channel 14" "Not requested,Requested" bitfld.long 0x04 13. " [13] ,Interrupt request status for channel 13" "Not requested,Requested" bitfld.long 0x04 12. " [12] ,Interrupt request status for channel 12" "Not requested,Requested" newline bitfld.long 0x04 11. " [11] ,Interrupt request status for channel 11" "Not requested,Requested" bitfld.long 0x04 10. " [10] ,Interrupt request status for channel 10" "Not requested,Requested" bitfld.long 0x04 9. " [9] ,Interrupt request status for channel 9" "Not requested,Requested" bitfld.long 0x04 8. " [8] ,Interrupt request status for channel 8" "Not requested,Requested" newline bitfld.long 0x04 7. " [7] ,Interrupt request status for channel 7" "Not requested,Requested" bitfld.long 0x04 6. " [6] ,Interrupt request status for channel 6" "Not requested,Requested" bitfld.long 0x04 5. " [5] ,Interrupt request status for channel 5" "Not requested,Requested" bitfld.long 0x04 4. " [4] ,Interrupt request status for channel 4" "Not requested,Requested" newline bitfld.long 0x04 3. " [3] ,Interrupt request status for channel 3" "Not requested,Requested" bitfld.long 0x04 2. " [2] ,Interrupt request status for channel 2" "Not requested,Requested" bitfld.long 0x04 1. " [1] ,Interrupt request status for channel 1" "Not requested,Requested" bitfld.long 0x04 0. " [0] ,Interrupt request status for channel 0" "Not requested,Requested" line.long 0x08 "HRS,Management Page Hardware Request Status Register" bitfld.long 0x08 31. " HRS[31] ,Hardware request status for channel 31" "Not requested,Requested" bitfld.long 0x08 30. " [30] ,Hardware request status for channel 30" "Not requested,Requested" bitfld.long 0x08 29. " [29] ,Hardware request status for channel 29" "Not requested,Requested" bitfld.long 0x08 28. " [28] ,Hardware request status for channel 28" "Not requested,Requested" newline bitfld.long 0x08 27. " [27] ,Hardware request status for channel 27" "Not requested,Requested" bitfld.long 0x08 26. " [26] ,Hardware request status for channel 26" "Not requested,Requested" bitfld.long 0x08 25. " [25] ,Hardware request status for channel 25" "Not requested,Requested" bitfld.long 0x08 24. " [24] ,Hardware request status for channel 24" "Not requested,Requested" newline bitfld.long 0x08 23. " [23] ,Hardware request status for channel 23" "Not requested,Requested" bitfld.long 0x08 22. " [22] ,Hardware request status for channel 22" "Not requested,Requested" bitfld.long 0x08 21. " [21] ,Hardware request status for channel 21" "Not requested,Requested" bitfld.long 0x08 20. " [20] ,Hardware request status for channel 20" "Not requested,Requested" newline bitfld.long 0x08 19. " [19] ,Hardware request status for channel 19" "Not requested,Requested" bitfld.long 0x08 18. " [18] ,Hardware request status for channel 18" "Not requested,Requested" bitfld.long 0x08 17. " [17] ,Hardware request status for channel 17" "Not requested,Requested" bitfld.long 0x08 16. " [16] ,Hardware request status for channel 16" "Not requested,Requested" newline bitfld.long 0x08 15. " [15] ,Hardware request status for channel 15" "Not requested,Requested" bitfld.long 0x08 14. " [14] ,Hardware request status for channel 14" "Not requested,Requested" bitfld.long 0x08 13. " [13] ,Hardware request status for channel 13" "Not requested,Requested" bitfld.long 0x08 12. " [12] ,Hardware request status for channel 12" "Not requested,Requested" newline bitfld.long 0x08 11. " [11] ,Hardware request status for channel 11" "Not requested,Requested" bitfld.long 0x08 10. " [10] ,Hardware request status for channel 10" "Not requested,Requested" bitfld.long 0x08 9. " [9] ,Hardware request status for channel 9" "Not requested,Requested" bitfld.long 0x08 8. " [8] ,Hardware request status for channel 8" "Not requested,Requested" newline bitfld.long 0x08 7. " [7] ,Hardware request status for channel 7" "Not requested,Requested" bitfld.long 0x08 6. " [6] ,Hardware request status for channel 6" "Not requested,Requested" bitfld.long 0x08 5. " [5] ,Hardware request status for channel 5" "Not requested,Requested" bitfld.long 0x08 4. " [4] ,Hardware request status for channel 4" "Not requested,Requested" newline bitfld.long 0x08 3. " [3] ,Hardware request status for channel 3" "Not requested,Requested" bitfld.long 0x08 2. " [2] ,Hardware request status for channel 2" "Not requested,Requested" bitfld.long 0x08 1. " [1] ,Hardware request status for channel 1" "Not requested,Requested" bitfld.long 0x08 0. " [0] ,Hardware request status for channel 0" "Not requested,Requested" newline group.long 0x100++0x03 line.long 0x00 "CH0_GRPRI,Channel 0 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x104++0x03 line.long 0x00 "CH1_GRPRI,Channel 1 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x108++0x03 line.long 0x00 "CH2_GRPRI,Channel 2 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x10C++0x03 line.long 0x00 "CH3_GRPRI,Channel 3 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x110++0x03 line.long 0x00 "CH4_GRPRI,Channel 4 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x114++0x03 line.long 0x00 "CH5_GRPRI,Channel 5 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x118++0x03 line.long 0x00 "CH6_GRPRI,Channel 6 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x11C++0x03 line.long 0x00 "CH7_GRPRI,Channel 7 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x120++0x03 line.long 0x00 "CH8_GRPRI,Channel 8 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x124++0x03 line.long 0x00 "CH9_GRPRI,Channel 9 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x128++0x03 line.long 0x00 "CH10_GRPRI,Channel 10 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x12C++0x03 line.long 0x00 "CH11_GRPRI,Channel 11 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x130++0x03 line.long 0x00 "CH12_GRPRI,Channel 12 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x134++0x03 line.long 0x00 "CH13_GRPRI,Channel 13 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x138++0x03 line.long 0x00 "CH14_GRPRI,Channel 14 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x13C++0x03 line.long 0x00 "CH15_GRPRI,Channel 15 Arbitration Group" bitfld.long 0x00 0.--4. " GRPRI ,Arbitration group for channel 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree.open "TCD (Transfer Control Descriptor)" tree "Channel 0" base ad:0x5AA00000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5AA00000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5AA00000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5AA00000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 1" base ad:0x5AA10000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5AA10000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5AA10000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5AA10000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 2" base ad:0x5AA20000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5AA20000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5AA20000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5AA20000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 3" base ad:0x5AA30000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5AA30000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5AA30000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5AA30000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 4" base ad:0x5AA40000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5AA40000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5AA40000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5AA40000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 5" base ad:0x5AA50000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5AA50000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5AA50000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5AA50000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 6" base ad:0x5AA60000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5AA60000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5AA60000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5AA60000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 7" base ad:0x5AA70000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5AA70000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5AA70000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5AA70000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 8" base ad:0x5AA80000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5AA80000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5AA80000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5AA80000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 9" base ad:0x5AA90000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5AA90000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5AA90000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5AA90000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 10" base ad:0x5AAA0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5AAA0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5AAA0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5AAA0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 11" base ad:0x5AAB0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5AAB0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5AAB0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5AAB0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 12" base ad:0x5AAC0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5AAC0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5AAC0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5AAC0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 13" base ad:0x5AAD0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5AAD0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5AAD0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5AAD0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 14" base ad:0x5AAE0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5AAE0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5AAE0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5AAE0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree "Channel 15" base ad:0x5AAF0000 width 17. group.long 0x00++0x13 line.long 0x00 "CSR,Channel Control And Status" rbitfld.long 0x00 31. " ACTIVE ,Channel active" "Idle,Executing" eventfld.long 0x00 30. " DONE ,Channel done" "Not completed,Completed" bitfld.long 0x00 3. " EBW ,Enable buffered writes" "Disabled,Enabled" bitfld.long 0x00 2. " EEI ,Enable error interrupt" "Disabled,Enabled" newline bitfld.long 0x00 1. " EARQ ,Enable asynchronous DMA request in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " ERQ ,Enable DMA request" "Disabled,Enabled" line.long 0x04 "ES,Channel Error Status" eventfld.long 0x04 31. " ERR ,Error in channel" "No error,Error" rbitfld.long 0x04 7. " SAE ,Source address error" "No error,Error" rbitfld.long 0x04 6. " SOE ,Source offset error" "No error,Error" rbitfld.long 0x04 5. " DAE ,Destination address error" "No error,Error" newline rbitfld.long 0x04 4. " DOE ,Destination offset error" "No error,Error" rbitfld.long 0x04 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" rbitfld.long 0x04 2. " SGE ,Scatter/gather configuration error" "No error,Error" rbitfld.long 0x04 1. " SBE ,Source bus error" "No error,Error" newline rbitfld.long 0x04 0. " DBE ,Destination bus error" "No error,Error" line.long 0x08 "INT,Channel Interrupt Status" eventfld.long 0x08 0. " INT ,Interrupt request" "Not requested,Requested" line.long 0x0C "SBR,Channel System Bus Register" bitfld.long 0x0C 17.--22. " ATTR ,Attribute output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x0C 15. " PAL ,Privileged access level" "User,Privileged" rbitfld.long 0x0C 0.--4. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "PRI,Channel Priority Register" bitfld.long 0x10 31. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.long 0x10 30. " DPA ,Disable preempt ability" "No,Yes" bitfld.long 0x10 0.--2. " APL ,Arbitration priority level" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" group.word 0x24++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset" line.word 0x02 "ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,16-byte,32-byte,64-byte,?..." if ((per.l(ad:0x5AAF0000+0x28)&0xC0000000)==0x00) group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Transfer Size without Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Number of bytes to transfer per service request" else group.long 0x28++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Minor loop offset" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Number of bytes to transfer per service request" endif group.long 0x2C++0x07 line.long 0x00 "SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address Register" line.long 0x04 "DADDR,TCD Destination Address" group.word 0x34++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if ((per.w(ad:0x5AAF0000+0x36)&0x8000)==0x00) group.word 0x36++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word 0x36++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Minor loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long 0x38++0x03 line.long 0x00 "DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address Register" group.word 0x3C++0x01 line.word 0x00 "CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Major loop link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " ESDA ,Enable store destination address" "Disabled,Enabled" bitfld.word 0x00 6. " EEOP ,Enable end-of-packet processing" "Disabled,Enabled" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if ((per.w(ad:0x5AAF0000+0x3E)&0x8000)==0x00) group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word 0x3E++0x01 line.word 0x00 "BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif width 0x0B tree.end tree.end tree.end tree.end tree "ESAI (Enhanced Serial Audio Interface)" base ad:0x59010000 width 7. wgroup.long 0x00++0x03 line.long 0x00 "ETDR,ESAI Transmit Data Register" newline hgroup.long 0x04++0x03 hide.long 0x00 "ERDR,ESAI Receive Data Register" in newline group.long 0x08++0x03 line.long 0x00 "ECR,ESAI Control Register" bitfld.long 0x00 19. " ETI ,EXTAL transmitter in" "HCKT normal,EXTAL muxed into HCKT" bitfld.long 0x00 18. " ETO ,EXTAL transmitter out" "HCKT normal,EXTAL driven onto HCKT" bitfld.long 0x00 17. " ERI ,EXTAL receiver in" "HCKR normal,EXTAL muxed into HCKR" newline bitfld.long 0x00 16. " ERO ,EXTAL receiver out" "HCKR normal,EXTAL driven onto HCKR" bitfld.long 0x00 1. " ERST ,ESAI reset" "No reset,Reset" bitfld.long 0x00 0. " ESAIEN ,ESAI enable" "Disabled,Enabled" rgroup.long 0x0C++0x03 line.long 0x00 "ESR,ESAI Status Register" bitfld.long 0x00 10. " TINIT ,Transmit initialization" "Finished,Not finished" bitfld.long 0x00 9. " RFF ,Receive FIFO full" "< FIFO watermark,>= FIFO watermark" bitfld.long 0x00 8. " TFE ,Transmit FIFO empty" "< FIFO watermark,>= FIFO watermark" bitfld.long 0x00 7. " TLS ,Transmit last slot" "Not highest priority,Highest priority" newline bitfld.long 0x00 6. " TDE ,Transmit data exception" "Not highest priority,Highest priority" bitfld.long 0x00 5. " TED ,Transmit even data" "Not highest priority,Highest priority" bitfld.long 0x00 4. " TD ,Transmit data" "Not highest priority,Highest priority" bitfld.long 0x00 3. " RLS ,Receive last slot" "Not highest priority,Highest priority" newline bitfld.long 0x00 2. " RDE ,Receive data exception" "Not highest priority,Highest priority" bitfld.long 0x00 1. " RED ,Receive even data" "Not highest priority,Highest priority" bitfld.long 0x00 0. " RD ,Receive data" "Not highest priority,Highest priority" if (((per.l(ad:0x59010000+0x10))&0x01)==0x01) group.long 0x10++0x03 line.long 0x00 "TFCR,Transmit FIFO Configuration Register" bitfld.long 0x00 19. " TIEN ,Transmitter initialization enable" "Disabled,Enabled" bitfld.long 0x00 16.--18. " TWA ,Transmit word alignment" "MSB=31/7-0 ignored,MSB=27/3-0 ignored,MSB=23,MSB=19/Bottom 4 zeroed,MSB=15/Bottom 8 zeroed,MSB=11/Bottom 12 zeroed,MSB=7/Bottom 16 zeroed,MSB=3/Bottom 20 zeroed" hexmask.long.byte 0x00 8.--15. 1. " TFWM ,Transmit FIFO watermark" rbitfld.long 0x00 7. " TE5 ,Transmitter #5 FIFO enable" "Disabled,Enabled" newline rbitfld.long 0x00 6. " TE4 ,Transmitter #4 FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 5. " TE3 ,Transmitter #3 FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 4. " TE2 ,Transmitter #2 FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 3. " TE1 ,Transmitter #1 FIFO enable" "Disabled,Enabled" newline rbitfld.long 0x00 2. " TE0 ,Transmitter #0 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 1. " TFR ,Transmit FIFO reset" "No reset,Reset" bitfld.long 0x00 0. " TFE ,Transmit FIFO enable" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "TFCR,Transmit FIFO Configuration Register" bitfld.long 0x00 19. " TIEN ,Transmitter initialization enable" "Disabled,Enabled" bitfld.long 0x00 16.--18. " TWA ,Transmit word alignment" "MSB=31/7-0 ignored,MSB=27/3-0 ignored,MSB=23,MSB=19/Bottom 4 zeroed,MSB=15/Bottom 8 zeroed,MSB=11/Bottom 12 zeroed,MSB=7/Bottom 16 zeroed,MSB=3/Bottom 20 zeroed" hexmask.long.byte 0x00 8.--15. 1. " TFWM ,Transmit FIFO watermark" bitfld.long 0x00 7. " TE5 ,Transmitter #5 FIFO enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " TE4 ,Transmitter #4 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 5. " TE3 ,Transmitter #3 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 4. " TE2 ,Transmitter #2 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 3. " TE1 ,Transmitter #1 FIFO enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " TE0 ,Transmitter #0 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 1. " TFR ,Transmit FIFO reset" "No reset,Reset" bitfld.long 0x00 0. " TFE ,Transmit FIFO enable" "Disabled,Enabled" endif rgroup.long 0x14++0x03 line.long 0x00 "TFSR,Transmit FIFO Status Register" bitfld.long 0x00 12.--14. " NTFO ,Next transmitter FIFO out" "#0,#1,#2,#3,#4,#5,?..." bitfld.long 0x00 8.--10. " NTFI ,Next transmitter FIFO in" "#0,#1,#2,#3,#4,#5,?..." hexmask.long.byte 0x00 0.--7. 1. " TFCNT ,Transmit FIFO counter" if (((per.l(ad:0x59010000+0x18))&0x01)==0x01) group.long 0x18++0x03 line.long 0x00 "RFCR,Receive FIFO Configuration Register" bitfld.long 0x00 19. " REXT ,Receive extension" "Zero,Sign" bitfld.long 0x00 16.--18. " RWA ,Receive word alignment" "MSB=31/7-0 zeroed,MSB=27/3-0 zeroed,MSB=23,MSB=19/3-0 ignored,MSB=15/7-0 ignored,MSB=11/11-0 ignored,MSB=7/15-0 ignored,MSB=3/19-0 ignored" hexmask.long.byte 0x00 8.--15. 1. " RFWM ,Receive FIFO watermark" rbitfld.long 0x00 5. " RE[3] ,Receiver #3 FIFO enable" "Disabled,Enabled" newline rbitfld.long 0x00 4. " [2] ,Receiver #2 FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 3. " [1] ,Receiver #1 FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 2. " [0] ,Receiver #0 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 1. " RFR ,Receive FIFO reset" "No reset,Reset" newline bitfld.long 0x00 0. " RFE ,Receive FIFO enable" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "RFCR,Receive FIFO Configuration Register" bitfld.long 0x00 19. " REXT ,Receive extension" "Zero,Sign" bitfld.long 0x00 16.--18. " RWA ,Receive word alignment" "MSB=31/7-0 ignored,MSB=27/3-0 ignored,MSB=23,MSB=19/Bottom 4 zeroed,MSB=15/Bottom 8 zeroed,MSB=11/Bottom 12 zeroed,MSB=7/Bottom 16 zeroed,MSB=3/Bottom 20 zeroed" hexmask.long.byte 0x00 8.--15. 1. " RFWM ,Receive FIFO watermark" bitfld.long 0x00 5. " RE[3] ,Receiver #3 FIFO enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " [2] ,Receiver #2 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 3. " [1] ,Receiver #1 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 2. " [0] ,Receiver #0 FIFO enable" "Disabled,Enabled" bitfld.long 0x00 1. " RFR ,Receive FIFO reset" "No reset,Reset" newline bitfld.long 0x00 0. " RFE ,Receive FIFO enable" "Disabled,Enabled" endif rgroup.long 0x1C++0x03 line.long 0x00 "RFSR,Receive FIFO Status Register" bitfld.long 0x00 12.--13. " NRFI ,Next receiver FIFO in" "#0,#1,#2,#3" bitfld.long 0x00 8.--9. " NRFO ,Next receiver FIFO out" "#0,#1,#2,#3" hexmask.long.byte 0x00 0.--7. 1. " RFCNT ,Receive FIFO counter" wgroup.long 0x80++0x03 line.long 0x00 "TX0,ESAI Transmit Data Register 0" hexmask.long.tbyte 0x00 0.--23. 1. " TX0 ,Stores the data to be transmitted" wgroup.long 0x84++0x03 line.long 0x00 "TX1,ESAI Transmit Data Register 1" hexmask.long.tbyte 0x00 0.--23. 1. " TX1 ,Stores the data to be transmitted" wgroup.long 0x88++0x03 line.long 0x00 "TX2,ESAI Transmit Data Register 2" hexmask.long.tbyte 0x00 0.--23. 1. " TX2 ,Stores the data to be transmitted" wgroup.long 0x8C++0x03 line.long 0x00 "TX3,ESAI Transmit Data Register 3" hexmask.long.tbyte 0x00 0.--23. 1. " TX3 ,Stores the data to be transmitted" wgroup.long 0x90++0x03 line.long 0x00 "TX4,ESAI Transmit Data Register 4" hexmask.long.tbyte 0x00 0.--23. 1. " TX4 ,Stores the data to be transmitted" wgroup.long 0x94++0x03 line.long 0x00 "TX5,ESAI Transmit Data Register 5" hexmask.long.tbyte 0x00 0.--23. 1. " TX5 ,Stores the data to be transmitted" wgroup.long 0x98++0x03 line.long 0x00 "TSR,ESAI Transmit Slot Register" hexmask.long.tbyte 0x00 0.--23. 1. " TSR ,Transmit slot register" rgroup.long 0xA0++0x03 line.long 0x00 "RX0,ESAI Receive Data Register 0" hexmask.long.tbyte 0x00 0.--23. 1. " RX0 ,Data from the receive shift register" rgroup.long 0xA4++0x03 line.long 0x00 "RX1,ESAI Receive Data Register 1" hexmask.long.tbyte 0x00 0.--23. 1. " RX1 ,Data from the receive shift register" rgroup.long 0xA8++0x03 line.long 0x00 "RX2,ESAI Receive Data Register 2" hexmask.long.tbyte 0x00 0.--23. 1. " RX2 ,Data from the receive shift register" rgroup.long 0xAC++0x03 line.long 0x00 "RX3,ESAI Receive Data Register 3" hexmask.long.tbyte 0x00 0.--23. 1. " RX3 ,Data from the receive shift register" newline rgroup.long 0xCC++0x03 line.long 0x00 "SAISR,Serial Audio Interface Status Register" bitfld.long 0x00 17. " TODFE ,SAISR transmit odd-data register empty" "Not empty,Empty" bitfld.long 0x00 16. " TEDE ,SAISR transmit even-data register empty" "Not empty,Empty" bitfld.long 0x00 15. " TDE ,SAISR transmit data register empty" "Not empty,Empty" bitfld.long 0x00 14. " TUE ,SAISR transmit underrun error flag" "No error,Error" newline bitfld.long 0x00 13. " TFS ,SAISR transmit frame sync flag" "Not occurred,Occurred" bitfld.long 0x00 10. " RODF ,SAISR receive odd-data register full" "Not full,Full" bitfld.long 0x00 9. " REDF ,SAISR receive even-data register full" "Not full,Full" bitfld.long 0x00 8. " RDF ,SAISR receive data register full" "Not full,Full" newline bitfld.long 0x00 7. " ROE ,SAISR receive overrun error flag" "No error,Error" bitfld.long 0x00 6. " RFS ,SAISR receive frame sync flag" "Not occurred,Occurred" bitfld.long 0x00 2. " IF2 ,SAISR serial input flag 2" "Not occurred,Occurred" bitfld.long 0x00 1. " IF1 ,SAISR serial input flag 1" "Not occurred,Occurred" newline bitfld.long 0x00 0. " IF0 ,SAISR serial input flag 0" "Not occurred,Occurred" group.long 0xD0++0x03 line.long 0x00 "SAICR,Serial Audio Interface Control Register" bitfld.long 0x00 8. " ALC ,SAICR alignment control" "23 bit,15 bit" bitfld.long 0x00 7. " TEBE ,SAICR transmit external buffer enable" "Disabled,Enabled" bitfld.long 0x00 6. " SYN ,SAICR synchronous mode selection" "Asynchronous,Synchronous" bitfld.long 0x00 2. " OF[2] ,SAICR serial output flag 2" "Not occurred,Occurred" newline bitfld.long 0x00 1. " [1] ,SAICR serial output flag 1" "Not occurred,Occurred" bitfld.long 0x00 0. " [0] ,SAICR serial output flag 0" "Not occurred,Occurred" if ((per.l(ad:0x59010000+0xD8)&0x3E00)==0x00) group.long 0xD4++0x03 line.long 0x00 "TCR,Transmit Control Register" bitfld.long 0x00 23. " TLIE ,Transmit last slot interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " TIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " TEDIE ,Transmit even slot data interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " TEIE ,Transmit exception interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TPR ,Transmit section personal reset" "No effect,Reset" bitfld.long 0x00 17. " PADC ,Transmit zero padding control" "Disabled,Enabled" bitfld.long 0x00 16. " TFSR ,Transmit frame sync relative timing" "First bit of data,Last bit of prev data" bitfld.long 0x00 15. " TFSL ,Transmit frame sync length" "Word-length,1-bit clock period" newline bitfld.long 0x00 10.--14. " TSWS ,Transmit slot and word length select" "Slot-8/Word-8,Slot-12/Word-12,Slot-16/Word-16,Slot-20/Word-20,Slot-12/Word-8,Slot-16/Word-12,Slot-20/Word-16,Slot-24/Word-20,Slot-16/Word-8,Slot-20/Word-12,Slot-24/Word-16,,Slot-20/Word-8,Slot-24/Word-12,,Slot-32/Word-20,Slot-24/Word-8,,Slot-32/Word-16,,,Slot-32/Word-12,,,Slot-32/Word-8,,,,,,Slot-24/Word-24,Slot-32/Word-24" bitfld.long 0x00 8.--9. " TMOD ,Transmit network mode control" "Normal,On-demand,?..." bitfld.long 0x00 7. " TWA ,Transmit word alignment control" "Left,Right" bitfld.long 0x00 6. " TSHFD ,Transmit shift direction" "MSB first,LSB first" newline bitfld.long 0x00 5. " TE[5] ,ESAI transmit 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,ESAI transmit 4 enable" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,ESAI transmit 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,ESAI transmit 2 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,ESAI transmit 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,ESAI transmit 0 enable" "Disabled,Enabled" elif ((per.l(ad:0x59010000+0xD8)&0x3E00)==0x1800) group.long 0xD4++0x03 line.long 0x00 "TCR,Transmit Control Register" bitfld.long 0x00 23. " TLIE ,Transmit last slot interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " TIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " TEDIE ,Transmit even slot data interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " TEIE ,Transmit exception interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TPR ,Transmit section personal reset" "No effect,Reset" bitfld.long 0x00 17. " PADC ,Transmit zero padding control" "Disabled,Enabled" bitfld.long 0x00 16. " TFSR ,Transmit frame sync relative timing" "First bit of data,Last bit of prev data" bitfld.long 0x00 15. " TFSL ,Transmit frame sync length" "Word-length,1-bit clock period" newline bitfld.long 0x00 10.--14. " TSWS ,Transmit slot and word length select" "Slot-8/Word-8,Slot-12/Word-12,Slot-16/Word-16,Slot-20/Word-20,Slot-12/Word-8,Slot-16/Word-12,Slot-20/Word-16,Slot-24/Word-20,Slot-16/Word-8,Slot-20/Word-12,Slot-24/Word-16,,Slot-20/Word-8,Slot-24/Word-12,,Slot-32/Word-20,Slot-24/Word-8,,Slot-32/Word-16,,,Slot-32/Word-12,,,Slot-32/Word-8,,,,,,Slot-24/Word-24,Slot-32/Word-24" bitfld.long 0x00 8.--9. " TMOD ,Transmit network mode control" "Normal,Network,,AC97" bitfld.long 0x00 7. " TWA ,Transmit word alignment control" "Left,Right" bitfld.long 0x00 6. " TSHFD ,Transmit shift direction" "MSB first,LSB first" newline bitfld.long 0x00 5. " TE[5] ,ESAI transmit 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,ESAI transmit 4 enable" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,ESAI transmit 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,ESAI transmit 2 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,ESAI transmit 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,ESAI transmit 0 enable" "Disabled,Enabled" else group.long 0xD4++0x03 line.long 0x00 "TCR,Transmit Control Register" bitfld.long 0x00 23. " TLIE ,Transmit last slot interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " TIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " TEDIE ,Transmit even slot data interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " TEIE ,Transmit exception interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TPR ,Transmit section personal reset" "No effect,Reset" bitfld.long 0x00 17. " PADC ,Transmit zero padding control" "Disabled,Enabled" bitfld.long 0x00 16. " TFSR ,Transmit frame sync relative timing" "First bit of data,Last bit of prev data" bitfld.long 0x00 15. " TFSL ,Transmit frame sync length" "Word-length,1-bit clock period" newline bitfld.long 0x00 10.--14. " TSWS ,Transmit slot and word length select" "Slot-8/Word-8,Slot-12/Word-12,Slot-16/Word-16,Slot-20/Word-20,Slot-12/Word-8,Slot-16/Word-12,Slot-20/Word-16,Slot-24/Word-20,Slot-16/Word-8,Slot-20/Word-12,Slot-24/Word-16,,Slot-20/Word-8,Slot-24/Word-12,,Slot-32/Word-20,Slot-24/Word-8,,Slot-32/Word-16,,,Slot-32/Word-12,,,Slot-32/Word-8,,,,,,Slot-24/Word-24,Slot-32/Word-24" bitfld.long 0x00 8.--9. " TMOD ,Transmit network mode control" "Normal,Network,?..." bitfld.long 0x00 7. " TWA ,Transmit word alignment control" "Left,Right" bitfld.long 0x00 6. " TSHFD ,Transmit shift direction" "MSB first,LSB first" newline bitfld.long 0x00 5. " TE[5] ,ESAI transmit 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,ESAI transmit 4 enable" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,ESAI transmit 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,ESAI transmit 2 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,ESAI transmit 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,ESAI transmit 0 enable" "Disabled,Enabled" endif group.long 0xD8++0x03 line.long 0x00 "TCCR,Transmit Clock Control Register" bitfld.long 0x00 23. " THCKD ,High frequency clock direction (HCKR pin) (HCKT pin)" "Input,Output" bitfld.long 0x00 22. " TFSD ,Frame sync signal direction (FST pin)" "Input,Output" bitfld.long 0x00 21. " TCKD ,Transmitter Clock source direction (SCKT pin)" "External,Internal" bitfld.long 0x00 20. " THCKP ,Transmitter high frequency clock polarity" "Normal,Inverted" newline bitfld.long 0x00 19. " TFSP ,Transmitter frame sync polarity [clocked/latched]" "Rising/Falling,Falling/Rising" bitfld.long 0x00 18. " TCKP ,Transmitter clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" bitfld.long 0x00 14.--17. " TFP ,Tx high frequency clock divider control" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 9.--13. " TDC ,Frame rate divider control" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline bitfld.long 0x00 8. " TPSR ,Transmit prescaler range" "Div by 8,Bypassed" hexmask.long.byte 0x00 0.--7. 1. " TPM ,Transmit prescale modulus select" if ((per.l(ad:0x59010000+0xE0)&0x3E00)==0x00) group.long 0xDC++0x03 line.long 0x00 "RCR,Receive Control Register" bitfld.long 0x00 23. " RLIE ,Receive last slot interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " RIE ,Receive interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " REDIE ,Receive even slot data interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " REIE ,Receive exception interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " RPR ,Receiver section personal reset" "No effect,Reset" bitfld.long 0x00 16. " RFSR ,Receiver frame sync relative timing" "First bit of data,Last bit of prev data" bitfld.long 0x00 15. " RFSL ,Receiver frame sync length" "Word-length,1-bit clock period" bitfld.long 0x00 10.--14. " RSWS ,Receiver slot and word length select" "Slot-8/Word-8,Slot-12/Word-12,Slot-16/Word-16,Slot-20/Word-20,Slot-12/Word-8,Slot-16/Word-12,Slot-20/Word-16,Slot-24/Word-20,Slot-16/Word-8,Slot-20/Word-12,Slot-24/Word-16,,Slot-20/Word-8,Slot-24/Word-12,,Slot-32/Word-20,Slot-24/Word-8,,Slot-32/Word-16,,,Slot-32/Word-12,,,Slot-32/Word-8,,,,,,Slot-24/Word-24,Slot-32/Word-24" newline bitfld.long 0x00 8.--9. " RMOD ,Receiver network mode control" "Normal,On-demand,?..." bitfld.long 0x00 7. " RWA ,Receiver word alignment control" "Left,Right" bitfld.long 0x00 6. " RSHFD ,Receiver shift direction" "MSB first,LSB first" bitfld.long 0x00 3. " RE[3] ,ESAI receiver 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " [2] ,ESAI receiver 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,ESAI receiver 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,ESAI receiver 0 enable" "Disabled,Enabled" elif ((per.l(ad:0x59010000+0xE0)&0x3E00)==0x1800) group.long 0xDC++0x03 line.long 0x00 "RCR,Receive Control Register" bitfld.long 0x00 23. " RLIE ,Receive last slot interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " RIE ,Receive interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " REDIE ,Receive even slot data interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " REIE ,Receive exception interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " RPR ,Receiver section personal reset" "No effect,Reset" bitfld.long 0x00 16. " RFSR ,Receiver frame sync relative timing" "First bit of data,Last bit of prev data" bitfld.long 0x00 15. " RFSL ,Receiver frame sync length" "Word-length,1-bit clock period" bitfld.long 0x00 10.--14. " RSWS ,Receiver slot and word length select" "Slot-8/Word-8,Slot-12/Word-12,Slot-16/Word-16,Slot-20/Word-20,Slot-12/Word-8,Slot-16/Word-12,Slot-20/Word-16,Slot-24/Word-20,Slot-16/Word-8,Slot-20/Word-12,Slot-24/Word-16,,Slot-20/Word-8,Slot-24/Word-12,,Slot-32/Word-20,Slot-24/Word-8,,Slot-32/Word-16,,,Slot-32/Word-12,,,Slot-32/Word-8,,,,,,Slot-24/Word-24,Slot-32/Word-24" newline bitfld.long 0x00 8.--9. " RMOD ,Receiver network mode control" "Normal,Network,,AC97" bitfld.long 0x00 7. " RWA ,Receiver word alignment control" "Left,Right" bitfld.long 0x00 6. " RSHFD ,Receiver shift direction" "MSB first,LSB first" bitfld.long 0x00 3. " RE[3] ,ESAI receiver 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " [2] ,ESAI receiver 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,ESAI receiver 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,ESAI receiver 0 enable" "Disabled,Enabled" else group.long 0xDC++0x03 line.long 0x00 "RCR,Receive Control Register" bitfld.long 0x00 23. " RLIE ,Receive last slot interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " RIE ,Receive interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " REDIE ,Receive even slot data interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " REIE ,Receive exception interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " RPR ,Receiver section personal reset" "No effect,Reset" bitfld.long 0x00 16. " RFSR ,Receiver frame sync relative timing" "First bit of data,Last bit of prev data" bitfld.long 0x00 15. " RFSL ,Receiver frame sync length" "Word-length,1-bit clock period" bitfld.long 0x00 10.--14. " RSWS ,Receiver slot and word length select" "Slot-8/Word-8,Slot-12/Word-12,Slot-16/Word-16,Slot-20/Word-20,Slot-12/Word-8,Slot-16/Word-12,Slot-20/Word-16,Slot-24/Word-20,Slot-16/Word-8,Slot-20/Word-12,Slot-24/Word-16,,Slot-20/Word-8,Slot-24/Word-12,,Slot-32/Word-20,Slot-24/Word-8,,Slot-32/Word-16,,,Slot-32/Word-12,,,Slot-32/Word-8,,,,,,Slot-24/Word-24,Slot-32/Word-24" newline bitfld.long 0x00 8.--9. " RMOD ,Receiver network mode control" "Normal,Network,?..." bitfld.long 0x00 7. " RWA ,Receiver word alignment control" "Left,Right" bitfld.long 0x00 6. " RSHFD ,Receiver shift direction" "MSB first,LSB first" bitfld.long 0x00 3. " RE[3] ,ESAI receiver 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " [2] ,ESAI receiver 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,ESAI receiver 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,ESAI receiver 0 enable" "Disabled,Enabled" endif if ((per.l(ad:0x59010000+0xDC)&0x300)==0x100)&&((per.l(ad:0x59010000+0xD0)&0x40)==0x00) group.long 0xE0++0x03 line.long 0x00 "RCCR,Receive Clock Control Register" bitfld.long 0x00 23. " RHCKD ,High frequency clock direction (HCKR pin)" "HCKR input,HCKR output" bitfld.long 0x00 22. " RFSD ,Frame sync signal direction (FSR pin)" "FSR input,FSR output" bitfld.long 0x00 21. " RCKD ,Clock source direction (SCKR pin)" "SCKR input,SCKR output" bitfld.long 0x00 20. " RHCKP ,Receiver high frequency clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" newline bitfld.long 0x00 19. " RFSP ,Receiver frame sync polarity [clocked/latched]" "Rising/Falling,Falling/Rising" bitfld.long 0x00 18. " RCKP ,Receiver clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" bitfld.long 0x00 14.--17. " RFP ,Rx high frequency clock divider control" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 9.--13. " RDC ,Rx frame rate divider control" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline bitfld.long 0x00 8. " RPSR ,Receiver prescaler range" "Div by 8,Bypassed" hexmask.long.byte 0x00 0.--7. 1. " RPM ,Receiver prescale modulus select (divide ratio from 1 to 256)" elif ((per.l(ad:0x59010000+0xDC)&0x300)==0x100)&&((per.l(ad:0x59010000+0xD0)&0x40)==0x40)&&((per.l(ad:0x59010000+0xD0)&0x80)==0x0) group.long 0xE0++0x03 line.long 0x00 "RCCR,Receive Clock Control Register" bitfld.long 0x00 23. " RHCKD ,High frequency clock direction (HCKR pin)" "IF2,OF2" bitfld.long 0x00 22. " RFSD ,Frame sync signal direction (FSR pin)" "IF1,OF1" bitfld.long 0x00 21. " RCKD ,Clock source direction (SCKR pin)" "IF0,OF0" bitfld.long 0x00 20. " RHCKP ,Receiver high frequency clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" newline bitfld.long 0x00 19. " RFSP ,Receiver frame sync polarity [clocked/latched]" "Rising/Falling,Falling/Rising" bitfld.long 0x00 18. " RCKP ,Receiver clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" bitfld.long 0x00 14.--17. " RFP ,Rx high frequency clock divider control" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 9.--13. " RDC ,Rx frame rate divider control" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline bitfld.long 0x00 8. " RPSR ,Receiver prescaler range" "Div by 8,Bypassed" hexmask.long.byte 0x00 0.--7. 1. " RPM ,Receiver prescale modulus select (divide ratio from 1 to 256)" elif ((per.l(ad:0x59010000+0xDC)&0x300)==0x100)&&((per.l(ad:0x59010000+0xD0)&0x40)==0x40)&&((per.l(ad:0x59010000+0xD0)&0x80)==0x80) group.long 0xE0++0x03 line.long 0x00 "RCCR,Receive Clock Control Register" bitfld.long 0x00 23. " RHCKD ,High frequency clock direction (HCKR pin)" "IF2,OF2" bitfld.long 0x00 22. " RFSD ,Frame sync signal direction (FSR pin)" ",TxBufferEnable" bitfld.long 0x00 21. " RCKD ,Clock source direction (SCKR pin)" "IF0,OF0" bitfld.long 0x00 20. " RHCKP ,Receiver high frequency clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" newline bitfld.long 0x00 19. " RFSP ,Receiver frame sync polarity [clocked/latched]" "Rising/Falling,Falling/Rising" bitfld.long 0x00 18. " RCKP ,Receiver clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" bitfld.long 0x00 14.--17. " RFP ,Rx high frequency clock divider control" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 9.--13. " RDC ,Rx frame rate divider control" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline bitfld.long 0x00 8. " RPSR ,Receiver prescaler range" "Div by 8,Bypassed" hexmask.long.byte 0x00 0.--7. 1. " RPM ,Receiver prescale modulus select (divide ratio from 1 to 256)" elif ((per.l(ad:0x59010000+0xD0)&0x40)==0x00) group.long 0xE0++0x03 line.long 0x00 "RCCR,Receive Clock Control Register" bitfld.long 0x00 23. " RHCKD ,High frequency clock direction (HCKR pin)" "HCKR input,HCKR output" bitfld.long 0x00 22. " RFSD ,Frame sync signal direction (FSR pin)" "FSR input,FSR output" bitfld.long 0x00 21. " RCKD ,Clock source direction (SCKR pin)" "SCKR input,SCKR output" bitfld.long 0x00 20. " RHCKP ,Receiver high frequency clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" newline bitfld.long 0x00 19. " RFSP ,Receiver frame sync polarity [clocked/latched]" "Rising/Falling,Falling/Rising" bitfld.long 0x00 18. " RCKP ,Receiver clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" bitfld.long 0x00 14.--17. " RFP ,Rx high frequency clock divider control" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 9.--13. " RDC ,Rx frame rate divider control" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline bitfld.long 0x00 8. " RPSR ,Receiver prescaler range" "Div by 8,Bypassed" hexmask.long.byte 0x00 0.--7. 1. " RPM ,Receiver prescale modulus select (divide ratio from 1 to 256)" elif (((per.l(ad:0x59010000+0xD0)&0x40)==0x40)&&((per.l(ad:0x59010000+0xD0)&0x80)==0x00)) group.long 0xE0++0x03 line.long 0x00 "RCCR,Receive Clock Control Register" bitfld.long 0x00 23. " RHCKD ,High frequency clock direction (HCKR pin)" "IF2,OF2" bitfld.long 0x00 22. " RFSD ,Frame sync signal direction (FSR pin)" "IF1,OF1" bitfld.long 0x00 21. " RCKD ,Clock source direction (SCKR pin)" "IF0,OF0" bitfld.long 0x00 20. " RHCKP ,Receiver high frequency clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" newline bitfld.long 0x00 19. " RFSP ,Receiver frame sync polarity [clocked/latched]" "Rising/Falling,Falling/Rising" bitfld.long 0x00 18. " RCKP ,Receiver clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" bitfld.long 0x00 14.--17. " RFP ,Rx high frequency clock divider control" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 9.--13. " RDC ,Rx frame rate divider control" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline bitfld.long 0x00 8. " RPSR ,Receiver prescaler range" "Div by 8,Bypassed" hexmask.long.byte 0x00 0.--7. 1. " RPM ,Receiver prescale modulus select (divide ratio from 1 to 256)" elif (((per.l(ad:0x59010000+0xD0)&0x40)==0x40)&&((per.l(ad:0x59010000+0xD0)&0x80)==0x80)) group.long 0xE0++0x03 line.long 0x00 "RCCR,Receive Clock Control Register" bitfld.long 0x00 23. " RHCKD ,High frequency clock direction (HCKR pin)" "IF2,OF2" bitfld.long 0x00 22. " RFSD ,Frame sync signal direction (FSR pin)" ",TxBufferEnable" bitfld.long 0x00 21. " RCKD ,Clock source direction (SCKR pin)" "IF0,OF0" bitfld.long 0x00 20. " RHCKP ,Receiver high frequency clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" newline bitfld.long 0x00 19. " RFSP ,Receiver frame sync polarity [clocked/latched]" "Rising/Falling,Falling/Rising" bitfld.long 0x00 18. " RCKP ,Receiver clock polarity [clocked/latched]" "Rising/Falling,Falling/Rising" bitfld.long 0x00 14.--17. " RFP ,Rx high frequency clock divider control" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 9.--13. " RDC ,Rx frame rate divider control" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline bitfld.long 0x00 8. " RPSR ,Receiver prescaler range" "Div by 8,Bypassed" hexmask.long.byte 0x00 0.--7. 1. " RPM ,Receiver prescale modulus select (divide ratio from 1 to 256)" endif group.long 0xE4++0x0F line.long 0x00 "TSMA,Transmit Slot Mask Register A" bitfld.long 0x00 15. " TS[15] ,Transmit slot 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Transmit slot 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Transmit slot 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Transmit slot 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Transmit slot 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Transmit slot 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Transmit slot 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Transmit slot 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Transmit slot 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Transmit slot 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Transmit slot 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Transmit slot 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Transmit slot 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Transmit slot 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Transmit slot 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Transmit slot 0" "Disabled,Enabled" line.long 0x04 "TSMB,Transmit Slot Mask Register B" bitfld.long 0x04 15. " TS[31] ,Transmit slot 31" "Disabled,Enabled" bitfld.long 0x04 14. " [30] ,Transmit slot 30" "Disabled,Enabled" bitfld.long 0x04 13. " [29] ,Transmit slot 29" "Disabled,Enabled" bitfld.long 0x04 12. " [28] ,Transmit slot 28" "Disabled,Enabled" newline bitfld.long 0x04 11. " [27] ,Transmit slot 27" "Disabled,Enabled" bitfld.long 0x04 10. " [26] ,Transmit slot 26" "Disabled,Enabled" bitfld.long 0x04 9. " [25] ,Transmit slot 25" "Disabled,Enabled" bitfld.long 0x04 8. " [24] ,Transmit slot 24" "Disabled,Enabled" newline bitfld.long 0x04 7. " [23] ,Transmit slot 23" "Disabled,Enabled" bitfld.long 0x04 6. " [22] ,Transmit slot 22" "Disabled,Enabled" bitfld.long 0x04 5. " [21] ,Transmit slot 21" "Disabled,Enabled" bitfld.long 0x04 4. " [20] ,Transmit slot 20" "Disabled,Enabled" newline bitfld.long 0x04 3. " [19] ,Transmit slot 19" "Disabled,Enabled" bitfld.long 0x04 2. " [18] ,Transmit slot 18" "Disabled,Enabled" bitfld.long 0x04 1. " [17] ,Transmit slot 17" "Disabled,Enabled" bitfld.long 0x04 0. " [16] ,Transmit slot 16" "Disabled,Enabled" line.long 0x08 "RSMA,Receive Slot Mask Register A" bitfld.long 0x08 15. " RS[15] ,Receive slot 15" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Receive slot 14" "Disabled,Enabled" bitfld.long 0x08 13. " [13] ,Receive slot 13" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Receive slot 12" "Disabled,Enabled" newline bitfld.long 0x08 11. " [11] ,Receive slot 11" "Disabled,Enabled" bitfld.long 0x08 10. " [10] ,Receive slot 10" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Receive slot 9" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Receive slot 8" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Receive slot 7" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Receive slot 6" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Receive slot 5" "Disabled,Enabled" bitfld.long 0x08 4. " [4] ,Receive slot 4" "Disabled,Enabled" newline bitfld.long 0x08 3. " [3] ,Receive slot 3" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Receive slot 2" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Receive slot 1" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Receive slot 0" "Disabled,Enabled" line.long 0x0C "RSMB,Receive Slot Mask Register B" bitfld.long 0x0C 15. " RS[31] ,Receive slot 31" "Disabled,Enabled" bitfld.long 0x0C 14. " [30] ,Receive slot 30" "Disabled,Enabled" bitfld.long 0x0C 13. " [29] ,Receive slot 29" "Disabled,Enabled" bitfld.long 0x0C 12. " [28] ,Receive slot 28" "Disabled,Enabled" newline bitfld.long 0x0C 11. " [27] ,Receive slot 27" "Disabled,Enabled" bitfld.long 0x0C 10. " [26] ,Receive slot 26" "Disabled,Enabled" bitfld.long 0x0C 9. " [25] ,Receive slot 25" "Disabled,Enabled" bitfld.long 0x0C 8. " [24] ,Receive slot 24" "Disabled,Enabled" newline bitfld.long 0x0C 7. " [23] ,Receive slot 23" "Disabled,Enabled" bitfld.long 0x0C 6. " [22] ,Receive slot 22" "Disabled,Enabled" bitfld.long 0x0C 5. " [21] ,Receive slot 21" "Disabled,Enabled" bitfld.long 0x0C 4. " [20] ,Receive slot 20" "Disabled,Enabled" newline bitfld.long 0x0C 3. " [19] ,Receive slot 19" "Disabled,Enabled" bitfld.long 0x0C 2. " [18] ,Receive slot 18" "Disabled,Enabled" bitfld.long 0x0C 1. " [17] ,Receive slot 17" "Disabled,Enabled" bitfld.long 0x0C 0. " [16] ,Receive slot 16" "Disabled,Enabled" group.long 0xF8++0x07 line.long 0x00 "PRRC,Port C Direction Register" bitfld.long 0x00 11. " PDC[11] ,Port C direction pin 11" "0,1" bitfld.long 0x00 10. " [10] ,Port C direction pin 10" "0,1" bitfld.long 0x00 9. " [9] ,Port C direction pin 9" "0,1" bitfld.long 0x00 8. " [8] ,Port C direction pin 8" "0,1" newline bitfld.long 0x00 7. " [7] ,Port C direction pin 7" "0,1" bitfld.long 0x00 6. " [6] ,Port C direction pin 6" "0,1" bitfld.long 0x00 5. " [5] ,Port C direction pin 5" "0,1" bitfld.long 0x00 4. " [4] ,Port C direction pin 4" "0,1" newline bitfld.long 0x00 3. " [3] ,Port C direction pin 3" "0,1" bitfld.long 0x00 2. " [2] ,Port C direction pin 2" "0,1" bitfld.long 0x00 1. " [1] ,Port C direction pin 1" "0,1" bitfld.long 0x00 0. " [0] ,Port C direction pin 0" "0,1" line.long 0x04 "PCRC,Port C Control Register" bitfld.long 0x04 11. " PC[11] ,Port C control pin 11" "0,1" bitfld.long 0x04 10. " [10] ,Port C control pin 10" "0,1" bitfld.long 0x04 9. " [9] ,Port C control pin 9" "0,1" bitfld.long 0x04 8. " [8] ,Port C control pin 8" "0,1" newline bitfld.long 0x04 7. " [7] ,Port C control pin 7" "0,1" bitfld.long 0x04 6. " [6] ,Port C control pin 6" "0,1" bitfld.long 0x04 5. " [5] ,Port C control pin 5" "0,1" bitfld.long 0x04 4. " [4] ,Port C control pin 4" "0,1" newline bitfld.long 0x04 3. " [3] ,Port C control pin 3" "0,1" bitfld.long 0x04 2. " [2] ,Port C control pin 2" "0,1" bitfld.long 0x04 1. " [1] ,Port C control pin 1" "0,1" bitfld.long 0x04 0. " [0] ,Port C control pin 0" "0,1" width 0x0B tree.end tree.open "FLEXCAN (Flexible Controller Area Network)" tree "CAN0" base ad:0x5A8D0000 width 10. if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) if (((per.l(ad:0x5A8D0000+0x00))&0x20000000)==0x20000000) if (((per.l(ad:0x5A8D0000+0x00))&0x800)==0x800) if ((per.l(ad:0x5A8D0000)&0x100000)==0x00) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline bitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" newline hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline rbitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" newline hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif else if ((per.l(ad:0x5A8D0000)&0x100000)==0x00) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" bitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline bitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" newline hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" bitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline rbitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" newline hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif endif else if (((per.l(ad:0x5A8D0000+0x00))&0x800)==0x800) if ((per.l(ad:0x5A8D0000)&0x100000)==0x00) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline bitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline rbitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif else if ((per.l(ad:0x5A8D0000)&0x100000)==0x00) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" bitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline bitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" bitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline rbitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif endif endif else if (((per.l(ad:0x5A8D0000+0x00))&0x20000000)==0x20000000) if ((per.l(ad:0x5A8D0000)&0x100000)==0x00) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline bitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" rbitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" rbitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" rbitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" rbitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" rbitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" newline rbitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" rbitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" rbitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" rbitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" newline hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline rbitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" rbitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" rbitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" rbitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" rbitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" rbitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" newline rbitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" rbitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" rbitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" rbitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" newline hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif else if ((per.l(ad:0x5A8D0000)&0x100000)==0x00) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline bitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" rbitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" rbitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" rbitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" rbitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" rbitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline rbitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" rbitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" rbitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline rbitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" rbitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" rbitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" rbitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" rbitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" rbitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline rbitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" rbitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" rbitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif endif endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) if (((per.l(ad:0x5A8D0000+0x00))&0x200000)==0x200000) if ((per.l(ad:0x5A8D0000)&0x80000000)==0x00) group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" bitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" bitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" ",1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" bitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Peripheral,Oscillator" bitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline bitfld.long 0x00 11. " TWRNMSK ,Tx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RWRNMSK ,Rx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline bitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" bitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" bitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" bitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" else group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" bitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" bitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" ",1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Peripheral,Oscillator" bitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline bitfld.long 0x00 11. " TWRNMSK ,Tx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RWRNMSK ,Rx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline bitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" bitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" bitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" bitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" endif else if ((per.l(ad:0x5A8D0000)&0x80000000)==0x00) group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" bitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" bitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" ",1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" bitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Peripheral,Oscillator" bitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline rbitfld.long 0x00 11. " TWRNMSK ,Tx warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 10. " RWRNMSK ,Rx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline bitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" bitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" bitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" bitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" else group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" bitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" bitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" ",1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Peripheral,Oscillator" bitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline rbitfld.long 0x00 11. " TWRNMSK ,Tx warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 10. " RWRNMSK ,Rx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline bitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" bitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" bitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" bitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" endif endif else if (((per.l(ad:0x5A8D0000+0x00))&0x200000)==0x200000) if ((per.l(ad:0x5A8D0000)&0x80000000)==0x00) group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" rbitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" rbitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" ",1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" bitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Peripheral,Oscillator" rbitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline bitfld.long 0x00 11. " TWRNMSK ,Tx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RWRNMSK ,Rx warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline rbitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" rbitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" rbitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" rbitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" else group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" rbitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" rbitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" ",1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Peripheral,Oscillator" rbitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline bitfld.long 0x00 11. " TWRNMSK ,Tx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RWRNMSK ,Rx warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline rbitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" rbitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" rbitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" rbitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" endif else if ((per.l(ad:0x5A8D0000)&0x80000000)==0x00) group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" rbitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" rbitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" ",1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" bitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Peripheral,Oscillator" rbitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline rbitfld.long 0x00 11. " TWRNMSK ,Tx warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 10. " RWRNMSK ,Rx warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline rbitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" rbitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" rbitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" rbitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" else group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" rbitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" rbitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" ",1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Peripheral,Oscillator" rbitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline rbitfld.long 0x00 11. " TWRNMSK ,Tx warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 10. " RWRNMSK ,Rx warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline rbitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" rbitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" rbitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" rbitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" endif endif endif group.long 0x08++0x03 line.long 0x00 "TIMER,Free Running Timer" hexmask.long.word 0x00 0.--15. 1. " TIMER ,Timer value" if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long 0x10++0x0F line.long 0x00 "RXMGMASK,Rx Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG[31] ,Mailbox filter 31 mask" "0,1" bitfld.long 0x00 30. " [30] ,Mailbox filter 30 mask" "0,1" bitfld.long 0x00 29. " [29] ,Mailbox filter 29 mask" "0,1" bitfld.long 0x00 28. " [28] ,Mailbox filter 28 mask" "0,1" newline bitfld.long 0x00 27. " [27] ,Mailbox filter 27 mask" "0,1" bitfld.long 0x00 26. " [26] ,Mailbox filter 26 mask" "0,1" bitfld.long 0x00 25. " [25] ,Mailbox filter 25 mask" "0,1" bitfld.long 0x00 24. " [24] ,Mailbox filter 24 mask" "0,1" newline bitfld.long 0x00 23. " [23] ,Mailbox filter 23 mask" "0,1" bitfld.long 0x00 22. " [22] ,Mailbox filter 22 mask" "0,1" bitfld.long 0x00 21. " [21] ,Mailbox filter 21 mask" "0,1" bitfld.long 0x00 20. " [20] ,Mailbox filter 20 mask" "0,1" newline bitfld.long 0x00 19. " [19] ,Mailbox filter 19 mask" "0,1" bitfld.long 0x00 18. " [18] ,Mailbox filter 18 mask" "0,1" bitfld.long 0x00 17. " [17] ,Mailbox filter 17 mask" "0,1" bitfld.long 0x00 16. " [16] ,Mailbox filter 16 mask" "0,1" newline bitfld.long 0x00 15. " [15] ,Mailbox filter 15 mask" "0,1" bitfld.long 0x00 14. " [14] ,Mailbox filter 14 mask" "0,1" bitfld.long 0x00 13. " [13] ,Mailbox filter 13 mask" "0,1" bitfld.long 0x00 12. " [12] ,Mailbox filter 12 mask" "0,1" newline bitfld.long 0x00 11. " [11] ,Mailbox filter 11 mask" "0,1" bitfld.long 0x00 10. " [10] ,Mailbox filter 10 mask" "0,1" bitfld.long 0x00 9. " [9] ,Mailbox filter 9 mask" "0,1" bitfld.long 0x00 8. " [8] ,Mailbox filter 8 mask" "0,1" newline bitfld.long 0x00 7. " [7] ,Mailbox filter 7 mask" "0,1" bitfld.long 0x00 6. " [6] ,Mailbox filter 6 mask" "0,1" bitfld.long 0x00 5. " [5] ,Mailbox filter 5 mask" "0,1" bitfld.long 0x00 4. " [4] ,Mailbox filter 4 mask" "0,1" newline bitfld.long 0x00 3. " [3] ,Mailbox filter 3 mask" "0,1" bitfld.long 0x00 2. " [2] ,Mailbox filter 2 mask" "0,1" bitfld.long 0x00 1. " [1] ,Mailbox filter 1 mask" "0,1" bitfld.long 0x00 0. " [0] ,Mailbox filter 0 mask" "0,1" line.long 0x04 "RX14MASK,Rx Buffer 14 Mask Register" bitfld.long 0x04 31. " RX14M[31] ,Rx buffer 14 mask bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Rx buffer 14 mask bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Rx buffer 14 mask bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Rx buffer 14 mask bit 28" "0,1" newline bitfld.long 0x04 27. " [27] ,Rx buffer 14 mask bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Rx buffer 14 mask bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Rx buffer 14 mask bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Rx buffer 14 mask bit 24" "0,1" newline bitfld.long 0x04 23. " [23] ,Rx buffer 14 mask bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Rx buffer 14 mask bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Rx buffer 14 mask bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Rx buffer 14 mask bit 20" "0,1" newline bitfld.long 0x04 19. " [19] ,Rx buffer 14 mask bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Rx buffer 14 mask bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Rx buffer 14 mask bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Rx buffer 14 mask bit 16" "0,1" newline bitfld.long 0x04 15. " [15] ,Rx buffer 14 mask bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Rx buffer 14 mask bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Rx buffer 14 mask bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Rx buffer 14 mask bit 12" "0,1" newline bitfld.long 0x04 11. " [11] ,Rx buffer 14 mask bit 11" "0,1" bitfld.long 0x04 10. " [10] ,Rx buffer 14 mask bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Rx buffer 14 mask bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Rx buffer 14 mask bit 8" "0,1" newline bitfld.long 0x04 7. " [7] ,Rx buffer 14 mask bit 7" "0,1" bitfld.long 0x04 6. " [6] ,Rx buffer 14 mask bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Rx buffer 14 mask bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Rx buffer 14 mask bit 4" "0,1" newline bitfld.long 0x04 3. " [3] ,Rx buffer 14 mask bit 3" "0,1" bitfld.long 0x04 2. " [2] ,Rx buffer 14 mask bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Rx buffer 14 mask bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Rx buffer 14 mask bit 0" "0,1" line.long 0x08 "RX15MASK,Rx Buffer 15 Mask Register" bitfld.long 0x08 31. " RX15M[31] ,Rx buffer 15 mask bit 31" "0,1" bitfld.long 0x08 30. " [30] ,Rx buffer 15 mask bit 30" "0,1" bitfld.long 0x08 29. " [29] ,Rx buffer 15 mask bit 29" "0,1" bitfld.long 0x08 28. " [28] ,Rx buffer 15 mask bit 28" "0,1" newline bitfld.long 0x08 27. " [27] ,Rx buffer 15 mask bit 27" "0,1" bitfld.long 0x08 26. " [26] ,Rx buffer 15 mask bit 26" "0,1" bitfld.long 0x08 25. " [25] ,Rx buffer 15 mask bit 25" "0,1" bitfld.long 0x08 24. " [24] ,Rx buffer 15 mask bit 24" "0,1" newline bitfld.long 0x08 23. " [23] ,Rx buffer 15 mask bit 23" "0,1" bitfld.long 0x08 22. " [22] ,Rx buffer 15 mask bit 22" "0,1" bitfld.long 0x08 21. " [21] ,Rx buffer 15 mask bit 21" "0,1" bitfld.long 0x08 20. " [20] ,Rx buffer 15 mask bit 20" "0,1" newline bitfld.long 0x08 19. " [19] ,Rx buffer 15 mask bit 19" "0,1" bitfld.long 0x08 18. " [18] ,Rx buffer 15 mask bit 18" "0,1" bitfld.long 0x08 17. " [17] ,Rx buffer 15 mask bit 17" "0,1" bitfld.long 0x08 16. " [16] ,Rx buffer 15 mask bit 16" "0,1" newline bitfld.long 0x08 15. " [15] ,Rx buffer 15 mask bit 15" "0,1" bitfld.long 0x08 14. " [14] ,Rx buffer 15 mask bit 14" "0,1" bitfld.long 0x08 13. " [13] ,Rx buffer 15 mask bit 13" "0,1" bitfld.long 0x08 12. " [12] ,Rx buffer 15 mask bit 12" "0,1" newline bitfld.long 0x08 11. " [11] ,Rx buffer 15 mask bit 11" "0,1" bitfld.long 0x08 10. " [10] ,Rx buffer 15 mask bit 10" "0,1" bitfld.long 0x08 9. " [9] ,Rx buffer 15 mask bit 9" "0,1" bitfld.long 0x08 8. " [8] ,Rx buffer 15 mask bit 8" "0,1" newline bitfld.long 0x08 7. " [7] ,Rx buffer 15 mask bit 7" "0,1" bitfld.long 0x08 6. " [6] ,Rx buffer 15 mask bit 6" "0,1" bitfld.long 0x08 5. " [5] ,Rx buffer 15 mask bit 5" "0,1" bitfld.long 0x08 4. " [4] ,Rx buffer 15 mask bit 4" "0,1" newline bitfld.long 0x08 3. " [3] ,Rx buffer 15 mask bit 3" "0,1" bitfld.long 0x08 2. " [2] ,Rx buffer 15 mask bit 2" "0,1" bitfld.long 0x08 1. " [1] ,Rx buffer 15 mask bit 1" "0,1" bitfld.long 0x08 0. " [0] ,Rx buffer 15 mask bit 0" "0,1" line.long 0x0C "ECR,Error Counter Register" hexmask.long.byte 0x0C 24.--31. 1. " RXERRCNT_FAST ,Receive error counter for fast bit" hexmask.long.byte 0x0C 16.--23. 1. " TXERRCNT_FAST ,Transmit error counter for fast bits" hexmask.long.byte 0x0C 8.--15. 1. " RXERRCNT ,Receive error counter" hexmask.long.byte 0x0C 0.--7. 1. " TXERRCNT ,Transmit error counter" else rgroup.long 0x10++0x0F line.long 0x00 "RXMGMASK,Rx Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG[31] ,Mailbox filter 31 mask" "0,1" bitfld.long 0x00 30. " [30] ,Mailbox filter 30 mask" "0,1" bitfld.long 0x00 29. " [29] ,Mailbox filter 29 mask" "0,1" bitfld.long 0x00 28. " [28] ,Mailbox filter 28 mask" "0,1" newline bitfld.long 0x00 27. " [27] ,Mailbox filter 27 mask" "0,1" bitfld.long 0x00 26. " [26] ,Mailbox filter 26 mask" "0,1" bitfld.long 0x00 25. " [25] ,Mailbox filter 25 mask" "0,1" bitfld.long 0x00 24. " [24] ,Mailbox filter 24 mask" "0,1" newline bitfld.long 0x00 23. " [23] ,Mailbox filter 23 mask" "0,1" bitfld.long 0x00 22. " [22] ,Mailbox filter 22 mask" "0,1" bitfld.long 0x00 21. " [21] ,Mailbox filter 21 mask" "0,1" bitfld.long 0x00 20. " [20] ,Mailbox filter 20 mask" "0,1" newline bitfld.long 0x00 19. " [19] ,Mailbox filter 19 mask" "0,1" bitfld.long 0x00 18. " [18] ,Mailbox filter 18 mask" "0,1" bitfld.long 0x00 17. " [17] ,Mailbox filter 17 mask" "0,1" bitfld.long 0x00 16. " [16] ,Mailbox filter 16 mask" "0,1" newline bitfld.long 0x00 15. " [15] ,Mailbox filter 15 mask" "0,1" bitfld.long 0x00 14. " [14] ,Mailbox filter 14 mask" "0,1" bitfld.long 0x00 13. " [13] ,Mailbox filter 13 mask" "0,1" bitfld.long 0x00 12. " [12] ,Mailbox filter 12 mask" "0,1" newline bitfld.long 0x00 11. " [11] ,Mailbox filter 11 mask" "0,1" bitfld.long 0x00 10. " [10] ,Mailbox filter 10 mask" "0,1" bitfld.long 0x00 9. " [9] ,Mailbox filter 9 mask" "0,1" bitfld.long 0x00 8. " [8] ,Mailbox filter 8 mask" "0,1" newline bitfld.long 0x00 7. " [7] ,Mailbox filter 7 mask" "0,1" bitfld.long 0x00 6. " [6] ,Mailbox filter 6 mask" "0,1" bitfld.long 0x00 5. " [5] ,Mailbox filter 5 mask" "0,1" bitfld.long 0x00 4. " [4] ,Mailbox filter 4 mask" "0,1" newline bitfld.long 0x00 3. " [3] ,Mailbox filter 3 mask" "0,1" bitfld.long 0x00 2. " [2] ,Mailbox filter 2 mask" "0,1" bitfld.long 0x00 1. " [1] ,Mailbox filter 1 mask" "0,1" bitfld.long 0x00 0. " [0] ,Mailbox filter 0 mask" "0,1" line.long 0x04 "RX14MASK,Rx Buffer 14 Mask Register" bitfld.long 0x04 31. " RX14M[31] ,Mailbox 14 filter 31 mask" "0,1" bitfld.long 0x04 30. " [30] ,Mailbox 14 filter 30 mask" "0,1" bitfld.long 0x04 29. " [29] ,Mailbox 14 filter 29 mask" "0,1" bitfld.long 0x04 28. " [28] ,Mailbox 14 filter 28 mask" "0,1" newline bitfld.long 0x04 27. " [27] ,Mailbox 14 filter 27 mask" "0,1" bitfld.long 0x04 26. " [26] ,Mailbox 14 filter 26 mask" "0,1" bitfld.long 0x04 25. " [25] ,Mailbox 14 filter 25 mask" "0,1" bitfld.long 0x04 24. " [24] ,Mailbox 14 filter 24 mask" "0,1" newline bitfld.long 0x04 23. " [23] ,Mailbox 14 filter 23 mask" "0,1" bitfld.long 0x04 22. " [22] ,Mailbox 14 filter 22 mask" "0,1" bitfld.long 0x04 21. " [21] ,Mailbox 14 filter 21 mask" "0,1" bitfld.long 0x04 20. " [20] ,Mailbox 14 filter 20 mask" "0,1" newline bitfld.long 0x04 19. " [19] ,Mailbox 14 filter 19 mask" "0,1" bitfld.long 0x04 18. " [18] ,Mailbox 14 filter 18 mask" "0,1" bitfld.long 0x04 17. " [17] ,Mailbox 14 filter 17 mask" "0,1" bitfld.long 0x04 16. " [16] ,Mailbox 14 filter 16 mask" "0,1" newline bitfld.long 0x04 15. " [15] ,Mailbox 14 filter 15 mask" "0,1" bitfld.long 0x04 14. " [14] ,Mailbox 14 filter 14 mask" "0,1" bitfld.long 0x04 13. " [13] ,Mailbox 14 filter 13 mask" "0,1" bitfld.long 0x04 12. " [12] ,Mailbox 14 filter 12 mask" "0,1" newline bitfld.long 0x04 11. " [11] ,Mailbox 14 filter 11 mask" "0,1" bitfld.long 0x04 10. " [10] ,Mailbox 14 filter 10 mask" "0,1" bitfld.long 0x04 9. " [9] ,Mailbox 14 filter 9 mask" "0,1" bitfld.long 0x04 8. " [8] ,Mailbox 14 filter 8 mask" "0,1" newline bitfld.long 0x04 7. " [7] ,Mailbox 14 filter 7 mask" "0,1" bitfld.long 0x04 6. " [6] ,Mailbox 14 filter 6 mask" "0,1" bitfld.long 0x04 5. " [5] ,Mailbox 14 filter 5 mask" "0,1" bitfld.long 0x04 4. " [4] ,Mailbox 14 filter 4 mask" "0,1" newline bitfld.long 0x04 3. " [3] ,Mailbox 14 filter 3 mask" "0,1" bitfld.long 0x04 2. " [2] ,Mailbox 14 filter 2 mask" "0,1" bitfld.long 0x04 1. " [1] ,Mailbox 14 filter 1 mask" "0,1" bitfld.long 0x04 0. " [0] ,Mailbox 14 filter 0 mask" "0,1" line.long 0x08 "RX15MASK,Rx Buffer 15 Mask Register" bitfld.long 0x08 31. " RX15M[31] ,Mailbox 15 filter 31 mask" "0,1" bitfld.long 0x08 30. " [30] ,Mailbox 15 filter 30 mask" "0,1" bitfld.long 0x08 29. " [29] ,Mailbox 15 filter 29 mask" "0,1" bitfld.long 0x08 28. " [28] ,Mailbox 15 filter 28 mask" "0,1" newline bitfld.long 0x08 27. " [27] ,Mailbox 15 filter 27 mask" "0,1" bitfld.long 0x08 26. " [26] ,Mailbox 15 filter 26 mask" "0,1" bitfld.long 0x08 25. " [25] ,Mailbox 15 filter 25 mask" "0,1" bitfld.long 0x08 24. " [24] ,Mailbox 15 filter 24 mask" "0,1" newline bitfld.long 0x08 23. " [23] ,Mailbox 15 filter 23 mask" "0,1" bitfld.long 0x08 22. " [22] ,Mailbox 15 filter 22 mask" "0,1" bitfld.long 0x08 21. " [21] ,Mailbox 15 filter 21 mask" "0,1" bitfld.long 0x08 20. " [20] ,Mailbox 15 filter 20 mask" "0,1" newline bitfld.long 0x08 19. " [19] ,Mailbox 15 filter 19 mask" "0,1" bitfld.long 0x08 18. " [18] ,Mailbox 15 filter 18 mask" "0,1" bitfld.long 0x08 17. " [17] ,Mailbox 15 filter 17 mask" "0,1" bitfld.long 0x08 16. " [16] ,Mailbox 15 filter 16 mask" "0,1" newline bitfld.long 0x08 15. " [15] ,Mailbox 15 filter 15 mask" "0,1" bitfld.long 0x08 14. " [14] ,Mailbox 15 filter 14 mask" "0,1" bitfld.long 0x08 13. " [13] ,Mailbox 15 filter 13 mask" "0,1" bitfld.long 0x08 12. " [12] ,Mailbox 15 filter 12 mask" "0,1" newline bitfld.long 0x08 11. " [11] ,Mailbox 15 filter 11 mask" "0,1" bitfld.long 0x08 10. " [10] ,Mailbox 15 filter 10 mask" "0,1" bitfld.long 0x08 9. " [9] ,Mailbox 15 filter 9 mask" "0,1" bitfld.long 0x08 8. " [8] ,Mailbox 15 filter 8 mask" "0,1" newline bitfld.long 0x08 7. " [7] ,Mailbox 15 filter 7 mask" "0,1" bitfld.long 0x08 6. " [6] ,Mailbox 15 filter 6 mask" "0,1" bitfld.long 0x08 5. " [5] ,Mailbox 15 filter 5 mask" "0,1" bitfld.long 0x08 4. " [4] ,Mailbox 15 filter 4 mask" "0,1" newline bitfld.long 0x08 3. " [3] ,Mailbox 15 filter 3 mask" "0,1" bitfld.long 0x08 2. " [2] ,Mailbox 15 filter 2 mask" "0,1" bitfld.long 0x08 1. " [1] ,Mailbox 15 filter 1 mask" "0,1" bitfld.long 0x08 0. " [0] ,Mailbox 15 filter 0 mask" "0,1" line.long 0x0C "ECR,Error Counter Register" hexmask.long.byte 0x0C 24.--31. 1. " RXERRCNT_FAST ,Receive error counter for fast bit" hexmask.long.byte 0x0C 16.--23. 1. " TXERRCNT_FAST ,Transmit error counter for fast bits" hexmask.long.byte 0x0C 8.--15. 1. " RXERRCNT ,Receive error counter" hexmask.long.byte 0x0C 0.--7. 1. " TXERRCNT ,Transmit error counter" endif newline hgroup.long 0x20++0x03 hide.long 0x00 "ESR1,Error And Status Register 1" in newline group.long 0x24++0x0B line.long 0x00 "IMASK2,Interrupt Mask Register 2" bitfld.long 0x00 31. " BUF[63]TO32M ,Buffer MB63 mask" "Disabled,Enabled" bitfld.long 0x00 30. " [62] ,Buffer MB62 mask" "Disabled,Enabled" bitfld.long 0x00 29. " [61] ,Buffer MB61 mask" "Disabled,Enabled" bitfld.long 0x00 28. " [60] ,Buffer MB60 mask" "Disabled,Enabled" newline bitfld.long 0x00 27. " [59] ,Buffer MB59 mask" "Disabled,Enabled" bitfld.long 0x00 26. " [58] ,Buffer MB58 mask" "Disabled,Enabled" bitfld.long 0x00 25. " [57] ,Buffer MB57 mask" "Disabled,Enabled" bitfld.long 0x00 24. " [56] ,Buffer MB56 mask" "Disabled,Enabled" newline bitfld.long 0x00 23. " [55] ,Buffer MB55 mask" "Disabled,Enabled" bitfld.long 0x00 22. " [54] ,Buffer MB54 mask" "Disabled,Enabled" bitfld.long 0x00 21. " [53] ,Buffer MB53 mask" "Disabled,Enabled" bitfld.long 0x00 20. " [52] ,Buffer MB52 mask" "Disabled,Enabled" newline bitfld.long 0x00 19. " [51] ,Buffer MB51 mask" "Disabled,Enabled" bitfld.long 0x00 18. " [50] ,Buffer MB50 mask" "Disabled,Enabled" bitfld.long 0x00 17. " [49] ,Buffer MB49 mask" "Disabled,Enabled" bitfld.long 0x00 16. " [48] ,Buffer MB48 mask" "Disabled,Enabled" newline bitfld.long 0x00 15. " [47] ,Buffer MB47 mask" "Disabled,Enabled" bitfld.long 0x00 14. " [46] ,Buffer MB46 mask" "Disabled,Enabled" bitfld.long 0x00 13. " [45] ,Buffer MB45 mask" "Disabled,Enabled" bitfld.long 0x00 12. " [44] ,Buffer MB44 mask" "Disabled,Enabled" newline bitfld.long 0x00 11. " [43] ,Buffer MB43 mask" "Disabled,Enabled" bitfld.long 0x00 10. " [42] ,Buffer MB42 mask" "Disabled,Enabled" bitfld.long 0x00 9. " [41] ,Buffer MB41 mask" "Disabled,Enabled" bitfld.long 0x00 8. " [40] ,Buffer MB40 mask" "Disabled,Enabled" newline bitfld.long 0x00 7. " [39] ,Buffer MB39 mask" "Disabled,Enabled" bitfld.long 0x00 6. " [38] ,Buffer MB38 mask" "Disabled,Enabled" bitfld.long 0x00 5. " [37] ,Buffer MB37 mask" "Disabled,Enabled" bitfld.long 0x00 4. " [36] ,Buffer MB36 mask" "Disabled,Enabled" newline bitfld.long 0x00 3. " [35] ,Buffer MB35 mask" "Disabled,Enabled" bitfld.long 0x00 2. " [34] ,Buffer MB34 mask" "Disabled,Enabled" bitfld.long 0x00 1. " [33] ,Buffer MB33 mask" "Disabled,Enabled" bitfld.long 0x00 0. " [32] ,Buffer MB32 mask" "Disabled,Enabled" line.long 0x04 "IMASK1,Interrupt Masks Register 1" bitfld.long 0x04 31. " BUF[31]TO0M ,Buffer MB31 mask" "Disabled,Enabled" bitfld.long 0x04 30. " [30] ,Buffer MB30 mask" "Disabled,Enabled" bitfld.long 0x04 29. " [29] ,Buffer MB29 mask" "Disabled,Enabled" bitfld.long 0x04 28. " [28] ,Buffer MB28 mask" "Disabled,Enabled" newline bitfld.long 0x04 27. " [27] ,Buffer MB27 mask" "Disabled,Enabled" bitfld.long 0x04 26. " [26] ,Buffer MB26 mask" "Disabled,Enabled" bitfld.long 0x04 25. " [25] ,Buffer MB25 mask" "Disabled,Enabled" bitfld.long 0x04 24. " [24] ,Buffer MB24 mask" "Disabled,Enabled" newline bitfld.long 0x04 23. " [23] ,Buffer MB23 mask" "Disabled,Enabled" bitfld.long 0x04 22. " [22] ,Buffer MB22 mask" "Disabled,Enabled" bitfld.long 0x04 21. " [21] ,Buffer MB21 mask" "Disabled,Enabled" bitfld.long 0x04 20. " [20] ,Buffer MB20 mask" "Disabled,Enabled" newline bitfld.long 0x04 19. " [19] ,Buffer MB19 mask" "Disabled,Enabled" bitfld.long 0x04 18. " [18] ,Buffer MB18 mask" "Disabled,Enabled" bitfld.long 0x04 17. " [17] ,Buffer MB17 mask" "Disabled,Enabled" bitfld.long 0x04 16. " [16] ,Buffer MB16 mask" "Disabled,Enabled" newline bitfld.long 0x04 15. " [15] ,Buffer MB15 mask" "Disabled,Enabled" bitfld.long 0x04 14. " [14] ,Buffer MB14 mask" "Disabled,Enabled" bitfld.long 0x04 13. " [13] ,Buffer MB13 mask" "Disabled,Enabled" bitfld.long 0x04 12. " [12] ,Buffer MB12 mask" "Disabled,Enabled" newline bitfld.long 0x04 11. " [11] ,Buffer MB11 mask" "Disabled,Enabled" bitfld.long 0x04 10. " [10] ,Buffer MB10 mask" "Disabled,Enabled" bitfld.long 0x04 9. " [9] ,Buffer MB9 mask" "Disabled,Enabled" bitfld.long 0x04 8. " [8] ,Buffer MB8 mask" "Disabled,Enabled" newline bitfld.long 0x04 7. " [7] ,Buffer MB7 mask" "Disabled,Enabled" bitfld.long 0x04 6. " [6] ,Buffer MB6 mask" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,Buffer MB5 mask" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,Buffer MB4 mask" "Disabled,Enabled" newline bitfld.long 0x04 3. " [3] ,Buffer MB3 mask" "Disabled,Enabled" bitfld.long 0x04 2. " [2] ,Buffer MB2 mask" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,Buffer MB1 mask" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,Buffer MB0 mask" "Disabled,Enabled" line.long 0x08 "IFLAG2,Interrupt Flags 2 Register" eventfld.long 0x08 31. " BUF[63]TO32I ,Buffer MB63 interrupt" "Not occurred,Occurred" eventfld.long 0x08 30. " [62] ,Buffer MB62 interrupt" "Not occurred,Occurred" eventfld.long 0x08 29. " [61] ,Buffer MB61 interrupt" "Not occurred,Occurred" eventfld.long 0x08 28. " [60] ,Buffer MB60 interrupt" "Not occurred,Occurred" newline eventfld.long 0x08 27. " [59] ,Buffer MB59 interrupt" "Not occurred,Occurred" eventfld.long 0x08 26. " [58] ,Buffer MB58 interrupt" "Not occurred,Occurred" eventfld.long 0x08 25. " [57] ,Buffer MB57 interrupt" "Not occurred,Occurred" eventfld.long 0x08 24. " [56] ,Buffer MB56 interrupt" "Not occurred,Occurred" newline eventfld.long 0x08 23. " [55] ,Buffer MB55 interrupt" "Not occurred,Occurred" eventfld.long 0x08 22. " [54] ,Buffer MB54 interrupt" "Not occurred,Occurred" eventfld.long 0x08 21. " [53] ,Buffer MB53 interrupt" "Not occurred,Occurred" eventfld.long 0x08 20. " [52] ,Buffer MB52 interrupt" "Not occurred,Occurred" newline eventfld.long 0x08 19. " [51] ,Buffer MB51 interrupt" "Not occurred,Occurred" eventfld.long 0x08 18. " [50] ,Buffer MB50 interrupt" "Not occurred,Occurred" eventfld.long 0x08 17. " [49] ,Buffer MB49 interrupt" "Not occurred,Occurred" eventfld.long 0x08 16. " [48] ,Buffer MB48 interrupt" "Not occurred,Occurred" newline eventfld.long 0x08 15. " [47] ,Buffer MB47 interrupt" "Not occurred,Occurred" eventfld.long 0x08 14. " [46] ,Buffer MB46 interrupt" "Not occurred,Occurred" eventfld.long 0x08 13. " [45] ,Buffer MB45 interrupt" "Not occurred,Occurred" eventfld.long 0x08 12. " [44] ,Buffer MB44 interrupt" "Not occurred,Occurred" newline eventfld.long 0x08 11. " [43] ,Buffer MB43 interrupt" "Not occurred,Occurred" eventfld.long 0x08 10. " [42] ,Buffer MB42 interrupt" "Not occurred,Occurred" eventfld.long 0x08 9. " [41] ,Buffer MB41 interrupt" "Not occurred,Occurred" eventfld.long 0x08 8. " [40] ,Buffer MB40 interrupt" "Not occurred,Occurred" newline eventfld.long 0x08 7. " [39] ,Buffer MB39 interrupt" "Not occurred,Occurred" eventfld.long 0x08 6. " [38] ,Buffer MB38 interrupt" "Not occurred,Occurred" eventfld.long 0x08 5. " [37] ,Buffer MB37 interrupt" "Not occurred,Occurred" eventfld.long 0x08 4. " [36] ,Buffer MB36 interrupt" "Not occurred,Occurred" newline eventfld.long 0x08 3. " [35] ,Buffer MB35 interrupt" "Not occurred,Occurred" eventfld.long 0x08 2. " [34] ,Buffer MB34 interrupt" "Not occurred,Occurred" eventfld.long 0x08 1. " [33] ,Buffer MB33 interrupt" "Not occurred,Occurred" eventfld.long 0x08 0. " [32] ,Buffer MB32 interrupt" "Not occurred,Occurred" if (((per.l(ad:0x5A8D0000))&0x20000000)==0x00) group.long 0x30++0x03 line.long 0x00 "IFLAG1,Interrupt Flags 1 Register" eventfld.long 0x00 31. " BUF[31]I ,Buffer MB 31 interrupt" "Not occurred,Occurred" eventfld.long 0x00 30. " [30] ,Buffer MB30 interrupt" "Not occurred,Occurred" eventfld.long 0x00 29. " [29] ,Buffer MB29 interrupt" "Not occurred,Occurred" eventfld.long 0x00 28. " [28] ,Buffer MB28 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 27. " [27] ,Buffer MB27 interrupt" "Not occurred,Occurred" eventfld.long 0x00 26. " [26] ,Buffer MB26 interrupt" "Not occurred,Occurred" eventfld.long 0x00 25. " [25] ,Buffer MB25 interrupt" "Not occurred,Occurred" eventfld.long 0x00 24. " [24] ,Buffer MB24 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 23. " [23] ,Buffer MB23 interrupt" "Not occurred,Occurred" eventfld.long 0x00 22. " [22] ,Buffer MB22 interrupt" "Not occurred,Occurred" eventfld.long 0x00 21. " [21] ,Buffer MB21 interrupt" "Not occurred,Occurred" eventfld.long 0x00 20. " [20] ,Buffer MB20 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 19. " [19] ,Buffer MB19 interrupt" "Not occurred,Occurred" eventfld.long 0x00 18. " [18] ,Buffer MB18 interrupt" "Not occurred,Occurred" eventfld.long 0x00 17. " [17] ,Buffer MB17 interrupt" "Not occurred,Occurred" eventfld.long 0x00 16. " [16] ,Buffer MB16 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 15. " [15] ,Buffer MB15 interrupt" "Not occurred,Occurred" eventfld.long 0x00 14. " [14] ,Buffer MB14 interrupt" "Not occurred,Occurred" eventfld.long 0x00 13. " [13] ,Buffer MB13 interrupt" "Not occurred,Occurred" eventfld.long 0x00 12. " [12] ,Buffer MB12 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 11. " [11] ,Buffer MB11 interrupt" "Not occurred,Occurred" eventfld.long 0x00 10. " [10] ,Buffer MB10 interrupt" "Not occurred,Occurred" eventfld.long 0x00 9. " [9] ,Buffer MB9 interrupt" "Not occurred,Occurred" eventfld.long 0x00 8. " [8] ,Buffer MB8 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 7. " [7] ,Buffer MB7 interrupt" "Not occurred,Occurred" eventfld.long 0x00 6. " [6] ,Buffer MB6 interrupt" "Not occurred,Occurred" eventfld.long 0x00 5. " [5] ,Buffer MB5 interrupt" "Not occurred,Occurred" eventfld.long 0x00 4. " [4] ,Buffer MB4 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 3. " [3] ,Buffer MB3 interrupt" "Not occurred,Occurred" eventfld.long 0x00 2. " [2] ,Buffer MB2 interrupt" "Not occurred,Occurred" eventfld.long 0x00 1. " [1] ,Buffer MB1 interrupt" "Not occurred,Occurred" eventfld.long 0x00 0. " [0] ,Buffer MB0 interrupt" "Not occurred,Occurred" else group.long 0x30++0x03 line.long 0x00 "IFLAG1,Interrupt Flags 1 Register" eventfld.long 0x00 31. " BUF[31]I ,Buffer MB31 interrupt" "Not occurred,Occurred" eventfld.long 0x00 30. " [30] ,Buffer MB30 interrupt" "Not occurred,Occurred" eventfld.long 0x00 29. " [29] ,Buffer MB29 interrupt" "Not occurred,Occurred" eventfld.long 0x00 28. " [28] ,Buffer MB28 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 27. " [27] ,Buffer MB27 interrupt" "Not occurred,Occurred" eventfld.long 0x00 26. " [26] ,Buffer MB26 interrupt" "Not occurred,Occurred" eventfld.long 0x00 25. " [25] ,Buffer MB25 interrupt" "Not occurred,Occurred" eventfld.long 0x00 24. " [24] ,Buffer MB24 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 23. " [23] ,Buffer MB23 interrupt" "Not occurred,Occurred" eventfld.long 0x00 22. " [22] ,Buffer MB22 interrupt" "Not occurred,Occurred" eventfld.long 0x00 21. " [21] ,Buffer MB21 interrupt" "Not occurred,Occurred" eventfld.long 0x00 20. " [20] ,Buffer MB20 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 19. " [19] ,Buffer MB19 interrupt" "Not occurred,Occurred" eventfld.long 0x00 18. " [18] ,Buffer MB18 interrupt" "Not occurred,Occurred" eventfld.long 0x00 17. " [17] ,Buffer MB17 interrupt" "Not occurred,Occurred" eventfld.long 0x00 16. " [16] ,Buffer MB16 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 15. " [15] ,Buffer MB15 interrupt" "Not occurred,Occurred" eventfld.long 0x00 14. " [14] ,Buffer MB14 interrupt" "Not occurred,Occurred" eventfld.long 0x00 13. " [13] ,Buffer MB13 interrupt" "Not occurred,Occurred" eventfld.long 0x00 12. " [12] ,Buffer MB12 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 11. " [11] ,Buffer MB11 interrupt" "Not occurred,Occurred" eventfld.long 0x00 10. " [10] ,Buffer MB10 interrupt" "Not occurred,Occurred" eventfld.long 0x00 9. " [9] ,Buffer MB9 interrupt" "Not occurred,Occurred" eventfld.long 0x00 8. " [8] ,Buffer MB8 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 7. " [7] ,Rx FIFO overflow" "No overflow,Overflow" eventfld.long 0x00 6. " [6] ,Rx FIFO almost full warning" "< 5 unread messages in FIFO,> 5 unread messages in FIFO" eventfld.long 0x00 5. " [5] ,Least one frame is available to be read from the FIFO" "Not available,Available" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long 0x34++0x03 line.long 0x00 "CTRL2,Control 2 Register" bitfld.long 0x00 31. " ERRMSK_FAST ,Error interrupt mask for errors detected in the data phase of fast CAN FD frames" "Disabled,Enabled" bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Disabled,Enabled" bitfld.long 0x00 24.--27. " RFFN ,Number of Rx FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128,?..." bitfld.long 0x00 19.--23. " TASD ,Tx arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "Rx FIFO first,Mailboxes first" bitfld.long 0x00 17. " RRS ,Remote request storing" "Remote response generated,Remote request stored" bitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for Rx mailboxes" "Disabled,Enabled" newline bitfld.long 0x00 14. " PREXCEN ,Protocol exception enable" "Disabled,Enabled" bitfld.long 0x00 12. " ISOCANFDEN ,ISO CAN FD enable" "Disabled,Enabled" bitfld.long 0x00 11. " EDFLTDIS ,Edge filter disable" "No,Yes" else group.long 0x34++0x03 line.long 0x00 "CTRL2,Control 2 Register" bitfld.long 0x00 31. " ERRMSK_FAST ,Error interrupt mask for errors detected in the data phase of fast CAN FD frames" "Disabled,Enabled" bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 24.--27. " RFFN ,Number of Rx FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128,?..." rbitfld.long 0x00 19.--23. " TASD ,Tx arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "Rx FIFO first,Mailboxes first" rbitfld.long 0x00 17. " RRS ,Remote request storing" "Remote response generated,Remote request stored" rbitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for Rx mailboxes" "Disabled,Enabled" rbitfld.long 0x00 15. " TIMER_SRC ,Timer source" "CAN bit clock,External time tick" newline rbitfld.long 0x00 14. " PREXCEN ,Protocol exception enable" "Disabled,Enabled" rbitfld.long 0x00 12. " ISOCANFDEN ,ISO CAN FD enable" "Disabled,Enabled" rbitfld.long 0x00 11. " EDFLTDIS ,Edge filter disable" "No,Yes" endif rgroup.long 0x38++0x03 line.long 0x00 "ESR2,Error And Status Register 2" hexmask.long.byte 0x00 16.--22. 1. " LPTM ,Lowest priority Tx mailbox" bitfld.long 0x00 14. " VPS ,Valid priority status" "Not valid,Valid" bitfld.long 0x00 13. " IMB ,Inactive mailbox available" "Not available,Available" rgroup.long 0x44++0x03 line.long 0x00 "CRCR,CRC Register" hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,CRC mailbox number" hexmask.long.word 0x00 0.--14. 1. " TXCRC ,CRC value of the last message transmitted" if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long 0x48++0x03 line.long 0x00 "RXFGMASK,Rx FIFO Global Mask Register" bitfld.long 0x00 31. " FGM[31] ,Rx FIFO global mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Rx FIFO global mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Rx FIFO global mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Rx FIFO global mask bit 28" "0,1" newline bitfld.long 0x00 27. " [27] ,Rx FIFO global mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Rx FIFO global mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Rx FIFO global mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Rx FIFO global mask bit 24" "0,1" newline bitfld.long 0x00 23. " [23] ,Rx FIFO global mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Rx FIFO global mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Rx FIFO global mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Rx FIFO global mask bit 20" "0,1" newline bitfld.long 0x00 19. " [19] ,Rx FIFO global mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Rx FIFO global mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Rx FIFO global mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Rx FIFO global mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Rx FIFO global mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Rx FIFO global mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Rx FIFO global mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Rx FIFO global mask bit 12" "0,1" newline bitfld.long 0x00 11. " [11] ,Rx FIFO global mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Rx FIFO global mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Rx FIFO global mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Rx FIFO global mask bit 8" "0,1" newline bitfld.long 0x00 7. " [7] ,Rx FIFO global mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Rx FIFO global mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Rx FIFO global mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Rx FIFO global mask bit 4" "0,1" newline bitfld.long 0x00 3. " [3] ,Rx FIFO global mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Rx FIFO global mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Rx FIFO global mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Rx FIFO global mask bit 0" "0,1" else rgroup.long 0x48++0x03 line.long 0x00 "RXFGMASK,Rx FIFO Global Mask Register" bitfld.long 0x00 31. " FGM[31] ,Rx FIFO global mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Rx FIFO global mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Rx FIFO global mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Rx FIFO global mask bit 28" "0,1" newline bitfld.long 0x00 27. " [27] ,Rx FIFO global mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Rx FIFO global mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Rx FIFO global mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Rx FIFO global mask bit 24" "0,1" newline bitfld.long 0x00 23. " [23] ,Rx FIFO global mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Rx FIFO global mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Rx FIFO global mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Rx FIFO global mask bit 20" "0,1" newline bitfld.long 0x00 19. " [19] ,Rx FIFO global mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Rx FIFO global mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Rx FIFO global mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Rx FIFO global mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Rx FIFO global mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Rx FIFO global mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Rx FIFO global mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Rx FIFO global mask bit 12" "0,1" newline bitfld.long 0x00 11. " [11] ,Rx FIFO global mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Rx FIFO global mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Rx FIFO global mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Rx FIFO global mask bit 8" "0,1" newline bitfld.long 0x00 7. " [7] ,Rx FIFO global mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Rx FIFO global mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Rx FIFO global mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Rx FIFO global mask bit 4" "0,1" newline bitfld.long 0x00 3. " [3] ,Rx FIFO global mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Rx FIFO global mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Rx FIFO global mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Rx FIFO global mask bit 0" "0,1" endif rgroup.long 0x4C++0x03 line.long 0x00 "RXFIR,Rx FIFO Information Register" hexmask.long.word 0x00 0.--8. 1. " IDHIT ,Identifier acceptance filter hit by the received message" if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long 0x50++0x03 line.long 0x00 "CBT,CAN Bit Timing Register" bitfld.long 0x00 31. " BTF ,Bit timing format enable" "Disabled,Enabled" hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,Extended prescaler division factor" bitfld.long 0x00 16.--20. " ERJW ,Extended resync jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--15. " EPROPSEG ,Extended propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 5.--9. " EPSEG1 ,Extended phase segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " EPSEG2 ,Extended phase segment 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else rgroup.long 0x50++0x03 line.long 0x00 "CBT,CAN Bit Timing Register" bitfld.long 0x00 31. " BTF ,Bit timing format enable" "Disabled,Enabled" hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,Extended prescaler division factor" bitfld.long 0x00 16.--20. " ERJW ,Extended resync jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--15. " EPROPSEG ,Extended propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 5.--9. " EPSEG1 ,Extended phase segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " EPSEG2 ,Extended phase segment 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif tree "Rx Individual Mask Registers 0-63" if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x0+0x880)++0x03 line.long 0x00 "RXIMR0,Rx Individual Mask Register 0" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x0+0x880)++0x03 line.long 0x00 "RXIMR0,Rx Individual Mask Register 0" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x4+0x880)++0x03 line.long 0x00 "RXIMR1,Rx Individual Mask Register 1" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x4+0x880)++0x03 line.long 0x00 "RXIMR1,Rx Individual Mask Register 1" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x8+0x880)++0x03 line.long 0x00 "RXIMR2,Rx Individual Mask Register 2" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x8+0x880)++0x03 line.long 0x00 "RXIMR2,Rx Individual Mask Register 2" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0xC+0x880)++0x03 line.long 0x00 "RXIMR3,Rx Individual Mask Register 3" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xC+0x880)++0x03 line.long 0x00 "RXIMR3,Rx Individual Mask Register 3" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x10+0x880)++0x03 line.long 0x00 "RXIMR4,Rx Individual Mask Register 4" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x10+0x880)++0x03 line.long 0x00 "RXIMR4,Rx Individual Mask Register 4" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x14+0x880)++0x03 line.long 0x00 "RXIMR5,Rx Individual Mask Register 5" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x14+0x880)++0x03 line.long 0x00 "RXIMR5,Rx Individual Mask Register 5" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x18+0x880)++0x03 line.long 0x00 "RXIMR6,Rx Individual Mask Register 6" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x18+0x880)++0x03 line.long 0x00 "RXIMR6,Rx Individual Mask Register 6" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x1C+0x880)++0x03 line.long 0x00 "RXIMR7,Rx Individual Mask Register 7" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x1C+0x880)++0x03 line.long 0x00 "RXIMR7,Rx Individual Mask Register 7" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x20+0x880)++0x03 line.long 0x00 "RXIMR8,Rx Individual Mask Register 8" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x20+0x880)++0x03 line.long 0x00 "RXIMR8,Rx Individual Mask Register 8" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x24+0x880)++0x03 line.long 0x00 "RXIMR9,Rx Individual Mask Register 9" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x24+0x880)++0x03 line.long 0x00 "RXIMR9,Rx Individual Mask Register 9" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x28+0x880)++0x03 line.long 0x00 "RXIMR10,Rx Individual Mask Register 10" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x28+0x880)++0x03 line.long 0x00 "RXIMR10,Rx Individual Mask Register 10" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x2C+0x880)++0x03 line.long 0x00 "RXIMR11,Rx Individual Mask Register 11" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x2C+0x880)++0x03 line.long 0x00 "RXIMR11,Rx Individual Mask Register 11" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x30+0x880)++0x03 line.long 0x00 "RXIMR12,Rx Individual Mask Register 12" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x30+0x880)++0x03 line.long 0x00 "RXIMR12,Rx Individual Mask Register 12" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x34+0x880)++0x03 line.long 0x00 "RXIMR13,Rx Individual Mask Register 13" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x34+0x880)++0x03 line.long 0x00 "RXIMR13,Rx Individual Mask Register 13" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x38+0x880)++0x03 line.long 0x00 "RXIMR14,Rx Individual Mask Register 14" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x38+0x880)++0x03 line.long 0x00 "RXIMR14,Rx Individual Mask Register 14" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x3C+0x880)++0x03 line.long 0x00 "RXIMR15,Rx Individual Mask Register 15" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x3C+0x880)++0x03 line.long 0x00 "RXIMR15,Rx Individual Mask Register 15" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x40+0x880)++0x03 line.long 0x00 "RXIMR16,Rx Individual Mask Register 16" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x40+0x880)++0x03 line.long 0x00 "RXIMR16,Rx Individual Mask Register 16" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x44+0x880)++0x03 line.long 0x00 "RXIMR17,Rx Individual Mask Register 17" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x44+0x880)++0x03 line.long 0x00 "RXIMR17,Rx Individual Mask Register 17" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x48+0x880)++0x03 line.long 0x00 "RXIMR18,Rx Individual Mask Register 18" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x48+0x880)++0x03 line.long 0x00 "RXIMR18,Rx Individual Mask Register 18" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x4C+0x880)++0x03 line.long 0x00 "RXIMR19,Rx Individual Mask Register 19" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x4C+0x880)++0x03 line.long 0x00 "RXIMR19,Rx Individual Mask Register 19" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x50+0x880)++0x03 line.long 0x00 "RXIMR20,Rx Individual Mask Register 20" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x50+0x880)++0x03 line.long 0x00 "RXIMR20,Rx Individual Mask Register 20" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x54+0x880)++0x03 line.long 0x00 "RXIMR21,Rx Individual Mask Register 21" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x54+0x880)++0x03 line.long 0x00 "RXIMR21,Rx Individual Mask Register 21" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x58+0x880)++0x03 line.long 0x00 "RXIMR22,Rx Individual Mask Register 22" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x58+0x880)++0x03 line.long 0x00 "RXIMR22,Rx Individual Mask Register 22" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x5C+0x880)++0x03 line.long 0x00 "RXIMR23,Rx Individual Mask Register 23" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x5C+0x880)++0x03 line.long 0x00 "RXIMR23,Rx Individual Mask Register 23" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x60+0x880)++0x03 line.long 0x00 "RXIMR24,Rx Individual Mask Register 24" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x60+0x880)++0x03 line.long 0x00 "RXIMR24,Rx Individual Mask Register 24" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x64+0x880)++0x03 line.long 0x00 "RXIMR25,Rx Individual Mask Register 25" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x64+0x880)++0x03 line.long 0x00 "RXIMR25,Rx Individual Mask Register 25" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x68+0x880)++0x03 line.long 0x00 "RXIMR26,Rx Individual Mask Register 26" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x68+0x880)++0x03 line.long 0x00 "RXIMR26,Rx Individual Mask Register 26" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x6C+0x880)++0x03 line.long 0x00 "RXIMR27,Rx Individual Mask Register 27" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x6C+0x880)++0x03 line.long 0x00 "RXIMR27,Rx Individual Mask Register 27" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x70+0x880)++0x03 line.long 0x00 "RXIMR28,Rx Individual Mask Register 28" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x70+0x880)++0x03 line.long 0x00 "RXIMR28,Rx Individual Mask Register 28" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x74+0x880)++0x03 line.long 0x00 "RXIMR29,Rx Individual Mask Register 29" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x74+0x880)++0x03 line.long 0x00 "RXIMR29,Rx Individual Mask Register 29" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x78+0x880)++0x03 line.long 0x00 "RXIMR30,Rx Individual Mask Register 30" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x78+0x880)++0x03 line.long 0x00 "RXIMR30,Rx Individual Mask Register 30" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x7C+0x880)++0x03 line.long 0x00 "RXIMR31,Rx Individual Mask Register 31" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x7C+0x880)++0x03 line.long 0x00 "RXIMR31,Rx Individual Mask Register 31" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x80+0x880)++0x03 line.long 0x00 "RXIMR32,Rx Individual Mask Register 32" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x80+0x880)++0x03 line.long 0x00 "RXIMR32,Rx Individual Mask Register 32" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x84+0x880)++0x03 line.long 0x00 "RXIMR33,Rx Individual Mask Register 33" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x84+0x880)++0x03 line.long 0x00 "RXIMR33,Rx Individual Mask Register 33" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x88+0x880)++0x03 line.long 0x00 "RXIMR34,Rx Individual Mask Register 34" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x88+0x880)++0x03 line.long 0x00 "RXIMR34,Rx Individual Mask Register 34" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x8C+0x880)++0x03 line.long 0x00 "RXIMR35,Rx Individual Mask Register 35" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x8C+0x880)++0x03 line.long 0x00 "RXIMR35,Rx Individual Mask Register 35" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x90+0x880)++0x03 line.long 0x00 "RXIMR36,Rx Individual Mask Register 36" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x90+0x880)++0x03 line.long 0x00 "RXIMR36,Rx Individual Mask Register 36" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x94+0x880)++0x03 line.long 0x00 "RXIMR37,Rx Individual Mask Register 37" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x94+0x880)++0x03 line.long 0x00 "RXIMR37,Rx Individual Mask Register 37" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x98+0x880)++0x03 line.long 0x00 "RXIMR38,Rx Individual Mask Register 38" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x98+0x880)++0x03 line.long 0x00 "RXIMR38,Rx Individual Mask Register 38" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0x9C+0x880)++0x03 line.long 0x00 "RXIMR39,Rx Individual Mask Register 39" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x9C+0x880)++0x03 line.long 0x00 "RXIMR39,Rx Individual Mask Register 39" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0xA0+0x880)++0x03 line.long 0x00 "RXIMR40,Rx Individual Mask Register 40" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xA0+0x880)++0x03 line.long 0x00 "RXIMR40,Rx Individual Mask Register 40" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0xA4+0x880)++0x03 line.long 0x00 "RXIMR41,Rx Individual Mask Register 41" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xA4+0x880)++0x03 line.long 0x00 "RXIMR41,Rx Individual Mask Register 41" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0xA8+0x880)++0x03 line.long 0x00 "RXIMR42,Rx Individual Mask Register 42" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xA8+0x880)++0x03 line.long 0x00 "RXIMR42,Rx Individual Mask Register 42" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0xAC+0x880)++0x03 line.long 0x00 "RXIMR43,Rx Individual Mask Register 43" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xAC+0x880)++0x03 line.long 0x00 "RXIMR43,Rx Individual Mask Register 43" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0xB0+0x880)++0x03 line.long 0x00 "RXIMR44,Rx Individual Mask Register 44" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xB0+0x880)++0x03 line.long 0x00 "RXIMR44,Rx Individual Mask Register 44" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0xB4+0x880)++0x03 line.long 0x00 "RXIMR45,Rx Individual Mask Register 45" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xB4+0x880)++0x03 line.long 0x00 "RXIMR45,Rx Individual Mask Register 45" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0xB8+0x880)++0x03 line.long 0x00 "RXIMR46,Rx Individual Mask Register 46" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xB8+0x880)++0x03 line.long 0x00 "RXIMR46,Rx Individual Mask Register 46" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0xBC+0x880)++0x03 line.long 0x00 "RXIMR47,Rx Individual Mask Register 47" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xBC+0x880)++0x03 line.long 0x00 "RXIMR47,Rx Individual Mask Register 47" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0xC0+0x880)++0x03 line.long 0x00 "RXIMR48,Rx Individual Mask Register 48" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xC0+0x880)++0x03 line.long 0x00 "RXIMR48,Rx Individual Mask Register 48" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0xC4+0x880)++0x03 line.long 0x00 "RXIMR49,Rx Individual Mask Register 49" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xC4+0x880)++0x03 line.long 0x00 "RXIMR49,Rx Individual Mask Register 49" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0xC8+0x880)++0x03 line.long 0x00 "RXIMR50,Rx Individual Mask Register 50" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xC8+0x880)++0x03 line.long 0x00 "RXIMR50,Rx Individual Mask Register 50" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0xCC+0x880)++0x03 line.long 0x00 "RXIMR51,Rx Individual Mask Register 51" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xCC+0x880)++0x03 line.long 0x00 "RXIMR51,Rx Individual Mask Register 51" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0xD0+0x880)++0x03 line.long 0x00 "RXIMR52,Rx Individual Mask Register 52" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xD0+0x880)++0x03 line.long 0x00 "RXIMR52,Rx Individual Mask Register 52" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0xD4+0x880)++0x03 line.long 0x00 "RXIMR53,Rx Individual Mask Register 53" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xD4+0x880)++0x03 line.long 0x00 "RXIMR53,Rx Individual Mask Register 53" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0xD8+0x880)++0x03 line.long 0x00 "RXIMR54,Rx Individual Mask Register 54" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xD8+0x880)++0x03 line.long 0x00 "RXIMR54,Rx Individual Mask Register 54" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0xDC+0x880)++0x03 line.long 0x00 "RXIMR55,Rx Individual Mask Register 55" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xDC+0x880)++0x03 line.long 0x00 "RXIMR55,Rx Individual Mask Register 55" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0xE0+0x880)++0x03 line.long 0x00 "RXIMR56,Rx Individual Mask Register 56" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xE0+0x880)++0x03 line.long 0x00 "RXIMR56,Rx Individual Mask Register 56" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0xE4+0x880)++0x03 line.long 0x00 "RXIMR57,Rx Individual Mask Register 57" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xE4+0x880)++0x03 line.long 0x00 "RXIMR57,Rx Individual Mask Register 57" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0xE8+0x880)++0x03 line.long 0x00 "RXIMR58,Rx Individual Mask Register 58" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xE8+0x880)++0x03 line.long 0x00 "RXIMR58,Rx Individual Mask Register 58" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0xEC+0x880)++0x03 line.long 0x00 "RXIMR59,Rx Individual Mask Register 59" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xEC+0x880)++0x03 line.long 0x00 "RXIMR59,Rx Individual Mask Register 59" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0xF0+0x880)++0x03 line.long 0x00 "RXIMR60,Rx Individual Mask Register 60" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xF0+0x880)++0x03 line.long 0x00 "RXIMR60,Rx Individual Mask Register 60" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0xF4+0x880)++0x03 line.long 0x00 "RXIMR61,Rx Individual Mask Register 61" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xF4+0x880)++0x03 line.long 0x00 "RXIMR61,Rx Individual Mask Register 61" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0xF8+0x880)++0x03 line.long 0x00 "RXIMR62,Rx Individual Mask Register 62" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xF8+0x880)++0x03 line.long 0x00 "RXIMR62,Rx Individual Mask Register 62" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long (0xFC+0x880)++0x03 line.long 0x00 "RXIMR63,Rx Individual Mask Register 63" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xFC+0x880)++0x03 line.long 0x00 "RXIMR63,Rx Individual Mask Register 63" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif tree.end newline if (((per.l(ad:0x5A8D0000+0x00))&0x50000000)==0x50000000) group.long 0xC00++0x07 line.long 0x00 "FDCTRL,CAN FD Control Register" bitfld.long 0x00 31. " FDRATE ,Bit rate switch enable" "Disabled,Enabled" bitfld.long 0x00 19.--20. " MBDSR1 ,Message buffer data size for region 1" "8 bytes,16 bytes,32 bytes,64 bytes" bitfld.long 0x00 16.--17. " MBDSR0 ,Message buffer data size for region 0" "8 bytes,16 bytes,32 bytes,64 bytes" bitfld.long 0x00 15. " TDCEN ,Transceiver delay compensation enable" "Disabled,Enabled" newline eventfld.long 0x00 14. " TDCFAIL ,Transceiver delay compensation fail" "In range,Out of range" bitfld.long 0x00 8.--12. " TDCOFF ,Transceiver delay compensation offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--5. " TDCVAL ,Transceiver delay compensation value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "FDCBT,CAN FD Bit Timing Register" hexmask.long.word 0x04 20.--29. 1. " FPRESDIV ,Fast prescaler division factor" bitfld.long 0x04 16.--18. " FRJW ,Fast resync jump width" "0,1,2,3,4,5,6,7" bitfld.long 0x04 10.--14. " FPROPSEG ,Fast propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 5.--7. " FPSEG1 ,Fast phase segment 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 0.--2. " FPSEG2 ,Fast phase segment 2" "0,1,2,3,4,5,6,7" else group.long 0xC00++0x03 line.long 0x00 "FDCTRL,CAN FD Control Register" bitfld.long 0x00 31. " FDRATE ,Bit rate switch enable" "Disabled,Enabled" bitfld.long 0x00 19.--20. " MBDSR1 ,Message buffer data size for region 1" "8 bytes,16 bytes,32 bytes,64 bytes" rbitfld.long 0x00 16.--17. " MBDSR0 ,Message buffer data size for region 0" "8 bytes,16 bytes,32 bytes,64 bytes" rbitfld.long 0x00 15. " TDCEN ,Transceiver delay compensation enable" "Disabled,Enabled" newline eventfld.long 0x00 14. " TDCFAIL ,Transceiver delay compensation fail" "In range,Out of range" rbitfld.long 0x00 8.--12. " TDCOFF ,Transceiver delay compensation offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--5. " TDCVAL ,Transceiver delay compensation value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0xC04++0x03 line.long 0x00 "FDCBT,CAN FD Bit Timing Register" hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,Fast prescaler division factor" bitfld.long 0x00 16.--18. " FRJW ,Fast resync jump width" "1,2,3,4,5,6,7,8" bitfld.long 0x00 10.--14. " FPROPSEG ,Fast propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--7. " FPSEG1 ,Fast phase segment 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--2. " FPSEG2 ,Fast phase segment 2" "0,1,2,3,4,5,6,7" endif rgroup.long 0xC08++0x03 line.long 0x00 "FDCRC,CAN FD CRC Register" hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,CRC mailbox number for FD_TXCRC" hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCRC ,Extended transmitted CRC value" width 0x0B tree.end tree "CAN1" base ad:0x5A8E0000 width 10. if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) if (((per.l(ad:0x5A8E0000+0x00))&0x20000000)==0x20000000) if (((per.l(ad:0x5A8E0000+0x00))&0x800)==0x800) if ((per.l(ad:0x5A8E0000)&0x100000)==0x00) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline bitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" newline hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline rbitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" newline hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif else if ((per.l(ad:0x5A8E0000)&0x100000)==0x00) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" bitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline bitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" newline hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" bitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline rbitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" newline hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif endif else if (((per.l(ad:0x5A8E0000+0x00))&0x800)==0x800) if ((per.l(ad:0x5A8E0000)&0x100000)==0x00) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline bitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline rbitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif else if ((per.l(ad:0x5A8E0000)&0x100000)==0x00) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" bitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline bitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" bitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline rbitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif endif endif else if (((per.l(ad:0x5A8E0000+0x00))&0x20000000)==0x20000000) if ((per.l(ad:0x5A8E0000)&0x100000)==0x00) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline bitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" rbitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" rbitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" rbitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" rbitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" rbitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" newline rbitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" rbitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" rbitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" rbitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" newline hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline rbitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" rbitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" rbitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" rbitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" rbitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" rbitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" newline rbitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" rbitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" rbitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" rbitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" newline hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif else if ((per.l(ad:0x5A8E0000)&0x100000)==0x00) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline bitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" rbitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" rbitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" rbitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" rbitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" rbitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline rbitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" rbitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" rbitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline rbitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" rbitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" rbitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" rbitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" rbitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" rbitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline rbitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" rbitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" rbitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif endif endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) if (((per.l(ad:0x5A8E0000+0x00))&0x200000)==0x200000) if ((per.l(ad:0x5A8E0000)&0x80000000)==0x00) group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" bitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" bitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" ",1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" bitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Peripheral,Oscillator" bitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline bitfld.long 0x00 11. " TWRNMSK ,Tx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RWRNMSK ,Rx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline bitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" bitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" bitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" bitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" else group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" bitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" bitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" ",1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Peripheral,Oscillator" bitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline bitfld.long 0x00 11. " TWRNMSK ,Tx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RWRNMSK ,Rx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline bitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" bitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" bitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" bitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" endif else if ((per.l(ad:0x5A8E0000)&0x80000000)==0x00) group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" bitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" bitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" ",1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" bitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Peripheral,Oscillator" bitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline rbitfld.long 0x00 11. " TWRNMSK ,Tx warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 10. " RWRNMSK ,Rx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline bitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" bitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" bitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" bitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" else group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" bitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" bitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" ",1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Peripheral,Oscillator" bitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline rbitfld.long 0x00 11. " TWRNMSK ,Tx warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 10. " RWRNMSK ,Rx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline bitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" bitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" bitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" bitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" endif endif else if (((per.l(ad:0x5A8E0000+0x00))&0x200000)==0x200000) if ((per.l(ad:0x5A8E0000)&0x80000000)==0x00) group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" rbitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" rbitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" ",1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" bitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Peripheral,Oscillator" rbitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline bitfld.long 0x00 11. " TWRNMSK ,Tx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RWRNMSK ,Rx warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline rbitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" rbitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" rbitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" rbitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" else group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" rbitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" rbitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" ",1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Peripheral,Oscillator" rbitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline bitfld.long 0x00 11. " TWRNMSK ,Tx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RWRNMSK ,Rx warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline rbitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" rbitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" rbitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" rbitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" endif else if ((per.l(ad:0x5A8E0000)&0x80000000)==0x00) group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" rbitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" rbitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" ",1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" bitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Peripheral,Oscillator" rbitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline rbitfld.long 0x00 11. " TWRNMSK ,Tx warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 10. " RWRNMSK ,Rx warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline rbitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" rbitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" rbitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" rbitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" else group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" rbitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" rbitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" ",1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Peripheral,Oscillator" rbitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline rbitfld.long 0x00 11. " TWRNMSK ,Tx warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 10. " RWRNMSK ,Rx warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline rbitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" rbitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" rbitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" rbitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" endif endif endif group.long 0x08++0x03 line.long 0x00 "TIMER,Free Running Timer" hexmask.long.word 0x00 0.--15. 1. " TIMER ,Timer value" if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long 0x10++0x0F line.long 0x00 "RXMGMASK,Rx Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG[31] ,Mailbox filter 31 mask" "0,1" bitfld.long 0x00 30. " [30] ,Mailbox filter 30 mask" "0,1" bitfld.long 0x00 29. " [29] ,Mailbox filter 29 mask" "0,1" bitfld.long 0x00 28. " [28] ,Mailbox filter 28 mask" "0,1" newline bitfld.long 0x00 27. " [27] ,Mailbox filter 27 mask" "0,1" bitfld.long 0x00 26. " [26] ,Mailbox filter 26 mask" "0,1" bitfld.long 0x00 25. " [25] ,Mailbox filter 25 mask" "0,1" bitfld.long 0x00 24. " [24] ,Mailbox filter 24 mask" "0,1" newline bitfld.long 0x00 23. " [23] ,Mailbox filter 23 mask" "0,1" bitfld.long 0x00 22. " [22] ,Mailbox filter 22 mask" "0,1" bitfld.long 0x00 21. " [21] ,Mailbox filter 21 mask" "0,1" bitfld.long 0x00 20. " [20] ,Mailbox filter 20 mask" "0,1" newline bitfld.long 0x00 19. " [19] ,Mailbox filter 19 mask" "0,1" bitfld.long 0x00 18. " [18] ,Mailbox filter 18 mask" "0,1" bitfld.long 0x00 17. " [17] ,Mailbox filter 17 mask" "0,1" bitfld.long 0x00 16. " [16] ,Mailbox filter 16 mask" "0,1" newline bitfld.long 0x00 15. " [15] ,Mailbox filter 15 mask" "0,1" bitfld.long 0x00 14. " [14] ,Mailbox filter 14 mask" "0,1" bitfld.long 0x00 13. " [13] ,Mailbox filter 13 mask" "0,1" bitfld.long 0x00 12. " [12] ,Mailbox filter 12 mask" "0,1" newline bitfld.long 0x00 11. " [11] ,Mailbox filter 11 mask" "0,1" bitfld.long 0x00 10. " [10] ,Mailbox filter 10 mask" "0,1" bitfld.long 0x00 9. " [9] ,Mailbox filter 9 mask" "0,1" bitfld.long 0x00 8. " [8] ,Mailbox filter 8 mask" "0,1" newline bitfld.long 0x00 7. " [7] ,Mailbox filter 7 mask" "0,1" bitfld.long 0x00 6. " [6] ,Mailbox filter 6 mask" "0,1" bitfld.long 0x00 5. " [5] ,Mailbox filter 5 mask" "0,1" bitfld.long 0x00 4. " [4] ,Mailbox filter 4 mask" "0,1" newline bitfld.long 0x00 3. " [3] ,Mailbox filter 3 mask" "0,1" bitfld.long 0x00 2. " [2] ,Mailbox filter 2 mask" "0,1" bitfld.long 0x00 1. " [1] ,Mailbox filter 1 mask" "0,1" bitfld.long 0x00 0. " [0] ,Mailbox filter 0 mask" "0,1" line.long 0x04 "RX14MASK,Rx Buffer 14 Mask Register" bitfld.long 0x04 31. " RX14M[31] ,Rx buffer 14 mask bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Rx buffer 14 mask bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Rx buffer 14 mask bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Rx buffer 14 mask bit 28" "0,1" newline bitfld.long 0x04 27. " [27] ,Rx buffer 14 mask bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Rx buffer 14 mask bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Rx buffer 14 mask bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Rx buffer 14 mask bit 24" "0,1" newline bitfld.long 0x04 23. " [23] ,Rx buffer 14 mask bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Rx buffer 14 mask bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Rx buffer 14 mask bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Rx buffer 14 mask bit 20" "0,1" newline bitfld.long 0x04 19. " [19] ,Rx buffer 14 mask bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Rx buffer 14 mask bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Rx buffer 14 mask bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Rx buffer 14 mask bit 16" "0,1" newline bitfld.long 0x04 15. " [15] ,Rx buffer 14 mask bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Rx buffer 14 mask bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Rx buffer 14 mask bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Rx buffer 14 mask bit 12" "0,1" newline bitfld.long 0x04 11. " [11] ,Rx buffer 14 mask bit 11" "0,1" bitfld.long 0x04 10. " [10] ,Rx buffer 14 mask bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Rx buffer 14 mask bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Rx buffer 14 mask bit 8" "0,1" newline bitfld.long 0x04 7. " [7] ,Rx buffer 14 mask bit 7" "0,1" bitfld.long 0x04 6. " [6] ,Rx buffer 14 mask bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Rx buffer 14 mask bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Rx buffer 14 mask bit 4" "0,1" newline bitfld.long 0x04 3. " [3] ,Rx buffer 14 mask bit 3" "0,1" bitfld.long 0x04 2. " [2] ,Rx buffer 14 mask bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Rx buffer 14 mask bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Rx buffer 14 mask bit 0" "0,1" line.long 0x08 "RX15MASK,Rx Buffer 15 Mask Register" bitfld.long 0x08 31. " RX15M[31] ,Rx buffer 15 mask bit 31" "0,1" bitfld.long 0x08 30. " [30] ,Rx buffer 15 mask bit 30" "0,1" bitfld.long 0x08 29. " [29] ,Rx buffer 15 mask bit 29" "0,1" bitfld.long 0x08 28. " [28] ,Rx buffer 15 mask bit 28" "0,1" newline bitfld.long 0x08 27. " [27] ,Rx buffer 15 mask bit 27" "0,1" bitfld.long 0x08 26. " [26] ,Rx buffer 15 mask bit 26" "0,1" bitfld.long 0x08 25. " [25] ,Rx buffer 15 mask bit 25" "0,1" bitfld.long 0x08 24. " [24] ,Rx buffer 15 mask bit 24" "0,1" newline bitfld.long 0x08 23. " [23] ,Rx buffer 15 mask bit 23" "0,1" bitfld.long 0x08 22. " [22] ,Rx buffer 15 mask bit 22" "0,1" bitfld.long 0x08 21. " [21] ,Rx buffer 15 mask bit 21" "0,1" bitfld.long 0x08 20. " [20] ,Rx buffer 15 mask bit 20" "0,1" newline bitfld.long 0x08 19. " [19] ,Rx buffer 15 mask bit 19" "0,1" bitfld.long 0x08 18. " [18] ,Rx buffer 15 mask bit 18" "0,1" bitfld.long 0x08 17. " [17] ,Rx buffer 15 mask bit 17" "0,1" bitfld.long 0x08 16. " [16] ,Rx buffer 15 mask bit 16" "0,1" newline bitfld.long 0x08 15. " [15] ,Rx buffer 15 mask bit 15" "0,1" bitfld.long 0x08 14. " [14] ,Rx buffer 15 mask bit 14" "0,1" bitfld.long 0x08 13. " [13] ,Rx buffer 15 mask bit 13" "0,1" bitfld.long 0x08 12. " [12] ,Rx buffer 15 mask bit 12" "0,1" newline bitfld.long 0x08 11. " [11] ,Rx buffer 15 mask bit 11" "0,1" bitfld.long 0x08 10. " [10] ,Rx buffer 15 mask bit 10" "0,1" bitfld.long 0x08 9. " [9] ,Rx buffer 15 mask bit 9" "0,1" bitfld.long 0x08 8. " [8] ,Rx buffer 15 mask bit 8" "0,1" newline bitfld.long 0x08 7. " [7] ,Rx buffer 15 mask bit 7" "0,1" bitfld.long 0x08 6. " [6] ,Rx buffer 15 mask bit 6" "0,1" bitfld.long 0x08 5. " [5] ,Rx buffer 15 mask bit 5" "0,1" bitfld.long 0x08 4. " [4] ,Rx buffer 15 mask bit 4" "0,1" newline bitfld.long 0x08 3. " [3] ,Rx buffer 15 mask bit 3" "0,1" bitfld.long 0x08 2. " [2] ,Rx buffer 15 mask bit 2" "0,1" bitfld.long 0x08 1. " [1] ,Rx buffer 15 mask bit 1" "0,1" bitfld.long 0x08 0. " [0] ,Rx buffer 15 mask bit 0" "0,1" line.long 0x0C "ECR,Error Counter Register" hexmask.long.byte 0x0C 24.--31. 1. " RXERRCNT_FAST ,Receive error counter for fast bit" hexmask.long.byte 0x0C 16.--23. 1. " TXERRCNT_FAST ,Transmit error counter for fast bits" hexmask.long.byte 0x0C 8.--15. 1. " RXERRCNT ,Receive error counter" hexmask.long.byte 0x0C 0.--7. 1. " TXERRCNT ,Transmit error counter" else rgroup.long 0x10++0x0F line.long 0x00 "RXMGMASK,Rx Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG[31] ,Mailbox filter 31 mask" "0,1" bitfld.long 0x00 30. " [30] ,Mailbox filter 30 mask" "0,1" bitfld.long 0x00 29. " [29] ,Mailbox filter 29 mask" "0,1" bitfld.long 0x00 28. " [28] ,Mailbox filter 28 mask" "0,1" newline bitfld.long 0x00 27. " [27] ,Mailbox filter 27 mask" "0,1" bitfld.long 0x00 26. " [26] ,Mailbox filter 26 mask" "0,1" bitfld.long 0x00 25. " [25] ,Mailbox filter 25 mask" "0,1" bitfld.long 0x00 24. " [24] ,Mailbox filter 24 mask" "0,1" newline bitfld.long 0x00 23. " [23] ,Mailbox filter 23 mask" "0,1" bitfld.long 0x00 22. " [22] ,Mailbox filter 22 mask" "0,1" bitfld.long 0x00 21. " [21] ,Mailbox filter 21 mask" "0,1" bitfld.long 0x00 20. " [20] ,Mailbox filter 20 mask" "0,1" newline bitfld.long 0x00 19. " [19] ,Mailbox filter 19 mask" "0,1" bitfld.long 0x00 18. " [18] ,Mailbox filter 18 mask" "0,1" bitfld.long 0x00 17. " [17] ,Mailbox filter 17 mask" "0,1" bitfld.long 0x00 16. " [16] ,Mailbox filter 16 mask" "0,1" newline bitfld.long 0x00 15. " [15] ,Mailbox filter 15 mask" "0,1" bitfld.long 0x00 14. " [14] ,Mailbox filter 14 mask" "0,1" bitfld.long 0x00 13. " [13] ,Mailbox filter 13 mask" "0,1" bitfld.long 0x00 12. " [12] ,Mailbox filter 12 mask" "0,1" newline bitfld.long 0x00 11. " [11] ,Mailbox filter 11 mask" "0,1" bitfld.long 0x00 10. " [10] ,Mailbox filter 10 mask" "0,1" bitfld.long 0x00 9. " [9] ,Mailbox filter 9 mask" "0,1" bitfld.long 0x00 8. " [8] ,Mailbox filter 8 mask" "0,1" newline bitfld.long 0x00 7. " [7] ,Mailbox filter 7 mask" "0,1" bitfld.long 0x00 6. " [6] ,Mailbox filter 6 mask" "0,1" bitfld.long 0x00 5. " [5] ,Mailbox filter 5 mask" "0,1" bitfld.long 0x00 4. " [4] ,Mailbox filter 4 mask" "0,1" newline bitfld.long 0x00 3. " [3] ,Mailbox filter 3 mask" "0,1" bitfld.long 0x00 2. " [2] ,Mailbox filter 2 mask" "0,1" bitfld.long 0x00 1. " [1] ,Mailbox filter 1 mask" "0,1" bitfld.long 0x00 0. " [0] ,Mailbox filter 0 mask" "0,1" line.long 0x04 "RX14MASK,Rx Buffer 14 Mask Register" bitfld.long 0x04 31. " RX14M[31] ,Mailbox 14 filter 31 mask" "0,1" bitfld.long 0x04 30. " [30] ,Mailbox 14 filter 30 mask" "0,1" bitfld.long 0x04 29. " [29] ,Mailbox 14 filter 29 mask" "0,1" bitfld.long 0x04 28. " [28] ,Mailbox 14 filter 28 mask" "0,1" newline bitfld.long 0x04 27. " [27] ,Mailbox 14 filter 27 mask" "0,1" bitfld.long 0x04 26. " [26] ,Mailbox 14 filter 26 mask" "0,1" bitfld.long 0x04 25. " [25] ,Mailbox 14 filter 25 mask" "0,1" bitfld.long 0x04 24. " [24] ,Mailbox 14 filter 24 mask" "0,1" newline bitfld.long 0x04 23. " [23] ,Mailbox 14 filter 23 mask" "0,1" bitfld.long 0x04 22. " [22] ,Mailbox 14 filter 22 mask" "0,1" bitfld.long 0x04 21. " [21] ,Mailbox 14 filter 21 mask" "0,1" bitfld.long 0x04 20. " [20] ,Mailbox 14 filter 20 mask" "0,1" newline bitfld.long 0x04 19. " [19] ,Mailbox 14 filter 19 mask" "0,1" bitfld.long 0x04 18. " [18] ,Mailbox 14 filter 18 mask" "0,1" bitfld.long 0x04 17. " [17] ,Mailbox 14 filter 17 mask" "0,1" bitfld.long 0x04 16. " [16] ,Mailbox 14 filter 16 mask" "0,1" newline bitfld.long 0x04 15. " [15] ,Mailbox 14 filter 15 mask" "0,1" bitfld.long 0x04 14. " [14] ,Mailbox 14 filter 14 mask" "0,1" bitfld.long 0x04 13. " [13] ,Mailbox 14 filter 13 mask" "0,1" bitfld.long 0x04 12. " [12] ,Mailbox 14 filter 12 mask" "0,1" newline bitfld.long 0x04 11. " [11] ,Mailbox 14 filter 11 mask" "0,1" bitfld.long 0x04 10. " [10] ,Mailbox 14 filter 10 mask" "0,1" bitfld.long 0x04 9. " [9] ,Mailbox 14 filter 9 mask" "0,1" bitfld.long 0x04 8. " [8] ,Mailbox 14 filter 8 mask" "0,1" newline bitfld.long 0x04 7. " [7] ,Mailbox 14 filter 7 mask" "0,1" bitfld.long 0x04 6. " [6] ,Mailbox 14 filter 6 mask" "0,1" bitfld.long 0x04 5. " [5] ,Mailbox 14 filter 5 mask" "0,1" bitfld.long 0x04 4. " [4] ,Mailbox 14 filter 4 mask" "0,1" newline bitfld.long 0x04 3. " [3] ,Mailbox 14 filter 3 mask" "0,1" bitfld.long 0x04 2. " [2] ,Mailbox 14 filter 2 mask" "0,1" bitfld.long 0x04 1. " [1] ,Mailbox 14 filter 1 mask" "0,1" bitfld.long 0x04 0. " [0] ,Mailbox 14 filter 0 mask" "0,1" line.long 0x08 "RX15MASK,Rx Buffer 15 Mask Register" bitfld.long 0x08 31. " RX15M[31] ,Mailbox 15 filter 31 mask" "0,1" bitfld.long 0x08 30. " [30] ,Mailbox 15 filter 30 mask" "0,1" bitfld.long 0x08 29. " [29] ,Mailbox 15 filter 29 mask" "0,1" bitfld.long 0x08 28. " [28] ,Mailbox 15 filter 28 mask" "0,1" newline bitfld.long 0x08 27. " [27] ,Mailbox 15 filter 27 mask" "0,1" bitfld.long 0x08 26. " [26] ,Mailbox 15 filter 26 mask" "0,1" bitfld.long 0x08 25. " [25] ,Mailbox 15 filter 25 mask" "0,1" bitfld.long 0x08 24. " [24] ,Mailbox 15 filter 24 mask" "0,1" newline bitfld.long 0x08 23. " [23] ,Mailbox 15 filter 23 mask" "0,1" bitfld.long 0x08 22. " [22] ,Mailbox 15 filter 22 mask" "0,1" bitfld.long 0x08 21. " [21] ,Mailbox 15 filter 21 mask" "0,1" bitfld.long 0x08 20. " [20] ,Mailbox 15 filter 20 mask" "0,1" newline bitfld.long 0x08 19. " [19] ,Mailbox 15 filter 19 mask" "0,1" bitfld.long 0x08 18. " [18] ,Mailbox 15 filter 18 mask" "0,1" bitfld.long 0x08 17. " [17] ,Mailbox 15 filter 17 mask" "0,1" bitfld.long 0x08 16. " [16] ,Mailbox 15 filter 16 mask" "0,1" newline bitfld.long 0x08 15. " [15] ,Mailbox 15 filter 15 mask" "0,1" bitfld.long 0x08 14. " [14] ,Mailbox 15 filter 14 mask" "0,1" bitfld.long 0x08 13. " [13] ,Mailbox 15 filter 13 mask" "0,1" bitfld.long 0x08 12. " [12] ,Mailbox 15 filter 12 mask" "0,1" newline bitfld.long 0x08 11. " [11] ,Mailbox 15 filter 11 mask" "0,1" bitfld.long 0x08 10. " [10] ,Mailbox 15 filter 10 mask" "0,1" bitfld.long 0x08 9. " [9] ,Mailbox 15 filter 9 mask" "0,1" bitfld.long 0x08 8. " [8] ,Mailbox 15 filter 8 mask" "0,1" newline bitfld.long 0x08 7. " [7] ,Mailbox 15 filter 7 mask" "0,1" bitfld.long 0x08 6. " [6] ,Mailbox 15 filter 6 mask" "0,1" bitfld.long 0x08 5. " [5] ,Mailbox 15 filter 5 mask" "0,1" bitfld.long 0x08 4. " [4] ,Mailbox 15 filter 4 mask" "0,1" newline bitfld.long 0x08 3. " [3] ,Mailbox 15 filter 3 mask" "0,1" bitfld.long 0x08 2. " [2] ,Mailbox 15 filter 2 mask" "0,1" bitfld.long 0x08 1. " [1] ,Mailbox 15 filter 1 mask" "0,1" bitfld.long 0x08 0. " [0] ,Mailbox 15 filter 0 mask" "0,1" line.long 0x0C "ECR,Error Counter Register" hexmask.long.byte 0x0C 24.--31. 1. " RXERRCNT_FAST ,Receive error counter for fast bit" hexmask.long.byte 0x0C 16.--23. 1. " TXERRCNT_FAST ,Transmit error counter for fast bits" hexmask.long.byte 0x0C 8.--15. 1. " RXERRCNT ,Receive error counter" hexmask.long.byte 0x0C 0.--7. 1. " TXERRCNT ,Transmit error counter" endif newline hgroup.long 0x20++0x03 hide.long 0x00 "ESR1,Error And Status Register 1" in newline group.long 0x24++0x0B line.long 0x00 "IMASK2,Interrupt Mask Register 2" bitfld.long 0x00 31. " BUF[63]TO32M ,Buffer MB63 mask" "Disabled,Enabled" bitfld.long 0x00 30. " [62] ,Buffer MB62 mask" "Disabled,Enabled" bitfld.long 0x00 29. " [61] ,Buffer MB61 mask" "Disabled,Enabled" bitfld.long 0x00 28. " [60] ,Buffer MB60 mask" "Disabled,Enabled" newline bitfld.long 0x00 27. " [59] ,Buffer MB59 mask" "Disabled,Enabled" bitfld.long 0x00 26. " [58] ,Buffer MB58 mask" "Disabled,Enabled" bitfld.long 0x00 25. " [57] ,Buffer MB57 mask" "Disabled,Enabled" bitfld.long 0x00 24. " [56] ,Buffer MB56 mask" "Disabled,Enabled" newline bitfld.long 0x00 23. " [55] ,Buffer MB55 mask" "Disabled,Enabled" bitfld.long 0x00 22. " [54] ,Buffer MB54 mask" "Disabled,Enabled" bitfld.long 0x00 21. " [53] ,Buffer MB53 mask" "Disabled,Enabled" bitfld.long 0x00 20. " [52] ,Buffer MB52 mask" "Disabled,Enabled" newline bitfld.long 0x00 19. " [51] ,Buffer MB51 mask" "Disabled,Enabled" bitfld.long 0x00 18. " [50] ,Buffer MB50 mask" "Disabled,Enabled" bitfld.long 0x00 17. " [49] ,Buffer MB49 mask" "Disabled,Enabled" bitfld.long 0x00 16. " [48] ,Buffer MB48 mask" "Disabled,Enabled" newline bitfld.long 0x00 15. " [47] ,Buffer MB47 mask" "Disabled,Enabled" bitfld.long 0x00 14. " [46] ,Buffer MB46 mask" "Disabled,Enabled" bitfld.long 0x00 13. " [45] ,Buffer MB45 mask" "Disabled,Enabled" bitfld.long 0x00 12. " [44] ,Buffer MB44 mask" "Disabled,Enabled" newline bitfld.long 0x00 11. " [43] ,Buffer MB43 mask" "Disabled,Enabled" bitfld.long 0x00 10. " [42] ,Buffer MB42 mask" "Disabled,Enabled" bitfld.long 0x00 9. " [41] ,Buffer MB41 mask" "Disabled,Enabled" bitfld.long 0x00 8. " [40] ,Buffer MB40 mask" "Disabled,Enabled" newline bitfld.long 0x00 7. " [39] ,Buffer MB39 mask" "Disabled,Enabled" bitfld.long 0x00 6. " [38] ,Buffer MB38 mask" "Disabled,Enabled" bitfld.long 0x00 5. " [37] ,Buffer MB37 mask" "Disabled,Enabled" bitfld.long 0x00 4. " [36] ,Buffer MB36 mask" "Disabled,Enabled" newline bitfld.long 0x00 3. " [35] ,Buffer MB35 mask" "Disabled,Enabled" bitfld.long 0x00 2. " [34] ,Buffer MB34 mask" "Disabled,Enabled" bitfld.long 0x00 1. " [33] ,Buffer MB33 mask" "Disabled,Enabled" bitfld.long 0x00 0. " [32] ,Buffer MB32 mask" "Disabled,Enabled" line.long 0x04 "IMASK1,Interrupt Masks Register 1" bitfld.long 0x04 31. " BUF[31]TO0M ,Buffer MB31 mask" "Disabled,Enabled" bitfld.long 0x04 30. " [30] ,Buffer MB30 mask" "Disabled,Enabled" bitfld.long 0x04 29. " [29] ,Buffer MB29 mask" "Disabled,Enabled" bitfld.long 0x04 28. " [28] ,Buffer MB28 mask" "Disabled,Enabled" newline bitfld.long 0x04 27. " [27] ,Buffer MB27 mask" "Disabled,Enabled" bitfld.long 0x04 26. " [26] ,Buffer MB26 mask" "Disabled,Enabled" bitfld.long 0x04 25. " [25] ,Buffer MB25 mask" "Disabled,Enabled" bitfld.long 0x04 24. " [24] ,Buffer MB24 mask" "Disabled,Enabled" newline bitfld.long 0x04 23. " [23] ,Buffer MB23 mask" "Disabled,Enabled" bitfld.long 0x04 22. " [22] ,Buffer MB22 mask" "Disabled,Enabled" bitfld.long 0x04 21. " [21] ,Buffer MB21 mask" "Disabled,Enabled" bitfld.long 0x04 20. " [20] ,Buffer MB20 mask" "Disabled,Enabled" newline bitfld.long 0x04 19. " [19] ,Buffer MB19 mask" "Disabled,Enabled" bitfld.long 0x04 18. " [18] ,Buffer MB18 mask" "Disabled,Enabled" bitfld.long 0x04 17. " [17] ,Buffer MB17 mask" "Disabled,Enabled" bitfld.long 0x04 16. " [16] ,Buffer MB16 mask" "Disabled,Enabled" newline bitfld.long 0x04 15. " [15] ,Buffer MB15 mask" "Disabled,Enabled" bitfld.long 0x04 14. " [14] ,Buffer MB14 mask" "Disabled,Enabled" bitfld.long 0x04 13. " [13] ,Buffer MB13 mask" "Disabled,Enabled" bitfld.long 0x04 12. " [12] ,Buffer MB12 mask" "Disabled,Enabled" newline bitfld.long 0x04 11. " [11] ,Buffer MB11 mask" "Disabled,Enabled" bitfld.long 0x04 10. " [10] ,Buffer MB10 mask" "Disabled,Enabled" bitfld.long 0x04 9. " [9] ,Buffer MB9 mask" "Disabled,Enabled" bitfld.long 0x04 8. " [8] ,Buffer MB8 mask" "Disabled,Enabled" newline bitfld.long 0x04 7. " [7] ,Buffer MB7 mask" "Disabled,Enabled" bitfld.long 0x04 6. " [6] ,Buffer MB6 mask" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,Buffer MB5 mask" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,Buffer MB4 mask" "Disabled,Enabled" newline bitfld.long 0x04 3. " [3] ,Buffer MB3 mask" "Disabled,Enabled" bitfld.long 0x04 2. " [2] ,Buffer MB2 mask" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,Buffer MB1 mask" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,Buffer MB0 mask" "Disabled,Enabled" line.long 0x08 "IFLAG2,Interrupt Flags 2 Register" eventfld.long 0x08 31. " BUF[63]TO32I ,Buffer MB63 interrupt" "Not occurred,Occurred" eventfld.long 0x08 30. " [62] ,Buffer MB62 interrupt" "Not occurred,Occurred" eventfld.long 0x08 29. " [61] ,Buffer MB61 interrupt" "Not occurred,Occurred" eventfld.long 0x08 28. " [60] ,Buffer MB60 interrupt" "Not occurred,Occurred" newline eventfld.long 0x08 27. " [59] ,Buffer MB59 interrupt" "Not occurred,Occurred" eventfld.long 0x08 26. " [58] ,Buffer MB58 interrupt" "Not occurred,Occurred" eventfld.long 0x08 25. " [57] ,Buffer MB57 interrupt" "Not occurred,Occurred" eventfld.long 0x08 24. " [56] ,Buffer MB56 interrupt" "Not occurred,Occurred" newline eventfld.long 0x08 23. " [55] ,Buffer MB55 interrupt" "Not occurred,Occurred" eventfld.long 0x08 22. " [54] ,Buffer MB54 interrupt" "Not occurred,Occurred" eventfld.long 0x08 21. " [53] ,Buffer MB53 interrupt" "Not occurred,Occurred" eventfld.long 0x08 20. " [52] ,Buffer MB52 interrupt" "Not occurred,Occurred" newline eventfld.long 0x08 19. " [51] ,Buffer MB51 interrupt" "Not occurred,Occurred" eventfld.long 0x08 18. " [50] ,Buffer MB50 interrupt" "Not occurred,Occurred" eventfld.long 0x08 17. " [49] ,Buffer MB49 interrupt" "Not occurred,Occurred" eventfld.long 0x08 16. " [48] ,Buffer MB48 interrupt" "Not occurred,Occurred" newline eventfld.long 0x08 15. " [47] ,Buffer MB47 interrupt" "Not occurred,Occurred" eventfld.long 0x08 14. " [46] ,Buffer MB46 interrupt" "Not occurred,Occurred" eventfld.long 0x08 13. " [45] ,Buffer MB45 interrupt" "Not occurred,Occurred" eventfld.long 0x08 12. " [44] ,Buffer MB44 interrupt" "Not occurred,Occurred" newline eventfld.long 0x08 11. " [43] ,Buffer MB43 interrupt" "Not occurred,Occurred" eventfld.long 0x08 10. " [42] ,Buffer MB42 interrupt" "Not occurred,Occurred" eventfld.long 0x08 9. " [41] ,Buffer MB41 interrupt" "Not occurred,Occurred" eventfld.long 0x08 8. " [40] ,Buffer MB40 interrupt" "Not occurred,Occurred" newline eventfld.long 0x08 7. " [39] ,Buffer MB39 interrupt" "Not occurred,Occurred" eventfld.long 0x08 6. " [38] ,Buffer MB38 interrupt" "Not occurred,Occurred" eventfld.long 0x08 5. " [37] ,Buffer MB37 interrupt" "Not occurred,Occurred" eventfld.long 0x08 4. " [36] ,Buffer MB36 interrupt" "Not occurred,Occurred" newline eventfld.long 0x08 3. " [35] ,Buffer MB35 interrupt" "Not occurred,Occurred" eventfld.long 0x08 2. " [34] ,Buffer MB34 interrupt" "Not occurred,Occurred" eventfld.long 0x08 1. " [33] ,Buffer MB33 interrupt" "Not occurred,Occurred" eventfld.long 0x08 0. " [32] ,Buffer MB32 interrupt" "Not occurred,Occurred" if (((per.l(ad:0x5A8E0000))&0x20000000)==0x00) group.long 0x30++0x03 line.long 0x00 "IFLAG1,Interrupt Flags 1 Register" eventfld.long 0x00 31. " BUF[31]I ,Buffer MB 31 interrupt" "Not occurred,Occurred" eventfld.long 0x00 30. " [30] ,Buffer MB30 interrupt" "Not occurred,Occurred" eventfld.long 0x00 29. " [29] ,Buffer MB29 interrupt" "Not occurred,Occurred" eventfld.long 0x00 28. " [28] ,Buffer MB28 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 27. " [27] ,Buffer MB27 interrupt" "Not occurred,Occurred" eventfld.long 0x00 26. " [26] ,Buffer MB26 interrupt" "Not occurred,Occurred" eventfld.long 0x00 25. " [25] ,Buffer MB25 interrupt" "Not occurred,Occurred" eventfld.long 0x00 24. " [24] ,Buffer MB24 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 23. " [23] ,Buffer MB23 interrupt" "Not occurred,Occurred" eventfld.long 0x00 22. " [22] ,Buffer MB22 interrupt" "Not occurred,Occurred" eventfld.long 0x00 21. " [21] ,Buffer MB21 interrupt" "Not occurred,Occurred" eventfld.long 0x00 20. " [20] ,Buffer MB20 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 19. " [19] ,Buffer MB19 interrupt" "Not occurred,Occurred" eventfld.long 0x00 18. " [18] ,Buffer MB18 interrupt" "Not occurred,Occurred" eventfld.long 0x00 17. " [17] ,Buffer MB17 interrupt" "Not occurred,Occurred" eventfld.long 0x00 16. " [16] ,Buffer MB16 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 15. " [15] ,Buffer MB15 interrupt" "Not occurred,Occurred" eventfld.long 0x00 14. " [14] ,Buffer MB14 interrupt" "Not occurred,Occurred" eventfld.long 0x00 13. " [13] ,Buffer MB13 interrupt" "Not occurred,Occurred" eventfld.long 0x00 12. " [12] ,Buffer MB12 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 11. " [11] ,Buffer MB11 interrupt" "Not occurred,Occurred" eventfld.long 0x00 10. " [10] ,Buffer MB10 interrupt" "Not occurred,Occurred" eventfld.long 0x00 9. " [9] ,Buffer MB9 interrupt" "Not occurred,Occurred" eventfld.long 0x00 8. " [8] ,Buffer MB8 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 7. " [7] ,Buffer MB7 interrupt" "Not occurred,Occurred" eventfld.long 0x00 6. " [6] ,Buffer MB6 interrupt" "Not occurred,Occurred" eventfld.long 0x00 5. " [5] ,Buffer MB5 interrupt" "Not occurred,Occurred" eventfld.long 0x00 4. " [4] ,Buffer MB4 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 3. " [3] ,Buffer MB3 interrupt" "Not occurred,Occurred" eventfld.long 0x00 2. " [2] ,Buffer MB2 interrupt" "Not occurred,Occurred" eventfld.long 0x00 1. " [1] ,Buffer MB1 interrupt" "Not occurred,Occurred" eventfld.long 0x00 0. " [0] ,Buffer MB0 interrupt" "Not occurred,Occurred" else group.long 0x30++0x03 line.long 0x00 "IFLAG1,Interrupt Flags 1 Register" eventfld.long 0x00 31. " BUF[31]I ,Buffer MB31 interrupt" "Not occurred,Occurred" eventfld.long 0x00 30. " [30] ,Buffer MB30 interrupt" "Not occurred,Occurred" eventfld.long 0x00 29. " [29] ,Buffer MB29 interrupt" "Not occurred,Occurred" eventfld.long 0x00 28. " [28] ,Buffer MB28 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 27. " [27] ,Buffer MB27 interrupt" "Not occurred,Occurred" eventfld.long 0x00 26. " [26] ,Buffer MB26 interrupt" "Not occurred,Occurred" eventfld.long 0x00 25. " [25] ,Buffer MB25 interrupt" "Not occurred,Occurred" eventfld.long 0x00 24. " [24] ,Buffer MB24 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 23. " [23] ,Buffer MB23 interrupt" "Not occurred,Occurred" eventfld.long 0x00 22. " [22] ,Buffer MB22 interrupt" "Not occurred,Occurred" eventfld.long 0x00 21. " [21] ,Buffer MB21 interrupt" "Not occurred,Occurred" eventfld.long 0x00 20. " [20] ,Buffer MB20 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 19. " [19] ,Buffer MB19 interrupt" "Not occurred,Occurred" eventfld.long 0x00 18. " [18] ,Buffer MB18 interrupt" "Not occurred,Occurred" eventfld.long 0x00 17. " [17] ,Buffer MB17 interrupt" "Not occurred,Occurred" eventfld.long 0x00 16. " [16] ,Buffer MB16 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 15. " [15] ,Buffer MB15 interrupt" "Not occurred,Occurred" eventfld.long 0x00 14. " [14] ,Buffer MB14 interrupt" "Not occurred,Occurred" eventfld.long 0x00 13. " [13] ,Buffer MB13 interrupt" "Not occurred,Occurred" eventfld.long 0x00 12. " [12] ,Buffer MB12 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 11. " [11] ,Buffer MB11 interrupt" "Not occurred,Occurred" eventfld.long 0x00 10. " [10] ,Buffer MB10 interrupt" "Not occurred,Occurred" eventfld.long 0x00 9. " [9] ,Buffer MB9 interrupt" "Not occurred,Occurred" eventfld.long 0x00 8. " [8] ,Buffer MB8 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 7. " [7] ,Rx FIFO overflow" "No overflow,Overflow" eventfld.long 0x00 6. " [6] ,Rx FIFO almost full warning" "< 5 unread messages in FIFO,> 5 unread messages in FIFO" eventfld.long 0x00 5. " [5] ,Least one frame is available to be read from the FIFO" "Not available,Available" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long 0x34++0x03 line.long 0x00 "CTRL2,Control 2 Register" bitfld.long 0x00 31. " ERRMSK_FAST ,Error interrupt mask for errors detected in the data phase of fast CAN FD frames" "Disabled,Enabled" bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Disabled,Enabled" bitfld.long 0x00 24.--27. " RFFN ,Number of Rx FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128,?..." bitfld.long 0x00 19.--23. " TASD ,Tx arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "Rx FIFO first,Mailboxes first" bitfld.long 0x00 17. " RRS ,Remote request storing" "Remote response generated,Remote request stored" bitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for Rx mailboxes" "Disabled,Enabled" newline bitfld.long 0x00 14. " PREXCEN ,Protocol exception enable" "Disabled,Enabled" bitfld.long 0x00 12. " ISOCANFDEN ,ISO CAN FD enable" "Disabled,Enabled" bitfld.long 0x00 11. " EDFLTDIS ,Edge filter disable" "No,Yes" else group.long 0x34++0x03 line.long 0x00 "CTRL2,Control 2 Register" bitfld.long 0x00 31. " ERRMSK_FAST ,Error interrupt mask for errors detected in the data phase of fast CAN FD frames" "Disabled,Enabled" bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 24.--27. " RFFN ,Number of Rx FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128,?..." rbitfld.long 0x00 19.--23. " TASD ,Tx arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "Rx FIFO first,Mailboxes first" rbitfld.long 0x00 17. " RRS ,Remote request storing" "Remote response generated,Remote request stored" rbitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for Rx mailboxes" "Disabled,Enabled" rbitfld.long 0x00 15. " TIMER_SRC ,Timer source" "CAN bit clock,External time tick" newline rbitfld.long 0x00 14. " PREXCEN ,Protocol exception enable" "Disabled,Enabled" rbitfld.long 0x00 12. " ISOCANFDEN ,ISO CAN FD enable" "Disabled,Enabled" rbitfld.long 0x00 11. " EDFLTDIS ,Edge filter disable" "No,Yes" endif rgroup.long 0x38++0x03 line.long 0x00 "ESR2,Error And Status Register 2" hexmask.long.byte 0x00 16.--22. 1. " LPTM ,Lowest priority Tx mailbox" bitfld.long 0x00 14. " VPS ,Valid priority status" "Not valid,Valid" bitfld.long 0x00 13. " IMB ,Inactive mailbox available" "Not available,Available" rgroup.long 0x44++0x03 line.long 0x00 "CRCR,CRC Register" hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,CRC mailbox number" hexmask.long.word 0x00 0.--14. 1. " TXCRC ,CRC value of the last message transmitted" if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long 0x48++0x03 line.long 0x00 "RXFGMASK,Rx FIFO Global Mask Register" bitfld.long 0x00 31. " FGM[31] ,Rx FIFO global mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Rx FIFO global mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Rx FIFO global mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Rx FIFO global mask bit 28" "0,1" newline bitfld.long 0x00 27. " [27] ,Rx FIFO global mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Rx FIFO global mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Rx FIFO global mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Rx FIFO global mask bit 24" "0,1" newline bitfld.long 0x00 23. " [23] ,Rx FIFO global mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Rx FIFO global mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Rx FIFO global mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Rx FIFO global mask bit 20" "0,1" newline bitfld.long 0x00 19. " [19] ,Rx FIFO global mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Rx FIFO global mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Rx FIFO global mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Rx FIFO global mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Rx FIFO global mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Rx FIFO global mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Rx FIFO global mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Rx FIFO global mask bit 12" "0,1" newline bitfld.long 0x00 11. " [11] ,Rx FIFO global mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Rx FIFO global mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Rx FIFO global mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Rx FIFO global mask bit 8" "0,1" newline bitfld.long 0x00 7. " [7] ,Rx FIFO global mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Rx FIFO global mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Rx FIFO global mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Rx FIFO global mask bit 4" "0,1" newline bitfld.long 0x00 3. " [3] ,Rx FIFO global mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Rx FIFO global mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Rx FIFO global mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Rx FIFO global mask bit 0" "0,1" else rgroup.long 0x48++0x03 line.long 0x00 "RXFGMASK,Rx FIFO Global Mask Register" bitfld.long 0x00 31. " FGM[31] ,Rx FIFO global mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Rx FIFO global mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Rx FIFO global mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Rx FIFO global mask bit 28" "0,1" newline bitfld.long 0x00 27. " [27] ,Rx FIFO global mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Rx FIFO global mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Rx FIFO global mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Rx FIFO global mask bit 24" "0,1" newline bitfld.long 0x00 23. " [23] ,Rx FIFO global mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Rx FIFO global mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Rx FIFO global mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Rx FIFO global mask bit 20" "0,1" newline bitfld.long 0x00 19. " [19] ,Rx FIFO global mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Rx FIFO global mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Rx FIFO global mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Rx FIFO global mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Rx FIFO global mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Rx FIFO global mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Rx FIFO global mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Rx FIFO global mask bit 12" "0,1" newline bitfld.long 0x00 11. " [11] ,Rx FIFO global mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Rx FIFO global mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Rx FIFO global mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Rx FIFO global mask bit 8" "0,1" newline bitfld.long 0x00 7. " [7] ,Rx FIFO global mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Rx FIFO global mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Rx FIFO global mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Rx FIFO global mask bit 4" "0,1" newline bitfld.long 0x00 3. " [3] ,Rx FIFO global mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Rx FIFO global mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Rx FIFO global mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Rx FIFO global mask bit 0" "0,1" endif rgroup.long 0x4C++0x03 line.long 0x00 "RXFIR,Rx FIFO Information Register" hexmask.long.word 0x00 0.--8. 1. " IDHIT ,Identifier acceptance filter hit by the received message" if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long 0x50++0x03 line.long 0x00 "CBT,CAN Bit Timing Register" bitfld.long 0x00 31. " BTF ,Bit timing format enable" "Disabled,Enabled" hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,Extended prescaler division factor" bitfld.long 0x00 16.--20. " ERJW ,Extended resync jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--15. " EPROPSEG ,Extended propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 5.--9. " EPSEG1 ,Extended phase segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " EPSEG2 ,Extended phase segment 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else rgroup.long 0x50++0x03 line.long 0x00 "CBT,CAN Bit Timing Register" bitfld.long 0x00 31. " BTF ,Bit timing format enable" "Disabled,Enabled" hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,Extended prescaler division factor" bitfld.long 0x00 16.--20. " ERJW ,Extended resync jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--15. " EPROPSEG ,Extended propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 5.--9. " EPSEG1 ,Extended phase segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " EPSEG2 ,Extended phase segment 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif tree "Rx Individual Mask Registers 0-63" if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x0+0x880)++0x03 line.long 0x00 "RXIMR0,Rx Individual Mask Register 0" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x0+0x880)++0x03 line.long 0x00 "RXIMR0,Rx Individual Mask Register 0" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x4+0x880)++0x03 line.long 0x00 "RXIMR1,Rx Individual Mask Register 1" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x4+0x880)++0x03 line.long 0x00 "RXIMR1,Rx Individual Mask Register 1" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x8+0x880)++0x03 line.long 0x00 "RXIMR2,Rx Individual Mask Register 2" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x8+0x880)++0x03 line.long 0x00 "RXIMR2,Rx Individual Mask Register 2" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0xC+0x880)++0x03 line.long 0x00 "RXIMR3,Rx Individual Mask Register 3" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xC+0x880)++0x03 line.long 0x00 "RXIMR3,Rx Individual Mask Register 3" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x10+0x880)++0x03 line.long 0x00 "RXIMR4,Rx Individual Mask Register 4" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x10+0x880)++0x03 line.long 0x00 "RXIMR4,Rx Individual Mask Register 4" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x14+0x880)++0x03 line.long 0x00 "RXIMR5,Rx Individual Mask Register 5" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x14+0x880)++0x03 line.long 0x00 "RXIMR5,Rx Individual Mask Register 5" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x18+0x880)++0x03 line.long 0x00 "RXIMR6,Rx Individual Mask Register 6" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x18+0x880)++0x03 line.long 0x00 "RXIMR6,Rx Individual Mask Register 6" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x1C+0x880)++0x03 line.long 0x00 "RXIMR7,Rx Individual Mask Register 7" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x1C+0x880)++0x03 line.long 0x00 "RXIMR7,Rx Individual Mask Register 7" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x20+0x880)++0x03 line.long 0x00 "RXIMR8,Rx Individual Mask Register 8" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x20+0x880)++0x03 line.long 0x00 "RXIMR8,Rx Individual Mask Register 8" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x24+0x880)++0x03 line.long 0x00 "RXIMR9,Rx Individual Mask Register 9" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x24+0x880)++0x03 line.long 0x00 "RXIMR9,Rx Individual Mask Register 9" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x28+0x880)++0x03 line.long 0x00 "RXIMR10,Rx Individual Mask Register 10" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x28+0x880)++0x03 line.long 0x00 "RXIMR10,Rx Individual Mask Register 10" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x2C+0x880)++0x03 line.long 0x00 "RXIMR11,Rx Individual Mask Register 11" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x2C+0x880)++0x03 line.long 0x00 "RXIMR11,Rx Individual Mask Register 11" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x30+0x880)++0x03 line.long 0x00 "RXIMR12,Rx Individual Mask Register 12" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x30+0x880)++0x03 line.long 0x00 "RXIMR12,Rx Individual Mask Register 12" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x34+0x880)++0x03 line.long 0x00 "RXIMR13,Rx Individual Mask Register 13" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x34+0x880)++0x03 line.long 0x00 "RXIMR13,Rx Individual Mask Register 13" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x38+0x880)++0x03 line.long 0x00 "RXIMR14,Rx Individual Mask Register 14" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x38+0x880)++0x03 line.long 0x00 "RXIMR14,Rx Individual Mask Register 14" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x3C+0x880)++0x03 line.long 0x00 "RXIMR15,Rx Individual Mask Register 15" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x3C+0x880)++0x03 line.long 0x00 "RXIMR15,Rx Individual Mask Register 15" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x40+0x880)++0x03 line.long 0x00 "RXIMR16,Rx Individual Mask Register 16" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x40+0x880)++0x03 line.long 0x00 "RXIMR16,Rx Individual Mask Register 16" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x44+0x880)++0x03 line.long 0x00 "RXIMR17,Rx Individual Mask Register 17" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x44+0x880)++0x03 line.long 0x00 "RXIMR17,Rx Individual Mask Register 17" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x48+0x880)++0x03 line.long 0x00 "RXIMR18,Rx Individual Mask Register 18" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x48+0x880)++0x03 line.long 0x00 "RXIMR18,Rx Individual Mask Register 18" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x4C+0x880)++0x03 line.long 0x00 "RXIMR19,Rx Individual Mask Register 19" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x4C+0x880)++0x03 line.long 0x00 "RXIMR19,Rx Individual Mask Register 19" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x50+0x880)++0x03 line.long 0x00 "RXIMR20,Rx Individual Mask Register 20" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x50+0x880)++0x03 line.long 0x00 "RXIMR20,Rx Individual Mask Register 20" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x54+0x880)++0x03 line.long 0x00 "RXIMR21,Rx Individual Mask Register 21" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x54+0x880)++0x03 line.long 0x00 "RXIMR21,Rx Individual Mask Register 21" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x58+0x880)++0x03 line.long 0x00 "RXIMR22,Rx Individual Mask Register 22" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x58+0x880)++0x03 line.long 0x00 "RXIMR22,Rx Individual Mask Register 22" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x5C+0x880)++0x03 line.long 0x00 "RXIMR23,Rx Individual Mask Register 23" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x5C+0x880)++0x03 line.long 0x00 "RXIMR23,Rx Individual Mask Register 23" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x60+0x880)++0x03 line.long 0x00 "RXIMR24,Rx Individual Mask Register 24" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x60+0x880)++0x03 line.long 0x00 "RXIMR24,Rx Individual Mask Register 24" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x64+0x880)++0x03 line.long 0x00 "RXIMR25,Rx Individual Mask Register 25" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x64+0x880)++0x03 line.long 0x00 "RXIMR25,Rx Individual Mask Register 25" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x68+0x880)++0x03 line.long 0x00 "RXIMR26,Rx Individual Mask Register 26" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x68+0x880)++0x03 line.long 0x00 "RXIMR26,Rx Individual Mask Register 26" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x6C+0x880)++0x03 line.long 0x00 "RXIMR27,Rx Individual Mask Register 27" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x6C+0x880)++0x03 line.long 0x00 "RXIMR27,Rx Individual Mask Register 27" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x70+0x880)++0x03 line.long 0x00 "RXIMR28,Rx Individual Mask Register 28" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x70+0x880)++0x03 line.long 0x00 "RXIMR28,Rx Individual Mask Register 28" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x74+0x880)++0x03 line.long 0x00 "RXIMR29,Rx Individual Mask Register 29" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x74+0x880)++0x03 line.long 0x00 "RXIMR29,Rx Individual Mask Register 29" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x78+0x880)++0x03 line.long 0x00 "RXIMR30,Rx Individual Mask Register 30" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x78+0x880)++0x03 line.long 0x00 "RXIMR30,Rx Individual Mask Register 30" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x7C+0x880)++0x03 line.long 0x00 "RXIMR31,Rx Individual Mask Register 31" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x7C+0x880)++0x03 line.long 0x00 "RXIMR31,Rx Individual Mask Register 31" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x80+0x880)++0x03 line.long 0x00 "RXIMR32,Rx Individual Mask Register 32" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x80+0x880)++0x03 line.long 0x00 "RXIMR32,Rx Individual Mask Register 32" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x84+0x880)++0x03 line.long 0x00 "RXIMR33,Rx Individual Mask Register 33" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x84+0x880)++0x03 line.long 0x00 "RXIMR33,Rx Individual Mask Register 33" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x88+0x880)++0x03 line.long 0x00 "RXIMR34,Rx Individual Mask Register 34" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x88+0x880)++0x03 line.long 0x00 "RXIMR34,Rx Individual Mask Register 34" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x8C+0x880)++0x03 line.long 0x00 "RXIMR35,Rx Individual Mask Register 35" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x8C+0x880)++0x03 line.long 0x00 "RXIMR35,Rx Individual Mask Register 35" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x90+0x880)++0x03 line.long 0x00 "RXIMR36,Rx Individual Mask Register 36" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x90+0x880)++0x03 line.long 0x00 "RXIMR36,Rx Individual Mask Register 36" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x94+0x880)++0x03 line.long 0x00 "RXIMR37,Rx Individual Mask Register 37" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x94+0x880)++0x03 line.long 0x00 "RXIMR37,Rx Individual Mask Register 37" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x98+0x880)++0x03 line.long 0x00 "RXIMR38,Rx Individual Mask Register 38" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x98+0x880)++0x03 line.long 0x00 "RXIMR38,Rx Individual Mask Register 38" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0x9C+0x880)++0x03 line.long 0x00 "RXIMR39,Rx Individual Mask Register 39" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x9C+0x880)++0x03 line.long 0x00 "RXIMR39,Rx Individual Mask Register 39" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0xA0+0x880)++0x03 line.long 0x00 "RXIMR40,Rx Individual Mask Register 40" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xA0+0x880)++0x03 line.long 0x00 "RXIMR40,Rx Individual Mask Register 40" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0xA4+0x880)++0x03 line.long 0x00 "RXIMR41,Rx Individual Mask Register 41" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xA4+0x880)++0x03 line.long 0x00 "RXIMR41,Rx Individual Mask Register 41" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0xA8+0x880)++0x03 line.long 0x00 "RXIMR42,Rx Individual Mask Register 42" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xA8+0x880)++0x03 line.long 0x00 "RXIMR42,Rx Individual Mask Register 42" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0xAC+0x880)++0x03 line.long 0x00 "RXIMR43,Rx Individual Mask Register 43" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xAC+0x880)++0x03 line.long 0x00 "RXIMR43,Rx Individual Mask Register 43" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0xB0+0x880)++0x03 line.long 0x00 "RXIMR44,Rx Individual Mask Register 44" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xB0+0x880)++0x03 line.long 0x00 "RXIMR44,Rx Individual Mask Register 44" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0xB4+0x880)++0x03 line.long 0x00 "RXIMR45,Rx Individual Mask Register 45" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xB4+0x880)++0x03 line.long 0x00 "RXIMR45,Rx Individual Mask Register 45" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0xB8+0x880)++0x03 line.long 0x00 "RXIMR46,Rx Individual Mask Register 46" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xB8+0x880)++0x03 line.long 0x00 "RXIMR46,Rx Individual Mask Register 46" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0xBC+0x880)++0x03 line.long 0x00 "RXIMR47,Rx Individual Mask Register 47" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xBC+0x880)++0x03 line.long 0x00 "RXIMR47,Rx Individual Mask Register 47" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0xC0+0x880)++0x03 line.long 0x00 "RXIMR48,Rx Individual Mask Register 48" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xC0+0x880)++0x03 line.long 0x00 "RXIMR48,Rx Individual Mask Register 48" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0xC4+0x880)++0x03 line.long 0x00 "RXIMR49,Rx Individual Mask Register 49" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xC4+0x880)++0x03 line.long 0x00 "RXIMR49,Rx Individual Mask Register 49" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0xC8+0x880)++0x03 line.long 0x00 "RXIMR50,Rx Individual Mask Register 50" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xC8+0x880)++0x03 line.long 0x00 "RXIMR50,Rx Individual Mask Register 50" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0xCC+0x880)++0x03 line.long 0x00 "RXIMR51,Rx Individual Mask Register 51" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xCC+0x880)++0x03 line.long 0x00 "RXIMR51,Rx Individual Mask Register 51" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0xD0+0x880)++0x03 line.long 0x00 "RXIMR52,Rx Individual Mask Register 52" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xD0+0x880)++0x03 line.long 0x00 "RXIMR52,Rx Individual Mask Register 52" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0xD4+0x880)++0x03 line.long 0x00 "RXIMR53,Rx Individual Mask Register 53" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xD4+0x880)++0x03 line.long 0x00 "RXIMR53,Rx Individual Mask Register 53" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0xD8+0x880)++0x03 line.long 0x00 "RXIMR54,Rx Individual Mask Register 54" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xD8+0x880)++0x03 line.long 0x00 "RXIMR54,Rx Individual Mask Register 54" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0xDC+0x880)++0x03 line.long 0x00 "RXIMR55,Rx Individual Mask Register 55" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xDC+0x880)++0x03 line.long 0x00 "RXIMR55,Rx Individual Mask Register 55" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0xE0+0x880)++0x03 line.long 0x00 "RXIMR56,Rx Individual Mask Register 56" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xE0+0x880)++0x03 line.long 0x00 "RXIMR56,Rx Individual Mask Register 56" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0xE4+0x880)++0x03 line.long 0x00 "RXIMR57,Rx Individual Mask Register 57" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xE4+0x880)++0x03 line.long 0x00 "RXIMR57,Rx Individual Mask Register 57" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0xE8+0x880)++0x03 line.long 0x00 "RXIMR58,Rx Individual Mask Register 58" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xE8+0x880)++0x03 line.long 0x00 "RXIMR58,Rx Individual Mask Register 58" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0xEC+0x880)++0x03 line.long 0x00 "RXIMR59,Rx Individual Mask Register 59" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xEC+0x880)++0x03 line.long 0x00 "RXIMR59,Rx Individual Mask Register 59" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0xF0+0x880)++0x03 line.long 0x00 "RXIMR60,Rx Individual Mask Register 60" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xF0+0x880)++0x03 line.long 0x00 "RXIMR60,Rx Individual Mask Register 60" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0xF4+0x880)++0x03 line.long 0x00 "RXIMR61,Rx Individual Mask Register 61" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xF4+0x880)++0x03 line.long 0x00 "RXIMR61,Rx Individual Mask Register 61" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0xF8+0x880)++0x03 line.long 0x00 "RXIMR62,Rx Individual Mask Register 62" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xF8+0x880)++0x03 line.long 0x00 "RXIMR62,Rx Individual Mask Register 62" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long (0xFC+0x880)++0x03 line.long 0x00 "RXIMR63,Rx Individual Mask Register 63" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xFC+0x880)++0x03 line.long 0x00 "RXIMR63,Rx Individual Mask Register 63" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif tree.end newline if (((per.l(ad:0x5A8E0000+0x00))&0x50000000)==0x50000000) group.long 0xC00++0x07 line.long 0x00 "FDCTRL,CAN FD Control Register" bitfld.long 0x00 31. " FDRATE ,Bit rate switch enable" "Disabled,Enabled" bitfld.long 0x00 19.--20. " MBDSR1 ,Message buffer data size for region 1" "8 bytes,16 bytes,32 bytes,64 bytes" bitfld.long 0x00 16.--17. " MBDSR0 ,Message buffer data size for region 0" "8 bytes,16 bytes,32 bytes,64 bytes" bitfld.long 0x00 15. " TDCEN ,Transceiver delay compensation enable" "Disabled,Enabled" newline eventfld.long 0x00 14. " TDCFAIL ,Transceiver delay compensation fail" "In range,Out of range" bitfld.long 0x00 8.--12. " TDCOFF ,Transceiver delay compensation offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--5. " TDCVAL ,Transceiver delay compensation value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "FDCBT,CAN FD Bit Timing Register" hexmask.long.word 0x04 20.--29. 1. " FPRESDIV ,Fast prescaler division factor" bitfld.long 0x04 16.--18. " FRJW ,Fast resync jump width" "0,1,2,3,4,5,6,7" bitfld.long 0x04 10.--14. " FPROPSEG ,Fast propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 5.--7. " FPSEG1 ,Fast phase segment 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 0.--2. " FPSEG2 ,Fast phase segment 2" "0,1,2,3,4,5,6,7" else group.long 0xC00++0x03 line.long 0x00 "FDCTRL,CAN FD Control Register" bitfld.long 0x00 31. " FDRATE ,Bit rate switch enable" "Disabled,Enabled" bitfld.long 0x00 19.--20. " MBDSR1 ,Message buffer data size for region 1" "8 bytes,16 bytes,32 bytes,64 bytes" rbitfld.long 0x00 16.--17. " MBDSR0 ,Message buffer data size for region 0" "8 bytes,16 bytes,32 bytes,64 bytes" rbitfld.long 0x00 15. " TDCEN ,Transceiver delay compensation enable" "Disabled,Enabled" newline eventfld.long 0x00 14. " TDCFAIL ,Transceiver delay compensation fail" "In range,Out of range" rbitfld.long 0x00 8.--12. " TDCOFF ,Transceiver delay compensation offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--5. " TDCVAL ,Transceiver delay compensation value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0xC04++0x03 line.long 0x00 "FDCBT,CAN FD Bit Timing Register" hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,Fast prescaler division factor" bitfld.long 0x00 16.--18. " FRJW ,Fast resync jump width" "1,2,3,4,5,6,7,8" bitfld.long 0x00 10.--14. " FPROPSEG ,Fast propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--7. " FPSEG1 ,Fast phase segment 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--2. " FPSEG2 ,Fast phase segment 2" "0,1,2,3,4,5,6,7" endif rgroup.long 0xC08++0x03 line.long 0x00 "FDCRC,CAN FD CRC Register" hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,CRC mailbox number for FD_TXCRC" hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCRC ,Extended transmitted CRC value" width 0x0B tree.end tree "CAN2" base ad:0x5A8F0000 width 10. if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) if (((per.l(ad:0x5A8F0000+0x00))&0x20000000)==0x20000000) if (((per.l(ad:0x5A8F0000+0x00))&0x800)==0x800) if ((per.l(ad:0x5A8F0000)&0x100000)==0x00) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline bitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" newline hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline rbitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" newline hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif else if ((per.l(ad:0x5A8F0000)&0x100000)==0x00) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" bitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline bitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" newline hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" bitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline rbitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" newline hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif endif else if (((per.l(ad:0x5A8F0000+0x00))&0x800)==0x800) if ((per.l(ad:0x5A8F0000)&0x100000)==0x00) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline bitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline rbitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif else if ((per.l(ad:0x5A8F0000)&0x100000)==0x00) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" bitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline bitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" bitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline rbitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" bitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif endif endif else if (((per.l(ad:0x5A8F0000+0x00))&0x20000000)==0x20000000) if ((per.l(ad:0x5A8F0000)&0x100000)==0x00) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline bitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" rbitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" rbitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" rbitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" rbitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" rbitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" newline rbitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" rbitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" rbitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" rbitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" newline hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline rbitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" rbitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" rbitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" rbitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" rbitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" rbitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" newline rbitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" rbitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" rbitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" rbitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" newline hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif else if ((per.l(ad:0x5A8F0000)&0x100000)==0x00) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline bitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" rbitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" rbitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" rbitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" rbitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" rbitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline rbitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" rbitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" rbitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt flexcan" "No freeze mode,Freeze mode (FRZ bit needed)" newline rbitfld.long 0x00 27. " NOTRDY ,Flexcan not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt generation enable" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" newline rbitfld.long 0x00 22. " SLFWAK ,Self wake up feature enable" "Disabled,Enabled" rbitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low-Power mode acknowledge" "Not low-power,Low-power" rbitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" newline bitfld.long 0x00 18. " DOZE ,Defines whether FlexCAN is allowed to enter low-power mode" "Disabled,Enabled" rbitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" rbitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" rbitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline rbitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" rbitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" rbitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" endif endif endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) if (((per.l(ad:0x5A8F0000+0x00))&0x200000)==0x200000) if ((per.l(ad:0x5A8F0000)&0x80000000)==0x00) group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" bitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" bitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" ",1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" bitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Peripheral,Oscillator" bitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline bitfld.long 0x00 11. " TWRNMSK ,Tx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RWRNMSK ,Rx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline bitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" bitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" bitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" bitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" else group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" bitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" bitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" ",1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Peripheral,Oscillator" bitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline bitfld.long 0x00 11. " TWRNMSK ,Tx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RWRNMSK ,Rx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline bitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" bitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" bitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" bitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" endif else if ((per.l(ad:0x5A8F0000)&0x80000000)==0x00) group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" bitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" bitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" ",1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" bitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Peripheral,Oscillator" bitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline rbitfld.long 0x00 11. " TWRNMSK ,Tx warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 10. " RWRNMSK ,Rx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline bitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" bitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" bitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" bitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" else group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" bitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" bitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" ",1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Peripheral,Oscillator" bitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline rbitfld.long 0x00 11. " TWRNMSK ,Tx warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 10. " RWRNMSK ,Rx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline bitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" bitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" bitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" bitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" endif endif else if (((per.l(ad:0x5A8F0000+0x00))&0x200000)==0x200000) if ((per.l(ad:0x5A8F0000)&0x80000000)==0x00) group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" rbitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" rbitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" ",1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" bitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Peripheral,Oscillator" rbitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline bitfld.long 0x00 11. " TWRNMSK ,Tx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RWRNMSK ,Rx warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline rbitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" rbitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" rbitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" rbitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" else group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" rbitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" rbitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" ",1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Peripheral,Oscillator" rbitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline bitfld.long 0x00 11. " TWRNMSK ,Tx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RWRNMSK ,Rx warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline rbitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" rbitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" rbitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" rbitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" endif else if ((per.l(ad:0x5A8F0000)&0x80000000)==0x00) group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" rbitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" rbitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" ",1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" bitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Peripheral,Oscillator" rbitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline rbitfld.long 0x00 11. " TWRNMSK ,Tx warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 10. " RWRNMSK ,Rx warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline rbitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" rbitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" rbitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" rbitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" else group.long 0x04++0x03 line.long 0x00 "CTRL1,Control 1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ,Prescaler division factor" rbitfld.long 0x00 22.--23. " RJW ,Resync jump width" "0,1,2,3" rbitfld.long 0x00 19.--21. " PSEG1 ,Phase segment 1" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--18. " PSEG2 ,Phase segment 2" ",1,2,3,4,5,6,7" newline bitfld.long 0x00 15. " BOFFMSK ,Bus off interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " ERRMSK ,Error interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 13. " CLKSRC ,CAN engine clock source" "Peripheral,Oscillator" rbitfld.long 0x00 12. " LPB ,Loop back mode" "Disabled,Enabled" newline rbitfld.long 0x00 11. " TWRNMSK ,Tx warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 10. " RWRNMSK ,Rx warning interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 7. " SMP ,CAN bit sampling" "1 sample,3 samples" bitfld.long 0x00 6. " BOFFREC ,Bus off recovery disable" "No,Yes" newline rbitfld.long 0x00 5. " TSYN ,Timer sync" "Disabled,Enabled" rbitfld.long 0x00 4. " LBUF ,Lowest buffer transmitted first" "Highest first,Lowest first" rbitfld.long 0x00 3. " LOM ,Listen only mode" "Disabled,Enabled" rbitfld.long 0x00 0.--2. " PROPSEG ,Propagation segment" "0,1,2,3,4,5,6,7" endif endif endif group.long 0x08++0x03 line.long 0x00 "TIMER,Free Running Timer" hexmask.long.word 0x00 0.--15. 1. " TIMER ,Timer value" if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long 0x10++0x0F line.long 0x00 "RXMGMASK,Rx Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG[31] ,Mailbox filter 31 mask" "0,1" bitfld.long 0x00 30. " [30] ,Mailbox filter 30 mask" "0,1" bitfld.long 0x00 29. " [29] ,Mailbox filter 29 mask" "0,1" bitfld.long 0x00 28. " [28] ,Mailbox filter 28 mask" "0,1" newline bitfld.long 0x00 27. " [27] ,Mailbox filter 27 mask" "0,1" bitfld.long 0x00 26. " [26] ,Mailbox filter 26 mask" "0,1" bitfld.long 0x00 25. " [25] ,Mailbox filter 25 mask" "0,1" bitfld.long 0x00 24. " [24] ,Mailbox filter 24 mask" "0,1" newline bitfld.long 0x00 23. " [23] ,Mailbox filter 23 mask" "0,1" bitfld.long 0x00 22. " [22] ,Mailbox filter 22 mask" "0,1" bitfld.long 0x00 21. " [21] ,Mailbox filter 21 mask" "0,1" bitfld.long 0x00 20. " [20] ,Mailbox filter 20 mask" "0,1" newline bitfld.long 0x00 19. " [19] ,Mailbox filter 19 mask" "0,1" bitfld.long 0x00 18. " [18] ,Mailbox filter 18 mask" "0,1" bitfld.long 0x00 17. " [17] ,Mailbox filter 17 mask" "0,1" bitfld.long 0x00 16. " [16] ,Mailbox filter 16 mask" "0,1" newline bitfld.long 0x00 15. " [15] ,Mailbox filter 15 mask" "0,1" bitfld.long 0x00 14. " [14] ,Mailbox filter 14 mask" "0,1" bitfld.long 0x00 13. " [13] ,Mailbox filter 13 mask" "0,1" bitfld.long 0x00 12. " [12] ,Mailbox filter 12 mask" "0,1" newline bitfld.long 0x00 11. " [11] ,Mailbox filter 11 mask" "0,1" bitfld.long 0x00 10. " [10] ,Mailbox filter 10 mask" "0,1" bitfld.long 0x00 9. " [9] ,Mailbox filter 9 mask" "0,1" bitfld.long 0x00 8. " [8] ,Mailbox filter 8 mask" "0,1" newline bitfld.long 0x00 7. " [7] ,Mailbox filter 7 mask" "0,1" bitfld.long 0x00 6. " [6] ,Mailbox filter 6 mask" "0,1" bitfld.long 0x00 5. " [5] ,Mailbox filter 5 mask" "0,1" bitfld.long 0x00 4. " [4] ,Mailbox filter 4 mask" "0,1" newline bitfld.long 0x00 3. " [3] ,Mailbox filter 3 mask" "0,1" bitfld.long 0x00 2. " [2] ,Mailbox filter 2 mask" "0,1" bitfld.long 0x00 1. " [1] ,Mailbox filter 1 mask" "0,1" bitfld.long 0x00 0. " [0] ,Mailbox filter 0 mask" "0,1" line.long 0x04 "RX14MASK,Rx Buffer 14 Mask Register" bitfld.long 0x04 31. " RX14M[31] ,Rx buffer 14 mask bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Rx buffer 14 mask bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Rx buffer 14 mask bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Rx buffer 14 mask bit 28" "0,1" newline bitfld.long 0x04 27. " [27] ,Rx buffer 14 mask bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Rx buffer 14 mask bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Rx buffer 14 mask bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Rx buffer 14 mask bit 24" "0,1" newline bitfld.long 0x04 23. " [23] ,Rx buffer 14 mask bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Rx buffer 14 mask bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Rx buffer 14 mask bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Rx buffer 14 mask bit 20" "0,1" newline bitfld.long 0x04 19. " [19] ,Rx buffer 14 mask bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Rx buffer 14 mask bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Rx buffer 14 mask bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Rx buffer 14 mask bit 16" "0,1" newline bitfld.long 0x04 15. " [15] ,Rx buffer 14 mask bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Rx buffer 14 mask bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Rx buffer 14 mask bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Rx buffer 14 mask bit 12" "0,1" newline bitfld.long 0x04 11. " [11] ,Rx buffer 14 mask bit 11" "0,1" bitfld.long 0x04 10. " [10] ,Rx buffer 14 mask bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Rx buffer 14 mask bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Rx buffer 14 mask bit 8" "0,1" newline bitfld.long 0x04 7. " [7] ,Rx buffer 14 mask bit 7" "0,1" bitfld.long 0x04 6. " [6] ,Rx buffer 14 mask bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Rx buffer 14 mask bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Rx buffer 14 mask bit 4" "0,1" newline bitfld.long 0x04 3. " [3] ,Rx buffer 14 mask bit 3" "0,1" bitfld.long 0x04 2. " [2] ,Rx buffer 14 mask bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Rx buffer 14 mask bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Rx buffer 14 mask bit 0" "0,1" line.long 0x08 "RX15MASK,Rx Buffer 15 Mask Register" bitfld.long 0x08 31. " RX15M[31] ,Rx buffer 15 mask bit 31" "0,1" bitfld.long 0x08 30. " [30] ,Rx buffer 15 mask bit 30" "0,1" bitfld.long 0x08 29. " [29] ,Rx buffer 15 mask bit 29" "0,1" bitfld.long 0x08 28. " [28] ,Rx buffer 15 mask bit 28" "0,1" newline bitfld.long 0x08 27. " [27] ,Rx buffer 15 mask bit 27" "0,1" bitfld.long 0x08 26. " [26] ,Rx buffer 15 mask bit 26" "0,1" bitfld.long 0x08 25. " [25] ,Rx buffer 15 mask bit 25" "0,1" bitfld.long 0x08 24. " [24] ,Rx buffer 15 mask bit 24" "0,1" newline bitfld.long 0x08 23. " [23] ,Rx buffer 15 mask bit 23" "0,1" bitfld.long 0x08 22. " [22] ,Rx buffer 15 mask bit 22" "0,1" bitfld.long 0x08 21. " [21] ,Rx buffer 15 mask bit 21" "0,1" bitfld.long 0x08 20. " [20] ,Rx buffer 15 mask bit 20" "0,1" newline bitfld.long 0x08 19. " [19] ,Rx buffer 15 mask bit 19" "0,1" bitfld.long 0x08 18. " [18] ,Rx buffer 15 mask bit 18" "0,1" bitfld.long 0x08 17. " [17] ,Rx buffer 15 mask bit 17" "0,1" bitfld.long 0x08 16. " [16] ,Rx buffer 15 mask bit 16" "0,1" newline bitfld.long 0x08 15. " [15] ,Rx buffer 15 mask bit 15" "0,1" bitfld.long 0x08 14. " [14] ,Rx buffer 15 mask bit 14" "0,1" bitfld.long 0x08 13. " [13] ,Rx buffer 15 mask bit 13" "0,1" bitfld.long 0x08 12. " [12] ,Rx buffer 15 mask bit 12" "0,1" newline bitfld.long 0x08 11. " [11] ,Rx buffer 15 mask bit 11" "0,1" bitfld.long 0x08 10. " [10] ,Rx buffer 15 mask bit 10" "0,1" bitfld.long 0x08 9. " [9] ,Rx buffer 15 mask bit 9" "0,1" bitfld.long 0x08 8. " [8] ,Rx buffer 15 mask bit 8" "0,1" newline bitfld.long 0x08 7. " [7] ,Rx buffer 15 mask bit 7" "0,1" bitfld.long 0x08 6. " [6] ,Rx buffer 15 mask bit 6" "0,1" bitfld.long 0x08 5. " [5] ,Rx buffer 15 mask bit 5" "0,1" bitfld.long 0x08 4. " [4] ,Rx buffer 15 mask bit 4" "0,1" newline bitfld.long 0x08 3. " [3] ,Rx buffer 15 mask bit 3" "0,1" bitfld.long 0x08 2. " [2] ,Rx buffer 15 mask bit 2" "0,1" bitfld.long 0x08 1. " [1] ,Rx buffer 15 mask bit 1" "0,1" bitfld.long 0x08 0. " [0] ,Rx buffer 15 mask bit 0" "0,1" line.long 0x0C "ECR,Error Counter Register" hexmask.long.byte 0x0C 24.--31. 1. " RXERRCNT_FAST ,Receive error counter for fast bit" hexmask.long.byte 0x0C 16.--23. 1. " TXERRCNT_FAST ,Transmit error counter for fast bits" hexmask.long.byte 0x0C 8.--15. 1. " RXERRCNT ,Receive error counter" hexmask.long.byte 0x0C 0.--7. 1. " TXERRCNT ,Transmit error counter" else rgroup.long 0x10++0x0F line.long 0x00 "RXMGMASK,Rx Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG[31] ,Mailbox filter 31 mask" "0,1" bitfld.long 0x00 30. " [30] ,Mailbox filter 30 mask" "0,1" bitfld.long 0x00 29. " [29] ,Mailbox filter 29 mask" "0,1" bitfld.long 0x00 28. " [28] ,Mailbox filter 28 mask" "0,1" newline bitfld.long 0x00 27. " [27] ,Mailbox filter 27 mask" "0,1" bitfld.long 0x00 26. " [26] ,Mailbox filter 26 mask" "0,1" bitfld.long 0x00 25. " [25] ,Mailbox filter 25 mask" "0,1" bitfld.long 0x00 24. " [24] ,Mailbox filter 24 mask" "0,1" newline bitfld.long 0x00 23. " [23] ,Mailbox filter 23 mask" "0,1" bitfld.long 0x00 22. " [22] ,Mailbox filter 22 mask" "0,1" bitfld.long 0x00 21. " [21] ,Mailbox filter 21 mask" "0,1" bitfld.long 0x00 20. " [20] ,Mailbox filter 20 mask" "0,1" newline bitfld.long 0x00 19. " [19] ,Mailbox filter 19 mask" "0,1" bitfld.long 0x00 18. " [18] ,Mailbox filter 18 mask" "0,1" bitfld.long 0x00 17. " [17] ,Mailbox filter 17 mask" "0,1" bitfld.long 0x00 16. " [16] ,Mailbox filter 16 mask" "0,1" newline bitfld.long 0x00 15. " [15] ,Mailbox filter 15 mask" "0,1" bitfld.long 0x00 14. " [14] ,Mailbox filter 14 mask" "0,1" bitfld.long 0x00 13. " [13] ,Mailbox filter 13 mask" "0,1" bitfld.long 0x00 12. " [12] ,Mailbox filter 12 mask" "0,1" newline bitfld.long 0x00 11. " [11] ,Mailbox filter 11 mask" "0,1" bitfld.long 0x00 10. " [10] ,Mailbox filter 10 mask" "0,1" bitfld.long 0x00 9. " [9] ,Mailbox filter 9 mask" "0,1" bitfld.long 0x00 8. " [8] ,Mailbox filter 8 mask" "0,1" newline bitfld.long 0x00 7. " [7] ,Mailbox filter 7 mask" "0,1" bitfld.long 0x00 6. " [6] ,Mailbox filter 6 mask" "0,1" bitfld.long 0x00 5. " [5] ,Mailbox filter 5 mask" "0,1" bitfld.long 0x00 4. " [4] ,Mailbox filter 4 mask" "0,1" newline bitfld.long 0x00 3. " [3] ,Mailbox filter 3 mask" "0,1" bitfld.long 0x00 2. " [2] ,Mailbox filter 2 mask" "0,1" bitfld.long 0x00 1. " [1] ,Mailbox filter 1 mask" "0,1" bitfld.long 0x00 0. " [0] ,Mailbox filter 0 mask" "0,1" line.long 0x04 "RX14MASK,Rx Buffer 14 Mask Register" bitfld.long 0x04 31. " RX14M[31] ,Mailbox 14 filter 31 mask" "0,1" bitfld.long 0x04 30. " [30] ,Mailbox 14 filter 30 mask" "0,1" bitfld.long 0x04 29. " [29] ,Mailbox 14 filter 29 mask" "0,1" bitfld.long 0x04 28. " [28] ,Mailbox 14 filter 28 mask" "0,1" newline bitfld.long 0x04 27. " [27] ,Mailbox 14 filter 27 mask" "0,1" bitfld.long 0x04 26. " [26] ,Mailbox 14 filter 26 mask" "0,1" bitfld.long 0x04 25. " [25] ,Mailbox 14 filter 25 mask" "0,1" bitfld.long 0x04 24. " [24] ,Mailbox 14 filter 24 mask" "0,1" newline bitfld.long 0x04 23. " [23] ,Mailbox 14 filter 23 mask" "0,1" bitfld.long 0x04 22. " [22] ,Mailbox 14 filter 22 mask" "0,1" bitfld.long 0x04 21. " [21] ,Mailbox 14 filter 21 mask" "0,1" bitfld.long 0x04 20. " [20] ,Mailbox 14 filter 20 mask" "0,1" newline bitfld.long 0x04 19. " [19] ,Mailbox 14 filter 19 mask" "0,1" bitfld.long 0x04 18. " [18] ,Mailbox 14 filter 18 mask" "0,1" bitfld.long 0x04 17. " [17] ,Mailbox 14 filter 17 mask" "0,1" bitfld.long 0x04 16. " [16] ,Mailbox 14 filter 16 mask" "0,1" newline bitfld.long 0x04 15. " [15] ,Mailbox 14 filter 15 mask" "0,1" bitfld.long 0x04 14. " [14] ,Mailbox 14 filter 14 mask" "0,1" bitfld.long 0x04 13. " [13] ,Mailbox 14 filter 13 mask" "0,1" bitfld.long 0x04 12. " [12] ,Mailbox 14 filter 12 mask" "0,1" newline bitfld.long 0x04 11. " [11] ,Mailbox 14 filter 11 mask" "0,1" bitfld.long 0x04 10. " [10] ,Mailbox 14 filter 10 mask" "0,1" bitfld.long 0x04 9. " [9] ,Mailbox 14 filter 9 mask" "0,1" bitfld.long 0x04 8. " [8] ,Mailbox 14 filter 8 mask" "0,1" newline bitfld.long 0x04 7. " [7] ,Mailbox 14 filter 7 mask" "0,1" bitfld.long 0x04 6. " [6] ,Mailbox 14 filter 6 mask" "0,1" bitfld.long 0x04 5. " [5] ,Mailbox 14 filter 5 mask" "0,1" bitfld.long 0x04 4. " [4] ,Mailbox 14 filter 4 mask" "0,1" newline bitfld.long 0x04 3. " [3] ,Mailbox 14 filter 3 mask" "0,1" bitfld.long 0x04 2. " [2] ,Mailbox 14 filter 2 mask" "0,1" bitfld.long 0x04 1. " [1] ,Mailbox 14 filter 1 mask" "0,1" bitfld.long 0x04 0. " [0] ,Mailbox 14 filter 0 mask" "0,1" line.long 0x08 "RX15MASK,Rx Buffer 15 Mask Register" bitfld.long 0x08 31. " RX15M[31] ,Mailbox 15 filter 31 mask" "0,1" bitfld.long 0x08 30. " [30] ,Mailbox 15 filter 30 mask" "0,1" bitfld.long 0x08 29. " [29] ,Mailbox 15 filter 29 mask" "0,1" bitfld.long 0x08 28. " [28] ,Mailbox 15 filter 28 mask" "0,1" newline bitfld.long 0x08 27. " [27] ,Mailbox 15 filter 27 mask" "0,1" bitfld.long 0x08 26. " [26] ,Mailbox 15 filter 26 mask" "0,1" bitfld.long 0x08 25. " [25] ,Mailbox 15 filter 25 mask" "0,1" bitfld.long 0x08 24. " [24] ,Mailbox 15 filter 24 mask" "0,1" newline bitfld.long 0x08 23. " [23] ,Mailbox 15 filter 23 mask" "0,1" bitfld.long 0x08 22. " [22] ,Mailbox 15 filter 22 mask" "0,1" bitfld.long 0x08 21. " [21] ,Mailbox 15 filter 21 mask" "0,1" bitfld.long 0x08 20. " [20] ,Mailbox 15 filter 20 mask" "0,1" newline bitfld.long 0x08 19. " [19] ,Mailbox 15 filter 19 mask" "0,1" bitfld.long 0x08 18. " [18] ,Mailbox 15 filter 18 mask" "0,1" bitfld.long 0x08 17. " [17] ,Mailbox 15 filter 17 mask" "0,1" bitfld.long 0x08 16. " [16] ,Mailbox 15 filter 16 mask" "0,1" newline bitfld.long 0x08 15. " [15] ,Mailbox 15 filter 15 mask" "0,1" bitfld.long 0x08 14. " [14] ,Mailbox 15 filter 14 mask" "0,1" bitfld.long 0x08 13. " [13] ,Mailbox 15 filter 13 mask" "0,1" bitfld.long 0x08 12. " [12] ,Mailbox 15 filter 12 mask" "0,1" newline bitfld.long 0x08 11. " [11] ,Mailbox 15 filter 11 mask" "0,1" bitfld.long 0x08 10. " [10] ,Mailbox 15 filter 10 mask" "0,1" bitfld.long 0x08 9. " [9] ,Mailbox 15 filter 9 mask" "0,1" bitfld.long 0x08 8. " [8] ,Mailbox 15 filter 8 mask" "0,1" newline bitfld.long 0x08 7. " [7] ,Mailbox 15 filter 7 mask" "0,1" bitfld.long 0x08 6. " [6] ,Mailbox 15 filter 6 mask" "0,1" bitfld.long 0x08 5. " [5] ,Mailbox 15 filter 5 mask" "0,1" bitfld.long 0x08 4. " [4] ,Mailbox 15 filter 4 mask" "0,1" newline bitfld.long 0x08 3. " [3] ,Mailbox 15 filter 3 mask" "0,1" bitfld.long 0x08 2. " [2] ,Mailbox 15 filter 2 mask" "0,1" bitfld.long 0x08 1. " [1] ,Mailbox 15 filter 1 mask" "0,1" bitfld.long 0x08 0. " [0] ,Mailbox 15 filter 0 mask" "0,1" line.long 0x0C "ECR,Error Counter Register" hexmask.long.byte 0x0C 24.--31. 1. " RXERRCNT_FAST ,Receive error counter for fast bit" hexmask.long.byte 0x0C 16.--23. 1. " TXERRCNT_FAST ,Transmit error counter for fast bits" hexmask.long.byte 0x0C 8.--15. 1. " RXERRCNT ,Receive error counter" hexmask.long.byte 0x0C 0.--7. 1. " TXERRCNT ,Transmit error counter" endif newline hgroup.long 0x20++0x03 hide.long 0x00 "ESR1,Error And Status Register 1" in newline group.long 0x24++0x0B line.long 0x00 "IMASK2,Interrupt Mask Register 2" bitfld.long 0x00 31. " BUF[63]TO32M ,Buffer MB63 mask" "Disabled,Enabled" bitfld.long 0x00 30. " [62] ,Buffer MB62 mask" "Disabled,Enabled" bitfld.long 0x00 29. " [61] ,Buffer MB61 mask" "Disabled,Enabled" bitfld.long 0x00 28. " [60] ,Buffer MB60 mask" "Disabled,Enabled" newline bitfld.long 0x00 27. " [59] ,Buffer MB59 mask" "Disabled,Enabled" bitfld.long 0x00 26. " [58] ,Buffer MB58 mask" "Disabled,Enabled" bitfld.long 0x00 25. " [57] ,Buffer MB57 mask" "Disabled,Enabled" bitfld.long 0x00 24. " [56] ,Buffer MB56 mask" "Disabled,Enabled" newline bitfld.long 0x00 23. " [55] ,Buffer MB55 mask" "Disabled,Enabled" bitfld.long 0x00 22. " [54] ,Buffer MB54 mask" "Disabled,Enabled" bitfld.long 0x00 21. " [53] ,Buffer MB53 mask" "Disabled,Enabled" bitfld.long 0x00 20. " [52] ,Buffer MB52 mask" "Disabled,Enabled" newline bitfld.long 0x00 19. " [51] ,Buffer MB51 mask" "Disabled,Enabled" bitfld.long 0x00 18. " [50] ,Buffer MB50 mask" "Disabled,Enabled" bitfld.long 0x00 17. " [49] ,Buffer MB49 mask" "Disabled,Enabled" bitfld.long 0x00 16. " [48] ,Buffer MB48 mask" "Disabled,Enabled" newline bitfld.long 0x00 15. " [47] ,Buffer MB47 mask" "Disabled,Enabled" bitfld.long 0x00 14. " [46] ,Buffer MB46 mask" "Disabled,Enabled" bitfld.long 0x00 13. " [45] ,Buffer MB45 mask" "Disabled,Enabled" bitfld.long 0x00 12. " [44] ,Buffer MB44 mask" "Disabled,Enabled" newline bitfld.long 0x00 11. " [43] ,Buffer MB43 mask" "Disabled,Enabled" bitfld.long 0x00 10. " [42] ,Buffer MB42 mask" "Disabled,Enabled" bitfld.long 0x00 9. " [41] ,Buffer MB41 mask" "Disabled,Enabled" bitfld.long 0x00 8. " [40] ,Buffer MB40 mask" "Disabled,Enabled" newline bitfld.long 0x00 7. " [39] ,Buffer MB39 mask" "Disabled,Enabled" bitfld.long 0x00 6. " [38] ,Buffer MB38 mask" "Disabled,Enabled" bitfld.long 0x00 5. " [37] ,Buffer MB37 mask" "Disabled,Enabled" bitfld.long 0x00 4. " [36] ,Buffer MB36 mask" "Disabled,Enabled" newline bitfld.long 0x00 3. " [35] ,Buffer MB35 mask" "Disabled,Enabled" bitfld.long 0x00 2. " [34] ,Buffer MB34 mask" "Disabled,Enabled" bitfld.long 0x00 1. " [33] ,Buffer MB33 mask" "Disabled,Enabled" bitfld.long 0x00 0. " [32] ,Buffer MB32 mask" "Disabled,Enabled" line.long 0x04 "IMASK1,Interrupt Masks Register 1" bitfld.long 0x04 31. " BUF[31]TO0M ,Buffer MB31 mask" "Disabled,Enabled" bitfld.long 0x04 30. " [30] ,Buffer MB30 mask" "Disabled,Enabled" bitfld.long 0x04 29. " [29] ,Buffer MB29 mask" "Disabled,Enabled" bitfld.long 0x04 28. " [28] ,Buffer MB28 mask" "Disabled,Enabled" newline bitfld.long 0x04 27. " [27] ,Buffer MB27 mask" "Disabled,Enabled" bitfld.long 0x04 26. " [26] ,Buffer MB26 mask" "Disabled,Enabled" bitfld.long 0x04 25. " [25] ,Buffer MB25 mask" "Disabled,Enabled" bitfld.long 0x04 24. " [24] ,Buffer MB24 mask" "Disabled,Enabled" newline bitfld.long 0x04 23. " [23] ,Buffer MB23 mask" "Disabled,Enabled" bitfld.long 0x04 22. " [22] ,Buffer MB22 mask" "Disabled,Enabled" bitfld.long 0x04 21. " [21] ,Buffer MB21 mask" "Disabled,Enabled" bitfld.long 0x04 20. " [20] ,Buffer MB20 mask" "Disabled,Enabled" newline bitfld.long 0x04 19. " [19] ,Buffer MB19 mask" "Disabled,Enabled" bitfld.long 0x04 18. " [18] ,Buffer MB18 mask" "Disabled,Enabled" bitfld.long 0x04 17. " [17] ,Buffer MB17 mask" "Disabled,Enabled" bitfld.long 0x04 16. " [16] ,Buffer MB16 mask" "Disabled,Enabled" newline bitfld.long 0x04 15. " [15] ,Buffer MB15 mask" "Disabled,Enabled" bitfld.long 0x04 14. " [14] ,Buffer MB14 mask" "Disabled,Enabled" bitfld.long 0x04 13. " [13] ,Buffer MB13 mask" "Disabled,Enabled" bitfld.long 0x04 12. " [12] ,Buffer MB12 mask" "Disabled,Enabled" newline bitfld.long 0x04 11. " [11] ,Buffer MB11 mask" "Disabled,Enabled" bitfld.long 0x04 10. " [10] ,Buffer MB10 mask" "Disabled,Enabled" bitfld.long 0x04 9. " [9] ,Buffer MB9 mask" "Disabled,Enabled" bitfld.long 0x04 8. " [8] ,Buffer MB8 mask" "Disabled,Enabled" newline bitfld.long 0x04 7. " [7] ,Buffer MB7 mask" "Disabled,Enabled" bitfld.long 0x04 6. " [6] ,Buffer MB6 mask" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,Buffer MB5 mask" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,Buffer MB4 mask" "Disabled,Enabled" newline bitfld.long 0x04 3. " [3] ,Buffer MB3 mask" "Disabled,Enabled" bitfld.long 0x04 2. " [2] ,Buffer MB2 mask" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,Buffer MB1 mask" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,Buffer MB0 mask" "Disabled,Enabled" line.long 0x08 "IFLAG2,Interrupt Flags 2 Register" eventfld.long 0x08 31. " BUF[63]TO32I ,Buffer MB63 interrupt" "Not occurred,Occurred" eventfld.long 0x08 30. " [62] ,Buffer MB62 interrupt" "Not occurred,Occurred" eventfld.long 0x08 29. " [61] ,Buffer MB61 interrupt" "Not occurred,Occurred" eventfld.long 0x08 28. " [60] ,Buffer MB60 interrupt" "Not occurred,Occurred" newline eventfld.long 0x08 27. " [59] ,Buffer MB59 interrupt" "Not occurred,Occurred" eventfld.long 0x08 26. " [58] ,Buffer MB58 interrupt" "Not occurred,Occurred" eventfld.long 0x08 25. " [57] ,Buffer MB57 interrupt" "Not occurred,Occurred" eventfld.long 0x08 24. " [56] ,Buffer MB56 interrupt" "Not occurred,Occurred" newline eventfld.long 0x08 23. " [55] ,Buffer MB55 interrupt" "Not occurred,Occurred" eventfld.long 0x08 22. " [54] ,Buffer MB54 interrupt" "Not occurred,Occurred" eventfld.long 0x08 21. " [53] ,Buffer MB53 interrupt" "Not occurred,Occurred" eventfld.long 0x08 20. " [52] ,Buffer MB52 interrupt" "Not occurred,Occurred" newline eventfld.long 0x08 19. " [51] ,Buffer MB51 interrupt" "Not occurred,Occurred" eventfld.long 0x08 18. " [50] ,Buffer MB50 interrupt" "Not occurred,Occurred" eventfld.long 0x08 17. " [49] ,Buffer MB49 interrupt" "Not occurred,Occurred" eventfld.long 0x08 16. " [48] ,Buffer MB48 interrupt" "Not occurred,Occurred" newline eventfld.long 0x08 15. " [47] ,Buffer MB47 interrupt" "Not occurred,Occurred" eventfld.long 0x08 14. " [46] ,Buffer MB46 interrupt" "Not occurred,Occurred" eventfld.long 0x08 13. " [45] ,Buffer MB45 interrupt" "Not occurred,Occurred" eventfld.long 0x08 12. " [44] ,Buffer MB44 interrupt" "Not occurred,Occurred" newline eventfld.long 0x08 11. " [43] ,Buffer MB43 interrupt" "Not occurred,Occurred" eventfld.long 0x08 10. " [42] ,Buffer MB42 interrupt" "Not occurred,Occurred" eventfld.long 0x08 9. " [41] ,Buffer MB41 interrupt" "Not occurred,Occurred" eventfld.long 0x08 8. " [40] ,Buffer MB40 interrupt" "Not occurred,Occurred" newline eventfld.long 0x08 7. " [39] ,Buffer MB39 interrupt" "Not occurred,Occurred" eventfld.long 0x08 6. " [38] ,Buffer MB38 interrupt" "Not occurred,Occurred" eventfld.long 0x08 5. " [37] ,Buffer MB37 interrupt" "Not occurred,Occurred" eventfld.long 0x08 4. " [36] ,Buffer MB36 interrupt" "Not occurred,Occurred" newline eventfld.long 0x08 3. " [35] ,Buffer MB35 interrupt" "Not occurred,Occurred" eventfld.long 0x08 2. " [34] ,Buffer MB34 interrupt" "Not occurred,Occurred" eventfld.long 0x08 1. " [33] ,Buffer MB33 interrupt" "Not occurred,Occurred" eventfld.long 0x08 0. " [32] ,Buffer MB32 interrupt" "Not occurred,Occurred" if (((per.l(ad:0x5A8F0000))&0x20000000)==0x00) group.long 0x30++0x03 line.long 0x00 "IFLAG1,Interrupt Flags 1 Register" eventfld.long 0x00 31. " BUF[31]I ,Buffer MB 31 interrupt" "Not occurred,Occurred" eventfld.long 0x00 30. " [30] ,Buffer MB30 interrupt" "Not occurred,Occurred" eventfld.long 0x00 29. " [29] ,Buffer MB29 interrupt" "Not occurred,Occurred" eventfld.long 0x00 28. " [28] ,Buffer MB28 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 27. " [27] ,Buffer MB27 interrupt" "Not occurred,Occurred" eventfld.long 0x00 26. " [26] ,Buffer MB26 interrupt" "Not occurred,Occurred" eventfld.long 0x00 25. " [25] ,Buffer MB25 interrupt" "Not occurred,Occurred" eventfld.long 0x00 24. " [24] ,Buffer MB24 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 23. " [23] ,Buffer MB23 interrupt" "Not occurred,Occurred" eventfld.long 0x00 22. " [22] ,Buffer MB22 interrupt" "Not occurred,Occurred" eventfld.long 0x00 21. " [21] ,Buffer MB21 interrupt" "Not occurred,Occurred" eventfld.long 0x00 20. " [20] ,Buffer MB20 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 19. " [19] ,Buffer MB19 interrupt" "Not occurred,Occurred" eventfld.long 0x00 18. " [18] ,Buffer MB18 interrupt" "Not occurred,Occurred" eventfld.long 0x00 17. " [17] ,Buffer MB17 interrupt" "Not occurred,Occurred" eventfld.long 0x00 16. " [16] ,Buffer MB16 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 15. " [15] ,Buffer MB15 interrupt" "Not occurred,Occurred" eventfld.long 0x00 14. " [14] ,Buffer MB14 interrupt" "Not occurred,Occurred" eventfld.long 0x00 13. " [13] ,Buffer MB13 interrupt" "Not occurred,Occurred" eventfld.long 0x00 12. " [12] ,Buffer MB12 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 11. " [11] ,Buffer MB11 interrupt" "Not occurred,Occurred" eventfld.long 0x00 10. " [10] ,Buffer MB10 interrupt" "Not occurred,Occurred" eventfld.long 0x00 9. " [9] ,Buffer MB9 interrupt" "Not occurred,Occurred" eventfld.long 0x00 8. " [8] ,Buffer MB8 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 7. " [7] ,Buffer MB7 interrupt" "Not occurred,Occurred" eventfld.long 0x00 6. " [6] ,Buffer MB6 interrupt" "Not occurred,Occurred" eventfld.long 0x00 5. " [5] ,Buffer MB5 interrupt" "Not occurred,Occurred" eventfld.long 0x00 4. " [4] ,Buffer MB4 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 3. " [3] ,Buffer MB3 interrupt" "Not occurred,Occurred" eventfld.long 0x00 2. " [2] ,Buffer MB2 interrupt" "Not occurred,Occurred" eventfld.long 0x00 1. " [1] ,Buffer MB1 interrupt" "Not occurred,Occurred" eventfld.long 0x00 0. " [0] ,Buffer MB0 interrupt" "Not occurred,Occurred" else group.long 0x30++0x03 line.long 0x00 "IFLAG1,Interrupt Flags 1 Register" eventfld.long 0x00 31. " BUF[31]I ,Buffer MB31 interrupt" "Not occurred,Occurred" eventfld.long 0x00 30. " [30] ,Buffer MB30 interrupt" "Not occurred,Occurred" eventfld.long 0x00 29. " [29] ,Buffer MB29 interrupt" "Not occurred,Occurred" eventfld.long 0x00 28. " [28] ,Buffer MB28 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 27. " [27] ,Buffer MB27 interrupt" "Not occurred,Occurred" eventfld.long 0x00 26. " [26] ,Buffer MB26 interrupt" "Not occurred,Occurred" eventfld.long 0x00 25. " [25] ,Buffer MB25 interrupt" "Not occurred,Occurred" eventfld.long 0x00 24. " [24] ,Buffer MB24 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 23. " [23] ,Buffer MB23 interrupt" "Not occurred,Occurred" eventfld.long 0x00 22. " [22] ,Buffer MB22 interrupt" "Not occurred,Occurred" eventfld.long 0x00 21. " [21] ,Buffer MB21 interrupt" "Not occurred,Occurred" eventfld.long 0x00 20. " [20] ,Buffer MB20 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 19. " [19] ,Buffer MB19 interrupt" "Not occurred,Occurred" eventfld.long 0x00 18. " [18] ,Buffer MB18 interrupt" "Not occurred,Occurred" eventfld.long 0x00 17. " [17] ,Buffer MB17 interrupt" "Not occurred,Occurred" eventfld.long 0x00 16. " [16] ,Buffer MB16 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 15. " [15] ,Buffer MB15 interrupt" "Not occurred,Occurred" eventfld.long 0x00 14. " [14] ,Buffer MB14 interrupt" "Not occurred,Occurred" eventfld.long 0x00 13. " [13] ,Buffer MB13 interrupt" "Not occurred,Occurred" eventfld.long 0x00 12. " [12] ,Buffer MB12 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 11. " [11] ,Buffer MB11 interrupt" "Not occurred,Occurred" eventfld.long 0x00 10. " [10] ,Buffer MB10 interrupt" "Not occurred,Occurred" eventfld.long 0x00 9. " [9] ,Buffer MB9 interrupt" "Not occurred,Occurred" eventfld.long 0x00 8. " [8] ,Buffer MB8 interrupt" "Not occurred,Occurred" newline eventfld.long 0x00 7. " [7] ,Rx FIFO overflow" "No overflow,Overflow" eventfld.long 0x00 6. " [6] ,Rx FIFO almost full warning" "< 5 unread messages in FIFO,> 5 unread messages in FIFO" eventfld.long 0x00 5. " [5] ,Least one frame is available to be read from the FIFO" "Not available,Available" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long 0x34++0x03 line.long 0x00 "CTRL2,Control 2 Register" bitfld.long 0x00 31. " ERRMSK_FAST ,Error interrupt mask for errors detected in the data phase of fast CAN FD frames" "Disabled,Enabled" bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Disabled,Enabled" bitfld.long 0x00 24.--27. " RFFN ,Number of Rx FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128,?..." bitfld.long 0x00 19.--23. " TASD ,Tx arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "Rx FIFO first,Mailboxes first" bitfld.long 0x00 17. " RRS ,Remote request storing" "Remote response generated,Remote request stored" bitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for Rx mailboxes" "Disabled,Enabled" newline bitfld.long 0x00 14. " PREXCEN ,Protocol exception enable" "Disabled,Enabled" bitfld.long 0x00 12. " ISOCANFDEN ,ISO CAN FD enable" "Disabled,Enabled" bitfld.long 0x00 11. " EDFLTDIS ,Edge filter disable" "No,Yes" else group.long 0x34++0x03 line.long 0x00 "CTRL2,Control 2 Register" bitfld.long 0x00 31. " ERRMSK_FAST ,Error interrupt mask for errors detected in the data phase of fast CAN FD frames" "Disabled,Enabled" bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 24.--27. " RFFN ,Number of Rx FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128,?..." rbitfld.long 0x00 19.--23. " TASD ,Tx arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "Rx FIFO first,Mailboxes first" rbitfld.long 0x00 17. " RRS ,Remote request storing" "Remote response generated,Remote request stored" rbitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for Rx mailboxes" "Disabled,Enabled" rbitfld.long 0x00 15. " TIMER_SRC ,Timer source" "CAN bit clock,External time tick" newline rbitfld.long 0x00 14. " PREXCEN ,Protocol exception enable" "Disabled,Enabled" rbitfld.long 0x00 12. " ISOCANFDEN ,ISO CAN FD enable" "Disabled,Enabled" rbitfld.long 0x00 11. " EDFLTDIS ,Edge filter disable" "No,Yes" endif rgroup.long 0x38++0x03 line.long 0x00 "ESR2,Error And Status Register 2" hexmask.long.byte 0x00 16.--22. 1. " LPTM ,Lowest priority Tx mailbox" bitfld.long 0x00 14. " VPS ,Valid priority status" "Not valid,Valid" bitfld.long 0x00 13. " IMB ,Inactive mailbox available" "Not available,Available" rgroup.long 0x44++0x03 line.long 0x00 "CRCR,CRC Register" hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,CRC mailbox number" hexmask.long.word 0x00 0.--14. 1. " TXCRC ,CRC value of the last message transmitted" if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long 0x48++0x03 line.long 0x00 "RXFGMASK,Rx FIFO Global Mask Register" bitfld.long 0x00 31. " FGM[31] ,Rx FIFO global mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Rx FIFO global mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Rx FIFO global mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Rx FIFO global mask bit 28" "0,1" newline bitfld.long 0x00 27. " [27] ,Rx FIFO global mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Rx FIFO global mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Rx FIFO global mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Rx FIFO global mask bit 24" "0,1" newline bitfld.long 0x00 23. " [23] ,Rx FIFO global mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Rx FIFO global mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Rx FIFO global mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Rx FIFO global mask bit 20" "0,1" newline bitfld.long 0x00 19. " [19] ,Rx FIFO global mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Rx FIFO global mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Rx FIFO global mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Rx FIFO global mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Rx FIFO global mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Rx FIFO global mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Rx FIFO global mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Rx FIFO global mask bit 12" "0,1" newline bitfld.long 0x00 11. " [11] ,Rx FIFO global mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Rx FIFO global mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Rx FIFO global mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Rx FIFO global mask bit 8" "0,1" newline bitfld.long 0x00 7. " [7] ,Rx FIFO global mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Rx FIFO global mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Rx FIFO global mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Rx FIFO global mask bit 4" "0,1" newline bitfld.long 0x00 3. " [3] ,Rx FIFO global mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Rx FIFO global mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Rx FIFO global mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Rx FIFO global mask bit 0" "0,1" else rgroup.long 0x48++0x03 line.long 0x00 "RXFGMASK,Rx FIFO Global Mask Register" bitfld.long 0x00 31. " FGM[31] ,Rx FIFO global mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Rx FIFO global mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Rx FIFO global mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Rx FIFO global mask bit 28" "0,1" newline bitfld.long 0x00 27. " [27] ,Rx FIFO global mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Rx FIFO global mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Rx FIFO global mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Rx FIFO global mask bit 24" "0,1" newline bitfld.long 0x00 23. " [23] ,Rx FIFO global mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Rx FIFO global mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Rx FIFO global mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Rx FIFO global mask bit 20" "0,1" newline bitfld.long 0x00 19. " [19] ,Rx FIFO global mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Rx FIFO global mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Rx FIFO global mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Rx FIFO global mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Rx FIFO global mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Rx FIFO global mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Rx FIFO global mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Rx FIFO global mask bit 12" "0,1" newline bitfld.long 0x00 11. " [11] ,Rx FIFO global mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Rx FIFO global mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Rx FIFO global mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Rx FIFO global mask bit 8" "0,1" newline bitfld.long 0x00 7. " [7] ,Rx FIFO global mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Rx FIFO global mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Rx FIFO global mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Rx FIFO global mask bit 4" "0,1" newline bitfld.long 0x00 3. " [3] ,Rx FIFO global mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Rx FIFO global mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Rx FIFO global mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Rx FIFO global mask bit 0" "0,1" endif rgroup.long 0x4C++0x03 line.long 0x00 "RXFIR,Rx FIFO Information Register" hexmask.long.word 0x00 0.--8. 1. " IDHIT ,Identifier acceptance filter hit by the received message" if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long 0x50++0x03 line.long 0x00 "CBT,CAN Bit Timing Register" bitfld.long 0x00 31. " BTF ,Bit timing format enable" "Disabled,Enabled" hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,Extended prescaler division factor" bitfld.long 0x00 16.--20. " ERJW ,Extended resync jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--15. " EPROPSEG ,Extended propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 5.--9. " EPSEG1 ,Extended phase segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " EPSEG2 ,Extended phase segment 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else rgroup.long 0x50++0x03 line.long 0x00 "CBT,CAN Bit Timing Register" bitfld.long 0x00 31. " BTF ,Bit timing format enable" "Disabled,Enabled" hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,Extended prescaler division factor" bitfld.long 0x00 16.--20. " ERJW ,Extended resync jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--15. " EPROPSEG ,Extended propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 5.--9. " EPSEG1 ,Extended phase segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " EPSEG2 ,Extended phase segment 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif tree "Rx Individual Mask Registers 0-63" if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x0+0x880)++0x03 line.long 0x00 "RXIMR0,Rx Individual Mask Register 0" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x0+0x880)++0x03 line.long 0x00 "RXIMR0,Rx Individual Mask Register 0" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x4+0x880)++0x03 line.long 0x00 "RXIMR1,Rx Individual Mask Register 1" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x4+0x880)++0x03 line.long 0x00 "RXIMR1,Rx Individual Mask Register 1" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x8+0x880)++0x03 line.long 0x00 "RXIMR2,Rx Individual Mask Register 2" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x8+0x880)++0x03 line.long 0x00 "RXIMR2,Rx Individual Mask Register 2" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0xC+0x880)++0x03 line.long 0x00 "RXIMR3,Rx Individual Mask Register 3" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xC+0x880)++0x03 line.long 0x00 "RXIMR3,Rx Individual Mask Register 3" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x10+0x880)++0x03 line.long 0x00 "RXIMR4,Rx Individual Mask Register 4" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x10+0x880)++0x03 line.long 0x00 "RXIMR4,Rx Individual Mask Register 4" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x14+0x880)++0x03 line.long 0x00 "RXIMR5,Rx Individual Mask Register 5" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x14+0x880)++0x03 line.long 0x00 "RXIMR5,Rx Individual Mask Register 5" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x18+0x880)++0x03 line.long 0x00 "RXIMR6,Rx Individual Mask Register 6" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x18+0x880)++0x03 line.long 0x00 "RXIMR6,Rx Individual Mask Register 6" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x1C+0x880)++0x03 line.long 0x00 "RXIMR7,Rx Individual Mask Register 7" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x1C+0x880)++0x03 line.long 0x00 "RXIMR7,Rx Individual Mask Register 7" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x20+0x880)++0x03 line.long 0x00 "RXIMR8,Rx Individual Mask Register 8" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x20+0x880)++0x03 line.long 0x00 "RXIMR8,Rx Individual Mask Register 8" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x24+0x880)++0x03 line.long 0x00 "RXIMR9,Rx Individual Mask Register 9" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x24+0x880)++0x03 line.long 0x00 "RXIMR9,Rx Individual Mask Register 9" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x28+0x880)++0x03 line.long 0x00 "RXIMR10,Rx Individual Mask Register 10" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x28+0x880)++0x03 line.long 0x00 "RXIMR10,Rx Individual Mask Register 10" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x2C+0x880)++0x03 line.long 0x00 "RXIMR11,Rx Individual Mask Register 11" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x2C+0x880)++0x03 line.long 0x00 "RXIMR11,Rx Individual Mask Register 11" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x30+0x880)++0x03 line.long 0x00 "RXIMR12,Rx Individual Mask Register 12" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x30+0x880)++0x03 line.long 0x00 "RXIMR12,Rx Individual Mask Register 12" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x34+0x880)++0x03 line.long 0x00 "RXIMR13,Rx Individual Mask Register 13" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x34+0x880)++0x03 line.long 0x00 "RXIMR13,Rx Individual Mask Register 13" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x38+0x880)++0x03 line.long 0x00 "RXIMR14,Rx Individual Mask Register 14" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x38+0x880)++0x03 line.long 0x00 "RXIMR14,Rx Individual Mask Register 14" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x3C+0x880)++0x03 line.long 0x00 "RXIMR15,Rx Individual Mask Register 15" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x3C+0x880)++0x03 line.long 0x00 "RXIMR15,Rx Individual Mask Register 15" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x40+0x880)++0x03 line.long 0x00 "RXIMR16,Rx Individual Mask Register 16" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x40+0x880)++0x03 line.long 0x00 "RXIMR16,Rx Individual Mask Register 16" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x44+0x880)++0x03 line.long 0x00 "RXIMR17,Rx Individual Mask Register 17" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x44+0x880)++0x03 line.long 0x00 "RXIMR17,Rx Individual Mask Register 17" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x48+0x880)++0x03 line.long 0x00 "RXIMR18,Rx Individual Mask Register 18" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x48+0x880)++0x03 line.long 0x00 "RXIMR18,Rx Individual Mask Register 18" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x4C+0x880)++0x03 line.long 0x00 "RXIMR19,Rx Individual Mask Register 19" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x4C+0x880)++0x03 line.long 0x00 "RXIMR19,Rx Individual Mask Register 19" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x50+0x880)++0x03 line.long 0x00 "RXIMR20,Rx Individual Mask Register 20" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x50+0x880)++0x03 line.long 0x00 "RXIMR20,Rx Individual Mask Register 20" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x54+0x880)++0x03 line.long 0x00 "RXIMR21,Rx Individual Mask Register 21" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x54+0x880)++0x03 line.long 0x00 "RXIMR21,Rx Individual Mask Register 21" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x58+0x880)++0x03 line.long 0x00 "RXIMR22,Rx Individual Mask Register 22" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x58+0x880)++0x03 line.long 0x00 "RXIMR22,Rx Individual Mask Register 22" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x5C+0x880)++0x03 line.long 0x00 "RXIMR23,Rx Individual Mask Register 23" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x5C+0x880)++0x03 line.long 0x00 "RXIMR23,Rx Individual Mask Register 23" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x60+0x880)++0x03 line.long 0x00 "RXIMR24,Rx Individual Mask Register 24" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x60+0x880)++0x03 line.long 0x00 "RXIMR24,Rx Individual Mask Register 24" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x64+0x880)++0x03 line.long 0x00 "RXIMR25,Rx Individual Mask Register 25" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x64+0x880)++0x03 line.long 0x00 "RXIMR25,Rx Individual Mask Register 25" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x68+0x880)++0x03 line.long 0x00 "RXIMR26,Rx Individual Mask Register 26" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x68+0x880)++0x03 line.long 0x00 "RXIMR26,Rx Individual Mask Register 26" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x6C+0x880)++0x03 line.long 0x00 "RXIMR27,Rx Individual Mask Register 27" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x6C+0x880)++0x03 line.long 0x00 "RXIMR27,Rx Individual Mask Register 27" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x70+0x880)++0x03 line.long 0x00 "RXIMR28,Rx Individual Mask Register 28" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x70+0x880)++0x03 line.long 0x00 "RXIMR28,Rx Individual Mask Register 28" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x74+0x880)++0x03 line.long 0x00 "RXIMR29,Rx Individual Mask Register 29" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x74+0x880)++0x03 line.long 0x00 "RXIMR29,Rx Individual Mask Register 29" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x78+0x880)++0x03 line.long 0x00 "RXIMR30,Rx Individual Mask Register 30" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x78+0x880)++0x03 line.long 0x00 "RXIMR30,Rx Individual Mask Register 30" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x7C+0x880)++0x03 line.long 0x00 "RXIMR31,Rx Individual Mask Register 31" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x7C+0x880)++0x03 line.long 0x00 "RXIMR31,Rx Individual Mask Register 31" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x80+0x880)++0x03 line.long 0x00 "RXIMR32,Rx Individual Mask Register 32" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x80+0x880)++0x03 line.long 0x00 "RXIMR32,Rx Individual Mask Register 32" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x84+0x880)++0x03 line.long 0x00 "RXIMR33,Rx Individual Mask Register 33" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x84+0x880)++0x03 line.long 0x00 "RXIMR33,Rx Individual Mask Register 33" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x88+0x880)++0x03 line.long 0x00 "RXIMR34,Rx Individual Mask Register 34" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x88+0x880)++0x03 line.long 0x00 "RXIMR34,Rx Individual Mask Register 34" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x8C+0x880)++0x03 line.long 0x00 "RXIMR35,Rx Individual Mask Register 35" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x8C+0x880)++0x03 line.long 0x00 "RXIMR35,Rx Individual Mask Register 35" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x90+0x880)++0x03 line.long 0x00 "RXIMR36,Rx Individual Mask Register 36" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x90+0x880)++0x03 line.long 0x00 "RXIMR36,Rx Individual Mask Register 36" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x94+0x880)++0x03 line.long 0x00 "RXIMR37,Rx Individual Mask Register 37" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x94+0x880)++0x03 line.long 0x00 "RXIMR37,Rx Individual Mask Register 37" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x98+0x880)++0x03 line.long 0x00 "RXIMR38,Rx Individual Mask Register 38" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x98+0x880)++0x03 line.long 0x00 "RXIMR38,Rx Individual Mask Register 38" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0x9C+0x880)++0x03 line.long 0x00 "RXIMR39,Rx Individual Mask Register 39" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0x9C+0x880)++0x03 line.long 0x00 "RXIMR39,Rx Individual Mask Register 39" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0xA0+0x880)++0x03 line.long 0x00 "RXIMR40,Rx Individual Mask Register 40" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xA0+0x880)++0x03 line.long 0x00 "RXIMR40,Rx Individual Mask Register 40" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0xA4+0x880)++0x03 line.long 0x00 "RXIMR41,Rx Individual Mask Register 41" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xA4+0x880)++0x03 line.long 0x00 "RXIMR41,Rx Individual Mask Register 41" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0xA8+0x880)++0x03 line.long 0x00 "RXIMR42,Rx Individual Mask Register 42" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xA8+0x880)++0x03 line.long 0x00 "RXIMR42,Rx Individual Mask Register 42" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0xAC+0x880)++0x03 line.long 0x00 "RXIMR43,Rx Individual Mask Register 43" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xAC+0x880)++0x03 line.long 0x00 "RXIMR43,Rx Individual Mask Register 43" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0xB0+0x880)++0x03 line.long 0x00 "RXIMR44,Rx Individual Mask Register 44" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xB0+0x880)++0x03 line.long 0x00 "RXIMR44,Rx Individual Mask Register 44" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0xB4+0x880)++0x03 line.long 0x00 "RXIMR45,Rx Individual Mask Register 45" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xB4+0x880)++0x03 line.long 0x00 "RXIMR45,Rx Individual Mask Register 45" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0xB8+0x880)++0x03 line.long 0x00 "RXIMR46,Rx Individual Mask Register 46" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xB8+0x880)++0x03 line.long 0x00 "RXIMR46,Rx Individual Mask Register 46" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0xBC+0x880)++0x03 line.long 0x00 "RXIMR47,Rx Individual Mask Register 47" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xBC+0x880)++0x03 line.long 0x00 "RXIMR47,Rx Individual Mask Register 47" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0xC0+0x880)++0x03 line.long 0x00 "RXIMR48,Rx Individual Mask Register 48" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xC0+0x880)++0x03 line.long 0x00 "RXIMR48,Rx Individual Mask Register 48" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0xC4+0x880)++0x03 line.long 0x00 "RXIMR49,Rx Individual Mask Register 49" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xC4+0x880)++0x03 line.long 0x00 "RXIMR49,Rx Individual Mask Register 49" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0xC8+0x880)++0x03 line.long 0x00 "RXIMR50,Rx Individual Mask Register 50" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xC8+0x880)++0x03 line.long 0x00 "RXIMR50,Rx Individual Mask Register 50" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0xCC+0x880)++0x03 line.long 0x00 "RXIMR51,Rx Individual Mask Register 51" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xCC+0x880)++0x03 line.long 0x00 "RXIMR51,Rx Individual Mask Register 51" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0xD0+0x880)++0x03 line.long 0x00 "RXIMR52,Rx Individual Mask Register 52" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xD0+0x880)++0x03 line.long 0x00 "RXIMR52,Rx Individual Mask Register 52" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0xD4+0x880)++0x03 line.long 0x00 "RXIMR53,Rx Individual Mask Register 53" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xD4+0x880)++0x03 line.long 0x00 "RXIMR53,Rx Individual Mask Register 53" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0xD8+0x880)++0x03 line.long 0x00 "RXIMR54,Rx Individual Mask Register 54" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xD8+0x880)++0x03 line.long 0x00 "RXIMR54,Rx Individual Mask Register 54" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0xDC+0x880)++0x03 line.long 0x00 "RXIMR55,Rx Individual Mask Register 55" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xDC+0x880)++0x03 line.long 0x00 "RXIMR55,Rx Individual Mask Register 55" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0xE0+0x880)++0x03 line.long 0x00 "RXIMR56,Rx Individual Mask Register 56" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xE0+0x880)++0x03 line.long 0x00 "RXIMR56,Rx Individual Mask Register 56" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0xE4+0x880)++0x03 line.long 0x00 "RXIMR57,Rx Individual Mask Register 57" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xE4+0x880)++0x03 line.long 0x00 "RXIMR57,Rx Individual Mask Register 57" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0xE8+0x880)++0x03 line.long 0x00 "RXIMR58,Rx Individual Mask Register 58" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xE8+0x880)++0x03 line.long 0x00 "RXIMR58,Rx Individual Mask Register 58" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0xEC+0x880)++0x03 line.long 0x00 "RXIMR59,Rx Individual Mask Register 59" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xEC+0x880)++0x03 line.long 0x00 "RXIMR59,Rx Individual Mask Register 59" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0xF0+0x880)++0x03 line.long 0x00 "RXIMR60,Rx Individual Mask Register 60" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xF0+0x880)++0x03 line.long 0x00 "RXIMR60,Rx Individual Mask Register 60" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0xF4+0x880)++0x03 line.long 0x00 "RXIMR61,Rx Individual Mask Register 61" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xF4+0x880)++0x03 line.long 0x00 "RXIMR61,Rx Individual Mask Register 61" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0xF8+0x880)++0x03 line.long 0x00 "RXIMR62,Rx Individual Mask Register 62" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xF8+0x880)++0x03 line.long 0x00 "RXIMR62,Rx Individual Mask Register 62" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long (0xFC+0x880)++0x03 line.long 0x00 "RXIMR63,Rx Individual Mask Register 63" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" else rgroup.long (0xFC+0x880)++0x03 line.long 0x00 "RXIMR63,Rx Individual Mask Register 63" bitfld.long 0x00 31. " MI[31] ,Standard ID mask bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Standard ID mask bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Standard ID mask bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Standard ID mask bit 28" "0,1" bitfld.long 0x00 27. " [27] ,Standard ID mask bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Standard ID mask bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Standard ID mask bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Standard ID mask bit 24" "0,1" bitfld.long 0x00 23. " [23] ,Standard ID mask bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Standard ID mask bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Standard ID mask bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Standard ID mask bit 20" "0,1" bitfld.long 0x00 19. " [19] ,Standard ID mask bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Standard ID mask bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Standard ID mask bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Standard ID mask bit 16" "0,1" newline bitfld.long 0x00 15. " [15] ,Standard ID mask bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Standard ID mask bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Standard ID mask bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Standard ID mask bit 12" "0,1" bitfld.long 0x00 11. " [11] ,Standard ID mask bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Standard ID mask bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Standard ID mask bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Standard ID mask bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Standard ID mask bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Standard ID mask bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Standard ID mask bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Standard ID mask bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Standard ID mask bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Standard ID mask bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Standard ID mask bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Standard ID mask bit 0" "0,1" endif tree.end newline if (((per.l(ad:0x5A8F0000+0x00))&0x50000000)==0x50000000) group.long 0xC00++0x07 line.long 0x00 "FDCTRL,CAN FD Control Register" bitfld.long 0x00 31. " FDRATE ,Bit rate switch enable" "Disabled,Enabled" bitfld.long 0x00 19.--20. " MBDSR1 ,Message buffer data size for region 1" "8 bytes,16 bytes,32 bytes,64 bytes" bitfld.long 0x00 16.--17. " MBDSR0 ,Message buffer data size for region 0" "8 bytes,16 bytes,32 bytes,64 bytes" bitfld.long 0x00 15. " TDCEN ,Transceiver delay compensation enable" "Disabled,Enabled" newline eventfld.long 0x00 14. " TDCFAIL ,Transceiver delay compensation fail" "In range,Out of range" bitfld.long 0x00 8.--12. " TDCOFF ,Transceiver delay compensation offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--5. " TDCVAL ,Transceiver delay compensation value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "FDCBT,CAN FD Bit Timing Register" hexmask.long.word 0x04 20.--29. 1. " FPRESDIV ,Fast prescaler division factor" bitfld.long 0x04 16.--18. " FRJW ,Fast resync jump width" "0,1,2,3,4,5,6,7" bitfld.long 0x04 10.--14. " FPROPSEG ,Fast propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 5.--7. " FPSEG1 ,Fast phase segment 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 0.--2. " FPSEG2 ,Fast phase segment 2" "0,1,2,3,4,5,6,7" else group.long 0xC00++0x03 line.long 0x00 "FDCTRL,CAN FD Control Register" bitfld.long 0x00 31. " FDRATE ,Bit rate switch enable" "Disabled,Enabled" bitfld.long 0x00 19.--20. " MBDSR1 ,Message buffer data size for region 1" "8 bytes,16 bytes,32 bytes,64 bytes" rbitfld.long 0x00 16.--17. " MBDSR0 ,Message buffer data size for region 0" "8 bytes,16 bytes,32 bytes,64 bytes" rbitfld.long 0x00 15. " TDCEN ,Transceiver delay compensation enable" "Disabled,Enabled" newline eventfld.long 0x00 14. " TDCFAIL ,Transceiver delay compensation fail" "In range,Out of range" rbitfld.long 0x00 8.--12. " TDCOFF ,Transceiver delay compensation offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--5. " TDCVAL ,Transceiver delay compensation value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0xC04++0x03 line.long 0x00 "FDCBT,CAN FD Bit Timing Register" hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,Fast prescaler division factor" bitfld.long 0x00 16.--18. " FRJW ,Fast resync jump width" "1,2,3,4,5,6,7,8" bitfld.long 0x00 10.--14. " FPROPSEG ,Fast propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--7. " FPSEG1 ,Fast phase segment 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--2. " FPSEG2 ,Fast phase segment 2" "0,1,2,3,4,5,6,7" endif rgroup.long 0xC08++0x03 line.long 0x00 "FDCRC,CAN FD CRC Register" hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,CRC mailbox number for FD_TXCRC" hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCRC ,Extended transmitted CRC value" width 0x0B tree.end tree.end tree.open "FTM (FlexTimer)" tree "FTM0" base ad:0x5A8A0000 width 12. if (((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04) group.long 0x00++0x03 line.long 0x00 "SC,Status And Control Register" bitfld.long 0x00 24.--27. " FLTPS ,Filter prescaler" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 23. " PWMEN[23] ,Channel 23 PWM enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Channel 22 PWM enable bit" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Channel 21 PWM enable bit" "Disabled,Enabled" newline bitfld.long 0x00 20. " [20] ,Channel 20 PWM enable bit" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Channel 19 PWM enable bit" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Channel 18 PWM enable bit" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Channel 17 PWM enable bit" "Disabled,Enabled" newline bitfld.long 0x00 16. " [16] ,Channel 16 PWM enable bit" "Disabled,Enabled" rbitfld.long 0x00 9. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 8. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 7. " RF ,Reload flag" "No reload,Reload" newline bitfld.long 0x00 6. " RIE ,Reload point interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting mode,Up-Down counting mode" bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clock,FTM clock,Fixed clock,External clock" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "SC,Status And Control Register" bitfld.long 0x00 24.--27. " FLTPS ,Filter prescaler" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 23. " PWMEN[23] ,Channel 23 PWM enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Channel 22 PWM enable bit" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Channel 21 PWM enable bit" "Disabled,Enabled" newline bitfld.long 0x00 20. " [20] ,Channel 20 PWM enable bit" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Channel 19 PWM enable bit" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Channel 18 PWM enable bit" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Channel 17 PWM enable bit" "Disabled,Enabled" newline bitfld.long 0x00 16. " [16] ,Channel 16 PWM enable bit" "Disabled,Enabled" rbitfld.long 0x00 9. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 8. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 7. " RF ,Reload flag" "No reload,Reload" newline bitfld.long 0x00 6. " RIE ,Reload point interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting mode,Up-Down counting mode" rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clock,FTM clock,Fixed clock,External clock" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif group.long 0x04++0x07 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "MOD,Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" if ((((per.l(ad:0x5A8A0000+0x64))&0x05)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0xC))&0x30)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (0) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (0) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (0) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (0) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x05)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0xC))&0x30)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (0) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (0) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (0) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (0) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x05)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0xC))&0x30)==0x10)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (0) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (0) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (0) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (0) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x05)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0xC))&0x30)==0x10)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (0) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (0) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (0) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (0) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x05)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0xC))&0x30)==(0x20||0x30))&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (0) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (0) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (0) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (0) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x05)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0xC))&0x30)==(0x20||0x30))&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (0) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (0) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (0) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (0) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x05)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x20)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (0) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (0) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (0) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (0) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x05)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x20)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (0) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (0) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (0) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (0) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x05)==0x01)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (0) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (0) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (0) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (0) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x05)==0x01)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (0) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (0) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (0) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (0) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x05)==0x04)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (0) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (0) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (0) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (0) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x05)==0x04)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (0) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (0) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (0) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (0) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0xC++0x03 hide.long 0x00 "C0SC,Channel (0) Status And Control Register" newline endif group.long (0xC+0x04)++0x03 line.long 0x00 "C0V,Channel (0) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x5A8A0000+0x64))&0x05)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x14))&0x30)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (1) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (1) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (1) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (1) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x05)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x14))&0x30)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (1) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (1) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (1) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (1) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x05)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x14))&0x30)==0x10)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (1) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (1) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (1) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (1) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x05)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x14))&0x30)==0x10)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (1) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (1) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (1) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (1) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x05)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x14))&0x30)==(0x20||0x30))&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (1) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (1) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (1) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (1) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x05)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x14))&0x30)==(0x20||0x30))&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (1) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (1) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (1) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (1) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x05)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x20)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (1) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (1) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (1) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (1) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x05)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x20)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (1) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (1) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (1) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (1) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x05)==0x01)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (1) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (1) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (1) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (1) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x05)==0x01)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (1) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (1) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (1) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (1) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x05)==0x04)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (1) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (1) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (1) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (1) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x05)==0x04)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (1) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (1) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (1) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (1) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x14++0x03 hide.long 0x00 "C1SC,Channel (1) Status And Control Register" newline endif group.long (0x14+0x04)++0x03 line.long 0x00 "C1V,Channel (1) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x5A8A0000+0x64))&0x500)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x1C))&0x30)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (2) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (2) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (2) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (2) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x500)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x1C))&0x30)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (2) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (2) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (2) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (2) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x500)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x1C))&0x30)==0x10)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (2) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (2) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (2) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (2) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x500)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x1C))&0x30)==0x10)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (2) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (2) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (2) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (2) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x500)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x1C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (2) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (2) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (2) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (2) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x500)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x1C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (2) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (2) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (2) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (2) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x500)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x20)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (2) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (2) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (2) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (2) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x500)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x20)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (2) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (2) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (2) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (2) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x500)==0x100)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (2) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (2) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (2) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (2) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x500)==0x100)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (2) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (2) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (2) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (2) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x500)==0x400)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (2) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (2) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (2) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (2) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x500)==0x400)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (2) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (2) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (2) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (2) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x1C++0x03 hide.long 0x00 "C2SC,Channel (2) Status And Control Register" newline endif group.long (0x1C+0x04)++0x03 line.long 0x00 "C2V,Channel (2) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x5A8A0000+0x64))&0x500)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x24))&0x30)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (3) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (3) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (3) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (3) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x500)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x24))&0x30)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (3) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (3) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (3) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (3) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x500)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x24))&0x30)==0x10)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (3) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (3) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (3) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (3) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x500)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x24))&0x30)==0x10)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (3) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (3) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (3) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (3) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x500)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x24))&0x30)==(0x20||0x30))&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (3) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (3) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (3) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (3) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x500)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x24))&0x30)==(0x20||0x30))&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (3) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (3) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (3) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (3) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x500)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x20)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (3) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (3) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (3) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (3) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x500)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x20)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (3) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (3) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (3) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (3) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x500)==0x100)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (3) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (3) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (3) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (3) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x500)==0x100)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (3) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (3) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (3) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (3) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x500)==0x400)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (3) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (3) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (3) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (3) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x500)==0x400)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (3) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (3) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (3) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (3) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x24++0x03 hide.long 0x00 "C3SC,Channel (3) Status And Control Register" newline endif group.long (0x24+0x04)++0x03 line.long 0x00 "C3V,Channel (3) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x5A8A0000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x2C))&0x30)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (4) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (4) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (4) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (4) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x2C))&0x30)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (4) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (4) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (4) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (4) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x2C))&0x30)==0x10)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (4) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (4) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (4) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (4) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x2C))&0x30)==0x10)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (4) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (4) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (4) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (4) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x2C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (4) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (4) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (4) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (4) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x2C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (4) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (4) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (4) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (4) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x20)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (4) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (4) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (4) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (4) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x20)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (4) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (4) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (4) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (4) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x50000)==0x10000)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (4) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (4) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (4) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (4) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x50000)==0x10000)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (4) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (4) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (4) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (4) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x50000)==0x40000)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (4) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (4) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (4) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (4) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x50000)==0x40000)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (4) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (4) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (4) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (4) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x2C++0x03 hide.long 0x00 "C4SC,Channel (4) Status And Control Register" newline endif group.long (0x2C+0x04)++0x03 line.long 0x00 "C4V,Channel (4) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x5A8A0000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x34))&0x30)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (5) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (5) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (5) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (5) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x34))&0x30)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (5) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (5) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (5) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (5) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x34))&0x30)==0x10)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (5) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (5) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (5) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (5) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x34))&0x30)==0x10)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (5) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (5) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (5) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (5) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x34))&0x30)==(0x20||0x30))&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (5) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (5) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (5) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (5) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x34))&0x30)==(0x20||0x30))&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (5) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (5) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (5) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (5) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x20)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (5) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (5) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (5) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (5) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x20)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (5) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (5) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (5) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (5) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x50000)==0x10000)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (5) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (5) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (5) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (5) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x50000)==0x10000)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (5) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (5) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (5) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (5) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x50000)==0x40000)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (5) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (5) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (5) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (5) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x50000)==0x40000)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (5) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (5) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (5) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (5) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x34++0x03 hide.long 0x00 "C5SC,Channel (5) Status And Control Register" newline endif group.long (0x34+0x04)++0x03 line.long 0x00 "C5V,Channel (5) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x5A8A0000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x3C))&0x30)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (6) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (6) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (6) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (6) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x3C))&0x30)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (6) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (6) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (6) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (6) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x3C))&0x30)==0x10)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (6) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (6) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (6) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (6) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x3C))&0x30)==0x10)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (6) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (6) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (6) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (6) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x3C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (6) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (6) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (6) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (6) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x3C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (6) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (6) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (6) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (6) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x20)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (6) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (6) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (6) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (6) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x20)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (6) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (6) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (6) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (6) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x5000000)==0x1000000)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (6) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (6) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (6) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (6) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x5000000)==0x1000000)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (6) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (6) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (6) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (6) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x5000000)==0x4000000)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (6) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (6) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (6) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (6) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x5000000)==0x4000000)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (6) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (6) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (6) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (6) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x3C++0x03 hide.long 0x00 "C6SC,Channel (6) Status And Control Register" newline endif group.long (0x3C+0x04)++0x03 line.long 0x00 "C6V,Channel (6) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x5A8A0000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x44))&0x30)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (7) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (7) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (7) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (7) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x44))&0x30)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (7) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (7) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (7) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (7) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x44))&0x30)==0x10)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (7) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (7) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (7) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (7) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x44))&0x30)==0x10)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (7) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (7) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (7) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (7) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x44))&0x30)==(0x20||0x30))&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (7) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (7) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (7) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (7) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x44))&0x30)==(0x20||0x30))&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (7) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (7) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (7) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (7) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x20)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (7) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (7) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (7) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (7) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x5A8A0000))&0x20)==0x20)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (7) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (7) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (7) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (7) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x5000000)==0x1000000)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (7) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (7) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (7) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (7) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x5000000)==0x1000000)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (7) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (7) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (7) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (7) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x5000000)==0x4000000)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (7) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (7) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (7) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (7) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8A0000+0x64))&0x5000000)==0x4000000)&&(((per.l(ad:0x5A8A0000))&0x20)==0x00)&&(((per.l(ad:0x5A8A0000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (7) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (7) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (7) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (7) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x44++0x03 hide.long 0x00 "C7SC,Channel (7) Status And Control Register" newline endif group.long (0x44+0x04)++0x03 line.long 0x00 "C7V,Channel (7) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x4C++0x03 line.long 0x00 "CNTIN,Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of the FTM counter" newline hgroup.long 0x50++0x03 hide.long 0x00 "STATUS,Capture And Compare Status Register" in newline if (((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04) group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channels/Manual clear,All channels/Manual clear,All channels/Automatic clear" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode" "Disabled,Enabled" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Channel output initialization" "No effect,Initialize" bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault Control Mode" "Disabled,Even channels/Manual clear,All channels/Manual clear,All channels/Automatic clear" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode" "Disabled,Enabled" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Channel output initialization" "No effect,Initialize" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "SYNC,Synchronization Register" newline bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Rising edges,PWM synchronization" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Count normally,Trigger detected" bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "OUTINIT,Initial State For Channels Output Register" bitfld.long 0x04 7. " CH[7]OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " [6] ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " [5] ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " [4] ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " [3] ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " [2] ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " [1] ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " [0] ,Channel 0 output initialization value" "0,1" line.long 0x08 "OUTMASK,Output Mask Register" bitfld.long 0x08 7. " CH[7]OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " [6] ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " [5] ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " [4] ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " [3] ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " [2] ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " [1] ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " [0] ,Channel 0 output mask" "Not masked,Masked" if (((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04) group.long 0x64++0x07 line.long 0x00 "COMBINE,Function For Linked Channels Register" bitfld.long 0x00 31. " MCOMBINE3 ,Modified combine mode for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 30. " FAULTEN3 ,Fault control for channels 6 and 7 enable" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,Synchronization for channels 6 and 7 enable" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime insertion in channels 6 and 7 enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures for channels 6 and 7" "Inactive,Active" bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture for channels 6 and 7 enable" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complement mode of channel 6 and 7" "Disabled,Enabled" bitfld.long 0x00 24. " COMBINE3 ,Combine mode for channels 6 and 7" "Disabled,Enabled" newline bitfld.long 0x00 23. " MCOMBINE2 ,Modified combine mode for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 22. " FAULTEN2 ,Fault control for channels 4 and 5 enable" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,Synchronization for channels 4 and 5 enable" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime insertion in channels 4 and 5 enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures for channels 4 and 5" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture for channels 4 and 5 enable" "Disabled,Enabled" bitfld.long 0x00 17. " COMP2 ,Complement mode of channel 4 and 5" "Disabled,Enabled" bitfld.long 0x00 16. " COMBINE2 ,Combine mode for channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 15. " MCOMBINE1 ,Modified combine mode for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 14. " FAULTEN1 ,Fault control for channels 2 and 3 enable" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,Synchronization for channels 2 and 3 enable" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Deadtime insertion in channels 2 and 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for channels 2 and 3" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture for channels 2 and 3 enable" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complement mode of channel 2 and 3" "Disabled,Enabled" bitfld.long 0x00 8. " COMBINE1 ,Combine mode for channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 7. " MCOMBINE0 ,Modified combine mode for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 6. " FAULTEN0 ,Fault control for channels 0 and 1 enable" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization for channels 0 and 1 enable" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime insertion in channels 0 and 1 enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for channels 0 and 1" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture for channels 0 and 1 enable" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complement mode of channel 0 and 1" "Disabled,Enabled" bitfld.long 0x00 0. " COMBINE0 ,Combine mode for channels 0 and 1" "Disabled,Enabled" line.long 0x04 "DEADTIME,Deadtime Configuration Register" bitfld.long 0x04 16.--19. " DTVALEX ,Extended deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x04 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x64++0x03 line.long 0x00 "COMBINE,Function For Linked Channels Register" bitfld.long 0x00 31. " MCOMBINE3 ,Modified combine mode for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 30. " FAULTEN3 ,Fault control for channels 6 and 7 enable" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,Synchronization for channels 6 and 7 enable" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime insertion in channels 6 and 7 enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures for channels 6 and 7" "Inactive,Active" rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture for channels 6 and 7 enable" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complement mode of channel 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 24. " COMBINE3 ,Combine mode for channels 6 and 7" "Disabled,Enabled" newline rbitfld.long 0x00 23. " MCOMBINE2 ,Modified combine mode for channels 4 and 5" "Disabled,Enabled" rbitfld.long 0x00 22. " FAULTEN2 ,Fault control for channels 4 and 5 enable" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,Synchronization for channels 4 and 5 enable" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime insertion in channels 4 and 5 enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures for channels 4 and 5" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture for channels 4 and 5 enable" "Disabled,Enabled" rbitfld.long 0x00 17. " COMP2 ,Complement mode of channel 4 and 5" "Disabled,Enabled" rbitfld.long 0x00 16. " COMBINE2 ,Combine mode for channels 4 and 5" "Disabled,Enabled" newline rbitfld.long 0x00 15. " MCOMBINE1 ,Modified combine mode for channels 2 and 3" "Disabled,Enabled" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control for channels 2 and 3 enable" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,Synchronization for channels 2 and 3 enable" "Disabled,Enabled" rbitfld.long 0x00 12. " DTEN1 ,Deadtime insertion in channels 2 and 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for channels 2 and 3" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture for channels 2 and 3 enable" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complement mode of channel 2 and 3" "Disabled,Enabled" rbitfld.long 0x00 8. " COMBINE1 ,Combine mode for channels 2 and 3" "Disabled,Enabled" newline rbitfld.long 0x00 7. " MCOMBINE0 ,Modified combine mode for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 6. " FAULTEN0 ,Fault control for channels 0 and 1 enable" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization for channels 0 and 1 enable" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime insertion in channels 0 and 1 enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for channels 0 and 1" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture for channels 0 and 1 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complement mode of channel 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 0. " COMBINE0 ,Combine mode for channels 0 and 1" "Disabled,Enabled" rgroup.long 0x68++0x03 line.long 0x00 "DEADTIME,Deadtime Configuration Register" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "EXTTRIG,FTM External Trigger Register" bitfld.long 0x00 9. " CH[7]TRIG ,Channel 7 external trigger enable" "Disabled,Enabled" bitfld.long 0x00 8. " [6] ,Channel 6 external trigger enable" "Disabled,Enabled" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " CH[1]TRIG ,Channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " [0] ,Channel 0 trigger enable" "Disabled,Enabled" bitfld.long 0x00 3. " [5] ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " [4] ,Channel 4 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " [3] ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " [2] ,Channel 2 trigger enable" "Disabled,Enabled" if (((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04) group.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity Register" bitfld.long 0x00 7. " POL[7] ,Channel 7 polarity" "High,Low" bitfld.long 0x00 6. " [6] ,Channel 6 polarity" "High,Low" bitfld.long 0x00 5. " [5] ,Channel 5 polarity" "High,Low" bitfld.long 0x00 4. " [4] ,Channel 4 polarity" "High,Low" newline bitfld.long 0x00 3. " [3] ,Channel 3 polarity" "High,Low" bitfld.long 0x00 2. " [2] ,Channel 2 polarity" "High,Low" bitfld.long 0x00 1. " [1] ,Channel 1 polarity" "High,Low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "High,Low" else rgroup.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity Register" bitfld.long 0x00 7. " POL[7] ,Channel 7 polarity" "High,Low" bitfld.long 0x00 6. " [6] ,Channel 6 polarity" "High,Low" bitfld.long 0x00 5. " [5] ,Channel 5 polarity" "High,Low" bitfld.long 0x00 4. " [4] ,Channel 4 polarity" "High,Low" newline bitfld.long 0x00 3. " [3] ,Channel 3 polarity" "High,Low" bitfld.long 0x00 2. " [2] ,Channel 2 polarity" "High,Low" bitfld.long 0x00 1. " [1] ,Channel 1 polarity" "High,Low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "High,Low" endif hgroup.long 0x74++0x03 hide.long 0x00 "FMS,Fault Mode Status Register" newline in newline group.long 0x78++0x03 line.long 0x00 "FILTER,Input Capture Filter Control Register" bitfld.long 0x00 12.--15. " CH[3]FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " [2] ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " [1] ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " [0] ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04) group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control Register" bitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe values,Tri-stated" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " FFLTR[3]EN ,Fault input 3 filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " [2] ,fault input 2 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " [1] ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " [0] ,Fault input 0 filter enable" "Disabled,Enabled" bitfld.long 0x00 3. " FAULT[3]EN ,Fault input 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Fault input 2 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Fault input 0 enable" "Disabled,Enabled" else group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control Register" rbitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe values,Tri-stated" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 7. " FFLTR[3]EN ,Fault input 3 filter enable" "Disabled,Enabled" rbitfld.long 0x00 6. " [2] ,fault input 2 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 5. " [1] ,Fault input 1 filter enable" "Disabled,Enabled" rbitfld.long 0x00 4. " [0] ,Fault input 0 filter enable" "Disabled,Enabled" rbitfld.long 0x00 3. " FAULT[3]EN ,Fault input 3 enable" "Disabled,Enabled" rbitfld.long 0x00 2. " [2] ,Fault input 2 enable" "Disabled,Enabled" newline rbitfld.long 0x00 1. " [1] ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " [0] ,Fault input 0 enable" "Disabled,Enabled" endif if (((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04) group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "A and B encoding,Count and direction encoding" bitfld.long 0x00 2. " QUADIR ,FTM counter direction in quadrature decoder mode" "Decreasing,Increasing" bitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Bottom,Top" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "A and B encoding,Count and direction encoding" bitfld.long 0x00 2. " QUADIR ,FTM counter direction in quadrature decoder mode" "Decreasing,Increasing" bitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Bottom,Top" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "CONF,Configuration Register" bitfld.long 0x00 11. " ITRIGR ,Initialization trigger on reload point" "On counter wrap,On reload point reach" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " BDMMODE ,Selects the behavior in BDM mode [FTM counter/Channel (n) CHF bit/FTM channels output/Writes to MOD CNTIN and C(n)V]" "Stopped/Settable/Functional/Bypassed,Stopped/Not set/Forced/Bypassed,Stopped/Not set/Frozen/Bypassed,Functional/Settable/Functional/Functional" newline bitfld.long 0x00 0.--4. " LDFQ ,Frequency of the reload opportunities" "All,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" if (((per.l(ad:0x5A8A0000+0x54))&0x04)==0x04) group.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM Fault Input Polarity Register" bitfld.long 0x00 3. " FLT[3]POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " [2] ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " [1] ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " [0] ,Fault input 0 polarity" "Active high,Active low" else rgroup.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM Fault Input Polarity Register" bitfld.long 0x00 3. " FLT[3]POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " [2] ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " [1] ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " [0] ,Fault input 0 polarity" "Active high,Active low" endif group.long 0x8C++0x0F line.long 0x00 "SYNCONF,Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization active" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization active" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization active" "Not activated,Activated" newline bitfld.long 0x00 17. " HWWRBUF ,MOD HCR CNTIN and CV registers synchronization active" "Not activated,Activated" bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization active" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization active" "Not activated,Activated" newline bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization active" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization active" "Not activated,Activated" bitfld.long 0x00 9. " SWWRBUF ,MOD HCR CNTIN and CV registers synchronization active" "Not activated,Activated" newline bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization active" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,Synchronization mode" "Legacy PWM,Enhanced PWM" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Rising edges,PWM synchronization" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "At rising edges of input clock,PWM synchronization" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "At rising edges of input clock,PWM synchronization" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "INVCTRL,FTM Inverting Control Register" bitfld.long 0x04 3. " INV[3]EN ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " [2] ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,Pair channels 1 inverting enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " [0] ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "SWOCTRL,FTM Software Output Control Register" bitfld.long 0x08 15. " CH[7]OCV ,Channel 7 software output control value" "Force 0,Force 1" bitfld.long 0x08 14. " [6] ,Channel 6 software output control value" "Force 0,Force 1" bitfld.long 0x08 13. " [5] ,Channel 5 software output control value" "Force 0,Force 1" newline bitfld.long 0x08 12. " [4] ,Channel 4 software output control value" "Force 0,Force 1" bitfld.long 0x08 11. " [3] ,Channel 3 software output control value" "Force 0,Force 1" bitfld.long 0x08 10. " [2] ,Channel 2 software output control value" "Force 0,Force 1" newline bitfld.long 0x08 9. " [1] ,Channel 1 software output control value" "Force 0,Force 1" bitfld.long 0x08 8. " [0] ,Channel 0 software output control value" "Force 0,Force 1" bitfld.long 0x08 7. " CH[7]OC ,Channel 7 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " [6] ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " [4] ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " [3] ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Channel 1 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " [0] ,Channel 0 software output control enable" "Disabled,Enabled" line.long 0x0C "PWMLOAD,FTM PWM Load Register" bitfld.long 0x0C 11. " GLDOK ,Global load OK" "No action,Set" bitfld.long 0x0C 10. " GLEN ,Global load enable" "Disabled,Enabled" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" newline bitfld.long 0x0C 8. " HCSEL ,Half cycle select" "Disabled,Enabled" bitfld.long 0x0C 7. " CH[7]SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " [6] ,Channel 6 select" "Not included,Included" newline bitfld.long 0x0C 5. " [5] ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " [4] ,Channel 4 select" "Not included,Included" bitfld.long 0x0C 3. " [3] ,Channel 3 select" "Not included,Included" newline bitfld.long 0x0C 2. " [2] ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " [1] ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " [0] ,Channel 0 select" "Not included,Included" newline group.long 0x9C++0x03 line.long 0x00 "HCR,Half Cycle Register" hexmask.long.word 0x00 0.--15. 1. " HCVAL ,Half cycle value" group.long 0x200++0x03 line.long 0x00 "MOD_MIRROR,Mirror Of Modulo Value Register" hexmask.long.word 0x00 16.--31. 1. " MOD ,Mirror of the modulo integer value" bitfld.long 0x00 11.--15. " FRACMOD ,Modulo fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x204++0x03 line.long 0x00 "C0V_MIRROR,Mirror of Channel 0 Match Value Register" hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the channel 0 match integer value" bitfld.long 0x00 11.--15. " FRACVAL ,Channel 0 match fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x208++0x03 line.long 0x00 "C1V_MIRROR,Mirror of Channel 1 Match Value Register" hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the channel 1 match integer value" bitfld.long 0x00 11.--15. " FRACVAL ,Channel 1 match fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x20C++0x03 line.long 0x00 "C2V_MIRROR,Mirror of Channel 2 Match Value Register" hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the channel 2 match integer value" bitfld.long 0x00 11.--15. " FRACVAL ,Channel 2 match fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x210++0x03 line.long 0x00 "C3V_MIRROR,Mirror of Channel 3 Match Value Register" hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the channel 3 match integer value" bitfld.long 0x00 11.--15. " FRACVAL ,Channel 3 match fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x214++0x03 line.long 0x00 "C4V_MIRROR,Mirror of Channel 4 Match Value Register" hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the channel 4 match integer value" bitfld.long 0x00 11.--15. " FRACVAL ,Channel 4 match fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x218++0x03 line.long 0x00 "C5V_MIRROR,Mirror of Channel 5 Match Value Register" hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the channel 5 match integer value" bitfld.long 0x00 11.--15. " FRACVAL ,Channel 5 match fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x21C++0x03 line.long 0x00 "C6V_MIRROR,Mirror of Channel 6 Match Value Register" hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the channel 6 match integer value" bitfld.long 0x00 11.--15. " FRACVAL ,Channel 6 match fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x220++0x03 line.long 0x00 "C7V_MIRROR,Mirror of Channel 7 Match Value Register" hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the channel 7 match integer value" bitfld.long 0x00 11.--15. " FRACVAL ,Channel 7 match fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "FTM1" base ad:0x5A8B0000 width 12. if (((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04) group.long 0x00++0x03 line.long 0x00 "SC,Status And Control Register" bitfld.long 0x00 24.--27. " FLTPS ,Filter prescaler" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 23. " PWMEN[23] ,Channel 23 PWM enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Channel 22 PWM enable bit" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Channel 21 PWM enable bit" "Disabled,Enabled" newline bitfld.long 0x00 20. " [20] ,Channel 20 PWM enable bit" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Channel 19 PWM enable bit" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Channel 18 PWM enable bit" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Channel 17 PWM enable bit" "Disabled,Enabled" newline bitfld.long 0x00 16. " [16] ,Channel 16 PWM enable bit" "Disabled,Enabled" rbitfld.long 0x00 9. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 8. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 7. " RF ,Reload flag" "No reload,Reload" newline bitfld.long 0x00 6. " RIE ,Reload point interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting mode,Up-Down counting mode" bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clock,FTM clock,Fixed clock,External clock" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "SC,Status And Control Register" bitfld.long 0x00 24.--27. " FLTPS ,Filter prescaler" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 23. " PWMEN[23] ,Channel 23 PWM enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Channel 22 PWM enable bit" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Channel 21 PWM enable bit" "Disabled,Enabled" newline bitfld.long 0x00 20. " [20] ,Channel 20 PWM enable bit" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Channel 19 PWM enable bit" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Channel 18 PWM enable bit" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Channel 17 PWM enable bit" "Disabled,Enabled" newline bitfld.long 0x00 16. " [16] ,Channel 16 PWM enable bit" "Disabled,Enabled" rbitfld.long 0x00 9. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 8. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 7. " RF ,Reload flag" "No reload,Reload" newline bitfld.long 0x00 6. " RIE ,Reload point interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting mode,Up-Down counting mode" rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clock,FTM clock,Fixed clock,External clock" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif group.long 0x04++0x07 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "MOD,Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" if ((((per.l(ad:0x5A8B0000+0x64))&0x05)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0xC))&0x30)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (0) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (0) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (0) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (0) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x05)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0xC))&0x30)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (0) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (0) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (0) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (0) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x05)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0xC))&0x30)==0x10)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (0) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (0) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (0) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (0) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x05)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0xC))&0x30)==0x10)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (0) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (0) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (0) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (0) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x05)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0xC))&0x30)==(0x20||0x30))&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (0) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (0) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (0) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (0) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x05)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0xC))&0x30)==(0x20||0x30))&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (0) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (0) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (0) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (0) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x05)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x20)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (0) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (0) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (0) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (0) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x05)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x20)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (0) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (0) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (0) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (0) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x05)==0x01)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (0) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (0) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (0) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (0) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x05)==0x01)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (0) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (0) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (0) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (0) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x05)==0x04)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (0) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (0) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (0) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (0) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x05)==0x04)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (0) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (0) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (0) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (0) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0xC++0x03 hide.long 0x00 "C0SC,Channel (0) Status And Control Register" newline endif group.long (0xC+0x04)++0x03 line.long 0x00 "C0V,Channel (0) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x5A8B0000+0x64))&0x05)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x14))&0x30)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (1) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (1) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (1) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (1) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x05)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x14))&0x30)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (1) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (1) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (1) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (1) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x05)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x14))&0x30)==0x10)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (1) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (1) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (1) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (1) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x05)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x14))&0x30)==0x10)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (1) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (1) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (1) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (1) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x05)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x14))&0x30)==(0x20||0x30))&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (1) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (1) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (1) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (1) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x05)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x14))&0x30)==(0x20||0x30))&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (1) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (1) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (1) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (1) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x05)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x20)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (1) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (1) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (1) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (1) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x05)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x20)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (1) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (1) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (1) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (1) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x05)==0x01)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (1) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (1) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (1) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (1) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x05)==0x01)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (1) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (1) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (1) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (1) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x05)==0x04)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (1) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (1) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (1) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (1) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x05)==0x04)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (1) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (1) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (1) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (1) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x14++0x03 hide.long 0x00 "C1SC,Channel (1) Status And Control Register" newline endif group.long (0x14+0x04)++0x03 line.long 0x00 "C1V,Channel (1) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x5A8B0000+0x64))&0x500)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x1C))&0x30)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (2) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (2) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (2) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (2) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x500)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x1C))&0x30)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (2) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (2) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (2) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (2) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x500)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x1C))&0x30)==0x10)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (2) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (2) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (2) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (2) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x500)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x1C))&0x30)==0x10)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (2) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (2) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (2) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (2) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x500)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x1C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (2) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (2) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (2) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (2) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x500)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x1C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (2) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (2) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (2) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (2) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x500)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x20)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (2) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (2) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (2) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (2) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x500)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x20)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (2) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (2) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (2) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (2) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x500)==0x100)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (2) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (2) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (2) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (2) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x500)==0x100)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (2) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (2) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (2) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (2) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x500)==0x400)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (2) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (2) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (2) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (2) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x500)==0x400)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (2) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (2) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (2) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (2) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x1C++0x03 hide.long 0x00 "C2SC,Channel (2) Status And Control Register" newline endif group.long (0x1C+0x04)++0x03 line.long 0x00 "C2V,Channel (2) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x5A8B0000+0x64))&0x500)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x24))&0x30)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (3) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (3) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (3) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (3) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x500)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x24))&0x30)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (3) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (3) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (3) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (3) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x500)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x24))&0x30)==0x10)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (3) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (3) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (3) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (3) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x500)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x24))&0x30)==0x10)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (3) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (3) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (3) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (3) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x500)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x24))&0x30)==(0x20||0x30))&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (3) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (3) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (3) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (3) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x500)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x24))&0x30)==(0x20||0x30))&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (3) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (3) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (3) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (3) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x500)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x20)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (3) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (3) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (3) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (3) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x500)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x20)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (3) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (3) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (3) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (3) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x500)==0x100)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (3) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (3) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (3) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (3) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x500)==0x100)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (3) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (3) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (3) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (3) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x500)==0x400)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (3) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (3) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (3) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (3) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x500)==0x400)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (3) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (3) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (3) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (3) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x24++0x03 hide.long 0x00 "C3SC,Channel (3) Status And Control Register" newline endif group.long (0x24+0x04)++0x03 line.long 0x00 "C3V,Channel (3) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x5A8B0000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x2C))&0x30)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (4) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (4) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (4) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (4) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x2C))&0x30)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (4) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (4) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (4) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (4) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x2C))&0x30)==0x10)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (4) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (4) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (4) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (4) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x2C))&0x30)==0x10)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (4) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (4) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (4) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (4) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x2C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (4) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (4) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (4) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (4) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x2C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (4) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (4) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (4) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (4) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x20)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (4) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (4) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (4) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (4) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x20)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (4) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (4) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (4) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (4) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x50000)==0x10000)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (4) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (4) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (4) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (4) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x50000)==0x10000)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (4) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (4) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (4) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (4) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x50000)==0x40000)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (4) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (4) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (4) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (4) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x50000)==0x40000)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (4) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (4) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (4) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (4) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x2C++0x03 hide.long 0x00 "C4SC,Channel (4) Status And Control Register" newline endif group.long (0x2C+0x04)++0x03 line.long 0x00 "C4V,Channel (4) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x5A8B0000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x34))&0x30)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (5) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (5) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (5) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (5) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x34))&0x30)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (5) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (5) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (5) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (5) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x34))&0x30)==0x10)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (5) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (5) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (5) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (5) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x34))&0x30)==0x10)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (5) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (5) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (5) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (5) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x34))&0x30)==(0x20||0x30))&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (5) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (5) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (5) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (5) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x34))&0x30)==(0x20||0x30))&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (5) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (5) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (5) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (5) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x20)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (5) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (5) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (5) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (5) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x20)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (5) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (5) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (5) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (5) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x50000)==0x10000)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (5) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (5) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (5) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (5) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x50000)==0x10000)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (5) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (5) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (5) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (5) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x50000)==0x40000)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (5) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (5) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (5) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (5) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x50000)==0x40000)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (5) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (5) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (5) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (5) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x34++0x03 hide.long 0x00 "C5SC,Channel (5) Status And Control Register" newline endif group.long (0x34+0x04)++0x03 line.long 0x00 "C5V,Channel (5) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x5A8B0000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x3C))&0x30)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (6) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (6) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (6) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (6) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x3C))&0x30)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (6) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (6) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (6) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (6) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x3C))&0x30)==0x10)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (6) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (6) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (6) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (6) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x3C))&0x30)==0x10)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (6) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (6) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (6) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (6) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x3C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (6) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (6) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (6) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (6) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x3C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (6) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (6) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (6) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (6) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x20)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (6) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (6) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (6) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (6) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x20)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (6) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (6) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (6) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (6) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x5000000)==0x1000000)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (6) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (6) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (6) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (6) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x5000000)==0x1000000)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (6) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (6) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (6) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (6) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x5000000)==0x4000000)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (6) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (6) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (6) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (6) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x5000000)==0x4000000)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (6) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (6) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (6) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (6) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x3C++0x03 hide.long 0x00 "C6SC,Channel (6) Status And Control Register" newline endif group.long (0x3C+0x04)++0x03 line.long 0x00 "C6V,Channel (6) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x5A8B0000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x44))&0x30)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (7) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (7) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (7) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (7) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x44))&0x30)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (7) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (7) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (7) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (7) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x44))&0x30)==0x10)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (7) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (7) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (7) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (7) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x44))&0x30)==0x10)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (7) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (7) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (7) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (7) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x44))&0x30)==(0x20||0x30))&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (7) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (7) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (7) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (7) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x44))&0x30)==(0x20||0x30))&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (7) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (7) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (7) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (7) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x20)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (7) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (7) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (7) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (7) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x5A8B0000))&0x20)==0x20)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (7) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (7) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (7) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (7) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x5000000)==0x1000000)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (7) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (7) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (7) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (7) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x5000000)==0x1000000)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (7) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (7) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (7) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (7) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x5000000)==0x4000000)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (7) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (7) input state" "0,1" bitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (7) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (7) interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x5A8B0000+0x64))&0x5000000)==0x4000000)&&(((per.l(ad:0x5A8B0000))&0x20)==0x00)&&(((per.l(ad:0x5A8B0000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 10. " CHOV ,Channel (7) output value" "0,1" bitfld.long 0x00 9. " CHIS ,Channel (7) input state" "0,1" rbitfld.long 0x00 8. " TRIGMODE ,Trigger mode control" "Normal,Trigger pulse" rbitfld.long 0x00 7. " CHF ,Channel (7) flag" "Not occurred,Occurred" newline bitfld.long 0x00 6. " CHIE ,Channel (7) interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edges" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x44++0x03 hide.long 0x00 "C7SC,Channel (7) Status And Control Register" newline endif group.long (0x44+0x04)++0x03 line.long 0x00 "C7V,Channel (7) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x4C++0x03 line.long 0x00 "CNTIN,Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of the FTM counter" newline hgroup.long 0x50++0x03 hide.long 0x00 "STATUS,Capture And Compare Status Register" in newline if (((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04) group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channels/Manual clear,All channels/Manual clear,All channels/Automatic clear" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode" "Disabled,Enabled" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Channel output initialization" "No effect,Initialize" bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault Control Mode" "Disabled,Even channels/Manual clear,All channels/Manual clear,All channels/Automatic clear" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode" "Disabled,Enabled" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Channel output initialization" "No effect,Initialize" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "SYNC,Synchronization Register" newline bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Rising edges,PWM synchronization" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Count normally,Trigger detected" bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "OUTINIT,Initial State For Channels Output Register" bitfld.long 0x04 7. " CH[7]OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " [6] ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " [5] ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " [4] ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " [3] ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " [2] ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " [1] ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " [0] ,Channel 0 output initialization value" "0,1" line.long 0x08 "OUTMASK,Output Mask Register" bitfld.long 0x08 7. " CH[7]OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " [6] ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " [5] ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " [4] ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " [3] ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " [2] ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " [1] ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " [0] ,Channel 0 output mask" "Not masked,Masked" if (((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04) group.long 0x64++0x07 line.long 0x00 "COMBINE,Function For Linked Channels Register" bitfld.long 0x00 31. " MCOMBINE3 ,Modified combine mode for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 30. " FAULTEN3 ,Fault control for channels 6 and 7 enable" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,Synchronization for channels 6 and 7 enable" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime insertion in channels 6 and 7 enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures for channels 6 and 7" "Inactive,Active" bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture for channels 6 and 7 enable" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complement mode of channel 6 and 7" "Disabled,Enabled" bitfld.long 0x00 24. " COMBINE3 ,Combine mode for channels 6 and 7" "Disabled,Enabled" newline bitfld.long 0x00 23. " MCOMBINE2 ,Modified combine mode for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 22. " FAULTEN2 ,Fault control for channels 4 and 5 enable" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,Synchronization for channels 4 and 5 enable" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime insertion in channels 4 and 5 enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures for channels 4 and 5" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture for channels 4 and 5 enable" "Disabled,Enabled" bitfld.long 0x00 17. " COMP2 ,Complement mode of channel 4 and 5" "Disabled,Enabled" bitfld.long 0x00 16. " COMBINE2 ,Combine mode for channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 15. " MCOMBINE1 ,Modified combine mode for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 14. " FAULTEN1 ,Fault control for channels 2 and 3 enable" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,Synchronization for channels 2 and 3 enable" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Deadtime insertion in channels 2 and 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for channels 2 and 3" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture for channels 2 and 3 enable" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complement mode of channel 2 and 3" "Disabled,Enabled" bitfld.long 0x00 8. " COMBINE1 ,Combine mode for channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 7. " MCOMBINE0 ,Modified combine mode for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 6. " FAULTEN0 ,Fault control for channels 0 and 1 enable" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization for channels 0 and 1 enable" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime insertion in channels 0 and 1 enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for channels 0 and 1" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture for channels 0 and 1 enable" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complement mode of channel 0 and 1" "Disabled,Enabled" bitfld.long 0x00 0. " COMBINE0 ,Combine mode for channels 0 and 1" "Disabled,Enabled" line.long 0x04 "DEADTIME,Deadtime Configuration Register" bitfld.long 0x04 16.--19. " DTVALEX ,Extended deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x04 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x64++0x03 line.long 0x00 "COMBINE,Function For Linked Channels Register" bitfld.long 0x00 31. " MCOMBINE3 ,Modified combine mode for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 30. " FAULTEN3 ,Fault control for channels 6 and 7 enable" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,Synchronization for channels 6 and 7 enable" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime insertion in channels 6 and 7 enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures for channels 6 and 7" "Inactive,Active" rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture for channels 6 and 7 enable" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complement mode of channel 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 24. " COMBINE3 ,Combine mode for channels 6 and 7" "Disabled,Enabled" newline rbitfld.long 0x00 23. " MCOMBINE2 ,Modified combine mode for channels 4 and 5" "Disabled,Enabled" rbitfld.long 0x00 22. " FAULTEN2 ,Fault control for channels 4 and 5 enable" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,Synchronization for channels 4 and 5 enable" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime insertion in channels 4 and 5 enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures for channels 4 and 5" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture for channels 4 and 5 enable" "Disabled,Enabled" rbitfld.long 0x00 17. " COMP2 ,Complement mode of channel 4 and 5" "Disabled,Enabled" rbitfld.long 0x00 16. " COMBINE2 ,Combine mode for channels 4 and 5" "Disabled,Enabled" newline rbitfld.long 0x00 15. " MCOMBINE1 ,Modified combine mode for channels 2 and 3" "Disabled,Enabled" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control for channels 2 and 3 enable" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,Synchronization for channels 2 and 3 enable" "Disabled,Enabled" rbitfld.long 0x00 12. " DTEN1 ,Deadtime insertion in channels 2 and 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for channels 2 and 3" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture for channels 2 and 3 enable" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complement mode of channel 2 and 3" "Disabled,Enabled" rbitfld.long 0x00 8. " COMBINE1 ,Combine mode for channels 2 and 3" "Disabled,Enabled" newline rbitfld.long 0x00 7. " MCOMBINE0 ,Modified combine mode for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 6. " FAULTEN0 ,Fault control for channels 0 and 1 enable" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization for channels 0 and 1 enable" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime insertion in channels 0 and 1 enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for channels 0 and 1" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture for channels 0 and 1 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complement mode of channel 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 0. " COMBINE0 ,Combine mode for channels 0 and 1" "Disabled,Enabled" rgroup.long 0x68++0x03 line.long 0x00 "DEADTIME,Deadtime Configuration Register" bitfld.long 0x00 16.--19. " DTVALEX ,Extended deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "EXTTRIG,FTM External Trigger Register" bitfld.long 0x00 9. " CH[7]TRIG ,Channel 7 external trigger enable" "Disabled,Enabled" bitfld.long 0x00 8. " [6] ,Channel 6 external trigger enable" "Disabled,Enabled" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " CH[1]TRIG ,Channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " [0] ,Channel 0 trigger enable" "Disabled,Enabled" bitfld.long 0x00 3. " [5] ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " [4] ,Channel 4 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " [3] ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " [2] ,Channel 2 trigger enable" "Disabled,Enabled" if (((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04) group.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity Register" bitfld.long 0x00 7. " POL[7] ,Channel 7 polarity" "High,Low" bitfld.long 0x00 6. " [6] ,Channel 6 polarity" "High,Low" bitfld.long 0x00 5. " [5] ,Channel 5 polarity" "High,Low" bitfld.long 0x00 4. " [4] ,Channel 4 polarity" "High,Low" newline bitfld.long 0x00 3. " [3] ,Channel 3 polarity" "High,Low" bitfld.long 0x00 2. " [2] ,Channel 2 polarity" "High,Low" bitfld.long 0x00 1. " [1] ,Channel 1 polarity" "High,Low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "High,Low" else rgroup.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity Register" bitfld.long 0x00 7. " POL[7] ,Channel 7 polarity" "High,Low" bitfld.long 0x00 6. " [6] ,Channel 6 polarity" "High,Low" bitfld.long 0x00 5. " [5] ,Channel 5 polarity" "High,Low" bitfld.long 0x00 4. " [4] ,Channel 4 polarity" "High,Low" newline bitfld.long 0x00 3. " [3] ,Channel 3 polarity" "High,Low" bitfld.long 0x00 2. " [2] ,Channel 2 polarity" "High,Low" bitfld.long 0x00 1. " [1] ,Channel 1 polarity" "High,Low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "High,Low" endif hgroup.long 0x74++0x03 hide.long 0x00 "FMS,Fault Mode Status Register" newline in newline group.long 0x78++0x03 line.long 0x00 "FILTER,Input Capture Filter Control Register" bitfld.long 0x00 12.--15. " CH[3]FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " [2] ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " [1] ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " [0] ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04) group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control Register" bitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe values,Tri-stated" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " FFLTR[3]EN ,Fault input 3 filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " [2] ,fault input 2 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " [1] ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " [0] ,Fault input 0 filter enable" "Disabled,Enabled" bitfld.long 0x00 3. " FAULT[3]EN ,Fault input 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Fault input 2 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Fault input 0 enable" "Disabled,Enabled" else group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control Register" rbitfld.long 0x00 15. " FSTATE ,Fault output state" "Safe values,Tri-stated" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 7. " FFLTR[3]EN ,Fault input 3 filter enable" "Disabled,Enabled" rbitfld.long 0x00 6. " [2] ,fault input 2 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 5. " [1] ,Fault input 1 filter enable" "Disabled,Enabled" rbitfld.long 0x00 4. " [0] ,Fault input 0 filter enable" "Disabled,Enabled" rbitfld.long 0x00 3. " FAULT[3]EN ,Fault input 3 enable" "Disabled,Enabled" rbitfld.long 0x00 2. " [2] ,Fault input 2 enable" "Disabled,Enabled" newline rbitfld.long 0x00 1. " [1] ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " [0] ,Fault input 0 enable" "Disabled,Enabled" endif if (((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04) group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "A and B encoding,Count and direction encoding" bitfld.long 0x00 2. " QUADIR ,FTM counter direction in quadrature decoder mode" "Decreasing,Increasing" bitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Bottom,Top" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "A and B encoding,Count and direction encoding" bitfld.long 0x00 2. " QUADIR ,FTM counter direction in quadrature decoder mode" "Decreasing,Increasing" bitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Bottom,Top" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "CONF,Configuration Register" bitfld.long 0x00 11. " ITRIGR ,Initialization trigger on reload point" "On counter wrap,On reload point reach" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " BDMMODE ,Selects the behavior in BDM mode [FTM counter/Channel (n) CHF bit/FTM channels output/Writes to MOD CNTIN and C(n)V]" "Stopped/Settable/Functional/Bypassed,Stopped/Not set/Forced/Bypassed,Stopped/Not set/Frozen/Bypassed,Functional/Settable/Functional/Functional" newline bitfld.long 0x00 0.--4. " LDFQ ,Frequency of the reload opportunities" "All,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" if (((per.l(ad:0x5A8B0000+0x54))&0x04)==0x04) group.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM Fault Input Polarity Register" bitfld.long 0x00 3. " FLT[3]POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " [2] ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " [1] ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " [0] ,Fault input 0 polarity" "Active high,Active low" else rgroup.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM Fault Input Polarity Register" bitfld.long 0x00 3. " FLT[3]POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " [2] ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " [1] ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " [0] ,Fault input 0 polarity" "Active high,Active low" endif group.long 0x8C++0x0F line.long 0x00 "SYNCONF,Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization active" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization active" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization active" "Not activated,Activated" newline bitfld.long 0x00 17. " HWWRBUF ,MOD HCR CNTIN and CV registers synchronization active" "Not activated,Activated" bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization active" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization active" "Not activated,Activated" newline bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization active" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization active" "Not activated,Activated" bitfld.long 0x00 9. " SWWRBUF ,MOD HCR CNTIN and CV registers synchronization active" "Not activated,Activated" newline bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization active" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,Synchronization mode" "Legacy PWM,Enhanced PWM" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Rising edges,PWM synchronization" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "At rising edges of input clock,PWM synchronization" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "At rising edges of input clock,PWM synchronization" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "INVCTRL,FTM Inverting Control Register" bitfld.long 0x04 3. " INV[3]EN ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " [2] ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,Pair channels 1 inverting enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " [0] ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "SWOCTRL,FTM Software Output Control Register" bitfld.long 0x08 15. " CH[7]OCV ,Channel 7 software output control value" "Force 0,Force 1" bitfld.long 0x08 14. " [6] ,Channel 6 software output control value" "Force 0,Force 1" bitfld.long 0x08 13. " [5] ,Channel 5 software output control value" "Force 0,Force 1" newline bitfld.long 0x08 12. " [4] ,Channel 4 software output control value" "Force 0,Force 1" bitfld.long 0x08 11. " [3] ,Channel 3 software output control value" "Force 0,Force 1" bitfld.long 0x08 10. " [2] ,Channel 2 software output control value" "Force 0,Force 1" newline bitfld.long 0x08 9. " [1] ,Channel 1 software output control value" "Force 0,Force 1" bitfld.long 0x08 8. " [0] ,Channel 0 software output control value" "Force 0,Force 1" bitfld.long 0x08 7. " CH[7]OC ,Channel 7 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " [6] ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " [4] ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " [3] ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Channel 1 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " [0] ,Channel 0 software output control enable" "Disabled,Enabled" line.long 0x0C "PWMLOAD,FTM PWM Load Register" bitfld.long 0x0C 11. " GLDOK ,Global load OK" "No action,Set" bitfld.long 0x0C 10. " GLEN ,Global load enable" "Disabled,Enabled" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" newline bitfld.long 0x0C 8. " HCSEL ,Half cycle select" "Disabled,Enabled" bitfld.long 0x0C 7. " CH[7]SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " [6] ,Channel 6 select" "Not included,Included" newline bitfld.long 0x0C 5. " [5] ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " [4] ,Channel 4 select" "Not included,Included" bitfld.long 0x0C 3. " [3] ,Channel 3 select" "Not included,Included" newline bitfld.long 0x0C 2. " [2] ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " [1] ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " [0] ,Channel 0 select" "Not included,Included" newline group.long 0x9C++0x03 line.long 0x00 "HCR,Half Cycle Register" hexmask.long.word 0x00 0.--15. 1. " HCVAL ,Half cycle value" group.long 0x200++0x03 line.long 0x00 "MOD_MIRROR,Mirror Of Modulo Value Register" hexmask.long.word 0x00 16.--31. 1. " MOD ,Mirror of the modulo integer value" bitfld.long 0x00 11.--15. " FRACMOD ,Modulo fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x204++0x03 line.long 0x00 "C0V_MIRROR,Mirror of Channel 0 Match Value Register" hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the channel 0 match integer value" bitfld.long 0x00 11.--15. " FRACVAL ,Channel 0 match fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x208++0x03 line.long 0x00 "C1V_MIRROR,Mirror of Channel 1 Match Value Register" hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the channel 1 match integer value" bitfld.long 0x00 11.--15. " FRACVAL ,Channel 1 match fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x20C++0x03 line.long 0x00 "C2V_MIRROR,Mirror of Channel 2 Match Value Register" hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the channel 2 match integer value" bitfld.long 0x00 11.--15. " FRACVAL ,Channel 2 match fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x210++0x03 line.long 0x00 "C3V_MIRROR,Mirror of Channel 3 Match Value Register" hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the channel 3 match integer value" bitfld.long 0x00 11.--15. " FRACVAL ,Channel 3 match fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x214++0x03 line.long 0x00 "C4V_MIRROR,Mirror of Channel 4 Match Value Register" hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the channel 4 match integer value" bitfld.long 0x00 11.--15. " FRACVAL ,Channel 4 match fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x218++0x03 line.long 0x00 "C5V_MIRROR,Mirror of Channel 5 Match Value Register" hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the channel 5 match integer value" bitfld.long 0x00 11.--15. " FRACVAL ,Channel 5 match fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x21C++0x03 line.long 0x00 "C6V_MIRROR,Mirror of Channel 6 Match Value Register" hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the channel 6 match integer value" bitfld.long 0x00 11.--15. " FRACVAL ,Channel 6 match fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x220++0x03 line.long 0x00 "C7V_MIRROR,Mirror of Channel 7 Match Value Register" hexmask.long.word 0x00 16.--31. 1. " VAL ,Mirror of the channel 7 match integer value" bitfld.long 0x00 11.--15. " FRACVAL ,Channel 7 match fractional value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree.end tree "LCDIF (Enhanced LCD Interface)" base ad:0x5A180000 width 16. tree "Control Registers" if ((per.l(ad:0x5A180000+0x0)&0x300)==0x00) if (((per.l(ad:0x5A180000+0x0)&0x40000)==0x00)&&((per.l(ad:0x5A180000+0x0)&0x01)==0x00)) group.long 0x0++0x03 line.long 0x00 "CTRL0,LCDIF General Control Register 0" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" newline bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" newline bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16-bit data format" "RGB565,ARGB555" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" elif (((per.l(ad:0x5A180000+0x0)&0x40000)==0x4000)&&((per.l(ad:0x5A180000+0x0)&0x01)==0x00)) group.long 0x0++0x03 line.long 0x00 "CTRL0,LCDIF General Control Register 0" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" newline bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16-bit data format" "RGB565,ARGB555" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" elif (((per.l(ad:0x5A180000+0x0)&0x40000)==0x00)&&((per.l(ad:0x5A180000+0x0)&0x01)==0x01)) group.long 0x0++0x03 line.long 0x00 "CTRL0,LCDIF General Control Register 0" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" newline bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" newline bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16-bit data format" "RGB565,ARGB555" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" else group.long 0x0++0x03 line.long 0x00 "CTRL0,LCDIF General Control Register 0" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" newline bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16-bit data format" "RGB565,ARGB555" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" endif elif ((per.l(ad:0x5A180000+0x0)&0x300)==0x200) if (((per.l(ad:0x5A180000+0x0)&0x40000)==0x00)&&((per.l(ad:0x5A180000+0x0)&0x01)==0x00)) group.long 0x0++0x03 line.long 0x00 "CTRL0,LCDIF General Control Register 0" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" newline bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" newline bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18-bit data format/alingment" "18 bpp RGB666/lower bits,18 bpp RGB666/higher bits" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" elif (((per.l(ad:0x5A180000+0x0)&0x40000)==0x4000)&&((per.l(ad:0x5A180000+0x0)&0x01)==0x00)) group.long 0x0++0x03 line.long 0x00 "CTRL0,LCDIF General Control Register 0" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" newline bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18-bit data format/alingment" "18 bpp RGB666/lower bits,18 bpp RGB666/higher bits" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" elif (((per.l(ad:0x5A180000+0x0)&0x40000)==0x00)&&((per.l(ad:0x5A180000+0x0)&0x01)==0x01)) group.long 0x0++0x03 line.long 0x00 "CTRL0,LCDIF General Control Register 0" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" newline bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" newline bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18-bit data format/alingment" "18 bpp RGB666/lower bits,18 bpp RGB666/higher bits" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" else group.long 0x0++0x03 line.long 0x00 "CTRL0,LCDIF General Control Register 0" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" newline bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18-bit data format/alingment" "18 bpp RGB666/lower bits,18 bpp RGB666/higher bits" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" endif elif ((per.l(ad:0x5A180000+0x0)&0x300)==0x300) if (((per.l(ad:0x5A180000+0x0)&0x40000)==0x00)&&((per.l(ad:0x5A180000+0x0)&0x01)==0x00)) group.long 0x0++0x03 line.long 0x00 "CTRL0,LCDIF General Control Register 0" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" newline bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" newline bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24-bit data format" "24 bpp RGB888,18 bpp 1 color per byte" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" elif (((per.l(ad:0x5A180000+0x0)&0x40000)==0x4000)&&((per.l(ad:0x5A180000+0x0)&0x01)==0x00)) group.long 0x0++0x03 line.long 0x00 "CTRL0,LCDIF General Control Register 0" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" newline bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24-bit data format" "24 bpp RGB888,18 bpp 1 color per byte" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" elif (((per.l(ad:0x5A180000+0x0)&0x40000)==0x00)&&((per.l(ad:0x5A180000+0x0)&0x01)==0x01)) group.long 0x0++0x03 line.long 0x00 "CTRL0,LCDIF General Control Register 0" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" newline bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" newline bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24-bit data format" "24 bpp RGB888,18 bpp 1 color per byte" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" else group.long 0x0++0x03 line.long 0x00 "CTRL0,LCDIF General Control Register 0" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" newline bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24-bit data format" "24 bpp RGB888,18 bpp 1 color per byte" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" endif else if (((per.l(ad:0x5A180000+0x0)&0x40000)==0x00)&&((per.l(ad:0x5A180000+0x0)&0x01)==0x00)) group.long 0x0++0x03 line.long 0x00 "CTRL0,LCDIF General Control Register 0" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" newline bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" newline bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" elif (((per.l(ad:0x5A180000+0x0)&0x40000)==0x4000)&&((per.l(ad:0x5A180000+0x0)&0x01)==0x00)) group.long 0x0++0x03 line.long 0x00 "CTRL0,LCDIF General Control Register 0" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" newline bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" elif (((per.l(ad:0x5A180000+0x0)&0x40000)==0x00)&&((per.l(ad:0x5A180000+0x0)&0x01)==0x01)) group.long 0x0++0x03 line.long 0x00 "CTRL0,LCDIF General Control Register 0" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" newline bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" newline bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" else group.long 0x0++0x03 line.long 0x00 "CTRL0,LCDIF General Control Register 0" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" newline bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" endif endif if ((per.l(ad:0x5A180000+0x4)&0x300)==0x00) if (((per.l(ad:0x5A180000+0x4)&0x40000)==0x00)&&((per.l(ad:0x5A180000+0x4)&0x01)==0x00)) group.long 0x4++0x03 line.long 0x00 "CTRL1,LCDIF General Control Register 1" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" newline bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" newline bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16-bit data format" "RGB565,ARGB555" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" elif (((per.l(ad:0x5A180000+0x4)&0x40000)==0x4000)&&((per.l(ad:0x5A180000+0x4)&0x01)==0x00)) group.long 0x4++0x03 line.long 0x00 "CTRL1,LCDIF General Control Register 1" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" newline bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16-bit data format" "RGB565,ARGB555" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" elif (((per.l(ad:0x5A180000+0x4)&0x40000)==0x00)&&((per.l(ad:0x5A180000+0x4)&0x01)==0x01)) group.long 0x4++0x03 line.long 0x00 "CTRL1,LCDIF General Control Register 1" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" newline bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" newline bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16-bit data format" "RGB565,ARGB555" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" else group.long 0x4++0x03 line.long 0x00 "CTRL1,LCDIF General Control Register 1" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" newline bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16-bit data format" "RGB565,ARGB555" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" endif elif ((per.l(ad:0x5A180000+0x4)&0x300)==0x200) if (((per.l(ad:0x5A180000+0x4)&0x40000)==0x00)&&((per.l(ad:0x5A180000+0x4)&0x01)==0x00)) group.long 0x4++0x03 line.long 0x00 "CTRL1,LCDIF General Control Register 1" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" newline bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" newline bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18-bit data format/alingment" "18 bpp RGB666/lower bits,18 bpp RGB666/higher bits" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" elif (((per.l(ad:0x5A180000+0x4)&0x40000)==0x4000)&&((per.l(ad:0x5A180000+0x4)&0x01)==0x00)) group.long 0x4++0x03 line.long 0x00 "CTRL1,LCDIF General Control Register 1" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" newline bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18-bit data format/alingment" "18 bpp RGB666/lower bits,18 bpp RGB666/higher bits" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" elif (((per.l(ad:0x5A180000+0x4)&0x40000)==0x00)&&((per.l(ad:0x5A180000+0x4)&0x01)==0x01)) group.long 0x4++0x03 line.long 0x00 "CTRL1,LCDIF General Control Register 1" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" newline bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" newline bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18-bit data format/alingment" "18 bpp RGB666/lower bits,18 bpp RGB666/higher bits" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" else group.long 0x4++0x03 line.long 0x00 "CTRL1,LCDIF General Control Register 1" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" newline bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18-bit data format/alingment" "18 bpp RGB666/lower bits,18 bpp RGB666/higher bits" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" endif elif ((per.l(ad:0x5A180000+0x4)&0x300)==0x300) if (((per.l(ad:0x5A180000+0x4)&0x40000)==0x00)&&((per.l(ad:0x5A180000+0x4)&0x01)==0x00)) group.long 0x4++0x03 line.long 0x00 "CTRL1,LCDIF General Control Register 1" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" newline bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" newline bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24-bit data format" "24 bpp RGB888,18 bpp 1 color per byte" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" elif (((per.l(ad:0x5A180000+0x4)&0x40000)==0x4000)&&((per.l(ad:0x5A180000+0x4)&0x01)==0x00)) group.long 0x4++0x03 line.long 0x00 "CTRL1,LCDIF General Control Register 1" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" newline bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24-bit data format" "24 bpp RGB888,18 bpp 1 color per byte" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" elif (((per.l(ad:0x5A180000+0x4)&0x40000)==0x00)&&((per.l(ad:0x5A180000+0x4)&0x01)==0x01)) group.long 0x4++0x03 line.long 0x00 "CTRL1,LCDIF General Control Register 1" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" newline bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" newline bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24-bit data format" "24 bpp RGB888,18 bpp 1 color per byte" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" else group.long 0x4++0x03 line.long 0x00 "CTRL1,LCDIF General Control Register 1" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" newline bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24-bit data format" "24 bpp RGB888,18 bpp 1 color per byte" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" endif else if (((per.l(ad:0x5A180000+0x4)&0x40000)==0x00)&&((per.l(ad:0x5A180000+0x4)&0x01)==0x00)) group.long 0x4++0x03 line.long 0x00 "CTRL1,LCDIF General Control Register 1" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" newline bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" newline bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" elif (((per.l(ad:0x5A180000+0x4)&0x40000)==0x4000)&&((per.l(ad:0x5A180000+0x4)&0x01)==0x00)) group.long 0x4++0x03 line.long 0x00 "CTRL1,LCDIF General Control Register 1" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" newline bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" elif (((per.l(ad:0x5A180000+0x4)&0x40000)==0x00)&&((per.l(ad:0x5A180000+0x4)&0x01)==0x01)) group.long 0x4++0x03 line.long 0x00 "CTRL1,LCDIF General Control Register 1" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" newline bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" newline bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" else group.long 0x4++0x03 line.long 0x00 "CTRL1,LCDIF General Control Register 1" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" newline bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" endif endif if ((per.l(ad:0x5A180000+0x8)&0x300)==0x00) if (((per.l(ad:0x5A180000+0x8)&0x40000)==0x00)&&((per.l(ad:0x5A180000+0x8)&0x01)==0x00)) group.long 0x8++0x03 line.long 0x00 "CTRL2,LCDIF General Control Register 2" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" newline bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" newline bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16-bit data format" "RGB565,ARGB555" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" elif (((per.l(ad:0x5A180000+0x8)&0x40000)==0x4000)&&((per.l(ad:0x5A180000+0x8)&0x01)==0x00)) group.long 0x8++0x03 line.long 0x00 "CTRL2,LCDIF General Control Register 2" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" newline bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16-bit data format" "RGB565,ARGB555" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" elif (((per.l(ad:0x5A180000+0x8)&0x40000)==0x00)&&((per.l(ad:0x5A180000+0x8)&0x01)==0x01)) group.long 0x8++0x03 line.long 0x00 "CTRL2,LCDIF General Control Register 2" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" newline bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" newline bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16-bit data format" "RGB565,ARGB555" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" else group.long 0x8++0x03 line.long 0x00 "CTRL2,LCDIF General Control Register 2" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" newline bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16-bit data format" "RGB565,ARGB555" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" endif elif ((per.l(ad:0x5A180000+0x8)&0x300)==0x200) if (((per.l(ad:0x5A180000+0x8)&0x40000)==0x00)&&((per.l(ad:0x5A180000+0x8)&0x01)==0x00)) group.long 0x8++0x03 line.long 0x00 "CTRL2,LCDIF General Control Register 2" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" newline bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" newline bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18-bit data format/alingment" "18 bpp RGB666/lower bits,18 bpp RGB666/higher bits" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" elif (((per.l(ad:0x5A180000+0x8)&0x40000)==0x4000)&&((per.l(ad:0x5A180000+0x8)&0x01)==0x00)) group.long 0x8++0x03 line.long 0x00 "CTRL2,LCDIF General Control Register 2" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" newline bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18-bit data format/alingment" "18 bpp RGB666/lower bits,18 bpp RGB666/higher bits" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" elif (((per.l(ad:0x5A180000+0x8)&0x40000)==0x00)&&((per.l(ad:0x5A180000+0x8)&0x01)==0x01)) group.long 0x8++0x03 line.long 0x00 "CTRL2,LCDIF General Control Register 2" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" newline bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" newline bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18-bit data format/alingment" "18 bpp RGB666/lower bits,18 bpp RGB666/higher bits" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" else group.long 0x8++0x03 line.long 0x00 "CTRL2,LCDIF General Control Register 2" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" newline bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18-bit data format/alingment" "18 bpp RGB666/lower bits,18 bpp RGB666/higher bits" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" endif elif ((per.l(ad:0x5A180000+0x8)&0x300)==0x300) if (((per.l(ad:0x5A180000+0x8)&0x40000)==0x00)&&((per.l(ad:0x5A180000+0x8)&0x01)==0x00)) group.long 0x8++0x03 line.long 0x00 "CTRL2,LCDIF General Control Register 2" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" newline bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" newline bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24-bit data format" "24 bpp RGB888,18 bpp 1 color per byte" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" elif (((per.l(ad:0x5A180000+0x8)&0x40000)==0x4000)&&((per.l(ad:0x5A180000+0x8)&0x01)==0x00)) group.long 0x8++0x03 line.long 0x00 "CTRL2,LCDIF General Control Register 2" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" newline bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24-bit data format" "24 bpp RGB888,18 bpp 1 color per byte" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" elif (((per.l(ad:0x5A180000+0x8)&0x40000)==0x00)&&((per.l(ad:0x5A180000+0x8)&0x01)==0x01)) group.long 0x8++0x03 line.long 0x00 "CTRL2,LCDIF General Control Register 2" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" newline bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" newline bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24-bit data format" "24 bpp RGB888,18 bpp 1 color per byte" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" else group.long 0x8++0x03 line.long 0x00 "CTRL2,LCDIF General Control Register 2" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" newline bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24-bit data format" "24 bpp RGB888,18 bpp 1 color per byte" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" endif else if (((per.l(ad:0x5A180000+0x8)&0x40000)==0x00)&&((per.l(ad:0x5A180000+0x8)&0x01)==0x00)) group.long 0x8++0x03 line.long 0x00 "CTRL2,LCDIF General Control Register 2" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" newline bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" newline bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" elif (((per.l(ad:0x5A180000+0x8)&0x40000)==0x4000)&&((per.l(ad:0x5A180000+0x8)&0x01)==0x00)) group.long 0x8++0x03 line.long 0x00 "CTRL2,LCDIF General Control Register 2" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" newline bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" elif (((per.l(ad:0x5A180000+0x8)&0x40000)==0x00)&&((per.l(ad:0x5A180000+0x8)&0x01)==0x01)) group.long 0x8++0x03 line.long 0x00 "CTRL2,LCDIF General Control Register 2" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" newline bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" newline bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" else group.long 0x8++0x03 line.long 0x00 "CTRL2,LCDIF General Control Register 2" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" newline bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" endif endif if ((per.l(ad:0x5A180000+0xC)&0x300)==0x00) if (((per.l(ad:0x5A180000+0xC)&0x40000)==0x00)&&((per.l(ad:0x5A180000+0xC)&0x01)==0x00)) group.long 0xC++0x03 line.long 0x00 "CTRL3,LCDIF General Control Register 3" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" newline bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" newline bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16-bit data format" "RGB565,ARGB555" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" elif (((per.l(ad:0x5A180000+0xC)&0x40000)==0x4000)&&((per.l(ad:0x5A180000+0xC)&0x01)==0x00)) group.long 0xC++0x03 line.long 0x00 "CTRL3,LCDIF General Control Register 3" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" newline bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16-bit data format" "RGB565,ARGB555" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" elif (((per.l(ad:0x5A180000+0xC)&0x40000)==0x00)&&((per.l(ad:0x5A180000+0xC)&0x01)==0x01)) group.long 0xC++0x03 line.long 0x00 "CTRL3,LCDIF General Control Register 3" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" newline bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" newline bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16-bit data format" "RGB565,ARGB555" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" else group.long 0xC++0x03 line.long 0x00 "CTRL3,LCDIF General Control Register 3" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" newline bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,16-bit data format" "RGB565,ARGB555" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" endif elif ((per.l(ad:0x5A180000+0xC)&0x300)==0x200) if (((per.l(ad:0x5A180000+0xC)&0x40000)==0x00)&&((per.l(ad:0x5A180000+0xC)&0x01)==0x00)) group.long 0xC++0x03 line.long 0x00 "CTRL3,LCDIF General Control Register 3" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" newline bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" newline bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18-bit data format/alingment" "18 bpp RGB666/lower bits,18 bpp RGB666/higher bits" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" elif (((per.l(ad:0x5A180000+0xC)&0x40000)==0x4000)&&((per.l(ad:0x5A180000+0xC)&0x01)==0x00)) group.long 0xC++0x03 line.long 0x00 "CTRL3,LCDIF General Control Register 3" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" newline bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18-bit data format/alingment" "18 bpp RGB666/lower bits,18 bpp RGB666/higher bits" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" elif (((per.l(ad:0x5A180000+0xC)&0x40000)==0x00)&&((per.l(ad:0x5A180000+0xC)&0x01)==0x01)) group.long 0xC++0x03 line.long 0x00 "CTRL3,LCDIF General Control Register 3" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" newline bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" newline bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18-bit data format/alingment" "18 bpp RGB666/lower bits,18 bpp RGB666/higher bits" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" else group.long 0xC++0x03 line.long 0x00 "CTRL3,LCDIF General Control Register 3" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" newline bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,18-bit data format/alingment" "18 bpp RGB666/lower bits,18 bpp RGB666/higher bits" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" endif elif ((per.l(ad:0x5A180000+0xC)&0x300)==0x300) if (((per.l(ad:0x5A180000+0xC)&0x40000)==0x00)&&((per.l(ad:0x5A180000+0xC)&0x01)==0x00)) group.long 0xC++0x03 line.long 0x00 "CTRL3,LCDIF General Control Register 3" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" newline bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" newline bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24-bit data format" "24 bpp RGB888,18 bpp 1 color per byte" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" elif (((per.l(ad:0x5A180000+0xC)&0x40000)==0x4000)&&((per.l(ad:0x5A180000+0xC)&0x01)==0x00)) group.long 0xC++0x03 line.long 0x00 "CTRL3,LCDIF General Control Register 3" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" newline bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24-bit data format" "24 bpp RGB888,18 bpp 1 color per byte" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" elif (((per.l(ad:0x5A180000+0xC)&0x40000)==0x00)&&((per.l(ad:0x5A180000+0xC)&0x01)==0x01)) group.long 0xC++0x03 line.long 0x00 "CTRL3,LCDIF General Control Register 3" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" newline bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" newline bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24-bit data format" "24 bpp RGB888,18 bpp 1 color per byte" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" else group.long 0xC++0x03 line.long 0x00 "CTRL3,LCDIF General Control Register 3" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" newline bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,24-bit data format" "24 bpp RGB888,18 bpp 1 color per byte" bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" endif else if (((per.l(ad:0x5A180000+0xC)&0x40000)==0x00)&&((per.l(ad:0x5A180000+0xC)&0x01)==0x00)) group.long 0xC++0x03 line.long 0x00 "CTRL3,LCDIF General Control Register 3" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" newline bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" newline bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" elif (((per.l(ad:0x5A180000+0xC)&0x40000)==0x4000)&&((per.l(ad:0x5A180000+0xC)&0x01)==0x00)) group.long 0xC++0x03 line.long 0x00 "CTRL3,LCDIF General Control Register 3" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" newline bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" elif (((per.l(ad:0x5A180000+0xC)&0x40000)==0x00)&&((per.l(ad:0x5A180000+0xC)&0x01)==0x01)) group.long 0xC++0x03 line.long 0x00 "CTRL3,LCDIF General Control Register 3" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" newline bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" newline bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" else group.long 0xC++0x03 line.long 0x00 "CTRL3,LCDIF General Control Register 3" bitfld.long 0x00 31. " SFTRST ,Force block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " YCBCR422_INPUT ,Input data colorspace" "RGB,YCbCr 4:2:2" bitfld.long 0x00 28. " READ_WRITEB ,R/W mode select" "Write,Read" newline bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Direction of shift of transmit data" "Left,Right" newline bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,ITU-R BT.656 digital video interface mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BYPASS_COUNT ,Indefinitely continuing normal operation by block until it is told to stop enable" "Disabled,Enabled" bitfld.long 0x00 18. " VSYNC_MODE ,VSYNC mode enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DOTCLK_MODE ,DOTCLK mode enable" "Disabled,Enabled" rbitfld.long 0x00 16. " DATA_SELECT ,Mode/Polarity select bit" "Command/Low,Data/High" newline bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Bytes fetched by the bus master interface swap configuration" "NO_SWAP,BIG_ENDIAN_SWAP,HWD_SWAP,HWD_BYTE_SWAP" newline bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" newline bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,RGB to YCbCr colorspace conversion enable" "Disabled,Enabled" bitfld.long 0x00 5. " MASTER ,LCDIF act as a bus master enable" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 0. " RUN ,LCDIF start transferring data bit between the SoC and the display" "Not started,Started" endif endif tree.end tree "Control 1 Registers" if ((per.l(ad:0x5A180000+0x0)&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "CTRL10,LCDIF General Control 1 Register 0" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Selects pin on which write strobe will be driven in 6800 and 8080 modes" "LCD_RD_E(6800)/LCD_WR_RW0(8080),LCD_WR_RW0(both 6800 and 8080)" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode." "Disabled,Enabled" newline bitfld.long 0x00 25. " BM_ERROR_IRQ ,Bus master error interrupt is requested by the LCDIF block" "Not requested,Requested" bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,LCDIF recover on underflow enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "Disabled,Enabled" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "Disabled,Enabled" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Latency FIFO (LFIFO)/TXFIFO/RXFIFO clear" "Not cleared,Cleared" bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,If this bit is set the LCDIF block will assert the CUR_FRAME_DONE interrupt only on alternate fields" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. " BYTE_PACKING_FORMAT ,This bitfield is used to show which data bytes in a 32-bit word are valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Overflow interrupt in the TXFIFO in the write mode enable" "Disabled,Enabled" newline bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Underflow interrupt in the TXFIFO in the write mode enable" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,In VSYNC/DOTCLK mode leading edge encounter interrupt and in DVI mode beginning of new field interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the LCDIF block" "Not requested,Requested" newline bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the LCDIF block" "Not requested,Requested" bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,CUR_FRAME_DONE interrupt is requested by the LCDIF block" "Not requested,Requested" newline bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,VSYNC_EDGE interrupt is requested by the LCDIF block" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,This bit enables the use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,This bit is used to select between the 8080 and 6800 series of microprocessor modes" "8080,6800" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "Low,High" else group.long 0x10++0x03 line.long 0x00 "CTRL10,LCDIF General Control 1 Register 0" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Selects pin on which write strobe will be driven in 6800 and 8080 modes" "LCD_RD_E(6800)/LCD_WR_RW0(8080),LCD_WR_RW0(both 6800 and 8080)" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode." "Disabled,Enabled" newline bitfld.long 0x00 25. " BM_ERROR_IRQ ,Bus master error interrupt is requested by the LCDIF block" "Not requested,Requested" bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,LCDIF recover on underflow enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "Disabled,Enabled" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "Disabled,Enabled" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Latency FIFO (LFIFO)/TXFIFO/RXFIFO clear" "Not cleared,Cleared" bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,If this bit is set the LCDIF block will assert the CUR_FRAME_DONE interrupt only on alternate fields" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. " BYTE_PACKING_FORMAT ,This bitfield is used to show which data bytes in a 32-bit word are valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Overflow interrupt in the TXFIFO in the write mode enable" "Disabled,Enabled" newline bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Underflow interrupt in the TXFIFO in the write mode enable" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,In VSYNC/DOTCLK mode leading edge encounter interrupt and in DVI mode beginning of new field interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the LCDIF block" "Not requested,Requested" newline bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the LCDIF block" "Not requested,Requested" bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,CUR_FRAME_DONE interrupt is requested by the LCDIF block" "Not requested,Requested" newline bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,VSYNC_EDGE interrupt is requested by the LCDIF block" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,This bit enables the use of the interface's busy signal input" "Disabled,Enabled" newline rbitfld.long 0x00 1. " MODE86 ,This bit is used to select between the 8080 and 6800 series of microprocessor modes" "8080,6800" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "Low,High" endif if ((per.l(ad:0x5A180000+0x4)&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "CTRL11,LCDIF General Control 1 Register 1" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Selects pin on which write strobe will be driven in 6800 and 8080 modes" "LCD_RD_E(6800)/LCD_WR_RW1(8080),LCD_WR_RW1(both 6800 and 8080)" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode." "Disabled,Enabled" newline bitfld.long 0x00 25. " BM_ERROR_IRQ ,Bus master error interrupt is requested by the LCDIF block" "Not requested,Requested" bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,LCDIF recover on underflow enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "Disabled,Enabled" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "Disabled,Enabled" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Latency FIFO (LFIFO)/TXFIFO/RXFIFO clear" "Not cleared,Cleared" bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,If this bit is set the LCDIF block will assert the CUR_FRAME_DONE interrupt only on alternate fields" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. " BYTE_PACKING_FORMAT ,This bitfield is used to show which data bytes in a 32-bit word are valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Overflow interrupt in the TXFIFO in the write mode enable" "Disabled,Enabled" newline bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Underflow interrupt in the TXFIFO in the write mode enable" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,In VSYNC/DOTCLK mode leading edge encounter interrupt and in DVI mode beginning of new field interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the LCDIF block" "Not requested,Requested" newline bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the LCDIF block" "Not requested,Requested" bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,CUR_FRAME_DONE interrupt is requested by the LCDIF block" "Not requested,Requested" newline bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,VSYNC_EDGE interrupt is requested by the LCDIF block" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,This bit enables the use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,This bit is used to select between the 8080 and 6800 series of microprocessor modes" "8080,6800" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "Low,High" else group.long 0x14++0x03 line.long 0x00 "CTRL11,LCDIF General Control 1 Register 1" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Selects pin on which write strobe will be driven in 6800 and 8080 modes" "LCD_RD_E(6800)/LCD_WR_RW1(8080),LCD_WR_RW1(both 6800 and 8080)" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode." "Disabled,Enabled" newline bitfld.long 0x00 25. " BM_ERROR_IRQ ,Bus master error interrupt is requested by the LCDIF block" "Not requested,Requested" bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,LCDIF recover on underflow enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "Disabled,Enabled" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "Disabled,Enabled" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Latency FIFO (LFIFO)/TXFIFO/RXFIFO clear" "Not cleared,Cleared" bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,If this bit is set the LCDIF block will assert the CUR_FRAME_DONE interrupt only on alternate fields" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. " BYTE_PACKING_FORMAT ,This bitfield is used to show which data bytes in a 32-bit word are valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Overflow interrupt in the TXFIFO in the write mode enable" "Disabled,Enabled" newline bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Underflow interrupt in the TXFIFO in the write mode enable" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,In VSYNC/DOTCLK mode leading edge encounter interrupt and in DVI mode beginning of new field interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the LCDIF block" "Not requested,Requested" newline bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the LCDIF block" "Not requested,Requested" bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,CUR_FRAME_DONE interrupt is requested by the LCDIF block" "Not requested,Requested" newline bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,VSYNC_EDGE interrupt is requested by the LCDIF block" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,This bit enables the use of the interface's busy signal input" "Disabled,Enabled" newline rbitfld.long 0x00 1. " MODE86 ,This bit is used to select between the 8080 and 6800 series of microprocessor modes" "8080,6800" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "Low,High" endif if ((per.l(ad:0x5A180000+0x8)&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "CTRL12,LCDIF General Control 1 Register 2" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Selects pin on which write strobe will be driven in 6800 and 8080 modes" "LCD_RD_E(6800)/LCD_WR_RW2(8080),LCD_WR_RW2(both 6800 and 8080)" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode." "Disabled,Enabled" newline bitfld.long 0x00 25. " BM_ERROR_IRQ ,Bus master error interrupt is requested by the LCDIF block" "Not requested,Requested" bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,LCDIF recover on underflow enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "Disabled,Enabled" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "Disabled,Enabled" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Latency FIFO (LFIFO)/TXFIFO/RXFIFO clear" "Not cleared,Cleared" bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,If this bit is set the LCDIF block will assert the CUR_FRAME_DONE interrupt only on alternate fields" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. " BYTE_PACKING_FORMAT ,This bitfield is used to show which data bytes in a 32-bit word are valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Overflow interrupt in the TXFIFO in the write mode enable" "Disabled,Enabled" newline bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Underflow interrupt in the TXFIFO in the write mode enable" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,In VSYNC/DOTCLK mode leading edge encounter interrupt and in DVI mode beginning of new field interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the LCDIF block" "Not requested,Requested" newline bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the LCDIF block" "Not requested,Requested" bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,CUR_FRAME_DONE interrupt is requested by the LCDIF block" "Not requested,Requested" newline bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,VSYNC_EDGE interrupt is requested by the LCDIF block" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,This bit enables the use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,This bit is used to select between the 8080 and 6800 series of microprocessor modes" "8080,6800" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "Low,High" else group.long 0x18++0x03 line.long 0x00 "CTRL12,LCDIF General Control 1 Register 2" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Selects pin on which write strobe will be driven in 6800 and 8080 modes" "LCD_RD_E(6800)/LCD_WR_RW2(8080),LCD_WR_RW2(both 6800 and 8080)" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode." "Disabled,Enabled" newline bitfld.long 0x00 25. " BM_ERROR_IRQ ,Bus master error interrupt is requested by the LCDIF block" "Not requested,Requested" bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,LCDIF recover on underflow enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "Disabled,Enabled" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "Disabled,Enabled" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Latency FIFO (LFIFO)/TXFIFO/RXFIFO clear" "Not cleared,Cleared" bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,If this bit is set the LCDIF block will assert the CUR_FRAME_DONE interrupt only on alternate fields" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. " BYTE_PACKING_FORMAT ,This bitfield is used to show which data bytes in a 32-bit word are valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Overflow interrupt in the TXFIFO in the write mode enable" "Disabled,Enabled" newline bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Underflow interrupt in the TXFIFO in the write mode enable" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,In VSYNC/DOTCLK mode leading edge encounter interrupt and in DVI mode beginning of new field interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the LCDIF block" "Not requested,Requested" newline bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the LCDIF block" "Not requested,Requested" bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,CUR_FRAME_DONE interrupt is requested by the LCDIF block" "Not requested,Requested" newline bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,VSYNC_EDGE interrupt is requested by the LCDIF block" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,This bit enables the use of the interface's busy signal input" "Disabled,Enabled" newline rbitfld.long 0x00 1. " MODE86 ,This bit is used to select between the 8080 and 6800 series of microprocessor modes" "8080,6800" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "Low,High" endif if ((per.l(ad:0x5A180000+0xC)&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "CTRL13,LCDIF General Control 1 Register 3" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Selects pin on which write strobe will be driven in 6800 and 8080 modes" "LCD_RD_E(6800)/LCD_WR_RW3(8080),LCD_WR_RW3(both 6800 and 8080)" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode." "Disabled,Enabled" newline bitfld.long 0x00 25. " BM_ERROR_IRQ ,Bus master error interrupt is requested by the LCDIF block" "Not requested,Requested" bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,LCDIF recover on underflow enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "Disabled,Enabled" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "Disabled,Enabled" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Latency FIFO (LFIFO)/TXFIFO/RXFIFO clear" "Not cleared,Cleared" bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,If this bit is set the LCDIF block will assert the CUR_FRAME_DONE interrupt only on alternate fields" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. " BYTE_PACKING_FORMAT ,This bitfield is used to show which data bytes in a 32-bit word are valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Overflow interrupt in the TXFIFO in the write mode enable" "Disabled,Enabled" newline bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Underflow interrupt in the TXFIFO in the write mode enable" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,In VSYNC/DOTCLK mode leading edge encounter interrupt and in DVI mode beginning of new field interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the LCDIF block" "Not requested,Requested" newline bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the LCDIF block" "Not requested,Requested" bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,CUR_FRAME_DONE interrupt is requested by the LCDIF block" "Not requested,Requested" newline bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,VSYNC_EDGE interrupt is requested by the LCDIF block" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,This bit enables the use of the interface's busy signal input" "Disabled,Enabled" newline bitfld.long 0x00 1. " MODE86 ,This bit is used to select between the 8080 and 6800 series of microprocessor modes" "8080,6800" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "Low,High" else group.long 0x1C++0x03 line.long 0x00 "CTRL13,LCDIF General Control 1 Register 3" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Selects pin on which write strobe will be driven in 6800 and 8080 modes" "LCD_RD_E(6800)/LCD_WR_RW3(8080),LCD_WR_RW3(both 6800 and 8080)" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode." "Disabled,Enabled" newline bitfld.long 0x00 25. " BM_ERROR_IRQ ,Bus master error interrupt is requested by the LCDIF block" "Not requested,Requested" bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,LCDIF recover on underflow enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "Disabled,Enabled" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "Disabled,Enabled" newline bitfld.long 0x00 21. " FIFO_CLEAR ,Latency FIFO (LFIFO)/TXFIFO/RXFIFO clear" "Not cleared,Cleared" bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,If this bit is set the LCDIF block will assert the CUR_FRAME_DONE interrupt only on alternate fields" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. " BYTE_PACKING_FORMAT ,This bitfield is used to show which data bytes in a 32-bit word are valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Overflow interrupt in the TXFIFO in the write mode enable" "Disabled,Enabled" newline bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Underflow interrupt in the TXFIFO in the write mode enable" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state" "Disabled,Enabled" newline bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,In VSYNC/DOTCLK mode leading edge encounter interrupt and in DVI mode beginning of new field interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Overflow interrupt is requested by the LCDIF block" "Not requested,Requested" newline bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Underflow interrupt is requested by the LCDIF block" "Not requested,Requested" bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,CUR_FRAME_DONE interrupt is requested by the LCDIF block" "Not requested,Requested" newline bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,VSYNC_EDGE interrupt is requested by the LCDIF block" "Not requested,Requested" bitfld.long 0x00 2. " BUSY_ENABLE ,This bit enables the use of the interface's busy signal input" "Disabled,Enabled" newline rbitfld.long 0x00 1. " MODE86 ,This bit is used to select between the 8080 and 6800 series of microprocessor modes" "8080,6800" bitfld.long 0x00 0. " RESET ,Reset bit for the external LCD controller" "Low,High" endif tree.end tree "Control 2 Registers" if ((per.l(ad:0x5A180000+0x0)&0x20)==0x20) group.long 0x20++0x03 line.long 0x00 "CTRL20,LCDIF General Control 2 Register 0" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master" "1,2,4,8,16,?..." bitfld.long 0x00 20. " BURST_LEN_8 ,AXI bursts of length 8 (9 in packed 24 bpp mode) enable" "Disabled,Enabled" newline bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,This field determines the order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,This field determines the order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." newline bitfld.long 0x00 10. " READ_PACK_DIR ,Stored data endian format" "Little endian,Big endian" bitfld.long 0x00 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Convert incoming data to the RGB format given by WORD_LENGTH bitfield" "Disabled,Enabled" newline bitfld.long 0x00 8. " READ_MODE_6_BIT_INPUT ,Input data is 6-bit wide in LCD_DATABUS_WIDTH[8-bit] mode" "No,Yes" bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,?..." newline bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,The value in this field determines the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" else group.long 0x20++0x03 line.long 0x00 "CTRL20,LCDIF General Control 2 Register 0" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master" "1,2,4,8,16,?..." bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,This field determines the order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." newline bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,This field determines the order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 10. " READ_PACK_DIR ,Stored data endian format" "Little endian,Big endian" newline bitfld.long 0x00 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Convert incoming data to the RGB format given by WORD_LENGTH bitfield" "Disabled,Enabled" bitfld.long 0x00 8. " READ_MODE_6_BIT_INPUT ,Input data is 6-bit wide in LCD_DATABUS_WIDTH[8-bit] mode" "No,Yes" newline bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,?..." bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,The value in this field determines the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" endif if ((per.l(ad:0x5A180000+0x4)&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "CTRL21,LCDIF General Control 2 Register 1" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master" "1,2,4,8,16,?..." bitfld.long 0x00 20. " BURST_LEN_8 ,AXI bursts of length 8 (9 in packed 24 bpp mode) enable" "Disabled,Enabled" newline bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,This field determines the order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,This field determines the order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." newline bitfld.long 0x00 10. " READ_PACK_DIR ,Stored data endian format" "Little endian,Big endian" bitfld.long 0x00 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Convert incoming data to the RGB format given by WORD_LENGTH bitfield" "Disabled,Enabled" newline bitfld.long 0x00 8. " READ_MODE_6_BIT_INPUT ,Input data is 6-bit wide in LCD_DATABUS_WIDTH[8-bit] mode" "No,Yes" bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,?..." newline bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,The value in this field determines the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" else group.long 0x24++0x03 line.long 0x00 "CTRL21,LCDIF General Control 2 Register 1" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master" "1,2,4,8,16,?..." bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,This field determines the order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." newline bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,This field determines the order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 10. " READ_PACK_DIR ,Stored data endian format" "Little endian,Big endian" newline bitfld.long 0x00 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Convert incoming data to the RGB format given by WORD_LENGTH bitfield" "Disabled,Enabled" bitfld.long 0x00 8. " READ_MODE_6_BIT_INPUT ,Input data is 6-bit wide in LCD_DATABUS_WIDTH[8-bit] mode" "No,Yes" newline bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,?..." bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,The value in this field determines the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" endif if ((per.l(ad:0x5A180000+0x8)&0x20)==0x20) group.long 0x28++0x03 line.long 0x00 "CTRL22,LCDIF General Control 2 Register 2" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master" "1,2,4,8,16,?..." bitfld.long 0x00 20. " BURST_LEN_8 ,AXI bursts of length 8 (9 in packed 24 bpp mode) enable" "Disabled,Enabled" newline bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,This field determines the order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,This field determines the order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." newline bitfld.long 0x00 10. " READ_PACK_DIR ,Stored data endian format" "Little endian,Big endian" bitfld.long 0x00 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Convert incoming data to the RGB format given by WORD_LENGTH bitfield" "Disabled,Enabled" newline bitfld.long 0x00 8. " READ_MODE_6_BIT_INPUT ,Input data is 6-bit wide in LCD_DATABUS_WIDTH[8-bit] mode" "No,Yes" bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,?..." newline bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,The value in this field determines the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" else group.long 0x28++0x03 line.long 0x00 "CTRL22,LCDIF General Control 2 Register 2" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master" "1,2,4,8,16,?..." bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,This field determines the order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." newline bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,This field determines the order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 10. " READ_PACK_DIR ,Stored data endian format" "Little endian,Big endian" newline bitfld.long 0x00 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Convert incoming data to the RGB format given by WORD_LENGTH bitfield" "Disabled,Enabled" bitfld.long 0x00 8. " READ_MODE_6_BIT_INPUT ,Input data is 6-bit wide in LCD_DATABUS_WIDTH[8-bit] mode" "No,Yes" newline bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,?..." bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,The value in this field determines the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" endif if ((per.l(ad:0x5A180000+0xC)&0x20)==0x20) group.long 0x2C++0x03 line.long 0x00 "CTRL23,LCDIF General Control 2 Register 3" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master" "1,2,4,8,16,?..." bitfld.long 0x00 20. " BURST_LEN_8 ,AXI bursts of length 8 (9 in packed 24 bpp mode) enable" "Disabled,Enabled" newline bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,This field determines the order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,This field determines the order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." newline bitfld.long 0x00 10. " READ_PACK_DIR ,Stored data endian format" "Little endian,Big endian" bitfld.long 0x00 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Convert incoming data to the RGB format given by WORD_LENGTH bitfield" "Disabled,Enabled" newline bitfld.long 0x00 8. " READ_MODE_6_BIT_INPUT ,Input data is 6-bit wide in LCD_DATABUS_WIDTH[8-bit] mode" "No,Yes" bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,?..." newline bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,The value in this field determines the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" else group.long 0x2C++0x03 line.long 0x00 "CTRL23,LCDIF General Control 2 Register 3" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master" "1,2,4,8,16,?..." bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,This field determines the order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." newline bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,This field determines the order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 10. " READ_PACK_DIR ,Stored data endian format" "Little endian,Big endian" newline bitfld.long 0x00 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Convert incoming data to the RGB format given by WORD_LENGTH bitfield" "Disabled,Enabled" bitfld.long 0x00 8. " READ_MODE_6_BIT_INPUT ,Input data is 6-bit wide in LCD_DATABUS_WIDTH[8-bit] mode" "No,Yes" newline bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,?..." bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,The value in this field determines the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" endif tree.end group.long 0x30++0x03 line.long 0x00 "TRANSFER_COUNT,LCDIF Horizontal And Vertical Valid Data Count Register" hexmask.long.word 0x00 16.--31. 1. " V_COUNT ,Number of horizontal lines per frame which contain valid data" hexmask.long.word 0x00 0.--15. 1. " H_COUNT ,Total valid data (pixels) in each horizontal line" group.long 0x40++0x03 line.long 0x00 "CUR_BUF,LCD Interface Current Buffer Address Register" group.long 0x50++0x03 line.long 0x00 "NEXT_BUF,LCD Interface Next Buffer Address Register" group.long 0x60++0x03 line.long 0x00 "TIMING,LCD Interface Timing Register" hexmask.long.byte 0x00 24.--31. 1. " CMD_HOLD ,Number of DISPLAY CLOCK (pix_clk) cycles that the LCD_RS signal is active after LCD_CS is deasserted" hexmask.long.byte 0x00 16.--23. 1. " CMD_SETUP ,Number of DISPLAY CLOCK (pix_clk) cycles that the LCD_RS signal is active before LCD_CS is asserted" newline hexmask.long.byte 0x00 8.--15. 1. " DATA_HOLD ,Data bus hold time in DISPLAY CLOCK (pix_clk) cycles" hexmask.long.byte 0x00 0.--7. 1. " DATA_SETUP ,Data bus setup time in DISPLAY CLOCK (pix_clk) cycles" group.long 0x70++0x03 line.long 0x00 "VDCTRL00,LCDIF VSYNC Mode And Dotclk Mode Control Register 00" bitfld.long 0x00 29. " VSYNC_OEB ,VSYNC input/output" "Output,Input" bitfld.long 0x00 28. " ENABLE_PRESENT ,Generate the ENABLE signal in the DOTCLK mode" "Not generated,Generated" newline bitfld.long 0x00 27. " VSYNC_POL ,Polarity during VSYNC_PULSE_WIDTH time/rest of the VSYNC period" "Active low/Active high,Active high/Active low" bitfld.long 0x00 26. " HSYNC_POL ,Polarity during HSYNC_PULSE_WIDTH time/rest of the HSYNC period" "Active low/Active high,Active high/Active low" newline bitfld.long 0x00 25. " DOTCLK_POL ,DOTCLK edge for data launch/capture" "Negative/Positive,Positive/Negative" bitfld.long 0x00 24. " ENABLE_POL ,Polarity during valid data transfer on each horizontal line" "Active low,Active high" newline bitfld.long 0x00 21. " VSYNC_PERIOD_UNIT ,VSYNC_PERIOD field unit" "DISPLAY CLOCK cycle,Complete horizontal line" bitfld.long 0x00 20. " VSYNC_PULSE_WIDTH_UNIT ,VSYNC_PULSE_WIDTH field unit" "DISPLAY CLOCK cycle,Complete horizontal line" newline bitfld.long 0x00 19. " HALF_LINE ,Extend the VSYNC period (VSYNC_PERIOD field value) with half of the horizontal line (HORIZONTAL_PERIOD field value)" "Disabled,Enabled" bitfld.long 0x00 18. " HALF_LINE_MODE ,Half line mode enable [all fields will end with half a horizontal line]" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" group.long 0x74++0x03 line.long 0x00 "VDCTRL01,LCDIF VSYNC Mode And Dotclk Mode Control Register 01" bitfld.long 0x00 29. " VSYNC_OEB ,VSYNC input/output" "Output,Input" bitfld.long 0x00 28. " ENABLE_PRESENT ,Generate the ENABLE signal in the DOTCLK mode" "Not generated,Generated" newline bitfld.long 0x00 27. " VSYNC_POL ,Polarity during VSYNC_PULSE_WIDTH time/rest of the VSYNC period" "Active low/Active high,Active high/Active low" bitfld.long 0x00 26. " HSYNC_POL ,Polarity during HSYNC_PULSE_WIDTH time/rest of the HSYNC period" "Active low/Active high,Active high/Active low" newline bitfld.long 0x00 25. " DOTCLK_POL ,DOTCLK edge for data launch/capture" "Negative/Positive,Positive/Negative" bitfld.long 0x00 24. " ENABLE_POL ,Polarity during valid data transfer on each horizontal line" "Active low,Active high" newline bitfld.long 0x00 21. " VSYNC_PERIOD_UNIT ,VSYNC_PERIOD field unit" "DISPLAY CLOCK cycle,Complete horizontal line" bitfld.long 0x00 20. " VSYNC_PULSE_WIDTH_UNIT ,VSYNC_PULSE_WIDTH field unit" "DISPLAY CLOCK cycle,Complete horizontal line" newline bitfld.long 0x00 19. " HALF_LINE ,Extend the VSYNC period (VSYNC_PERIOD field value) with half of the horizontal line (HORIZONTAL_PERIOD field value)" "Disabled,Enabled" bitfld.long 0x00 18. " HALF_LINE_MODE ,Half line mode enable [all fields will end with half a horizontal line]" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" group.long 0x78++0x03 line.long 0x00 "VDCTRL02,LCDIF VSYNC Mode And Dotclk Mode Control Register 02" bitfld.long 0x00 29. " VSYNC_OEB ,VSYNC input/output" "Output,Input" bitfld.long 0x00 28. " ENABLE_PRESENT ,Generate the ENABLE signal in the DOTCLK mode" "Not generated,Generated" newline bitfld.long 0x00 27. " VSYNC_POL ,Polarity during VSYNC_PULSE_WIDTH time/rest of the VSYNC period" "Active low/Active high,Active high/Active low" bitfld.long 0x00 26. " HSYNC_POL ,Polarity during HSYNC_PULSE_WIDTH time/rest of the HSYNC period" "Active low/Active high,Active high/Active low" newline bitfld.long 0x00 25. " DOTCLK_POL ,DOTCLK edge for data launch/capture" "Negative/Positive,Positive/Negative" bitfld.long 0x00 24. " ENABLE_POL ,Polarity during valid data transfer on each horizontal line" "Active low,Active high" newline bitfld.long 0x00 21. " VSYNC_PERIOD_UNIT ,VSYNC_PERIOD field unit" "DISPLAY CLOCK cycle,Complete horizontal line" bitfld.long 0x00 20. " VSYNC_PULSE_WIDTH_UNIT ,VSYNC_PULSE_WIDTH field unit" "DISPLAY CLOCK cycle,Complete horizontal line" newline bitfld.long 0x00 19. " HALF_LINE ,Extend the VSYNC period (VSYNC_PERIOD field value) with half of the horizontal line (HORIZONTAL_PERIOD field value)" "Disabled,Enabled" bitfld.long 0x00 18. " HALF_LINE_MODE ,Half line mode enable [all fields will end with half a horizontal line]" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" group.long 0x7C++0x03 line.long 0x00 "VDCTRL03,LCDIF VSYNC Mode And Dotclk Mode Control Register 03" bitfld.long 0x00 29. " VSYNC_OEB ,VSYNC input/output" "Output,Input" bitfld.long 0x00 28. " ENABLE_PRESENT ,Generate the ENABLE signal in the DOTCLK mode" "Not generated,Generated" newline bitfld.long 0x00 27. " VSYNC_POL ,Polarity during VSYNC_PULSE_WIDTH time/rest of the VSYNC period" "Active low/Active high,Active high/Active low" bitfld.long 0x00 26. " HSYNC_POL ,Polarity during HSYNC_PULSE_WIDTH time/rest of the HSYNC period" "Active low/Active high,Active high/Active low" newline bitfld.long 0x00 25. " DOTCLK_POL ,DOTCLK edge for data launch/capture" "Negative/Positive,Positive/Negative" bitfld.long 0x00 24. " ENABLE_POL ,Polarity during valid data transfer on each horizontal line" "Active low,Active high" newline bitfld.long 0x00 21. " VSYNC_PERIOD_UNIT ,VSYNC_PERIOD field unit" "DISPLAY CLOCK cycle,Complete horizontal line" bitfld.long 0x00 20. " VSYNC_PULSE_WIDTH_UNIT ,VSYNC_PULSE_WIDTH field unit" "DISPLAY CLOCK cycle,Complete horizontal line" newline bitfld.long 0x00 19. " HALF_LINE ,Extend the VSYNC period (VSYNC_PERIOD field value) with half of the horizontal line (HORIZONTAL_PERIOD field value)" "Disabled,Enabled" bitfld.long 0x00 18. " HALF_LINE_MODE ,Half line mode enable [all fields will end with half a horizontal line]" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" group.long 0x80++0x03 line.long 0x00 "VDCTRL1,LCDIF VSYNC Mode And Dotclk Mode Control Register 1" group.long 0x90++0x03 line.long 0x00 "VDCTRL2,LCDIF VSYNC Mode And Dotclk Mode Control Register 2" hexmask.long.word 0x00 18.--31. 1. " HSYNC_PULSE_WIDTH ,Number of DISPLAY CLOCK (pix_clk) cycles for which HSYNC signal is active" hexmask.long.tbyte 0x00 0.--17. 1. " HSYNC_PERIOD ,Total number of DISPLAY CLOCK (pix_clk) cycles between two positive or two negative edges of the HSYNC signal" group.long 0xA0++0x03 line.long 0x00 "VDCTRL3,LCDIF VSYNC Mode And Dotclk Mode Control Register 3" bitfld.long 0x00 29. " MUX_SYNC_SIGNALS ,Internally mux HSYNC with LCD_D14; DOTCLK with LCD_D13; ENABLE with LCD_D12 [these signals will go out on separate pins if disabled]" "Disabled,Enabled" bitfld.long 0x00 28. " VSYNC_ONLY ,Mode of operation additional control bit" "DOTCLK,VSYNC" newline hexmask.long.word 0x00 16.--27. 1. " HORIZONTAL_WAIT_CNT ,In the DOTCLK mode wait for this number of clocks from edge of HSYNC signal to account for horizontal back porch plus the number of DOTCLKs before the moving picture information begins" hexmask.long.word 0x00 0.--15. 1. " VERTICAL_WAIT_CNT ,Number of DISPLAY CLOCK (pix_clk) cycles from the VSYNC edge before starting LCD transactions [applicable only if WAIT_FOR_VSYNC_EDGE is set]" group.long 0xB0++0x03 line.long 0x00 "VDCTRL4,LCDIF VSYNC Mode And Dotclk Mode Control Register 4" bitfld.long 0x00 29.--31. " DOTCLK_DLY_SEL ,Amount of time by which the DOTCLK signal should be delayed before coming out of the LCD_DOTCK pin" "2 ns,4 ns,6 ns,8 ns,?..." bitfld.long 0x00 18. " SYNC_SIGNALS_ON ,VSYNC/HSYNC/DOTCLK control signals active at least one frame before the data transfers start and remain active at least one frame after the data transfers end" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 0.--17. 1. " DOTCLK_H_VALID_DATA_CNT ,Total number of DISPLAY CLOCK (pix_clk) cycles on each horizontal line that carry valid data in DOTCLK mode" group.long 0xC0++0x03 line.long 0x00 "DVICTRL0,Digital Video Interface Control 0 Register" hexmask.long.word 0x00 16.--27. 1. " H_ACTIVE_CNT ,Number of active video samples to be transmitted" hexmask.long.word 0x00 0.--11. 1. " H_BLANKING_CNT ,Number of blanking samples to be inserted between EAV and SAV during horizontal blanking interval" group.long 0xD0++0x03 line.long 0x00 "DVICTRL1,Digital Video Interface Control 1 Register" hexmask.long.word 0x00 20.--29. 1. " F1_START_LINE ,Vertical line number from which Field 1 begins" hexmask.long.word 0x00 10.--19. 1. " F1_END_LINE ,Vertical line number at which Field1 ends" newline hexmask.long.word 0x00 0.--9. 1. " F2_START_LINE ,Vertical line number from which Field 2 begins" group.long 0xE0++0x03 line.long 0x00 "DVICTRL2,Digital Video Interface Control 2 Register" hexmask.long.word 0x00 20.--29. 1. " F2_END_LINE ,Vertical line number at which Field 2 ends" hexmask.long.word 0x00 10.--19. 1. " V1_BLANK_START_LINE ,Vertical line number towards the end of Field1 where first Vertical Blanking interval starts" newline hexmask.long.word 0x00 0.--9. 1. " V1_BLANK_END_LINE ,Vertical line number in the beginning part of Field2 where first Vertical Blanking interval ends" group.long 0xF0++0x03 line.long 0x00 "DVICTRL3,Digital Video Interface Control 3 Register" hexmask.long.word 0x00 20.--29. 1. " V2_BLANK_START_LINE ,Vertical line number towards the end of Field2 where second Vertical Blanking interval starts" hexmask.long.word 0x00 10.--19. 1. " V2_BLANK_END_LINE ,Vertical line number in the beginning part of Field1 where second Vertical Blanking interval ends" newline hexmask.long.word 0x00 0.--9. 1. " V_LINES_CNT ,Total number of vertical lines per frame (generally 525 or 625)" group.long 0x100++0x03 line.long 0x00 "DVICTRL4,Digital Video Interface Control 4 Register" hexmask.long.byte 0x00 24.--31. 1. " Y_FILL_VALUE ,Value of Y component of filler data" hexmask.long.byte 0x00 16.--23. 1. " CB_FILL_VALUE ,Value of CB component of filler data" newline hexmask.long.byte 0x00 8.--15. 1. " CR_FILL_VALUE ,Value of CR component of filler data" hexmask.long.byte 0x00 0.--7. 1. " H_FILL_CNT ,Number of active video samples that have to be filled with the filler data in the front and back portions of the active horizontal interval" group.long 0x110++0x03 line.long 0x00 "CSC_COEFF0,RGB To YCbCr 4:2:2 CSC Coefficient 0 Register" hexmask.long.word 0x00 16.--25. 1. " C0 ,Two's complement red multiplier coefficient for Y" bitfld.long 0x00 0.--1. " CSC_SUBSAMPLE_FILTER ,Filtering and subsampling scheme to be performed on the chroma components in order to convert from YCbCr 4:4:4 to YCbCr 4:2:2 space" "Sample and hold,,Interstitial,Cosited" group.long 0x120++0x03 line.long 0x00 "CSC_COEFF1,RGB To YCbCr 4:2:2 CSC Coefficient 1 Register" hexmask.long.word 0x00 16.--25. 1. " C2 ,Two's complement blue multiplier coefficient for Y" hexmask.long.word 0x00 0.--9. 1. " C1 ,Two's complement green multiplier coefficient for Y" group.long 0x130++0x03 line.long 0x00 "CSC_COEFF2,RGB To YCbCr 4:2:2 CSC Coefficent 2 Register" hexmask.long.word 0x00 16.--25. 1. " C4 ,Two's complement green multiplier coefficient for Cb" hexmask.long.word 0x00 0.--9. 1. " C3 ,Two's complement red multiplier coefficient for Cb" group.long 0x140++0x03 line.long 0x00 "CSC_COEFF3,RGB To YCbCr 4:2:2 CSC Coefficient 3 Register" hexmask.long.word 0x00 16.--25. 1. " C6 ,Two's complement red multiplier coefficient for Cr" hexmask.long.word 0x00 0.--9. 1. " C5 ,Two's complement blue multiplier coefficient for Cb" group.long 0x150++0x03 line.long 0x00 "CSC_COEFF4,RGB To YCbCr 4:2:2 CSC Coefficient 4 Register" hexmask.long.word 0x00 16.--25. 1. " C8 ,Two's complement blue multiplier coefficient for Cr" hexmask.long.word 0x00 0.--9. 1. " C7 ,Two's complement green multiplier coefficient for Cr" group.long 0x160++0x03 line.long 0x00 "CSC_OFFSET,RGB To YCbCr 4:2:2 CSC Offset Register" hexmask.long.word 0x00 16.--24. 0x01 " CBCR_OFFSET ,Two's complement offset for the Cb and Cr components" hexmask.long.word 0x00 0.--8. 0x01 " Y_OFFSET ,Two's complement offset for the Y component" group.long 0x170++0x03 line.long 0x00 "CSC_LIMIT,RGB To YCbCr 4:2:2 CSC Limit Register" hexmask.long.byte 0x00 24.--31. 1. " CBCR_MIN ,Lower limit of Cb and Cr after RGB to 4:2:2 YCbCr conversion" hexmask.long.byte 0x00 16.--23. 1. " CBCR_MAX ,Upper limit of Cb and Cr after RGB to 4:2:2 YCbCr conversion" newline hexmask.long.byte 0x00 8.--15. 1. " Y_MIN ,Lower limit of Y after RGB to 4:2:2 YCbCr conversion" hexmask.long.byte 0x00 0.--7. 1. " Y_MAX ,Upper limit of Y after RGB to 4:2:2 YCbCr conversion" group.long 0x180++0x03 line.long 0x00 "DATA,LCD Interface Data Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_THREE ,Byte 3 (most significant byte) of data written to LCDIF" hexmask.long.byte 0x00 16.--23. 1. " DATA_TWO ,Byte 2 of data written to LCDIF" newline hexmask.long.byte 0x00 8.--15. 1. " DATA_ONE ,Byte 1 of data written to LCDIF" hexmask.long.byte 0x00 0.--7. 1. " DATA_ZERO ,Byte 0 (least significant byte) of data written to LCDIF" group.long 0x190++0x03 line.long 0x00 "BM_ERROR_STAT,Bus Master Error Status Register" group.long 0x1A0++0x03 line.long 0x00 "CRC_STAT,CRC Status Register" rgroup.long 0x1B0++0x03 line.long 0x00 "STAT,LCD Interface Status Register" bitfld.long 0x00 31. " PRESENT ,LCDIF present on this product" "Not present,Present" bitfld.long 0x00 29. " LFIFO_FULL ,Read only view of the signals that indicates LCD LFIFO is full" "Not full,Full" newline bitfld.long 0x00 28. " LFIFO_EMPTY ,Read only view of the signals that indicates LCD LFIFO is empty" "Not empty,Empty" bitfld.long 0x00 27. " TXFIFO_FULL ,Read only view of the signals that indicates LCD TXFIFO is full" "Not full,Full" newline bitfld.long 0x00 26. " TXFIFO_EMPTY ,Read only view of the signals that indicates LCD TXFIFO is empty" "Not empty,Empty" bitfld.long 0x00 25. " BUSY ,Read only view of the input busy signal from the external LCD controller" "Not busy,Busy" newline bitfld.long 0x00 24. " DVI_CURRENT_FIELD ,Read only view of the current field being transmitted" "Field 1,Field 2" hexmask.long.word 0x00 0.--8. 1. " LFIFO_COUNT ,Read only view of the current count in Latency buffer (LFIFO)" group.long 0x200++0x03 line.long 0x00 "THRES,LCDIF Threshold Register" hexmask.long.word 0x00 16.--24. 1. " FASTCLOCK ,When the number of pixels in the input pixel FIFO is LESS than this value the fast clock control output will be raised" hexmask.long.word 0x00 0.--8. 1. " PANIC ,When the number of pixels in the input pixel FIFO is less than this value the internal panic control output will be raised" group.long 0x210++0x03 line.long 0x00 "AS_CTRL,LCDIF AS Buffer Control Register" bitfld.long 0x00 31. " CSI_VSYNC_ENABLE ,Sync mode with CSI input enable" "Disabled,Enabled" bitfld.long 0x00 30. " CSI_VSYNC_POL ,Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period" "Active low,Active high" newline bitfld.long 0x00 29. " CSI_VSYNC_MODE ,VSYNC generate mode" "Internal sync,External sync" bitfld.long 0x00 28. " CSI_SYNC_ON_IRQ_EN ,Enable an interrupt when LCDIF lock with CSI vsync input" "Disabled,Enabled" newline bitfld.long 0x00 27. " CSI_SYNC_ON_IRQ ,VSYNC generate mode" "Internal sync,External sync" bitfld.long 0x00 23. " PS_DISABLE ,Disable PS buffer data" "No,Yes" newline bitfld.long 0x00 21.--22. " INPUT_DATA_SWIZZLE ,This field specifies how to swap the bytes either in the HW_LCDIF_DATA register or those fetched by the AXI master part of LCDIF" "Little endian,Big endian,Half-words,Bytes within half-word" bitfld.long 0x00 20. " ALPHA_INVERT ,Alpha value invert" "Not inverted,Inverted" newline bitfld.long 0x00 16.--19. " ROP ,Indicates a raster operation to perform when enabled" "MASKAS,MASKNOTAS,MASKASNOT,MERGEAS,MERGENOTAS,MERGEASNOT,NOTCOPYAS,NOT,NOTMASKAS,NOTMERGEAS,XORAS,NOTXORAS,?..." hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE values are programmed in REG_AS_CTRL[ALPHA_CTRL]" newline bitfld.long 0x00 4.--7. " FORMAT ,Indicates the input buffer format for AS" "ARGB8888,,,,RGB888,,,,ARGB1555,ARGB4444,,,RGB555,RGB444,RGB565,?..." bitfld.long 0x00 3. " ENABLE_COLORKEY ,Colorkey functionality enable for alpha surface" "Disabled,Enabled" newline bitfld.long 0x00 1.--2. " ALPHA_CTRL ,Alpha value construction for this alpha surface" "Embedded,Override,Multiply,ROPs" bitfld.long 0x00 0. " AS_ENABLE ,Fetch AS buffer data in bus master mode and combine it with another buffer" "Disabled,Enabled" group.long 0x220++0x03 line.long 0x00 "AS_BUF,Alpha Surface Buffer Pointer Register" group.long 0x230++0x03 line.long 0x00 "AS_NEXT_BUF,AS_NEXT_BUF Register" group.long 0x240++0x03 line.long 0x00 "AS_CLRKEYLOW,LCDIF Overlay Color Key Low Register" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,Low range of RGB color key applied to AS buffer" group.long 0x250++0x03 line.long 0x00 "AS_CLRKEYHIGH,LCDIF Overlay Color Key High Register" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,High range of RGB color key applied to AS buffer" group.long 0x260++0x03 line.long 0x00 "SYNC_DELAY,LCD Working In Sync Mode With CSI For VSYNC Delay Register" hexmask.long.word 0x00 16.--31. 1. " V_COUNT_DELAY ,LCDIF VSYNC delayed counter for CSI_VSYNC" hexmask.long.word 0x00 0.--15. 1. " H_COUNT_DELAY ,LCDIF VSYNC delayed counter for CSI_VSYNC" width 0x0B tree.end tree.open "LPI2C (Low Power Inter-Integrated Circuit)" tree "LPI2C0" base ad:0x5A800000 width 8. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number" line.long 0x04 "PARAM,Parameter Register" bitfld.long 0x04 8.--11. " MRXFIFO ,Master receive FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x04 0.--3. " MTXFIFO ,Master transmit FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" group.long 0x10++0x13 line.long 0x00 "MCR,Master Control Register" bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset" bitfld.long 0x00 3. " DBGEN ,Debug enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " MEN ,Master enable" "Disabled,Enabled" line.long 0x04 "MSR,Master Status Register" rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x04 24. " MBF ,Master busy flag" "Idle,Busy" eventfld.long 0x04 14. " DMF ,Data match flag" "Not received,Received" eventfld.long 0x04 13. " PLTF ,Pin low timeout flag" "Not occurred/disabled,Occurred" newline eventfld.long 0x04 12. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x04 11. " ALF ,Arbitration lost flag" "Not lost,Lost" eventfld.long 0x04 10. " NDF ,NACK detect flag" "Not detected,Detected" eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected" newline eventfld.long 0x04 8. " EPF ,End packet flag" "Not generated/Repeated,Generated/Repeated" rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "MIER,Master Interrupt Enable Register" bitfld.long 0x08 14. " DMIE ,Data match interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " PLTIE ,Pin low timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " FEIE ,FIFO error interrupt disable" "No,Yes" newline bitfld.long 0x08 11. " ALIE ,Arbitration lost interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " NDIE ,NACK detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " EPIE ,End packet interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "MDER,Master DMA Enable Register" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" line.long 0x10 "MCFGR0,Master Configuration Register 0" bitfld.long 0x10 9. " RDMO ,Receive data match only" "Stored,Discarded" bitfld.long 0x10 8. " CIRFIFO ,Circular FIFO enable" "Disabled,Enabled" bitfld.long 0x10 2. " HRSEL ,Host request select" "HREQ pin,Input trigger" newline bitfld.long 0x10 1. " HRPOL ,Host request polarity" "Active low,Active high" bitfld.long 0x10 0. " HREN ,Host request enable" "Disabled,Enabled" newline if (((per.l(ad:0x5A800000+0x10))&0x01)==0x01) rgroup.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Disabled,,1st word = MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "SCL,SCL or SDA" newline bitfld.long 0x00 9. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "No effect,Enabled" bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" else group.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Disabled,,1st word = MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "On SCL low too long,On SCL or SDA low too long" newline bitfld.long 0x00 9. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "No effect,Enabled" bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" endif newline if ((((per.l(ad:0x5A800000+0x10))&0x01)==0x00)||(((per.l(ad:0x5A800000+0x14))&0x1000000)==0x00)) group.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" else rgroup.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" endif if (((per.l(ad:0x5A800000+0x10))&0x01)==0x01) rgroup.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x58++0x03 line.long 0x00 "MFCR,Master FIFO Control Register" bitfld.long 0x00 16.--17. " RXWATER ,Receive FIFO watermark" "0,1,2,3" bitfld.long 0x00 0.--1. " TXWATER ,Transmit FIFO watermark" "0,1,2,3" rgroup.long 0x5C++0x03 line.long 0x00 "MFSR,Master FIFO Status Register" bitfld.long 0x00 16.--18. " RXCOUNT ,Receive FIFO count" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " TXCOUNT ,Transmit FIFO count" "0,1,2,3,4,5,6,7" newline wgroup.long 0x60++0x03 line.long 0x00 "MTDR,Master Transmit Data Register" bitfld.long 0x00 8.--10. " CMD ,Command data" "Transmit,Receive,Generate STOP,Receive and discard,START and transmit,START and transmit (NACK returned),START and transmit (high speed mode),START and transmit high speed mode (NACK returned)" newline hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data" newline hgroup.long 0x70++0x03 hide.long 0x00 "MRDR,Master Receive Data Register" in newline group.long 0x110++0x0F line.long 0x00 "SCR,Slave Control Register" bitfld.long 0x00 9. " RRF ,Receive FIFO reset" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Transmit FIFO reset" "No effect,Reset" bitfld.long 0x00 5. " FILTDZ ,Filter doze enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " FILTEN ,Filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " SEN ,Slave enable" "Disabled,Enabled" line.long 0x04 "SSR,Slave Status Register" rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x04 24. " SBF ,Slave busy flag" "Idle,Busy" rbitfld.long 0x04 15. " SARF ,SMBus alert response flag" "Not detected,Detected" rbitfld.long 0x04 14. " GCF ,General call flag" "Not detected,Detected" newline rbitfld.long 0x04 13. " AM1F ,Address match 1 flag" "Not matched,Matched" rbitfld.long 0x04 12. " AM0F ,Address match 0 flag" "Not matched,Matched" eventfld.long 0x04 11. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x04 10. " BEF ,Bit error flag" "No error,Error" newline eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected" eventfld.long 0x04 8. " RSF ,Repeated start flag" "Not detected,Detected" rbitfld.long 0x04 3. " TAF ,Transmit ACK flag" "Not required,Required" rbitfld.long 0x04 2. " AVF ,Address valid flag" "Invalid,Valid" newline rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "SIER,Slave Interrupt Enable Register" bitfld.long 0x08 15. " SARIE ,SMBus alert response interrupt enable" "Disabled,Enabled" bitfld.long 0x08 14. " GCIE ,General call interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " AM1F ,Address match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " AM0IE ,Address match 0 interrupt disable" "No,Yes" newline bitfld.long 0x08 11. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " BEIE ,Bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 8. " RSIE ,Repeated start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " TAIE ,Transmit ACK interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " AVIE ,Address valid interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "SDER,Slave DMA Enable Register" bitfld.long 0x0C 2. " AVDE ,Address valid DMA enable" "Disabled,Enabled" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" newline if (((per.l(ad:0x5A800000+0x110))&0x01)==0x01) rgroup.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration match" "0 (7-bit),0 (10-bit),0 (7-bit) / 1 (7-bit),0 (10-bit) / 1 (10-bit),0 (7-bit) / 1 (10-bit),0 (10-bit) / 1 (7-bit),From 0 (7-bit) to 1 (7-bit),From 0 (10-bit) to 1 (10-bit)" bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" bitfld.long 0x00 12. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return data / clear RDF,Return address / clear AVF" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer,On TDR empty" bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration match" "0 (7-bit),0 (10-bit),0 (7-bit) / 1 (7-bit),0 (10-bit) / 1 (10-bit),0 (7-bit) / 1 (10-bit),0 (10-bit) / 1 (7-bit),From 0 (7-bit) to 1 (7-bit),From 0 (10-bit) to 1 (10-bit)" bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" bitfld.long 0x00 12. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return data / clear RDF,Return address / clear AVF" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer,On TDR empty" bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline if (((per.l(ad:0x5A800000+0x110))&0x01)==0x01) rgroup.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" else group.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" endif rgroup.long 0x150++0x03 line.long 0x00 "SASR,Slave Address Status Register" bitfld.long 0x00 14. " ANV ,Address invalid" "No,Yes" hexmask.long.word 0x00 0.--10. 0x01 " RADDR ,Received address" if (((per.l(ad:0x5A800000+0x124))&0x08)==0x08) group.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,NACK transmit" "ACK,NACK" else rgroup.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,NACK transmit" "ACK,NACK" endif wgroup.long 0x160++0x03 line.long 0x00 "STDR,Slave Transmit Data Register" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data" rgroup.long 0x170++0x03 line.long 0x00 "SRDR,Slave Receive Data Register" bitfld.long 0x00 15. " SOF ,Start of frame" "Not the first data word,First data word" bitfld.long 0x00 14. " RXEMPTY ,RX empty" "Not empty,Empty" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data receive" width 0x0B tree.end tree "LPI2C1" base ad:0x5A810000 width 8. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number" line.long 0x04 "PARAM,Parameter Register" bitfld.long 0x04 8.--11. " MRXFIFO ,Master receive FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x04 0.--3. " MTXFIFO ,Master transmit FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" group.long 0x10++0x13 line.long 0x00 "MCR,Master Control Register" bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset" bitfld.long 0x00 3. " DBGEN ,Debug enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " MEN ,Master enable" "Disabled,Enabled" line.long 0x04 "MSR,Master Status Register" rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x04 24. " MBF ,Master busy flag" "Idle,Busy" eventfld.long 0x04 14. " DMF ,Data match flag" "Not received,Received" eventfld.long 0x04 13. " PLTF ,Pin low timeout flag" "Not occurred/disabled,Occurred" newline eventfld.long 0x04 12. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x04 11. " ALF ,Arbitration lost flag" "Not lost,Lost" eventfld.long 0x04 10. " NDF ,NACK detect flag" "Not detected,Detected" eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected" newline eventfld.long 0x04 8. " EPF ,End packet flag" "Not generated/Repeated,Generated/Repeated" rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "MIER,Master Interrupt Enable Register" bitfld.long 0x08 14. " DMIE ,Data match interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " PLTIE ,Pin low timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " FEIE ,FIFO error interrupt disable" "No,Yes" newline bitfld.long 0x08 11. " ALIE ,Arbitration lost interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " NDIE ,NACK detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " EPIE ,End packet interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "MDER,Master DMA Enable Register" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" line.long 0x10 "MCFGR0,Master Configuration Register 0" bitfld.long 0x10 9. " RDMO ,Receive data match only" "Stored,Discarded" bitfld.long 0x10 8. " CIRFIFO ,Circular FIFO enable" "Disabled,Enabled" bitfld.long 0x10 2. " HRSEL ,Host request select" "HREQ pin,Input trigger" newline bitfld.long 0x10 1. " HRPOL ,Host request polarity" "Active low,Active high" bitfld.long 0x10 0. " HREN ,Host request enable" "Disabled,Enabled" newline if (((per.l(ad:0x5A810000+0x10))&0x01)==0x01) rgroup.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Disabled,,1st word = MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "SCL,SCL or SDA" newline bitfld.long 0x00 9. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "No effect,Enabled" bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" else group.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Disabled,,1st word = MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "On SCL low too long,On SCL or SDA low too long" newline bitfld.long 0x00 9. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "No effect,Enabled" bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" endif newline if ((((per.l(ad:0x5A810000+0x10))&0x01)==0x00)||(((per.l(ad:0x5A810000+0x14))&0x1000000)==0x00)) group.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" else rgroup.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" endif if (((per.l(ad:0x5A810000+0x10))&0x01)==0x01) rgroup.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x58++0x03 line.long 0x00 "MFCR,Master FIFO Control Register" bitfld.long 0x00 16.--17. " RXWATER ,Receive FIFO watermark" "0,1,2,3" bitfld.long 0x00 0.--1. " TXWATER ,Transmit FIFO watermark" "0,1,2,3" rgroup.long 0x5C++0x03 line.long 0x00 "MFSR,Master FIFO Status Register" bitfld.long 0x00 16.--18. " RXCOUNT ,Receive FIFO count" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " TXCOUNT ,Transmit FIFO count" "0,1,2,3,4,5,6,7" newline wgroup.long 0x60++0x03 line.long 0x00 "MTDR,Master Transmit Data Register" bitfld.long 0x00 8.--10. " CMD ,Command data" "Transmit,Receive,Generate STOP,Receive and discard,START and transmit,START and transmit (NACK returned),START and transmit (high speed mode),START and transmit high speed mode (NACK returned)" newline hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data" newline hgroup.long 0x70++0x03 hide.long 0x00 "MRDR,Master Receive Data Register" in newline group.long 0x110++0x0F line.long 0x00 "SCR,Slave Control Register" bitfld.long 0x00 9. " RRF ,Receive FIFO reset" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Transmit FIFO reset" "No effect,Reset" bitfld.long 0x00 5. " FILTDZ ,Filter doze enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " FILTEN ,Filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " SEN ,Slave enable" "Disabled,Enabled" line.long 0x04 "SSR,Slave Status Register" rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x04 24. " SBF ,Slave busy flag" "Idle,Busy" rbitfld.long 0x04 15. " SARF ,SMBus alert response flag" "Not detected,Detected" rbitfld.long 0x04 14. " GCF ,General call flag" "Not detected,Detected" newline rbitfld.long 0x04 13. " AM1F ,Address match 1 flag" "Not matched,Matched" rbitfld.long 0x04 12. " AM0F ,Address match 0 flag" "Not matched,Matched" eventfld.long 0x04 11. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x04 10. " BEF ,Bit error flag" "No error,Error" newline eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected" eventfld.long 0x04 8. " RSF ,Repeated start flag" "Not detected,Detected" rbitfld.long 0x04 3. " TAF ,Transmit ACK flag" "Not required,Required" rbitfld.long 0x04 2. " AVF ,Address valid flag" "Invalid,Valid" newline rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "SIER,Slave Interrupt Enable Register" bitfld.long 0x08 15. " SARIE ,SMBus alert response interrupt enable" "Disabled,Enabled" bitfld.long 0x08 14. " GCIE ,General call interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " AM1F ,Address match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " AM0IE ,Address match 0 interrupt disable" "No,Yes" newline bitfld.long 0x08 11. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " BEIE ,Bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 8. " RSIE ,Repeated start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " TAIE ,Transmit ACK interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " AVIE ,Address valid interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "SDER,Slave DMA Enable Register" bitfld.long 0x0C 2. " AVDE ,Address valid DMA enable" "Disabled,Enabled" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" newline if (((per.l(ad:0x5A810000+0x110))&0x01)==0x01) rgroup.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration match" "0 (7-bit),0 (10-bit),0 (7-bit) / 1 (7-bit),0 (10-bit) / 1 (10-bit),0 (7-bit) / 1 (10-bit),0 (10-bit) / 1 (7-bit),From 0 (7-bit) to 1 (7-bit),From 0 (10-bit) to 1 (10-bit)" bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" bitfld.long 0x00 12. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return data / clear RDF,Return address / clear AVF" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer,On TDR empty" bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration match" "0 (7-bit),0 (10-bit),0 (7-bit) / 1 (7-bit),0 (10-bit) / 1 (10-bit),0 (7-bit) / 1 (10-bit),0 (10-bit) / 1 (7-bit),From 0 (7-bit) to 1 (7-bit),From 0 (10-bit) to 1 (10-bit)" bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" bitfld.long 0x00 12. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return data / clear RDF,Return address / clear AVF" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer,On TDR empty" bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline if (((per.l(ad:0x5A810000+0x110))&0x01)==0x01) rgroup.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" else group.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" endif rgroup.long 0x150++0x03 line.long 0x00 "SASR,Slave Address Status Register" bitfld.long 0x00 14. " ANV ,Address invalid" "No,Yes" hexmask.long.word 0x00 0.--10. 0x01 " RADDR ,Received address" if (((per.l(ad:0x5A810000+0x124))&0x08)==0x08) group.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,NACK transmit" "ACK,NACK" else rgroup.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,NACK transmit" "ACK,NACK" endif wgroup.long 0x160++0x03 line.long 0x00 "STDR,Slave Transmit Data Register" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data" rgroup.long 0x170++0x03 line.long 0x00 "SRDR,Slave Receive Data Register" bitfld.long 0x00 15. " SOF ,Start of frame" "Not the first data word,First data word" bitfld.long 0x00 14. " RXEMPTY ,RX empty" "Not empty,Empty" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data receive" width 0x0B tree.end tree "LPI2C2" base ad:0x5A820000 width 8. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number" line.long 0x04 "PARAM,Parameter Register" bitfld.long 0x04 8.--11. " MRXFIFO ,Master receive FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x04 0.--3. " MTXFIFO ,Master transmit FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" group.long 0x10++0x13 line.long 0x00 "MCR,Master Control Register" bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset" bitfld.long 0x00 3. " DBGEN ,Debug enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " MEN ,Master enable" "Disabled,Enabled" line.long 0x04 "MSR,Master Status Register" rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x04 24. " MBF ,Master busy flag" "Idle,Busy" eventfld.long 0x04 14. " DMF ,Data match flag" "Not received,Received" eventfld.long 0x04 13. " PLTF ,Pin low timeout flag" "Not occurred/disabled,Occurred" newline eventfld.long 0x04 12. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x04 11. " ALF ,Arbitration lost flag" "Not lost,Lost" eventfld.long 0x04 10. " NDF ,NACK detect flag" "Not detected,Detected" eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected" newline eventfld.long 0x04 8. " EPF ,End packet flag" "Not generated/Repeated,Generated/Repeated" rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "MIER,Master Interrupt Enable Register" bitfld.long 0x08 14. " DMIE ,Data match interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " PLTIE ,Pin low timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " FEIE ,FIFO error interrupt disable" "No,Yes" newline bitfld.long 0x08 11. " ALIE ,Arbitration lost interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " NDIE ,NACK detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " EPIE ,End packet interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "MDER,Master DMA Enable Register" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" line.long 0x10 "MCFGR0,Master Configuration Register 0" bitfld.long 0x10 9. " RDMO ,Receive data match only" "Stored,Discarded" bitfld.long 0x10 8. " CIRFIFO ,Circular FIFO enable" "Disabled,Enabled" bitfld.long 0x10 2. " HRSEL ,Host request select" "HREQ pin,Input trigger" newline bitfld.long 0x10 1. " HRPOL ,Host request polarity" "Active low,Active high" bitfld.long 0x10 0. " HREN ,Host request enable" "Disabled,Enabled" newline if (((per.l(ad:0x5A820000+0x10))&0x01)==0x01) rgroup.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Disabled,,1st word = MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "SCL,SCL or SDA" newline bitfld.long 0x00 9. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "No effect,Enabled" bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" else group.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Disabled,,1st word = MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "On SCL low too long,On SCL or SDA low too long" newline bitfld.long 0x00 9. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "No effect,Enabled" bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" endif newline if ((((per.l(ad:0x5A820000+0x10))&0x01)==0x00)||(((per.l(ad:0x5A820000+0x14))&0x1000000)==0x00)) group.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" else rgroup.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" endif if (((per.l(ad:0x5A820000+0x10))&0x01)==0x01) rgroup.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x58++0x03 line.long 0x00 "MFCR,Master FIFO Control Register" bitfld.long 0x00 16.--17. " RXWATER ,Receive FIFO watermark" "0,1,2,3" bitfld.long 0x00 0.--1. " TXWATER ,Transmit FIFO watermark" "0,1,2,3" rgroup.long 0x5C++0x03 line.long 0x00 "MFSR,Master FIFO Status Register" bitfld.long 0x00 16.--18. " RXCOUNT ,Receive FIFO count" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " TXCOUNT ,Transmit FIFO count" "0,1,2,3,4,5,6,7" newline wgroup.long 0x60++0x03 line.long 0x00 "MTDR,Master Transmit Data Register" bitfld.long 0x00 8.--10. " CMD ,Command data" "Transmit,Receive,Generate STOP,Receive and discard,START and transmit,START and transmit (NACK returned),START and transmit (high speed mode),START and transmit high speed mode (NACK returned)" newline hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data" newline hgroup.long 0x70++0x03 hide.long 0x00 "MRDR,Master Receive Data Register" in newline group.long 0x110++0x0F line.long 0x00 "SCR,Slave Control Register" bitfld.long 0x00 9. " RRF ,Receive FIFO reset" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Transmit FIFO reset" "No effect,Reset" bitfld.long 0x00 5. " FILTDZ ,Filter doze enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " FILTEN ,Filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " SEN ,Slave enable" "Disabled,Enabled" line.long 0x04 "SSR,Slave Status Register" rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x04 24. " SBF ,Slave busy flag" "Idle,Busy" rbitfld.long 0x04 15. " SARF ,SMBus alert response flag" "Not detected,Detected" rbitfld.long 0x04 14. " GCF ,General call flag" "Not detected,Detected" newline rbitfld.long 0x04 13. " AM1F ,Address match 1 flag" "Not matched,Matched" rbitfld.long 0x04 12. " AM0F ,Address match 0 flag" "Not matched,Matched" eventfld.long 0x04 11. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x04 10. " BEF ,Bit error flag" "No error,Error" newline eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected" eventfld.long 0x04 8. " RSF ,Repeated start flag" "Not detected,Detected" rbitfld.long 0x04 3. " TAF ,Transmit ACK flag" "Not required,Required" rbitfld.long 0x04 2. " AVF ,Address valid flag" "Invalid,Valid" newline rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "SIER,Slave Interrupt Enable Register" bitfld.long 0x08 15. " SARIE ,SMBus alert response interrupt enable" "Disabled,Enabled" bitfld.long 0x08 14. " GCIE ,General call interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " AM1F ,Address match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " AM0IE ,Address match 0 interrupt disable" "No,Yes" newline bitfld.long 0x08 11. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " BEIE ,Bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 8. " RSIE ,Repeated start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " TAIE ,Transmit ACK interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " AVIE ,Address valid interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "SDER,Slave DMA Enable Register" bitfld.long 0x0C 2. " AVDE ,Address valid DMA enable" "Disabled,Enabled" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" newline if (((per.l(ad:0x5A820000+0x110))&0x01)==0x01) rgroup.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration match" "0 (7-bit),0 (10-bit),0 (7-bit) / 1 (7-bit),0 (10-bit) / 1 (10-bit),0 (7-bit) / 1 (10-bit),0 (10-bit) / 1 (7-bit),From 0 (7-bit) to 1 (7-bit),From 0 (10-bit) to 1 (10-bit)" bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" bitfld.long 0x00 12. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return data / clear RDF,Return address / clear AVF" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer,On TDR empty" bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration match" "0 (7-bit),0 (10-bit),0 (7-bit) / 1 (7-bit),0 (10-bit) / 1 (10-bit),0 (7-bit) / 1 (10-bit),0 (10-bit) / 1 (7-bit),From 0 (7-bit) to 1 (7-bit),From 0 (10-bit) to 1 (10-bit)" bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" bitfld.long 0x00 12. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return data / clear RDF,Return address / clear AVF" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer,On TDR empty" bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline if (((per.l(ad:0x5A820000+0x110))&0x01)==0x01) rgroup.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" else group.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" endif rgroup.long 0x150++0x03 line.long 0x00 "SASR,Slave Address Status Register" bitfld.long 0x00 14. " ANV ,Address invalid" "No,Yes" hexmask.long.word 0x00 0.--10. 0x01 " RADDR ,Received address" if (((per.l(ad:0x5A820000+0x124))&0x08)==0x08) group.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,NACK transmit" "ACK,NACK" else rgroup.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,NACK transmit" "ACK,NACK" endif wgroup.long 0x160++0x03 line.long 0x00 "STDR,Slave Transmit Data Register" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data" rgroup.long 0x170++0x03 line.long 0x00 "SRDR,Slave Receive Data Register" bitfld.long 0x00 15. " SOF ,Start of frame" "Not the first data word,First data word" bitfld.long 0x00 14. " RXEMPTY ,RX empty" "Not empty,Empty" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data receive" width 0x0B tree.end tree "LPI2C3" base ad:0x5A830000 width 8. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number" line.long 0x04 "PARAM,Parameter Register" bitfld.long 0x04 8.--11. " MRXFIFO ,Master receive FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x04 0.--3. " MTXFIFO ,Master transmit FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" group.long 0x10++0x13 line.long 0x00 "MCR,Master Control Register" bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset" bitfld.long 0x00 3. " DBGEN ,Debug enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " MEN ,Master enable" "Disabled,Enabled" line.long 0x04 "MSR,Master Status Register" rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x04 24. " MBF ,Master busy flag" "Idle,Busy" eventfld.long 0x04 14. " DMF ,Data match flag" "Not received,Received" eventfld.long 0x04 13. " PLTF ,Pin low timeout flag" "Not occurred/disabled,Occurred" newline eventfld.long 0x04 12. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x04 11. " ALF ,Arbitration lost flag" "Not lost,Lost" eventfld.long 0x04 10. " NDF ,NACK detect flag" "Not detected,Detected" eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected" newline eventfld.long 0x04 8. " EPF ,End packet flag" "Not generated/Repeated,Generated/Repeated" rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "MIER,Master Interrupt Enable Register" bitfld.long 0x08 14. " DMIE ,Data match interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " PLTIE ,Pin low timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " FEIE ,FIFO error interrupt disable" "No,Yes" newline bitfld.long 0x08 11. " ALIE ,Arbitration lost interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " NDIE ,NACK detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 8. " EPIE ,End packet interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "MDER,Master DMA Enable Register" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" line.long 0x10 "MCFGR0,Master Configuration Register 0" bitfld.long 0x10 9. " RDMO ,Receive data match only" "Stored,Discarded" bitfld.long 0x10 8. " CIRFIFO ,Circular FIFO enable" "Disabled,Enabled" bitfld.long 0x10 2. " HRSEL ,Host request select" "HREQ pin,Input trigger" newline bitfld.long 0x10 1. " HRPOL ,Host request polarity" "Active low,Active high" bitfld.long 0x10 0. " HREN ,Host request enable" "Disabled,Enabled" newline if (((per.l(ad:0x5A830000+0x10))&0x01)==0x01) rgroup.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Disabled,,1st word = MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "SCL,SCL or SDA" newline bitfld.long 0x00 9. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "No effect,Enabled" bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" else group.long 0x24++0x0B line.long 0x00 "MCFGR1,Master Configuration Register 1" bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Disabled,,1st word = MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "On SCL low too long,On SCL or SDA low too long" newline bitfld.long 0x00 9. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "No effect,Enabled" bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "MCFGR2,Master Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout" line.long 0x08 "MCFGR3,Master Configuration Register 3" hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout" endif newline if ((((per.l(ad:0x5A830000+0x10))&0x01)==0x00)||(((per.l(ad:0x5A830000+0x14))&0x1000000)==0x00)) group.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" else rgroup.long 0x40++0x03 line.long 0x00 "MDMR,Master Data Match Register" hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value" hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value" endif if (((per.l(ad:0x5A830000+0x10))&0x01)==0x01) rgroup.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x48++0x03 line.long 0x00 "MCCR0,Master Clock Configuration Register 0" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x50++0x03 line.long 0x00 "MCCR1,Master Clock Configuration Register 1" bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " SETHOLD ,Hold delay setup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x58++0x03 line.long 0x00 "MFCR,Master FIFO Control Register" bitfld.long 0x00 16.--17. " RXWATER ,Receive FIFO watermark" "0,1,2,3" bitfld.long 0x00 0.--1. " TXWATER ,Transmit FIFO watermark" "0,1,2,3" rgroup.long 0x5C++0x03 line.long 0x00 "MFSR,Master FIFO Status Register" bitfld.long 0x00 16.--18. " RXCOUNT ,Receive FIFO count" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " TXCOUNT ,Transmit FIFO count" "0,1,2,3,4,5,6,7" newline wgroup.long 0x60++0x03 line.long 0x00 "MTDR,Master Transmit Data Register" bitfld.long 0x00 8.--10. " CMD ,Command data" "Transmit,Receive,Generate STOP,Receive and discard,START and transmit,START and transmit (NACK returned),START and transmit (high speed mode),START and transmit high speed mode (NACK returned)" newline hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data" newline hgroup.long 0x70++0x03 hide.long 0x00 "MRDR,Master Receive Data Register" in newline group.long 0x110++0x0F line.long 0x00 "SCR,Slave Control Register" bitfld.long 0x00 9. " RRF ,Receive FIFO reset" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Transmit FIFO reset" "No effect,Reset" bitfld.long 0x00 5. " FILTDZ ,Filter doze enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " FILTEN ,Filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " SEN ,Slave enable" "Disabled,Enabled" line.long 0x04 "SSR,Slave Status Register" rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy" rbitfld.long 0x04 24. " SBF ,Slave busy flag" "Idle,Busy" rbitfld.long 0x04 15. " SARF ,SMBus alert response flag" "Not detected,Detected" rbitfld.long 0x04 14. " GCF ,General call flag" "Not detected,Detected" newline rbitfld.long 0x04 13. " AM1F ,Address match 1 flag" "Not matched,Matched" rbitfld.long 0x04 12. " AM0F ,Address match 0 flag" "Not matched,Matched" eventfld.long 0x04 11. " FEF ,FIFO error flag" "No error,Error" eventfld.long 0x04 10. " BEF ,Bit error flag" "No error,Error" newline eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected" eventfld.long 0x04 8. " RSF ,Repeated start flag" "Not detected,Detected" rbitfld.long 0x04 3. " TAF ,Transmit ACK flag" "Not required,Required" rbitfld.long 0x04 2. " AVF ,Address valid flag" "Invalid,Valid" newline rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "SIER,Slave Interrupt Enable Register" bitfld.long 0x08 15. " SARIE ,SMBus alert response interrupt enable" "Disabled,Enabled" bitfld.long 0x08 14. " GCIE ,General call interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " AM1F ,Address match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " AM0IE ,Address match 0 interrupt disable" "No,Yes" newline bitfld.long 0x08 11. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " BEIE ,Bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 8. " RSIE ,Repeated start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " TAIE ,Transmit ACK interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " AVIE ,Address valid interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "SDER,Slave DMA Enable Register" bitfld.long 0x0C 2. " AVDE ,Address valid DMA enable" "Disabled,Enabled" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" newline if (((per.l(ad:0x5A830000+0x110))&0x01)==0x01) rgroup.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration match" "0 (7-bit),0 (10-bit),0 (7-bit) / 1 (7-bit),0 (10-bit) / 1 (10-bit),0 (7-bit) / 1 (10-bit),0 (10-bit) / 1 (7-bit),From 0 (7-bit) to 1 (7-bit),From 0 (10-bit) to 1 (10-bit)" bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" bitfld.long 0x00 12. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return data / clear RDF,Return address / clear AVF" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer,On TDR empty" bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x124++0x07 line.long 0x00 "SCFGR1,Slave Configuration Register 1" bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration match" "0 (7-bit),0 (10-bit),0 (7-bit) / 1 (7-bit),0 (10-bit) / 1 (10-bit),0 (7-bit) / 1 (10-bit),0 (10-bit) / 1 (7-bit),From 0 (7-bit) to 1 (7-bit),From 0 (10-bit) to 1 (10-bit)" bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled" bitfld.long 0x00 12. " IGNACK ,NACK ignore" "Not ignored,Ignored" bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return data / clear RDF,Return address / clear AVF" newline bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer,On TDR empty" bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled" newline bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled" bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled" bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled" line.long 0x04 "SCFGR2,Slave Configuration Register 2" bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline if (((per.l(ad:0x5A830000+0x110))&0x01)==0x01) rgroup.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" else group.long 0x140++0x03 line.long 0x00 "SAMR,Slave Address Match Register" hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value" hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value" endif rgroup.long 0x150++0x03 line.long 0x00 "SASR,Slave Address Status Register" bitfld.long 0x00 14. " ANV ,Address invalid" "No,Yes" hexmask.long.word 0x00 0.--10. 0x01 " RADDR ,Received address" if (((per.l(ad:0x5A830000+0x124))&0x08)==0x08) group.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,NACK transmit" "ACK,NACK" else rgroup.long 0x154++0x03 line.long 0x00 "STAR,Slave Transmit ACK Register" bitfld.long 0x00 0. " TXNACK ,NACK transmit" "ACK,NACK" endif wgroup.long 0x160++0x03 line.long 0x00 "STDR,Slave Transmit Data Register" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data" rgroup.long 0x170++0x03 line.long 0x00 "SRDR,Slave Receive Data Register" bitfld.long 0x00 15. " SOF ,Start of frame" "Not the first data word,First data word" bitfld.long 0x00 14. " RXEMPTY ,RX empty" "Not empty,Empty" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data receive" width 0x0B tree.end tree.end tree.open "LPSPI (Low Power Serial Peripheral Interface)" tree "LPSPI0" base ad:0x5A000000 width 7. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Module identification number" line.long 0x04 "PARAM,Parameter Register" hexmask.long.byte 0x04 8.--15. 1. " RXFIFO ,Receive FIFO size" hexmask.long.byte 0x04 0.--7. 1. " TXFIFO ,Transmit FIFO size" group.long 0x10++0x13 line.long 0x00 "CR,Control Register" bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset" bitfld.long 0x00 3. " DBGEN ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 2. " DOZEN ,Doze mode enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " MEN ,Module enable" "Disabled,Enabled" line.long 0x04 "SR,Status Register" rbitfld.long 0x04 24. " MBF ,Module busy flag" "Idle,Busy" eventfld.long 0x04 13. " DMF ,Data match flag" "Not matched,Matched" eventfld.long 0x04 12. " REF ,Receive error flag" "No error,Error" eventfld.long 0x04 11. " TEF ,Transmit error flag" "No error,Error" newline eventfld.long 0x04 10. " TCF ,Transfer complete flag" "Not completed,Completed" eventfld.long 0x04 9. " FCF ,Frame complete flag" "Not completed,Completed" eventfld.long 0x04 8. " WCF ,Word complete flag" "Not completed,Completed" rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" newline rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "IER,Interrupt Enable Register" bitfld.long 0x08 13. " DMIE ,Data match interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " REIE ,Receive error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 11. " TEIE ,Transmit error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 9. " FCIE ,Frame complete interrupt enable" "Disabled,Enabled" bitfld.long 0x08 8. " WCIE ,Word complete interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "DER,DMA Enable Register" bitfld.long 0x0C 9. " FCDE ,Frame complete DMA enable" "Disabled,Enabled" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" line.long 0x10 "CFGR0,Configuration Register 0" bitfld.long 0x10 9. " RDMO ,Receive data match only" "All data,Match only" bitfld.long 0x10 8. " CIRFIFO ,Circular FIFO enable" "Disabled,Enabled" bitfld.long 0x10 2. " HRSEL ,Host request select" "Pin LPSPI_HREQ,Input trigger" bitfld.long 0x10 1. " HRPOL ,Host request polarity" "Active low,Active high" newline bitfld.long 0x10 0. " HREN ,Host request enable" "Disabled,Enabled" if (((per.l(ad:0x5A000000+0x10))&0x01)==0x01) if (((per.l(ad:0x5A000000+0x24))&0x01)==0x01) rgroup.long 0x24++0x03 line.long 0x00 "CFGR1,Configuration Register 1" bitfld.long 0x00 27. " PCSCFG ,PCS disable" "No,Yes" bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated" bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Disabled,,1st == MATCH0 | MATCH1,Any == MATCH0 | MATCH1,1st == MATCH0 & 2nd == MATCH1,Any = MATCH0 & next = MATCH1,1st & MATCH1 == MATCH0 & MATCH1,Any & MATCH1 == MATCH0 & MATCH1" newline bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high" bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high" bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high" bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high" newline bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled" bitfld.long 0x00 1. " SAMPLE ,Sample point" "SCK edge,Delayed SCK edge" bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode" else rgroup.long 0x24++0x03 line.long 0x00 "CFGR1,Configuration Register 1" bitfld.long 0x00 27. " PCSCFG ,PCS disable" "No,Yes" bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated" bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=match0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" newline bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high" bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high" bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high" bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high" newline bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled" bitfld.long 0x00 2. " AUTOPCS ,Automatic PCS" "Disabled,Enabled" bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode" endif else if (((per.l(ad:0x5A000000+0x24))&0x01)==0x01) group.long 0x24++0x03 line.long 0x00 "CFGR1,Configuration Register 1" bitfld.long 0x00 27. " PCSCFG ,Peripheral chip select configuration" "PCS enabled,PCS disabled" bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated" bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=match0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" newline bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high" bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high" bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high" bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high" newline bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled" bitfld.long 0x00 1. " SAMPLE ,Sample point" "SCK edge,Delayed SCK edge" bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode" else group.long 0x24++0x03 line.long 0x00 "CFGR1,Configuration Register 1" bitfld.long 0x00 27. " PCSCFG ,Peripheral chip select configuration" "PCS enabled,PCS disabled" bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated" bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=match0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" newline bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high" bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high" bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high" bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high" newline bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled" bitfld.long 0x00 2. " AUTOPCS ,Automatic PCS" "Disabled,Enabled" bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode" endif endif group.long 0x30++0x07 line.long 0x00 "DMR0,Data Match Register 0" line.long 0x04 "DMR1,Data Match Register 1" if (((per.l(ad:0x5A000000+0x24))&0x01)==0x01) if (((per.l(ad:0x5A000000+0x10))&0x01)==0x01) group.long 0x40++0x03 line.long 0x00 "CCR,Clock Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay" hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay" hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers" hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider" else rgroup.long 0x40++0x03 line.long 0x00 "CCR,Clock Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay" hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay" hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers" hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider" endif else hgroup.long 0x40++0x03 hide.long 0x00 "CCR,Clock Configuration Register" endif group.long 0x58++0x03 line.long 0x00 "FCR,FIFO Control Register" bitfld.long 0x00 16.--21. " RXWATER ,Receive FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TXWATER ,Transmit FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x5C++0x03 line.long 0x00 "FSR,FIFO Status Register" hexmask.long.byte 0x00 16.--22. 1. " RXCOUNT ,Receive FIFO count" hexmask.long.byte 0x00 0.--6. 1. " TXCOUNT ,Transmit FIFO count" group.long 0x60++0x03 line.long 0x00 "TCR,Transmit Command Register" bitfld.long 0x00 31. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 30. " CPHA ,Clock phase" "Leading capture/following change,Leading change/following capture" bitfld.long 0x00 27.--29. " PRESCALE ,Prescaler value" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.long 0x00 24.--25. " PCS ,Peripheral chip select" "LPSPI_PCS[0],LPSPI_PCS[1],LPSPI_PCS[2],LPSPI_PCS[3]" newline bitfld.long 0x00 23. " LSBF ,LSB first" "MSB first,LSB first" bitfld.long 0x00 22. " BYSW ,Byte swap" "Disabled,Enabled" bitfld.long 0x00 21. " CONT ,Continuous transfer" "Disabled,Enabled" bitfld.long 0x00 20. " CONTC ,Continuing command" "New transfer,Continuing transfer" newline bitfld.long 0x00 19. " RXMSK ,Receive data mask" "Not masked,Masked" bitfld.long 0x00 18. " TXMSK ,Transmit data mask" "Not masked,Masked" bitfld.long 0x00 16.--17. " WIDTH ,Transfer width" "Single bit,Two bit,Four bit,?..." hexmask.long.word 0x00 0.--11. 1. " FRAMESZ ,Frame size" wgroup.long 0x64++0x03 line.long 0x00 "TDR,Transmit Data Register" rgroup.long 0x70++0x03 line.long 0x00 "RSR,Receive Status Register" bitfld.long 0x00 1. " RXEMPTY ,RX FIFO empty" "Not empty,Empty" bitfld.long 0x00 0. " SOF ,Start of frame" "Subsequent data,First data" hgroup.long 0x74++0x03 hide.long 0x00 "RDR,Receive Data Register" in width 0x0B tree.end tree "LPSPI1" base ad:0x5A010000 width 7. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Module identification number" line.long 0x04 "PARAM,Parameter Register" hexmask.long.byte 0x04 8.--15. 1. " RXFIFO ,Receive FIFO size" hexmask.long.byte 0x04 0.--7. 1. " TXFIFO ,Transmit FIFO size" group.long 0x10++0x13 line.long 0x00 "CR,Control Register" bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset" bitfld.long 0x00 3. " DBGEN ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 2. " DOZEN ,Doze mode enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " MEN ,Module enable" "Disabled,Enabled" line.long 0x04 "SR,Status Register" rbitfld.long 0x04 24. " MBF ,Module busy flag" "Idle,Busy" eventfld.long 0x04 13. " DMF ,Data match flag" "Not matched,Matched" eventfld.long 0x04 12. " REF ,Receive error flag" "No error,Error" eventfld.long 0x04 11. " TEF ,Transmit error flag" "No error,Error" newline eventfld.long 0x04 10. " TCF ,Transfer complete flag" "Not completed,Completed" eventfld.long 0x04 9. " FCF ,Frame complete flag" "Not completed,Completed" eventfld.long 0x04 8. " WCF ,Word complete flag" "Not completed,Completed" rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" newline rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "IER,Interrupt Enable Register" bitfld.long 0x08 13. " DMIE ,Data match interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " REIE ,Receive error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 11. " TEIE ,Transmit error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 9. " FCIE ,Frame complete interrupt enable" "Disabled,Enabled" bitfld.long 0x08 8. " WCIE ,Word complete interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "DER,DMA Enable Register" bitfld.long 0x0C 9. " FCDE ,Frame complete DMA enable" "Disabled,Enabled" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" line.long 0x10 "CFGR0,Configuration Register 0" bitfld.long 0x10 9. " RDMO ,Receive data match only" "All data,Match only" bitfld.long 0x10 8. " CIRFIFO ,Circular FIFO enable" "Disabled,Enabled" bitfld.long 0x10 2. " HRSEL ,Host request select" "Pin LPSPI_HREQ,Input trigger" bitfld.long 0x10 1. " HRPOL ,Host request polarity" "Active low,Active high" newline bitfld.long 0x10 0. " HREN ,Host request enable" "Disabled,Enabled" if (((per.l(ad:0x5A010000+0x10))&0x01)==0x01) if (((per.l(ad:0x5A010000+0x24))&0x01)==0x01) rgroup.long 0x24++0x03 line.long 0x00 "CFGR1,Configuration Register 1" bitfld.long 0x00 27. " PCSCFG ,PCS disable" "No,Yes" bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated" bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Disabled,,1st == MATCH0 | MATCH1,Any == MATCH0 | MATCH1,1st == MATCH0 & 2nd == MATCH1,Any = MATCH0 & next = MATCH1,1st & MATCH1 == MATCH0 & MATCH1,Any & MATCH1 == MATCH0 & MATCH1" newline bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high" bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high" bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high" bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high" newline bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled" bitfld.long 0x00 1. " SAMPLE ,Sample point" "SCK edge,Delayed SCK edge" bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode" else rgroup.long 0x24++0x03 line.long 0x00 "CFGR1,Configuration Register 1" bitfld.long 0x00 27. " PCSCFG ,PCS disable" "No,Yes" bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated" bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=match0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" newline bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high" bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high" bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high" bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high" newline bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled" bitfld.long 0x00 2. " AUTOPCS ,Automatic PCS" "Disabled,Enabled" bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode" endif else if (((per.l(ad:0x5A010000+0x24))&0x01)==0x01) group.long 0x24++0x03 line.long 0x00 "CFGR1,Configuration Register 1" bitfld.long 0x00 27. " PCSCFG ,Peripheral chip select configuration" "PCS enabled,PCS disabled" bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated" bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=match0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" newline bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high" bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high" bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high" bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high" newline bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled" bitfld.long 0x00 1. " SAMPLE ,Sample point" "SCK edge,Delayed SCK edge" bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode" else group.long 0x24++0x03 line.long 0x00 "CFGR1,Configuration Register 1" bitfld.long 0x00 27. " PCSCFG ,Peripheral chip select configuration" "PCS enabled,PCS disabled" bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated" bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=match0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" newline bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high" bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high" bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high" bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high" newline bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled" bitfld.long 0x00 2. " AUTOPCS ,Automatic PCS" "Disabled,Enabled" bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode" endif endif group.long 0x30++0x07 line.long 0x00 "DMR0,Data Match Register 0" line.long 0x04 "DMR1,Data Match Register 1" if (((per.l(ad:0x5A010000+0x24))&0x01)==0x01) if (((per.l(ad:0x5A010000+0x10))&0x01)==0x01) group.long 0x40++0x03 line.long 0x00 "CCR,Clock Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay" hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay" hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers" hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider" else rgroup.long 0x40++0x03 line.long 0x00 "CCR,Clock Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay" hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay" hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers" hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider" endif else hgroup.long 0x40++0x03 hide.long 0x00 "CCR,Clock Configuration Register" endif group.long 0x58++0x03 line.long 0x00 "FCR,FIFO Control Register" bitfld.long 0x00 16.--21. " RXWATER ,Receive FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TXWATER ,Transmit FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x5C++0x03 line.long 0x00 "FSR,FIFO Status Register" hexmask.long.byte 0x00 16.--22. 1. " RXCOUNT ,Receive FIFO count" hexmask.long.byte 0x00 0.--6. 1. " TXCOUNT ,Transmit FIFO count" group.long 0x60++0x03 line.long 0x00 "TCR,Transmit Command Register" bitfld.long 0x00 31. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 30. " CPHA ,Clock phase" "Leading capture/following change,Leading change/following capture" bitfld.long 0x00 27.--29. " PRESCALE ,Prescaler value" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.long 0x00 24.--25. " PCS ,Peripheral chip select" "LPSPI_PCS[0],LPSPI_PCS[1],LPSPI_PCS[2],LPSPI_PCS[3]" newline bitfld.long 0x00 23. " LSBF ,LSB first" "MSB first,LSB first" bitfld.long 0x00 22. " BYSW ,Byte swap" "Disabled,Enabled" bitfld.long 0x00 21. " CONT ,Continuous transfer" "Disabled,Enabled" bitfld.long 0x00 20. " CONTC ,Continuing command" "New transfer,Continuing transfer" newline bitfld.long 0x00 19. " RXMSK ,Receive data mask" "Not masked,Masked" bitfld.long 0x00 18. " TXMSK ,Transmit data mask" "Not masked,Masked" bitfld.long 0x00 16.--17. " WIDTH ,Transfer width" "Single bit,Two bit,Four bit,?..." hexmask.long.word 0x00 0.--11. 1. " FRAMESZ ,Frame size" wgroup.long 0x64++0x03 line.long 0x00 "TDR,Transmit Data Register" rgroup.long 0x70++0x03 line.long 0x00 "RSR,Receive Status Register" bitfld.long 0x00 1. " RXEMPTY ,RX FIFO empty" "Not empty,Empty" bitfld.long 0x00 0. " SOF ,Start of frame" "Subsequent data,First data" hgroup.long 0x74++0x03 hide.long 0x00 "RDR,Receive Data Register" in width 0x0B tree.end tree "LPSPI2" base ad:0x5A020000 width 7. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Module identification number" line.long 0x04 "PARAM,Parameter Register" hexmask.long.byte 0x04 8.--15. 1. " RXFIFO ,Receive FIFO size" hexmask.long.byte 0x04 0.--7. 1. " TXFIFO ,Transmit FIFO size" group.long 0x10++0x13 line.long 0x00 "CR,Control Register" bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset" bitfld.long 0x00 3. " DBGEN ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 2. " DOZEN ,Doze mode enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " MEN ,Module enable" "Disabled,Enabled" line.long 0x04 "SR,Status Register" rbitfld.long 0x04 24. " MBF ,Module busy flag" "Idle,Busy" eventfld.long 0x04 13. " DMF ,Data match flag" "Not matched,Matched" eventfld.long 0x04 12. " REF ,Receive error flag" "No error,Error" eventfld.long 0x04 11. " TEF ,Transmit error flag" "No error,Error" newline eventfld.long 0x04 10. " TCF ,Transfer complete flag" "Not completed,Completed" eventfld.long 0x04 9. " FCF ,Frame complete flag" "Not completed,Completed" eventfld.long 0x04 8. " WCF ,Word complete flag" "Not completed,Completed" rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" newline rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "IER,Interrupt Enable Register" bitfld.long 0x08 13. " DMIE ,Data match interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " REIE ,Receive error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 11. " TEIE ,Transmit error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 9. " FCIE ,Frame complete interrupt enable" "Disabled,Enabled" bitfld.long 0x08 8. " WCIE ,Word complete interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "DER,DMA Enable Register" bitfld.long 0x0C 9. " FCDE ,Frame complete DMA enable" "Disabled,Enabled" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" line.long 0x10 "CFGR0,Configuration Register 0" bitfld.long 0x10 9. " RDMO ,Receive data match only" "All data,Match only" bitfld.long 0x10 8. " CIRFIFO ,Circular FIFO enable" "Disabled,Enabled" bitfld.long 0x10 2. " HRSEL ,Host request select" "Pin LPSPI_HREQ,Input trigger" bitfld.long 0x10 1. " HRPOL ,Host request polarity" "Active low,Active high" newline bitfld.long 0x10 0. " HREN ,Host request enable" "Disabled,Enabled" if (((per.l(ad:0x5A020000+0x10))&0x01)==0x01) if (((per.l(ad:0x5A020000+0x24))&0x01)==0x01) rgroup.long 0x24++0x03 line.long 0x00 "CFGR1,Configuration Register 1" bitfld.long 0x00 27. " PCSCFG ,PCS disable" "No,Yes" bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated" bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Disabled,,1st == MATCH0 | MATCH1,Any == MATCH0 | MATCH1,1st == MATCH0 & 2nd == MATCH1,Any = MATCH0 & next = MATCH1,1st & MATCH1 == MATCH0 & MATCH1,Any & MATCH1 == MATCH0 & MATCH1" newline bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high" bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high" bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high" bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high" newline bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled" bitfld.long 0x00 1. " SAMPLE ,Sample point" "SCK edge,Delayed SCK edge" bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode" else rgroup.long 0x24++0x03 line.long 0x00 "CFGR1,Configuration Register 1" bitfld.long 0x00 27. " PCSCFG ,PCS disable" "No,Yes" bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated" bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=match0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" newline bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high" bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high" bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high" bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high" newline bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled" bitfld.long 0x00 2. " AUTOPCS ,Automatic PCS" "Disabled,Enabled" bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode" endif else if (((per.l(ad:0x5A020000+0x24))&0x01)==0x01) group.long 0x24++0x03 line.long 0x00 "CFGR1,Configuration Register 1" bitfld.long 0x00 27. " PCSCFG ,Peripheral chip select configuration" "PCS enabled,PCS disabled" bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated" bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=match0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" newline bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high" bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high" bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high" bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high" newline bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled" bitfld.long 0x00 1. " SAMPLE ,Sample point" "SCK edge,Delayed SCK edge" bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode" else group.long 0x24++0x03 line.long 0x00 "CFGR1,Configuration Register 1" bitfld.long 0x00 27. " PCSCFG ,Peripheral chip select configuration" "PCS enabled,PCS disabled" bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated" bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=match0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" newline bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high" bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high" bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high" bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high" newline bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled" bitfld.long 0x00 2. " AUTOPCS ,Automatic PCS" "Disabled,Enabled" bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode" endif endif group.long 0x30++0x07 line.long 0x00 "DMR0,Data Match Register 0" line.long 0x04 "DMR1,Data Match Register 1" if (((per.l(ad:0x5A020000+0x24))&0x01)==0x01) if (((per.l(ad:0x5A020000+0x10))&0x01)==0x01) group.long 0x40++0x03 line.long 0x00 "CCR,Clock Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay" hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay" hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers" hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider" else rgroup.long 0x40++0x03 line.long 0x00 "CCR,Clock Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay" hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay" hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers" hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider" endif else hgroup.long 0x40++0x03 hide.long 0x00 "CCR,Clock Configuration Register" endif group.long 0x58++0x03 line.long 0x00 "FCR,FIFO Control Register" bitfld.long 0x00 16.--21. " RXWATER ,Receive FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TXWATER ,Transmit FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x5C++0x03 line.long 0x00 "FSR,FIFO Status Register" hexmask.long.byte 0x00 16.--22. 1. " RXCOUNT ,Receive FIFO count" hexmask.long.byte 0x00 0.--6. 1. " TXCOUNT ,Transmit FIFO count" group.long 0x60++0x03 line.long 0x00 "TCR,Transmit Command Register" bitfld.long 0x00 31. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 30. " CPHA ,Clock phase" "Leading capture/following change,Leading change/following capture" bitfld.long 0x00 27.--29. " PRESCALE ,Prescaler value" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.long 0x00 24.--25. " PCS ,Peripheral chip select" "LPSPI_PCS[0],LPSPI_PCS[1],LPSPI_PCS[2],LPSPI_PCS[3]" newline bitfld.long 0x00 23. " LSBF ,LSB first" "MSB first,LSB first" bitfld.long 0x00 22. " BYSW ,Byte swap" "Disabled,Enabled" bitfld.long 0x00 21. " CONT ,Continuous transfer" "Disabled,Enabled" bitfld.long 0x00 20. " CONTC ,Continuing command" "New transfer,Continuing transfer" newline bitfld.long 0x00 19. " RXMSK ,Receive data mask" "Not masked,Masked" bitfld.long 0x00 18. " TXMSK ,Transmit data mask" "Not masked,Masked" bitfld.long 0x00 16.--17. " WIDTH ,Transfer width" "Single bit,Two bit,Four bit,?..." hexmask.long.word 0x00 0.--11. 1. " FRAMESZ ,Frame size" wgroup.long 0x64++0x03 line.long 0x00 "TDR,Transmit Data Register" rgroup.long 0x70++0x03 line.long 0x00 "RSR,Receive Status Register" bitfld.long 0x00 1. " RXEMPTY ,RX FIFO empty" "Not empty,Empty" bitfld.long 0x00 0. " SOF ,Start of frame" "Subsequent data,First data" hgroup.long 0x74++0x03 hide.long 0x00 "RDR,Receive Data Register" in width 0x0B tree.end tree "LPSPI3" base ad:0x5A030000 width 7. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Module identification number" line.long 0x04 "PARAM,Parameter Register" hexmask.long.byte 0x04 8.--15. 1. " RXFIFO ,Receive FIFO size" hexmask.long.byte 0x04 0.--7. 1. " TXFIFO ,Transmit FIFO size" group.long 0x10++0x13 line.long 0x00 "CR,Control Register" bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset" bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset" bitfld.long 0x00 3. " DBGEN ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 2. " DOZEN ,Doze mode enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " MEN ,Module enable" "Disabled,Enabled" line.long 0x04 "SR,Status Register" rbitfld.long 0x04 24. " MBF ,Module busy flag" "Idle,Busy" eventfld.long 0x04 13. " DMF ,Data match flag" "Not matched,Matched" eventfld.long 0x04 12. " REF ,Receive error flag" "No error,Error" eventfld.long 0x04 11. " TEF ,Transmit error flag" "No error,Error" newline eventfld.long 0x04 10. " TCF ,Transfer complete flag" "Not completed,Completed" eventfld.long 0x04 9. " FCF ,Frame complete flag" "Not completed,Completed" eventfld.long 0x04 8. " WCF ,Word complete flag" "Not completed,Completed" rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready" newline rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested" line.long 0x08 "IER,Interrupt Enable Register" bitfld.long 0x08 13. " DMIE ,Data match interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " REIE ,Receive error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 11. " TEIE ,Transmit error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 9. " FCIE ,Frame complete interrupt enable" "Disabled,Enabled" bitfld.long 0x08 8. " WCIE ,Word complete interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled" line.long 0x0C "DER,DMA Enable Register" bitfld.long 0x0C 9. " FCDE ,Frame complete DMA enable" "Disabled,Enabled" bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled" line.long 0x10 "CFGR0,Configuration Register 0" bitfld.long 0x10 9. " RDMO ,Receive data match only" "All data,Match only" bitfld.long 0x10 8. " CIRFIFO ,Circular FIFO enable" "Disabled,Enabled" bitfld.long 0x10 2. " HRSEL ,Host request select" "Pin LPSPI_HREQ,Input trigger" bitfld.long 0x10 1. " HRPOL ,Host request polarity" "Active low,Active high" newline bitfld.long 0x10 0. " HREN ,Host request enable" "Disabled,Enabled" if (((per.l(ad:0x5A030000+0x10))&0x01)==0x01) if (((per.l(ad:0x5A030000+0x24))&0x01)==0x01) rgroup.long 0x24++0x03 line.long 0x00 "CFGR1,Configuration Register 1" bitfld.long 0x00 27. " PCSCFG ,PCS disable" "No,Yes" bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated" bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Disabled,,1st == MATCH0 | MATCH1,Any == MATCH0 | MATCH1,1st == MATCH0 & 2nd == MATCH1,Any = MATCH0 & next = MATCH1,1st & MATCH1 == MATCH0 & MATCH1,Any & MATCH1 == MATCH0 & MATCH1" newline bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high" bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high" bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high" bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high" newline bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled" bitfld.long 0x00 1. " SAMPLE ,Sample point" "SCK edge,Delayed SCK edge" bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode" else rgroup.long 0x24++0x03 line.long 0x00 "CFGR1,Configuration Register 1" bitfld.long 0x00 27. " PCSCFG ,PCS disable" "No,Yes" bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated" bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=match0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" newline bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high" bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high" bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high" bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high" newline bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled" bitfld.long 0x00 2. " AUTOPCS ,Automatic PCS" "Disabled,Enabled" bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode" endif else if (((per.l(ad:0x5A030000+0x24))&0x01)==0x01) group.long 0x24++0x03 line.long 0x00 "CFGR1,Configuration Register 1" bitfld.long 0x00 27. " PCSCFG ,Peripheral chip select configuration" "PCS enabled,PCS disabled" bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated" bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=match0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" newline bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high" bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high" bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high" bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high" newline bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled" bitfld.long 0x00 1. " SAMPLE ,Sample point" "SCK edge,Delayed SCK edge" bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode" else group.long 0x24++0x03 line.long 0x00 "CFGR1,Configuration Register 1" bitfld.long 0x00 27. " PCSCFG ,Peripheral chip select configuration" "PCS enabled,PCS disabled" bitfld.long 0x00 26. " OUTCFG ,Output config" "Retained,Tristated" bitfld.long 0x00 24.--25. " PINCFG ,Pin configuration" "SIN for input/SOUT for output,SIN for both,SOUT for both,SOUT for input/SIN for output" bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=match0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1" newline bitfld.long 0x00 11. " PCSPOL[3] ,Peripheral chip select 3 polarity" "Active low,Active high" bitfld.long 0x00 10. " [2] ,Peripheral chip select 2 polarity" "Active low,Active high" bitfld.long 0x00 9. " [1] ,Peripheral chip select 1 polarity" "Active low,Active high" bitfld.long 0x00 8. " [0] ,Peripheral chip select 0 polarity" "Active low,Active high" newline bitfld.long 0x00 3. " NOSTALL ,No stall" "Disabled,Enabled" bitfld.long 0x00 2. " AUTOPCS ,Automatic PCS" "Disabled,Enabled" bitfld.long 0x00 0. " MASTER ,Master mode" "Slave mode,Master mode" endif endif group.long 0x30++0x07 line.long 0x00 "DMR0,Data Match Register 0" line.long 0x04 "DMR1,Data Match Register 1" if (((per.l(ad:0x5A030000+0x24))&0x01)==0x01) if (((per.l(ad:0x5A030000+0x10))&0x01)==0x01) group.long 0x40++0x03 line.long 0x00 "CCR,Clock Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay" hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay" hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers" hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider" else rgroup.long 0x40++0x03 line.long 0x00 "CCR,Clock Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCKPCS ,SCK to PCS delay" hexmask.long.byte 0x00 16.--23. 1. " PCSSCK ,PCS to SCK delay" hexmask.long.byte 0x00 8.--15. 1. " DBT ,Delay between transfers" hexmask.long.byte 0x00 0.--7. 1. " SCKDIV ,SCK divider" endif else hgroup.long 0x40++0x03 hide.long 0x00 "CCR,Clock Configuration Register" endif group.long 0x58++0x03 line.long 0x00 "FCR,FIFO Control Register" bitfld.long 0x00 16.--21. " RXWATER ,Receive FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TXWATER ,Transmit FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x5C++0x03 line.long 0x00 "FSR,FIFO Status Register" hexmask.long.byte 0x00 16.--22. 1. " RXCOUNT ,Receive FIFO count" hexmask.long.byte 0x00 0.--6. 1. " TXCOUNT ,Transmit FIFO count" group.long 0x60++0x03 line.long 0x00 "TCR,Transmit Command Register" bitfld.long 0x00 31. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 30. " CPHA ,Clock phase" "Leading capture/following change,Leading change/following capture" bitfld.long 0x00 27.--29. " PRESCALE ,Prescaler value" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.long 0x00 24.--25. " PCS ,Peripheral chip select" "LPSPI_PCS[0],LPSPI_PCS[1],LPSPI_PCS[2],LPSPI_PCS[3]" newline bitfld.long 0x00 23. " LSBF ,LSB first" "MSB first,LSB first" bitfld.long 0x00 22. " BYSW ,Byte swap" "Disabled,Enabled" bitfld.long 0x00 21. " CONT ,Continuous transfer" "Disabled,Enabled" bitfld.long 0x00 20. " CONTC ,Continuing command" "New transfer,Continuing transfer" newline bitfld.long 0x00 19. " RXMSK ,Receive data mask" "Not masked,Masked" bitfld.long 0x00 18. " TXMSK ,Transmit data mask" "Not masked,Masked" bitfld.long 0x00 16.--17. " WIDTH ,Transfer width" "Single bit,Two bit,Four bit,?..." hexmask.long.word 0x00 0.--11. 1. " FRAMESZ ,Frame size" wgroup.long 0x64++0x03 line.long 0x00 "TDR,Transmit Data Register" rgroup.long 0x70++0x03 line.long 0x00 "RSR,Receive Status Register" bitfld.long 0x00 1. " RXEMPTY ,RX FIFO empty" "Not empty,Empty" bitfld.long 0x00 0. " SOF ,Start of frame" "Subsequent data,First data" hgroup.long 0x74++0x03 hide.long 0x00 "RDR,Receive Data Register" in width 0x0B tree.end tree.end tree.open "LPUART (Low Power Universal Asynchronous Receiver/Transmitter)" tree "LPUART0" base ad:0x5A060000 width 8. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature identification number" line.long 0x04 "PARAM,Parameter Register" hexmask.long.byte 0x04 8.--15. 1. " RXFIFO ,Receive FIFO size" hexmask.long.byte 0x04 0.--7. 1. " TXFIFO ,Transmit FIFO size" group.long 0x08++0x03 line.long 0x00 "GLOBAL,Global Register" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" if (((per.l(ad:0x5A060000+0x18))&0xC0000)==0x00) group.long 0x0C++0x03 line.long 0x00 "PINCFG,Pin Configuration Register" bitfld.long 0x00 0.--1. " TRGSEL ,Trigger select" "Disabled,Instead RX in,Instead CTS in,TX out modulation" else rgroup.long 0x0C++0x03 line.long 0x00 "PINCFG,Pin Configuration Register" bitfld.long 0x00 0.--1. " TRGSEL ,Trigger select" "Disabled,Instead RX in,Instead CTS in,TX out modulation" endif group.long 0x10++0x07 line.long 0x00 "BAUD,Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" bitfld.long 0x00 29. " M10 ,10-bit mode select" "7/8/9 bit,10 bit" newline bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" "16x,,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 20. " RIDMAE ,Receiver idle DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " SBNS ,Stop bit number select" "One,Two" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" bitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" bitfld.long 0x04 26. " BRK13 ,Break character generation length" "9-13 bit,12-15 bit" newline bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" newline eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" newline if (((per.l(ad:0x5A060000+0x18))&0xC0000)==0x00) if ((per.b(ad:0x5A060000+0x18)&0x08)==0x08) group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" newline bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,LPUART in Doze mode enabled" "LPUART enabled,LPUART disabled" newline bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" else group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" newline bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,LPUART in Doze mode enabled" "LPUART enabled,LPUART disabled" newline bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif else group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" rbitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" rbitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" rbitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline rbitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" rbitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline rbitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" rbitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" newline rbitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" rbitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" rbitfld.long 0x00 6. " DOZEEN ,LPUART in Doze mode enabled" "LPUART enabled,LPUART disabled" newline rbitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" rbitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" rbitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline rbitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" rbitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" rbitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif group.long 0x1C++0x07 line.long 0x00 "DATA,Data Register" rbitfld.long 0x00 15. " NOISY ,Current received dataword noise" "Not noisy,Noisy" rbitfld.long 0x00 14. " PARITYE ,Current received dataword parity error" "No error,Error" bitfld.long 0x00 13. " FRETSC ,Current received dataword frame error/Transmit special character" "No error/Normal character,Error/Special character" newline rbitfld.long 0x00 12. " RXEMPT ,Receive buffer empty" "Not empty,Empty" rbitfld.long 0x00 11. " IDLINE ,Receiver line idle status before receiving current character" "Not idle,Idle" newline bitfld.long 0x00 9. " R9T9 ,Read receive data buffer 9 or write transmit data buffer 9" "Low,High" bitfld.long 0x00 8. " R8T8 ,Read receive data buffer 8 or write transmit data buffer 8" "Low,High" bitfld.long 0x00 7. " R7T7 ,Read receive data buffer 7 or write transmit data buffer 7" "Low,High" newline bitfld.long 0x00 6. " R6T6 ,Read receive data buffer 6 or write transmit data buffer 6" "Low,High" bitfld.long 0x00 5. " R5T5 ,Read receive data buffer 5 or write transmit data buffer 5" "Low,High" bitfld.long 0x00 4. " R4T4 ,Read receive data buffer 4 or write transmit data buffer 4" "Low,High" newline bitfld.long 0x00 3. " R3T3 ,Read receive data buffer 3 or write transmit data buffer 3" "Low,High" bitfld.long 0x00 2. " R2T2 ,Read receive data buffer 2 or write transmit data buffer 2" "Low,High" bitfld.long 0x00 1. " R1T1 ,Read receive data buffer 1 or write transmit data buffer 1" "Low,High" newline bitfld.long 0x00 0. " R0T0 ,Read receive data buffer 0 or write transmit data buffer 0" "Low,High" line.long 0x04 "MATCH,Match Address Register" hexmask.long.word 0x04 16.--25. 0x01 " MA2 ,Match address 2" hexmask.long.word 0x04 0.--9. 0x01 " MA1 ,Match address 1" if (((per.l(ad:0x5A060000+0x18))&0xC0000)==0x00) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" bitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" newline bitfld.long 0x00 8.--12. " RTSWATER ,Receive RTS configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" elif (((per.l(ad:0x5A060000+0x18))&0xC0000)==0x40000) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" newline rbitfld.long 0x00 8.--12. " RTSWATER ,Receive RTS configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" rbitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" elif (((per.l(ad:0x5A060000+0x18))&0xC0000)==0x80000) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" newline bitfld.long 0x00 8.--12. " RTSWATER ,Receive RTS configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" rbitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline rbitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" newline rbitfld.long 0x00 8.--12. " RTSWATER ,Receive RTS configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" rbitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" rbitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline rbitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" endif if ((((per.l(ad:0x5A060000+0x18))&0xC0000)==0x00)&&(((per.l(ad:0x5A060000+0x28))&0xC00000)==0xC00000)) group.long 0x28++0x03 line.long 0x00 "FIFO,FIFO Register" rbitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO empty" "Not empty,Empty" rbitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO empty" "Not empty,Empty" eventfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" eventfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" newline rbitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" else rgroup.long 0x28++0x03 line.long 0x00 "FIFO,FIFO Register" bitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" bitfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" endif if (((per.l(ad:0x5A060000+0x18))&0x80000)==0x80000) rgroup.long 0x2C++0x03 line.long 0x00 "WATER,Watermark Register" bitfld.long 0x00 24.--29. " RXCOUNT ,Receive counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--20. " RXWATER ,Receive watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " TXCOUNT ,Transmit counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--4. " TXWATER ,Transmit watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x2C++0x03 line.long 0x00 "WATER,Watermark Register" rbitfld.long 0x00 24.--29. " RXCOUNT ,Receive counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--20. " RXWATER ,Receive watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " TXCOUNT ,Transmit counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--4. " TXWATER ,Transmit watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif width 0x0B tree.end tree "LPUART1" base ad:0x5A070000 width 8. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature identification number" line.long 0x04 "PARAM,Parameter Register" hexmask.long.byte 0x04 8.--15. 1. " RXFIFO ,Receive FIFO size" hexmask.long.byte 0x04 0.--7. 1. " TXFIFO ,Transmit FIFO size" group.long 0x08++0x03 line.long 0x00 "GLOBAL,Global Register" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" if (((per.l(ad:0x5A070000+0x18))&0xC0000)==0x00) group.long 0x0C++0x03 line.long 0x00 "PINCFG,Pin Configuration Register" bitfld.long 0x00 0.--1. " TRGSEL ,Trigger select" "Disabled,Instead RX in,Instead CTS in,TX out modulation" else rgroup.long 0x0C++0x03 line.long 0x00 "PINCFG,Pin Configuration Register" bitfld.long 0x00 0.--1. " TRGSEL ,Trigger select" "Disabled,Instead RX in,Instead CTS in,TX out modulation" endif group.long 0x10++0x07 line.long 0x00 "BAUD,Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" bitfld.long 0x00 29. " M10 ,10-bit mode select" "7/8/9 bit,10 bit" newline bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" "16x,,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 20. " RIDMAE ,Receiver idle DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " SBNS ,Stop bit number select" "One,Two" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" bitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" bitfld.long 0x04 26. " BRK13 ,Break character generation length" "9-13 bit,12-15 bit" newline bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" newline eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" newline if (((per.l(ad:0x5A070000+0x18))&0xC0000)==0x00) if ((per.b(ad:0x5A070000+0x18)&0x08)==0x08) group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" newline bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,LPUART in Doze mode enabled" "LPUART enabled,LPUART disabled" newline bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" else group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" newline bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,LPUART in Doze mode enabled" "LPUART enabled,LPUART disabled" newline bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif else group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" rbitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" rbitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" rbitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline rbitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" rbitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline rbitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" rbitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" newline rbitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" rbitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" rbitfld.long 0x00 6. " DOZEEN ,LPUART in Doze mode enabled" "LPUART enabled,LPUART disabled" newline rbitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" rbitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" rbitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline rbitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" rbitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" rbitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif group.long 0x1C++0x07 line.long 0x00 "DATA,Data Register" rbitfld.long 0x00 15. " NOISY ,Current received dataword noise" "Not noisy,Noisy" rbitfld.long 0x00 14. " PARITYE ,Current received dataword parity error" "No error,Error" bitfld.long 0x00 13. " FRETSC ,Current received dataword frame error/Transmit special character" "No error/Normal character,Error/Special character" newline rbitfld.long 0x00 12. " RXEMPT ,Receive buffer empty" "Not empty,Empty" rbitfld.long 0x00 11. " IDLINE ,Receiver line idle status before receiving current character" "Not idle,Idle" newline bitfld.long 0x00 9. " R9T9 ,Read receive data buffer 9 or write transmit data buffer 9" "Low,High" bitfld.long 0x00 8. " R8T8 ,Read receive data buffer 8 or write transmit data buffer 8" "Low,High" bitfld.long 0x00 7. " R7T7 ,Read receive data buffer 7 or write transmit data buffer 7" "Low,High" newline bitfld.long 0x00 6. " R6T6 ,Read receive data buffer 6 or write transmit data buffer 6" "Low,High" bitfld.long 0x00 5. " R5T5 ,Read receive data buffer 5 or write transmit data buffer 5" "Low,High" bitfld.long 0x00 4. " R4T4 ,Read receive data buffer 4 or write transmit data buffer 4" "Low,High" newline bitfld.long 0x00 3. " R3T3 ,Read receive data buffer 3 or write transmit data buffer 3" "Low,High" bitfld.long 0x00 2. " R2T2 ,Read receive data buffer 2 or write transmit data buffer 2" "Low,High" bitfld.long 0x00 1. " R1T1 ,Read receive data buffer 1 or write transmit data buffer 1" "Low,High" newline bitfld.long 0x00 0. " R0T0 ,Read receive data buffer 0 or write transmit data buffer 0" "Low,High" line.long 0x04 "MATCH,Match Address Register" hexmask.long.word 0x04 16.--25. 0x01 " MA2 ,Match address 2" hexmask.long.word 0x04 0.--9. 0x01 " MA1 ,Match address 1" if (((per.l(ad:0x5A070000+0x18))&0xC0000)==0x00) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" bitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" newline bitfld.long 0x00 8.--12. " RTSWATER ,Receive RTS configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" elif (((per.l(ad:0x5A070000+0x18))&0xC0000)==0x40000) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" newline rbitfld.long 0x00 8.--12. " RTSWATER ,Receive RTS configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" rbitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" elif (((per.l(ad:0x5A070000+0x18))&0xC0000)==0x80000) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" newline bitfld.long 0x00 8.--12. " RTSWATER ,Receive RTS configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" rbitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline rbitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" newline rbitfld.long 0x00 8.--12. " RTSWATER ,Receive RTS configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" rbitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" rbitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline rbitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" endif if ((((per.l(ad:0x5A070000+0x18))&0xC0000)==0x00)&&(((per.l(ad:0x5A070000+0x28))&0xC00000)==0xC00000)) group.long 0x28++0x03 line.long 0x00 "FIFO,FIFO Register" rbitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO empty" "Not empty,Empty" rbitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO empty" "Not empty,Empty" eventfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" eventfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" newline rbitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" else rgroup.long 0x28++0x03 line.long 0x00 "FIFO,FIFO Register" bitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" bitfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" endif if (((per.l(ad:0x5A070000+0x18))&0x80000)==0x80000) rgroup.long 0x2C++0x03 line.long 0x00 "WATER,Watermark Register" bitfld.long 0x00 24.--29. " RXCOUNT ,Receive counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--20. " RXWATER ,Receive watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " TXCOUNT ,Transmit counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--4. " TXWATER ,Transmit watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x2C++0x03 line.long 0x00 "WATER,Watermark Register" rbitfld.long 0x00 24.--29. " RXCOUNT ,Receive counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--20. " RXWATER ,Receive watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " TXCOUNT ,Transmit counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--4. " TXWATER ,Transmit watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif width 0x0B tree.end tree "LPUART2" base ad:0x5A080000 width 8. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature identification number" line.long 0x04 "PARAM,Parameter Register" hexmask.long.byte 0x04 8.--15. 1. " RXFIFO ,Receive FIFO size" hexmask.long.byte 0x04 0.--7. 1. " TXFIFO ,Transmit FIFO size" group.long 0x08++0x03 line.long 0x00 "GLOBAL,Global Register" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" if (((per.l(ad:0x5A080000+0x18))&0xC0000)==0x00) group.long 0x0C++0x03 line.long 0x00 "PINCFG,Pin Configuration Register" bitfld.long 0x00 0.--1. " TRGSEL ,Trigger select" "Disabled,Instead RX in,Instead CTS in,TX out modulation" else rgroup.long 0x0C++0x03 line.long 0x00 "PINCFG,Pin Configuration Register" bitfld.long 0x00 0.--1. " TRGSEL ,Trigger select" "Disabled,Instead RX in,Instead CTS in,TX out modulation" endif group.long 0x10++0x07 line.long 0x00 "BAUD,Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" bitfld.long 0x00 29. " M10 ,10-bit mode select" "7/8/9 bit,10 bit" newline bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" "16x,,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 20. " RIDMAE ,Receiver idle DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " SBNS ,Stop bit number select" "One,Two" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" bitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" bitfld.long 0x04 26. " BRK13 ,Break character generation length" "9-13 bit,12-15 bit" newline bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" newline eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" newline if (((per.l(ad:0x5A080000+0x18))&0xC0000)==0x00) if ((per.b(ad:0x5A080000+0x18)&0x08)==0x08) group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" newline bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,LPUART in Doze mode enabled" "LPUART enabled,LPUART disabled" newline bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" else group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" newline bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,LPUART in Doze mode enabled" "LPUART enabled,LPUART disabled" newline bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif else group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" rbitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" rbitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" rbitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline rbitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" rbitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline rbitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" rbitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" newline rbitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" rbitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" rbitfld.long 0x00 6. " DOZEEN ,LPUART in Doze mode enabled" "LPUART enabled,LPUART disabled" newline rbitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" rbitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" rbitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline rbitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" rbitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" rbitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif group.long 0x1C++0x07 line.long 0x00 "DATA,Data Register" rbitfld.long 0x00 15. " NOISY ,Current received dataword noise" "Not noisy,Noisy" rbitfld.long 0x00 14. " PARITYE ,Current received dataword parity error" "No error,Error" bitfld.long 0x00 13. " FRETSC ,Current received dataword frame error/Transmit special character" "No error/Normal character,Error/Special character" newline rbitfld.long 0x00 12. " RXEMPT ,Receive buffer empty" "Not empty,Empty" rbitfld.long 0x00 11. " IDLINE ,Receiver line idle status before receiving current character" "Not idle,Idle" newline bitfld.long 0x00 9. " R9T9 ,Read receive data buffer 9 or write transmit data buffer 9" "Low,High" bitfld.long 0x00 8. " R8T8 ,Read receive data buffer 8 or write transmit data buffer 8" "Low,High" bitfld.long 0x00 7. " R7T7 ,Read receive data buffer 7 or write transmit data buffer 7" "Low,High" newline bitfld.long 0x00 6. " R6T6 ,Read receive data buffer 6 or write transmit data buffer 6" "Low,High" bitfld.long 0x00 5. " R5T5 ,Read receive data buffer 5 or write transmit data buffer 5" "Low,High" bitfld.long 0x00 4. " R4T4 ,Read receive data buffer 4 or write transmit data buffer 4" "Low,High" newline bitfld.long 0x00 3. " R3T3 ,Read receive data buffer 3 or write transmit data buffer 3" "Low,High" bitfld.long 0x00 2. " R2T2 ,Read receive data buffer 2 or write transmit data buffer 2" "Low,High" bitfld.long 0x00 1. " R1T1 ,Read receive data buffer 1 or write transmit data buffer 1" "Low,High" newline bitfld.long 0x00 0. " R0T0 ,Read receive data buffer 0 or write transmit data buffer 0" "Low,High" line.long 0x04 "MATCH,Match Address Register" hexmask.long.word 0x04 16.--25. 0x01 " MA2 ,Match address 2" hexmask.long.word 0x04 0.--9. 0x01 " MA1 ,Match address 1" if (((per.l(ad:0x5A080000+0x18))&0xC0000)==0x00) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" bitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" newline bitfld.long 0x00 8.--12. " RTSWATER ,Receive RTS configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" elif (((per.l(ad:0x5A080000+0x18))&0xC0000)==0x40000) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" newline rbitfld.long 0x00 8.--12. " RTSWATER ,Receive RTS configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" rbitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" elif (((per.l(ad:0x5A080000+0x18))&0xC0000)==0x80000) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" newline bitfld.long 0x00 8.--12. " RTSWATER ,Receive RTS configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" rbitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline rbitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" newline rbitfld.long 0x00 8.--12. " RTSWATER ,Receive RTS configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" rbitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" rbitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline rbitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" endif if ((((per.l(ad:0x5A080000+0x18))&0xC0000)==0x00)&&(((per.l(ad:0x5A080000+0x28))&0xC00000)==0xC00000)) group.long 0x28++0x03 line.long 0x00 "FIFO,FIFO Register" rbitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO empty" "Not empty,Empty" rbitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO empty" "Not empty,Empty" eventfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" eventfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" newline rbitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" else rgroup.long 0x28++0x03 line.long 0x00 "FIFO,FIFO Register" bitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" bitfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" endif if (((per.l(ad:0x5A080000+0x18))&0x80000)==0x80000) rgroup.long 0x2C++0x03 line.long 0x00 "WATER,Watermark Register" bitfld.long 0x00 24.--29. " RXCOUNT ,Receive counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--20. " RXWATER ,Receive watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " TXCOUNT ,Transmit counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--4. " TXWATER ,Transmit watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x2C++0x03 line.long 0x00 "WATER,Watermark Register" rbitfld.long 0x00 24.--29. " RXCOUNT ,Receive counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--20. " RXWATER ,Receive watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " TXCOUNT ,Transmit counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--4. " TXWATER ,Transmit watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif width 0x0B tree.end tree "LPUART3" base ad:0x5A090000 width 8. rgroup.long 0x00++0x07 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature identification number" line.long 0x04 "PARAM,Parameter Register" hexmask.long.byte 0x04 8.--15. 1. " RXFIFO ,Receive FIFO size" hexmask.long.byte 0x04 0.--7. 1. " TXFIFO ,Transmit FIFO size" group.long 0x08++0x03 line.long 0x00 "GLOBAL,Global Register" bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset" if (((per.l(ad:0x5A090000+0x18))&0xC0000)==0x00) group.long 0x0C++0x03 line.long 0x00 "PINCFG,Pin Configuration Register" bitfld.long 0x00 0.--1. " TRGSEL ,Trigger select" "Disabled,Instead RX in,Instead CTS in,TX out modulation" else rgroup.long 0x0C++0x03 line.long 0x00 "PINCFG,Pin Configuration Register" bitfld.long 0x00 0.--1. " TRGSEL ,Trigger select" "Disabled,Instead RX in,Instead CTS in,TX out modulation" endif group.long 0x10++0x07 line.long 0x00 "BAUD,Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" bitfld.long 0x00 29. " M10 ,10-bit mode select" "7/8/9 bit,10 bit" newline bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" "16x,,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 20. " RIDMAE ,Receiver idle DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " SBNS ,Stop bit number select" "One,Two" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" bitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" bitfld.long 0x04 26. " BRK13 ,Break character generation length" "9-13 bit,12-15 bit" newline bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "Disabled,Enabled" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" newline eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" newline if (((per.l(ad:0x5A090000+0x18))&0xC0000)==0x00) if ((per.b(ad:0x5A090000+0x18)&0x08)==0x08) group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" newline bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,LPUART in Doze mode enabled" "LPUART enabled,LPUART disabled" newline bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" else group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" newline bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,LPUART in Doze mode enabled" "LPUART enabled,LPUART disabled" newline bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif else group.long 0x18++0x03 line.long 0x00 "CTRL,Control Register" rbitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" rbitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" rbitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline rbitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" rbitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline rbitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" rbitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 11. " M7 ,7-Bit Mode Select" "8/9/10 bit,7 bit" newline rbitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" rbitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" rbitfld.long 0x00 6. " DOZEEN ,LPUART in Doze mode enabled" "LPUART enabled,LPUART disabled" newline rbitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" rbitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" rbitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline rbitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" rbitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" rbitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif group.long 0x1C++0x07 line.long 0x00 "DATA,Data Register" rbitfld.long 0x00 15. " NOISY ,Current received dataword noise" "Not noisy,Noisy" rbitfld.long 0x00 14. " PARITYE ,Current received dataword parity error" "No error,Error" bitfld.long 0x00 13. " FRETSC ,Current received dataword frame error/Transmit special character" "No error/Normal character,Error/Special character" newline rbitfld.long 0x00 12. " RXEMPT ,Receive buffer empty" "Not empty,Empty" rbitfld.long 0x00 11. " IDLINE ,Receiver line idle status before receiving current character" "Not idle,Idle" newline bitfld.long 0x00 9. " R9T9 ,Read receive data buffer 9 or write transmit data buffer 9" "Low,High" bitfld.long 0x00 8. " R8T8 ,Read receive data buffer 8 or write transmit data buffer 8" "Low,High" bitfld.long 0x00 7. " R7T7 ,Read receive data buffer 7 or write transmit data buffer 7" "Low,High" newline bitfld.long 0x00 6. " R6T6 ,Read receive data buffer 6 or write transmit data buffer 6" "Low,High" bitfld.long 0x00 5. " R5T5 ,Read receive data buffer 5 or write transmit data buffer 5" "Low,High" bitfld.long 0x00 4. " R4T4 ,Read receive data buffer 4 or write transmit data buffer 4" "Low,High" newline bitfld.long 0x00 3. " R3T3 ,Read receive data buffer 3 or write transmit data buffer 3" "Low,High" bitfld.long 0x00 2. " R2T2 ,Read receive data buffer 2 or write transmit data buffer 2" "Low,High" bitfld.long 0x00 1. " R1T1 ,Read receive data buffer 1 or write transmit data buffer 1" "Low,High" newline bitfld.long 0x00 0. " R0T0 ,Read receive data buffer 0 or write transmit data buffer 0" "Low,High" line.long 0x04 "MATCH,Match Address Register" hexmask.long.word 0x04 16.--25. 0x01 " MA2 ,Match address 2" hexmask.long.word 0x04 0.--9. 0x01 " MA1 ,Match address 1" if (((per.l(ad:0x5A090000+0x18))&0xC0000)==0x00) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" bitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" newline bitfld.long 0x00 8.--12. " RTSWATER ,Receive RTS configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" elif (((per.l(ad:0x5A090000+0x18))&0xC0000)==0x40000) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" newline rbitfld.long 0x00 8.--12. " RTSWATER ,Receive RTS configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" rbitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" elif (((per.l(ad:0x5A090000+0x18))&0xC0000)==0x80000) group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" newline bitfld.long 0x00 8.--12. " RTSWATER ,Receive RTS configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" rbitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline rbitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "MODIR,Modem IrDA Register" rbitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" rbitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" newline rbitfld.long 0x00 8.--12. " RTSWATER ,Receive RTS configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "CTS_B pin,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" rbitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" rbitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline rbitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" endif if ((((per.l(ad:0x5A090000+0x18))&0xC0000)==0x00)&&(((per.l(ad:0x5A090000+0x28))&0xC00000)==0xC00000)) group.long 0x28++0x03 line.long 0x00 "FIFO,FIFO Register" rbitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO empty" "Not empty,Empty" rbitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO empty" "Not empty,Empty" eventfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" eventfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" newline rbitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" else rgroup.long 0x28++0x03 line.long 0x00 "FIFO,FIFO Register" bitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" bitfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth (datawords)" "1,4,8,16,32,64,128,256" endif if (((per.l(ad:0x5A090000+0x18))&0x80000)==0x80000) rgroup.long 0x2C++0x03 line.long 0x00 "WATER,Watermark Register" bitfld.long 0x00 24.--29. " RXCOUNT ,Receive counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--20. " RXWATER ,Receive watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " TXCOUNT ,Transmit counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--4. " TXWATER ,Transmit watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x2C++0x03 line.long 0x00 "WATER,Watermark Register" rbitfld.long 0x00 24.--29. " RXCOUNT ,Receive counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 16.--20. " RXWATER ,Receive watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " TXCOUNT ,Transmit counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--4. " TXWATER ,Transmit watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif width 0x0B tree.end tree.end tree "MQS (Medium Quality Sound)" base ad:0x59850000 width 5. group.long 0x00++0x03 line.long 0x00 "MCR,MQS Configuration Register" bitfld.long 0x00 28. " ENB ,MQS module enable" "Disabled,Enabled" bitfld.long 0x00 24. " RST ,Software reset" "Negate reset,Assert reset" bitfld.long 0x00 20. " OVR ,PWM oversampling ratio" "32,64" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Clock divider ratio" width 0x0B tree.end tree.open "SAI (Synchronous Audio Interface)" tree "SAI0" base ad:0x59040000 width 6. if (((per.l(ad:0x59040000)&0x80000000)==0x80000000))&&(((per.l(ad:0x59040000)&0x40000)==0x00)) group.long 0x00++0x03 line.long 0x00 "TCSR,Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" newline eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled transmit FIFO empty)" "Not detected,Detected" rbitfld.long 0x00 16. " FRF ,FIFO request flag (Transmit FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "TCSR,Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" newline eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled transmit FIFO empty)" "Not detected,Detected" rbitfld.long 0x00 16. " FRF ,FIFO request flag (Transmit FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" endif group.long 0x04++0x03 line.long 0x00 "TCR1,Transmit Configuration 1 Register" bitfld.long 0x00 0.--5. " TFW ,Transmit FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0x59040000)&0x80000000)==0x00)) group.long 0x08++0x03 line.long 0x00 "TCR2,Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous with RX,Synchronous with SAI TX,Synchronous with SAI RX" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal logic clocked" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "High,Low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally slave mode,Internally master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" else rgroup.long 0x08++0x03 line.long 0x00 "TCR2,Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous with RX,Synchronous with SAI TX,Synchronous with SAI RX" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal logic clocked" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "High,Low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally slave mode,Internally master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" endif group.long 0x0C++0x03 line.long 0x00 "TCR3,Transmit Configuration 3 Register" bitfld.long 0x00 16. " TCE ,Transmit channel enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x59040000)&0x80000000)==0x00)) group.long 0x10++0x07 line.long 0x00 "TCR4,Transmit Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "From start,From error" bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode enable" "Disabled,,Enabled: 8 bit,Enabled: 16 bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,On FWF clear" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "High,Low" newline bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally slave mode,Internally master mode" line.long 0x04 "TCR5,Transmit Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" else rgroup.long 0x10++0x07 line.long 0x00 "TCR4,Transmit Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "From start,From error" bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode enable" "Disabled,,Enabled: 8 bit,Enabled: 16 bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,On FWF clear" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "High,Low" newline bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally slave mode,Internally master mode" line.long 0x04 "TCR5,Transmit Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" endif wgroup.long 0x20++0x03 line.long 0x00 "TDR0,Transmit Data Register 0" rgroup.long 0x40++0x03 line.long 0x00 "TFR0,Transmit FIFO Register 0" hexmask.long.byte 0x00 16.--22. 0x01 " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--6. 0x01 " RFP ,Read FIFO pointer" group.long 0x60++0x03 line.long 0x00 "TMR,Transmit Mask Register" bitfld.long 0x00 31. " TWM[31] ,Transmit word 31 mask" "Unmasked,Masked" bitfld.long 0x00 30. " [30] ,Transmit word 30 mask" "Unmasked,Masked" bitfld.long 0x00 29. " [29] ,Transmit word 29 mask" "Unmasked,Masked" bitfld.long 0x00 28. " [28] ,Transmit word 28 mask" "Unmasked,Masked" newline bitfld.long 0x00 27. " [27] ,Transmit word 27 mask" "Unmasked,Masked" bitfld.long 0x00 26. " [26] ,Transmit word 26 mask" "Unmasked,Masked" bitfld.long 0x00 25. " [25] ,Transmit word 25 mask" "Unmasked,Masked" bitfld.long 0x00 24. " [24] ,Transmit word 24 mask" "Unmasked,Masked" newline bitfld.long 0x00 23. " [23] ,Transmit word 23 mask" "Unmasked,Masked" bitfld.long 0x00 22. " [22] ,Transmit word 22 mask" "Unmasked,Masked" bitfld.long 0x00 21. " [21] ,Transmit word 21 mask" "Unmasked,Masked" bitfld.long 0x00 20. " [20] ,Transmit word 20 mask" "Unmasked,Masked" newline bitfld.long 0x00 19. " [19] ,Transmit word 19 mask" "Unmasked,Masked" bitfld.long 0x00 18. " [18] ,Transmit word 18 mask" "Unmasked,Masked" bitfld.long 0x00 17. " [17] ,Transmit word 17 mask" "Unmasked,Masked" bitfld.long 0x00 16. " [16] ,Transmit word 16 mask" "Unmasked,Masked" newline bitfld.long 0x00 15. " [15] ,Transmit word 15 mask" "Unmasked,Masked" bitfld.long 0x00 14. " [14] ,Transmit word 14 mask" "Unmasked,Masked" bitfld.long 0x00 13. " [13] ,Transmit word 13 mask" "Unmasked,Masked" bitfld.long 0x00 12. " [12] ,Transmit word 12 mask" "Unmasked,Masked" newline bitfld.long 0x00 11. " [11] ,Transmit word 11 mask" "Unmasked,Masked" bitfld.long 0x00 10. " [10] ,Transmit word 10 mask" "Unmasked,Masked" bitfld.long 0x00 9. " [9] ,Transmit word 9 mask" "Unmasked,Masked" bitfld.long 0x00 8. " [8] ,Transmit word 8 mask" "Unmasked,Masked" newline bitfld.long 0x00 7. " [7] ,Transmit word 7 mask" "Unmasked,Masked" bitfld.long 0x00 6. " [6] ,Transmit word 6 mask" "Unmasked,Masked" bitfld.long 0x00 5. " [5] ,Transmit word 5 mask" "Unmasked,Masked" bitfld.long 0x00 4. " [4] ,Transmit word 4 mask" "Unmasked,Masked" newline bitfld.long 0x00 3. " [3] ,Transmit word 3 mask" "Unmasked,Masked" bitfld.long 0x00 2. " [2] ,Transmit word 2 mask" "Unmasked,Masked" bitfld.long 0x00 1. " [1] ,Transmit word 1 mask" "Unmasked,Masked" bitfld.long 0x00 0. " [0] ,Transmit word 0 mask" "Unmasked,Masked" newline if (((per.l(ad:0x59040000+0x80)&0x80000000)==0x80000000))&&(((per.l(ad:0x59040000+0x80)&0x40000)==0x00)) group.long 0x80++0x03 line.long 0x00 "RCSR,Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" newline eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" bitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" bitfld.long 0x00 16. " FRF ,FIFO request flag (Receive FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "RCSR,Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" newline eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" bitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" bitfld.long 0x00 16. " FRF ,FIFO request flag (Receive FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "RCR1,Receive Configuration 1 Register" bitfld.long 0x00 0.--5. " RFW ,Receive FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0x59040000+0x80)&0x80000000)==0x00)) group.long 0x88++0x03 line.long 0x00 "RCR2,Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous with TX,Synchronous with SAI RX,Synchronous with SAI TX" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal logic clocked" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "High,Low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally in slave mode,Internally in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" else rgroup.long 0x88++0x03 line.long 0x00 "RCR2,Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous with TX,Synchronous with SAI RX,Synchronous with SAI TX" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal logic clocked" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "High,Low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally in slave mode,Internally in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" endif group.long 0x8C++0x03 line.long 0x00 "RCR3,Receive Configuration 3 Register" bitfld.long 0x00 16. " RCE ,Receive channel enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x59040000+0x80)&0x80000000)==0x00)) group.long 0x90++0x07 line.long 0x00 "RCR4,Receive Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "From start,From error" bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,Enabled: 8 bit,Enabled: 16 bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,On FWF clear" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "High,Low" newline bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally in slave mode,Internally in master mode" line.long 0x04 "RCR5,Receive Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" else rgroup.long 0x90++0x07 line.long 0x00 "RCR4,Receive Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "From start,From error" bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,Enabled: 8 bit,Enabled: 16 bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,On FWF clear" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "High,Low" newline bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally in slave mode,Internally in master mode" line.long 0x04 "RCR5,Receive Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" endif hgroup.long 0xA0++0x03 hide.long 0x00 "RDR0,Receive Data Register 0" in rgroup.long 0xC0++0x03 line.long 0x00 "RFR0,Receive FIFO Register 0" hexmask.long.byte 0x00 16.--22. 0x01 " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--6. 0x01 " RFP ,Read FIFO pointer" group.long 0xE0++0x03 line.long 0x00 "RMR,Receive Mask Register" bitfld.long 0x00 31. " RWM[31] ,Receive word 31 mask" "Unmasked,Masked" bitfld.long 0x00 30. " [30] ,Receive word 30 mask" "Unmasked,Masked" bitfld.long 0x00 29. " [29] ,Receive word 29 mask" "Unmasked,Masked" bitfld.long 0x00 28. " [28] ,Receive word 28 mask" "Unmasked,Masked" newline bitfld.long 0x00 27. " [27] ,Receive word 27 mask" "Unmasked,Masked" bitfld.long 0x00 26. " [26] ,Receive word 26 mask" "Unmasked,Masked" bitfld.long 0x00 25. " [25] ,Receive word 25 mask" "Unmasked,Masked" bitfld.long 0x00 24. " [24] ,Receive word 24 mask" "Unmasked,Masked" newline bitfld.long 0x00 23. " [23] ,Receive word 23 mask" "Unmasked,Masked" bitfld.long 0x00 22. " [22] ,Receive word 22 mask" "Unmasked,Masked" bitfld.long 0x00 21. " [21] ,Receive word 21 mask" "Unmasked,Masked" bitfld.long 0x00 20. " [20] ,Receive word 20 mask" "Unmasked,Masked" newline bitfld.long 0x00 19. " [19] ,Receive word 19 mask" "Unmasked,Masked" bitfld.long 0x00 18. " [18] ,Receive word 18 mask" "Unmasked,Masked" bitfld.long 0x00 17. " [17] ,Receive word 17 mask" "Unmasked,Masked" bitfld.long 0x00 16. " [16] ,Receive word 16 mask" "Unmasked,Masked" newline bitfld.long 0x00 15. " [15] ,Receive word 15 mask" "Unmasked,Masked" bitfld.long 0x00 14. " [14] ,Receive word 14 mask" "Unmasked,Masked" bitfld.long 0x00 13. " [13] ,Receive word 13 mask" "Unmasked,Masked" bitfld.long 0x00 12. " [12] ,Receive word 12 mask" "Unmasked,Masked" newline bitfld.long 0x00 11. " [11] ,Receive word 11 mask" "Unmasked,Masked" bitfld.long 0x00 10. " [10] ,Receive word 10 mask" "Unmasked,Masked" bitfld.long 0x00 9. " [9] ,Receive word 9 mask" "Unmasked,Masked" bitfld.long 0x00 8. " [8] ,Receive word 8 mask" "Unmasked,Masked" newline bitfld.long 0x00 7. " [7] ,Receive word 7 mask" "Unmasked,Masked" bitfld.long 0x00 6. " [6] ,Receive word 6 mask" "Unmasked,Masked" bitfld.long 0x00 5. " [5] ,Receive word 5 mask" "Unmasked,Masked" bitfld.long 0x00 4. " [4] ,Receive word 4 mask" "Unmasked,Masked" newline bitfld.long 0x00 3. " [3] ,Receive word 3 mask" "Unmasked,Masked" bitfld.long 0x00 2. " [2] ,Receive word 2 mask" "Unmasked,Masked" bitfld.long 0x00 1. " [1] ,Receive word 1 mask" "Unmasked,Masked" bitfld.long 0x00 0. " [0] ,Receive word 0 mask" "Unmasked,Masked" width 0x0B tree.end tree "SAI1" base ad:0x59050000 width 6. if (((per.l(ad:0x59050000)&0x80000000)==0x80000000))&&(((per.l(ad:0x59050000)&0x40000)==0x00)) group.long 0x00++0x03 line.long 0x00 "TCSR,Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" newline eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled transmit FIFO empty)" "Not detected,Detected" rbitfld.long 0x00 16. " FRF ,FIFO request flag (Transmit FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "TCSR,Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" newline eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled transmit FIFO empty)" "Not detected,Detected" rbitfld.long 0x00 16. " FRF ,FIFO request flag (Transmit FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" endif group.long 0x04++0x03 line.long 0x00 "TCR1,Transmit Configuration 1 Register" bitfld.long 0x00 0.--5. " TFW ,Transmit FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0x59050000)&0x80000000)==0x00)) group.long 0x08++0x03 line.long 0x00 "TCR2,Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous with RX,Synchronous with SAI TX,Synchronous with SAI RX" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal logic clocked" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "High,Low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally slave mode,Internally master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" else rgroup.long 0x08++0x03 line.long 0x00 "TCR2,Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous with RX,Synchronous with SAI TX,Synchronous with SAI RX" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal logic clocked" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "High,Low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally slave mode,Internally master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" endif group.long 0x0C++0x03 line.long 0x00 "TCR3,Transmit Configuration 3 Register" bitfld.long 0x00 16. " TCE ,Transmit channel enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x59050000)&0x80000000)==0x00)) group.long 0x10++0x07 line.long 0x00 "TCR4,Transmit Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "From start,From error" bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode enable" "Disabled,,Enabled: 8 bit,Enabled: 16 bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,On FWF clear" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "High,Low" newline bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally slave mode,Internally master mode" line.long 0x04 "TCR5,Transmit Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" else rgroup.long 0x10++0x07 line.long 0x00 "TCR4,Transmit Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "From start,From error" bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode enable" "Disabled,,Enabled: 8 bit,Enabled: 16 bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,On FWF clear" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "High,Low" newline bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally slave mode,Internally master mode" line.long 0x04 "TCR5,Transmit Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" endif wgroup.long 0x20++0x03 line.long 0x00 "TDR0,Transmit Data Register 0" rgroup.long 0x40++0x03 line.long 0x00 "TFR0,Transmit FIFO Register 0" hexmask.long.byte 0x00 16.--22. 0x01 " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--6. 0x01 " RFP ,Read FIFO pointer" group.long 0x60++0x03 line.long 0x00 "TMR,Transmit Mask Register" bitfld.long 0x00 31. " TWM[31] ,Transmit word 31 mask" "Unmasked,Masked" bitfld.long 0x00 30. " [30] ,Transmit word 30 mask" "Unmasked,Masked" bitfld.long 0x00 29. " [29] ,Transmit word 29 mask" "Unmasked,Masked" bitfld.long 0x00 28. " [28] ,Transmit word 28 mask" "Unmasked,Masked" newline bitfld.long 0x00 27. " [27] ,Transmit word 27 mask" "Unmasked,Masked" bitfld.long 0x00 26. " [26] ,Transmit word 26 mask" "Unmasked,Masked" bitfld.long 0x00 25. " [25] ,Transmit word 25 mask" "Unmasked,Masked" bitfld.long 0x00 24. " [24] ,Transmit word 24 mask" "Unmasked,Masked" newline bitfld.long 0x00 23. " [23] ,Transmit word 23 mask" "Unmasked,Masked" bitfld.long 0x00 22. " [22] ,Transmit word 22 mask" "Unmasked,Masked" bitfld.long 0x00 21. " [21] ,Transmit word 21 mask" "Unmasked,Masked" bitfld.long 0x00 20. " [20] ,Transmit word 20 mask" "Unmasked,Masked" newline bitfld.long 0x00 19. " [19] ,Transmit word 19 mask" "Unmasked,Masked" bitfld.long 0x00 18. " [18] ,Transmit word 18 mask" "Unmasked,Masked" bitfld.long 0x00 17. " [17] ,Transmit word 17 mask" "Unmasked,Masked" bitfld.long 0x00 16. " [16] ,Transmit word 16 mask" "Unmasked,Masked" newline bitfld.long 0x00 15. " [15] ,Transmit word 15 mask" "Unmasked,Masked" bitfld.long 0x00 14. " [14] ,Transmit word 14 mask" "Unmasked,Masked" bitfld.long 0x00 13. " [13] ,Transmit word 13 mask" "Unmasked,Masked" bitfld.long 0x00 12. " [12] ,Transmit word 12 mask" "Unmasked,Masked" newline bitfld.long 0x00 11. " [11] ,Transmit word 11 mask" "Unmasked,Masked" bitfld.long 0x00 10. " [10] ,Transmit word 10 mask" "Unmasked,Masked" bitfld.long 0x00 9. " [9] ,Transmit word 9 mask" "Unmasked,Masked" bitfld.long 0x00 8. " [8] ,Transmit word 8 mask" "Unmasked,Masked" newline bitfld.long 0x00 7. " [7] ,Transmit word 7 mask" "Unmasked,Masked" bitfld.long 0x00 6. " [6] ,Transmit word 6 mask" "Unmasked,Masked" bitfld.long 0x00 5. " [5] ,Transmit word 5 mask" "Unmasked,Masked" bitfld.long 0x00 4. " [4] ,Transmit word 4 mask" "Unmasked,Masked" newline bitfld.long 0x00 3. " [3] ,Transmit word 3 mask" "Unmasked,Masked" bitfld.long 0x00 2. " [2] ,Transmit word 2 mask" "Unmasked,Masked" bitfld.long 0x00 1. " [1] ,Transmit word 1 mask" "Unmasked,Masked" bitfld.long 0x00 0. " [0] ,Transmit word 0 mask" "Unmasked,Masked" newline if (((per.l(ad:0x59050000+0x80)&0x80000000)==0x80000000))&&(((per.l(ad:0x59050000+0x80)&0x40000)==0x00)) group.long 0x80++0x03 line.long 0x00 "RCSR,Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" newline eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" bitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" bitfld.long 0x00 16. " FRF ,FIFO request flag (Receive FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "RCSR,Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" newline eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" bitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" bitfld.long 0x00 16. " FRF ,FIFO request flag (Receive FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "RCR1,Receive Configuration 1 Register" bitfld.long 0x00 0.--5. " RFW ,Receive FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0x59050000+0x80)&0x80000000)==0x00)) group.long 0x88++0x03 line.long 0x00 "RCR2,Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous with TX,Synchronous with SAI RX,Synchronous with SAI TX" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal logic clocked" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "High,Low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally in slave mode,Internally in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" else rgroup.long 0x88++0x03 line.long 0x00 "RCR2,Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous with TX,Synchronous with SAI RX,Synchronous with SAI TX" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal logic clocked" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "High,Low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally in slave mode,Internally in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" endif group.long 0x8C++0x03 line.long 0x00 "RCR3,Receive Configuration 3 Register" bitfld.long 0x00 16. " RCE ,Receive channel enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x59050000+0x80)&0x80000000)==0x00)) group.long 0x90++0x07 line.long 0x00 "RCR4,Receive Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "From start,From error" bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,Enabled: 8 bit,Enabled: 16 bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,On FWF clear" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "High,Low" newline bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally in slave mode,Internally in master mode" line.long 0x04 "RCR5,Receive Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" else rgroup.long 0x90++0x07 line.long 0x00 "RCR4,Receive Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "From start,From error" bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,Enabled: 8 bit,Enabled: 16 bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,On FWF clear" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "High,Low" newline bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally in slave mode,Internally in master mode" line.long 0x04 "RCR5,Receive Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" endif hgroup.long 0xA0++0x03 hide.long 0x00 "RDR0,Receive Data Register 0" in rgroup.long 0xC0++0x03 line.long 0x00 "RFR0,Receive FIFO Register 0" hexmask.long.byte 0x00 16.--22. 0x01 " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--6. 0x01 " RFP ,Read FIFO pointer" group.long 0xE0++0x03 line.long 0x00 "RMR,Receive Mask Register" bitfld.long 0x00 31. " RWM[31] ,Receive word 31 mask" "Unmasked,Masked" bitfld.long 0x00 30. " [30] ,Receive word 30 mask" "Unmasked,Masked" bitfld.long 0x00 29. " [29] ,Receive word 29 mask" "Unmasked,Masked" bitfld.long 0x00 28. " [28] ,Receive word 28 mask" "Unmasked,Masked" newline bitfld.long 0x00 27. " [27] ,Receive word 27 mask" "Unmasked,Masked" bitfld.long 0x00 26. " [26] ,Receive word 26 mask" "Unmasked,Masked" bitfld.long 0x00 25. " [25] ,Receive word 25 mask" "Unmasked,Masked" bitfld.long 0x00 24. " [24] ,Receive word 24 mask" "Unmasked,Masked" newline bitfld.long 0x00 23. " [23] ,Receive word 23 mask" "Unmasked,Masked" bitfld.long 0x00 22. " [22] ,Receive word 22 mask" "Unmasked,Masked" bitfld.long 0x00 21. " [21] ,Receive word 21 mask" "Unmasked,Masked" bitfld.long 0x00 20. " [20] ,Receive word 20 mask" "Unmasked,Masked" newline bitfld.long 0x00 19. " [19] ,Receive word 19 mask" "Unmasked,Masked" bitfld.long 0x00 18. " [18] ,Receive word 18 mask" "Unmasked,Masked" bitfld.long 0x00 17. " [17] ,Receive word 17 mask" "Unmasked,Masked" bitfld.long 0x00 16. " [16] ,Receive word 16 mask" "Unmasked,Masked" newline bitfld.long 0x00 15. " [15] ,Receive word 15 mask" "Unmasked,Masked" bitfld.long 0x00 14. " [14] ,Receive word 14 mask" "Unmasked,Masked" bitfld.long 0x00 13. " [13] ,Receive word 13 mask" "Unmasked,Masked" bitfld.long 0x00 12. " [12] ,Receive word 12 mask" "Unmasked,Masked" newline bitfld.long 0x00 11. " [11] ,Receive word 11 mask" "Unmasked,Masked" bitfld.long 0x00 10. " [10] ,Receive word 10 mask" "Unmasked,Masked" bitfld.long 0x00 9. " [9] ,Receive word 9 mask" "Unmasked,Masked" bitfld.long 0x00 8. " [8] ,Receive word 8 mask" "Unmasked,Masked" newline bitfld.long 0x00 7. " [7] ,Receive word 7 mask" "Unmasked,Masked" bitfld.long 0x00 6. " [6] ,Receive word 6 mask" "Unmasked,Masked" bitfld.long 0x00 5. " [5] ,Receive word 5 mask" "Unmasked,Masked" bitfld.long 0x00 4. " [4] ,Receive word 4 mask" "Unmasked,Masked" newline bitfld.long 0x00 3. " [3] ,Receive word 3 mask" "Unmasked,Masked" bitfld.long 0x00 2. " [2] ,Receive word 2 mask" "Unmasked,Masked" bitfld.long 0x00 1. " [1] ,Receive word 1 mask" "Unmasked,Masked" bitfld.long 0x00 0. " [0] ,Receive word 0 mask" "Unmasked,Masked" width 0x0B tree.end tree "SAI2" base ad:0x59060000 width 6. if (((per.l(ad:0x59060000)&0x80000000)==0x80000000))&&(((per.l(ad:0x59060000)&0x40000)==0x00)) group.long 0x00++0x03 line.long 0x00 "TCSR,Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" newline eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled transmit FIFO empty)" "Not detected,Detected" rbitfld.long 0x00 16. " FRF ,FIFO request flag (Transmit FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "TCSR,Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" newline eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled transmit FIFO empty)" "Not detected,Detected" rbitfld.long 0x00 16. " FRF ,FIFO request flag (Transmit FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" endif group.long 0x04++0x03 line.long 0x00 "TCR1,Transmit Configuration 1 Register" bitfld.long 0x00 0.--5. " TFW ,Transmit FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0x59060000)&0x80000000)==0x00)) group.long 0x08++0x03 line.long 0x00 "TCR2,Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous with RX,Synchronous with SAI TX,Synchronous with SAI RX" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal logic clocked" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "High,Low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally slave mode,Internally master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" else rgroup.long 0x08++0x03 line.long 0x00 "TCR2,Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous with RX,Synchronous with SAI TX,Synchronous with SAI RX" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal logic clocked" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "High,Low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally slave mode,Internally master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" endif group.long 0x0C++0x03 line.long 0x00 "TCR3,Transmit Configuration 3 Register" bitfld.long 0x00 16. " TCE ,Transmit channel enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x59060000)&0x80000000)==0x00)) group.long 0x10++0x07 line.long 0x00 "TCR4,Transmit Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "From start,From error" bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode enable" "Disabled,,Enabled: 8 bit,Enabled: 16 bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,On FWF clear" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "High,Low" newline bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally slave mode,Internally master mode" line.long 0x04 "TCR5,Transmit Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" else rgroup.long 0x10++0x07 line.long 0x00 "TCR4,Transmit Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "From start,From error" bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode enable" "Disabled,,Enabled: 8 bit,Enabled: 16 bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,On FWF clear" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "High,Low" newline bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally slave mode,Internally master mode" line.long 0x04 "TCR5,Transmit Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" endif wgroup.long 0x20++0x03 line.long 0x00 "TDR0,Transmit Data Register 0" rgroup.long 0x40++0x03 line.long 0x00 "TFR0,Transmit FIFO Register 0" hexmask.long.byte 0x00 16.--22. 0x01 " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--6. 0x01 " RFP ,Read FIFO pointer" group.long 0x60++0x03 line.long 0x00 "TMR,Transmit Mask Register" bitfld.long 0x00 31. " TWM[31] ,Transmit word 31 mask" "Unmasked,Masked" bitfld.long 0x00 30. " [30] ,Transmit word 30 mask" "Unmasked,Masked" bitfld.long 0x00 29. " [29] ,Transmit word 29 mask" "Unmasked,Masked" bitfld.long 0x00 28. " [28] ,Transmit word 28 mask" "Unmasked,Masked" newline bitfld.long 0x00 27. " [27] ,Transmit word 27 mask" "Unmasked,Masked" bitfld.long 0x00 26. " [26] ,Transmit word 26 mask" "Unmasked,Masked" bitfld.long 0x00 25. " [25] ,Transmit word 25 mask" "Unmasked,Masked" bitfld.long 0x00 24. " [24] ,Transmit word 24 mask" "Unmasked,Masked" newline bitfld.long 0x00 23. " [23] ,Transmit word 23 mask" "Unmasked,Masked" bitfld.long 0x00 22. " [22] ,Transmit word 22 mask" "Unmasked,Masked" bitfld.long 0x00 21. " [21] ,Transmit word 21 mask" "Unmasked,Masked" bitfld.long 0x00 20. " [20] ,Transmit word 20 mask" "Unmasked,Masked" newline bitfld.long 0x00 19. " [19] ,Transmit word 19 mask" "Unmasked,Masked" bitfld.long 0x00 18. " [18] ,Transmit word 18 mask" "Unmasked,Masked" bitfld.long 0x00 17. " [17] ,Transmit word 17 mask" "Unmasked,Masked" bitfld.long 0x00 16. " [16] ,Transmit word 16 mask" "Unmasked,Masked" newline bitfld.long 0x00 15. " [15] ,Transmit word 15 mask" "Unmasked,Masked" bitfld.long 0x00 14. " [14] ,Transmit word 14 mask" "Unmasked,Masked" bitfld.long 0x00 13. " [13] ,Transmit word 13 mask" "Unmasked,Masked" bitfld.long 0x00 12. " [12] ,Transmit word 12 mask" "Unmasked,Masked" newline bitfld.long 0x00 11. " [11] ,Transmit word 11 mask" "Unmasked,Masked" bitfld.long 0x00 10. " [10] ,Transmit word 10 mask" "Unmasked,Masked" bitfld.long 0x00 9. " [9] ,Transmit word 9 mask" "Unmasked,Masked" bitfld.long 0x00 8. " [8] ,Transmit word 8 mask" "Unmasked,Masked" newline bitfld.long 0x00 7. " [7] ,Transmit word 7 mask" "Unmasked,Masked" bitfld.long 0x00 6. " [6] ,Transmit word 6 mask" "Unmasked,Masked" bitfld.long 0x00 5. " [5] ,Transmit word 5 mask" "Unmasked,Masked" bitfld.long 0x00 4. " [4] ,Transmit word 4 mask" "Unmasked,Masked" newline bitfld.long 0x00 3. " [3] ,Transmit word 3 mask" "Unmasked,Masked" bitfld.long 0x00 2. " [2] ,Transmit word 2 mask" "Unmasked,Masked" bitfld.long 0x00 1. " [1] ,Transmit word 1 mask" "Unmasked,Masked" bitfld.long 0x00 0. " [0] ,Transmit word 0 mask" "Unmasked,Masked" newline if (((per.l(ad:0x59060000+0x80)&0x80000000)==0x80000000))&&(((per.l(ad:0x59060000+0x80)&0x40000)==0x00)) group.long 0x80++0x03 line.long 0x00 "RCSR,Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" newline eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" bitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" bitfld.long 0x00 16. " FRF ,FIFO request flag (Receive FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "RCSR,Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" newline eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" bitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" bitfld.long 0x00 16. " FRF ,FIFO request flag (Receive FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "RCR1,Receive Configuration 1 Register" bitfld.long 0x00 0.--5. " RFW ,Receive FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0x59060000+0x80)&0x80000000)==0x00)) group.long 0x88++0x03 line.long 0x00 "RCR2,Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous with TX,Synchronous with SAI RX,Synchronous with SAI TX" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal logic clocked" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "High,Low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally in slave mode,Internally in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" else rgroup.long 0x88++0x03 line.long 0x00 "RCR2,Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous with TX,Synchronous with SAI RX,Synchronous with SAI TX" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal logic clocked" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "High,Low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally in slave mode,Internally in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" endif group.long 0x8C++0x03 line.long 0x00 "RCR3,Receive Configuration 3 Register" bitfld.long 0x00 16. " RCE ,Receive channel enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x59060000+0x80)&0x80000000)==0x00)) group.long 0x90++0x07 line.long 0x00 "RCR4,Receive Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "From start,From error" bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,Enabled: 8 bit,Enabled: 16 bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,On FWF clear" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "High,Low" newline bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally in slave mode,Internally in master mode" line.long 0x04 "RCR5,Receive Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" else rgroup.long 0x90++0x07 line.long 0x00 "RCR4,Receive Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "From start,From error" bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,Enabled: 8 bit,Enabled: 16 bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,On FWF clear" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "High,Low" newline bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally in slave mode,Internally in master mode" line.long 0x04 "RCR5,Receive Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" endif hgroup.long 0xA0++0x03 hide.long 0x00 "RDR0,Receive Data Register 0" in rgroup.long 0xC0++0x03 line.long 0x00 "RFR0,Receive FIFO Register 0" hexmask.long.byte 0x00 16.--22. 0x01 " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--6. 0x01 " RFP ,Read FIFO pointer" group.long 0xE0++0x03 line.long 0x00 "RMR,Receive Mask Register" bitfld.long 0x00 31. " RWM[31] ,Receive word 31 mask" "Unmasked,Masked" bitfld.long 0x00 30. " [30] ,Receive word 30 mask" "Unmasked,Masked" bitfld.long 0x00 29. " [29] ,Receive word 29 mask" "Unmasked,Masked" bitfld.long 0x00 28. " [28] ,Receive word 28 mask" "Unmasked,Masked" newline bitfld.long 0x00 27. " [27] ,Receive word 27 mask" "Unmasked,Masked" bitfld.long 0x00 26. " [26] ,Receive word 26 mask" "Unmasked,Masked" bitfld.long 0x00 25. " [25] ,Receive word 25 mask" "Unmasked,Masked" bitfld.long 0x00 24. " [24] ,Receive word 24 mask" "Unmasked,Masked" newline bitfld.long 0x00 23. " [23] ,Receive word 23 mask" "Unmasked,Masked" bitfld.long 0x00 22. " [22] ,Receive word 22 mask" "Unmasked,Masked" bitfld.long 0x00 21. " [21] ,Receive word 21 mask" "Unmasked,Masked" bitfld.long 0x00 20. " [20] ,Receive word 20 mask" "Unmasked,Masked" newline bitfld.long 0x00 19. " [19] ,Receive word 19 mask" "Unmasked,Masked" bitfld.long 0x00 18. " [18] ,Receive word 18 mask" "Unmasked,Masked" bitfld.long 0x00 17. " [17] ,Receive word 17 mask" "Unmasked,Masked" bitfld.long 0x00 16. " [16] ,Receive word 16 mask" "Unmasked,Masked" newline bitfld.long 0x00 15. " [15] ,Receive word 15 mask" "Unmasked,Masked" bitfld.long 0x00 14. " [14] ,Receive word 14 mask" "Unmasked,Masked" bitfld.long 0x00 13. " [13] ,Receive word 13 mask" "Unmasked,Masked" bitfld.long 0x00 12. " [12] ,Receive word 12 mask" "Unmasked,Masked" newline bitfld.long 0x00 11. " [11] ,Receive word 11 mask" "Unmasked,Masked" bitfld.long 0x00 10. " [10] ,Receive word 10 mask" "Unmasked,Masked" bitfld.long 0x00 9. " [9] ,Receive word 9 mask" "Unmasked,Masked" bitfld.long 0x00 8. " [8] ,Receive word 8 mask" "Unmasked,Masked" newline bitfld.long 0x00 7. " [7] ,Receive word 7 mask" "Unmasked,Masked" bitfld.long 0x00 6. " [6] ,Receive word 6 mask" "Unmasked,Masked" bitfld.long 0x00 5. " [5] ,Receive word 5 mask" "Unmasked,Masked" bitfld.long 0x00 4. " [4] ,Receive word 4 mask" "Unmasked,Masked" newline bitfld.long 0x00 3. " [3] ,Receive word 3 mask" "Unmasked,Masked" bitfld.long 0x00 2. " [2] ,Receive word 2 mask" "Unmasked,Masked" bitfld.long 0x00 1. " [1] ,Receive word 1 mask" "Unmasked,Masked" bitfld.long 0x00 0. " [0] ,Receive word 0 mask" "Unmasked,Masked" width 0x0B tree.end tree "SAI3" base ad:0x59070000 width 6. if (((per.l(ad:0x59070000)&0x80000000)==0x80000000))&&(((per.l(ad:0x59070000)&0x40000)==0x00)) group.long 0x00++0x03 line.long 0x00 "TCSR,Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" newline eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled transmit FIFO empty)" "Not detected,Detected" rbitfld.long 0x00 16. " FRF ,FIFO request flag (Transmit FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "TCSR,Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" newline eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled transmit FIFO empty)" "Not detected,Detected" rbitfld.long 0x00 16. " FRF ,FIFO request flag (Transmit FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" endif group.long 0x04++0x03 line.long 0x00 "TCR1,Transmit Configuration 1 Register" bitfld.long 0x00 0.--5. " TFW ,Transmit FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0x59070000)&0x80000000)==0x00)) group.long 0x08++0x03 line.long 0x00 "TCR2,Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous with RX,Synchronous with SAI TX,Synchronous with SAI RX" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal logic clocked" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "High,Low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally slave mode,Internally master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" else rgroup.long 0x08++0x03 line.long 0x00 "TCR2,Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous with RX,Synchronous with SAI TX,Synchronous with SAI RX" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal logic clocked" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "High,Low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally slave mode,Internally master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" endif group.long 0x0C++0x03 line.long 0x00 "TCR3,Transmit Configuration 3 Register" bitfld.long 0x00 16. " TCE ,Transmit channel enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x59070000)&0x80000000)==0x00)) group.long 0x10++0x07 line.long 0x00 "TCR4,Transmit Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "From start,From error" bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode enable" "Disabled,,Enabled: 8 bit,Enabled: 16 bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,On FWF clear" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "High,Low" newline bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally slave mode,Internally master mode" line.long 0x04 "TCR5,Transmit Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" else rgroup.long 0x10++0x07 line.long 0x00 "TCR4,Transmit Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "From start,From error" bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode enable" "Disabled,,Enabled: 8 bit,Enabled: 16 bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,On FWF clear" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "High,Low" newline bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally slave mode,Internally master mode" line.long 0x04 "TCR5,Transmit Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" endif wgroup.long 0x20++0x03 line.long 0x00 "TDR0,Transmit Data Register 0" rgroup.long 0x40++0x03 line.long 0x00 "TFR0,Transmit FIFO Register 0" hexmask.long.byte 0x00 16.--22. 0x01 " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--6. 0x01 " RFP ,Read FIFO pointer" group.long 0x60++0x03 line.long 0x00 "TMR,Transmit Mask Register" bitfld.long 0x00 31. " TWM[31] ,Transmit word 31 mask" "Unmasked,Masked" bitfld.long 0x00 30. " [30] ,Transmit word 30 mask" "Unmasked,Masked" bitfld.long 0x00 29. " [29] ,Transmit word 29 mask" "Unmasked,Masked" bitfld.long 0x00 28. " [28] ,Transmit word 28 mask" "Unmasked,Masked" newline bitfld.long 0x00 27. " [27] ,Transmit word 27 mask" "Unmasked,Masked" bitfld.long 0x00 26. " [26] ,Transmit word 26 mask" "Unmasked,Masked" bitfld.long 0x00 25. " [25] ,Transmit word 25 mask" "Unmasked,Masked" bitfld.long 0x00 24. " [24] ,Transmit word 24 mask" "Unmasked,Masked" newline bitfld.long 0x00 23. " [23] ,Transmit word 23 mask" "Unmasked,Masked" bitfld.long 0x00 22. " [22] ,Transmit word 22 mask" "Unmasked,Masked" bitfld.long 0x00 21. " [21] ,Transmit word 21 mask" "Unmasked,Masked" bitfld.long 0x00 20. " [20] ,Transmit word 20 mask" "Unmasked,Masked" newline bitfld.long 0x00 19. " [19] ,Transmit word 19 mask" "Unmasked,Masked" bitfld.long 0x00 18. " [18] ,Transmit word 18 mask" "Unmasked,Masked" bitfld.long 0x00 17. " [17] ,Transmit word 17 mask" "Unmasked,Masked" bitfld.long 0x00 16. " [16] ,Transmit word 16 mask" "Unmasked,Masked" newline bitfld.long 0x00 15. " [15] ,Transmit word 15 mask" "Unmasked,Masked" bitfld.long 0x00 14. " [14] ,Transmit word 14 mask" "Unmasked,Masked" bitfld.long 0x00 13. " [13] ,Transmit word 13 mask" "Unmasked,Masked" bitfld.long 0x00 12. " [12] ,Transmit word 12 mask" "Unmasked,Masked" newline bitfld.long 0x00 11. " [11] ,Transmit word 11 mask" "Unmasked,Masked" bitfld.long 0x00 10. " [10] ,Transmit word 10 mask" "Unmasked,Masked" bitfld.long 0x00 9. " [9] ,Transmit word 9 mask" "Unmasked,Masked" bitfld.long 0x00 8. " [8] ,Transmit word 8 mask" "Unmasked,Masked" newline bitfld.long 0x00 7. " [7] ,Transmit word 7 mask" "Unmasked,Masked" bitfld.long 0x00 6. " [6] ,Transmit word 6 mask" "Unmasked,Masked" bitfld.long 0x00 5. " [5] ,Transmit word 5 mask" "Unmasked,Masked" bitfld.long 0x00 4. " [4] ,Transmit word 4 mask" "Unmasked,Masked" newline bitfld.long 0x00 3. " [3] ,Transmit word 3 mask" "Unmasked,Masked" bitfld.long 0x00 2. " [2] ,Transmit word 2 mask" "Unmasked,Masked" bitfld.long 0x00 1. " [1] ,Transmit word 1 mask" "Unmasked,Masked" bitfld.long 0x00 0. " [0] ,Transmit word 0 mask" "Unmasked,Masked" newline if (((per.l(ad:0x59070000+0x80)&0x80000000)==0x80000000))&&(((per.l(ad:0x59070000+0x80)&0x40000)==0x00)) group.long 0x80++0x03 line.long 0x00 "RCSR,Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" newline eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" bitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" bitfld.long 0x00 16. " FRF ,FIFO request flag (Receive FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "RCSR,Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" newline eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" bitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" bitfld.long 0x00 16. " FRF ,FIFO request flag (Receive FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "RCR1,Receive Configuration 1 Register" bitfld.long 0x00 0.--5. " RFW ,Receive FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0x59070000+0x80)&0x80000000)==0x00)) group.long 0x88++0x03 line.long 0x00 "RCR2,Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous with TX,Synchronous with SAI RX,Synchronous with SAI TX" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal logic clocked" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "High,Low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally in slave mode,Internally in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" else rgroup.long 0x88++0x03 line.long 0x00 "RCR2,Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous with TX,Synchronous with SAI RX,Synchronous with SAI TX" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal logic clocked" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "High,Low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally in slave mode,Internally in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" endif group.long 0x8C++0x03 line.long 0x00 "RCR3,Receive Configuration 3 Register" bitfld.long 0x00 16. " RCE ,Receive channel enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x59070000+0x80)&0x80000000)==0x00)) group.long 0x90++0x07 line.long 0x00 "RCR4,Receive Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "From start,From error" bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,Enabled: 8 bit,Enabled: 16 bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,On FWF clear" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "High,Low" newline bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally in slave mode,Internally in master mode" line.long 0x04 "RCR5,Receive Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" else rgroup.long 0x90++0x07 line.long 0x00 "RCR4,Receive Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "From start,From error" bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,Enabled: 8 bit,Enabled: 16 bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,On FWF clear" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "High,Low" newline bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally in slave mode,Internally in master mode" line.long 0x04 "RCR5,Receive Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" endif hgroup.long 0xA0++0x03 hide.long 0x00 "RDR0,Receive Data Register 0" in rgroup.long 0xC0++0x03 line.long 0x00 "RFR0,Receive FIFO Register 0" hexmask.long.byte 0x00 16.--22. 0x01 " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--6. 0x01 " RFP ,Read FIFO pointer" group.long 0xE0++0x03 line.long 0x00 "RMR,Receive Mask Register" bitfld.long 0x00 31. " RWM[31] ,Receive word 31 mask" "Unmasked,Masked" bitfld.long 0x00 30. " [30] ,Receive word 30 mask" "Unmasked,Masked" bitfld.long 0x00 29. " [29] ,Receive word 29 mask" "Unmasked,Masked" bitfld.long 0x00 28. " [28] ,Receive word 28 mask" "Unmasked,Masked" newline bitfld.long 0x00 27. " [27] ,Receive word 27 mask" "Unmasked,Masked" bitfld.long 0x00 26. " [26] ,Receive word 26 mask" "Unmasked,Masked" bitfld.long 0x00 25. " [25] ,Receive word 25 mask" "Unmasked,Masked" bitfld.long 0x00 24. " [24] ,Receive word 24 mask" "Unmasked,Masked" newline bitfld.long 0x00 23. " [23] ,Receive word 23 mask" "Unmasked,Masked" bitfld.long 0x00 22. " [22] ,Receive word 22 mask" "Unmasked,Masked" bitfld.long 0x00 21. " [21] ,Receive word 21 mask" "Unmasked,Masked" bitfld.long 0x00 20. " [20] ,Receive word 20 mask" "Unmasked,Masked" newline bitfld.long 0x00 19. " [19] ,Receive word 19 mask" "Unmasked,Masked" bitfld.long 0x00 18. " [18] ,Receive word 18 mask" "Unmasked,Masked" bitfld.long 0x00 17. " [17] ,Receive word 17 mask" "Unmasked,Masked" bitfld.long 0x00 16. " [16] ,Receive word 16 mask" "Unmasked,Masked" newline bitfld.long 0x00 15. " [15] ,Receive word 15 mask" "Unmasked,Masked" bitfld.long 0x00 14. " [14] ,Receive word 14 mask" "Unmasked,Masked" bitfld.long 0x00 13. " [13] ,Receive word 13 mask" "Unmasked,Masked" bitfld.long 0x00 12. " [12] ,Receive word 12 mask" "Unmasked,Masked" newline bitfld.long 0x00 11. " [11] ,Receive word 11 mask" "Unmasked,Masked" bitfld.long 0x00 10. " [10] ,Receive word 10 mask" "Unmasked,Masked" bitfld.long 0x00 9. " [9] ,Receive word 9 mask" "Unmasked,Masked" bitfld.long 0x00 8. " [8] ,Receive word 8 mask" "Unmasked,Masked" newline bitfld.long 0x00 7. " [7] ,Receive word 7 mask" "Unmasked,Masked" bitfld.long 0x00 6. " [6] ,Receive word 6 mask" "Unmasked,Masked" bitfld.long 0x00 5. " [5] ,Receive word 5 mask" "Unmasked,Masked" bitfld.long 0x00 4. " [4] ,Receive word 4 mask" "Unmasked,Masked" newline bitfld.long 0x00 3. " [3] ,Receive word 3 mask" "Unmasked,Masked" bitfld.long 0x00 2. " [2] ,Receive word 2 mask" "Unmasked,Masked" bitfld.long 0x00 1. " [1] ,Receive word 1 mask" "Unmasked,Masked" bitfld.long 0x00 0. " [0] ,Receive word 0 mask" "Unmasked,Masked" width 0x0B tree.end tree "SAI4" base ad:0x59820000 width 6. if (((per.l(ad:0x59820000)&0x80000000)==0x80000000))&&(((per.l(ad:0x59820000)&0x40000)==0x00)) group.long 0x00++0x03 line.long 0x00 "TCSR,Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" newline eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled transmit FIFO empty)" "Not detected,Detected" rbitfld.long 0x00 16. " FRF ,FIFO request flag (Transmit FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "TCSR,Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" newline eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled transmit FIFO empty)" "Not detected,Detected" rbitfld.long 0x00 16. " FRF ,FIFO request flag (Transmit FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" endif group.long 0x04++0x03 line.long 0x00 "TCR1,Transmit Configuration 1 Register" bitfld.long 0x00 0.--5. " TFW ,Transmit FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0x59820000)&0x80000000)==0x00)) group.long 0x08++0x03 line.long 0x00 "TCR2,Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous with RX,Synchronous with SAI TX,Synchronous with SAI RX" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal logic clocked" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "High,Low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally slave mode,Internally master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" else rgroup.long 0x08++0x03 line.long 0x00 "TCR2,Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous with RX,Synchronous with SAI TX,Synchronous with SAI RX" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal logic clocked" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "High,Low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally slave mode,Internally master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" endif group.long 0x0C++0x03 line.long 0x00 "TCR3,Transmit Configuration 3 Register" bitfld.long 0x00 16. " TCE ,Transmit channel enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7" if (((per.l(ad:0x59820000)&0x80000000)==0x00)) group.long 0x10++0x07 line.long 0x00 "TCR4,Transmit Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "From start,From error" bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode enable" "Disabled,,Enabled: 8 bit,Enabled: 16 bit" bitfld.long 0x00 16.--18. " FRSZ ,Frame size" "0,1,2,3,4,5,6,7" textfld " " bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,On FWF clear" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "High,Low" newline bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally slave mode,Internally master mode" line.long 0x04 "TCR5,Transmit Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" else rgroup.long 0x10++0x07 line.long 0x00 "TCR4,Transmit Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "From start,From error" bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode enable" "Disabled,,Enabled: 8 bit,Enabled: 16 bit" bitfld.long 0x00 16.--18. " FRSZ ,Frame size" "0,1,2,3,4,5,6,7" textfld " " bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,On FWF clear" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "High,Low" newline bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally slave mode,Internally master mode" line.long 0x04 "TCR5,Transmit Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" endif wgroup.long 0x20++0x03 line.long 0x00 "TDR0,Transmit Data Register 0" rgroup.long 0x40++0x03 line.long 0x00 "TFR0,Transmit FIFO Register 0" hexmask.long.byte 0x00 16.--22. 0x01 " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--6. 0x01 " RFP ,Read FIFO pointer" group.long 0x60++0x03 line.long 0x00 "TMR,Transmit Mask Register" bitfld.long 0x00 7. " TWM[7] ,Transmit word 7 mask" "Unmasked,Masked" bitfld.long 0x00 6. " [6] ,Transmit word 6 mask" "Unmasked,Masked" bitfld.long 0x00 5. " [5] ,Transmit word 5 mask" "Unmasked,Masked" bitfld.long 0x00 4. " [4] ,Transmit word 4 mask" "Unmasked,Masked" newline bitfld.long 0x00 3. " [3] ,Transmit word 3 mask" "Unmasked,Masked" bitfld.long 0x00 2. " [2] ,Transmit word 2 mask" "Unmasked,Masked" bitfld.long 0x00 1. " [1] ,Transmit word 1 mask" "Unmasked,Masked" bitfld.long 0x00 0. " [0] ,Transmit word 0 mask" "Unmasked,Masked" newline if (((per.l(ad:0x59820000+0x80)&0x80000000)==0x80000000))&&(((per.l(ad:0x59820000+0x80)&0x40000)==0x00)) group.long 0x80++0x03 line.long 0x00 "RCSR,Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" newline eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" bitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" bitfld.long 0x00 16. " FRF ,FIFO request flag (Receive FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "RCSR,Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" newline eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" bitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" bitfld.long 0x00 16. " FRF ,FIFO request flag (Receive FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "RCR1,Receive Configuration 1 Register" bitfld.long 0x00 0.--5. " RFW ,Receive FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0x59820000+0x80)&0x80000000)==0x00)) group.long 0x88++0x03 line.long 0x00 "RCR2,Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous with TX,Synchronous with SAI RX,Synchronous with SAI TX" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal logic clocked" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "High,Low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally in slave mode,Internally in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" else rgroup.long 0x88++0x03 line.long 0x00 "RCR2,Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous with TX,Synchronous with SAI RX,Synchronous with SAI TX" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal logic clocked" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "High,Low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally in slave mode,Internally in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" endif group.long 0x8C++0x03 line.long 0x00 "RCR3,Receive Configuration 3 Register" bitfld.long 0x00 16. " RCE ,Receive channel enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7" if (((per.l(ad:0x59820000+0x80)&0x80000000)==0x00)) group.long 0x90++0x07 line.long 0x00 "RCR4,Receive Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "From start,From error" bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,Enabled: 8 bit,Enabled: 16 bit" bitfld.long 0x00 16.--18. " FRSZ ,Frame size" "0,1,2,3,4,5,6,7" textfld " " bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,On FWF clear" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "High,Low" newline bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally in slave mode,Internally in master mode" line.long 0x04 "RCR5,Receive Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" else rgroup.long 0x90++0x07 line.long 0x00 "RCR4,Receive Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "From start,From error" bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,Enabled: 8 bit,Enabled: 16 bit" bitfld.long 0x00 16.--18. " FRSZ ,Frame size" "0,1,2,3,4,5,6,7" textfld " " bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,On FWF clear" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "High,Low" newline bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally in slave mode,Internally in master mode" line.long 0x04 "RCR5,Receive Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" endif hgroup.long 0xA0++0x03 hide.long 0x00 "RDR0,Receive Data Register 0" in rgroup.long 0xC0++0x03 line.long 0x00 "RFR0,Receive FIFO Register 0" hexmask.long.byte 0x00 16.--22. 0x01 " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--6. 0x01 " RFP ,Read FIFO pointer" group.long 0xE0++0x03 line.long 0x00 "RMR,Receive Mask Register" bitfld.long 0x00 7. " RWM[7] ,Receive word 7 mask" "Unmasked,Masked" bitfld.long 0x00 6. " [6] ,Receive word 6 mask" "Unmasked,Masked" bitfld.long 0x00 5. " [5] ,Receive word 5 mask" "Unmasked,Masked" bitfld.long 0x00 4. " [4] ,Receive word 4 mask" "Unmasked,Masked" newline bitfld.long 0x00 3. " [3] ,Receive word 3 mask" "Unmasked,Masked" bitfld.long 0x00 2. " [2] ,Receive word 2 mask" "Unmasked,Masked" bitfld.long 0x00 1. " [1] ,Receive word 1 mask" "Unmasked,Masked" bitfld.long 0x00 0. " [0] ,Receive word 0 mask" "Unmasked,Masked" width 0x0B tree.end tree "SAI5" base ad:0x59830000 width 6. if (((per.l(ad:0x59830000)&0x80000000)==0x80000000))&&(((per.l(ad:0x59830000)&0x40000)==0x00)) group.long 0x00++0x03 line.long 0x00 "TCSR,Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" newline eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled transmit FIFO empty)" "Not detected,Detected" rbitfld.long 0x00 16. " FRF ,FIFO request flag (Transmit FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "TCSR,Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" newline eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" rbitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled transmit FIFO empty)" "Not detected,Detected" rbitfld.long 0x00 16. " FRF ,FIFO request flag (Transmit FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" endif group.long 0x04++0x03 line.long 0x00 "TCR1,Transmit Configuration 1 Register" bitfld.long 0x00 0.--5. " TFW ,Transmit FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0x59830000)&0x80000000)==0x00)) group.long 0x08++0x03 line.long 0x00 "TCR2,Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous with RX,Synchronous with SAI TX,Synchronous with SAI RX" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal logic clocked" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "High,Low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally slave mode,Internally master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" else rgroup.long 0x08++0x03 line.long 0x00 "TCR2,Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous with RX,Synchronous with SAI TX,Synchronous with SAI RX" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal logic clocked" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "High,Low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally slave mode,Internally master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" endif group.long 0x0C++0x03 line.long 0x00 "TCR3,Transmit Configuration 3 Register" bitfld.long 0x00 16. " TCE ,Transmit channel enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7" if (((per.l(ad:0x59830000)&0x80000000)==0x00)) group.long 0x10++0x07 line.long 0x00 "TCR4,Transmit Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "From start,From error" bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode enable" "Disabled,,Enabled: 8 bit,Enabled: 16 bit" bitfld.long 0x00 16.--18. " FRSZ ,Frame size" "0,1,2,3,4,5,6,7" textfld " " bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,On FWF clear" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "High,Low" newline bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally slave mode,Internally master mode" line.long 0x04 "TCR5,Transmit Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" else rgroup.long 0x10++0x07 line.long 0x00 "TCR4,Transmit Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "From start,From error" bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode enable" "Disabled,,Enabled: 8 bit,Enabled: 16 bit" bitfld.long 0x00 16.--18. " FRSZ ,Frame size" "0,1,2,3,4,5,6,7" textfld " " bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,On FWF clear" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "High,Low" newline bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally slave mode,Internally master mode" line.long 0x04 "TCR5,Transmit Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" endif wgroup.long 0x20++0x03 line.long 0x00 "TDR0,Transmit Data Register 0" rgroup.long 0x40++0x03 line.long 0x00 "TFR0,Transmit FIFO Register 0" hexmask.long.byte 0x00 16.--22. 0x01 " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--6. 0x01 " RFP ,Read FIFO pointer" group.long 0x60++0x03 line.long 0x00 "TMR,Transmit Mask Register" bitfld.long 0x00 7. " TWM[7] ,Transmit word 7 mask" "Unmasked,Masked" bitfld.long 0x00 6. " [6] ,Transmit word 6 mask" "Unmasked,Masked" bitfld.long 0x00 5. " [5] ,Transmit word 5 mask" "Unmasked,Masked" bitfld.long 0x00 4. " [4] ,Transmit word 4 mask" "Unmasked,Masked" newline bitfld.long 0x00 3. " [3] ,Transmit word 3 mask" "Unmasked,Masked" bitfld.long 0x00 2. " [2] ,Transmit word 2 mask" "Unmasked,Masked" bitfld.long 0x00 1. " [1] ,Transmit word 1 mask" "Unmasked,Masked" bitfld.long 0x00 0. " [0] ,Transmit word 0 mask" "Unmasked,Masked" newline if (((per.l(ad:0x59830000+0x80)&0x80000000)==0x80000000))&&(((per.l(ad:0x59830000+0x80)&0x40000)==0x00)) group.long 0x80++0x03 line.long 0x00 "RCSR,Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" newline eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" bitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" bitfld.long 0x00 16. " FRF ,FIFO request flag (Receive FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "RCSR,Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not detected,Detected" eventfld.long 0x00 19. " SEF ,Sync error flag" "Not detected,Detected" newline eventfld.long 0x00 18. " FEF ,FIFO error flag" "Not detected,Detected" bitfld.long 0x00 17. " FWF ,FIFO warning flag (Enabled receive FIFO full)" "Not detected,Detected" bitfld.long 0x00 16. " FRF ,FIFO request flag (Receive FIFO watermark reached)" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "RCR1,Receive Configuration 1 Register" bitfld.long 0x00 0.--5. " RFW ,Receive FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0x59830000+0x80)&0x80000000)==0x00)) group.long 0x88++0x03 line.long 0x00 "RCR2,Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous with TX,Synchronous with SAI RX,Synchronous with SAI TX" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal logic clocked" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "High,Low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally in slave mode,Internally in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" else rgroup.long 0x88++0x03 line.long 0x00 "RCR2,Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous with TX,Synchronous with SAI RX,Synchronous with SAI TX" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Not swapped,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal logic clocked" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,MCLK 1,MCLK 2,MCLK 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "High,Low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "Externally in slave mode,Internally in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" endif group.long 0x8C++0x03 line.long 0x00 "RCR3,Receive Configuration 3 Register" bitfld.long 0x00 16. " RCE ,Receive channel enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7" if (((per.l(ad:0x59830000+0x80)&0x80000000)==0x00)) group.long 0x90++0x07 line.long 0x00 "RCR4,Receive Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "From start,From error" bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,Enabled: 8 bit,Enabled: 16 bit" bitfld.long 0x00 16.--18. " FRSZ ,Frame size" "0,1,2,3,4,5,6,7" textfld " " bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,On FWF clear" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "High,Low" newline bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally in slave mode,Internally in master mode" line.long 0x04 "RCR5,Receive Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" else rgroup.long 0x90++0x07 line.long 0x00 "RCR4,Receive Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "From start,From error" bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,Enabled: 8 bit,Enabled: 16 bit" bitfld.long 0x00 16.--18. " FRSZ ,Frame size" "0,1,2,3,4,5,6,7" textfld " " bitfld.long 0x00 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 4. " MF ,MSB first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync early enable" "Disabled,Enabled" bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,On FWF clear" bitfld.long 0x00 1. " FSP ,Frame sync polarity" "High,Low" newline bitfld.long 0x00 0. " FSD ,Frame sync direction" "Externally in slave mode,Internally in master mode" line.long 0x04 "RCR5,Receive Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" endif hgroup.long 0xA0++0x03 hide.long 0x00 "RDR0,Receive Data Register 0" in rgroup.long 0xC0++0x03 line.long 0x00 "RFR0,Receive FIFO Register 0" hexmask.long.byte 0x00 16.--22. 0x01 " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--6. 0x01 " RFP ,Read FIFO pointer" group.long 0xE0++0x03 line.long 0x00 "RMR,Receive Mask Register" bitfld.long 0x00 7. " RWM[7] ,Receive word 7 mask" "Unmasked,Masked" bitfld.long 0x00 6. " [6] ,Receive word 6 mask" "Unmasked,Masked" bitfld.long 0x00 5. " [5] ,Receive word 5 mask" "Unmasked,Masked" bitfld.long 0x00 4. " [4] ,Receive word 4 mask" "Unmasked,Masked" newline bitfld.long 0x00 3. " [3] ,Receive word 3 mask" "Unmasked,Masked" bitfld.long 0x00 2. " [2] ,Receive word 2 mask" "Unmasked,Masked" bitfld.long 0x00 1. " [1] ,Receive word 1 mask" "Unmasked,Masked" bitfld.long 0x00 0. " [0] ,Receive word 0 mask" "Unmasked,Masked" width 0x0B tree.end tree.end tree "SPDIF (Sony/Philips Digital interface)" base ad:0x59020000 width 8. group.long 0x00++0x0F line.long 0x00 "SCR,SPDIF Configuration Register" bitfld.long 0x00 23. " RXFIFO_CTRL ,Rx FIFO control" "Normal,Always read zero" bitfld.long 0x00 22. " RXFIFO_OFF_ON ,SPDIF Rx FIFO on/off" "On,Off" newline bitfld.long 0x00 21. " RXFIFO_RST ,Rx FIFO reset" "Normal,Reset" bitfld.long 0x00 19.--20. " RXFIFOFULL_SEL ,Rx FIFO full interrupt select" "1,4,8,16" newline bitfld.long 0x00 18. " RXAUTOSYNC ,Rx auto sync off/on" "Off,On" bitfld.long 0x00 17. " TXAUTOSYNC ,Tx auto sync off/on" "Off,On" newline bitfld.long 0x00 15.--16. " TXFIFOEMPTY_SEL ,Tx FIFO empty interrupt select" "0,4,8,12" bitfld.long 0x00 13. " LOW_POWER ,SPDIF low-power mode enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " SOFT_RESET ,SPDIF software reset" "No reset,Reset" bitfld.long 0x00 10.--11. " TXFIFO_CTRL ,Tx FIFO control" "Digital zero,Normal,Reset,?..." newline bitfld.long 0x00 9. " DMA_RX_EN ,DMA receive request enable" "Disabled,Enabled" bitfld.long 0x00 8. " DMA_TX_EN ,DMA transmit request enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " VALCTRL ,Outgoing validity set/clear control" "Set,Clear" bitfld.long 0x00 2.--4. " TXSEL ,Tx select" "Off,SPDIFIN,,,,Normal,?..." newline bitfld.long 0x00 0.--1. " USRC_SEL ,USRC select" "No embedded,SPDIF,,Chip transmitter" line.long 0x04 "SRCD,CDText Control Register" bitfld.long 0x04 1. " USYNCMODE ,U sync mode" "Non-CD,CD" line.long 0x08 "SRPC,PhaseConfig Register" bitfld.long 0x08 7.--10. " CLKSRC_SEL ,Clock source selection" "ACM,?..." rbitfld.long 0x08 6. " LOCK ,DPLL lock" "Unlocked,Locked" bitfld.long 0x08 3.--5. " GAINSEL ,Gain selection" "24*(2**10),16*(2**10),12*(2**10),8*(2**10),6*(2**10),4*(2**10),3*(2**10),?..." line.long 0x0C "SIE,Interrupt Enable Register" bitfld.long 0x0C 20. " LOCK ,SPDIF receiver's DPLL lock interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 19. " TXUNOV ,SPDIF Tx FIFO under/overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 18. " TXRESYN ,SPDIF Tx FIFO resync interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 17. " CNEW ,SPDIF receive change in value of control channel interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 16. " VALNOGOOD ,SPDIF validity flag no good interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 15. " SYMERR ,SPDIF receiver found illegal symbol interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 14. " BITERR ,SPDIF receiver found parity bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 10. " URXFUL ,U channel receive register full" "Not full,Full" newline bitfld.long 0x0C 9. " URXOV ,U channel receive register overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 8. " QRXFUL ,Q channel receive register full" "Not full,Full" bitfld.long 0x0C 7. " QRXOV ,Q channel receive register overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 6. " UQSYNC ,U/Q channel sync found interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 5. " UQERR ,U/Q channel framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " RXFIFOUNOV ,Rx FIFO underrun/overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " RXFIFORESYN ,Rx FIFO resync interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 2. " LOCKLOSS ,SPDIF receiver loss of lock interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 1. " TXEM ,SPDIF Tx FIFO empty" "Not empty,Empty" bitfld.long 0x0C 0. " RXFIFOFUL ,SPDIF Rx FIFO full" "Not full,Full" wgroup.long 0x10++0x03 line.long 0x00 "SIC,Interrupt Clear Register" bitfld.long 0x00 20. " LOCK ,SPDIF receiver's DPLL lock interrupt clear" "No clear,Clear" bitfld.long 0x00 19. " TXUNOV ,SPDIF Tx FIFO under/overrun interrupt status" "No clear,Clear" bitfld.long 0x00 18. " TXRESYN ,SPDIF Tx FIFO resync interrupt status" "No clear,Clear" bitfld.long 0x00 17. " CNEW ,SPDIF receive change in value of control channel interrupt status" "No clear,Clear" newline bitfld.long 0x00 16. " VALNOGOOD ,SPDIF validity flag no good interrupt status" "No clear,Clear" bitfld.long 0x00 15. " SYMERR ,SPDIF receiver found illegal symbol interrupt status" "No clear,Clear" bitfld.long 0x00 14. " BITERR ,SPDIF receiver found parity bit error interrupt status" "No clear,Clear" bitfld.long 0x00 9. " URXOV ,U channel receive register overrun interrupt status" "No clear,Clear" newline bitfld.long 0x00 7. " QRXOV ,Q channel receive register overrun interrupt status" "No clear,Clear" bitfld.long 0x00 6. " UQSYNC ,U/Q channel sync found interrupt status" "No clear,Clear" bitfld.long 0x00 5. " UQERR ,U/Q channel framing error interrupt status" "No clear,Clear" bitfld.long 0x00 4. " RXFIFOUNOV ,Rx FIFO underrun/overrun interrupt status" "No clear,Clear" newline bitfld.long 0x00 3. " RXFIFORESYN ,Rx FIFO resync interrupt status" "No clear,Clear" bitfld.long 0x00 2. " LOCKLOSS ,SPDIF receiver loss of lock interrupt status" "No clear,Clear" rgroup.long 0x10++0x03 line.long 0x00 "SIS,Interrupt Stat Register" bitfld.long 0x00 20. " LOCK ,SPDIF receiver's DPLL lock interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 19. " TXUNOV ,SPDIF Tx FIFO under/overrun interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 18. " TXRESYN ,SPDIF Tx FIFO resync interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 17. " CNEW ,SPDIF receive change in value of control channel interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x00 16. " VALNOGOOD ,SPDIF validity flag no good interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 15. " SYMERR ,SPDIF receiver found illegal symbol interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 14. " BITERR ,SPDIF receiver found parity bit error interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 10. " URXFUL ,U channel receive register full" "Not full,Full" newline bitfld.long 0x00 9. " URXOV ,U channel receive register overrun interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 8. " QRXFUL ,Q channel receive register full" "Not full,Full" bitfld.long 0x00 7. " QRXOV ,Q channel receive register overrun interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 6. " UQSYNC ,U/Q channel sync found interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x00 5. " UQERR ,U/Q channel framing error interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 4. " RXFIFOUNOV ,Rx FIFO underrun/overrun interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 3. " RXFIFORESYN ,Rx FIFO resync interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 2. " LOCKLOSS ,SPDIF receiver loss of lock interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x00 1. " TXEM ,SPDIF Tx FIFO empty" "Not empty,Empty" bitfld.long 0x00 0. " RXFIFOFUL ,SPDIF Rx FIFO full" "Not full,Full" rgroup.long 0x14++0x17 line.long 0x00 "SRL,SPDIFRxLeft Register" hexmask.long.tbyte 0x00 0.--23. 1. " RXDATALEFT ,Processor receive SPDIF data left" line.long 0x04 "SRR,SPDIFRxRight Register" hexmask.long.tbyte 0x04 0.--23. 1. " RXDATARIGHT ,Processor receive SPDIF data right" line.long 0x08 "SRCSH,SPDIFRxCChannel_h Register" hexmask.long.tbyte 0x08 0.--23. 1. " RXCCHANNEL_H ,SPDIF receive C channel register contains first 24 bits of C channel without interpretation" line.long 0x0C "SRCSL,SPDIFRxCChannel_l Register" hexmask.long.tbyte 0x0C 0.--23. 1. " RXCCHANNEL_L ,SPDIF receive C channel register contains next 24 bits of C channel without interpretation" line.long 0x10 "SRU,UchannelRx Register" hexmask.long.tbyte 0x10 0.--23. 1. " RXUCHANNEL ,SPDIF receive U channel register contains next 3 U channel bytes" line.long 0x14 "SRQ,QchannelRx Register" hexmask.long.tbyte 0x14 0.--23. 1. " RXQCHANNEL ,SPDIF receive Q channel register contains next 3 Q channel bytes" wgroup.long 0x2C++0x07 line.long 0x00 "STL,SPDIFTxLeft Register" hexmask.long.tbyte 0x00 0.--23. 1. " TXDATALEFT ,SPDIF transmit left channel data" line.long 0x04 "STR,SPDIFTxRight Register" hexmask.long.tbyte 0x04 0.--23. 1. " TXDATARIGHT ,SPDIF transmit right channel data" group.long 0x34++0x07 line.long 0x00 "STCSCH,SPDIFTxCChannelCons_h Register" hexmask.long.tbyte 0x00 0.--23. 1. " TXCCHANNELCONS_H ,SPDIF transmit cons. C channel data contains first 24 bits without interpretation" line.long 0x04 "STCSCL,SPDIFTxCChannelCons_l Register" hexmask.long.tbyte 0x04 0.--23. 1. " TXCCHANNELCONS_L ,SPDIF transmit cons. C channel data contains next 24 bits without interpretation" rgroup.long 0x44++0x03 line.long 0x00 "SRFM,FreqMeas Register" hexmask.long.tbyte 0x00 0.--23. 1. " FREQMEAS ,Frequency measurement data" group.long 0x50++0x03 line.long 0x00 "STC,SPDIFTxClk Register" hexmask.long.word 0x00 11.--19. 1. " SYSCLK_DF ,System clock divider factor" bitfld.long 0x00 8.--10. " TXCLK_SOURCE ,Tx clock source" "ACM,?..." bitfld.long 0x00 7. " TX_ALL_CLK_EN ,SPDIF transfer clock enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--6. 1. " TXCLK_DF ,Divider factor" width 0x0B tree.end tree.open "GPT (General Purpose Timer)" tree "GPT0" base ad:0x590B0000 width 6. group.long 0x00++0x1B line.long 0x00 "CR,Control Register" bitfld.long 0x00 31. " FO3 ,Force output compare channel 3" "No effect,Force" bitfld.long 0x00 30. " FO2 ,Force output compare channel 2" "No effect,Force" bitfld.long 0x00 29. " FO1 ,Force output compare channel 1" "No effect,Force" bitfld.long 0x00 26.--28. " OM3 ,Output compare channel 3 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" newline bitfld.long 0x00 23.--25. " OM2 ,Output compare channel 2 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 20.--22. " OM1 ,Output compare channel 1 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 18.--19. " IM2 ,Input capture channel 2 operating mode" "Disabled,Rising,Falling,Both edges" bitfld.long 0x00 16.--17. " IM1 ,Input capture channel 1 operating mode" "Disabled,Rising,Falling,Both edges" newline bitfld.long 0x00 15. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 10. " EN_24M ,Enable 24MHz clock input from crystal" "Disabled,Enabled" bitfld.long 0x00 9. " FRR ,Free-run or restart mode" "Restart,Free-Run" bitfld.long 0x00 6.--8. " CLKSRC ,Clock source select" "No clock,Peripheral,High Freq,External,Low Freq,Crystal,?..." newline bitfld.long 0x00 5. " STOPEN ,GPT stop mode" "Disabled,Enabled" bitfld.long 0x00 4. " DOZEEN ,GPT doze mode" "Disabled,Enabled" bitfld.long 0x00 3. " WAITEN ,GPT wait mode enable" "Disabled,Enabled" bitfld.long 0x00 2. " DBGEN ,GPT debug mode enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " ENMOD ,GPT enable mode (main counter value)" "Freeze,Reset" bitfld.long 0x00 0. " EN ,GPT enable" "Disabled,Enabled" line.long 0x04 "PR,Prescaler Register" bitfld.long 0x04 12.--15. " PRESCALER24M ,24 MHz crystal clock prescaler division value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" hexmask.long.word 0x04 0.--11. 1. " PRESCALER ,Clock division coefficient" line.long 0x08 "SR,Status Register" eventfld.long 0x08 5. " ROV ,Rollover flag" "Not occurred,Occurred" eventfld.long 0x08 4. " IF2 ,Input capture 2 flag" "Not occurred,Occurred" eventfld.long 0x08 3. " IF1 ,Input capture 1 flag" "Not occurred,Occurred" eventfld.long 0x08 2. " OF3 ,Output compare 3 flag" "Not occurred,Occurred" newline eventfld.long 0x08 1. " OF2 ,Output compare 2 flag" "Not occurred,Occurred" eventfld.long 0x08 0. " OF1 ,Output compare 1 flag" "Not occurred,Occurred" line.long 0x0C "IR,Interrupt Register" bitfld.long 0x0C 5. " ROVIE ,Rollover interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " IF2IE ,Input capture 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " IF1IE ,Input capture 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 2. " OF3IE ,Output compare 3 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 1. " OF2IE ,Output compare 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " OF1IE ,Output compare 1 interrupt enable" "Disabled,Enabled" line.long 0x10 "OCR1,Output Compare Register 1" line.long 0x14 "OCR2,Output Compare Register 2" line.long 0x18 "OCR3,Output Compare Register 3" rgroup.long 0x1C++0x0B line.long 0x00 "ICR1,Input Compare Register 1" line.long 0x04 "ICR2,Input Compare Register 2" line.long 0x08 "CNT,Counter Register" width 0x0B tree.end tree "GPT1" base ad:0x590C0000 width 6. group.long 0x00++0x1B line.long 0x00 "CR,Control Register" bitfld.long 0x00 31. " FO3 ,Force output compare channel 3" "No effect,Force" bitfld.long 0x00 30. " FO2 ,Force output compare channel 2" "No effect,Force" bitfld.long 0x00 29. " FO1 ,Force output compare channel 1" "No effect,Force" bitfld.long 0x00 26.--28. " OM3 ,Output compare channel 3 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" newline bitfld.long 0x00 23.--25. " OM2 ,Output compare channel 2 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 20.--22. " OM1 ,Output compare channel 1 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 18.--19. " IM2 ,Input capture channel 2 operating mode" "Disabled,Rising,Falling,Both edges" bitfld.long 0x00 16.--17. " IM1 ,Input capture channel 1 operating mode" "Disabled,Rising,Falling,Both edges" newline bitfld.long 0x00 15. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 10. " EN_24M ,Enable 24MHz clock input from crystal" "Disabled,Enabled" bitfld.long 0x00 9. " FRR ,Free-run or restart mode" "Restart,Free-Run" bitfld.long 0x00 6.--8. " CLKSRC ,Clock source select" "No clock,Peripheral,High Freq,External,Low Freq,Crystal,?..." newline bitfld.long 0x00 5. " STOPEN ,GPT stop mode" "Disabled,Enabled" bitfld.long 0x00 4. " DOZEEN ,GPT doze mode" "Disabled,Enabled" bitfld.long 0x00 3. " WAITEN ,GPT wait mode enable" "Disabled,Enabled" bitfld.long 0x00 2. " DBGEN ,GPT debug mode enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " ENMOD ,GPT enable mode (main counter value)" "Freeze,Reset" bitfld.long 0x00 0. " EN ,GPT enable" "Disabled,Enabled" line.long 0x04 "PR,Prescaler Register" bitfld.long 0x04 12.--15. " PRESCALER24M ,24 MHz crystal clock prescaler division value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" hexmask.long.word 0x04 0.--11. 1. " PRESCALER ,Clock division coefficient" line.long 0x08 "SR,Status Register" eventfld.long 0x08 5. " ROV ,Rollover flag" "Not occurred,Occurred" eventfld.long 0x08 4. " IF2 ,Input capture 2 flag" "Not occurred,Occurred" eventfld.long 0x08 3. " IF1 ,Input capture 1 flag" "Not occurred,Occurred" eventfld.long 0x08 2. " OF3 ,Output compare 3 flag" "Not occurred,Occurred" newline eventfld.long 0x08 1. " OF2 ,Output compare 2 flag" "Not occurred,Occurred" eventfld.long 0x08 0. " OF1 ,Output compare 1 flag" "Not occurred,Occurred" line.long 0x0C "IR,Interrupt Register" bitfld.long 0x0C 5. " ROVIE ,Rollover interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " IF2IE ,Input capture 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " IF1IE ,Input capture 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 2. " OF3IE ,Output compare 3 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 1. " OF2IE ,Output compare 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " OF1IE ,Output compare 1 interrupt enable" "Disabled,Enabled" line.long 0x10 "OCR1,Output Compare Register 1" line.long 0x14 "OCR2,Output Compare Register 2" line.long 0x18 "OCR3,Output Compare Register 3" rgroup.long 0x1C++0x0B line.long 0x00 "ICR1,Input Compare Register 1" line.long 0x04 "ICR2,Input Compare Register 2" line.long 0x08 "CNT,Counter Register" width 0x0B tree.end tree "GPT2" base ad:0x590D0000 width 6. group.long 0x00++0x1B line.long 0x00 "CR,Control Register" bitfld.long 0x00 31. " FO3 ,Force output compare channel 3" "No effect,Force" bitfld.long 0x00 30. " FO2 ,Force output compare channel 2" "No effect,Force" bitfld.long 0x00 29. " FO1 ,Force output compare channel 1" "No effect,Force" bitfld.long 0x00 26.--28. " OM3 ,Output compare channel 3 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" newline bitfld.long 0x00 23.--25. " OM2 ,Output compare channel 2 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 20.--22. " OM1 ,Output compare channel 1 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 18.--19. " IM2 ,Input capture channel 2 operating mode" "Disabled,Rising,Falling,Both edges" bitfld.long 0x00 16.--17. " IM1 ,Input capture channel 1 operating mode" "Disabled,Rising,Falling,Both edges" newline bitfld.long 0x00 15. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 10. " EN_24M ,Enable 24MHz clock input from crystal" "Disabled,Enabled" bitfld.long 0x00 9. " FRR ,Free-run or restart mode" "Restart,Free-Run" bitfld.long 0x00 6.--8. " CLKSRC ,Clock source select" "No clock,Peripheral,High Freq,External,Low Freq,Crystal,?..." newline bitfld.long 0x00 5. " STOPEN ,GPT stop mode" "Disabled,Enabled" bitfld.long 0x00 4. " DOZEEN ,GPT doze mode" "Disabled,Enabled" bitfld.long 0x00 3. " WAITEN ,GPT wait mode enable" "Disabled,Enabled" bitfld.long 0x00 2. " DBGEN ,GPT debug mode enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " ENMOD ,GPT enable mode (main counter value)" "Freeze,Reset" bitfld.long 0x00 0. " EN ,GPT enable" "Disabled,Enabled" line.long 0x04 "PR,Prescaler Register" bitfld.long 0x04 12.--15. " PRESCALER24M ,24 MHz crystal clock prescaler division value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" hexmask.long.word 0x04 0.--11. 1. " PRESCALER ,Clock division coefficient" line.long 0x08 "SR,Status Register" eventfld.long 0x08 5. " ROV ,Rollover flag" "Not occurred,Occurred" eventfld.long 0x08 4. " IF2 ,Input capture 2 flag" "Not occurred,Occurred" eventfld.long 0x08 3. " IF1 ,Input capture 1 flag" "Not occurred,Occurred" eventfld.long 0x08 2. " OF3 ,Output compare 3 flag" "Not occurred,Occurred" newline eventfld.long 0x08 1. " OF2 ,Output compare 2 flag" "Not occurred,Occurred" eventfld.long 0x08 0. " OF1 ,Output compare 1 flag" "Not occurred,Occurred" line.long 0x0C "IR,Interrupt Register" bitfld.long 0x0C 5. " ROVIE ,Rollover interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " IF2IE ,Input capture 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " IF1IE ,Input capture 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 2. " OF3IE ,Output compare 3 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 1. " OF2IE ,Output compare 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " OF1IE ,Output compare 1 interrupt enable" "Disabled,Enabled" line.long 0x10 "OCR1,Output Compare Register 1" line.long 0x14 "OCR2,Output Compare Register 2" line.long 0x18 "OCR3,Output Compare Register 3" rgroup.long 0x1C++0x0B line.long 0x00 "ICR1,Input Compare Register 1" line.long 0x04 "ICR2,Input Compare Register 2" line.long 0x08 "CNT,Counter Register" width 0x0B tree.end tree "GPT3" base ad:0x590E0000 width 6. group.long 0x00++0x1B line.long 0x00 "CR,Control Register" bitfld.long 0x00 31. " FO3 ,Force output compare channel 3" "No effect,Force" bitfld.long 0x00 30. " FO2 ,Force output compare channel 2" "No effect,Force" bitfld.long 0x00 29. " FO1 ,Force output compare channel 1" "No effect,Force" bitfld.long 0x00 26.--28. " OM3 ,Output compare channel 3 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" newline bitfld.long 0x00 23.--25. " OM2 ,Output compare channel 2 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 20.--22. " OM1 ,Output compare channel 1 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 18.--19. " IM2 ,Input capture channel 2 operating mode" "Disabled,Rising,Falling,Both edges" bitfld.long 0x00 16.--17. " IM1 ,Input capture channel 1 operating mode" "Disabled,Rising,Falling,Both edges" newline bitfld.long 0x00 15. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 10. " EN_24M ,Enable 24MHz clock input from crystal" "Disabled,Enabled" bitfld.long 0x00 9. " FRR ,Free-run or restart mode" "Restart,Free-Run" bitfld.long 0x00 6.--8. " CLKSRC ,Clock source select" "No clock,Peripheral,High Freq,External,Low Freq,Crystal,?..." newline bitfld.long 0x00 5. " STOPEN ,GPT stop mode" "Disabled,Enabled" bitfld.long 0x00 4. " DOZEEN ,GPT doze mode" "Disabled,Enabled" bitfld.long 0x00 3. " WAITEN ,GPT wait mode enable" "Disabled,Enabled" bitfld.long 0x00 2. " DBGEN ,GPT debug mode enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " ENMOD ,GPT enable mode (main counter value)" "Freeze,Reset" bitfld.long 0x00 0. " EN ,GPT enable" "Disabled,Enabled" line.long 0x04 "PR,Prescaler Register" bitfld.long 0x04 12.--15. " PRESCALER24M ,24 MHz crystal clock prescaler division value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" hexmask.long.word 0x04 0.--11. 1. " PRESCALER ,Clock division coefficient" line.long 0x08 "SR,Status Register" eventfld.long 0x08 5. " ROV ,Rollover flag" "Not occurred,Occurred" eventfld.long 0x08 4. " IF2 ,Input capture 2 flag" "Not occurred,Occurred" eventfld.long 0x08 3. " IF1 ,Input capture 1 flag" "Not occurred,Occurred" eventfld.long 0x08 2. " OF3 ,Output compare 3 flag" "Not occurred,Occurred" newline eventfld.long 0x08 1. " OF2 ,Output compare 2 flag" "Not occurred,Occurred" eventfld.long 0x08 0. " OF1 ,Output compare 1 flag" "Not occurred,Occurred" line.long 0x0C "IR,Interrupt Register" bitfld.long 0x0C 5. " ROVIE ,Rollover interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " IF2IE ,Input capture 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " IF1IE ,Input capture 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 2. " OF3IE ,Output compare 3 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 1. " OF2IE ,Output compare 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " OF1IE ,Output compare 1 interrupt enable" "Disabled,Enabled" line.long 0x10 "OCR1,Output Compare Register 1" line.long 0x14 "OCR2,Output Compare Register 2" line.long 0x18 "OCR3,Output Compare Register 3" rgroup.long 0x1C++0x0B line.long 0x00 "ICR1,Input Compare Register 1" line.long 0x04 "ICR2,Input Compare Register 2" line.long 0x08 "CNT,Counter Register" width 0x0B tree.end tree "GPT4" base ad:0x590F0000 width 6. group.long 0x00++0x1B line.long 0x00 "CR,Control Register" bitfld.long 0x00 31. " FO3 ,Force output compare channel 3" "No effect,Force" bitfld.long 0x00 30. " FO2 ,Force output compare channel 2" "No effect,Force" bitfld.long 0x00 29. " FO1 ,Force output compare channel 1" "No effect,Force" bitfld.long 0x00 26.--28. " OM3 ,Output compare channel 3 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" newline bitfld.long 0x00 23.--25. " OM2 ,Output compare channel 2 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 20.--22. " OM1 ,Output compare channel 1 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 18.--19. " IM2 ,Input capture channel 2 operating mode" "Disabled,Rising,Falling,Both edges" bitfld.long 0x00 16.--17. " IM1 ,Input capture channel 1 operating mode" "Disabled,Rising,Falling,Both edges" newline bitfld.long 0x00 15. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 10. " EN_24M ,Enable 24MHz clock input from crystal" "Disabled,Enabled" bitfld.long 0x00 9. " FRR ,Free-run or restart mode" "Restart,Free-Run" bitfld.long 0x00 6.--8. " CLKSRC ,Clock source select" "No clock,Peripheral,High Freq,External,Low Freq,Crystal,?..." newline bitfld.long 0x00 5. " STOPEN ,GPT stop mode" "Disabled,Enabled" bitfld.long 0x00 4. " DOZEEN ,GPT doze mode" "Disabled,Enabled" bitfld.long 0x00 3. " WAITEN ,GPT wait mode enable" "Disabled,Enabled" bitfld.long 0x00 2. " DBGEN ,GPT debug mode enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " ENMOD ,GPT enable mode (main counter value)" "Freeze,Reset" bitfld.long 0x00 0. " EN ,GPT enable" "Disabled,Enabled" line.long 0x04 "PR,Prescaler Register" bitfld.long 0x04 12.--15. " PRESCALER24M ,24 MHz crystal clock prescaler division value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" hexmask.long.word 0x04 0.--11. 1. " PRESCALER ,Clock division coefficient" line.long 0x08 "SR,Status Register" eventfld.long 0x08 5. " ROV ,Rollover flag" "Not occurred,Occurred" eventfld.long 0x08 4. " IF2 ,Input capture 2 flag" "Not occurred,Occurred" eventfld.long 0x08 3. " IF1 ,Input capture 1 flag" "Not occurred,Occurred" eventfld.long 0x08 2. " OF3 ,Output compare 3 flag" "Not occurred,Occurred" newline eventfld.long 0x08 1. " OF2 ,Output compare 2 flag" "Not occurred,Occurred" eventfld.long 0x08 0. " OF1 ,Output compare 1 flag" "Not occurred,Occurred" line.long 0x0C "IR,Interrupt Register" bitfld.long 0x0C 5. " ROVIE ,Rollover interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " IF2IE ,Input capture 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " IF1IE ,Input capture 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 2. " OF3IE ,Output compare 3 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 1. " OF2IE ,Output compare 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " OF1IE ,Output compare 1 interrupt enable" "Disabled,Enabled" line.long 0x10 "OCR1,Output Compare Register 1" line.long 0x14 "OCR2,Output Compare Register 2" line.long 0x18 "OCR3,Output Compare Register 3" rgroup.long 0x1C++0x0B line.long 0x00 "ICR1,Input Compare Register 1" line.long 0x04 "ICR2,Input Compare Register 2" line.long 0x08 "CNT,Counter Register" width 0x0B tree.end tree "GPT5" base ad:0x59100000 width 6. group.long 0x00++0x1B line.long 0x00 "CR,Control Register" bitfld.long 0x00 31. " FO3 ,Force output compare channel 3" "No effect,Force" bitfld.long 0x00 30. " FO2 ,Force output compare channel 2" "No effect,Force" bitfld.long 0x00 29. " FO1 ,Force output compare channel 1" "No effect,Force" bitfld.long 0x00 26.--28. " OM3 ,Output compare channel 3 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" newline bitfld.long 0x00 23.--25. " OM2 ,Output compare channel 2 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 20.--22. " OM1 ,Output compare channel 1 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 18.--19. " IM2 ,Input capture channel 2 operating mode" "Disabled,Rising,Falling,Both edges" bitfld.long 0x00 16.--17. " IM1 ,Input capture channel 1 operating mode" "Disabled,Rising,Falling,Both edges" newline bitfld.long 0x00 15. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 10. " EN_24M ,Enable 24MHz clock input from crystal" "Disabled,Enabled" bitfld.long 0x00 9. " FRR ,Free-run or restart mode" "Restart,Free-Run" bitfld.long 0x00 6.--8. " CLKSRC ,Clock source select" "No clock,Peripheral,High Freq,External,Low Freq,Crystal,?..." newline bitfld.long 0x00 5. " STOPEN ,GPT stop mode" "Disabled,Enabled" bitfld.long 0x00 4. " DOZEEN ,GPT doze mode" "Disabled,Enabled" bitfld.long 0x00 3. " WAITEN ,GPT wait mode enable" "Disabled,Enabled" bitfld.long 0x00 2. " DBGEN ,GPT debug mode enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " ENMOD ,GPT enable mode (main counter value)" "Freeze,Reset" bitfld.long 0x00 0. " EN ,GPT enable" "Disabled,Enabled" line.long 0x04 "PR,Prescaler Register" bitfld.long 0x04 12.--15. " PRESCALER24M ,24 MHz crystal clock prescaler division value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" hexmask.long.word 0x04 0.--11. 1. " PRESCALER ,Clock division coefficient" line.long 0x08 "SR,Status Register" eventfld.long 0x08 5. " ROV ,Rollover flag" "Not occurred,Occurred" eventfld.long 0x08 4. " IF2 ,Input capture 2 flag" "Not occurred,Occurred" eventfld.long 0x08 3. " IF1 ,Input capture 1 flag" "Not occurred,Occurred" eventfld.long 0x08 2. " OF3 ,Output compare 3 flag" "Not occurred,Occurred" newline eventfld.long 0x08 1. " OF2 ,Output compare 2 flag" "Not occurred,Occurred" eventfld.long 0x08 0. " OF1 ,Output compare 1 flag" "Not occurred,Occurred" line.long 0x0C "IR,Interrupt Register" bitfld.long 0x0C 5. " ROVIE ,Rollover interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " IF2IE ,Input capture 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " IF1IE ,Input capture 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 2. " OF3IE ,Output compare 3 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 1. " OF2IE ,Output compare 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " OF1IE ,Output compare 1 interrupt enable" "Disabled,Enabled" line.long 0x10 "OCR1,Output Compare Register 1" line.long 0x14 "OCR2,Output Compare Register 2" line.long 0x18 "OCR3,Output Compare Register 3" rgroup.long 0x1C++0x0B line.long 0x00 "ICR1,Input Compare Register 1" line.long 0x04 "ICR2,Input Compare Register 2" line.long 0x08 "CNT,Counter Register" width 0x0B tree.end tree.end tree "PWM (Pulse Width Modulation)" base ad:0x5A190000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO water mark (FIFO empty flag set threshold)" ">= 1 empty slot,>= 2 empty slots,>= 3 empty slots,>= 4 empty slots" bitfld.long 0x00 25. " STOPEN ,Stop mode enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait mode enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " DBGEN ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte data swap control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word data swap control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM output configuration" "Set=rollover/Cleared=comparison,Set=comparison/Cleared=rollover,Disconnected,Disconnected" newline bitfld.long 0x00 16.--17. " CLKSRC ,Clock source select" "Off,IPG_CLK,IPG_CLK_HIGHFREQ,IPG_CLK_32K" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter clock prescaler value" bitfld.long 0x00 3. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample repeat" "Once,Twice,Four times,Eight times" newline bitfld.long 0x00 0. " EN ,PWM enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO write error status" "No error,Error" eventfld.long 0x04 5. " CMP ,Compare event status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over event status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO empty status" "Not empty,Empty" newline rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO available" "No available,1 word,2 words,3 words,4 words,?..." line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO empty interrupt enable" "Disabled,Enabled" line.long 0x0C "PWMSAR,PWM Sample Register" hexmask.long.word 0x0C 0.--15. 1. " SAMPLE ,Sample value" line.long 0x10 "PWMPR,PWM Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Period value" rgroup.long 0x14++0x03 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" width 0x0B tree.end tree.end tree.open "GPU/VPU Subsystems" tree.open "CSR (VPU Control And Status Registers)" tree "CSR0" base ad:0x2D040000 width 13. group.long 0x00++0x0B line.long 0x00 "ADDR_OFFSET,Boot Vector Address Offset Register" line.long 0x04 "CPUWAIT,CPU Wait Signal Control Register" bitfld.long 0x04 0. " CPW ,CPUWAIT input signal" "Processor running,Processor waiting" line.long 0x08 "CTL,Control Register" bitfld.long 0x08 14. " MCT ,Cache map disable" "No,Yes" bitfld.long 0x08 13. " DIS ,LPCAC disable" "No,Yes" bitfld.long 0x08 12. " DWB ,LPCAC write buffer disable" "No,Yes" bitfld.long 0x08 11. " NAL ,LPCAC data cache allocation disable" "No,Yes" newline bitfld.long 0x08 10. " CLR ,LPCAC data cache clear" "Not cleared,Cleared" hexmask.long.word 0x08 2.--9. 1. " ILT ,IRQLATENCY input control" bitfld.long 0x08 1. " TEV ,TXEV output override" "Not overridden,Overridden" bitfld.long 0x08 0. " REV ,RXEV input override" "Not overridden,Overridden" rgroup.long 0x0C++0x03 line.long 0x00 "STAT,Status Register" bitfld.long 0x00 0. " LKP ,LOCKUP output" "Low,High" group.long 0x20++0x0B line.long 0x00 "INT_SET/CLR,Interrupt Set/Clear Register" setclrfld.long 0x00 4. -0x0C 4. -0x08 4. " I[4] ,CSR interrupt 4" "No interrupt,Interrupt" setclrfld.long 0x00 3. -0x0C 3. -0x08 3. " [3] ,CSR interrupt 3" "No interrupt,Interrupt" setclrfld.long 0x00 2. -0x0C 2. -0x08 2. " [2] ,CSR interrupt 2" "No interrupt,Interrupt" setclrfld.long 0x00 1. -0x0C 1. -0x08 1. " [1] ,CSR interrupt 1" "No interrupt,Interrupt" setclrfld.long 0x00 0. -0x0C 0. -0x08 0. " [0] ,CSR interrupt 0" "No interrupt,Interrupt" line.long 0x04 "INT_EN,Interrupt Enable Register" bitfld.long 0x04 4. " IEN[4] ,Interrupt 4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,Interrupt 3 enable" "Disabled,Enabled" bitfld.long 0x04 2. " [2] ,Interrupt 2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,Interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,Interrupt 0 enable" "Disabled,Enabled" line.long 0x08 "INT_OVR,Interrupt Override Register" bitfld.long 0x08 4. " IOV[4] ,Interrupt 4 override" "Not overridden,Overridden" bitfld.long 0x08 3. " [3] ,Interrupt 3 override" "Not overridden,Overridden" bitfld.long 0x08 2. " [2] ,Interrupt 2 override" "Not overridden,Overridden" bitfld.long 0x08 1. " [1] ,Interrupt 1 override" "Not overridden,Overridden" bitfld.long 0x08 0. " [0] ,Interrupt 0 override" "Not overridden,Overridden" width 0x0B tree.end tree "CSR1" base ad:0x2D050000 width 13. group.long 0x00++0x0B line.long 0x00 "ADDR_OFFSET,Boot Vector Address Offset Register" line.long 0x04 "CPUWAIT,CPU Wait Signal Control Register" bitfld.long 0x04 0. " CPW ,CPUWAIT input signal" "Processor running,Processor waiting" line.long 0x08 "CTL,Control Register" bitfld.long 0x08 14. " MCT ,Cache map disable" "No,Yes" bitfld.long 0x08 13. " DIS ,LPCAC disable" "No,Yes" bitfld.long 0x08 12. " DWB ,LPCAC write buffer disable" "No,Yes" bitfld.long 0x08 11. " NAL ,LPCAC data cache allocation disable" "No,Yes" newline bitfld.long 0x08 10. " CLR ,LPCAC data cache clear" "Not cleared,Cleared" hexmask.long.word 0x08 2.--9. 1. " ILT ,IRQLATENCY input control" bitfld.long 0x08 1. " TEV ,TXEV output override" "Not overridden,Overridden" bitfld.long 0x08 0. " REV ,RXEV input override" "Not overridden,Overridden" rgroup.long 0x0C++0x03 line.long 0x00 "STAT,Status Register" bitfld.long 0x00 0. " LKP ,LOCKUP output" "Low,High" group.long 0x20++0x0B line.long 0x00 "INT_SET/CLR,Interrupt Set/Clear Register" setclrfld.long 0x00 4. -0x0C 4. -0x08 4. " I[4] ,CSR interrupt 4" "No interrupt,Interrupt" setclrfld.long 0x00 3. -0x0C 3. -0x08 3. " [3] ,CSR interrupt 3" "No interrupt,Interrupt" setclrfld.long 0x00 2. -0x0C 2. -0x08 2. " [2] ,CSR interrupt 2" "No interrupt,Interrupt" setclrfld.long 0x00 1. -0x0C 1. -0x08 1. " [1] ,CSR interrupt 1" "No interrupt,Interrupt" setclrfld.long 0x00 0. -0x0C 0. -0x08 0. " [0] ,CSR interrupt 0" "No interrupt,Interrupt" line.long 0x04 "INT_EN,Interrupt Enable Register" bitfld.long 0x04 4. " IEN[4] ,Interrupt 4 enable" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,Interrupt 3 enable" "Disabled,Enabled" bitfld.long 0x04 2. " [2] ,Interrupt 2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,Interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,Interrupt 0 enable" "Disabled,Enabled" line.long 0x08 "INT_OVR,Interrupt Override Register" bitfld.long 0x08 4. " IOV[4] ,Interrupt 4 override" "Not overridden,Overridden" bitfld.long 0x08 3. " [3] ,Interrupt 3 override" "Not overridden,Overridden" bitfld.long 0x08 2. " [2] ,Interrupt 2 override" "Not overridden,Overridden" bitfld.long 0x08 1. " [1] ,Interrupt 1 override" "Not overridden,Overridden" bitfld.long 0x08 0. " [0] ,Interrupt 0 override" "Not overridden,Overridden" width 0x0B tree.end tree.end tree.end tree.open "LSIO" tree.open "FLEXSPI (Flexible SPI)" tree "FLEXSPI0" base ad:0x5D120000 width 14. group.long 0x00++0x1F line.long 0x00 "MCR0,Module Control Register 0" hexmask.long.byte 0x00 24.--31. 1. " AHBGRANTWAIT ,Timeout wait cycle for AHB command grant" hexmask.long.byte 0x00 16.--23. 1. " IPGRANTWAIT ,Time out wait cycle for IP command grant" bitfld.long 0x00 15. " LEARNEN ,Data learning feature enable" "Disabled,Enabled" newline bitfld.long 0x00 14. " SCKFREERUNEN ,Force SCK output free-running enable" "Disabled,Enabled" bitfld.long 0x00 13. " COMBINATIONEN ,Support flash octal mode access" "Disabled,Enabled" bitfld.long 0x00 12. " DOZEEN ,Doze mode enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " HSEN ,Half speed serial flash access enable" "Disabled,Enabled" bitfld.long 0x00 8.--10. " SERCLKDIV ,The serial root clock could be divided inside FlexSPI" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 7. " ATDFEN ,AHB bus write access to IP TX FIFO enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " ARDFEN ,AHB bus read access to IP RX FIFO enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " RXCLKSRC ,Sample clock source selection for flash reading" "Internally,DQS,,Flash" bitfld.long 0x00 1. " MDIS ,Module disable" "No,Yes" newline bitfld.long 0x00 0. " SWRESET ,Software reset" "No reset,Reset" line.long 0x04 "MCR1,Module Control Register 1" hexmask.long.word 0x04 16.--31. 1. " SEQWAIT ,Command sequence execution" hexmask.long.word 0x04 0.--15. 1. " AHBBUSWAIT ,AHB read/write access" line.long 0x08 "MCR2,Module Control Register 2" hexmask.long.byte 0x08 24.--31. 1. " RESUMEWAIT ,Wait cycle for idle state before suspended command sequence resumed" bitfld.long 0x08 19. " SCKBDIFFOPT ,Use SCKB pad as SCKA differential clock output" "Not used,Used" bitfld.long 0x08 15. " SAMEDEVICEEN ,All external devices are same devices" "Disabled,Enabled" newline bitfld.long 0x08 14. " CLRLEARNPHASE ,The sampling clock phase selection reset" "No reset,Reset" bitfld.long 0x08 11. " CLRAHBBUFOPT ,AHB RX/TX buffer clean automatically enable" "Disabled,Enabled" line.long 0x0C "AHBCR,AHB Bus Control Register" bitfld.long 0x0C 6. " READADDROPT ,AHB read address option" "Read burst,No read burst" bitfld.long 0x0C 5. " PREFETCHEN ,AHB read prefetch enable" "Disabled,Enabled" bitfld.long 0x0C 4. " BUFFERABLEEN ,AHB bus bufferable write access support enable" "Disabled,Enabled" newline bitfld.long 0x0C 3. " CACHABLEEN ,AHB bus cachable read access support enable" "Disabled,Enabled" bitfld.long 0x0C 0. " APAREN ,Parallel mode enabled for AHB triggered command" "Individual,Parallel" line.long 0x10 "INTEN,Interrupt Enable Register" bitfld.long 0x10 11. " SEQTIMEOUTEN ,Sequence execution timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x10 10. " AHBBUSTIMEOUTEN ,AHB Bus timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x10 9. " SCKSTOPBYWREN ,SCK is stopped during command sequence because async TX FIFO empty interrupt enable" "Disabled,Enabled" newline bitfld.long 0x10 8. " SCKSTOPBYRDEN ,SCK is stopped during command sequence because async RX FIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x10 7. " DATALEARNFAILEN ,Data learning failed interrupt enable" "Disabled,Enabled" bitfld.long 0x10 6. " IPTXWEEN ,IP TX FIFO watermark empty interrupt enable" "Disabled,Enabled" newline bitfld.long 0x10 5. " IPRXWAEN ,IP RX FIFO watermark available interrupt enable" "Disabled,Enabled" bitfld.long 0x10 4. " AHBCMDERREN ,AHB triggered command sequences error detected interrupt enable" "Disabled,Enabled" bitfld.long 0x10 3. " IPCMDERREN ,IP triggered command sequences error detected interrupt enable" "Disabled,Enabled" newline bitfld.long 0x10 2. " AHBCMDGEEN ,AHB triggered command sequences grant timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x10 1. " IPCMDGEEN ,IP triggered command sequences grant timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x10 0. " IPCMDDONEEN ,IP triggered command sequences execution finished interrupt enable" "Disabled,Enabled" newline line.long 0x14 "INTR,Interrupt Register" eventfld.long 0x14 11. " SEQTIMEOUT ,Sequence execution timeout interrupt" "No interrupt,Interrupt" eventfld.long 0x14 10. " AHBBUSTIMEOUT ,AHB bus timeout interrupt" "No interrupt,Interrupt" eventfld.long 0x14 9. " SCKSTOPBYWR ,SCK is stopped during command sequence because async TX FIFO empty interrupt" "No interrupt,Interrupt" newline eventfld.long 0x14 8. " SCKSTOPBYRD ,SCK is stopped during command sequence because async RX FIFO full interrupt" "No interrupt,Interrupt" eventfld.long 0x14 7. " DATALEARNFAIL ,Data learning failed interrupt" "No interrupt,Interrupt" eventfld.long 0x14 6. " IPTXWE ,IP TX FIFO watermark empty interrupt" "No interrupt,Interrupt" newline eventfld.long 0x14 5. " IPRXWA ,IP RX FIFO watermark available interrupt" "No interrupt,Interrupt" eventfld.long 0x14 4. " AHBCMDERR ,AHB triggered command sequences error detected interrupt" "No interrupt,Interrupt" eventfld.long 0x14 3. " IPCMDERR ,IP triggered command sequences error detected interrupt" "No interrupt,Interrupt" newline eventfld.long 0x14 2. " AHBCMDGE ,AHB triggered command sequences grant timeout interrupt" "No interrupt,Interrupt" eventfld.long 0x14 1. " IPCMDGE ,P triggered command sequences grant timeout interrupt" "No interrupt,Interrupt" eventfld.long 0x14 0. " IPCMDDONE ,IP triggered command sequences execution finished interrupt" "No interrupt,Interrupt" newline line.long 0x18 "LUTKEY,LUT Key Register" line.long 0x1C "LUTCR,LUT Control Register" bitfld.long 0x1C 0.--1. " UNLOCK_LOCK ,LUT lock" ",Locked,Unlocked,?..." group.long 0x20++0x03 line.long 0x00 "AHBRXBUF0CR0,AHB RX Buffer 0 Control Register 0" bitfld.long 0x00 31. " PREFETCHEN ,AHB read prefetch enable" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PRIORITY ,AHB master read priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " MSTRID ,ID of AHB master associated with this buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--8. 1. " BUFSZ ,AHB RX buffer size in 64 bits" group.long 0x24++0x03 line.long 0x00 "AHBRXBUF1CR0,AHB RX Buffer 1 Control Register 0" bitfld.long 0x00 31. " PREFETCHEN ,AHB read prefetch enable" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PRIORITY ,AHB master read priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " MSTRID ,ID of AHB master associated with this buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--8. 1. " BUFSZ ,AHB RX buffer size in 64 bits" group.long 0x28++0x03 line.long 0x00 "AHBRXBUF2CR0,AHB RX Buffer 2 Control Register 0" bitfld.long 0x00 31. " PREFETCHEN ,AHB read prefetch enable" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PRIORITY ,AHB master read priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " MSTRID ,ID of AHB master associated with this buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--8. 1. " BUFSZ ,AHB RX buffer size in 64 bits" group.long 0x2C++0x03 line.long 0x00 "AHBRXBUF3CR0,AHB RX Buffer 3 Control Register 0" bitfld.long 0x00 31. " PREFETCHEN ,AHB read prefetch enable" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PRIORITY ,AHB master read priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " MSTRID ,ID of AHB master associated with this buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--8. 1. " BUFSZ ,AHB RX buffer size in 64 bits" group.long 0x30++0x03 line.long 0x00 "AHBRXBUF4CR0,AHB RX Buffer 4 Control Register 0" bitfld.long 0x00 31. " PREFETCHEN ,AHB read prefetch enable" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PRIORITY ,AHB master read priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " MSTRID ,ID of AHB master associated with this buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--8. 1. " BUFSZ ,AHB RX buffer size in 64 bits" group.long 0x34++0x03 line.long 0x00 "AHBRXBUF5CR0,AHB RX Buffer 5 Control Register 0" bitfld.long 0x00 31. " PREFETCHEN ,AHB read prefetch enable" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PRIORITY ,AHB master read priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " MSTRID ,ID of AHB master associated with this buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--8. 1. " BUFSZ ,AHB RX buffer size in 64 bits" group.long 0x38++0x03 line.long 0x00 "AHBRXBUF6CR0,AHB RX Buffer 6 Control Register 0" bitfld.long 0x00 31. " PREFETCHEN ,AHB read prefetch enable" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PRIORITY ,AHB master read priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " MSTRID ,ID of AHB master associated with this buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--8. 1. " BUFSZ ,AHB RX buffer size in 64 bits" group.long 0x3C++0x03 line.long 0x00 "AHBRXBUF7CR0,AHB RX Buffer 7 Control Register 0" bitfld.long 0x00 31. " PREFETCHEN ,AHB read prefetch enable" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PRIORITY ,AHB master read priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " MSTRID ,ID of AHB master associated with this buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--8. 1. " BUFSZ ,AHB RX buffer size in 64 bits" group.long 0x60++0x03 line.long 0x00 "FLSHA1CR0,Flash A1 Control 0 Register" hexmask.long.tbyte 0x00 0.--22. 1. " FLSHSZ ,Flash size in KB" group.long 0x64++0x03 line.long 0x00 "FLSHA2CR0,Flash A2 Control 0 Register" hexmask.long.tbyte 0x00 0.--22. 1. " FLSHSZ ,Flash size in KB" group.long 0x68++0x03 line.long 0x00 "FLSHB1CR0,Flash B1 Control 0 Register" hexmask.long.tbyte 0x00 0.--22. 1. " FLSHSZ ,Flash size in KB" group.long 0x6C++0x03 line.long 0x00 "FLSHB2CR0,Flash B2 Control 0 Register" hexmask.long.tbyte 0x00 0.--22. 1. " FLSHSZ ,Flash size in KB" group.long 0x70++0x03 line.long 0x00 "FLSHA1CR1,Flash A1 Control 1 Register" hexmask.long.word 0x00 16.--31. 1. " CSINTERVAL ,Used to set the minimum interval between flash device chip selection deassertion and flash device chip selection assertion" bitfld.long 0x00 15. " CSINTERVALUNIT ,CS interval unit" "1 cycle,256 cycles" bitfld.long 0x00 11.--14. " CAS ,Column address size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10. " WA ,Word addressable" "Disabled,Enabled" bitfld.long 0x00 5.--9. " TCSH ,Serial flash CS hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " TCSS ,Serial flash CS setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x74++0x03 line.long 0x00 "FLSHA2CR1,Flash A2 Control 1 Register" hexmask.long.word 0x00 16.--31. 1. " CSINTERVAL ,Used to set the minimum interval between flash device chip selection deassertion and flash device chip selection assertion" bitfld.long 0x00 15. " CSINTERVALUNIT ,CS interval unit" "1 cycle,256 cycles" bitfld.long 0x00 11.--14. " CAS ,Column address size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10. " WA ,Word addressable" "Disabled,Enabled" bitfld.long 0x00 5.--9. " TCSH ,Serial flash CS hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " TCSS ,Serial flash CS setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x78++0x03 line.long 0x00 "FLSHB1CR1,Flash B1 Control 1 Register" hexmask.long.word 0x00 16.--31. 1. " CSINTERVAL ,Used to set the minimum interval between flash device chip selection deassertion and flash device chip selection assertion" bitfld.long 0x00 15. " CSINTERVALUNIT ,CS interval unit" "1 cycle,256 cycles" bitfld.long 0x00 11.--14. " CAS ,Column address size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10. " WA ,Word addressable" "Disabled,Enabled" bitfld.long 0x00 5.--9. " TCSH ,Serial flash CS hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " TCSS ,Serial flash CS setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x7C++0x03 line.long 0x00 "FLSHB2CR1,Flash B2 Control 1 Register" hexmask.long.word 0x00 16.--31. 1. " CSINTERVAL ,Used to set the minimum interval between flash device chip selection deassertion and flash device chip selection assertion" bitfld.long 0x00 15. " CSINTERVALUNIT ,CS interval unit" "1 cycle,256 cycles" bitfld.long 0x00 11.--14. " CAS ,Column address size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10. " WA ,Word addressable" "Disabled,Enabled" bitfld.long 0x00 5.--9. " TCSH ,Serial flash CS hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " TCSS ,Serial flash CS setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x80++0x03 line.long 0x00 "FLSHA1CR2,Flash A1 Control 2 Register" bitfld.long 0x00 31. " CLRINSTRPTR ,Clear the instruction pointer" "Not cleared,Cleared" bitfld.long 0x00 28.--30. " AWRWAITUNIT ,AWRWAIT unit" "2 cycles,8 cycles,32 cycles,128 cycles,512 cycles,2048 cycles,8192 cycles,32768 cycles" hexmask.long.word 0x00 16.--27. 1. " AWRWAIT ,Time to write data into internal memory" newline bitfld.long 0x00 13.--15. " AWRSEQNUM ,Sequence number for AHB write triggered command" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--12. " AWRSEQID ,Sequence index for AHB write triggered command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--7. " ARDSEQNUM ,Sequence number for AHB read triggered command in LUT" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--4. " ARDSEQID ,Sequence index for AHB read triggered command in LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x84++0x03 line.long 0x00 "FLSHA2CR2,Flash A2 Control 2 Register" bitfld.long 0x00 31. " CLRINSTRPTR ,Clear the instruction pointer" "Not cleared,Cleared" bitfld.long 0x00 28.--30. " AWRWAITUNIT ,AWRWAIT unit" "2 cycles,8 cycles,32 cycles,128 cycles,512 cycles,2048 cycles,8192 cycles,32768 cycles" hexmask.long.word 0x00 16.--27. 1. " AWRWAIT ,Time to write data into internal memory" newline bitfld.long 0x00 13.--15. " AWRSEQNUM ,Sequence number for AHB write triggered command" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--12. " AWRSEQID ,Sequence index for AHB write triggered command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--7. " ARDSEQNUM ,Sequence number for AHB read triggered command in LUT" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--4. " ARDSEQID ,Sequence index for AHB read triggered command in LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x88++0x03 line.long 0x00 "FLSHB1CR2,Flash B1 Control 2 Register" bitfld.long 0x00 31. " CLRINSTRPTR ,Clear the instruction pointer" "Not cleared,Cleared" bitfld.long 0x00 28.--30. " AWRWAITUNIT ,AWRWAIT unit" "2 cycles,8 cycles,32 cycles,128 cycles,512 cycles,2048 cycles,8192 cycles,32768 cycles" hexmask.long.word 0x00 16.--27. 1. " AWRWAIT ,Time to write data into internal memory" newline bitfld.long 0x00 13.--15. " AWRSEQNUM ,Sequence number for AHB write triggered command" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--12. " AWRSEQID ,Sequence index for AHB write triggered command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--7. " ARDSEQNUM ,Sequence number for AHB read triggered command in LUT" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--4. " ARDSEQID ,Sequence index for AHB read triggered command in LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x8C++0x03 line.long 0x00 "FLSHB2CR2,Flash B2 Control 2 Register" bitfld.long 0x00 31. " CLRINSTRPTR ,Clear the instruction pointer" "Not cleared,Cleared" bitfld.long 0x00 28.--30. " AWRWAITUNIT ,AWRWAIT unit" "2 cycles,8 cycles,32 cycles,128 cycles,512 cycles,2048 cycles,8192 cycles,32768 cycles" hexmask.long.word 0x00 16.--27. 1. " AWRWAIT ,Time to write data into internal memory" newline bitfld.long 0x00 13.--15. " AWRSEQNUM ,Sequence number for AHB write triggered command" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--12. " AWRSEQID ,Sequence index for AHB write triggered command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--7. " ARDSEQNUM ,Sequence number for AHB read triggered command in LUT" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--4. " ARDSEQID ,Sequence index for AHB read triggered command in LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x94++0x03 line.long 0x00 "FLSHCR4,Flash Control Register 4" bitfld.long 0x00 3. " WMENB ,Write mask enable bit for flash device on port B" "Disabled,Enabled" bitfld.long 0x00 2. " WMENA ,Write mask enable bit for flash device on port A" "Disabled,Enabled" bitfld.long 0x00 0. " WMOPT1 ,AHB write burst start address alignment limitation disable" "No,Yes" group.long 0xA0++0x07 line.long 0x00 "IPCR0,IP Control Register 0" line.long 0x04 "IPCR1,IP Control Register 1" bitfld.long 0x04 31. " IPAREN ,Parallel mode" "Disabled,Enabled" bitfld.long 0x04 24.--26. " ISEQNUM ,Sequence number for IP command" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--20. " ISEQID ,Sequence index in LUT for IP command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x04 0.--15. 1. " IDATSZ ,Flash read/program data size (in bytes) for IP command" group.long 0xB0++0x17 line.long 0x00 "IPCMD,IP Command Register" bitfld.long 0x00 0. " TRG ,IP command trigger" "Not triggered,Triggered" line.long 0x04 "DLPR,Data Learn Pattern Register" line.long 0x08 "IPRXFCR,IP RX FIFO Control Register" bitfld.long 0x08 2.--7. " RXWMRK ,Watermark level" "64bits,128bits,192bits,256bits,320bits,384bits,448bits,512bits,576bits,640bits,704bits,768bits,832bits,896bits,960bits,1024bits,1088bits,1152bits,1216bits,1280bits,1344bits,1408bits,1472bits,1536bits,1600bits,1664bits,1728bits,1792bits,1856bits,1920bits,1984bits,2048bits,2112bits,2176bits,2240bits,2304bits,2368bits,2432bits,2496bits,2560bits,2624bits,2688bits,2752bits,2816bits,2880bits,2944bits,3008bits,3072bits,3136bits,3200bits,3264bits,3328bits,3392bits,3456bits,3520bits,3584bits,3648bits,3712bits,3776bits,3840bits,3904bits,3968bits,4032bits,4096bits" bitfld.long 0x08 1. " RXDMAEN ,IP RX FIFO reading by DMA enable" "Disabled,Enabled" bitfld.long 0x08 0. " CLRIPRXF ,Clear all valid data entries in IP RX FIFO" "Not cleared,Cleared" newline line.long 0x0C "IPTXFCR,IP TX FIFO Control Register" hexmask.long.word 0x0C 2.--8. 1. " TXWMRK ,Watermark level" bitfld.long 0x0C 1. " TXDMAEN ,IP TX FIFO filling by DMA enabled" "Disabled,Enabled" bitfld.long 0x0C 0. " CLRIPTXF ,Clear all valid data entries in IP TX FIFO" "Not cleared,Cleared" newline line.long 0x10 "DLLACR,DLLA Control 0 Register" bitfld.long 0x10 9.--14. " OVRDVAL ,Slave clock delay line delay cell number selection override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 8. " OVRDEN ,Slave clock delay line delay cell number selection override enable" "Disabled,Enabled" bitfld.long 0x10 3.--6. " SLVDLYTARGET ,The delay target for slave delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 1. " DLLRESET ,DDL reset" "No reset,Reset" bitfld.long 0x10 0. " DLLEN ,DLL calibration enable" "Disabled,Enabled" line.long 0x14 "DLLBCR,DLLB Control 0 Register" bitfld.long 0x14 9.--14. " OVRDVAL ,Slave clock delay line delay cell number selection override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 8. " OVRDEN ,Slave clock delay line delay cell number selection override enable" "Disabled,Enabled" bitfld.long 0x14 3.--6. " SLVDLYTARGET ,The delay target for slave delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 1. " DLLRESET ,DDL reset" "No reset,Reset" bitfld.long 0x14 0. " DLLEN ,DLL calibration enable" "Disabled,Enabled" rgroup.long 0xE0++0x17 line.long 0x00 "STS0,Status Register 0" bitfld.long 0x00 8.--11. " DATALEARNPHASEB ,Sampling clock phase selection on Port B after data learning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DATALEARNPHASEA ,Sampling clock phase selection on Port A after data learning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--3. " ARBCMDSRC ,Trigger source of current command sequence granted by arbitrator" "AHB Read,AHB Write,IP,Suspended" newline bitfld.long 0x00 1. " ARBIDLE ,State machine in ARB_CTL" "Busy,Idle" bitfld.long 0x00 0. " SEQIDLE ,State machine in SEQ_CTL" "Busy,Idle" newline line.long 0x04 "STS1,Status Register 1" bitfld.long 0x04 24.--27. " IPCMDERRCODE ,IP command error code" "No error,,JMP_ON_CS used with IP command,Unknown opcode,SDR used in DDR,DDR used in SDR,Start address exceed whole flash address range,,,,,,,,Sequence execution timeout,Flash boundary crossed" bitfld.long 0x04 16.--20. "IPCMDERRID ,Sequence index when IP command error detected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 8.--11. " AHBCMDERRCODE ,AHB command error code" "No error,,JMP_ON_CS used with AHB write command,Unknown opcode,SDR used in DDR,DDR used in SDR,,,,,,,,,Execution timeout,?..." bitfld.long 0x04 0.--4. " AHBCMDERRID ,Sequence index when an AHB command error is detected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline line.long 0x08 "STS2,Status Register 2" bitfld.long 0x08 24.--29. " BREFSEL ,Flash B sample clock reference delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 18.--23. " BSLVSEL ,Flash B sample clock slave delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 17. " BREFLOCK ,Flash B sample clock reference delay line locked" "Not locked,Locked" newline bitfld.long 0x08 16. " BSLVLOCK ,Flash B sample clock slave delay line locked" "Not locked,Locked" bitfld.long 0x08 8.--13. " AREFSEL ,Flash A sample clock reference delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 2.--7. " ASLVSEL ,Flash A sample clock slave delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 1. " AREFLOCK ,Flash A sample clock reference delay line locked" "Not locked,Locked" bitfld.long 0x08 0. " ASLVLOCK ,Flash A sample clock slave delay line locked" "Not locked,Locked" line.long 0x0C "AHBSPNDSTS,AHB Suspend Status Register" hexmask.long.word 0x0C 16.--31. 1. " DATLFT ,Left data size for suspended command sequence" bitfld.long 0x0C 1.--3. " BUFID ,AHB RX BUF ID for suspended command sequence" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0. " ACTIVE ,AHB read prefetch command sequence has been suspended" "Not suspended,Suspended" newline line.long 0x10 "IPRXFSTS,IP RX FIFO Status Register" hexmask.long.word 0x10 16.--31. 1. " RDCNTR ,Total read data counter" hexmask.long.byte 0x10 0.--7. 1. " FILL ,Fill level of IP RX FIFO" line.long 0x14 "IPTXFSTS,IP TX FIFO Status Register" hexmask.long.word 0x14 16.--31. 1. " WRCNTR ,Total write data counter" hexmask.long.byte 0x14 0.--7. 1. " FILL ,Fill level of IP TX FIFO" tree "RX/TX FIFO Data" rgroup.long 0x100++0x03 line.long 0x00 "RFDR0,IP RX FIFO Data 0 Register" rgroup.long 0x104++0x03 line.long 0x00 "RFDR1,IP RX FIFO Data 1 Register" rgroup.long 0x108++0x03 line.long 0x00 "RFDR2,IP RX FIFO Data 2 Register" rgroup.long 0x10C++0x03 line.long 0x00 "RFDR3,IP RX FIFO Data 3 Register" rgroup.long 0x110++0x03 line.long 0x00 "RFDR4,IP RX FIFO Data 4 Register" rgroup.long 0x114++0x03 line.long 0x00 "RFDR5,IP RX FIFO Data 5 Register" rgroup.long 0x118++0x03 line.long 0x00 "RFDR6,IP RX FIFO Data 6 Register" rgroup.long 0x11C++0x03 line.long 0x00 "RFDR7,IP RX FIFO Data 7 Register" rgroup.long 0x120++0x03 line.long 0x00 "RFDR8,IP RX FIFO Data 8 Register" rgroup.long 0x124++0x03 line.long 0x00 "RFDR9,IP RX FIFO Data 9 Register" rgroup.long 0x128++0x03 line.long 0x00 "RFDR10,IP RX FIFO Data 10 Register" rgroup.long 0x12C++0x03 line.long 0x00 "RFDR11,IP RX FIFO Data 11 Register" rgroup.long 0x130++0x03 line.long 0x00 "RFDR12,IP RX FIFO Data 12 Register" rgroup.long 0x134++0x03 line.long 0x00 "RFDR13,IP RX FIFO Data 13 Register" rgroup.long 0x138++0x03 line.long 0x00 "RFDR14,IP RX FIFO Data 14 Register" rgroup.long 0x13C++0x03 line.long 0x00 "RFDR15,IP RX FIFO Data 15 Register" rgroup.long 0x140++0x03 line.long 0x00 "RFDR16,IP RX FIFO Data 16 Register" rgroup.long 0x144++0x03 line.long 0x00 "RFDR17,IP RX FIFO Data 17 Register" rgroup.long 0x148++0x03 line.long 0x00 "RFDR18,IP RX FIFO Data 18 Register" rgroup.long 0x14C++0x03 line.long 0x00 "RFDR19,IP RX FIFO Data 19 Register" rgroup.long 0x150++0x03 line.long 0x00 "RFDR20,IP RX FIFO Data 20 Register" rgroup.long 0x154++0x03 line.long 0x00 "RFDR21,IP RX FIFO Data 21 Register" rgroup.long 0x158++0x03 line.long 0x00 "RFDR22,IP RX FIFO Data 22 Register" rgroup.long 0x15C++0x03 line.long 0x00 "RFDR23,IP RX FIFO Data 23 Register" rgroup.long 0x160++0x03 line.long 0x00 "RFDR24,IP RX FIFO Data 24 Register" rgroup.long 0x164++0x03 line.long 0x00 "RFDR25,IP RX FIFO Data 25 Register" rgroup.long 0x168++0x03 line.long 0x00 "RFDR26,IP RX FIFO Data 26 Register" rgroup.long 0x16C++0x03 line.long 0x00 "RFDR27,IP RX FIFO Data 27 Register" rgroup.long 0x170++0x03 line.long 0x00 "RFDR28,IP RX FIFO Data 28 Register" rgroup.long 0x174++0x03 line.long 0x00 "RFDR29,IP RX FIFO Data 29 Register" rgroup.long 0x178++0x03 line.long 0x00 "RFDR30,IP RX FIFO Data 30 Register" rgroup.long 0x17C++0x03 line.long 0x00 "RFDR31,IP RX FIFO Data 31 Register" wgroup.long 0x180++0x03 line.long 0x00 "TFDR0,IP TX FIFO Data 0 Register" wgroup.long 0x184++0x03 line.long 0x00 "TFDR1,IP TX FIFO Data 1 Register" wgroup.long 0x188++0x03 line.long 0x00 "TFDR2,IP TX FIFO Data 2 Register" wgroup.long 0x18C++0x03 line.long 0x00 "TFDR3,IP TX FIFO Data 3 Register" wgroup.long 0x190++0x03 line.long 0x00 "TFDR4,IP TX FIFO Data 4 Register" wgroup.long 0x194++0x03 line.long 0x00 "TFDR5,IP TX FIFO Data 5 Register" wgroup.long 0x198++0x03 line.long 0x00 "TFDR6,IP TX FIFO Data 6 Register" wgroup.long 0x19C++0x03 line.long 0x00 "TFDR7,IP TX FIFO Data 7 Register" wgroup.long 0x1A0++0x03 line.long 0x00 "TFDR8,IP TX FIFO Data 8 Register" wgroup.long 0x1A4++0x03 line.long 0x00 "TFDR9,IP TX FIFO Data 9 Register" wgroup.long 0x1A8++0x03 line.long 0x00 "TFDR10,IP TX FIFO Data 10 Register" wgroup.long 0x1AC++0x03 line.long 0x00 "TFDR11,IP TX FIFO Data 11 Register" wgroup.long 0x1B0++0x03 line.long 0x00 "TFDR12,IP TX FIFO Data 12 Register" wgroup.long 0x1B4++0x03 line.long 0x00 "TFDR13,IP TX FIFO Data 13 Register" wgroup.long 0x1B8++0x03 line.long 0x00 "TFDR14,IP TX FIFO Data 14 Register" wgroup.long 0x1BC++0x03 line.long 0x00 "TFDR15,IP TX FIFO Data 15 Register" wgroup.long 0x1C0++0x03 line.long 0x00 "TFDR16,IP TX FIFO Data 16 Register" wgroup.long 0x1C4++0x03 line.long 0x00 "TFDR17,IP TX FIFO Data 17 Register" wgroup.long 0x1C8++0x03 line.long 0x00 "TFDR18,IP TX FIFO Data 18 Register" wgroup.long 0x1CC++0x03 line.long 0x00 "TFDR19,IP TX FIFO Data 19 Register" wgroup.long 0x1D0++0x03 line.long 0x00 "TFDR20,IP TX FIFO Data 20 Register" wgroup.long 0x1D4++0x03 line.long 0x00 "TFDR21,IP TX FIFO Data 21 Register" wgroup.long 0x1D8++0x03 line.long 0x00 "TFDR22,IP TX FIFO Data 22 Register" wgroup.long 0x1DC++0x03 line.long 0x00 "TFDR23,IP TX FIFO Data 23 Register" wgroup.long 0x1E0++0x03 line.long 0x00 "TFDR24,IP TX FIFO Data 24 Register" wgroup.long 0x1E4++0x03 line.long 0x00 "TFDR25,IP TX FIFO Data 25 Register" wgroup.long 0x1E8++0x03 line.long 0x00 "TFDR26,IP TX FIFO Data 26 Register" wgroup.long 0x1EC++0x03 line.long 0x00 "TFDR27,IP TX FIFO Data 27 Register" wgroup.long 0x1F0++0x03 line.long 0x00 "TFDR28,IP TX FIFO Data 28 Register" wgroup.long 0x1F4++0x03 line.long 0x00 "TFDR29,IP TX FIFO Data 29 Register" wgroup.long 0x1F8++0x03 line.long 0x00 "TFDR30,IP TX FIFO Data 30 Register" wgroup.long 0x1FC++0x03 line.long 0x00 "TFDR31,IP TX FIFO Data 31 Register" tree.end tree "LUT Registers" if (((((per.l(ad:0x5D120000+0x200))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x200))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x200))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x200))&0xFC00)==0x7C00))) group.long 0x200++0x03 line.long 0x00 "LUT0,LUT 0 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x200))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x200))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x200))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x200))&0xFC00)==0x7C00)) group.long 0x200++0x03 line.long 0x00 "LUT0,LUT 0 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x200))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x200))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x200))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x200))&0xFC00)!=0x7C00)) group.long 0x200++0x03 line.long 0x00 "LUT0,LUT 0 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x200++0x03 line.long 0x00 "LUT0,LUT 0 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x204))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x204))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x204))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x204))&0xFC00)==0x7C00))) group.long 0x204++0x03 line.long 0x00 "LUT1,LUT 1 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x204))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x204))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x204))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x204))&0xFC00)==0x7C00)) group.long 0x204++0x03 line.long 0x00 "LUT1,LUT 1 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x204))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x204))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x204))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x204))&0xFC00)!=0x7C00)) group.long 0x204++0x03 line.long 0x00 "LUT1,LUT 1 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x204++0x03 line.long 0x00 "LUT1,LUT 1 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x208))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x208))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x208))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x208))&0xFC00)==0x7C00))) group.long 0x208++0x03 line.long 0x00 "LUT2,LUT 2 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x208))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x208))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x208))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x208))&0xFC00)==0x7C00)) group.long 0x208++0x03 line.long 0x00 "LUT2,LUT 2 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x208))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x208))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x208))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x208))&0xFC00)!=0x7C00)) group.long 0x208++0x03 line.long 0x00 "LUT2,LUT 2 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x208++0x03 line.long 0x00 "LUT2,LUT 2 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x20C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x20C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x20C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x20C))&0xFC00)==0x7C00))) group.long 0x20C++0x03 line.long 0x00 "LUT3,LUT 3 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x20C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x20C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x20C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x20C))&0xFC00)==0x7C00)) group.long 0x20C++0x03 line.long 0x00 "LUT3,LUT 3 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x20C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x20C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x20C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x20C))&0xFC00)!=0x7C00)) group.long 0x20C++0x03 line.long 0x00 "LUT3,LUT 3 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x20C++0x03 line.long 0x00 "LUT3,LUT 3 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x210))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x210))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x210))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x210))&0xFC00)==0x7C00))) group.long 0x210++0x03 line.long 0x00 "LUT4,LUT 4 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x210))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x210))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x210))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x210))&0xFC00)==0x7C00)) group.long 0x210++0x03 line.long 0x00 "LUT4,LUT 4 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x210))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x210))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x210))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x210))&0xFC00)!=0x7C00)) group.long 0x210++0x03 line.long 0x00 "LUT4,LUT 4 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x210++0x03 line.long 0x00 "LUT4,LUT 4 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x214))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x214))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x214))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x214))&0xFC00)==0x7C00))) group.long 0x214++0x03 line.long 0x00 "LUT5,LUT 5 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x214))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x214))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x214))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x214))&0xFC00)==0x7C00)) group.long 0x214++0x03 line.long 0x00 "LUT5,LUT 5 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x214))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x214))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x214))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x214))&0xFC00)!=0x7C00)) group.long 0x214++0x03 line.long 0x00 "LUT5,LUT 5 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x214++0x03 line.long 0x00 "LUT5,LUT 5 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x218))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x218))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x218))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x218))&0xFC00)==0x7C00))) group.long 0x218++0x03 line.long 0x00 "LUT6,LUT 6 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x218))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x218))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x218))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x218))&0xFC00)==0x7C00)) group.long 0x218++0x03 line.long 0x00 "LUT6,LUT 6 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x218))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x218))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x218))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x218))&0xFC00)!=0x7C00)) group.long 0x218++0x03 line.long 0x00 "LUT6,LUT 6 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x218++0x03 line.long 0x00 "LUT6,LUT 6 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x21C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x21C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x21C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x21C))&0xFC00)==0x7C00))) group.long 0x21C++0x03 line.long 0x00 "LUT7,LUT 7 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x21C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x21C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x21C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x21C))&0xFC00)==0x7C00)) group.long 0x21C++0x03 line.long 0x00 "LUT7,LUT 7 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x21C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x21C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x21C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x21C))&0xFC00)!=0x7C00)) group.long 0x21C++0x03 line.long 0x00 "LUT7,LUT 7 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x21C++0x03 line.long 0x00 "LUT7,LUT 7 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x220))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x220))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x220))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x220))&0xFC00)==0x7C00))) group.long 0x220++0x03 line.long 0x00 "LUT8,LUT 8 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x220))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x220))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x220))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x220))&0xFC00)==0x7C00)) group.long 0x220++0x03 line.long 0x00 "LUT8,LUT 8 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x220))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x220))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x220))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x220))&0xFC00)!=0x7C00)) group.long 0x220++0x03 line.long 0x00 "LUT8,LUT 8 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x220++0x03 line.long 0x00 "LUT8,LUT 8 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x224))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x224))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x224))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x224))&0xFC00)==0x7C00))) group.long 0x224++0x03 line.long 0x00 "LUT9,LUT 9 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x224))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x224))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x224))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x224))&0xFC00)==0x7C00)) group.long 0x224++0x03 line.long 0x00 "LUT9,LUT 9 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x224))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x224))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x224))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x224))&0xFC00)!=0x7C00)) group.long 0x224++0x03 line.long 0x00 "LUT9,LUT 9 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x224++0x03 line.long 0x00 "LUT9,LUT 9 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x228))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x228))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x228))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x228))&0xFC00)==0x7C00))) group.long 0x228++0x03 line.long 0x00 "LUT10,LUT 10 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x228))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x228))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x228))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x228))&0xFC00)==0x7C00)) group.long 0x228++0x03 line.long 0x00 "LUT10,LUT 10 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x228))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x228))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x228))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x228))&0xFC00)!=0x7C00)) group.long 0x228++0x03 line.long 0x00 "LUT10,LUT 10 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x228++0x03 line.long 0x00 "LUT10,LUT 10 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x22C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x22C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x22C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x22C))&0xFC00)==0x7C00))) group.long 0x22C++0x03 line.long 0x00 "LUT11,LUT 11 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x22C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x22C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x22C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x22C))&0xFC00)==0x7C00)) group.long 0x22C++0x03 line.long 0x00 "LUT11,LUT 11 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x22C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x22C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x22C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x22C))&0xFC00)!=0x7C00)) group.long 0x22C++0x03 line.long 0x00 "LUT11,LUT 11 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x22C++0x03 line.long 0x00 "LUT11,LUT 11 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x230))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x230))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x230))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x230))&0xFC00)==0x7C00))) group.long 0x230++0x03 line.long 0x00 "LUT12,LUT 12 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x230))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x230))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x230))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x230))&0xFC00)==0x7C00)) group.long 0x230++0x03 line.long 0x00 "LUT12,LUT 12 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x230))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x230))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x230))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x230))&0xFC00)!=0x7C00)) group.long 0x230++0x03 line.long 0x00 "LUT12,LUT 12 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x230++0x03 line.long 0x00 "LUT12,LUT 12 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x234))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x234))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x234))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x234))&0xFC00)==0x7C00))) group.long 0x234++0x03 line.long 0x00 "LUT13,LUT 13 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x234))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x234))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x234))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x234))&0xFC00)==0x7C00)) group.long 0x234++0x03 line.long 0x00 "LUT13,LUT 13 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x234))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x234))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x234))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x234))&0xFC00)!=0x7C00)) group.long 0x234++0x03 line.long 0x00 "LUT13,LUT 13 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x234++0x03 line.long 0x00 "LUT13,LUT 13 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x238))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x238))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x238))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x238))&0xFC00)==0x7C00))) group.long 0x238++0x03 line.long 0x00 "LUT14,LUT 14 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x238))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x238))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x238))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x238))&0xFC00)==0x7C00)) group.long 0x238++0x03 line.long 0x00 "LUT14,LUT 14 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x238))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x238))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x238))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x238))&0xFC00)!=0x7C00)) group.long 0x238++0x03 line.long 0x00 "LUT14,LUT 14 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x238++0x03 line.long 0x00 "LUT14,LUT 14 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x23C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x23C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x23C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x23C))&0xFC00)==0x7C00))) group.long 0x23C++0x03 line.long 0x00 "LUT15,LUT 15 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x23C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x23C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x23C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x23C))&0xFC00)==0x7C00)) group.long 0x23C++0x03 line.long 0x00 "LUT15,LUT 15 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x23C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x23C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x23C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x23C))&0xFC00)!=0x7C00)) group.long 0x23C++0x03 line.long 0x00 "LUT15,LUT 15 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x23C++0x03 line.long 0x00 "LUT15,LUT 15 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x240))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x240))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x240))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x240))&0xFC00)==0x7C00))) group.long 0x240++0x03 line.long 0x00 "LUT16,LUT 16 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x240))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x240))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x240))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x240))&0xFC00)==0x7C00)) group.long 0x240++0x03 line.long 0x00 "LUT16,LUT 16 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x240))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x240))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x240))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x240))&0xFC00)!=0x7C00)) group.long 0x240++0x03 line.long 0x00 "LUT16,LUT 16 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x240++0x03 line.long 0x00 "LUT16,LUT 16 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x244))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x244))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x244))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x244))&0xFC00)==0x7C00))) group.long 0x244++0x03 line.long 0x00 "LUT17,LUT 17 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x244))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x244))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x244))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x244))&0xFC00)==0x7C00)) group.long 0x244++0x03 line.long 0x00 "LUT17,LUT 17 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x244))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x244))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x244))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x244))&0xFC00)!=0x7C00)) group.long 0x244++0x03 line.long 0x00 "LUT17,LUT 17 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x244++0x03 line.long 0x00 "LUT17,LUT 17 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x248))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x248))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x248))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x248))&0xFC00)==0x7C00))) group.long 0x248++0x03 line.long 0x00 "LUT18,LUT 18 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x248))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x248))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x248))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x248))&0xFC00)==0x7C00)) group.long 0x248++0x03 line.long 0x00 "LUT18,LUT 18 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x248))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x248))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x248))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x248))&0xFC00)!=0x7C00)) group.long 0x248++0x03 line.long 0x00 "LUT18,LUT 18 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x248++0x03 line.long 0x00 "LUT18,LUT 18 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x24C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x24C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x24C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x24C))&0xFC00)==0x7C00))) group.long 0x24C++0x03 line.long 0x00 "LUT19,LUT 19 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x24C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x24C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x24C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x24C))&0xFC00)==0x7C00)) group.long 0x24C++0x03 line.long 0x00 "LUT19,LUT 19 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x24C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x24C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x24C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x24C))&0xFC00)!=0x7C00)) group.long 0x24C++0x03 line.long 0x00 "LUT19,LUT 19 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x24C++0x03 line.long 0x00 "LUT19,LUT 19 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x250))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x250))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x250))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x250))&0xFC00)==0x7C00))) group.long 0x250++0x03 line.long 0x00 "LUT20,LUT 20 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x250))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x250))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x250))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x250))&0xFC00)==0x7C00)) group.long 0x250++0x03 line.long 0x00 "LUT20,LUT 20 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x250))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x250))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x250))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x250))&0xFC00)!=0x7C00)) group.long 0x250++0x03 line.long 0x00 "LUT20,LUT 20 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x250++0x03 line.long 0x00 "LUT20,LUT 20 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x254))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x254))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x254))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x254))&0xFC00)==0x7C00))) group.long 0x254++0x03 line.long 0x00 "LUT21,LUT 21 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x254))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x254))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x254))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x254))&0xFC00)==0x7C00)) group.long 0x254++0x03 line.long 0x00 "LUT21,LUT 21 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x254))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x254))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x254))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x254))&0xFC00)!=0x7C00)) group.long 0x254++0x03 line.long 0x00 "LUT21,LUT 21 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x254++0x03 line.long 0x00 "LUT21,LUT 21 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x258))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x258))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x258))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x258))&0xFC00)==0x7C00))) group.long 0x258++0x03 line.long 0x00 "LUT22,LUT 22 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x258))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x258))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x258))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x258))&0xFC00)==0x7C00)) group.long 0x258++0x03 line.long 0x00 "LUT22,LUT 22 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x258))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x258))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x258))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x258))&0xFC00)!=0x7C00)) group.long 0x258++0x03 line.long 0x00 "LUT22,LUT 22 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x258++0x03 line.long 0x00 "LUT22,LUT 22 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x25C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x25C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x25C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x25C))&0xFC00)==0x7C00))) group.long 0x25C++0x03 line.long 0x00 "LUT23,LUT 23 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x25C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x25C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x25C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x25C))&0xFC00)==0x7C00)) group.long 0x25C++0x03 line.long 0x00 "LUT23,LUT 23 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x25C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x25C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x25C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x25C))&0xFC00)!=0x7C00)) group.long 0x25C++0x03 line.long 0x00 "LUT23,LUT 23 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x25C++0x03 line.long 0x00 "LUT23,LUT 23 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x260))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x260))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x260))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x260))&0xFC00)==0x7C00))) group.long 0x260++0x03 line.long 0x00 "LUT24,LUT 24 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x260))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x260))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x260))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x260))&0xFC00)==0x7C00)) group.long 0x260++0x03 line.long 0x00 "LUT24,LUT 24 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x260))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x260))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x260))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x260))&0xFC00)!=0x7C00)) group.long 0x260++0x03 line.long 0x00 "LUT24,LUT 24 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x260++0x03 line.long 0x00 "LUT24,LUT 24 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x264))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x264))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x264))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x264))&0xFC00)==0x7C00))) group.long 0x264++0x03 line.long 0x00 "LUT25,LUT 25 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x264))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x264))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x264))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x264))&0xFC00)==0x7C00)) group.long 0x264++0x03 line.long 0x00 "LUT25,LUT 25 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x264))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x264))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x264))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x264))&0xFC00)!=0x7C00)) group.long 0x264++0x03 line.long 0x00 "LUT25,LUT 25 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x264++0x03 line.long 0x00 "LUT25,LUT 25 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x268))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x268))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x268))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x268))&0xFC00)==0x7C00))) group.long 0x268++0x03 line.long 0x00 "LUT26,LUT 26 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x268))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x268))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x268))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x268))&0xFC00)==0x7C00)) group.long 0x268++0x03 line.long 0x00 "LUT26,LUT 26 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x268))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x268))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x268))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x268))&0xFC00)!=0x7C00)) group.long 0x268++0x03 line.long 0x00 "LUT26,LUT 26 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x268++0x03 line.long 0x00 "LUT26,LUT 26 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x26C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x26C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x26C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x26C))&0xFC00)==0x7C00))) group.long 0x26C++0x03 line.long 0x00 "LUT27,LUT 27 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x26C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x26C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x26C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x26C))&0xFC00)==0x7C00)) group.long 0x26C++0x03 line.long 0x00 "LUT27,LUT 27 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x26C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x26C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x26C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x26C))&0xFC00)!=0x7C00)) group.long 0x26C++0x03 line.long 0x00 "LUT27,LUT 27 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x26C++0x03 line.long 0x00 "LUT27,LUT 27 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x270))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x270))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x270))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x270))&0xFC00)==0x7C00))) group.long 0x270++0x03 line.long 0x00 "LUT28,LUT 28 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x270))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x270))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x270))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x270))&0xFC00)==0x7C00)) group.long 0x270++0x03 line.long 0x00 "LUT28,LUT 28 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x270))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x270))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x270))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x270))&0xFC00)!=0x7C00)) group.long 0x270++0x03 line.long 0x00 "LUT28,LUT 28 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x270++0x03 line.long 0x00 "LUT28,LUT 28 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x274))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x274))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x274))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x274))&0xFC00)==0x7C00))) group.long 0x274++0x03 line.long 0x00 "LUT29,LUT 29 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x274))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x274))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x274))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x274))&0xFC00)==0x7C00)) group.long 0x274++0x03 line.long 0x00 "LUT29,LUT 29 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x274))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x274))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x274))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x274))&0xFC00)!=0x7C00)) group.long 0x274++0x03 line.long 0x00 "LUT29,LUT 29 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x274++0x03 line.long 0x00 "LUT29,LUT 29 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x278))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x278))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x278))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x278))&0xFC00)==0x7C00))) group.long 0x278++0x03 line.long 0x00 "LUT30,LUT 30 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x278))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x278))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x278))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x278))&0xFC00)==0x7C00)) group.long 0x278++0x03 line.long 0x00 "LUT30,LUT 30 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x278))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x278))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x278))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x278))&0xFC00)!=0x7C00)) group.long 0x278++0x03 line.long 0x00 "LUT30,LUT 30 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x278++0x03 line.long 0x00 "LUT30,LUT 30 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x27C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x27C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x27C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x27C))&0xFC00)==0x7C00))) group.long 0x27C++0x03 line.long 0x00 "LUT31,LUT 31 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x27C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x27C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x27C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x27C))&0xFC00)==0x7C00)) group.long 0x27C++0x03 line.long 0x00 "LUT31,LUT 31 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x27C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x27C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x27C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x27C))&0xFC00)!=0x7C00)) group.long 0x27C++0x03 line.long 0x00 "LUT31,LUT 31 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x27C++0x03 line.long 0x00 "LUT31,LUT 31 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x280))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x280))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x280))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x280))&0xFC00)==0x7C00))) group.long 0x280++0x03 line.long 0x00 "LUT32,LUT 32 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x280))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x280))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x280))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x280))&0xFC00)==0x7C00)) group.long 0x280++0x03 line.long 0x00 "LUT32,LUT 32 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x280))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x280))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x280))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x280))&0xFC00)!=0x7C00)) group.long 0x280++0x03 line.long 0x00 "LUT32,LUT 32 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x280++0x03 line.long 0x00 "LUT32,LUT 32 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x284))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x284))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x284))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x284))&0xFC00)==0x7C00))) group.long 0x284++0x03 line.long 0x00 "LUT33,LUT 33 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x284))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x284))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x284))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x284))&0xFC00)==0x7C00)) group.long 0x284++0x03 line.long 0x00 "LUT33,LUT 33 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x284))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x284))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x284))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x284))&0xFC00)!=0x7C00)) group.long 0x284++0x03 line.long 0x00 "LUT33,LUT 33 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x284++0x03 line.long 0x00 "LUT33,LUT 33 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x288))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x288))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x288))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x288))&0xFC00)==0x7C00))) group.long 0x288++0x03 line.long 0x00 "LUT34,LUT 34 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x288))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x288))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x288))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x288))&0xFC00)==0x7C00)) group.long 0x288++0x03 line.long 0x00 "LUT34,LUT 34 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x288))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x288))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x288))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x288))&0xFC00)!=0x7C00)) group.long 0x288++0x03 line.long 0x00 "LUT34,LUT 34 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x288++0x03 line.long 0x00 "LUT34,LUT 34 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x28C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x28C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x28C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x28C))&0xFC00)==0x7C00))) group.long 0x28C++0x03 line.long 0x00 "LUT35,LUT 35 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x28C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x28C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x28C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x28C))&0xFC00)==0x7C00)) group.long 0x28C++0x03 line.long 0x00 "LUT35,LUT 35 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x28C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x28C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x28C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x28C))&0xFC00)!=0x7C00)) group.long 0x28C++0x03 line.long 0x00 "LUT35,LUT 35 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x28C++0x03 line.long 0x00 "LUT35,LUT 35 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x290))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x290))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x290))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x290))&0xFC00)==0x7C00))) group.long 0x290++0x03 line.long 0x00 "LUT36,LUT 36 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x290))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x290))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x290))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x290))&0xFC00)==0x7C00)) group.long 0x290++0x03 line.long 0x00 "LUT36,LUT 36 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x290))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x290))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x290))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x290))&0xFC00)!=0x7C00)) group.long 0x290++0x03 line.long 0x00 "LUT36,LUT 36 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x290++0x03 line.long 0x00 "LUT36,LUT 36 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x294))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x294))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x294))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x294))&0xFC00)==0x7C00))) group.long 0x294++0x03 line.long 0x00 "LUT37,LUT 37 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x294))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x294))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x294))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x294))&0xFC00)==0x7C00)) group.long 0x294++0x03 line.long 0x00 "LUT37,LUT 37 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x294))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x294))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x294))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x294))&0xFC00)!=0x7C00)) group.long 0x294++0x03 line.long 0x00 "LUT37,LUT 37 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x294++0x03 line.long 0x00 "LUT37,LUT 37 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x298))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x298))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x298))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x298))&0xFC00)==0x7C00))) group.long 0x298++0x03 line.long 0x00 "LUT38,LUT 38 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x298))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x298))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x298))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x298))&0xFC00)==0x7C00)) group.long 0x298++0x03 line.long 0x00 "LUT38,LUT 38 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x298))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x298))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x298))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x298))&0xFC00)!=0x7C00)) group.long 0x298++0x03 line.long 0x00 "LUT38,LUT 38 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x298++0x03 line.long 0x00 "LUT38,LUT 38 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x29C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x29C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x29C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x29C))&0xFC00)==0x7C00))) group.long 0x29C++0x03 line.long 0x00 "LUT39,LUT 39 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x29C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x29C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x29C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x29C))&0xFC00)==0x7C00)) group.long 0x29C++0x03 line.long 0x00 "LUT39,LUT 39 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x29C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x29C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x29C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x29C))&0xFC00)!=0x7C00)) group.long 0x29C++0x03 line.long 0x00 "LUT39,LUT 39 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x29C++0x03 line.long 0x00 "LUT39,LUT 39 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x2A0))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2A0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2A0))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2A0))&0xFC00)==0x7C00))) group.long 0x2A0++0x03 line.long 0x00 "LUT40,LUT 40 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2A0))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x2A0))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x2A0))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2A0))&0xFC00)==0x7C00)) group.long 0x2A0++0x03 line.long 0x00 "LUT40,LUT 40 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2A0))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2A0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2A0))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x2A0))&0xFC00)!=0x7C00)) group.long 0x2A0++0x03 line.long 0x00 "LUT40,LUT 40 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2A0++0x03 line.long 0x00 "LUT40,LUT 40 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x2A4))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2A4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2A4))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2A4))&0xFC00)==0x7C00))) group.long 0x2A4++0x03 line.long 0x00 "LUT41,LUT 41 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2A4))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x2A4))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x2A4))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2A4))&0xFC00)==0x7C00)) group.long 0x2A4++0x03 line.long 0x00 "LUT41,LUT 41 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2A4))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2A4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2A4))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x2A4))&0xFC00)!=0x7C00)) group.long 0x2A4++0x03 line.long 0x00 "LUT41,LUT 41 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2A4++0x03 line.long 0x00 "LUT41,LUT 41 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x2A8))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2A8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2A8))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2A8))&0xFC00)==0x7C00))) group.long 0x2A8++0x03 line.long 0x00 "LUT42,LUT 42 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2A8))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x2A8))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x2A8))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2A8))&0xFC00)==0x7C00)) group.long 0x2A8++0x03 line.long 0x00 "LUT42,LUT 42 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2A8))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2A8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2A8))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x2A8))&0xFC00)!=0x7C00)) group.long 0x2A8++0x03 line.long 0x00 "LUT42,LUT 42 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2A8++0x03 line.long 0x00 "LUT42,LUT 42 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x2AC))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2AC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2AC))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2AC))&0xFC00)==0x7C00))) group.long 0x2AC++0x03 line.long 0x00 "LUT43,LUT 43 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2AC))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x2AC))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x2AC))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2AC))&0xFC00)==0x7C00)) group.long 0x2AC++0x03 line.long 0x00 "LUT43,LUT 43 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2AC))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2AC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2AC))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x2AC))&0xFC00)!=0x7C00)) group.long 0x2AC++0x03 line.long 0x00 "LUT43,LUT 43 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2AC++0x03 line.long 0x00 "LUT43,LUT 43 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x2B0))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2B0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2B0))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2B0))&0xFC00)==0x7C00))) group.long 0x2B0++0x03 line.long 0x00 "LUT44,LUT 44 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2B0))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x2B0))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x2B0))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2B0))&0xFC00)==0x7C00)) group.long 0x2B0++0x03 line.long 0x00 "LUT44,LUT 44 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2B0))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2B0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2B0))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x2B0))&0xFC00)!=0x7C00)) group.long 0x2B0++0x03 line.long 0x00 "LUT44,LUT 44 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2B0++0x03 line.long 0x00 "LUT44,LUT 44 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x2B4))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2B4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2B4))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2B4))&0xFC00)==0x7C00))) group.long 0x2B4++0x03 line.long 0x00 "LUT45,LUT 45 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2B4))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x2B4))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x2B4))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2B4))&0xFC00)==0x7C00)) group.long 0x2B4++0x03 line.long 0x00 "LUT45,LUT 45 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2B4))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2B4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2B4))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x2B4))&0xFC00)!=0x7C00)) group.long 0x2B4++0x03 line.long 0x00 "LUT45,LUT 45 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2B4++0x03 line.long 0x00 "LUT45,LUT 45 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x2B8))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2B8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2B8))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2B8))&0xFC00)==0x7C00))) group.long 0x2B8++0x03 line.long 0x00 "LUT46,LUT 46 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2B8))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x2B8))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x2B8))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2B8))&0xFC00)==0x7C00)) group.long 0x2B8++0x03 line.long 0x00 "LUT46,LUT 46 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2B8))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2B8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2B8))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x2B8))&0xFC00)!=0x7C00)) group.long 0x2B8++0x03 line.long 0x00 "LUT46,LUT 46 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2B8++0x03 line.long 0x00 "LUT46,LUT 46 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x2BC))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2BC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2BC))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2BC))&0xFC00)==0x7C00))) group.long 0x2BC++0x03 line.long 0x00 "LUT47,LUT 47 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2BC))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x2BC))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x2BC))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2BC))&0xFC00)==0x7C00)) group.long 0x2BC++0x03 line.long 0x00 "LUT47,LUT 47 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2BC))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2BC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2BC))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x2BC))&0xFC00)!=0x7C00)) group.long 0x2BC++0x03 line.long 0x00 "LUT47,LUT 47 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2BC++0x03 line.long 0x00 "LUT47,LUT 47 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x2C0))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2C0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2C0))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2C0))&0xFC00)==0x7C00))) group.long 0x2C0++0x03 line.long 0x00 "LUT48,LUT 48 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2C0))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x2C0))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x2C0))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2C0))&0xFC00)==0x7C00)) group.long 0x2C0++0x03 line.long 0x00 "LUT48,LUT 48 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2C0))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2C0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2C0))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x2C0))&0xFC00)!=0x7C00)) group.long 0x2C0++0x03 line.long 0x00 "LUT48,LUT 48 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2C0++0x03 line.long 0x00 "LUT48,LUT 48 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x2C4))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2C4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2C4))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2C4))&0xFC00)==0x7C00))) group.long 0x2C4++0x03 line.long 0x00 "LUT49,LUT 49 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2C4))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x2C4))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x2C4))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2C4))&0xFC00)==0x7C00)) group.long 0x2C4++0x03 line.long 0x00 "LUT49,LUT 49 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2C4))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2C4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2C4))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x2C4))&0xFC00)!=0x7C00)) group.long 0x2C4++0x03 line.long 0x00 "LUT49,LUT 49 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2C4++0x03 line.long 0x00 "LUT49,LUT 49 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x2C8))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2C8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2C8))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2C8))&0xFC00)==0x7C00))) group.long 0x2C8++0x03 line.long 0x00 "LUT50,LUT 50 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2C8))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x2C8))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x2C8))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2C8))&0xFC00)==0x7C00)) group.long 0x2C8++0x03 line.long 0x00 "LUT50,LUT 50 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2C8))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2C8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2C8))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x2C8))&0xFC00)!=0x7C00)) group.long 0x2C8++0x03 line.long 0x00 "LUT50,LUT 50 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2C8++0x03 line.long 0x00 "LUT50,LUT 50 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x2CC))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2CC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2CC))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2CC))&0xFC00)==0x7C00))) group.long 0x2CC++0x03 line.long 0x00 "LUT51,LUT 51 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2CC))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x2CC))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x2CC))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2CC))&0xFC00)==0x7C00)) group.long 0x2CC++0x03 line.long 0x00 "LUT51,LUT 51 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2CC))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2CC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2CC))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x2CC))&0xFC00)!=0x7C00)) group.long 0x2CC++0x03 line.long 0x00 "LUT51,LUT 51 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2CC++0x03 line.long 0x00 "LUT51,LUT 51 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x2D0))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2D0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2D0))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2D0))&0xFC00)==0x7C00))) group.long 0x2D0++0x03 line.long 0x00 "LUT52,LUT 52 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2D0))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x2D0))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x2D0))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2D0))&0xFC00)==0x7C00)) group.long 0x2D0++0x03 line.long 0x00 "LUT52,LUT 52 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2D0))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2D0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2D0))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x2D0))&0xFC00)!=0x7C00)) group.long 0x2D0++0x03 line.long 0x00 "LUT52,LUT 52 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2D0++0x03 line.long 0x00 "LUT52,LUT 52 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x2D4))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2D4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2D4))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2D4))&0xFC00)==0x7C00))) group.long 0x2D4++0x03 line.long 0x00 "LUT53,LUT 53 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2D4))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x2D4))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x2D4))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2D4))&0xFC00)==0x7C00)) group.long 0x2D4++0x03 line.long 0x00 "LUT53,LUT 53 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2D4))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2D4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2D4))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x2D4))&0xFC00)!=0x7C00)) group.long 0x2D4++0x03 line.long 0x00 "LUT53,LUT 53 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2D4++0x03 line.long 0x00 "LUT53,LUT 53 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x2D8))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2D8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2D8))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2D8))&0xFC00)==0x7C00))) group.long 0x2D8++0x03 line.long 0x00 "LUT54,LUT 54 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2D8))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x2D8))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x2D8))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2D8))&0xFC00)==0x7C00)) group.long 0x2D8++0x03 line.long 0x00 "LUT54,LUT 54 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2D8))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2D8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2D8))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x2D8))&0xFC00)!=0x7C00)) group.long 0x2D8++0x03 line.long 0x00 "LUT54,LUT 54 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2D8++0x03 line.long 0x00 "LUT54,LUT 54 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x2DC))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2DC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2DC))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2DC))&0xFC00)==0x7C00))) group.long 0x2DC++0x03 line.long 0x00 "LUT55,LUT 55 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2DC))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x2DC))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x2DC))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2DC))&0xFC00)==0x7C00)) group.long 0x2DC++0x03 line.long 0x00 "LUT55,LUT 55 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2DC))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2DC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2DC))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x2DC))&0xFC00)!=0x7C00)) group.long 0x2DC++0x03 line.long 0x00 "LUT55,LUT 55 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2DC++0x03 line.long 0x00 "LUT55,LUT 55 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x2E0))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2E0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2E0))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2E0))&0xFC00)==0x7C00))) group.long 0x2E0++0x03 line.long 0x00 "LUT56,LUT 56 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2E0))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x2E0))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x2E0))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2E0))&0xFC00)==0x7C00)) group.long 0x2E0++0x03 line.long 0x00 "LUT56,LUT 56 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2E0))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2E0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2E0))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x2E0))&0xFC00)!=0x7C00)) group.long 0x2E0++0x03 line.long 0x00 "LUT56,LUT 56 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2E0++0x03 line.long 0x00 "LUT56,LUT 56 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x2E4))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2E4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2E4))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2E4))&0xFC00)==0x7C00))) group.long 0x2E4++0x03 line.long 0x00 "LUT57,LUT 57 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2E4))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x2E4))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x2E4))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2E4))&0xFC00)==0x7C00)) group.long 0x2E4++0x03 line.long 0x00 "LUT57,LUT 57 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2E4))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2E4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2E4))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x2E4))&0xFC00)!=0x7C00)) group.long 0x2E4++0x03 line.long 0x00 "LUT57,LUT 57 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2E4++0x03 line.long 0x00 "LUT57,LUT 57 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x2E8))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2E8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2E8))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2E8))&0xFC00)==0x7C00))) group.long 0x2E8++0x03 line.long 0x00 "LUT58,LUT 58 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2E8))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x2E8))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x2E8))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2E8))&0xFC00)==0x7C00)) group.long 0x2E8++0x03 line.long 0x00 "LUT58,LUT 58 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2E8))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2E8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2E8))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x2E8))&0xFC00)!=0x7C00)) group.long 0x2E8++0x03 line.long 0x00 "LUT58,LUT 58 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2E8++0x03 line.long 0x00 "LUT58,LUT 58 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x2EC))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2EC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2EC))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2EC))&0xFC00)==0x7C00))) group.long 0x2EC++0x03 line.long 0x00 "LUT59,LUT 59 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2EC))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x2EC))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x2EC))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2EC))&0xFC00)==0x7C00)) group.long 0x2EC++0x03 line.long 0x00 "LUT59,LUT 59 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2EC))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2EC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2EC))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x2EC))&0xFC00)!=0x7C00)) group.long 0x2EC++0x03 line.long 0x00 "LUT59,LUT 59 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2EC++0x03 line.long 0x00 "LUT59,LUT 59 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x2F0))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2F0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2F0))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2F0))&0xFC00)==0x7C00))) group.long 0x2F0++0x03 line.long 0x00 "LUT60,LUT 60 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2F0))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x2F0))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x2F0))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2F0))&0xFC00)==0x7C00)) group.long 0x2F0++0x03 line.long 0x00 "LUT60,LUT 60 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2F0))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2F0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2F0))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x2F0))&0xFC00)!=0x7C00)) group.long 0x2F0++0x03 line.long 0x00 "LUT60,LUT 60 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2F0++0x03 line.long 0x00 "LUT60,LUT 60 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x2F4))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2F4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2F4))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2F4))&0xFC00)==0x7C00))) group.long 0x2F4++0x03 line.long 0x00 "LUT61,LUT 61 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2F4))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x2F4))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x2F4))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2F4))&0xFC00)==0x7C00)) group.long 0x2F4++0x03 line.long 0x00 "LUT61,LUT 61 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2F4))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2F4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2F4))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x2F4))&0xFC00)!=0x7C00)) group.long 0x2F4++0x03 line.long 0x00 "LUT61,LUT 61 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2F4++0x03 line.long 0x00 "LUT61,LUT 61 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x2F8))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2F8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2F8))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2F8))&0xFC00)==0x7C00))) group.long 0x2F8++0x03 line.long 0x00 "LUT62,LUT 62 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2F8))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x2F8))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x2F8))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2F8))&0xFC00)==0x7C00)) group.long 0x2F8++0x03 line.long 0x00 "LUT62,LUT 62 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2F8))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2F8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2F8))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x2F8))&0xFC00)!=0x7C00)) group.long 0x2F8++0x03 line.long 0x00 "LUT62,LUT 62 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2F8++0x03 line.long 0x00 "LUT62,LUT 62 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x2FC))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2FC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2FC))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2FC))&0xFC00)==0x7C00))) group.long 0x2FC++0x03 line.long 0x00 "LUT63,LUT 63 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2FC))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x2FC))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x2FC))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x2FC))&0xFC00)==0x7C00)) group.long 0x2FC++0x03 line.long 0x00 "LUT63,LUT 63 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x2FC))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x2FC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x2FC))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x2FC))&0xFC00)!=0x7C00)) group.long 0x2FC++0x03 line.long 0x00 "LUT63,LUT 63 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2FC++0x03 line.long 0x00 "LUT63,LUT 63 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x300))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x300))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x300))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x300))&0xFC00)==0x7C00))) group.long 0x300++0x03 line.long 0x00 "LUT64,LUT 64 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x300))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x300))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x300))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x300))&0xFC00)==0x7C00)) group.long 0x300++0x03 line.long 0x00 "LUT64,LUT 64 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x300))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x300))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x300))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x300))&0xFC00)!=0x7C00)) group.long 0x300++0x03 line.long 0x00 "LUT64,LUT 64 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x300++0x03 line.long 0x00 "LUT64,LUT 64 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x304))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x304))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x304))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x304))&0xFC00)==0x7C00))) group.long 0x304++0x03 line.long 0x00 "LUT65,LUT 65 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x304))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x304))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x304))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x304))&0xFC00)==0x7C00)) group.long 0x304++0x03 line.long 0x00 "LUT65,LUT 65 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x304))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x304))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x304))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x304))&0xFC00)!=0x7C00)) group.long 0x304++0x03 line.long 0x00 "LUT65,LUT 65 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x304++0x03 line.long 0x00 "LUT65,LUT 65 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x308))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x308))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x308))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x308))&0xFC00)==0x7C00))) group.long 0x308++0x03 line.long 0x00 "LUT66,LUT 66 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x308))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x308))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x308))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x308))&0xFC00)==0x7C00)) group.long 0x308++0x03 line.long 0x00 "LUT66,LUT 66 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x308))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x308))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x308))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x308))&0xFC00)!=0x7C00)) group.long 0x308++0x03 line.long 0x00 "LUT66,LUT 66 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x308++0x03 line.long 0x00 "LUT66,LUT 66 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x30C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x30C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x30C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x30C))&0xFC00)==0x7C00))) group.long 0x30C++0x03 line.long 0x00 "LUT67,LUT 67 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x30C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x30C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x30C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x30C))&0xFC00)==0x7C00)) group.long 0x30C++0x03 line.long 0x00 "LUT67,LUT 67 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x30C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x30C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x30C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x30C))&0xFC00)!=0x7C00)) group.long 0x30C++0x03 line.long 0x00 "LUT67,LUT 67 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x30C++0x03 line.long 0x00 "LUT67,LUT 67 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x310))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x310))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x310))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x310))&0xFC00)==0x7C00))) group.long 0x310++0x03 line.long 0x00 "LUT68,LUT 68 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x310))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x310))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x310))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x310))&0xFC00)==0x7C00)) group.long 0x310++0x03 line.long 0x00 "LUT68,LUT 68 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x310))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x310))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x310))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x310))&0xFC00)!=0x7C00)) group.long 0x310++0x03 line.long 0x00 "LUT68,LUT 68 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x310++0x03 line.long 0x00 "LUT68,LUT 68 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x314))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x314))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x314))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x314))&0xFC00)==0x7C00))) group.long 0x314++0x03 line.long 0x00 "LUT69,LUT 69 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x314))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x314))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x314))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x314))&0xFC00)==0x7C00)) group.long 0x314++0x03 line.long 0x00 "LUT69,LUT 69 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x314))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x314))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x314))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x314))&0xFC00)!=0x7C00)) group.long 0x314++0x03 line.long 0x00 "LUT69,LUT 69 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x314++0x03 line.long 0x00 "LUT69,LUT 69 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x318))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x318))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x318))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x318))&0xFC00)==0x7C00))) group.long 0x318++0x03 line.long 0x00 "LUT70,LUT 70 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x318))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x318))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x318))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x318))&0xFC00)==0x7C00)) group.long 0x318++0x03 line.long 0x00 "LUT70,LUT 70 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x318))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x318))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x318))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x318))&0xFC00)!=0x7C00)) group.long 0x318++0x03 line.long 0x00 "LUT70,LUT 70 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x318++0x03 line.long 0x00 "LUT70,LUT 70 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x31C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x31C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x31C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x31C))&0xFC00)==0x7C00))) group.long 0x31C++0x03 line.long 0x00 "LUT71,LUT 71 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x31C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x31C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x31C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x31C))&0xFC00)==0x7C00)) group.long 0x31C++0x03 line.long 0x00 "LUT71,LUT 71 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x31C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x31C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x31C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x31C))&0xFC00)!=0x7C00)) group.long 0x31C++0x03 line.long 0x00 "LUT71,LUT 71 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x31C++0x03 line.long 0x00 "LUT71,LUT 71 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x320))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x320))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x320))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x320))&0xFC00)==0x7C00))) group.long 0x320++0x03 line.long 0x00 "LUT72,LUT 72 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x320))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x320))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x320))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x320))&0xFC00)==0x7C00)) group.long 0x320++0x03 line.long 0x00 "LUT72,LUT 72 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x320))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x320))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x320))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x320))&0xFC00)!=0x7C00)) group.long 0x320++0x03 line.long 0x00 "LUT72,LUT 72 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x320++0x03 line.long 0x00 "LUT72,LUT 72 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x324))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x324))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x324))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x324))&0xFC00)==0x7C00))) group.long 0x324++0x03 line.long 0x00 "LUT73,LUT 73 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x324))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x324))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x324))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x324))&0xFC00)==0x7C00)) group.long 0x324++0x03 line.long 0x00 "LUT73,LUT 73 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x324))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x324))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x324))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x324))&0xFC00)!=0x7C00)) group.long 0x324++0x03 line.long 0x00 "LUT73,LUT 73 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x324++0x03 line.long 0x00 "LUT73,LUT 73 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x328))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x328))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x328))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x328))&0xFC00)==0x7C00))) group.long 0x328++0x03 line.long 0x00 "LUT74,LUT 74 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x328))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x328))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x328))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x328))&0xFC00)==0x7C00)) group.long 0x328++0x03 line.long 0x00 "LUT74,LUT 74 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x328))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x328))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x328))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x328))&0xFC00)!=0x7C00)) group.long 0x328++0x03 line.long 0x00 "LUT74,LUT 74 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x328++0x03 line.long 0x00 "LUT74,LUT 74 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x32C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x32C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x32C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x32C))&0xFC00)==0x7C00))) group.long 0x32C++0x03 line.long 0x00 "LUT75,LUT 75 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x32C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x32C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x32C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x32C))&0xFC00)==0x7C00)) group.long 0x32C++0x03 line.long 0x00 "LUT75,LUT 75 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x32C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x32C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x32C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x32C))&0xFC00)!=0x7C00)) group.long 0x32C++0x03 line.long 0x00 "LUT75,LUT 75 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x32C++0x03 line.long 0x00 "LUT75,LUT 75 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x330))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x330))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x330))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x330))&0xFC00)==0x7C00))) group.long 0x330++0x03 line.long 0x00 "LUT76,LUT 76 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x330))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x330))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x330))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x330))&0xFC00)==0x7C00)) group.long 0x330++0x03 line.long 0x00 "LUT76,LUT 76 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x330))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x330))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x330))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x330))&0xFC00)!=0x7C00)) group.long 0x330++0x03 line.long 0x00 "LUT76,LUT 76 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x330++0x03 line.long 0x00 "LUT76,LUT 76 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x334))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x334))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x334))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x334))&0xFC00)==0x7C00))) group.long 0x334++0x03 line.long 0x00 "LUT77,LUT 77 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x334))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x334))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x334))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x334))&0xFC00)==0x7C00)) group.long 0x334++0x03 line.long 0x00 "LUT77,LUT 77 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x334))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x334))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x334))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x334))&0xFC00)!=0x7C00)) group.long 0x334++0x03 line.long 0x00 "LUT77,LUT 77 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x334++0x03 line.long 0x00 "LUT77,LUT 77 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x338))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x338))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x338))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x338))&0xFC00)==0x7C00))) group.long 0x338++0x03 line.long 0x00 "LUT78,LUT 78 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x338))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x338))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x338))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x338))&0xFC00)==0x7C00)) group.long 0x338++0x03 line.long 0x00 "LUT78,LUT 78 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x338))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x338))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x338))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x338))&0xFC00)!=0x7C00)) group.long 0x338++0x03 line.long 0x00 "LUT78,LUT 78 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x338++0x03 line.long 0x00 "LUT78,LUT 78 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x33C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x33C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x33C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x33C))&0xFC00)==0x7C00))) group.long 0x33C++0x03 line.long 0x00 "LUT79,LUT 79 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x33C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x33C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x33C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x33C))&0xFC00)==0x7C00)) group.long 0x33C++0x03 line.long 0x00 "LUT79,LUT 79 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x33C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x33C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x33C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x33C))&0xFC00)!=0x7C00)) group.long 0x33C++0x03 line.long 0x00 "LUT79,LUT 79 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x33C++0x03 line.long 0x00 "LUT79,LUT 79 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x340))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x340))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x340))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x340))&0xFC00)==0x7C00))) group.long 0x340++0x03 line.long 0x00 "LUT80,LUT 80 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x340))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x340))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x340))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x340))&0xFC00)==0x7C00)) group.long 0x340++0x03 line.long 0x00 "LUT80,LUT 80 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x340))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x340))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x340))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x340))&0xFC00)!=0x7C00)) group.long 0x340++0x03 line.long 0x00 "LUT80,LUT 80 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x340++0x03 line.long 0x00 "LUT80,LUT 80 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x344))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x344))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x344))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x344))&0xFC00)==0x7C00))) group.long 0x344++0x03 line.long 0x00 "LUT81,LUT 81 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x344))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x344))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x344))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x344))&0xFC00)==0x7C00)) group.long 0x344++0x03 line.long 0x00 "LUT81,LUT 81 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x344))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x344))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x344))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x344))&0xFC00)!=0x7C00)) group.long 0x344++0x03 line.long 0x00 "LUT81,LUT 81 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x344++0x03 line.long 0x00 "LUT81,LUT 81 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x348))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x348))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x348))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x348))&0xFC00)==0x7C00))) group.long 0x348++0x03 line.long 0x00 "LUT82,LUT 82 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x348))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x348))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x348))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x348))&0xFC00)==0x7C00)) group.long 0x348++0x03 line.long 0x00 "LUT82,LUT 82 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x348))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x348))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x348))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x348))&0xFC00)!=0x7C00)) group.long 0x348++0x03 line.long 0x00 "LUT82,LUT 82 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x348++0x03 line.long 0x00 "LUT82,LUT 82 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x34C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x34C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x34C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x34C))&0xFC00)==0x7C00))) group.long 0x34C++0x03 line.long 0x00 "LUT83,LUT 83 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x34C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x34C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x34C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x34C))&0xFC00)==0x7C00)) group.long 0x34C++0x03 line.long 0x00 "LUT83,LUT 83 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x34C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x34C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x34C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x34C))&0xFC00)!=0x7C00)) group.long 0x34C++0x03 line.long 0x00 "LUT83,LUT 83 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x34C++0x03 line.long 0x00 "LUT83,LUT 83 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x350))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x350))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x350))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x350))&0xFC00)==0x7C00))) group.long 0x350++0x03 line.long 0x00 "LUT84,LUT 84 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x350))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x350))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x350))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x350))&0xFC00)==0x7C00)) group.long 0x350++0x03 line.long 0x00 "LUT84,LUT 84 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x350))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x350))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x350))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x350))&0xFC00)!=0x7C00)) group.long 0x350++0x03 line.long 0x00 "LUT84,LUT 84 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x350++0x03 line.long 0x00 "LUT84,LUT 84 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x354))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x354))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x354))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x354))&0xFC00)==0x7C00))) group.long 0x354++0x03 line.long 0x00 "LUT85,LUT 85 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x354))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x354))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x354))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x354))&0xFC00)==0x7C00)) group.long 0x354++0x03 line.long 0x00 "LUT85,LUT 85 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x354))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x354))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x354))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x354))&0xFC00)!=0x7C00)) group.long 0x354++0x03 line.long 0x00 "LUT85,LUT 85 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x354++0x03 line.long 0x00 "LUT85,LUT 85 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x358))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x358))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x358))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x358))&0xFC00)==0x7C00))) group.long 0x358++0x03 line.long 0x00 "LUT86,LUT 86 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x358))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x358))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x358))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x358))&0xFC00)==0x7C00)) group.long 0x358++0x03 line.long 0x00 "LUT86,LUT 86 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x358))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x358))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x358))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x358))&0xFC00)!=0x7C00)) group.long 0x358++0x03 line.long 0x00 "LUT86,LUT 86 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x358++0x03 line.long 0x00 "LUT86,LUT 86 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x35C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x35C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x35C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x35C))&0xFC00)==0x7C00))) group.long 0x35C++0x03 line.long 0x00 "LUT87,LUT 87 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x35C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x35C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x35C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x35C))&0xFC00)==0x7C00)) group.long 0x35C++0x03 line.long 0x00 "LUT87,LUT 87 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x35C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x35C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x35C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x35C))&0xFC00)!=0x7C00)) group.long 0x35C++0x03 line.long 0x00 "LUT87,LUT 87 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x35C++0x03 line.long 0x00 "LUT87,LUT 87 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x360))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x360))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x360))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x360))&0xFC00)==0x7C00))) group.long 0x360++0x03 line.long 0x00 "LUT88,LUT 88 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x360))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x360))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x360))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x360))&0xFC00)==0x7C00)) group.long 0x360++0x03 line.long 0x00 "LUT88,LUT 88 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x360))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x360))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x360))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x360))&0xFC00)!=0x7C00)) group.long 0x360++0x03 line.long 0x00 "LUT88,LUT 88 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x360++0x03 line.long 0x00 "LUT88,LUT 88 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x364))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x364))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x364))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x364))&0xFC00)==0x7C00))) group.long 0x364++0x03 line.long 0x00 "LUT89,LUT 89 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x364))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x364))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x364))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x364))&0xFC00)==0x7C00)) group.long 0x364++0x03 line.long 0x00 "LUT89,LUT 89 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x364))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x364))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x364))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x364))&0xFC00)!=0x7C00)) group.long 0x364++0x03 line.long 0x00 "LUT89,LUT 89 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x364++0x03 line.long 0x00 "LUT89,LUT 89 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x368))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x368))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x368))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x368))&0xFC00)==0x7C00))) group.long 0x368++0x03 line.long 0x00 "LUT90,LUT 90 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x368))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x368))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x368))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x368))&0xFC00)==0x7C00)) group.long 0x368++0x03 line.long 0x00 "LUT90,LUT 90 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x368))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x368))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x368))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x368))&0xFC00)!=0x7C00)) group.long 0x368++0x03 line.long 0x00 "LUT90,LUT 90 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x368++0x03 line.long 0x00 "LUT90,LUT 90 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x36C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x36C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x36C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x36C))&0xFC00)==0x7C00))) group.long 0x36C++0x03 line.long 0x00 "LUT91,LUT 91 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x36C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x36C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x36C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x36C))&0xFC00)==0x7C00)) group.long 0x36C++0x03 line.long 0x00 "LUT91,LUT 91 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x36C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x36C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x36C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x36C))&0xFC00)!=0x7C00)) group.long 0x36C++0x03 line.long 0x00 "LUT91,LUT 91 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x36C++0x03 line.long 0x00 "LUT91,LUT 91 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x370))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x370))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x370))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x370))&0xFC00)==0x7C00))) group.long 0x370++0x03 line.long 0x00 "LUT92,LUT 92 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x370))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x370))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x370))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x370))&0xFC00)==0x7C00)) group.long 0x370++0x03 line.long 0x00 "LUT92,LUT 92 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x370))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x370))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x370))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x370))&0xFC00)!=0x7C00)) group.long 0x370++0x03 line.long 0x00 "LUT92,LUT 92 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x370++0x03 line.long 0x00 "LUT92,LUT 92 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x374))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x374))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x374))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x374))&0xFC00)==0x7C00))) group.long 0x374++0x03 line.long 0x00 "LUT93,LUT 93 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x374))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x374))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x374))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x374))&0xFC00)==0x7C00)) group.long 0x374++0x03 line.long 0x00 "LUT93,LUT 93 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x374))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x374))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x374))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x374))&0xFC00)!=0x7C00)) group.long 0x374++0x03 line.long 0x00 "LUT93,LUT 93 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x374++0x03 line.long 0x00 "LUT93,LUT 93 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x378))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x378))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x378))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x378))&0xFC00)==0x7C00))) group.long 0x378++0x03 line.long 0x00 "LUT94,LUT 94 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x378))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x378))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x378))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x378))&0xFC00)==0x7C00)) group.long 0x378++0x03 line.long 0x00 "LUT94,LUT 94 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x378))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x378))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x378))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x378))&0xFC00)!=0x7C00)) group.long 0x378++0x03 line.long 0x00 "LUT94,LUT 94 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x378++0x03 line.long 0x00 "LUT94,LUT 94 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x37C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x37C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x37C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x37C))&0xFC00)==0x7C00))) group.long 0x37C++0x03 line.long 0x00 "LUT95,LUT 95 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x37C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x37C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x37C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x37C))&0xFC00)==0x7C00)) group.long 0x37C++0x03 line.long 0x00 "LUT95,LUT 95 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x37C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x37C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x37C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x37C))&0xFC00)!=0x7C00)) group.long 0x37C++0x03 line.long 0x00 "LUT95,LUT 95 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x37C++0x03 line.long 0x00 "LUT95,LUT 95 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x380))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x380))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x380))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x380))&0xFC00)==0x7C00))) group.long 0x380++0x03 line.long 0x00 "LUT96,LUT 96 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x380))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x380))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x380))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x380))&0xFC00)==0x7C00)) group.long 0x380++0x03 line.long 0x00 "LUT96,LUT 96 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x380))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x380))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x380))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x380))&0xFC00)!=0x7C00)) group.long 0x380++0x03 line.long 0x00 "LUT96,LUT 96 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x380++0x03 line.long 0x00 "LUT96,LUT 96 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x384))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x384))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x384))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x384))&0xFC00)==0x7C00))) group.long 0x384++0x03 line.long 0x00 "LUT97,LUT 97 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x384))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x384))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x384))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x384))&0xFC00)==0x7C00)) group.long 0x384++0x03 line.long 0x00 "LUT97,LUT 97 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x384))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x384))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x384))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x384))&0xFC00)!=0x7C00)) group.long 0x384++0x03 line.long 0x00 "LUT97,LUT 97 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x384++0x03 line.long 0x00 "LUT97,LUT 97 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x388))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x388))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x388))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x388))&0xFC00)==0x7C00))) group.long 0x388++0x03 line.long 0x00 "LUT98,LUT 98 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x388))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x388))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x388))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x388))&0xFC00)==0x7C00)) group.long 0x388++0x03 line.long 0x00 "LUT98,LUT 98 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x388))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x388))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x388))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x388))&0xFC00)!=0x7C00)) group.long 0x388++0x03 line.long 0x00 "LUT98,LUT 98 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x388++0x03 line.long 0x00 "LUT98,LUT 98 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x38C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x38C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x38C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x38C))&0xFC00)==0x7C00))) group.long 0x38C++0x03 line.long 0x00 "LUT99,LUT 99 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x38C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x38C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x38C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x38C))&0xFC00)==0x7C00)) group.long 0x38C++0x03 line.long 0x00 "LUT99,LUT 99 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x38C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x38C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x38C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x38C))&0xFC00)!=0x7C00)) group.long 0x38C++0x03 line.long 0x00 "LUT99,LUT 99 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x38C++0x03 line.long 0x00 "LUT99,LUT 99 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x390))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x390))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x390))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x390))&0xFC00)==0x7C00))) group.long 0x390++0x03 line.long 0x00 "LUT100,LUT 100 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x390))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x390))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x390))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x390))&0xFC00)==0x7C00)) group.long 0x390++0x03 line.long 0x00 "LUT100,LUT 100 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x390))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x390))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x390))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x390))&0xFC00)!=0x7C00)) group.long 0x390++0x03 line.long 0x00 "LUT100,LUT 100 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x390++0x03 line.long 0x00 "LUT100,LUT 100 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x394))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x394))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x394))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x394))&0xFC00)==0x7C00))) group.long 0x394++0x03 line.long 0x00 "LUT101,LUT 101 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x394))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x394))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x394))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x394))&0xFC00)==0x7C00)) group.long 0x394++0x03 line.long 0x00 "LUT101,LUT 101 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x394))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x394))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x394))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x394))&0xFC00)!=0x7C00)) group.long 0x394++0x03 line.long 0x00 "LUT101,LUT 101 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x394++0x03 line.long 0x00 "LUT101,LUT 101 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x398))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x398))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x398))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x398))&0xFC00)==0x7C00))) group.long 0x398++0x03 line.long 0x00 "LUT102,LUT 102 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x398))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x398))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x398))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x398))&0xFC00)==0x7C00)) group.long 0x398++0x03 line.long 0x00 "LUT102,LUT 102 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x398))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x398))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x398))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x398))&0xFC00)!=0x7C00)) group.long 0x398++0x03 line.long 0x00 "LUT102,LUT 102 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x398++0x03 line.long 0x00 "LUT102,LUT 102 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x39C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x39C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x39C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x39C))&0xFC00)==0x7C00))) group.long 0x39C++0x03 line.long 0x00 "LUT103,LUT 103 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x39C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x39C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x39C))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x39C))&0xFC00)==0x7C00)) group.long 0x39C++0x03 line.long 0x00 "LUT103,LUT 103 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x39C))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x39C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x39C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x39C))&0xFC00)!=0x7C00)) group.long 0x39C++0x03 line.long 0x00 "LUT103,LUT 103 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x39C++0x03 line.long 0x00 "LUT103,LUT 103 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x3A0))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3A0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3A0))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3A0))&0xFC00)==0x7C00))) group.long 0x3A0++0x03 line.long 0x00 "LUT104,LUT 104 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3A0))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x3A0))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x3A0))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3A0))&0xFC00)==0x7C00)) group.long 0x3A0++0x03 line.long 0x00 "LUT104,LUT 104 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3A0))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3A0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3A0))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x3A0))&0xFC00)!=0x7C00)) group.long 0x3A0++0x03 line.long 0x00 "LUT104,LUT 104 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3A0++0x03 line.long 0x00 "LUT104,LUT 104 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x3A4))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3A4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3A4))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3A4))&0xFC00)==0x7C00))) group.long 0x3A4++0x03 line.long 0x00 "LUT105,LUT 105 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3A4))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x3A4))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x3A4))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3A4))&0xFC00)==0x7C00)) group.long 0x3A4++0x03 line.long 0x00 "LUT105,LUT 105 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3A4))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3A4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3A4))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x3A4))&0xFC00)!=0x7C00)) group.long 0x3A4++0x03 line.long 0x00 "LUT105,LUT 105 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3A4++0x03 line.long 0x00 "LUT105,LUT 105 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x3A8))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3A8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3A8))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3A8))&0xFC00)==0x7C00))) group.long 0x3A8++0x03 line.long 0x00 "LUT106,LUT 106 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3A8))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x3A8))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x3A8))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3A8))&0xFC00)==0x7C00)) group.long 0x3A8++0x03 line.long 0x00 "LUT106,LUT 106 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3A8))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3A8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3A8))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x3A8))&0xFC00)!=0x7C00)) group.long 0x3A8++0x03 line.long 0x00 "LUT106,LUT 106 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3A8++0x03 line.long 0x00 "LUT106,LUT 106 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x3AC))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3AC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3AC))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3AC))&0xFC00)==0x7C00))) group.long 0x3AC++0x03 line.long 0x00 "LUT107,LUT 107 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3AC))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x3AC))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x3AC))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3AC))&0xFC00)==0x7C00)) group.long 0x3AC++0x03 line.long 0x00 "LUT107,LUT 107 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3AC))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3AC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3AC))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x3AC))&0xFC00)!=0x7C00)) group.long 0x3AC++0x03 line.long 0x00 "LUT107,LUT 107 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3AC++0x03 line.long 0x00 "LUT107,LUT 107 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x3B0))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3B0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3B0))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3B0))&0xFC00)==0x7C00))) group.long 0x3B0++0x03 line.long 0x00 "LUT108,LUT 108 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3B0))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x3B0))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x3B0))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3B0))&0xFC00)==0x7C00)) group.long 0x3B0++0x03 line.long 0x00 "LUT108,LUT 108 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3B0))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3B0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3B0))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x3B0))&0xFC00)!=0x7C00)) group.long 0x3B0++0x03 line.long 0x00 "LUT108,LUT 108 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3B0++0x03 line.long 0x00 "LUT108,LUT 108 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x3B4))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3B4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3B4))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3B4))&0xFC00)==0x7C00))) group.long 0x3B4++0x03 line.long 0x00 "LUT109,LUT 109 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3B4))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x3B4))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x3B4))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3B4))&0xFC00)==0x7C00)) group.long 0x3B4++0x03 line.long 0x00 "LUT109,LUT 109 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3B4))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3B4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3B4))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x3B4))&0xFC00)!=0x7C00)) group.long 0x3B4++0x03 line.long 0x00 "LUT109,LUT 109 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3B4++0x03 line.long 0x00 "LUT109,LUT 109 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x3B8))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3B8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3B8))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3B8))&0xFC00)==0x7C00))) group.long 0x3B8++0x03 line.long 0x00 "LUT110,LUT 110 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3B8))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x3B8))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x3B8))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3B8))&0xFC00)==0x7C00)) group.long 0x3B8++0x03 line.long 0x00 "LUT110,LUT 110 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3B8))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3B8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3B8))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x3B8))&0xFC00)!=0x7C00)) group.long 0x3B8++0x03 line.long 0x00 "LUT110,LUT 110 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3B8++0x03 line.long 0x00 "LUT110,LUT 110 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x3BC))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3BC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3BC))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3BC))&0xFC00)==0x7C00))) group.long 0x3BC++0x03 line.long 0x00 "LUT111,LUT 111 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3BC))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x3BC))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x3BC))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3BC))&0xFC00)==0x7C00)) group.long 0x3BC++0x03 line.long 0x00 "LUT111,LUT 111 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3BC))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3BC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3BC))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x3BC))&0xFC00)!=0x7C00)) group.long 0x3BC++0x03 line.long 0x00 "LUT111,LUT 111 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3BC++0x03 line.long 0x00 "LUT111,LUT 111 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x3C0))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3C0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3C0))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3C0))&0xFC00)==0x7C00))) group.long 0x3C0++0x03 line.long 0x00 "LUT112,LUT 112 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3C0))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x3C0))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x3C0))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3C0))&0xFC00)==0x7C00)) group.long 0x3C0++0x03 line.long 0x00 "LUT112,LUT 112 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3C0))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3C0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3C0))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x3C0))&0xFC00)!=0x7C00)) group.long 0x3C0++0x03 line.long 0x00 "LUT112,LUT 112 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3C0++0x03 line.long 0x00 "LUT112,LUT 112 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x3C4))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3C4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3C4))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3C4))&0xFC00)==0x7C00))) group.long 0x3C4++0x03 line.long 0x00 "LUT113,LUT 113 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3C4))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x3C4))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x3C4))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3C4))&0xFC00)==0x7C00)) group.long 0x3C4++0x03 line.long 0x00 "LUT113,LUT 113 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3C4))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3C4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3C4))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x3C4))&0xFC00)!=0x7C00)) group.long 0x3C4++0x03 line.long 0x00 "LUT113,LUT 113 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3C4++0x03 line.long 0x00 "LUT113,LUT 113 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x3C8))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3C8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3C8))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3C8))&0xFC00)==0x7C00))) group.long 0x3C8++0x03 line.long 0x00 "LUT114,LUT 114 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3C8))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x3C8))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x3C8))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3C8))&0xFC00)==0x7C00)) group.long 0x3C8++0x03 line.long 0x00 "LUT114,LUT 114 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3C8))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3C8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3C8))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x3C8))&0xFC00)!=0x7C00)) group.long 0x3C8++0x03 line.long 0x00 "LUT114,LUT 114 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3C8++0x03 line.long 0x00 "LUT114,LUT 114 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x3CC))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3CC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3CC))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3CC))&0xFC00)==0x7C00))) group.long 0x3CC++0x03 line.long 0x00 "LUT115,LUT 115 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3CC))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x3CC))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x3CC))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3CC))&0xFC00)==0x7C00)) group.long 0x3CC++0x03 line.long 0x00 "LUT115,LUT 115 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3CC))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3CC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3CC))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x3CC))&0xFC00)!=0x7C00)) group.long 0x3CC++0x03 line.long 0x00 "LUT115,LUT 115 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3CC++0x03 line.long 0x00 "LUT115,LUT 115 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x3D0))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3D0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3D0))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3D0))&0xFC00)==0x7C00))) group.long 0x3D0++0x03 line.long 0x00 "LUT116,LUT 116 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3D0))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x3D0))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x3D0))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3D0))&0xFC00)==0x7C00)) group.long 0x3D0++0x03 line.long 0x00 "LUT116,LUT 116 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3D0))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3D0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3D0))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x3D0))&0xFC00)!=0x7C00)) group.long 0x3D0++0x03 line.long 0x00 "LUT116,LUT 116 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3D0++0x03 line.long 0x00 "LUT116,LUT 116 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x3D4))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3D4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3D4))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3D4))&0xFC00)==0x7C00))) group.long 0x3D4++0x03 line.long 0x00 "LUT117,LUT 117 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3D4))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x3D4))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x3D4))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3D4))&0xFC00)==0x7C00)) group.long 0x3D4++0x03 line.long 0x00 "LUT117,LUT 117 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3D4))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3D4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3D4))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x3D4))&0xFC00)!=0x7C00)) group.long 0x3D4++0x03 line.long 0x00 "LUT117,LUT 117 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3D4++0x03 line.long 0x00 "LUT117,LUT 117 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x3D8))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3D8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3D8))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3D8))&0xFC00)==0x7C00))) group.long 0x3D8++0x03 line.long 0x00 "LUT118,LUT 118 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3D8))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x3D8))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x3D8))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3D8))&0xFC00)==0x7C00)) group.long 0x3D8++0x03 line.long 0x00 "LUT118,LUT 118 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3D8))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3D8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3D8))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x3D8))&0xFC00)!=0x7C00)) group.long 0x3D8++0x03 line.long 0x00 "LUT118,LUT 118 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3D8++0x03 line.long 0x00 "LUT118,LUT 118 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x3DC))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3DC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3DC))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3DC))&0xFC00)==0x7C00))) group.long 0x3DC++0x03 line.long 0x00 "LUT119,LUT 119 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3DC))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x3DC))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x3DC))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3DC))&0xFC00)==0x7C00)) group.long 0x3DC++0x03 line.long 0x00 "LUT119,LUT 119 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3DC))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3DC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3DC))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x3DC))&0xFC00)!=0x7C00)) group.long 0x3DC++0x03 line.long 0x00 "LUT119,LUT 119 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3DC++0x03 line.long 0x00 "LUT119,LUT 119 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x3E0))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3E0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3E0))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3E0))&0xFC00)==0x7C00))) group.long 0x3E0++0x03 line.long 0x00 "LUT120,LUT 120 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3E0))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x3E0))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x3E0))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3E0))&0xFC00)==0x7C00)) group.long 0x3E0++0x03 line.long 0x00 "LUT120,LUT 120 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3E0))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3E0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3E0))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x3E0))&0xFC00)!=0x7C00)) group.long 0x3E0++0x03 line.long 0x00 "LUT120,LUT 120 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3E0++0x03 line.long 0x00 "LUT120,LUT 120 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x3E4))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3E4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3E4))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3E4))&0xFC00)==0x7C00))) group.long 0x3E4++0x03 line.long 0x00 "LUT121,LUT 121 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3E4))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x3E4))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x3E4))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3E4))&0xFC00)==0x7C00)) group.long 0x3E4++0x03 line.long 0x00 "LUT121,LUT 121 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3E4))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3E4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3E4))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x3E4))&0xFC00)!=0x7C00)) group.long 0x3E4++0x03 line.long 0x00 "LUT121,LUT 121 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3E4++0x03 line.long 0x00 "LUT121,LUT 121 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x3E8))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3E8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3E8))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3E8))&0xFC00)==0x7C00))) group.long 0x3E8++0x03 line.long 0x00 "LUT122,LUT 122 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3E8))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x3E8))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x3E8))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3E8))&0xFC00)==0x7C00)) group.long 0x3E8++0x03 line.long 0x00 "LUT122,LUT 122 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3E8))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3E8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3E8))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x3E8))&0xFC00)!=0x7C00)) group.long 0x3E8++0x03 line.long 0x00 "LUT122,LUT 122 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3E8++0x03 line.long 0x00 "LUT122,LUT 122 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x3EC))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3EC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3EC))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3EC))&0xFC00)==0x7C00))) group.long 0x3EC++0x03 line.long 0x00 "LUT123,LUT 123 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3EC))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x3EC))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x3EC))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3EC))&0xFC00)==0x7C00)) group.long 0x3EC++0x03 line.long 0x00 "LUT123,LUT 123 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3EC))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3EC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3EC))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x3EC))&0xFC00)!=0x7C00)) group.long 0x3EC++0x03 line.long 0x00 "LUT123,LUT 123 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3EC++0x03 line.long 0x00 "LUT123,LUT 123 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x3F0))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3F0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3F0))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3F0))&0xFC00)==0x7C00))) group.long 0x3F0++0x03 line.long 0x00 "LUT124,LUT 124 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3F0))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x3F0))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x3F0))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3F0))&0xFC00)==0x7C00)) group.long 0x3F0++0x03 line.long 0x00 "LUT124,LUT 124 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3F0))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3F0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3F0))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x3F0))&0xFC00)!=0x7C00)) group.long 0x3F0++0x03 line.long 0x00 "LUT124,LUT 124 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3F0++0x03 line.long 0x00 "LUT124,LUT 124 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x3F4))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3F4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3F4))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3F4))&0xFC00)==0x7C00))) group.long 0x3F4++0x03 line.long 0x00 "LUT125,LUT 125 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3F4))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x3F4))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x3F4))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3F4))&0xFC00)==0x7C00)) group.long 0x3F4++0x03 line.long 0x00 "LUT125,LUT 125 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3F4))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3F4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3F4))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x3F4))&0xFC00)!=0x7C00)) group.long 0x3F4++0x03 line.long 0x00 "LUT125,LUT 125 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3F4++0x03 line.long 0x00 "LUT125,LUT 125 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x3F8))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3F8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3F8))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3F8))&0xFC00)==0x7C00))) group.long 0x3F8++0x03 line.long 0x00 "LUT126,LUT 126 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3F8))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x3F8))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x3F8))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3F8))&0xFC00)==0x7C00)) group.long 0x3F8++0x03 line.long 0x00 "LUT126,LUT 126 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3F8))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3F8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3F8))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x3F8))&0xFC00)!=0x7C00)) group.long 0x3F8++0x03 line.long 0x00 "LUT126,LUT 126 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3F8++0x03 line.long 0x00 "LUT126,LUT 126 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D120000+0x3FC))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3FC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3FC))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3FC))&0xFC00)==0x7C00))) group.long 0x3FC++0x03 line.long 0x00 "LUT127,LUT 127 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3FC))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D120000+0x3FC))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D120000+0x3FC))&0xFC00)==0x00)||(((per.l(ad:0x5D120000+0x3FC))&0xFC00)==0x7C00)) group.long 0x3FC++0x03 line.long 0x00 "LUT127,LUT 127 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D120000+0x3FC))&0xFC000000)==0x00)||(((per.l(ad:0x5D120000+0x3FC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D120000+0x3FC))&0xFC00)!=0x00)&&(((per.l(ad:0x5D120000+0x3FC))&0xFC00)!=0x7C00)) group.long 0x3FC++0x03 line.long 0x00 "LUT127,LUT 127 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3FC++0x03 line.long 0x00 "LUT127,LUT 127 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif tree.end width 0x0B tree.end tree "FLEXSPI1" base ad:0x5D130000 width 14. group.long 0x00++0x1F line.long 0x00 "MCR0,Module Control Register 0" hexmask.long.byte 0x00 24.--31. 1. " AHBGRANTWAIT ,Timeout wait cycle for AHB command grant" hexmask.long.byte 0x00 16.--23. 1. " IPGRANTWAIT ,Time out wait cycle for IP command grant" bitfld.long 0x00 15. " LEARNEN ,Data learning feature enable" "Disabled,Enabled" newline bitfld.long 0x00 14. " SCKFREERUNEN ,Force SCK output free-running enable" "Disabled,Enabled" bitfld.long 0x00 13. " COMBINATIONEN ,Support flash octal mode access" "Disabled,Enabled" bitfld.long 0x00 12. " DOZEEN ,Doze mode enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " HSEN ,Half speed serial flash access enable" "Disabled,Enabled" bitfld.long 0x00 8.--10. " SERCLKDIV ,The serial root clock could be divided inside FlexSPI" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 7. " ATDFEN ,AHB bus write access to IP TX FIFO enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " ARDFEN ,AHB bus read access to IP RX FIFO enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " RXCLKSRC ,Sample clock source selection for flash reading" "Internally,DQS,,Flash" bitfld.long 0x00 1. " MDIS ,Module disable" "No,Yes" newline bitfld.long 0x00 0. " SWRESET ,Software reset" "No reset,Reset" line.long 0x04 "MCR1,Module Control Register 1" hexmask.long.word 0x04 16.--31. 1. " SEQWAIT ,Command sequence execution" hexmask.long.word 0x04 0.--15. 1. " AHBBUSWAIT ,AHB read/write access" line.long 0x08 "MCR2,Module Control Register 2" hexmask.long.byte 0x08 24.--31. 1. " RESUMEWAIT ,Wait cycle for idle state before suspended command sequence resumed" bitfld.long 0x08 19. " SCKBDIFFOPT ,Use SCKB pad as SCKA differential clock output" "Not used,Used" bitfld.long 0x08 15. " SAMEDEVICEEN ,All external devices are same devices" "Disabled,Enabled" newline bitfld.long 0x08 14. " CLRLEARNPHASE ,The sampling clock phase selection reset" "No reset,Reset" bitfld.long 0x08 11. " CLRAHBBUFOPT ,AHB RX/TX buffer clean automatically enable" "Disabled,Enabled" line.long 0x0C "AHBCR,AHB Bus Control Register" bitfld.long 0x0C 6. " READADDROPT ,AHB read address option" "Read burst,No read burst" bitfld.long 0x0C 5. " PREFETCHEN ,AHB read prefetch enable" "Disabled,Enabled" bitfld.long 0x0C 4. " BUFFERABLEEN ,AHB bus bufferable write access support enable" "Disabled,Enabled" newline bitfld.long 0x0C 3. " CACHABLEEN ,AHB bus cachable read access support enable" "Disabled,Enabled" bitfld.long 0x0C 0. " APAREN ,Parallel mode enabled for AHB triggered command" "Individual,Parallel" line.long 0x10 "INTEN,Interrupt Enable Register" bitfld.long 0x10 11. " SEQTIMEOUTEN ,Sequence execution timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x10 10. " AHBBUSTIMEOUTEN ,AHB Bus timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x10 9. " SCKSTOPBYWREN ,SCK is stopped during command sequence because async TX FIFO empty interrupt enable" "Disabled,Enabled" newline bitfld.long 0x10 8. " SCKSTOPBYRDEN ,SCK is stopped during command sequence because async RX FIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x10 7. " DATALEARNFAILEN ,Data learning failed interrupt enable" "Disabled,Enabled" bitfld.long 0x10 6. " IPTXWEEN ,IP TX FIFO watermark empty interrupt enable" "Disabled,Enabled" newline bitfld.long 0x10 5. " IPRXWAEN ,IP RX FIFO watermark available interrupt enable" "Disabled,Enabled" bitfld.long 0x10 4. " AHBCMDERREN ,AHB triggered command sequences error detected interrupt enable" "Disabled,Enabled" bitfld.long 0x10 3. " IPCMDERREN ,IP triggered command sequences error detected interrupt enable" "Disabled,Enabled" newline bitfld.long 0x10 2. " AHBCMDGEEN ,AHB triggered command sequences grant timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x10 1. " IPCMDGEEN ,IP triggered command sequences grant timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x10 0. " IPCMDDONEEN ,IP triggered command sequences execution finished interrupt enable" "Disabled,Enabled" newline line.long 0x14 "INTR,Interrupt Register" eventfld.long 0x14 11. " SEQTIMEOUT ,Sequence execution timeout interrupt" "No interrupt,Interrupt" eventfld.long 0x14 10. " AHBBUSTIMEOUT ,AHB bus timeout interrupt" "No interrupt,Interrupt" eventfld.long 0x14 9. " SCKSTOPBYWR ,SCK is stopped during command sequence because async TX FIFO empty interrupt" "No interrupt,Interrupt" newline eventfld.long 0x14 8. " SCKSTOPBYRD ,SCK is stopped during command sequence because async RX FIFO full interrupt" "No interrupt,Interrupt" eventfld.long 0x14 7. " DATALEARNFAIL ,Data learning failed interrupt" "No interrupt,Interrupt" eventfld.long 0x14 6. " IPTXWE ,IP TX FIFO watermark empty interrupt" "No interrupt,Interrupt" newline eventfld.long 0x14 5. " IPRXWA ,IP RX FIFO watermark available interrupt" "No interrupt,Interrupt" eventfld.long 0x14 4. " AHBCMDERR ,AHB triggered command sequences error detected interrupt" "No interrupt,Interrupt" eventfld.long 0x14 3. " IPCMDERR ,IP triggered command sequences error detected interrupt" "No interrupt,Interrupt" newline eventfld.long 0x14 2. " AHBCMDGE ,AHB triggered command sequences grant timeout interrupt" "No interrupt,Interrupt" eventfld.long 0x14 1. " IPCMDGE ,P triggered command sequences grant timeout interrupt" "No interrupt,Interrupt" eventfld.long 0x14 0. " IPCMDDONE ,IP triggered command sequences execution finished interrupt" "No interrupt,Interrupt" newline line.long 0x18 "LUTKEY,LUT Key Register" line.long 0x1C "LUTCR,LUT Control Register" bitfld.long 0x1C 0.--1. " UNLOCK_LOCK ,LUT lock" ",Locked,Unlocked,?..." group.long 0x20++0x03 line.long 0x00 "AHBRXBUF0CR0,AHB RX Buffer 0 Control Register 0" bitfld.long 0x00 31. " PREFETCHEN ,AHB read prefetch enable" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PRIORITY ,AHB master read priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " MSTRID ,ID of AHB master associated with this buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--8. 1. " BUFSZ ,AHB RX buffer size in 64 bits" group.long 0x24++0x03 line.long 0x00 "AHBRXBUF1CR0,AHB RX Buffer 1 Control Register 0" bitfld.long 0x00 31. " PREFETCHEN ,AHB read prefetch enable" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PRIORITY ,AHB master read priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " MSTRID ,ID of AHB master associated with this buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--8. 1. " BUFSZ ,AHB RX buffer size in 64 bits" group.long 0x28++0x03 line.long 0x00 "AHBRXBUF2CR0,AHB RX Buffer 2 Control Register 0" bitfld.long 0x00 31. " PREFETCHEN ,AHB read prefetch enable" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PRIORITY ,AHB master read priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " MSTRID ,ID of AHB master associated with this buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--8. 1. " BUFSZ ,AHB RX buffer size in 64 bits" group.long 0x2C++0x03 line.long 0x00 "AHBRXBUF3CR0,AHB RX Buffer 3 Control Register 0" bitfld.long 0x00 31. " PREFETCHEN ,AHB read prefetch enable" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PRIORITY ,AHB master read priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " MSTRID ,ID of AHB master associated with this buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--8. 1. " BUFSZ ,AHB RX buffer size in 64 bits" group.long 0x30++0x03 line.long 0x00 "AHBRXBUF4CR0,AHB RX Buffer 4 Control Register 0" bitfld.long 0x00 31. " PREFETCHEN ,AHB read prefetch enable" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PRIORITY ,AHB master read priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " MSTRID ,ID of AHB master associated with this buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--8. 1. " BUFSZ ,AHB RX buffer size in 64 bits" group.long 0x34++0x03 line.long 0x00 "AHBRXBUF5CR0,AHB RX Buffer 5 Control Register 0" bitfld.long 0x00 31. " PREFETCHEN ,AHB read prefetch enable" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PRIORITY ,AHB master read priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " MSTRID ,ID of AHB master associated with this buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--8. 1. " BUFSZ ,AHB RX buffer size in 64 bits" group.long 0x38++0x03 line.long 0x00 "AHBRXBUF6CR0,AHB RX Buffer 6 Control Register 0" bitfld.long 0x00 31. " PREFETCHEN ,AHB read prefetch enable" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PRIORITY ,AHB master read priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " MSTRID ,ID of AHB master associated with this buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--8. 1. " BUFSZ ,AHB RX buffer size in 64 bits" group.long 0x3C++0x03 line.long 0x00 "AHBRXBUF7CR0,AHB RX Buffer 7 Control Register 0" bitfld.long 0x00 31. " PREFETCHEN ,AHB read prefetch enable" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PRIORITY ,AHB master read priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " MSTRID ,ID of AHB master associated with this buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--8. 1. " BUFSZ ,AHB RX buffer size in 64 bits" group.long 0x60++0x03 line.long 0x00 "FLSHA1CR0,Flash A1 Control 0 Register" hexmask.long.tbyte 0x00 0.--22. 1. " FLSHSZ ,Flash size in KB" group.long 0x64++0x03 line.long 0x00 "FLSHA2CR0,Flash A2 Control 0 Register" hexmask.long.tbyte 0x00 0.--22. 1. " FLSHSZ ,Flash size in KB" group.long 0x68++0x03 line.long 0x00 "FLSHB1CR0,Flash B1 Control 0 Register" hexmask.long.tbyte 0x00 0.--22. 1. " FLSHSZ ,Flash size in KB" group.long 0x6C++0x03 line.long 0x00 "FLSHB2CR0,Flash B2 Control 0 Register" hexmask.long.tbyte 0x00 0.--22. 1. " FLSHSZ ,Flash size in KB" group.long 0x70++0x03 line.long 0x00 "FLSHA1CR1,Flash A1 Control 1 Register" hexmask.long.word 0x00 16.--31. 1. " CSINTERVAL ,Used to set the minimum interval between flash device chip selection deassertion and flash device chip selection assertion" bitfld.long 0x00 15. " CSINTERVALUNIT ,CS interval unit" "1 cycle,256 cycles" bitfld.long 0x00 11.--14. " CAS ,Column address size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10. " WA ,Word addressable" "Disabled,Enabled" bitfld.long 0x00 5.--9. " TCSH ,Serial flash CS hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " TCSS ,Serial flash CS setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x74++0x03 line.long 0x00 "FLSHA2CR1,Flash A2 Control 1 Register" hexmask.long.word 0x00 16.--31. 1. " CSINTERVAL ,Used to set the minimum interval between flash device chip selection deassertion and flash device chip selection assertion" bitfld.long 0x00 15. " CSINTERVALUNIT ,CS interval unit" "1 cycle,256 cycles" bitfld.long 0x00 11.--14. " CAS ,Column address size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10. " WA ,Word addressable" "Disabled,Enabled" bitfld.long 0x00 5.--9. " TCSH ,Serial flash CS hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " TCSS ,Serial flash CS setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x78++0x03 line.long 0x00 "FLSHB1CR1,Flash B1 Control 1 Register" hexmask.long.word 0x00 16.--31. 1. " CSINTERVAL ,Used to set the minimum interval between flash device chip selection deassertion and flash device chip selection assertion" bitfld.long 0x00 15. " CSINTERVALUNIT ,CS interval unit" "1 cycle,256 cycles" bitfld.long 0x00 11.--14. " CAS ,Column address size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10. " WA ,Word addressable" "Disabled,Enabled" bitfld.long 0x00 5.--9. " TCSH ,Serial flash CS hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " TCSS ,Serial flash CS setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x7C++0x03 line.long 0x00 "FLSHB2CR1,Flash B2 Control 1 Register" hexmask.long.word 0x00 16.--31. 1. " CSINTERVAL ,Used to set the minimum interval between flash device chip selection deassertion and flash device chip selection assertion" bitfld.long 0x00 15. " CSINTERVALUNIT ,CS interval unit" "1 cycle,256 cycles" bitfld.long 0x00 11.--14. " CAS ,Column address size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10. " WA ,Word addressable" "Disabled,Enabled" bitfld.long 0x00 5.--9. " TCSH ,Serial flash CS hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " TCSS ,Serial flash CS setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x80++0x03 line.long 0x00 "FLSHA1CR2,Flash A1 Control 2 Register" bitfld.long 0x00 31. " CLRINSTRPTR ,Clear the instruction pointer" "Not cleared,Cleared" bitfld.long 0x00 28.--30. " AWRWAITUNIT ,AWRWAIT unit" "2 cycles,8 cycles,32 cycles,128 cycles,512 cycles,2048 cycles,8192 cycles,32768 cycles" hexmask.long.word 0x00 16.--27. 1. " AWRWAIT ,Time to write data into internal memory" newline bitfld.long 0x00 13.--15. " AWRSEQNUM ,Sequence number for AHB write triggered command" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--12. " AWRSEQID ,Sequence index for AHB write triggered command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--7. " ARDSEQNUM ,Sequence number for AHB read triggered command in LUT" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--4. " ARDSEQID ,Sequence index for AHB read triggered command in LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x84++0x03 line.long 0x00 "FLSHA2CR2,Flash A2 Control 2 Register" bitfld.long 0x00 31. " CLRINSTRPTR ,Clear the instruction pointer" "Not cleared,Cleared" bitfld.long 0x00 28.--30. " AWRWAITUNIT ,AWRWAIT unit" "2 cycles,8 cycles,32 cycles,128 cycles,512 cycles,2048 cycles,8192 cycles,32768 cycles" hexmask.long.word 0x00 16.--27. 1. " AWRWAIT ,Time to write data into internal memory" newline bitfld.long 0x00 13.--15. " AWRSEQNUM ,Sequence number for AHB write triggered command" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--12. " AWRSEQID ,Sequence index for AHB write triggered command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--7. " ARDSEQNUM ,Sequence number for AHB read triggered command in LUT" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--4. " ARDSEQID ,Sequence index for AHB read triggered command in LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x88++0x03 line.long 0x00 "FLSHB1CR2,Flash B1 Control 2 Register" bitfld.long 0x00 31. " CLRINSTRPTR ,Clear the instruction pointer" "Not cleared,Cleared" bitfld.long 0x00 28.--30. " AWRWAITUNIT ,AWRWAIT unit" "2 cycles,8 cycles,32 cycles,128 cycles,512 cycles,2048 cycles,8192 cycles,32768 cycles" hexmask.long.word 0x00 16.--27. 1. " AWRWAIT ,Time to write data into internal memory" newline bitfld.long 0x00 13.--15. " AWRSEQNUM ,Sequence number for AHB write triggered command" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--12. " AWRSEQID ,Sequence index for AHB write triggered command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--7. " ARDSEQNUM ,Sequence number for AHB read triggered command in LUT" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--4. " ARDSEQID ,Sequence index for AHB read triggered command in LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x8C++0x03 line.long 0x00 "FLSHB2CR2,Flash B2 Control 2 Register" bitfld.long 0x00 31. " CLRINSTRPTR ,Clear the instruction pointer" "Not cleared,Cleared" bitfld.long 0x00 28.--30. " AWRWAITUNIT ,AWRWAIT unit" "2 cycles,8 cycles,32 cycles,128 cycles,512 cycles,2048 cycles,8192 cycles,32768 cycles" hexmask.long.word 0x00 16.--27. 1. " AWRWAIT ,Time to write data into internal memory" newline bitfld.long 0x00 13.--15. " AWRSEQNUM ,Sequence number for AHB write triggered command" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--12. " AWRSEQID ,Sequence index for AHB write triggered command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--7. " ARDSEQNUM ,Sequence number for AHB read triggered command in LUT" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--4. " ARDSEQID ,Sequence index for AHB read triggered command in LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x94++0x03 line.long 0x00 "FLSHCR4,Flash Control Register 4" bitfld.long 0x00 3. " WMENB ,Write mask enable bit for flash device on port B" "Disabled,Enabled" bitfld.long 0x00 2. " WMENA ,Write mask enable bit for flash device on port A" "Disabled,Enabled" bitfld.long 0x00 0. " WMOPT1 ,AHB write burst start address alignment limitation disable" "No,Yes" group.long 0xA0++0x07 line.long 0x00 "IPCR0,IP Control Register 0" line.long 0x04 "IPCR1,IP Control Register 1" bitfld.long 0x04 31. " IPAREN ,Parallel mode" "Disabled,Enabled" bitfld.long 0x04 24.--26. " ISEQNUM ,Sequence number for IP command" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--20. " ISEQID ,Sequence index in LUT for IP command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x04 0.--15. 1. " IDATSZ ,Flash read/program data size (in bytes) for IP command" group.long 0xB0++0x17 line.long 0x00 "IPCMD,IP Command Register" bitfld.long 0x00 0. " TRG ,IP command trigger" "Not triggered,Triggered" line.long 0x04 "DLPR,Data Learn Pattern Register" line.long 0x08 "IPRXFCR,IP RX FIFO Control Register" bitfld.long 0x08 2.--7. " RXWMRK ,Watermark level" "64bits,128bits,192bits,256bits,320bits,384bits,448bits,512bits,576bits,640bits,704bits,768bits,832bits,896bits,960bits,1024bits,1088bits,1152bits,1216bits,1280bits,1344bits,1408bits,1472bits,1536bits,1600bits,1664bits,1728bits,1792bits,1856bits,1920bits,1984bits,2048bits,2112bits,2176bits,2240bits,2304bits,2368bits,2432bits,2496bits,2560bits,2624bits,2688bits,2752bits,2816bits,2880bits,2944bits,3008bits,3072bits,3136bits,3200bits,3264bits,3328bits,3392bits,3456bits,3520bits,3584bits,3648bits,3712bits,3776bits,3840bits,3904bits,3968bits,4032bits,4096bits" bitfld.long 0x08 1. " RXDMAEN ,IP RX FIFO reading by DMA enable" "Disabled,Enabled" bitfld.long 0x08 0. " CLRIPRXF ,Clear all valid data entries in IP RX FIFO" "Not cleared,Cleared" newline line.long 0x0C "IPTXFCR,IP TX FIFO Control Register" hexmask.long.word 0x0C 2.--8. 1. " TXWMRK ,Watermark level" bitfld.long 0x0C 1. " TXDMAEN ,IP TX FIFO filling by DMA enabled" "Disabled,Enabled" bitfld.long 0x0C 0. " CLRIPTXF ,Clear all valid data entries in IP TX FIFO" "Not cleared,Cleared" newline line.long 0x10 "DLLACR,DLLA Control 0 Register" bitfld.long 0x10 9.--14. " OVRDVAL ,Slave clock delay line delay cell number selection override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 8. " OVRDEN ,Slave clock delay line delay cell number selection override enable" "Disabled,Enabled" bitfld.long 0x10 3.--6. " SLVDLYTARGET ,The delay target for slave delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 1. " DLLRESET ,DDL reset" "No reset,Reset" bitfld.long 0x10 0. " DLLEN ,DLL calibration enable" "Disabled,Enabled" line.long 0x14 "DLLBCR,DLLB Control 0 Register" bitfld.long 0x14 9.--14. " OVRDVAL ,Slave clock delay line delay cell number selection override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 8. " OVRDEN ,Slave clock delay line delay cell number selection override enable" "Disabled,Enabled" bitfld.long 0x14 3.--6. " SLVDLYTARGET ,The delay target for slave delay line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 1. " DLLRESET ,DDL reset" "No reset,Reset" bitfld.long 0x14 0. " DLLEN ,DLL calibration enable" "Disabled,Enabled" rgroup.long 0xE0++0x17 line.long 0x00 "STS0,Status Register 0" bitfld.long 0x00 8.--11. " DATALEARNPHASEB ,Sampling clock phase selection on Port B after data learning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DATALEARNPHASEA ,Sampling clock phase selection on Port A after data learning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--3. " ARBCMDSRC ,Trigger source of current command sequence granted by arbitrator" "AHB Read,AHB Write,IP,Suspended" newline bitfld.long 0x00 1. " ARBIDLE ,State machine in ARB_CTL" "Busy,Idle" bitfld.long 0x00 0. " SEQIDLE ,State machine in SEQ_CTL" "Busy,Idle" newline line.long 0x04 "STS1,Status Register 1" bitfld.long 0x04 24.--27. " IPCMDERRCODE ,IP command error code" "No error,,JMP_ON_CS used with IP command,Unknown opcode,SDR used in DDR,DDR used in SDR,Start address exceed whole flash address range,,,,,,,,Sequence execution timeout,Flash boundary crossed" bitfld.long 0x04 16.--20. "IPCMDERRID ,Sequence index when IP command error detected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 8.--11. " AHBCMDERRCODE ,AHB command error code" "No error,,JMP_ON_CS used with AHB write command,Unknown opcode,SDR used in DDR,DDR used in SDR,,,,,,,,,Execution timeout,?..." bitfld.long 0x04 0.--4. " AHBCMDERRID ,Sequence index when an AHB command error is detected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline line.long 0x08 "STS2,Status Register 2" bitfld.long 0x08 24.--29. " BREFSEL ,Flash B sample clock reference delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 18.--23. " BSLVSEL ,Flash B sample clock slave delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 17. " BREFLOCK ,Flash B sample clock reference delay line locked" "Not locked,Locked" newline bitfld.long 0x08 16. " BSLVLOCK ,Flash B sample clock slave delay line locked" "Not locked,Locked" bitfld.long 0x08 8.--13. " AREFSEL ,Flash A sample clock reference delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 2.--7. " ASLVSEL ,Flash A sample clock slave delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 1. " AREFLOCK ,Flash A sample clock reference delay line locked" "Not locked,Locked" bitfld.long 0x08 0. " ASLVLOCK ,Flash A sample clock slave delay line locked" "Not locked,Locked" line.long 0x0C "AHBSPNDSTS,AHB Suspend Status Register" hexmask.long.word 0x0C 16.--31. 1. " DATLFT ,Left data size for suspended command sequence" bitfld.long 0x0C 1.--3. " BUFID ,AHB RX BUF ID for suspended command sequence" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0. " ACTIVE ,AHB read prefetch command sequence has been suspended" "Not suspended,Suspended" newline line.long 0x10 "IPRXFSTS,IP RX FIFO Status Register" hexmask.long.word 0x10 16.--31. 1. " RDCNTR ,Total read data counter" hexmask.long.byte 0x10 0.--7. 1. " FILL ,Fill level of IP RX FIFO" line.long 0x14 "IPTXFSTS,IP TX FIFO Status Register" hexmask.long.word 0x14 16.--31. 1. " WRCNTR ,Total write data counter" hexmask.long.byte 0x14 0.--7. 1. " FILL ,Fill level of IP TX FIFO" tree "RX/TX FIFO Data" rgroup.long 0x100++0x03 line.long 0x00 "RFDR0,IP RX FIFO Data 0 Register" rgroup.long 0x104++0x03 line.long 0x00 "RFDR1,IP RX FIFO Data 1 Register" rgroup.long 0x108++0x03 line.long 0x00 "RFDR2,IP RX FIFO Data 2 Register" rgroup.long 0x10C++0x03 line.long 0x00 "RFDR3,IP RX FIFO Data 3 Register" rgroup.long 0x110++0x03 line.long 0x00 "RFDR4,IP RX FIFO Data 4 Register" rgroup.long 0x114++0x03 line.long 0x00 "RFDR5,IP RX FIFO Data 5 Register" rgroup.long 0x118++0x03 line.long 0x00 "RFDR6,IP RX FIFO Data 6 Register" rgroup.long 0x11C++0x03 line.long 0x00 "RFDR7,IP RX FIFO Data 7 Register" rgroup.long 0x120++0x03 line.long 0x00 "RFDR8,IP RX FIFO Data 8 Register" rgroup.long 0x124++0x03 line.long 0x00 "RFDR9,IP RX FIFO Data 9 Register" rgroup.long 0x128++0x03 line.long 0x00 "RFDR10,IP RX FIFO Data 10 Register" rgroup.long 0x12C++0x03 line.long 0x00 "RFDR11,IP RX FIFO Data 11 Register" rgroup.long 0x130++0x03 line.long 0x00 "RFDR12,IP RX FIFO Data 12 Register" rgroup.long 0x134++0x03 line.long 0x00 "RFDR13,IP RX FIFO Data 13 Register" rgroup.long 0x138++0x03 line.long 0x00 "RFDR14,IP RX FIFO Data 14 Register" rgroup.long 0x13C++0x03 line.long 0x00 "RFDR15,IP RX FIFO Data 15 Register" rgroup.long 0x140++0x03 line.long 0x00 "RFDR16,IP RX FIFO Data 16 Register" rgroup.long 0x144++0x03 line.long 0x00 "RFDR17,IP RX FIFO Data 17 Register" rgroup.long 0x148++0x03 line.long 0x00 "RFDR18,IP RX FIFO Data 18 Register" rgroup.long 0x14C++0x03 line.long 0x00 "RFDR19,IP RX FIFO Data 19 Register" rgroup.long 0x150++0x03 line.long 0x00 "RFDR20,IP RX FIFO Data 20 Register" rgroup.long 0x154++0x03 line.long 0x00 "RFDR21,IP RX FIFO Data 21 Register" rgroup.long 0x158++0x03 line.long 0x00 "RFDR22,IP RX FIFO Data 22 Register" rgroup.long 0x15C++0x03 line.long 0x00 "RFDR23,IP RX FIFO Data 23 Register" rgroup.long 0x160++0x03 line.long 0x00 "RFDR24,IP RX FIFO Data 24 Register" rgroup.long 0x164++0x03 line.long 0x00 "RFDR25,IP RX FIFO Data 25 Register" rgroup.long 0x168++0x03 line.long 0x00 "RFDR26,IP RX FIFO Data 26 Register" rgroup.long 0x16C++0x03 line.long 0x00 "RFDR27,IP RX FIFO Data 27 Register" rgroup.long 0x170++0x03 line.long 0x00 "RFDR28,IP RX FIFO Data 28 Register" rgroup.long 0x174++0x03 line.long 0x00 "RFDR29,IP RX FIFO Data 29 Register" rgroup.long 0x178++0x03 line.long 0x00 "RFDR30,IP RX FIFO Data 30 Register" rgroup.long 0x17C++0x03 line.long 0x00 "RFDR31,IP RX FIFO Data 31 Register" wgroup.long 0x180++0x03 line.long 0x00 "TFDR0,IP TX FIFO Data 0 Register" wgroup.long 0x184++0x03 line.long 0x00 "TFDR1,IP TX FIFO Data 1 Register" wgroup.long 0x188++0x03 line.long 0x00 "TFDR2,IP TX FIFO Data 2 Register" wgroup.long 0x18C++0x03 line.long 0x00 "TFDR3,IP TX FIFO Data 3 Register" wgroup.long 0x190++0x03 line.long 0x00 "TFDR4,IP TX FIFO Data 4 Register" wgroup.long 0x194++0x03 line.long 0x00 "TFDR5,IP TX FIFO Data 5 Register" wgroup.long 0x198++0x03 line.long 0x00 "TFDR6,IP TX FIFO Data 6 Register" wgroup.long 0x19C++0x03 line.long 0x00 "TFDR7,IP TX FIFO Data 7 Register" wgroup.long 0x1A0++0x03 line.long 0x00 "TFDR8,IP TX FIFO Data 8 Register" wgroup.long 0x1A4++0x03 line.long 0x00 "TFDR9,IP TX FIFO Data 9 Register" wgroup.long 0x1A8++0x03 line.long 0x00 "TFDR10,IP TX FIFO Data 10 Register" wgroup.long 0x1AC++0x03 line.long 0x00 "TFDR11,IP TX FIFO Data 11 Register" wgroup.long 0x1B0++0x03 line.long 0x00 "TFDR12,IP TX FIFO Data 12 Register" wgroup.long 0x1B4++0x03 line.long 0x00 "TFDR13,IP TX FIFO Data 13 Register" wgroup.long 0x1B8++0x03 line.long 0x00 "TFDR14,IP TX FIFO Data 14 Register" wgroup.long 0x1BC++0x03 line.long 0x00 "TFDR15,IP TX FIFO Data 15 Register" wgroup.long 0x1C0++0x03 line.long 0x00 "TFDR16,IP TX FIFO Data 16 Register" wgroup.long 0x1C4++0x03 line.long 0x00 "TFDR17,IP TX FIFO Data 17 Register" wgroup.long 0x1C8++0x03 line.long 0x00 "TFDR18,IP TX FIFO Data 18 Register" wgroup.long 0x1CC++0x03 line.long 0x00 "TFDR19,IP TX FIFO Data 19 Register" wgroup.long 0x1D0++0x03 line.long 0x00 "TFDR20,IP TX FIFO Data 20 Register" wgroup.long 0x1D4++0x03 line.long 0x00 "TFDR21,IP TX FIFO Data 21 Register" wgroup.long 0x1D8++0x03 line.long 0x00 "TFDR22,IP TX FIFO Data 22 Register" wgroup.long 0x1DC++0x03 line.long 0x00 "TFDR23,IP TX FIFO Data 23 Register" wgroup.long 0x1E0++0x03 line.long 0x00 "TFDR24,IP TX FIFO Data 24 Register" wgroup.long 0x1E4++0x03 line.long 0x00 "TFDR25,IP TX FIFO Data 25 Register" wgroup.long 0x1E8++0x03 line.long 0x00 "TFDR26,IP TX FIFO Data 26 Register" wgroup.long 0x1EC++0x03 line.long 0x00 "TFDR27,IP TX FIFO Data 27 Register" wgroup.long 0x1F0++0x03 line.long 0x00 "TFDR28,IP TX FIFO Data 28 Register" wgroup.long 0x1F4++0x03 line.long 0x00 "TFDR29,IP TX FIFO Data 29 Register" wgroup.long 0x1F8++0x03 line.long 0x00 "TFDR30,IP TX FIFO Data 30 Register" wgroup.long 0x1FC++0x03 line.long 0x00 "TFDR31,IP TX FIFO Data 31 Register" tree.end tree "LUT Registers" if (((((per.l(ad:0x5D130000+0x200))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x200))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x200))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x200))&0xFC00)==0x7C00))) group.long 0x200++0x03 line.long 0x00 "LUT0,LUT 0 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x200))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x200))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x200))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x200))&0xFC00)==0x7C00)) group.long 0x200++0x03 line.long 0x00 "LUT0,LUT 0 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x200))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x200))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x200))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x200))&0xFC00)!=0x7C00)) group.long 0x200++0x03 line.long 0x00 "LUT0,LUT 0 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x200++0x03 line.long 0x00 "LUT0,LUT 0 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x204))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x204))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x204))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x204))&0xFC00)==0x7C00))) group.long 0x204++0x03 line.long 0x00 "LUT1,LUT 1 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x204))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x204))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x204))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x204))&0xFC00)==0x7C00)) group.long 0x204++0x03 line.long 0x00 "LUT1,LUT 1 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x204))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x204))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x204))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x204))&0xFC00)!=0x7C00)) group.long 0x204++0x03 line.long 0x00 "LUT1,LUT 1 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x204++0x03 line.long 0x00 "LUT1,LUT 1 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x208))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x208))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x208))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x208))&0xFC00)==0x7C00))) group.long 0x208++0x03 line.long 0x00 "LUT2,LUT 2 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x208))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x208))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x208))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x208))&0xFC00)==0x7C00)) group.long 0x208++0x03 line.long 0x00 "LUT2,LUT 2 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x208))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x208))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x208))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x208))&0xFC00)!=0x7C00)) group.long 0x208++0x03 line.long 0x00 "LUT2,LUT 2 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x208++0x03 line.long 0x00 "LUT2,LUT 2 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x20C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x20C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x20C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x20C))&0xFC00)==0x7C00))) group.long 0x20C++0x03 line.long 0x00 "LUT3,LUT 3 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x20C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x20C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x20C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x20C))&0xFC00)==0x7C00)) group.long 0x20C++0x03 line.long 0x00 "LUT3,LUT 3 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x20C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x20C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x20C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x20C))&0xFC00)!=0x7C00)) group.long 0x20C++0x03 line.long 0x00 "LUT3,LUT 3 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x20C++0x03 line.long 0x00 "LUT3,LUT 3 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x210))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x210))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x210))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x210))&0xFC00)==0x7C00))) group.long 0x210++0x03 line.long 0x00 "LUT4,LUT 4 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x210))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x210))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x210))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x210))&0xFC00)==0x7C00)) group.long 0x210++0x03 line.long 0x00 "LUT4,LUT 4 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x210))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x210))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x210))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x210))&0xFC00)!=0x7C00)) group.long 0x210++0x03 line.long 0x00 "LUT4,LUT 4 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x210++0x03 line.long 0x00 "LUT4,LUT 4 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x214))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x214))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x214))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x214))&0xFC00)==0x7C00))) group.long 0x214++0x03 line.long 0x00 "LUT5,LUT 5 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x214))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x214))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x214))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x214))&0xFC00)==0x7C00)) group.long 0x214++0x03 line.long 0x00 "LUT5,LUT 5 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x214))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x214))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x214))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x214))&0xFC00)!=0x7C00)) group.long 0x214++0x03 line.long 0x00 "LUT5,LUT 5 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x214++0x03 line.long 0x00 "LUT5,LUT 5 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x218))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x218))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x218))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x218))&0xFC00)==0x7C00))) group.long 0x218++0x03 line.long 0x00 "LUT6,LUT 6 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x218))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x218))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x218))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x218))&0xFC00)==0x7C00)) group.long 0x218++0x03 line.long 0x00 "LUT6,LUT 6 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x218))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x218))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x218))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x218))&0xFC00)!=0x7C00)) group.long 0x218++0x03 line.long 0x00 "LUT6,LUT 6 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x218++0x03 line.long 0x00 "LUT6,LUT 6 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x21C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x21C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x21C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x21C))&0xFC00)==0x7C00))) group.long 0x21C++0x03 line.long 0x00 "LUT7,LUT 7 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x21C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x21C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x21C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x21C))&0xFC00)==0x7C00)) group.long 0x21C++0x03 line.long 0x00 "LUT7,LUT 7 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x21C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x21C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x21C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x21C))&0xFC00)!=0x7C00)) group.long 0x21C++0x03 line.long 0x00 "LUT7,LUT 7 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x21C++0x03 line.long 0x00 "LUT7,LUT 7 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x220))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x220))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x220))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x220))&0xFC00)==0x7C00))) group.long 0x220++0x03 line.long 0x00 "LUT8,LUT 8 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x220))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x220))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x220))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x220))&0xFC00)==0x7C00)) group.long 0x220++0x03 line.long 0x00 "LUT8,LUT 8 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x220))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x220))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x220))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x220))&0xFC00)!=0x7C00)) group.long 0x220++0x03 line.long 0x00 "LUT8,LUT 8 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x220++0x03 line.long 0x00 "LUT8,LUT 8 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x224))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x224))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x224))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x224))&0xFC00)==0x7C00))) group.long 0x224++0x03 line.long 0x00 "LUT9,LUT 9 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x224))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x224))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x224))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x224))&0xFC00)==0x7C00)) group.long 0x224++0x03 line.long 0x00 "LUT9,LUT 9 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x224))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x224))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x224))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x224))&0xFC00)!=0x7C00)) group.long 0x224++0x03 line.long 0x00 "LUT9,LUT 9 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x224++0x03 line.long 0x00 "LUT9,LUT 9 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x228))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x228))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x228))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x228))&0xFC00)==0x7C00))) group.long 0x228++0x03 line.long 0x00 "LUT10,LUT 10 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x228))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x228))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x228))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x228))&0xFC00)==0x7C00)) group.long 0x228++0x03 line.long 0x00 "LUT10,LUT 10 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x228))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x228))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x228))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x228))&0xFC00)!=0x7C00)) group.long 0x228++0x03 line.long 0x00 "LUT10,LUT 10 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x228++0x03 line.long 0x00 "LUT10,LUT 10 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x22C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x22C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x22C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x22C))&0xFC00)==0x7C00))) group.long 0x22C++0x03 line.long 0x00 "LUT11,LUT 11 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x22C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x22C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x22C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x22C))&0xFC00)==0x7C00)) group.long 0x22C++0x03 line.long 0x00 "LUT11,LUT 11 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x22C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x22C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x22C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x22C))&0xFC00)!=0x7C00)) group.long 0x22C++0x03 line.long 0x00 "LUT11,LUT 11 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x22C++0x03 line.long 0x00 "LUT11,LUT 11 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x230))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x230))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x230))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x230))&0xFC00)==0x7C00))) group.long 0x230++0x03 line.long 0x00 "LUT12,LUT 12 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x230))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x230))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x230))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x230))&0xFC00)==0x7C00)) group.long 0x230++0x03 line.long 0x00 "LUT12,LUT 12 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x230))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x230))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x230))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x230))&0xFC00)!=0x7C00)) group.long 0x230++0x03 line.long 0x00 "LUT12,LUT 12 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x230++0x03 line.long 0x00 "LUT12,LUT 12 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x234))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x234))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x234))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x234))&0xFC00)==0x7C00))) group.long 0x234++0x03 line.long 0x00 "LUT13,LUT 13 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x234))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x234))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x234))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x234))&0xFC00)==0x7C00)) group.long 0x234++0x03 line.long 0x00 "LUT13,LUT 13 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x234))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x234))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x234))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x234))&0xFC00)!=0x7C00)) group.long 0x234++0x03 line.long 0x00 "LUT13,LUT 13 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x234++0x03 line.long 0x00 "LUT13,LUT 13 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x238))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x238))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x238))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x238))&0xFC00)==0x7C00))) group.long 0x238++0x03 line.long 0x00 "LUT14,LUT 14 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x238))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x238))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x238))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x238))&0xFC00)==0x7C00)) group.long 0x238++0x03 line.long 0x00 "LUT14,LUT 14 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x238))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x238))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x238))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x238))&0xFC00)!=0x7C00)) group.long 0x238++0x03 line.long 0x00 "LUT14,LUT 14 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x238++0x03 line.long 0x00 "LUT14,LUT 14 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x23C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x23C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x23C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x23C))&0xFC00)==0x7C00))) group.long 0x23C++0x03 line.long 0x00 "LUT15,LUT 15 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x23C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x23C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x23C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x23C))&0xFC00)==0x7C00)) group.long 0x23C++0x03 line.long 0x00 "LUT15,LUT 15 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x23C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x23C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x23C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x23C))&0xFC00)!=0x7C00)) group.long 0x23C++0x03 line.long 0x00 "LUT15,LUT 15 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x23C++0x03 line.long 0x00 "LUT15,LUT 15 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x240))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x240))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x240))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x240))&0xFC00)==0x7C00))) group.long 0x240++0x03 line.long 0x00 "LUT16,LUT 16 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x240))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x240))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x240))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x240))&0xFC00)==0x7C00)) group.long 0x240++0x03 line.long 0x00 "LUT16,LUT 16 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x240))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x240))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x240))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x240))&0xFC00)!=0x7C00)) group.long 0x240++0x03 line.long 0x00 "LUT16,LUT 16 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x240++0x03 line.long 0x00 "LUT16,LUT 16 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x244))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x244))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x244))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x244))&0xFC00)==0x7C00))) group.long 0x244++0x03 line.long 0x00 "LUT17,LUT 17 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x244))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x244))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x244))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x244))&0xFC00)==0x7C00)) group.long 0x244++0x03 line.long 0x00 "LUT17,LUT 17 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x244))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x244))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x244))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x244))&0xFC00)!=0x7C00)) group.long 0x244++0x03 line.long 0x00 "LUT17,LUT 17 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x244++0x03 line.long 0x00 "LUT17,LUT 17 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x248))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x248))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x248))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x248))&0xFC00)==0x7C00))) group.long 0x248++0x03 line.long 0x00 "LUT18,LUT 18 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x248))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x248))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x248))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x248))&0xFC00)==0x7C00)) group.long 0x248++0x03 line.long 0x00 "LUT18,LUT 18 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x248))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x248))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x248))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x248))&0xFC00)!=0x7C00)) group.long 0x248++0x03 line.long 0x00 "LUT18,LUT 18 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x248++0x03 line.long 0x00 "LUT18,LUT 18 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x24C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x24C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x24C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x24C))&0xFC00)==0x7C00))) group.long 0x24C++0x03 line.long 0x00 "LUT19,LUT 19 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x24C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x24C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x24C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x24C))&0xFC00)==0x7C00)) group.long 0x24C++0x03 line.long 0x00 "LUT19,LUT 19 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x24C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x24C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x24C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x24C))&0xFC00)!=0x7C00)) group.long 0x24C++0x03 line.long 0x00 "LUT19,LUT 19 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x24C++0x03 line.long 0x00 "LUT19,LUT 19 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x250))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x250))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x250))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x250))&0xFC00)==0x7C00))) group.long 0x250++0x03 line.long 0x00 "LUT20,LUT 20 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x250))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x250))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x250))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x250))&0xFC00)==0x7C00)) group.long 0x250++0x03 line.long 0x00 "LUT20,LUT 20 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x250))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x250))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x250))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x250))&0xFC00)!=0x7C00)) group.long 0x250++0x03 line.long 0x00 "LUT20,LUT 20 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x250++0x03 line.long 0x00 "LUT20,LUT 20 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x254))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x254))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x254))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x254))&0xFC00)==0x7C00))) group.long 0x254++0x03 line.long 0x00 "LUT21,LUT 21 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x254))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x254))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x254))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x254))&0xFC00)==0x7C00)) group.long 0x254++0x03 line.long 0x00 "LUT21,LUT 21 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x254))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x254))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x254))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x254))&0xFC00)!=0x7C00)) group.long 0x254++0x03 line.long 0x00 "LUT21,LUT 21 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x254++0x03 line.long 0x00 "LUT21,LUT 21 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x258))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x258))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x258))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x258))&0xFC00)==0x7C00))) group.long 0x258++0x03 line.long 0x00 "LUT22,LUT 22 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x258))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x258))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x258))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x258))&0xFC00)==0x7C00)) group.long 0x258++0x03 line.long 0x00 "LUT22,LUT 22 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x258))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x258))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x258))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x258))&0xFC00)!=0x7C00)) group.long 0x258++0x03 line.long 0x00 "LUT22,LUT 22 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x258++0x03 line.long 0x00 "LUT22,LUT 22 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x25C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x25C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x25C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x25C))&0xFC00)==0x7C00))) group.long 0x25C++0x03 line.long 0x00 "LUT23,LUT 23 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x25C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x25C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x25C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x25C))&0xFC00)==0x7C00)) group.long 0x25C++0x03 line.long 0x00 "LUT23,LUT 23 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x25C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x25C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x25C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x25C))&0xFC00)!=0x7C00)) group.long 0x25C++0x03 line.long 0x00 "LUT23,LUT 23 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x25C++0x03 line.long 0x00 "LUT23,LUT 23 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x260))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x260))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x260))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x260))&0xFC00)==0x7C00))) group.long 0x260++0x03 line.long 0x00 "LUT24,LUT 24 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x260))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x260))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x260))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x260))&0xFC00)==0x7C00)) group.long 0x260++0x03 line.long 0x00 "LUT24,LUT 24 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x260))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x260))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x260))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x260))&0xFC00)!=0x7C00)) group.long 0x260++0x03 line.long 0x00 "LUT24,LUT 24 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x260++0x03 line.long 0x00 "LUT24,LUT 24 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x264))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x264))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x264))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x264))&0xFC00)==0x7C00))) group.long 0x264++0x03 line.long 0x00 "LUT25,LUT 25 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x264))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x264))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x264))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x264))&0xFC00)==0x7C00)) group.long 0x264++0x03 line.long 0x00 "LUT25,LUT 25 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x264))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x264))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x264))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x264))&0xFC00)!=0x7C00)) group.long 0x264++0x03 line.long 0x00 "LUT25,LUT 25 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x264++0x03 line.long 0x00 "LUT25,LUT 25 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x268))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x268))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x268))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x268))&0xFC00)==0x7C00))) group.long 0x268++0x03 line.long 0x00 "LUT26,LUT 26 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x268))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x268))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x268))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x268))&0xFC00)==0x7C00)) group.long 0x268++0x03 line.long 0x00 "LUT26,LUT 26 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x268))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x268))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x268))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x268))&0xFC00)!=0x7C00)) group.long 0x268++0x03 line.long 0x00 "LUT26,LUT 26 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x268++0x03 line.long 0x00 "LUT26,LUT 26 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x26C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x26C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x26C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x26C))&0xFC00)==0x7C00))) group.long 0x26C++0x03 line.long 0x00 "LUT27,LUT 27 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x26C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x26C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x26C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x26C))&0xFC00)==0x7C00)) group.long 0x26C++0x03 line.long 0x00 "LUT27,LUT 27 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x26C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x26C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x26C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x26C))&0xFC00)!=0x7C00)) group.long 0x26C++0x03 line.long 0x00 "LUT27,LUT 27 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x26C++0x03 line.long 0x00 "LUT27,LUT 27 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x270))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x270))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x270))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x270))&0xFC00)==0x7C00))) group.long 0x270++0x03 line.long 0x00 "LUT28,LUT 28 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x270))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x270))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x270))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x270))&0xFC00)==0x7C00)) group.long 0x270++0x03 line.long 0x00 "LUT28,LUT 28 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x270))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x270))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x270))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x270))&0xFC00)!=0x7C00)) group.long 0x270++0x03 line.long 0x00 "LUT28,LUT 28 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x270++0x03 line.long 0x00 "LUT28,LUT 28 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x274))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x274))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x274))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x274))&0xFC00)==0x7C00))) group.long 0x274++0x03 line.long 0x00 "LUT29,LUT 29 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x274))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x274))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x274))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x274))&0xFC00)==0x7C00)) group.long 0x274++0x03 line.long 0x00 "LUT29,LUT 29 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x274))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x274))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x274))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x274))&0xFC00)!=0x7C00)) group.long 0x274++0x03 line.long 0x00 "LUT29,LUT 29 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x274++0x03 line.long 0x00 "LUT29,LUT 29 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x278))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x278))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x278))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x278))&0xFC00)==0x7C00))) group.long 0x278++0x03 line.long 0x00 "LUT30,LUT 30 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x278))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x278))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x278))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x278))&0xFC00)==0x7C00)) group.long 0x278++0x03 line.long 0x00 "LUT30,LUT 30 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x278))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x278))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x278))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x278))&0xFC00)!=0x7C00)) group.long 0x278++0x03 line.long 0x00 "LUT30,LUT 30 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x278++0x03 line.long 0x00 "LUT30,LUT 30 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x27C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x27C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x27C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x27C))&0xFC00)==0x7C00))) group.long 0x27C++0x03 line.long 0x00 "LUT31,LUT 31 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x27C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x27C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x27C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x27C))&0xFC00)==0x7C00)) group.long 0x27C++0x03 line.long 0x00 "LUT31,LUT 31 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x27C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x27C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x27C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x27C))&0xFC00)!=0x7C00)) group.long 0x27C++0x03 line.long 0x00 "LUT31,LUT 31 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x27C++0x03 line.long 0x00 "LUT31,LUT 31 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x280))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x280))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x280))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x280))&0xFC00)==0x7C00))) group.long 0x280++0x03 line.long 0x00 "LUT32,LUT 32 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x280))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x280))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x280))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x280))&0xFC00)==0x7C00)) group.long 0x280++0x03 line.long 0x00 "LUT32,LUT 32 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x280))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x280))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x280))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x280))&0xFC00)!=0x7C00)) group.long 0x280++0x03 line.long 0x00 "LUT32,LUT 32 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x280++0x03 line.long 0x00 "LUT32,LUT 32 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x284))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x284))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x284))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x284))&0xFC00)==0x7C00))) group.long 0x284++0x03 line.long 0x00 "LUT33,LUT 33 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x284))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x284))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x284))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x284))&0xFC00)==0x7C00)) group.long 0x284++0x03 line.long 0x00 "LUT33,LUT 33 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x284))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x284))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x284))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x284))&0xFC00)!=0x7C00)) group.long 0x284++0x03 line.long 0x00 "LUT33,LUT 33 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x284++0x03 line.long 0x00 "LUT33,LUT 33 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x288))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x288))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x288))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x288))&0xFC00)==0x7C00))) group.long 0x288++0x03 line.long 0x00 "LUT34,LUT 34 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x288))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x288))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x288))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x288))&0xFC00)==0x7C00)) group.long 0x288++0x03 line.long 0x00 "LUT34,LUT 34 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x288))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x288))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x288))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x288))&0xFC00)!=0x7C00)) group.long 0x288++0x03 line.long 0x00 "LUT34,LUT 34 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x288++0x03 line.long 0x00 "LUT34,LUT 34 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x28C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x28C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x28C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x28C))&0xFC00)==0x7C00))) group.long 0x28C++0x03 line.long 0x00 "LUT35,LUT 35 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x28C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x28C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x28C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x28C))&0xFC00)==0x7C00)) group.long 0x28C++0x03 line.long 0x00 "LUT35,LUT 35 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x28C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x28C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x28C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x28C))&0xFC00)!=0x7C00)) group.long 0x28C++0x03 line.long 0x00 "LUT35,LUT 35 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x28C++0x03 line.long 0x00 "LUT35,LUT 35 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x290))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x290))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x290))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x290))&0xFC00)==0x7C00))) group.long 0x290++0x03 line.long 0x00 "LUT36,LUT 36 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x290))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x290))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x290))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x290))&0xFC00)==0x7C00)) group.long 0x290++0x03 line.long 0x00 "LUT36,LUT 36 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x290))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x290))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x290))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x290))&0xFC00)!=0x7C00)) group.long 0x290++0x03 line.long 0x00 "LUT36,LUT 36 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x290++0x03 line.long 0x00 "LUT36,LUT 36 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x294))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x294))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x294))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x294))&0xFC00)==0x7C00))) group.long 0x294++0x03 line.long 0x00 "LUT37,LUT 37 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x294))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x294))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x294))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x294))&0xFC00)==0x7C00)) group.long 0x294++0x03 line.long 0x00 "LUT37,LUT 37 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x294))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x294))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x294))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x294))&0xFC00)!=0x7C00)) group.long 0x294++0x03 line.long 0x00 "LUT37,LUT 37 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x294++0x03 line.long 0x00 "LUT37,LUT 37 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x298))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x298))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x298))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x298))&0xFC00)==0x7C00))) group.long 0x298++0x03 line.long 0x00 "LUT38,LUT 38 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x298))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x298))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x298))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x298))&0xFC00)==0x7C00)) group.long 0x298++0x03 line.long 0x00 "LUT38,LUT 38 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x298))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x298))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x298))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x298))&0xFC00)!=0x7C00)) group.long 0x298++0x03 line.long 0x00 "LUT38,LUT 38 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x298++0x03 line.long 0x00 "LUT38,LUT 38 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x29C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x29C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x29C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x29C))&0xFC00)==0x7C00))) group.long 0x29C++0x03 line.long 0x00 "LUT39,LUT 39 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x29C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x29C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x29C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x29C))&0xFC00)==0x7C00)) group.long 0x29C++0x03 line.long 0x00 "LUT39,LUT 39 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x29C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x29C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x29C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x29C))&0xFC00)!=0x7C00)) group.long 0x29C++0x03 line.long 0x00 "LUT39,LUT 39 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x29C++0x03 line.long 0x00 "LUT39,LUT 39 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x2A0))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2A0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2A0))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2A0))&0xFC00)==0x7C00))) group.long 0x2A0++0x03 line.long 0x00 "LUT40,LUT 40 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2A0))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x2A0))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x2A0))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2A0))&0xFC00)==0x7C00)) group.long 0x2A0++0x03 line.long 0x00 "LUT40,LUT 40 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2A0))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2A0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2A0))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x2A0))&0xFC00)!=0x7C00)) group.long 0x2A0++0x03 line.long 0x00 "LUT40,LUT 40 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2A0++0x03 line.long 0x00 "LUT40,LUT 40 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x2A4))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2A4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2A4))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2A4))&0xFC00)==0x7C00))) group.long 0x2A4++0x03 line.long 0x00 "LUT41,LUT 41 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2A4))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x2A4))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x2A4))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2A4))&0xFC00)==0x7C00)) group.long 0x2A4++0x03 line.long 0x00 "LUT41,LUT 41 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2A4))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2A4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2A4))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x2A4))&0xFC00)!=0x7C00)) group.long 0x2A4++0x03 line.long 0x00 "LUT41,LUT 41 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2A4++0x03 line.long 0x00 "LUT41,LUT 41 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x2A8))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2A8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2A8))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2A8))&0xFC00)==0x7C00))) group.long 0x2A8++0x03 line.long 0x00 "LUT42,LUT 42 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2A8))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x2A8))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x2A8))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2A8))&0xFC00)==0x7C00)) group.long 0x2A8++0x03 line.long 0x00 "LUT42,LUT 42 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2A8))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2A8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2A8))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x2A8))&0xFC00)!=0x7C00)) group.long 0x2A8++0x03 line.long 0x00 "LUT42,LUT 42 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2A8++0x03 line.long 0x00 "LUT42,LUT 42 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x2AC))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2AC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2AC))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2AC))&0xFC00)==0x7C00))) group.long 0x2AC++0x03 line.long 0x00 "LUT43,LUT 43 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2AC))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x2AC))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x2AC))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2AC))&0xFC00)==0x7C00)) group.long 0x2AC++0x03 line.long 0x00 "LUT43,LUT 43 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2AC))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2AC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2AC))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x2AC))&0xFC00)!=0x7C00)) group.long 0x2AC++0x03 line.long 0x00 "LUT43,LUT 43 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2AC++0x03 line.long 0x00 "LUT43,LUT 43 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x2B0))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2B0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2B0))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2B0))&0xFC00)==0x7C00))) group.long 0x2B0++0x03 line.long 0x00 "LUT44,LUT 44 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2B0))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x2B0))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x2B0))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2B0))&0xFC00)==0x7C00)) group.long 0x2B0++0x03 line.long 0x00 "LUT44,LUT 44 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2B0))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2B0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2B0))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x2B0))&0xFC00)!=0x7C00)) group.long 0x2B0++0x03 line.long 0x00 "LUT44,LUT 44 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2B0++0x03 line.long 0x00 "LUT44,LUT 44 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x2B4))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2B4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2B4))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2B4))&0xFC00)==0x7C00))) group.long 0x2B4++0x03 line.long 0x00 "LUT45,LUT 45 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2B4))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x2B4))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x2B4))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2B4))&0xFC00)==0x7C00)) group.long 0x2B4++0x03 line.long 0x00 "LUT45,LUT 45 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2B4))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2B4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2B4))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x2B4))&0xFC00)!=0x7C00)) group.long 0x2B4++0x03 line.long 0x00 "LUT45,LUT 45 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2B4++0x03 line.long 0x00 "LUT45,LUT 45 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x2B8))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2B8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2B8))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2B8))&0xFC00)==0x7C00))) group.long 0x2B8++0x03 line.long 0x00 "LUT46,LUT 46 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2B8))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x2B8))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x2B8))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2B8))&0xFC00)==0x7C00)) group.long 0x2B8++0x03 line.long 0x00 "LUT46,LUT 46 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2B8))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2B8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2B8))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x2B8))&0xFC00)!=0x7C00)) group.long 0x2B8++0x03 line.long 0x00 "LUT46,LUT 46 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2B8++0x03 line.long 0x00 "LUT46,LUT 46 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x2BC))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2BC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2BC))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2BC))&0xFC00)==0x7C00))) group.long 0x2BC++0x03 line.long 0x00 "LUT47,LUT 47 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2BC))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x2BC))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x2BC))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2BC))&0xFC00)==0x7C00)) group.long 0x2BC++0x03 line.long 0x00 "LUT47,LUT 47 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2BC))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2BC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2BC))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x2BC))&0xFC00)!=0x7C00)) group.long 0x2BC++0x03 line.long 0x00 "LUT47,LUT 47 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2BC++0x03 line.long 0x00 "LUT47,LUT 47 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x2C0))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2C0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2C0))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2C0))&0xFC00)==0x7C00))) group.long 0x2C0++0x03 line.long 0x00 "LUT48,LUT 48 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2C0))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x2C0))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x2C0))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2C0))&0xFC00)==0x7C00)) group.long 0x2C0++0x03 line.long 0x00 "LUT48,LUT 48 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2C0))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2C0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2C0))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x2C0))&0xFC00)!=0x7C00)) group.long 0x2C0++0x03 line.long 0x00 "LUT48,LUT 48 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2C0++0x03 line.long 0x00 "LUT48,LUT 48 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x2C4))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2C4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2C4))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2C4))&0xFC00)==0x7C00))) group.long 0x2C4++0x03 line.long 0x00 "LUT49,LUT 49 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2C4))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x2C4))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x2C4))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2C4))&0xFC00)==0x7C00)) group.long 0x2C4++0x03 line.long 0x00 "LUT49,LUT 49 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2C4))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2C4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2C4))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x2C4))&0xFC00)!=0x7C00)) group.long 0x2C4++0x03 line.long 0x00 "LUT49,LUT 49 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2C4++0x03 line.long 0x00 "LUT49,LUT 49 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x2C8))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2C8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2C8))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2C8))&0xFC00)==0x7C00))) group.long 0x2C8++0x03 line.long 0x00 "LUT50,LUT 50 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2C8))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x2C8))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x2C8))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2C8))&0xFC00)==0x7C00)) group.long 0x2C8++0x03 line.long 0x00 "LUT50,LUT 50 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2C8))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2C8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2C8))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x2C8))&0xFC00)!=0x7C00)) group.long 0x2C8++0x03 line.long 0x00 "LUT50,LUT 50 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2C8++0x03 line.long 0x00 "LUT50,LUT 50 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x2CC))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2CC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2CC))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2CC))&0xFC00)==0x7C00))) group.long 0x2CC++0x03 line.long 0x00 "LUT51,LUT 51 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2CC))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x2CC))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x2CC))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2CC))&0xFC00)==0x7C00)) group.long 0x2CC++0x03 line.long 0x00 "LUT51,LUT 51 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2CC))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2CC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2CC))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x2CC))&0xFC00)!=0x7C00)) group.long 0x2CC++0x03 line.long 0x00 "LUT51,LUT 51 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2CC++0x03 line.long 0x00 "LUT51,LUT 51 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x2D0))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2D0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2D0))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2D0))&0xFC00)==0x7C00))) group.long 0x2D0++0x03 line.long 0x00 "LUT52,LUT 52 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2D0))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x2D0))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x2D0))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2D0))&0xFC00)==0x7C00)) group.long 0x2D0++0x03 line.long 0x00 "LUT52,LUT 52 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2D0))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2D0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2D0))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x2D0))&0xFC00)!=0x7C00)) group.long 0x2D0++0x03 line.long 0x00 "LUT52,LUT 52 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2D0++0x03 line.long 0x00 "LUT52,LUT 52 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x2D4))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2D4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2D4))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2D4))&0xFC00)==0x7C00))) group.long 0x2D4++0x03 line.long 0x00 "LUT53,LUT 53 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2D4))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x2D4))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x2D4))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2D4))&0xFC00)==0x7C00)) group.long 0x2D4++0x03 line.long 0x00 "LUT53,LUT 53 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2D4))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2D4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2D4))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x2D4))&0xFC00)!=0x7C00)) group.long 0x2D4++0x03 line.long 0x00 "LUT53,LUT 53 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2D4++0x03 line.long 0x00 "LUT53,LUT 53 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x2D8))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2D8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2D8))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2D8))&0xFC00)==0x7C00))) group.long 0x2D8++0x03 line.long 0x00 "LUT54,LUT 54 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2D8))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x2D8))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x2D8))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2D8))&0xFC00)==0x7C00)) group.long 0x2D8++0x03 line.long 0x00 "LUT54,LUT 54 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2D8))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2D8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2D8))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x2D8))&0xFC00)!=0x7C00)) group.long 0x2D8++0x03 line.long 0x00 "LUT54,LUT 54 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2D8++0x03 line.long 0x00 "LUT54,LUT 54 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x2DC))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2DC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2DC))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2DC))&0xFC00)==0x7C00))) group.long 0x2DC++0x03 line.long 0x00 "LUT55,LUT 55 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2DC))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x2DC))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x2DC))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2DC))&0xFC00)==0x7C00)) group.long 0x2DC++0x03 line.long 0x00 "LUT55,LUT 55 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2DC))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2DC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2DC))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x2DC))&0xFC00)!=0x7C00)) group.long 0x2DC++0x03 line.long 0x00 "LUT55,LUT 55 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2DC++0x03 line.long 0x00 "LUT55,LUT 55 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x2E0))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2E0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2E0))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2E0))&0xFC00)==0x7C00))) group.long 0x2E0++0x03 line.long 0x00 "LUT56,LUT 56 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2E0))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x2E0))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x2E0))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2E0))&0xFC00)==0x7C00)) group.long 0x2E0++0x03 line.long 0x00 "LUT56,LUT 56 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2E0))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2E0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2E0))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x2E0))&0xFC00)!=0x7C00)) group.long 0x2E0++0x03 line.long 0x00 "LUT56,LUT 56 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2E0++0x03 line.long 0x00 "LUT56,LUT 56 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x2E4))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2E4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2E4))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2E4))&0xFC00)==0x7C00))) group.long 0x2E4++0x03 line.long 0x00 "LUT57,LUT 57 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2E4))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x2E4))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x2E4))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2E4))&0xFC00)==0x7C00)) group.long 0x2E4++0x03 line.long 0x00 "LUT57,LUT 57 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2E4))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2E4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2E4))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x2E4))&0xFC00)!=0x7C00)) group.long 0x2E4++0x03 line.long 0x00 "LUT57,LUT 57 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2E4++0x03 line.long 0x00 "LUT57,LUT 57 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x2E8))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2E8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2E8))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2E8))&0xFC00)==0x7C00))) group.long 0x2E8++0x03 line.long 0x00 "LUT58,LUT 58 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2E8))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x2E8))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x2E8))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2E8))&0xFC00)==0x7C00)) group.long 0x2E8++0x03 line.long 0x00 "LUT58,LUT 58 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2E8))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2E8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2E8))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x2E8))&0xFC00)!=0x7C00)) group.long 0x2E8++0x03 line.long 0x00 "LUT58,LUT 58 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2E8++0x03 line.long 0x00 "LUT58,LUT 58 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x2EC))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2EC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2EC))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2EC))&0xFC00)==0x7C00))) group.long 0x2EC++0x03 line.long 0x00 "LUT59,LUT 59 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2EC))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x2EC))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x2EC))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2EC))&0xFC00)==0x7C00)) group.long 0x2EC++0x03 line.long 0x00 "LUT59,LUT 59 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2EC))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2EC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2EC))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x2EC))&0xFC00)!=0x7C00)) group.long 0x2EC++0x03 line.long 0x00 "LUT59,LUT 59 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2EC++0x03 line.long 0x00 "LUT59,LUT 59 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x2F0))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2F0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2F0))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2F0))&0xFC00)==0x7C00))) group.long 0x2F0++0x03 line.long 0x00 "LUT60,LUT 60 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2F0))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x2F0))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x2F0))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2F0))&0xFC00)==0x7C00)) group.long 0x2F0++0x03 line.long 0x00 "LUT60,LUT 60 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2F0))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2F0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2F0))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x2F0))&0xFC00)!=0x7C00)) group.long 0x2F0++0x03 line.long 0x00 "LUT60,LUT 60 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2F0++0x03 line.long 0x00 "LUT60,LUT 60 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x2F4))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2F4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2F4))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2F4))&0xFC00)==0x7C00))) group.long 0x2F4++0x03 line.long 0x00 "LUT61,LUT 61 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2F4))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x2F4))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x2F4))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2F4))&0xFC00)==0x7C00)) group.long 0x2F4++0x03 line.long 0x00 "LUT61,LUT 61 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2F4))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2F4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2F4))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x2F4))&0xFC00)!=0x7C00)) group.long 0x2F4++0x03 line.long 0x00 "LUT61,LUT 61 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2F4++0x03 line.long 0x00 "LUT61,LUT 61 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x2F8))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2F8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2F8))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2F8))&0xFC00)==0x7C00))) group.long 0x2F8++0x03 line.long 0x00 "LUT62,LUT 62 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2F8))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x2F8))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x2F8))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2F8))&0xFC00)==0x7C00)) group.long 0x2F8++0x03 line.long 0x00 "LUT62,LUT 62 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2F8))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2F8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2F8))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x2F8))&0xFC00)!=0x7C00)) group.long 0x2F8++0x03 line.long 0x00 "LUT62,LUT 62 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2F8++0x03 line.long 0x00 "LUT62,LUT 62 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x2FC))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2FC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2FC))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2FC))&0xFC00)==0x7C00))) group.long 0x2FC++0x03 line.long 0x00 "LUT63,LUT 63 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2FC))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x2FC))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x2FC))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x2FC))&0xFC00)==0x7C00)) group.long 0x2FC++0x03 line.long 0x00 "LUT63,LUT 63 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x2FC))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x2FC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x2FC))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x2FC))&0xFC00)!=0x7C00)) group.long 0x2FC++0x03 line.long 0x00 "LUT63,LUT 63 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x2FC++0x03 line.long 0x00 "LUT63,LUT 63 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x300))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x300))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x300))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x300))&0xFC00)==0x7C00))) group.long 0x300++0x03 line.long 0x00 "LUT64,LUT 64 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x300))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x300))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x300))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x300))&0xFC00)==0x7C00)) group.long 0x300++0x03 line.long 0x00 "LUT64,LUT 64 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x300))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x300))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x300))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x300))&0xFC00)!=0x7C00)) group.long 0x300++0x03 line.long 0x00 "LUT64,LUT 64 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x300++0x03 line.long 0x00 "LUT64,LUT 64 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x304))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x304))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x304))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x304))&0xFC00)==0x7C00))) group.long 0x304++0x03 line.long 0x00 "LUT65,LUT 65 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x304))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x304))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x304))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x304))&0xFC00)==0x7C00)) group.long 0x304++0x03 line.long 0x00 "LUT65,LUT 65 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x304))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x304))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x304))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x304))&0xFC00)!=0x7C00)) group.long 0x304++0x03 line.long 0x00 "LUT65,LUT 65 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x304++0x03 line.long 0x00 "LUT65,LUT 65 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x308))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x308))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x308))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x308))&0xFC00)==0x7C00))) group.long 0x308++0x03 line.long 0x00 "LUT66,LUT 66 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x308))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x308))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x308))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x308))&0xFC00)==0x7C00)) group.long 0x308++0x03 line.long 0x00 "LUT66,LUT 66 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x308))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x308))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x308))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x308))&0xFC00)!=0x7C00)) group.long 0x308++0x03 line.long 0x00 "LUT66,LUT 66 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x308++0x03 line.long 0x00 "LUT66,LUT 66 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x30C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x30C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x30C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x30C))&0xFC00)==0x7C00))) group.long 0x30C++0x03 line.long 0x00 "LUT67,LUT 67 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x30C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x30C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x30C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x30C))&0xFC00)==0x7C00)) group.long 0x30C++0x03 line.long 0x00 "LUT67,LUT 67 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x30C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x30C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x30C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x30C))&0xFC00)!=0x7C00)) group.long 0x30C++0x03 line.long 0x00 "LUT67,LUT 67 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x30C++0x03 line.long 0x00 "LUT67,LUT 67 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x310))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x310))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x310))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x310))&0xFC00)==0x7C00))) group.long 0x310++0x03 line.long 0x00 "LUT68,LUT 68 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x310))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x310))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x310))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x310))&0xFC00)==0x7C00)) group.long 0x310++0x03 line.long 0x00 "LUT68,LUT 68 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x310))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x310))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x310))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x310))&0xFC00)!=0x7C00)) group.long 0x310++0x03 line.long 0x00 "LUT68,LUT 68 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x310++0x03 line.long 0x00 "LUT68,LUT 68 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x314))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x314))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x314))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x314))&0xFC00)==0x7C00))) group.long 0x314++0x03 line.long 0x00 "LUT69,LUT 69 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x314))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x314))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x314))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x314))&0xFC00)==0x7C00)) group.long 0x314++0x03 line.long 0x00 "LUT69,LUT 69 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x314))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x314))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x314))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x314))&0xFC00)!=0x7C00)) group.long 0x314++0x03 line.long 0x00 "LUT69,LUT 69 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x314++0x03 line.long 0x00 "LUT69,LUT 69 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x318))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x318))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x318))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x318))&0xFC00)==0x7C00))) group.long 0x318++0x03 line.long 0x00 "LUT70,LUT 70 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x318))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x318))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x318))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x318))&0xFC00)==0x7C00)) group.long 0x318++0x03 line.long 0x00 "LUT70,LUT 70 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x318))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x318))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x318))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x318))&0xFC00)!=0x7C00)) group.long 0x318++0x03 line.long 0x00 "LUT70,LUT 70 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x318++0x03 line.long 0x00 "LUT70,LUT 70 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x31C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x31C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x31C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x31C))&0xFC00)==0x7C00))) group.long 0x31C++0x03 line.long 0x00 "LUT71,LUT 71 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x31C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x31C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x31C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x31C))&0xFC00)==0x7C00)) group.long 0x31C++0x03 line.long 0x00 "LUT71,LUT 71 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x31C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x31C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x31C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x31C))&0xFC00)!=0x7C00)) group.long 0x31C++0x03 line.long 0x00 "LUT71,LUT 71 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x31C++0x03 line.long 0x00 "LUT71,LUT 71 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x320))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x320))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x320))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x320))&0xFC00)==0x7C00))) group.long 0x320++0x03 line.long 0x00 "LUT72,LUT 72 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x320))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x320))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x320))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x320))&0xFC00)==0x7C00)) group.long 0x320++0x03 line.long 0x00 "LUT72,LUT 72 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x320))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x320))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x320))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x320))&0xFC00)!=0x7C00)) group.long 0x320++0x03 line.long 0x00 "LUT72,LUT 72 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x320++0x03 line.long 0x00 "LUT72,LUT 72 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x324))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x324))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x324))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x324))&0xFC00)==0x7C00))) group.long 0x324++0x03 line.long 0x00 "LUT73,LUT 73 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x324))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x324))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x324))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x324))&0xFC00)==0x7C00)) group.long 0x324++0x03 line.long 0x00 "LUT73,LUT 73 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x324))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x324))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x324))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x324))&0xFC00)!=0x7C00)) group.long 0x324++0x03 line.long 0x00 "LUT73,LUT 73 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x324++0x03 line.long 0x00 "LUT73,LUT 73 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x328))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x328))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x328))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x328))&0xFC00)==0x7C00))) group.long 0x328++0x03 line.long 0x00 "LUT74,LUT 74 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x328))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x328))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x328))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x328))&0xFC00)==0x7C00)) group.long 0x328++0x03 line.long 0x00 "LUT74,LUT 74 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x328))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x328))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x328))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x328))&0xFC00)!=0x7C00)) group.long 0x328++0x03 line.long 0x00 "LUT74,LUT 74 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x328++0x03 line.long 0x00 "LUT74,LUT 74 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x32C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x32C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x32C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x32C))&0xFC00)==0x7C00))) group.long 0x32C++0x03 line.long 0x00 "LUT75,LUT 75 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x32C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x32C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x32C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x32C))&0xFC00)==0x7C00)) group.long 0x32C++0x03 line.long 0x00 "LUT75,LUT 75 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x32C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x32C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x32C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x32C))&0xFC00)!=0x7C00)) group.long 0x32C++0x03 line.long 0x00 "LUT75,LUT 75 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x32C++0x03 line.long 0x00 "LUT75,LUT 75 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x330))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x330))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x330))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x330))&0xFC00)==0x7C00))) group.long 0x330++0x03 line.long 0x00 "LUT76,LUT 76 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x330))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x330))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x330))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x330))&0xFC00)==0x7C00)) group.long 0x330++0x03 line.long 0x00 "LUT76,LUT 76 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x330))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x330))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x330))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x330))&0xFC00)!=0x7C00)) group.long 0x330++0x03 line.long 0x00 "LUT76,LUT 76 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x330++0x03 line.long 0x00 "LUT76,LUT 76 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x334))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x334))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x334))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x334))&0xFC00)==0x7C00))) group.long 0x334++0x03 line.long 0x00 "LUT77,LUT 77 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x334))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x334))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x334))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x334))&0xFC00)==0x7C00)) group.long 0x334++0x03 line.long 0x00 "LUT77,LUT 77 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x334))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x334))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x334))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x334))&0xFC00)!=0x7C00)) group.long 0x334++0x03 line.long 0x00 "LUT77,LUT 77 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x334++0x03 line.long 0x00 "LUT77,LUT 77 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x338))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x338))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x338))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x338))&0xFC00)==0x7C00))) group.long 0x338++0x03 line.long 0x00 "LUT78,LUT 78 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x338))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x338))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x338))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x338))&0xFC00)==0x7C00)) group.long 0x338++0x03 line.long 0x00 "LUT78,LUT 78 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x338))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x338))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x338))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x338))&0xFC00)!=0x7C00)) group.long 0x338++0x03 line.long 0x00 "LUT78,LUT 78 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x338++0x03 line.long 0x00 "LUT78,LUT 78 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x33C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x33C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x33C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x33C))&0xFC00)==0x7C00))) group.long 0x33C++0x03 line.long 0x00 "LUT79,LUT 79 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x33C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x33C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x33C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x33C))&0xFC00)==0x7C00)) group.long 0x33C++0x03 line.long 0x00 "LUT79,LUT 79 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x33C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x33C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x33C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x33C))&0xFC00)!=0x7C00)) group.long 0x33C++0x03 line.long 0x00 "LUT79,LUT 79 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x33C++0x03 line.long 0x00 "LUT79,LUT 79 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x340))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x340))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x340))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x340))&0xFC00)==0x7C00))) group.long 0x340++0x03 line.long 0x00 "LUT80,LUT 80 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x340))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x340))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x340))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x340))&0xFC00)==0x7C00)) group.long 0x340++0x03 line.long 0x00 "LUT80,LUT 80 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x340))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x340))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x340))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x340))&0xFC00)!=0x7C00)) group.long 0x340++0x03 line.long 0x00 "LUT80,LUT 80 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x340++0x03 line.long 0x00 "LUT80,LUT 80 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x344))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x344))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x344))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x344))&0xFC00)==0x7C00))) group.long 0x344++0x03 line.long 0x00 "LUT81,LUT 81 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x344))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x344))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x344))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x344))&0xFC00)==0x7C00)) group.long 0x344++0x03 line.long 0x00 "LUT81,LUT 81 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x344))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x344))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x344))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x344))&0xFC00)!=0x7C00)) group.long 0x344++0x03 line.long 0x00 "LUT81,LUT 81 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x344++0x03 line.long 0x00 "LUT81,LUT 81 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x348))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x348))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x348))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x348))&0xFC00)==0x7C00))) group.long 0x348++0x03 line.long 0x00 "LUT82,LUT 82 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x348))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x348))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x348))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x348))&0xFC00)==0x7C00)) group.long 0x348++0x03 line.long 0x00 "LUT82,LUT 82 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x348))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x348))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x348))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x348))&0xFC00)!=0x7C00)) group.long 0x348++0x03 line.long 0x00 "LUT82,LUT 82 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x348++0x03 line.long 0x00 "LUT82,LUT 82 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x34C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x34C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x34C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x34C))&0xFC00)==0x7C00))) group.long 0x34C++0x03 line.long 0x00 "LUT83,LUT 83 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x34C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x34C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x34C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x34C))&0xFC00)==0x7C00)) group.long 0x34C++0x03 line.long 0x00 "LUT83,LUT 83 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x34C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x34C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x34C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x34C))&0xFC00)!=0x7C00)) group.long 0x34C++0x03 line.long 0x00 "LUT83,LUT 83 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x34C++0x03 line.long 0x00 "LUT83,LUT 83 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x350))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x350))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x350))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x350))&0xFC00)==0x7C00))) group.long 0x350++0x03 line.long 0x00 "LUT84,LUT 84 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x350))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x350))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x350))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x350))&0xFC00)==0x7C00)) group.long 0x350++0x03 line.long 0x00 "LUT84,LUT 84 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x350))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x350))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x350))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x350))&0xFC00)!=0x7C00)) group.long 0x350++0x03 line.long 0x00 "LUT84,LUT 84 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x350++0x03 line.long 0x00 "LUT84,LUT 84 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x354))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x354))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x354))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x354))&0xFC00)==0x7C00))) group.long 0x354++0x03 line.long 0x00 "LUT85,LUT 85 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x354))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x354))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x354))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x354))&0xFC00)==0x7C00)) group.long 0x354++0x03 line.long 0x00 "LUT85,LUT 85 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x354))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x354))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x354))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x354))&0xFC00)!=0x7C00)) group.long 0x354++0x03 line.long 0x00 "LUT85,LUT 85 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x354++0x03 line.long 0x00 "LUT85,LUT 85 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x358))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x358))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x358))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x358))&0xFC00)==0x7C00))) group.long 0x358++0x03 line.long 0x00 "LUT86,LUT 86 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x358))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x358))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x358))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x358))&0xFC00)==0x7C00)) group.long 0x358++0x03 line.long 0x00 "LUT86,LUT 86 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x358))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x358))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x358))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x358))&0xFC00)!=0x7C00)) group.long 0x358++0x03 line.long 0x00 "LUT86,LUT 86 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x358++0x03 line.long 0x00 "LUT86,LUT 86 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x35C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x35C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x35C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x35C))&0xFC00)==0x7C00))) group.long 0x35C++0x03 line.long 0x00 "LUT87,LUT 87 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x35C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x35C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x35C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x35C))&0xFC00)==0x7C00)) group.long 0x35C++0x03 line.long 0x00 "LUT87,LUT 87 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x35C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x35C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x35C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x35C))&0xFC00)!=0x7C00)) group.long 0x35C++0x03 line.long 0x00 "LUT87,LUT 87 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x35C++0x03 line.long 0x00 "LUT87,LUT 87 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x360))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x360))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x360))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x360))&0xFC00)==0x7C00))) group.long 0x360++0x03 line.long 0x00 "LUT88,LUT 88 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x360))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x360))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x360))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x360))&0xFC00)==0x7C00)) group.long 0x360++0x03 line.long 0x00 "LUT88,LUT 88 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x360))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x360))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x360))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x360))&0xFC00)!=0x7C00)) group.long 0x360++0x03 line.long 0x00 "LUT88,LUT 88 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x360++0x03 line.long 0x00 "LUT88,LUT 88 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x364))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x364))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x364))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x364))&0xFC00)==0x7C00))) group.long 0x364++0x03 line.long 0x00 "LUT89,LUT 89 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x364))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x364))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x364))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x364))&0xFC00)==0x7C00)) group.long 0x364++0x03 line.long 0x00 "LUT89,LUT 89 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x364))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x364))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x364))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x364))&0xFC00)!=0x7C00)) group.long 0x364++0x03 line.long 0x00 "LUT89,LUT 89 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x364++0x03 line.long 0x00 "LUT89,LUT 89 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x368))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x368))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x368))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x368))&0xFC00)==0x7C00))) group.long 0x368++0x03 line.long 0x00 "LUT90,LUT 90 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x368))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x368))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x368))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x368))&0xFC00)==0x7C00)) group.long 0x368++0x03 line.long 0x00 "LUT90,LUT 90 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x368))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x368))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x368))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x368))&0xFC00)!=0x7C00)) group.long 0x368++0x03 line.long 0x00 "LUT90,LUT 90 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x368++0x03 line.long 0x00 "LUT90,LUT 90 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x36C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x36C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x36C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x36C))&0xFC00)==0x7C00))) group.long 0x36C++0x03 line.long 0x00 "LUT91,LUT 91 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x36C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x36C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x36C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x36C))&0xFC00)==0x7C00)) group.long 0x36C++0x03 line.long 0x00 "LUT91,LUT 91 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x36C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x36C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x36C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x36C))&0xFC00)!=0x7C00)) group.long 0x36C++0x03 line.long 0x00 "LUT91,LUT 91 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x36C++0x03 line.long 0x00 "LUT91,LUT 91 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x370))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x370))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x370))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x370))&0xFC00)==0x7C00))) group.long 0x370++0x03 line.long 0x00 "LUT92,LUT 92 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x370))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x370))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x370))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x370))&0xFC00)==0x7C00)) group.long 0x370++0x03 line.long 0x00 "LUT92,LUT 92 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x370))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x370))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x370))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x370))&0xFC00)!=0x7C00)) group.long 0x370++0x03 line.long 0x00 "LUT92,LUT 92 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x370++0x03 line.long 0x00 "LUT92,LUT 92 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x374))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x374))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x374))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x374))&0xFC00)==0x7C00))) group.long 0x374++0x03 line.long 0x00 "LUT93,LUT 93 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x374))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x374))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x374))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x374))&0xFC00)==0x7C00)) group.long 0x374++0x03 line.long 0x00 "LUT93,LUT 93 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x374))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x374))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x374))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x374))&0xFC00)!=0x7C00)) group.long 0x374++0x03 line.long 0x00 "LUT93,LUT 93 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x374++0x03 line.long 0x00 "LUT93,LUT 93 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x378))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x378))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x378))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x378))&0xFC00)==0x7C00))) group.long 0x378++0x03 line.long 0x00 "LUT94,LUT 94 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x378))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x378))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x378))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x378))&0xFC00)==0x7C00)) group.long 0x378++0x03 line.long 0x00 "LUT94,LUT 94 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x378))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x378))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x378))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x378))&0xFC00)!=0x7C00)) group.long 0x378++0x03 line.long 0x00 "LUT94,LUT 94 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x378++0x03 line.long 0x00 "LUT94,LUT 94 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x37C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x37C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x37C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x37C))&0xFC00)==0x7C00))) group.long 0x37C++0x03 line.long 0x00 "LUT95,LUT 95 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x37C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x37C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x37C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x37C))&0xFC00)==0x7C00)) group.long 0x37C++0x03 line.long 0x00 "LUT95,LUT 95 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x37C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x37C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x37C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x37C))&0xFC00)!=0x7C00)) group.long 0x37C++0x03 line.long 0x00 "LUT95,LUT 95 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x37C++0x03 line.long 0x00 "LUT95,LUT 95 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x380))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x380))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x380))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x380))&0xFC00)==0x7C00))) group.long 0x380++0x03 line.long 0x00 "LUT96,LUT 96 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x380))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x380))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x380))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x380))&0xFC00)==0x7C00)) group.long 0x380++0x03 line.long 0x00 "LUT96,LUT 96 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x380))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x380))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x380))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x380))&0xFC00)!=0x7C00)) group.long 0x380++0x03 line.long 0x00 "LUT96,LUT 96 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x380++0x03 line.long 0x00 "LUT96,LUT 96 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x384))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x384))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x384))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x384))&0xFC00)==0x7C00))) group.long 0x384++0x03 line.long 0x00 "LUT97,LUT 97 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x384))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x384))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x384))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x384))&0xFC00)==0x7C00)) group.long 0x384++0x03 line.long 0x00 "LUT97,LUT 97 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x384))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x384))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x384))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x384))&0xFC00)!=0x7C00)) group.long 0x384++0x03 line.long 0x00 "LUT97,LUT 97 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x384++0x03 line.long 0x00 "LUT97,LUT 97 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x388))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x388))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x388))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x388))&0xFC00)==0x7C00))) group.long 0x388++0x03 line.long 0x00 "LUT98,LUT 98 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x388))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x388))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x388))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x388))&0xFC00)==0x7C00)) group.long 0x388++0x03 line.long 0x00 "LUT98,LUT 98 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x388))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x388))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x388))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x388))&0xFC00)!=0x7C00)) group.long 0x388++0x03 line.long 0x00 "LUT98,LUT 98 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x388++0x03 line.long 0x00 "LUT98,LUT 98 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x38C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x38C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x38C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x38C))&0xFC00)==0x7C00))) group.long 0x38C++0x03 line.long 0x00 "LUT99,LUT 99 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x38C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x38C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x38C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x38C))&0xFC00)==0x7C00)) group.long 0x38C++0x03 line.long 0x00 "LUT99,LUT 99 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x38C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x38C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x38C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x38C))&0xFC00)!=0x7C00)) group.long 0x38C++0x03 line.long 0x00 "LUT99,LUT 99 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x38C++0x03 line.long 0x00 "LUT99,LUT 99 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x390))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x390))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x390))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x390))&0xFC00)==0x7C00))) group.long 0x390++0x03 line.long 0x00 "LUT100,LUT 100 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x390))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x390))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x390))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x390))&0xFC00)==0x7C00)) group.long 0x390++0x03 line.long 0x00 "LUT100,LUT 100 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x390))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x390))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x390))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x390))&0xFC00)!=0x7C00)) group.long 0x390++0x03 line.long 0x00 "LUT100,LUT 100 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x390++0x03 line.long 0x00 "LUT100,LUT 100 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x394))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x394))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x394))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x394))&0xFC00)==0x7C00))) group.long 0x394++0x03 line.long 0x00 "LUT101,LUT 101 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x394))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x394))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x394))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x394))&0xFC00)==0x7C00)) group.long 0x394++0x03 line.long 0x00 "LUT101,LUT 101 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x394))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x394))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x394))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x394))&0xFC00)!=0x7C00)) group.long 0x394++0x03 line.long 0x00 "LUT101,LUT 101 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x394++0x03 line.long 0x00 "LUT101,LUT 101 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x398))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x398))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x398))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x398))&0xFC00)==0x7C00))) group.long 0x398++0x03 line.long 0x00 "LUT102,LUT 102 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x398))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x398))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x398))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x398))&0xFC00)==0x7C00)) group.long 0x398++0x03 line.long 0x00 "LUT102,LUT 102 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x398))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x398))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x398))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x398))&0xFC00)!=0x7C00)) group.long 0x398++0x03 line.long 0x00 "LUT102,LUT 102 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x398++0x03 line.long 0x00 "LUT102,LUT 102 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x39C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x39C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x39C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x39C))&0xFC00)==0x7C00))) group.long 0x39C++0x03 line.long 0x00 "LUT103,LUT 103 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x39C))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x39C))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x39C))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x39C))&0xFC00)==0x7C00)) group.long 0x39C++0x03 line.long 0x00 "LUT103,LUT 103 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x39C))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x39C))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x39C))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x39C))&0xFC00)!=0x7C00)) group.long 0x39C++0x03 line.long 0x00 "LUT103,LUT 103 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x39C++0x03 line.long 0x00 "LUT103,LUT 103 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x3A0))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3A0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3A0))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3A0))&0xFC00)==0x7C00))) group.long 0x3A0++0x03 line.long 0x00 "LUT104,LUT 104 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3A0))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x3A0))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x3A0))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3A0))&0xFC00)==0x7C00)) group.long 0x3A0++0x03 line.long 0x00 "LUT104,LUT 104 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3A0))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3A0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3A0))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x3A0))&0xFC00)!=0x7C00)) group.long 0x3A0++0x03 line.long 0x00 "LUT104,LUT 104 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3A0++0x03 line.long 0x00 "LUT104,LUT 104 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x3A4))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3A4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3A4))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3A4))&0xFC00)==0x7C00))) group.long 0x3A4++0x03 line.long 0x00 "LUT105,LUT 105 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3A4))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x3A4))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x3A4))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3A4))&0xFC00)==0x7C00)) group.long 0x3A4++0x03 line.long 0x00 "LUT105,LUT 105 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3A4))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3A4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3A4))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x3A4))&0xFC00)!=0x7C00)) group.long 0x3A4++0x03 line.long 0x00 "LUT105,LUT 105 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3A4++0x03 line.long 0x00 "LUT105,LUT 105 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x3A8))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3A8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3A8))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3A8))&0xFC00)==0x7C00))) group.long 0x3A8++0x03 line.long 0x00 "LUT106,LUT 106 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3A8))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x3A8))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x3A8))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3A8))&0xFC00)==0x7C00)) group.long 0x3A8++0x03 line.long 0x00 "LUT106,LUT 106 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3A8))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3A8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3A8))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x3A8))&0xFC00)!=0x7C00)) group.long 0x3A8++0x03 line.long 0x00 "LUT106,LUT 106 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3A8++0x03 line.long 0x00 "LUT106,LUT 106 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x3AC))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3AC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3AC))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3AC))&0xFC00)==0x7C00))) group.long 0x3AC++0x03 line.long 0x00 "LUT107,LUT 107 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3AC))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x3AC))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x3AC))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3AC))&0xFC00)==0x7C00)) group.long 0x3AC++0x03 line.long 0x00 "LUT107,LUT 107 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3AC))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3AC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3AC))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x3AC))&0xFC00)!=0x7C00)) group.long 0x3AC++0x03 line.long 0x00 "LUT107,LUT 107 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3AC++0x03 line.long 0x00 "LUT107,LUT 107 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x3B0))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3B0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3B0))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3B0))&0xFC00)==0x7C00))) group.long 0x3B0++0x03 line.long 0x00 "LUT108,LUT 108 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3B0))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x3B0))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x3B0))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3B0))&0xFC00)==0x7C00)) group.long 0x3B0++0x03 line.long 0x00 "LUT108,LUT 108 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3B0))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3B0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3B0))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x3B0))&0xFC00)!=0x7C00)) group.long 0x3B0++0x03 line.long 0x00 "LUT108,LUT 108 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3B0++0x03 line.long 0x00 "LUT108,LUT 108 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x3B4))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3B4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3B4))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3B4))&0xFC00)==0x7C00))) group.long 0x3B4++0x03 line.long 0x00 "LUT109,LUT 109 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3B4))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x3B4))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x3B4))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3B4))&0xFC00)==0x7C00)) group.long 0x3B4++0x03 line.long 0x00 "LUT109,LUT 109 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3B4))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3B4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3B4))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x3B4))&0xFC00)!=0x7C00)) group.long 0x3B4++0x03 line.long 0x00 "LUT109,LUT 109 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3B4++0x03 line.long 0x00 "LUT109,LUT 109 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x3B8))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3B8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3B8))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3B8))&0xFC00)==0x7C00))) group.long 0x3B8++0x03 line.long 0x00 "LUT110,LUT 110 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3B8))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x3B8))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x3B8))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3B8))&0xFC00)==0x7C00)) group.long 0x3B8++0x03 line.long 0x00 "LUT110,LUT 110 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3B8))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3B8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3B8))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x3B8))&0xFC00)!=0x7C00)) group.long 0x3B8++0x03 line.long 0x00 "LUT110,LUT 110 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3B8++0x03 line.long 0x00 "LUT110,LUT 110 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x3BC))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3BC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3BC))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3BC))&0xFC00)==0x7C00))) group.long 0x3BC++0x03 line.long 0x00 "LUT111,LUT 111 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3BC))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x3BC))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x3BC))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3BC))&0xFC00)==0x7C00)) group.long 0x3BC++0x03 line.long 0x00 "LUT111,LUT 111 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3BC))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3BC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3BC))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x3BC))&0xFC00)!=0x7C00)) group.long 0x3BC++0x03 line.long 0x00 "LUT111,LUT 111 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3BC++0x03 line.long 0x00 "LUT111,LUT 111 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x3C0))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3C0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3C0))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3C0))&0xFC00)==0x7C00))) group.long 0x3C0++0x03 line.long 0x00 "LUT112,LUT 112 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3C0))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x3C0))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x3C0))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3C0))&0xFC00)==0x7C00)) group.long 0x3C0++0x03 line.long 0x00 "LUT112,LUT 112 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3C0))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3C0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3C0))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x3C0))&0xFC00)!=0x7C00)) group.long 0x3C0++0x03 line.long 0x00 "LUT112,LUT 112 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3C0++0x03 line.long 0x00 "LUT112,LUT 112 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x3C4))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3C4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3C4))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3C4))&0xFC00)==0x7C00))) group.long 0x3C4++0x03 line.long 0x00 "LUT113,LUT 113 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3C4))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x3C4))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x3C4))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3C4))&0xFC00)==0x7C00)) group.long 0x3C4++0x03 line.long 0x00 "LUT113,LUT 113 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3C4))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3C4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3C4))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x3C4))&0xFC00)!=0x7C00)) group.long 0x3C4++0x03 line.long 0x00 "LUT113,LUT 113 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3C4++0x03 line.long 0x00 "LUT113,LUT 113 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x3C8))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3C8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3C8))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3C8))&0xFC00)==0x7C00))) group.long 0x3C8++0x03 line.long 0x00 "LUT114,LUT 114 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3C8))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x3C8))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x3C8))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3C8))&0xFC00)==0x7C00)) group.long 0x3C8++0x03 line.long 0x00 "LUT114,LUT 114 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3C8))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3C8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3C8))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x3C8))&0xFC00)!=0x7C00)) group.long 0x3C8++0x03 line.long 0x00 "LUT114,LUT 114 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3C8++0x03 line.long 0x00 "LUT114,LUT 114 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x3CC))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3CC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3CC))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3CC))&0xFC00)==0x7C00))) group.long 0x3CC++0x03 line.long 0x00 "LUT115,LUT 115 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3CC))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x3CC))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x3CC))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3CC))&0xFC00)==0x7C00)) group.long 0x3CC++0x03 line.long 0x00 "LUT115,LUT 115 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3CC))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3CC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3CC))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x3CC))&0xFC00)!=0x7C00)) group.long 0x3CC++0x03 line.long 0x00 "LUT115,LUT 115 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3CC++0x03 line.long 0x00 "LUT115,LUT 115 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x3D0))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3D0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3D0))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3D0))&0xFC00)==0x7C00))) group.long 0x3D0++0x03 line.long 0x00 "LUT116,LUT 116 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3D0))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x3D0))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x3D0))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3D0))&0xFC00)==0x7C00)) group.long 0x3D0++0x03 line.long 0x00 "LUT116,LUT 116 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3D0))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3D0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3D0))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x3D0))&0xFC00)!=0x7C00)) group.long 0x3D0++0x03 line.long 0x00 "LUT116,LUT 116 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3D0++0x03 line.long 0x00 "LUT116,LUT 116 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x3D4))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3D4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3D4))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3D4))&0xFC00)==0x7C00))) group.long 0x3D4++0x03 line.long 0x00 "LUT117,LUT 117 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3D4))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x3D4))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x3D4))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3D4))&0xFC00)==0x7C00)) group.long 0x3D4++0x03 line.long 0x00 "LUT117,LUT 117 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3D4))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3D4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3D4))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x3D4))&0xFC00)!=0x7C00)) group.long 0x3D4++0x03 line.long 0x00 "LUT117,LUT 117 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3D4++0x03 line.long 0x00 "LUT117,LUT 117 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x3D8))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3D8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3D8))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3D8))&0xFC00)==0x7C00))) group.long 0x3D8++0x03 line.long 0x00 "LUT118,LUT 118 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3D8))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x3D8))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x3D8))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3D8))&0xFC00)==0x7C00)) group.long 0x3D8++0x03 line.long 0x00 "LUT118,LUT 118 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3D8))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3D8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3D8))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x3D8))&0xFC00)!=0x7C00)) group.long 0x3D8++0x03 line.long 0x00 "LUT118,LUT 118 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3D8++0x03 line.long 0x00 "LUT118,LUT 118 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x3DC))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3DC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3DC))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3DC))&0xFC00)==0x7C00))) group.long 0x3DC++0x03 line.long 0x00 "LUT119,LUT 119 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3DC))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x3DC))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x3DC))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3DC))&0xFC00)==0x7C00)) group.long 0x3DC++0x03 line.long 0x00 "LUT119,LUT 119 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3DC))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3DC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3DC))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x3DC))&0xFC00)!=0x7C00)) group.long 0x3DC++0x03 line.long 0x00 "LUT119,LUT 119 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3DC++0x03 line.long 0x00 "LUT119,LUT 119 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x3E0))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3E0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3E0))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3E0))&0xFC00)==0x7C00))) group.long 0x3E0++0x03 line.long 0x00 "LUT120,LUT 120 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3E0))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x3E0))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x3E0))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3E0))&0xFC00)==0x7C00)) group.long 0x3E0++0x03 line.long 0x00 "LUT120,LUT 120 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3E0))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3E0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3E0))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x3E0))&0xFC00)!=0x7C00)) group.long 0x3E0++0x03 line.long 0x00 "LUT120,LUT 120 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3E0++0x03 line.long 0x00 "LUT120,LUT 120 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x3E4))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3E4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3E4))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3E4))&0xFC00)==0x7C00))) group.long 0x3E4++0x03 line.long 0x00 "LUT121,LUT 121 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3E4))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x3E4))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x3E4))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3E4))&0xFC00)==0x7C00)) group.long 0x3E4++0x03 line.long 0x00 "LUT121,LUT 121 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3E4))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3E4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3E4))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x3E4))&0xFC00)!=0x7C00)) group.long 0x3E4++0x03 line.long 0x00 "LUT121,LUT 121 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3E4++0x03 line.long 0x00 "LUT121,LUT 121 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x3E8))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3E8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3E8))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3E8))&0xFC00)==0x7C00))) group.long 0x3E8++0x03 line.long 0x00 "LUT122,LUT 122 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3E8))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x3E8))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x3E8))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3E8))&0xFC00)==0x7C00)) group.long 0x3E8++0x03 line.long 0x00 "LUT122,LUT 122 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3E8))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3E8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3E8))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x3E8))&0xFC00)!=0x7C00)) group.long 0x3E8++0x03 line.long 0x00 "LUT122,LUT 122 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3E8++0x03 line.long 0x00 "LUT122,LUT 122 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x3EC))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3EC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3EC))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3EC))&0xFC00)==0x7C00))) group.long 0x3EC++0x03 line.long 0x00 "LUT123,LUT 123 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3EC))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x3EC))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x3EC))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3EC))&0xFC00)==0x7C00)) group.long 0x3EC++0x03 line.long 0x00 "LUT123,LUT 123 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3EC))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3EC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3EC))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x3EC))&0xFC00)!=0x7C00)) group.long 0x3EC++0x03 line.long 0x00 "LUT123,LUT 123 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3EC++0x03 line.long 0x00 "LUT123,LUT 123 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x3F0))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3F0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3F0))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3F0))&0xFC00)==0x7C00))) group.long 0x3F0++0x03 line.long 0x00 "LUT124,LUT 124 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3F0))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x3F0))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x3F0))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3F0))&0xFC00)==0x7C00)) group.long 0x3F0++0x03 line.long 0x00 "LUT124,LUT 124 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3F0))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3F0))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3F0))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x3F0))&0xFC00)!=0x7C00)) group.long 0x3F0++0x03 line.long 0x00 "LUT124,LUT 124 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3F0++0x03 line.long 0x00 "LUT124,LUT 124 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x3F4))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3F4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3F4))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3F4))&0xFC00)==0x7C00))) group.long 0x3F4++0x03 line.long 0x00 "LUT125,LUT 125 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3F4))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x3F4))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x3F4))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3F4))&0xFC00)==0x7C00)) group.long 0x3F4++0x03 line.long 0x00 "LUT125,LUT 125 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3F4))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3F4))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3F4))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x3F4))&0xFC00)!=0x7C00)) group.long 0x3F4++0x03 line.long 0x00 "LUT125,LUT 125 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3F4++0x03 line.long 0x00 "LUT125,LUT 125 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x3F8))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3F8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3F8))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3F8))&0xFC00)==0x7C00))) group.long 0x3F8++0x03 line.long 0x00 "LUT126,LUT 126 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3F8))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x3F8))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x3F8))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3F8))&0xFC00)==0x7C00)) group.long 0x3F8++0x03 line.long 0x00 "LUT126,LUT 126 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3F8))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3F8))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3F8))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x3F8))&0xFC00)!=0x7C00)) group.long 0x3F8++0x03 line.long 0x00 "LUT126,LUT 126 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3F8++0x03 line.long 0x00 "LUT126,LUT 126 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif if (((((per.l(ad:0x5D130000+0x3FC))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3FC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3FC))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3FC))&0xFC00)==0x7C00))) group.long 0x3FC++0x03 line.long 0x00 "LUT127,LUT 127 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3FC))&0xFC000000)!=0x00)&&(((per.l(ad:0x5D130000+0x3FC))&0xFC000000)!=0x7C000000))&&((((per.l(ad:0x5D130000+0x3FC))&0xFC00)==0x00)||(((per.l(ad:0x5D130000+0x3FC))&0xFC00)==0x7C00)) group.long 0x3FC++0x03 line.long 0x00 "LUT127,LUT 127 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "0,?..." hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" elif ((((per.l(ad:0x5D130000+0x3FC))&0xFC000000)==0x00)||(((per.l(ad:0x5D130000+0x3FC))&0xFC000000)==0x7C000000))&&((((per.l(ad:0x5D130000+0x3FC))&0xFC00)!=0x00)&&(((per.l(ad:0x5D130000+0x3FC))&0xFC00)!=0x7C00)) group.long 0x3FC++0x03 line.long 0x00 "LUT127,LUT 127 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "0,?..." hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" else group.long 0x3FC++0x03 line.long 0x00 "LUT127,LUT 127 Register" bitfld.long 0x00 26.--31. " OPCODE1 ,OPCODE1" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 24.--25. " NUM_PADS1 ,NUM_PADS1" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 16.--23. 1. " OPERAND1 ,OPERAND1" newline bitfld.long 0x00 10.--15. " OPCODE0 ,OPCODE0" "STOP,CMD_SDR,RADDR_SDR,CADDR_SDR,MODE1_SDR,MODE2_SDR,MODE4_SDR,MODE8_SDR,WRITE_SDR,READ_SDR,LEARN_SDR,DATSZ_SDR,DUMMY_SDR,DUMMY_RWDS_SDR,,,,,,,,,,,,,,,,,,JMP_ON_CS,,CMD_DDR,RADDR_DDR,CADDR_DDR,MODE1_DDR,MODE2_DDR,MODE4_DDR,MODE8_DDR,WRITE_DDR,READ_DDR,LEARN_DDR,DATSZ_DDR,DUMMY_DDR,DUMMY_RWDS_DDR,?..." bitfld.long 0x00 8.--9. " NUM_PADS0 ,NUM_PADS0" "Single,Dual,Quad,Octal" hexmask.long.byte 0x00 0.--7. 1. " OPERAND0 ,OPERAND0" endif tree.end width 0x0B tree.end tree.end tree.open "GPT (General Purpose Timer)" tree "GPT0" base ad:0x5D140000 width 6. group.long 0x00++0x1B line.long 0x00 "CR,Control Register" bitfld.long 0x00 31. " FO3 ,Force output compare channel 3" "No effect,Force" bitfld.long 0x00 30. " FO2 ,Force output compare channel 2" "No effect,Force" bitfld.long 0x00 29. " FO1 ,Force output compare channel 1" "No effect,Force" bitfld.long 0x00 26.--28. " OM3 ,Output compare channel 3 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" newline bitfld.long 0x00 23.--25. " OM2 ,Output compare channel 2 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 20.--22. " OM1 ,Output compare channel 1 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 18.--19. " IM2 ,Input capture channel 2 operating mode" "Disabled,Rising,Falling,Both edges" bitfld.long 0x00 16.--17. " IM1 ,Input capture channel 1 operating mode" "Disabled,Rising,Falling,Both edges" newline bitfld.long 0x00 15. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 10. " EN_24M ,Enable 24MHz clock input from crystal" "Disabled,Enabled" bitfld.long 0x00 9. " FRR ,Free-run or restart mode" "Restart,Free-Run" bitfld.long 0x00 6.--8. " CLKSRC ,Clock source select" "No clock,Peripheral,High Freq,External,Low Freq,Crystal,?..." newline bitfld.long 0x00 5. " STOPEN ,GPT stop mode" "Disabled,Enabled" bitfld.long 0x00 4. " DOZEEN ,GPT doze mode" "Disabled,Enabled" bitfld.long 0x00 3. " WAITEN ,GPT wait mode enable" "Disabled,Enabled" bitfld.long 0x00 2. " DBGEN ,GPT debug mode enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " ENMOD ,GPT enable mode (main counter value)" "Freeze,Reset" bitfld.long 0x00 0. " EN ,GPT enable" "Disabled,Enabled" line.long 0x04 "PR,Prescaler Register" bitfld.long 0x04 12.--15. " PRESCALER24M ,24 MHz crystal clock prescaler division value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" hexmask.long.word 0x04 0.--11. 1. " PRESCALER ,Clock division coefficient" line.long 0x08 "SR,Status Register" eventfld.long 0x08 5. " ROV ,Rollover flag" "Not occurred,Occurred" eventfld.long 0x08 4. " IF2 ,Input capture 2 flag" "Not occurred,Occurred" eventfld.long 0x08 3. " IF1 ,Input capture 1 flag" "Not occurred,Occurred" eventfld.long 0x08 2. " OF3 ,Output compare 3 flag" "Not occurred,Occurred" newline eventfld.long 0x08 1. " OF2 ,Output compare 2 flag" "Not occurred,Occurred" eventfld.long 0x08 0. " OF1 ,Output compare 1 flag" "Not occurred,Occurred" line.long 0x0C "IR,Interrupt Register" bitfld.long 0x0C 5. " ROVIE ,Rollover interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " IF2IE ,Input capture 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " IF1IE ,Input capture 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 2. " OF3IE ,Output compare 3 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 1. " OF2IE ,Output compare 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " OF1IE ,Output compare 1 interrupt enable" "Disabled,Enabled" line.long 0x10 "OCR1,Output Compare Register 1" line.long 0x14 "OCR2,Output Compare Register 2" line.long 0x18 "OCR3,Output Compare Register 3" rgroup.long 0x1C++0x0B line.long 0x00 "ICR1,Input Compare Register 1" line.long 0x04 "ICR2,Input Compare Register 2" line.long 0x08 "CNT,Counter Register" width 0x0B tree.end tree "GPT1" base ad:0x5D150000 width 6. group.long 0x00++0x1B line.long 0x00 "CR,Control Register" bitfld.long 0x00 31. " FO3 ,Force output compare channel 3" "No effect,Force" bitfld.long 0x00 30. " FO2 ,Force output compare channel 2" "No effect,Force" bitfld.long 0x00 29. " FO1 ,Force output compare channel 1" "No effect,Force" bitfld.long 0x00 26.--28. " OM3 ,Output compare channel 3 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" newline bitfld.long 0x00 23.--25. " OM2 ,Output compare channel 2 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 20.--22. " OM1 ,Output compare channel 1 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 18.--19. " IM2 ,Input capture channel 2 operating mode" "Disabled,Rising,Falling,Both edges" bitfld.long 0x00 16.--17. " IM1 ,Input capture channel 1 operating mode" "Disabled,Rising,Falling,Both edges" newline bitfld.long 0x00 15. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 10. " EN_24M ,Enable 24MHz clock input from crystal" "Disabled,Enabled" bitfld.long 0x00 9. " FRR ,Free-run or restart mode" "Restart,Free-Run" bitfld.long 0x00 6.--8. " CLKSRC ,Clock source select" "No clock,Peripheral,High Freq,External,Low Freq,Crystal,?..." newline bitfld.long 0x00 5. " STOPEN ,GPT stop mode" "Disabled,Enabled" bitfld.long 0x00 4. " DOZEEN ,GPT doze mode" "Disabled,Enabled" bitfld.long 0x00 3. " WAITEN ,GPT wait mode enable" "Disabled,Enabled" bitfld.long 0x00 2. " DBGEN ,GPT debug mode enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " ENMOD ,GPT enable mode (main counter value)" "Freeze,Reset" bitfld.long 0x00 0. " EN ,GPT enable" "Disabled,Enabled" line.long 0x04 "PR,Prescaler Register" bitfld.long 0x04 12.--15. " PRESCALER24M ,24 MHz crystal clock prescaler division value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" hexmask.long.word 0x04 0.--11. 1. " PRESCALER ,Clock division coefficient" line.long 0x08 "SR,Status Register" eventfld.long 0x08 5. " ROV ,Rollover flag" "Not occurred,Occurred" eventfld.long 0x08 4. " IF2 ,Input capture 2 flag" "Not occurred,Occurred" eventfld.long 0x08 3. " IF1 ,Input capture 1 flag" "Not occurred,Occurred" eventfld.long 0x08 2. " OF3 ,Output compare 3 flag" "Not occurred,Occurred" newline eventfld.long 0x08 1. " OF2 ,Output compare 2 flag" "Not occurred,Occurred" eventfld.long 0x08 0. " OF1 ,Output compare 1 flag" "Not occurred,Occurred" line.long 0x0C "IR,Interrupt Register" bitfld.long 0x0C 5. " ROVIE ,Rollover interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " IF2IE ,Input capture 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " IF1IE ,Input capture 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 2. " OF3IE ,Output compare 3 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 1. " OF2IE ,Output compare 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " OF1IE ,Output compare 1 interrupt enable" "Disabled,Enabled" line.long 0x10 "OCR1,Output Compare Register 1" line.long 0x14 "OCR2,Output Compare Register 2" line.long 0x18 "OCR3,Output Compare Register 3" rgroup.long 0x1C++0x0B line.long 0x00 "ICR1,Input Compare Register 1" line.long 0x04 "ICR2,Input Compare Register 2" line.long 0x08 "CNT,Counter Register" width 0x0B tree.end tree "GPT2" base ad:0x5D160000 width 6. group.long 0x00++0x1B line.long 0x00 "CR,Control Register" bitfld.long 0x00 31. " FO3 ,Force output compare channel 3" "No effect,Force" bitfld.long 0x00 30. " FO2 ,Force output compare channel 2" "No effect,Force" bitfld.long 0x00 29. " FO1 ,Force output compare channel 1" "No effect,Force" bitfld.long 0x00 26.--28. " OM3 ,Output compare channel 3 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" newline bitfld.long 0x00 23.--25. " OM2 ,Output compare channel 2 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 20.--22. " OM1 ,Output compare channel 1 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 18.--19. " IM2 ,Input capture channel 2 operating mode" "Disabled,Rising,Falling,Both edges" bitfld.long 0x00 16.--17. " IM1 ,Input capture channel 1 operating mode" "Disabled,Rising,Falling,Both edges" newline bitfld.long 0x00 15. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 10. " EN_24M ,Enable 24MHz clock input from crystal" "Disabled,Enabled" bitfld.long 0x00 9. " FRR ,Free-run or restart mode" "Restart,Free-Run" bitfld.long 0x00 6.--8. " CLKSRC ,Clock source select" "No clock,Peripheral,High Freq,External,Low Freq,Crystal,?..." newline bitfld.long 0x00 5. " STOPEN ,GPT stop mode" "Disabled,Enabled" bitfld.long 0x00 4. " DOZEEN ,GPT doze mode" "Disabled,Enabled" bitfld.long 0x00 3. " WAITEN ,GPT wait mode enable" "Disabled,Enabled" bitfld.long 0x00 2. " DBGEN ,GPT debug mode enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " ENMOD ,GPT enable mode (main counter value)" "Freeze,Reset" bitfld.long 0x00 0. " EN ,GPT enable" "Disabled,Enabled" line.long 0x04 "PR,Prescaler Register" bitfld.long 0x04 12.--15. " PRESCALER24M ,24 MHz crystal clock prescaler division value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" hexmask.long.word 0x04 0.--11. 1. " PRESCALER ,Clock division coefficient" line.long 0x08 "SR,Status Register" eventfld.long 0x08 5. " ROV ,Rollover flag" "Not occurred,Occurred" eventfld.long 0x08 4. " IF2 ,Input capture 2 flag" "Not occurred,Occurred" eventfld.long 0x08 3. " IF1 ,Input capture 1 flag" "Not occurred,Occurred" eventfld.long 0x08 2. " OF3 ,Output compare 3 flag" "Not occurred,Occurred" newline eventfld.long 0x08 1. " OF2 ,Output compare 2 flag" "Not occurred,Occurred" eventfld.long 0x08 0. " OF1 ,Output compare 1 flag" "Not occurred,Occurred" line.long 0x0C "IR,Interrupt Register" bitfld.long 0x0C 5. " ROVIE ,Rollover interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " IF2IE ,Input capture 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " IF1IE ,Input capture 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 2. " OF3IE ,Output compare 3 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 1. " OF2IE ,Output compare 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " OF1IE ,Output compare 1 interrupt enable" "Disabled,Enabled" line.long 0x10 "OCR1,Output Compare Register 1" line.long 0x14 "OCR2,Output Compare Register 2" line.long 0x18 "OCR3,Output Compare Register 3" rgroup.long 0x1C++0x0B line.long 0x00 "ICR1,Input Compare Register 1" line.long 0x04 "ICR2,Input Compare Register 2" line.long 0x08 "CNT,Counter Register" width 0x0B tree.end tree "GPT3" base ad:0x5D170000 width 6. group.long 0x00++0x1B line.long 0x00 "CR,Control Register" bitfld.long 0x00 31. " FO3 ,Force output compare channel 3" "No effect,Force" bitfld.long 0x00 30. " FO2 ,Force output compare channel 2" "No effect,Force" bitfld.long 0x00 29. " FO1 ,Force output compare channel 1" "No effect,Force" bitfld.long 0x00 26.--28. " OM3 ,Output compare channel 3 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" newline bitfld.long 0x00 23.--25. " OM2 ,Output compare channel 2 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 20.--22. " OM1 ,Output compare channel 1 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 18.--19. " IM2 ,Input capture channel 2 operating mode" "Disabled,Rising,Falling,Both edges" bitfld.long 0x00 16.--17. " IM1 ,Input capture channel 1 operating mode" "Disabled,Rising,Falling,Both edges" newline bitfld.long 0x00 15. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 10. " EN_24M ,Enable 24MHz clock input from crystal" "Disabled,Enabled" bitfld.long 0x00 9. " FRR ,Free-run or restart mode" "Restart,Free-Run" bitfld.long 0x00 6.--8. " CLKSRC ,Clock source select" "No clock,Peripheral,High Freq,External,Low Freq,Crystal,?..." newline bitfld.long 0x00 5. " STOPEN ,GPT stop mode" "Disabled,Enabled" bitfld.long 0x00 4. " DOZEEN ,GPT doze mode" "Disabled,Enabled" bitfld.long 0x00 3. " WAITEN ,GPT wait mode enable" "Disabled,Enabled" bitfld.long 0x00 2. " DBGEN ,GPT debug mode enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " ENMOD ,GPT enable mode (main counter value)" "Freeze,Reset" bitfld.long 0x00 0. " EN ,GPT enable" "Disabled,Enabled" line.long 0x04 "PR,Prescaler Register" bitfld.long 0x04 12.--15. " PRESCALER24M ,24 MHz crystal clock prescaler division value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" hexmask.long.word 0x04 0.--11. 1. " PRESCALER ,Clock division coefficient" line.long 0x08 "SR,Status Register" eventfld.long 0x08 5. " ROV ,Rollover flag" "Not occurred,Occurred" eventfld.long 0x08 4. " IF2 ,Input capture 2 flag" "Not occurred,Occurred" eventfld.long 0x08 3. " IF1 ,Input capture 1 flag" "Not occurred,Occurred" eventfld.long 0x08 2. " OF3 ,Output compare 3 flag" "Not occurred,Occurred" newline eventfld.long 0x08 1. " OF2 ,Output compare 2 flag" "Not occurred,Occurred" eventfld.long 0x08 0. " OF1 ,Output compare 1 flag" "Not occurred,Occurred" line.long 0x0C "IR,Interrupt Register" bitfld.long 0x0C 5. " ROVIE ,Rollover interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " IF2IE ,Input capture 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " IF1IE ,Input capture 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 2. " OF3IE ,Output compare 3 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 1. " OF2IE ,Output compare 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " OF1IE ,Output compare 1 interrupt enable" "Disabled,Enabled" line.long 0x10 "OCR1,Output Compare Register 1" line.long 0x14 "OCR2,Output Compare Register 2" line.long 0x18 "OCR3,Output Compare Register 3" rgroup.long 0x1C++0x0B line.long 0x00 "ICR1,Input Compare Register 1" line.long 0x04 "ICR2,Input Compare Register 2" line.long 0x08 "CNT,Counter Register" width 0x0B tree.end tree "GPT4" base ad:0x5D180000 width 6. group.long 0x00++0x1B line.long 0x00 "CR,Control Register" bitfld.long 0x00 31. " FO3 ,Force output compare channel 3" "No effect,Force" bitfld.long 0x00 30. " FO2 ,Force output compare channel 2" "No effect,Force" bitfld.long 0x00 29. " FO1 ,Force output compare channel 1" "No effect,Force" bitfld.long 0x00 26.--28. " OM3 ,Output compare channel 3 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" newline bitfld.long 0x00 23.--25. " OM2 ,Output compare channel 2 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 20.--22. " OM1 ,Output compare channel 1 operating mode" "Disconnected,Toggle,Clear,Set,Active low pulse,Active low pulse,Active low pulse,Active low pulse" bitfld.long 0x00 18.--19. " IM2 ,Input capture channel 2 operating mode" "Disabled,Rising,Falling,Both edges" bitfld.long 0x00 16.--17. " IM1 ,Input capture channel 1 operating mode" "Disabled,Rising,Falling,Both edges" newline bitfld.long 0x00 15. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 10. " EN_24M ,Enable 24MHz clock input from crystal" "Disabled,Enabled" bitfld.long 0x00 9. " FRR ,Free-run or restart mode" "Restart,Free-Run" bitfld.long 0x00 6.--8. " CLKSRC ,Clock source select" "No clock,Peripheral,High Freq,External,Low Freq,Crystal,?..." newline bitfld.long 0x00 5. " STOPEN ,GPT stop mode" "Disabled,Enabled" bitfld.long 0x00 4. " DOZEEN ,GPT doze mode" "Disabled,Enabled" bitfld.long 0x00 3. " WAITEN ,GPT wait mode enable" "Disabled,Enabled" bitfld.long 0x00 2. " DBGEN ,GPT debug mode enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " ENMOD ,GPT enable mode (main counter value)" "Freeze,Reset" bitfld.long 0x00 0. " EN ,GPT enable" "Disabled,Enabled" line.long 0x04 "PR,Prescaler Register" bitfld.long 0x04 12.--15. " PRESCALER24M ,24 MHz crystal clock prescaler division value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" hexmask.long.word 0x04 0.--11. 1. " PRESCALER ,Clock division coefficient" line.long 0x08 "SR,Status Register" eventfld.long 0x08 5. " ROV ,Rollover flag" "Not occurred,Occurred" eventfld.long 0x08 4. " IF2 ,Input capture 2 flag" "Not occurred,Occurred" eventfld.long 0x08 3. " IF1 ,Input capture 1 flag" "Not occurred,Occurred" eventfld.long 0x08 2. " OF3 ,Output compare 3 flag" "Not occurred,Occurred" newline eventfld.long 0x08 1. " OF2 ,Output compare 2 flag" "Not occurred,Occurred" eventfld.long 0x08 0. " OF1 ,Output compare 1 flag" "Not occurred,Occurred" line.long 0x0C "IR,Interrupt Register" bitfld.long 0x0C 5. " ROVIE ,Rollover interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " IF2IE ,Input capture 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " IF1IE ,Input capture 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 2. " OF3IE ,Output compare 3 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 1. " OF2IE ,Output compare 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " OF1IE ,Output compare 1 interrupt enable" "Disabled,Enabled" line.long 0x10 "OCR1,Output Compare Register 1" line.long 0x14 "OCR2,Output Compare Register 2" line.long 0x18 "OCR3,Output Compare Register 3" rgroup.long 0x1C++0x0B line.long 0x00 "ICR1,Input Compare Register 1" line.long 0x04 "ICR2,Input Compare Register 2" line.long 0x08 "CNT,Counter Register" width 0x0B tree.end tree.end tree.open "GPIO (General Purpose Input/Output)" tree "GPIO0" base ad:0x5D080000 width 11. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data Register" bitfld.long 0x00 31. " DR[31] ,Data bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,Data bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,Data bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,Data bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,Data bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,Data bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,Data bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,Data bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,Data bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,Data bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,Data bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,Data bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,Data bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,Data bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,Data bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,Data bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,Data bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,Data bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,Data bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,Data bit 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,Data bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,Data bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,Data bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,Data bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,Data bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,Data bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,Data bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,Data bit 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,Data bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,Data bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,Data bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,Data bit 0" "Low,High" line.long 0x04 "GDIR,GPIO Direction Register" bitfld.long 0x04 31. " GDIR[31] ,GPIO direction 31 bit" "Input,Output" bitfld.long 0x04 30. " [30] ,GPIO direction 30 bit" "Input,Output" bitfld.long 0x04 29. " [29] ,GPIO direction 29 bit" "Input,Output" bitfld.long 0x04 28. " [28] ,GPIO direction 28 bit" "Input,Output" newline bitfld.long 0x04 27. " [27] ,GPIO direction 27 bit" "Input,Output" bitfld.long 0x04 26. " [26] ,GPIO direction 26 bit" "Input,Output" bitfld.long 0x04 25. " [25] ,GPIO direction 25 bit" "Input,Output" bitfld.long 0x04 24. " [24] ,GPIO direction 24 bit" "Input,Output" newline bitfld.long 0x04 23. " [23] ,GPIO direction 23 bit" "Input,Output" bitfld.long 0x04 22. " [22] ,GPIO direction 22 bit" "Input,Output" bitfld.long 0x04 21. " [21] ,GPIO direction 21 bit" "Input,Output" bitfld.long 0x04 20. " [20] ,GPIO direction 20 bit" "Input,Output" newline bitfld.long 0x04 19. " [19] ,GPIO direction 19 bit" "Input,Output" bitfld.long 0x04 18. " [18] ,GPIO direction 18 bit" "Input,Output" bitfld.long 0x04 17. " [17] ,GPIO direction 17 bit" "Input,Output" bitfld.long 0x04 16. " [16] ,GPIO direction 16 bit" "Input,Output" newline bitfld.long 0x04 15. " [15] ,GPIO direction 15 bit" "Input,Output" bitfld.long 0x04 14. " [14] ,GPIO direction 14 bit" "Input,Output" bitfld.long 0x04 13. " [13] ,GPIO direction 13 bit" "Input,Output" bitfld.long 0x04 12. " [12] ,GPIO direction 12 bit" "Input,Output" newline bitfld.long 0x04 11. " [11] ,GPIO direction 11 bit" "Input,Output" bitfld.long 0x04 10. " [10] ,GPIO direction 10 bit" "Input,Output" bitfld.long 0x04 9. " [9] ,GPIO direction 9 bit" "Input,Output" bitfld.long 0x04 8. " [8] ,GPIO direction 8 bit" "Input,Output" newline bitfld.long 0x04 7. " [7] ,GPIO direction 7 bit" "Input,Output" bitfld.long 0x04 6. " [6] ,GPIO direction 6 bit" "Input,Output" bitfld.long 0x04 5. " [5] ,GPIO direction 5 bit" "Input,Output" bitfld.long 0x04 4. " [4] ,GPIO direction 4 bit" "Input,Output" newline bitfld.long 0x04 3. " [3] ,GPIO direction 3 bit" "Input,Output" bitfld.long 0x04 2. " [2] ,GPIO direction 2 bit" "Input,Output" bitfld.long 0x04 1. " [1] ,GPIO direction 1 bit" "Input,Output" bitfld.long 0x04 0. " [0] ,GPIO direction 0 bit" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO Pad Status Register" bitfld.long 0x00 31. " PSR[31] ,GPIO pad status bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,GPIO pad status bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,GPIO pad status bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,GPIO pad status bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,GPIO pad status bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,GPIO pad status bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,GPIO pad status bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,GPIO pad status bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,GPIO pad status bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,GPIO pad status bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,GPIO pad status bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,GPIO pad status bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,GPIO pad status bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,GPIO pad status bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,GPIO pad status bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,GPIO pad status bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,GPIO pad status bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,GPIO pad status bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,GPIO pad status bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,GPIO pad status bit 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,GPIO pad status bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,GPIO pad status bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,GPIO pad status bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,GPIO pad status bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,GPIO pad status bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,GPIO pad status bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,GPIO pad status bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,GPIO pad status bit 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,GPIO pad status bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,GPIO pad status bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,GPIO pad status bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,GPIO pad status bit 0" "Low,High" group.long 0x0C++0x13 line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1" bitfld.long 0x00 30.--31. " ICR[15] ,Controls the active condition of the interrupt function for GPIO interrupt 15" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 28.--29. " [14] ,Controls the active condition of the interrupt function for GPIO interrupt 14" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 26.--27. " [13] ,Controls the active condition of the interrupt function for GPIO interrupt 13" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 24.--25. " [12] ,Controls the active condition of the interrupt function for GPIO interrupt 12" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 22.--23. " [11] ,Controls the active condition of the interrupt function for GPIO interrupt 11" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 20.--21. " [10] ,Controls the active condition of the interrupt function for GPIO interrupt 10" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 18.--19. " [9] ,Controls the active condition of the interrupt function for GPIO interrupt 9" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 16.--17. " [8] ,Controls the active condition of the interrupt function for GPIO interrupt 8" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 14.--15. " [7] ,Controls the active condition of the interrupt function for GPIO interrupt 7" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 12.--13. " [6] ,Controls the active condition of the interrupt function for GPIO interrupt 6" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 10.--11. " [5] ,Controls the active condition of the interrupt function for GPIO interrupt 5" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 8.--9. " [4] ,Controls the active condition of the interrupt function for GPIO interrupt 4" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 6.--7. " [3] ,Controls the active condition of the interrupt function for GPIO interrupt 3" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 4.--5. " [2] ,Controls the active condition of the interrupt function for GPIO interrupt 2" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 2.--3. " [1] ,Controls the active condition of the interrupt function for GPIO interrupt 1" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 0.--1. " [0] ,Controls the active condition of the interrupt function for GPIO interrupt 0" "Low-level,High-level,Rising-edge,Falling-edge" line.long 0x04 "ICR2,GPIO Interrupt Configuration Register 2" bitfld.long 0x04 30.--31. " [31] ,Controls the active condition of the interrupt function for GPIO interrupt 31" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 28.--29. " [30] ,Controls the active condition of the interrupt function for GPIO interrupt 30" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 26.--27. " [29] ,Controls the active condition of the interrupt function for GPIO interrupt 29" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 24.--25. " [28] ,Controls the active condition of the interrupt function for GPIO interrupt 28" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 22.--23. " [27] ,Controls the active condition of the interrupt function for GPIO interrupt 27" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 20.--21. " [26] ,Controls the active condition of the interrupt function for GPIO interrupt 26" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 18.--19. " [25] ,Controls the active condition of the interrupt function for GPIO interrupt 25" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 16.--17. " [24] ,Controls the active condition of the interrupt function for GPIO interrupt 24" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 14.--15. " [23] ,Controls the active condition of the interrupt function for GPIO interrupt 23" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 12.--13. " [22] ,Controls the active condition of the interrupt function for GPIO interrupt 22" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 10.--11. " [21] ,Controls the active condition of the interrupt function for GPIO interrupt 21" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 8.--9. " [20] ,Controls the active condition of the interrupt function for GPIO interrupt 20" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 6.--7. " [19] ,Controls the active condition of the interrupt function for GPIO interrupt 19" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 4.--5. " [18] ,Controls the active condition of the interrupt function for GPIO interrupt 18" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 2.--3. " [17] ,Controls the active condition of the interrupt function for GPIO interrupt 17" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 0.--1. " [16] ,Controls the active condition of the interrupt function for GPIO interrupt 16" "Low-level,High-level,Rising-edge,Falling-edge" line.long 0x08 "IMR,GPIO Interrupt Mask Register" bitfld.long 0x08 31. " IMR[31] ,Interrupt 31 mask bit" "Disabled,Enabled" bitfld.long 0x08 30. " [30] ,Interrupt 30 mask bit" "Disabled,Enabled" bitfld.long 0x08 29. " [29] ,Interrupt 29 mask bit" "Disabled,Enabled" bitfld.long 0x08 28. " [28] ,Interrupt 28 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 27. " [27] ,Interrupt 27 mask bit" "Disabled,Enabled" bitfld.long 0x08 26. " [26] ,Interrupt 26 mask bit" "Disabled,Enabled" bitfld.long 0x08 25. " [25] ,Interrupt 25 mask bit" "Disabled,Enabled" bitfld.long 0x08 24. " [24] ,Interrupt 24 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 23. " [23] ,Interrupt 23 mask bit" "Disabled,Enabled" bitfld.long 0x08 22. " [22] ,Interrupt 22 mask bit" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Interrupt 21 mask bit" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Interrupt 20 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 19. " [19] ,Interrupt 19 mask bit" "Disabled,Enabled" bitfld.long 0x08 18. " [18] ,Interrupt 18 mask bit" "Disabled,Enabled" bitfld.long 0x08 17. " [17] ,Interrupt 17 mask bit" "Disabled,Enabled" bitfld.long 0x08 16. " [16] ,Interrupt 16 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 15. " [15] ,Interrupt 15 mask bit" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Interrupt 14 mask bit" "Disabled,Enabled" bitfld.long 0x08 13. " [13] ,Interrupt 13 mask bit" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Interrupt 12 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 11. " [11] ,Interrupt 11 mask bit" "Disabled,Enabled" bitfld.long 0x08 10. " [10] ,Interrupt 10 mask bit" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Interrupt 9 mask bit" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Interrupt 8 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Interrupt 7 mask bit" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Interrupt 6 mask bit" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Interrupt 5 mask bit" "Disabled,Enabled" bitfld.long 0x08 4. " [4] ,Interrupt 4 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 3. " [3] ,Interrupt 3 mask bit" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Interrupt 2 mask bit" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Interrupt 1 mask bit" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Interrupt 0 mask bit" "Disabled,Enabled" line.long 0x0C "ISR,GPIO Interrupt Status Register" eventfld.long 0x0C 31. " ISR[31] ,Interrupt 31 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 30. " [30] ,Interrupt 30 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 29. " [29] ,Interrupt 29 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 28. " [28] ,Interrupt 28 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 27. " [27] ,Interrupt 27 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 26. " [26] ,Interrupt 26 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 25. " [25] ,Interrupt 25 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 24. " [24] ,Interrupt 24 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 23. " [23] ,Interrupt 23 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 22. " [22] ,Interrupt 22 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 21. " [21] ,Interrupt 21 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 20. " [20] ,Interrupt 20 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 19. " [19] ,Interrupt 19 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 18. " [18] ,Interrupt 18 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 17. " [17] ,Interrupt 17 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 16. " [16] ,Interrupt 16 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 15. " [15] ,Interrupt 15 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 14. " [14] ,Interrupt 14 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 13. " [13] ,Interrupt 13 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 12. " [12] ,Interrupt 12 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 11. " [11] ,Interrupt 11 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 10. " [10] ,Interrupt 10 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 9. " [9] ,Interrupt 9 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 8. " [8] ,Interrupt 8 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 7. " [7] ,Interrupt 7 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 6. " [6] ,Interrupt 6 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 5. " [5] ,Interrupt 5 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 4. " [4] ,Interrupt 4 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 3. " [3] ,Interrupt 3 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 2. " [2] ,Interrupt 2 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 1. " [1] ,Interrupt 1 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 0. " [0] ,Interrupt 0 status bit" "No interrupt,Interrupt" line.long 0x10 "EDGE_SEL,GPIO Edge Select Register" bitfld.long 0x10 31. " GPIO_EDGE_SEL[31] ,Edge select bit 31" "31 setting,Any edge" bitfld.long 0x10 30. " [30] ,Edge select bit 30" "30 setting,Any edge" bitfld.long 0x10 29. " [29] ,Edge select bit 29" "29 setting,Any edge" bitfld.long 0x10 28. " [28] ,Edge select bit 28" "28 setting,Any edge" newline bitfld.long 0x10 27. " [27] ,Edge select bit 27" "27 setting,Any edge" bitfld.long 0x10 26. " [26] ,Edge select bit 26" "26 setting,Any edge" bitfld.long 0x10 25. " [25] ,Edge select bit 25" "25 setting,Any edge" bitfld.long 0x10 24. " [24] ,Edge select bit 24" "24 setting,Any edge" newline bitfld.long 0x10 23. " [23] ,Edge select bit 23" "23 setting,Any edge" bitfld.long 0x10 22. " [22] ,Edge select bit 22" "22 setting,Any edge" bitfld.long 0x10 21. " [21] ,Edge select bit 21" "21 setting,Any edge" bitfld.long 0x10 20. " [20] ,Edge select bit 20" "20 setting,Any edge" newline bitfld.long 0x10 19. " [19] ,Edge select bit 19" "19 setting,Any edge" bitfld.long 0x10 18. " [18] ,Edge select bit 18" "18 setting,Any edge" bitfld.long 0x10 17. " [17] ,Edge select bit 17" "17 setting,Any edge" bitfld.long 0x10 16. " [16] ,Edge select bit 16" "16 setting,Any edge" newline bitfld.long 0x10 15. " [15] ,Edge select bit 15" "15 setting,Any edge" bitfld.long 0x10 14. " [14] ,Edge select bit 14" "14 setting,Any edge" bitfld.long 0x10 13. " [13] ,Edge select bit 13" "13 setting,Any edge" bitfld.long 0x10 12. " [12] ,Edge select bit 12" "12 setting,Any edge" newline bitfld.long 0x10 11. " [11] ,Edge select bit 11" "11 setting,Any edge" bitfld.long 0x10 10. " [10] ,Edge select bit 10" "10 setting,Any edge" bitfld.long 0x10 9. " [9] ,Edge select bit 9" "9 setting,Any edge" bitfld.long 0x10 8. " [8] ,Edge select bit 8" "8 setting,Any edge" newline bitfld.long 0x10 7. " [7] ,Edge select bit 7" "7 setting,Any edge" bitfld.long 0x10 6. " [6] ,Edge select bit 6" "6 setting,Any edge" bitfld.long 0x10 5. " [5] ,Edge select bit 5" "5 setting,Any edge" bitfld.long 0x10 4. " [4] ,Edge select bit 4" "4 setting,Any edge" newline bitfld.long 0x10 3. " [3] ,Edge select bit 3" "3 setting,Any edge" bitfld.long 0x10 2. " [2] ,Edge select bit 2" "2 setting,Any edge" bitfld.long 0x10 1. " [1] ,Edge select bit 1" "1 setting,Any edge" bitfld.long 0x10 0. " [0] ,Edge select bit 0" "0 setting,Any edge" wgroup.long 0x84++0x0B line.long 0x00 "DR_SET,GPIO Data Register SET Register" bitfld.long 0x00 31. " DR_SET[31] ,Data bit 31 set" "Not set,Set" bitfld.long 0x00 30. " [30] ,Data bit 30 set" "Not set,Set" bitfld.long 0x00 29. " [29] ,Data bit 29 set" "Not set,Set" bitfld.long 0x00 28. " [28] ,Data bit 28 set" "Not set,Set" newline bitfld.long 0x00 27. " [27] ,Data bit 27 set" "Not set,Set" bitfld.long 0x00 26. " [26] ,Data bit 26 set" "Not set,Set" bitfld.long 0x00 25. " [25] ,Data bit 25 set" "Not set,Set" bitfld.long 0x00 24. " [24] ,Data bit 24 set" "Not set,Set" newline bitfld.long 0x00 23. " [23] ,Data bit 23 set" "Not set,Set" bitfld.long 0x00 22. " [22] ,Data bit 22 set" "Not set,Set" bitfld.long 0x00 21. " [21] ,Data bit 21 set" "Not set,Set" bitfld.long 0x00 20. " [20] ,Data bit 20 set" "Not set,Set" newline bitfld.long 0x00 19. " [19] ,Data bit 19 set" "Not set,Set" bitfld.long 0x00 18. " [18] ,Data bit 18 set" "Not set,Set" bitfld.long 0x00 17. " [17] ,Data bit 17 set" "Not set,Set" bitfld.long 0x00 16. " [16] ,Data bit 16 set" "Not set,Set" newline bitfld.long 0x00 15. " [15] ,Data bit 15 set" "Not set,Set" bitfld.long 0x00 14. " [14] ,Data bit 14 set" "Not set,Set" bitfld.long 0x00 13. " [13] ,Data bit 13 set" "Not set,Set" bitfld.long 0x00 12. " [12] ,Data bit 12 set" "Not set,Set" newline bitfld.long 0x00 11. " [11] ,Data bit 11 set" "Not set,Set" bitfld.long 0x00 10. " [10] ,Data bit 10 set" "Not set,Set" bitfld.long 0x00 9. " [9] ,Data bit 9 set" "Not set,Set" bitfld.long 0x00 8. " [8] ,Data bit 8 set" "Not set,Set" newline bitfld.long 0x00 7. " [7] ,Data bit 7 set" "Not set,Set" bitfld.long 0x00 6. " [6] ,Data bit 6 set" "Not set,Set" bitfld.long 0x00 5. " [5] ,Data bit 5 set" "Not set,Set" bitfld.long 0x00 4. " [4] ,Data bit 4 set" "Not set,Set" newline bitfld.long 0x00 3. " [3] ,Data bit 3 set" "Not set,Set" bitfld.long 0x00 2. " [2] ,Data bit 2 set" "Not set,Set" bitfld.long 0x00 1. " [1] ,Data bit 1 set" "Not set,Set" bitfld.long 0x00 0. " [0] ,Data bit 0 set" "Not set,Set" line.long 0x04 "DR_CLEAR,GPIO Data Register CLEAR Register" bitfld.long 0x04 31. " DR_CLEAR[31] ,Data bit 31 clear" "No effect,Clear" bitfld.long 0x04 30. " [30] ,Data bit 30 clear" "No effect,Clear" bitfld.long 0x04 29. " [29] ,Data bit 29 clear" "No effect,Clear" bitfld.long 0x04 28. " [28] ,Data bit 28 clear" "No effect,Clear" newline bitfld.long 0x04 27. " [27] ,Data bit 27 clear" "No effect,Clear" bitfld.long 0x04 26. " [26] ,Data bit 26 clear" "No effect,Clear" bitfld.long 0x04 25. " [25] ,Data bit 25 clear" "No effect,Clear" bitfld.long 0x04 24. " [24] ,Data bit 24 clear" "No effect,Clear" newline bitfld.long 0x04 23. " [23] ,Data bit 23 clear" "No effect,Clear" bitfld.long 0x04 22. " [22] ,Data bit 22 clear" "No effect,Clear" bitfld.long 0x04 21. " [21] ,Data bit 21 clear" "No effect,Clear" bitfld.long 0x04 20. " [20] ,Data bit 20 clear" "No effect,Clear" newline bitfld.long 0x04 19. " [19] ,Data bit 19 clear" "No effect,Clear" bitfld.long 0x04 18. " [18] ,Data bit 18 clear" "No effect,Clear" bitfld.long 0x04 17. " [17] ,Data bit 17 clear" "No effect,Clear" bitfld.long 0x04 16. " [16] ,Data bit 16 clear" "No effect,Clear" newline bitfld.long 0x04 15. " [15] ,Data bit 15 clear" "No effect,Clear" bitfld.long 0x04 14. " [14] ,Data bit 14 clear" "No effect,Clear" bitfld.long 0x04 13. " [13] ,Data bit 13 clear" "No effect,Clear" bitfld.long 0x04 12. " [12] ,Data bit 12 clear" "No effect,Clear" newline bitfld.long 0x04 11. " [11] ,Data bit 11 clear" "No effect,Clear" bitfld.long 0x04 10. " [10] ,Data bit 10 clear" "No effect,Clear" bitfld.long 0x04 9. " [9] ,Data bit 9 clear" "No effect,Clear" bitfld.long 0x04 8. " [8] ,Data bit 8 clear" "No effect,Clear" newline bitfld.long 0x04 7. " [7] ,Data bit 7 clear" "No effect,Clear" bitfld.long 0x04 6. " [6] ,Data bit 6 clear" "No effect,Clear" bitfld.long 0x04 5. " [5] ,Data bit 5 clear" "No effect,Clear" bitfld.long 0x04 4. " [4] ,Data bit 4 clear" "No effect,Clear" newline bitfld.long 0x04 3. " [3] ,Data bit 3 clear" "No effect,Clear" bitfld.long 0x04 2. " [2] ,Data bit 2 clear" "No effect,Clear" bitfld.long 0x04 1. " [1] ,Data bit 1 clear" "No effect,Clear" bitfld.long 0x04 0. " [0] ,Data bit 0 clear" "No effect,Clear" line.long 0x08 "DR_TOGGLE,GPIO Data Register TOGGLE Register" bitfld.long 0x08 31. " DR_TOGGLE[31] ,Data bit 31 toggle" "Not toggled,Toggled" bitfld.long 0x08 30. " [30] ,Data bit 30 toggle" "No effect,Clear" bitfld.long 0x08 29. " [29] ,Data bit 29 toggle" "Not toggled,Toggled" bitfld.long 0x08 28. " [28] ,Data bit 28 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 27. " [27] ,Data bit 27 toggle" "Not toggled,Toggled" bitfld.long 0x08 26. " [26] ,Data bit 26 toggle" "Not toggled,Toggled" bitfld.long 0x08 25. " [25] ,Data bit 25 toggle" "Not toggled,Toggled" bitfld.long 0x08 24. " [24] ,Data bit 24 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 23. " [23] ,Data bit 23 toggle" "Not toggled,Toggled" bitfld.long 0x08 22. " [22] ,Data bit 22 toggle" "Not toggled,Toggled" bitfld.long 0x08 21. " [21] ,Data bit 21 toggle" "Not toggled,Toggled" bitfld.long 0x08 20. " [20] ,Data bit 20 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 19. " [19] ,Data bit 19 toggle" "Not toggled,Toggled" bitfld.long 0x08 18. " [18] ,Data bit 18 toggle" "Not toggled,Toggled" bitfld.long 0x08 17. " [17] ,Data bit 17 toggle" "Not toggled,Toggled" bitfld.long 0x08 16. " [16] ,Data bit 16 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 15. " [15] ,Data bit 15 toggle" "Not toggled,Toggled" bitfld.long 0x08 14. " [14] ,Data bit 14 toggle" "Not toggled,Toggled" bitfld.long 0x08 13. " [13] ,Data bit 13 toggle" "Not toggled,Toggled" bitfld.long 0x08 12. " [12] ,Data bit 12 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 11. " [11] ,Data bit 11 toggle" "Not toggled,Toggled" bitfld.long 0x08 10. " [10] ,Data bit 10 toggle" "Not toggled,Toggled" bitfld.long 0x08 9. " [9] ,Data bit 9 toggle" "Not toggled,Toggled" bitfld.long 0x08 8. " [8] ,Data bit 8 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 7. " [7] ,Data bit 7 toggle" "Not toggled,Toggled" bitfld.long 0x08 6. " [6] ,Data bit 6 toggle" "Not toggled,Toggled" bitfld.long 0x08 5. " [5] ,Data bit 5 toggle" "Not toggled,Toggled" bitfld.long 0x08 4. " [4] ,Data bit 4 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 3. " [3] ,Data bit 3 toggle" "Not toggled,Toggled" bitfld.long 0x08 2. " [2] ,Data bit 2 toggle" "Not toggled,Toggled" bitfld.long 0x08 1. " [1] ,Data bit 1 toggle" "Not toggled,Toggled" bitfld.long 0x08 0. " [0] ,Data bit 0 toggle" "Not toggled,Toggled" width 0x0B tree.end tree "GPIO1" base ad:0x5D090000 width 11. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data Register" bitfld.long 0x00 31. " DR[31] ,Data bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,Data bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,Data bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,Data bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,Data bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,Data bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,Data bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,Data bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,Data bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,Data bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,Data bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,Data bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,Data bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,Data bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,Data bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,Data bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,Data bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,Data bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,Data bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,Data bit 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,Data bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,Data bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,Data bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,Data bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,Data bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,Data bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,Data bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,Data bit 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,Data bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,Data bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,Data bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,Data bit 0" "Low,High" line.long 0x04 "GDIR,GPIO Direction Register" bitfld.long 0x04 31. " GDIR[31] ,GPIO direction 31 bit" "Input,Output" bitfld.long 0x04 30. " [30] ,GPIO direction 30 bit" "Input,Output" bitfld.long 0x04 29. " [29] ,GPIO direction 29 bit" "Input,Output" bitfld.long 0x04 28. " [28] ,GPIO direction 28 bit" "Input,Output" newline bitfld.long 0x04 27. " [27] ,GPIO direction 27 bit" "Input,Output" bitfld.long 0x04 26. " [26] ,GPIO direction 26 bit" "Input,Output" bitfld.long 0x04 25. " [25] ,GPIO direction 25 bit" "Input,Output" bitfld.long 0x04 24. " [24] ,GPIO direction 24 bit" "Input,Output" newline bitfld.long 0x04 23. " [23] ,GPIO direction 23 bit" "Input,Output" bitfld.long 0x04 22. " [22] ,GPIO direction 22 bit" "Input,Output" bitfld.long 0x04 21. " [21] ,GPIO direction 21 bit" "Input,Output" bitfld.long 0x04 20. " [20] ,GPIO direction 20 bit" "Input,Output" newline bitfld.long 0x04 19. " [19] ,GPIO direction 19 bit" "Input,Output" bitfld.long 0x04 18. " [18] ,GPIO direction 18 bit" "Input,Output" bitfld.long 0x04 17. " [17] ,GPIO direction 17 bit" "Input,Output" bitfld.long 0x04 16. " [16] ,GPIO direction 16 bit" "Input,Output" newline bitfld.long 0x04 15. " [15] ,GPIO direction 15 bit" "Input,Output" bitfld.long 0x04 14. " [14] ,GPIO direction 14 bit" "Input,Output" bitfld.long 0x04 13. " [13] ,GPIO direction 13 bit" "Input,Output" bitfld.long 0x04 12. " [12] ,GPIO direction 12 bit" "Input,Output" newline bitfld.long 0x04 11. " [11] ,GPIO direction 11 bit" "Input,Output" bitfld.long 0x04 10. " [10] ,GPIO direction 10 bit" "Input,Output" bitfld.long 0x04 9. " [9] ,GPIO direction 9 bit" "Input,Output" bitfld.long 0x04 8. " [8] ,GPIO direction 8 bit" "Input,Output" newline bitfld.long 0x04 7. " [7] ,GPIO direction 7 bit" "Input,Output" bitfld.long 0x04 6. " [6] ,GPIO direction 6 bit" "Input,Output" bitfld.long 0x04 5. " [5] ,GPIO direction 5 bit" "Input,Output" bitfld.long 0x04 4. " [4] ,GPIO direction 4 bit" "Input,Output" newline bitfld.long 0x04 3. " [3] ,GPIO direction 3 bit" "Input,Output" bitfld.long 0x04 2. " [2] ,GPIO direction 2 bit" "Input,Output" bitfld.long 0x04 1. " [1] ,GPIO direction 1 bit" "Input,Output" bitfld.long 0x04 0. " [0] ,GPIO direction 0 bit" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO Pad Status Register" bitfld.long 0x00 31. " PSR[31] ,GPIO pad status bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,GPIO pad status bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,GPIO pad status bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,GPIO pad status bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,GPIO pad status bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,GPIO pad status bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,GPIO pad status bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,GPIO pad status bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,GPIO pad status bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,GPIO pad status bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,GPIO pad status bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,GPIO pad status bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,GPIO pad status bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,GPIO pad status bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,GPIO pad status bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,GPIO pad status bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,GPIO pad status bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,GPIO pad status bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,GPIO pad status bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,GPIO pad status bit 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,GPIO pad status bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,GPIO pad status bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,GPIO pad status bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,GPIO pad status bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,GPIO pad status bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,GPIO pad status bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,GPIO pad status bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,GPIO pad status bit 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,GPIO pad status bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,GPIO pad status bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,GPIO pad status bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,GPIO pad status bit 0" "Low,High" group.long 0x0C++0x13 line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1" bitfld.long 0x00 30.--31. " ICR[15] ,Controls the active condition of the interrupt function for GPIO interrupt 15" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 28.--29. " [14] ,Controls the active condition of the interrupt function for GPIO interrupt 14" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 26.--27. " [13] ,Controls the active condition of the interrupt function for GPIO interrupt 13" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 24.--25. " [12] ,Controls the active condition of the interrupt function for GPIO interrupt 12" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 22.--23. " [11] ,Controls the active condition of the interrupt function for GPIO interrupt 11" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 20.--21. " [10] ,Controls the active condition of the interrupt function for GPIO interrupt 10" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 18.--19. " [9] ,Controls the active condition of the interrupt function for GPIO interrupt 9" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 16.--17. " [8] ,Controls the active condition of the interrupt function for GPIO interrupt 8" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 14.--15. " [7] ,Controls the active condition of the interrupt function for GPIO interrupt 7" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 12.--13. " [6] ,Controls the active condition of the interrupt function for GPIO interrupt 6" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 10.--11. " [5] ,Controls the active condition of the interrupt function for GPIO interrupt 5" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 8.--9. " [4] ,Controls the active condition of the interrupt function for GPIO interrupt 4" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 6.--7. " [3] ,Controls the active condition of the interrupt function for GPIO interrupt 3" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 4.--5. " [2] ,Controls the active condition of the interrupt function for GPIO interrupt 2" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 2.--3. " [1] ,Controls the active condition of the interrupt function for GPIO interrupt 1" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 0.--1. " [0] ,Controls the active condition of the interrupt function for GPIO interrupt 0" "Low-level,High-level,Rising-edge,Falling-edge" line.long 0x04 "ICR2,GPIO Interrupt Configuration Register 2" bitfld.long 0x04 30.--31. " [31] ,Controls the active condition of the interrupt function for GPIO interrupt 31" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 28.--29. " [30] ,Controls the active condition of the interrupt function for GPIO interrupt 30" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 26.--27. " [29] ,Controls the active condition of the interrupt function for GPIO interrupt 29" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 24.--25. " [28] ,Controls the active condition of the interrupt function for GPIO interrupt 28" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 22.--23. " [27] ,Controls the active condition of the interrupt function for GPIO interrupt 27" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 20.--21. " [26] ,Controls the active condition of the interrupt function for GPIO interrupt 26" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 18.--19. " [25] ,Controls the active condition of the interrupt function for GPIO interrupt 25" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 16.--17. " [24] ,Controls the active condition of the interrupt function for GPIO interrupt 24" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 14.--15. " [23] ,Controls the active condition of the interrupt function for GPIO interrupt 23" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 12.--13. " [22] ,Controls the active condition of the interrupt function for GPIO interrupt 22" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 10.--11. " [21] ,Controls the active condition of the interrupt function for GPIO interrupt 21" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 8.--9. " [20] ,Controls the active condition of the interrupt function for GPIO interrupt 20" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 6.--7. " [19] ,Controls the active condition of the interrupt function for GPIO interrupt 19" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 4.--5. " [18] ,Controls the active condition of the interrupt function for GPIO interrupt 18" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 2.--3. " [17] ,Controls the active condition of the interrupt function for GPIO interrupt 17" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 0.--1. " [16] ,Controls the active condition of the interrupt function for GPIO interrupt 16" "Low-level,High-level,Rising-edge,Falling-edge" line.long 0x08 "IMR,GPIO Interrupt Mask Register" bitfld.long 0x08 31. " IMR[31] ,Interrupt 31 mask bit" "Disabled,Enabled" bitfld.long 0x08 30. " [30] ,Interrupt 30 mask bit" "Disabled,Enabled" bitfld.long 0x08 29. " [29] ,Interrupt 29 mask bit" "Disabled,Enabled" bitfld.long 0x08 28. " [28] ,Interrupt 28 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 27. " [27] ,Interrupt 27 mask bit" "Disabled,Enabled" bitfld.long 0x08 26. " [26] ,Interrupt 26 mask bit" "Disabled,Enabled" bitfld.long 0x08 25. " [25] ,Interrupt 25 mask bit" "Disabled,Enabled" bitfld.long 0x08 24. " [24] ,Interrupt 24 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 23. " [23] ,Interrupt 23 mask bit" "Disabled,Enabled" bitfld.long 0x08 22. " [22] ,Interrupt 22 mask bit" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Interrupt 21 mask bit" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Interrupt 20 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 19. " [19] ,Interrupt 19 mask bit" "Disabled,Enabled" bitfld.long 0x08 18. " [18] ,Interrupt 18 mask bit" "Disabled,Enabled" bitfld.long 0x08 17. " [17] ,Interrupt 17 mask bit" "Disabled,Enabled" bitfld.long 0x08 16. " [16] ,Interrupt 16 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 15. " [15] ,Interrupt 15 mask bit" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Interrupt 14 mask bit" "Disabled,Enabled" bitfld.long 0x08 13. " [13] ,Interrupt 13 mask bit" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Interrupt 12 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 11. " [11] ,Interrupt 11 mask bit" "Disabled,Enabled" bitfld.long 0x08 10. " [10] ,Interrupt 10 mask bit" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Interrupt 9 mask bit" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Interrupt 8 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Interrupt 7 mask bit" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Interrupt 6 mask bit" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Interrupt 5 mask bit" "Disabled,Enabled" bitfld.long 0x08 4. " [4] ,Interrupt 4 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 3. " [3] ,Interrupt 3 mask bit" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Interrupt 2 mask bit" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Interrupt 1 mask bit" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Interrupt 0 mask bit" "Disabled,Enabled" line.long 0x0C "ISR,GPIO Interrupt Status Register" eventfld.long 0x0C 31. " ISR[31] ,Interrupt 31 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 30. " [30] ,Interrupt 30 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 29. " [29] ,Interrupt 29 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 28. " [28] ,Interrupt 28 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 27. " [27] ,Interrupt 27 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 26. " [26] ,Interrupt 26 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 25. " [25] ,Interrupt 25 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 24. " [24] ,Interrupt 24 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 23. " [23] ,Interrupt 23 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 22. " [22] ,Interrupt 22 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 21. " [21] ,Interrupt 21 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 20. " [20] ,Interrupt 20 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 19. " [19] ,Interrupt 19 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 18. " [18] ,Interrupt 18 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 17. " [17] ,Interrupt 17 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 16. " [16] ,Interrupt 16 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 15. " [15] ,Interrupt 15 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 14. " [14] ,Interrupt 14 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 13. " [13] ,Interrupt 13 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 12. " [12] ,Interrupt 12 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 11. " [11] ,Interrupt 11 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 10. " [10] ,Interrupt 10 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 9. " [9] ,Interrupt 9 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 8. " [8] ,Interrupt 8 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 7. " [7] ,Interrupt 7 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 6. " [6] ,Interrupt 6 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 5. " [5] ,Interrupt 5 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 4. " [4] ,Interrupt 4 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 3. " [3] ,Interrupt 3 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 2. " [2] ,Interrupt 2 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 1. " [1] ,Interrupt 1 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 0. " [0] ,Interrupt 0 status bit" "No interrupt,Interrupt" line.long 0x10 "EDGE_SEL,GPIO Edge Select Register" bitfld.long 0x10 31. " GPIO_EDGE_SEL[31] ,Edge select bit 31" "31 setting,Any edge" bitfld.long 0x10 30. " [30] ,Edge select bit 30" "30 setting,Any edge" bitfld.long 0x10 29. " [29] ,Edge select bit 29" "29 setting,Any edge" bitfld.long 0x10 28. " [28] ,Edge select bit 28" "28 setting,Any edge" newline bitfld.long 0x10 27. " [27] ,Edge select bit 27" "27 setting,Any edge" bitfld.long 0x10 26. " [26] ,Edge select bit 26" "26 setting,Any edge" bitfld.long 0x10 25. " [25] ,Edge select bit 25" "25 setting,Any edge" bitfld.long 0x10 24. " [24] ,Edge select bit 24" "24 setting,Any edge" newline bitfld.long 0x10 23. " [23] ,Edge select bit 23" "23 setting,Any edge" bitfld.long 0x10 22. " [22] ,Edge select bit 22" "22 setting,Any edge" bitfld.long 0x10 21. " [21] ,Edge select bit 21" "21 setting,Any edge" bitfld.long 0x10 20. " [20] ,Edge select bit 20" "20 setting,Any edge" newline bitfld.long 0x10 19. " [19] ,Edge select bit 19" "19 setting,Any edge" bitfld.long 0x10 18. " [18] ,Edge select bit 18" "18 setting,Any edge" bitfld.long 0x10 17. " [17] ,Edge select bit 17" "17 setting,Any edge" bitfld.long 0x10 16. " [16] ,Edge select bit 16" "16 setting,Any edge" newline bitfld.long 0x10 15. " [15] ,Edge select bit 15" "15 setting,Any edge" bitfld.long 0x10 14. " [14] ,Edge select bit 14" "14 setting,Any edge" bitfld.long 0x10 13. " [13] ,Edge select bit 13" "13 setting,Any edge" bitfld.long 0x10 12. " [12] ,Edge select bit 12" "12 setting,Any edge" newline bitfld.long 0x10 11. " [11] ,Edge select bit 11" "11 setting,Any edge" bitfld.long 0x10 10. " [10] ,Edge select bit 10" "10 setting,Any edge" bitfld.long 0x10 9. " [9] ,Edge select bit 9" "9 setting,Any edge" bitfld.long 0x10 8. " [8] ,Edge select bit 8" "8 setting,Any edge" newline bitfld.long 0x10 7. " [7] ,Edge select bit 7" "7 setting,Any edge" bitfld.long 0x10 6. " [6] ,Edge select bit 6" "6 setting,Any edge" bitfld.long 0x10 5. " [5] ,Edge select bit 5" "5 setting,Any edge" bitfld.long 0x10 4. " [4] ,Edge select bit 4" "4 setting,Any edge" newline bitfld.long 0x10 3. " [3] ,Edge select bit 3" "3 setting,Any edge" bitfld.long 0x10 2. " [2] ,Edge select bit 2" "2 setting,Any edge" bitfld.long 0x10 1. " [1] ,Edge select bit 1" "1 setting,Any edge" bitfld.long 0x10 0. " [0] ,Edge select bit 0" "0 setting,Any edge" wgroup.long 0x84++0x0B line.long 0x00 "DR_SET,GPIO Data Register SET Register" bitfld.long 0x00 31. " DR_SET[31] ,Data bit 31 set" "Not set,Set" bitfld.long 0x00 30. " [30] ,Data bit 30 set" "Not set,Set" bitfld.long 0x00 29. " [29] ,Data bit 29 set" "Not set,Set" bitfld.long 0x00 28. " [28] ,Data bit 28 set" "Not set,Set" newline bitfld.long 0x00 27. " [27] ,Data bit 27 set" "Not set,Set" bitfld.long 0x00 26. " [26] ,Data bit 26 set" "Not set,Set" bitfld.long 0x00 25. " [25] ,Data bit 25 set" "Not set,Set" bitfld.long 0x00 24. " [24] ,Data bit 24 set" "Not set,Set" newline bitfld.long 0x00 23. " [23] ,Data bit 23 set" "Not set,Set" bitfld.long 0x00 22. " [22] ,Data bit 22 set" "Not set,Set" bitfld.long 0x00 21. " [21] ,Data bit 21 set" "Not set,Set" bitfld.long 0x00 20. " [20] ,Data bit 20 set" "Not set,Set" newline bitfld.long 0x00 19. " [19] ,Data bit 19 set" "Not set,Set" bitfld.long 0x00 18. " [18] ,Data bit 18 set" "Not set,Set" bitfld.long 0x00 17. " [17] ,Data bit 17 set" "Not set,Set" bitfld.long 0x00 16. " [16] ,Data bit 16 set" "Not set,Set" newline bitfld.long 0x00 15. " [15] ,Data bit 15 set" "Not set,Set" bitfld.long 0x00 14. " [14] ,Data bit 14 set" "Not set,Set" bitfld.long 0x00 13. " [13] ,Data bit 13 set" "Not set,Set" bitfld.long 0x00 12. " [12] ,Data bit 12 set" "Not set,Set" newline bitfld.long 0x00 11. " [11] ,Data bit 11 set" "Not set,Set" bitfld.long 0x00 10. " [10] ,Data bit 10 set" "Not set,Set" bitfld.long 0x00 9. " [9] ,Data bit 9 set" "Not set,Set" bitfld.long 0x00 8. " [8] ,Data bit 8 set" "Not set,Set" newline bitfld.long 0x00 7. " [7] ,Data bit 7 set" "Not set,Set" bitfld.long 0x00 6. " [6] ,Data bit 6 set" "Not set,Set" bitfld.long 0x00 5. " [5] ,Data bit 5 set" "Not set,Set" bitfld.long 0x00 4. " [4] ,Data bit 4 set" "Not set,Set" newline bitfld.long 0x00 3. " [3] ,Data bit 3 set" "Not set,Set" bitfld.long 0x00 2. " [2] ,Data bit 2 set" "Not set,Set" bitfld.long 0x00 1. " [1] ,Data bit 1 set" "Not set,Set" bitfld.long 0x00 0. " [0] ,Data bit 0 set" "Not set,Set" line.long 0x04 "DR_CLEAR,GPIO Data Register CLEAR Register" bitfld.long 0x04 31. " DR_CLEAR[31] ,Data bit 31 clear" "No effect,Clear" bitfld.long 0x04 30. " [30] ,Data bit 30 clear" "No effect,Clear" bitfld.long 0x04 29. " [29] ,Data bit 29 clear" "No effect,Clear" bitfld.long 0x04 28. " [28] ,Data bit 28 clear" "No effect,Clear" newline bitfld.long 0x04 27. " [27] ,Data bit 27 clear" "No effect,Clear" bitfld.long 0x04 26. " [26] ,Data bit 26 clear" "No effect,Clear" bitfld.long 0x04 25. " [25] ,Data bit 25 clear" "No effect,Clear" bitfld.long 0x04 24. " [24] ,Data bit 24 clear" "No effect,Clear" newline bitfld.long 0x04 23. " [23] ,Data bit 23 clear" "No effect,Clear" bitfld.long 0x04 22. " [22] ,Data bit 22 clear" "No effect,Clear" bitfld.long 0x04 21. " [21] ,Data bit 21 clear" "No effect,Clear" bitfld.long 0x04 20. " [20] ,Data bit 20 clear" "No effect,Clear" newline bitfld.long 0x04 19. " [19] ,Data bit 19 clear" "No effect,Clear" bitfld.long 0x04 18. " [18] ,Data bit 18 clear" "No effect,Clear" bitfld.long 0x04 17. " [17] ,Data bit 17 clear" "No effect,Clear" bitfld.long 0x04 16. " [16] ,Data bit 16 clear" "No effect,Clear" newline bitfld.long 0x04 15. " [15] ,Data bit 15 clear" "No effect,Clear" bitfld.long 0x04 14. " [14] ,Data bit 14 clear" "No effect,Clear" bitfld.long 0x04 13. " [13] ,Data bit 13 clear" "No effect,Clear" bitfld.long 0x04 12. " [12] ,Data bit 12 clear" "No effect,Clear" newline bitfld.long 0x04 11. " [11] ,Data bit 11 clear" "No effect,Clear" bitfld.long 0x04 10. " [10] ,Data bit 10 clear" "No effect,Clear" bitfld.long 0x04 9. " [9] ,Data bit 9 clear" "No effect,Clear" bitfld.long 0x04 8. " [8] ,Data bit 8 clear" "No effect,Clear" newline bitfld.long 0x04 7. " [7] ,Data bit 7 clear" "No effect,Clear" bitfld.long 0x04 6. " [6] ,Data bit 6 clear" "No effect,Clear" bitfld.long 0x04 5. " [5] ,Data bit 5 clear" "No effect,Clear" bitfld.long 0x04 4. " [4] ,Data bit 4 clear" "No effect,Clear" newline bitfld.long 0x04 3. " [3] ,Data bit 3 clear" "No effect,Clear" bitfld.long 0x04 2. " [2] ,Data bit 2 clear" "No effect,Clear" bitfld.long 0x04 1. " [1] ,Data bit 1 clear" "No effect,Clear" bitfld.long 0x04 0. " [0] ,Data bit 0 clear" "No effect,Clear" line.long 0x08 "DR_TOGGLE,GPIO Data Register TOGGLE Register" bitfld.long 0x08 31. " DR_TOGGLE[31] ,Data bit 31 toggle" "Not toggled,Toggled" bitfld.long 0x08 30. " [30] ,Data bit 30 toggle" "No effect,Clear" bitfld.long 0x08 29. " [29] ,Data bit 29 toggle" "Not toggled,Toggled" bitfld.long 0x08 28. " [28] ,Data bit 28 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 27. " [27] ,Data bit 27 toggle" "Not toggled,Toggled" bitfld.long 0x08 26. " [26] ,Data bit 26 toggle" "Not toggled,Toggled" bitfld.long 0x08 25. " [25] ,Data bit 25 toggle" "Not toggled,Toggled" bitfld.long 0x08 24. " [24] ,Data bit 24 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 23. " [23] ,Data bit 23 toggle" "Not toggled,Toggled" bitfld.long 0x08 22. " [22] ,Data bit 22 toggle" "Not toggled,Toggled" bitfld.long 0x08 21. " [21] ,Data bit 21 toggle" "Not toggled,Toggled" bitfld.long 0x08 20. " [20] ,Data bit 20 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 19. " [19] ,Data bit 19 toggle" "Not toggled,Toggled" bitfld.long 0x08 18. " [18] ,Data bit 18 toggle" "Not toggled,Toggled" bitfld.long 0x08 17. " [17] ,Data bit 17 toggle" "Not toggled,Toggled" bitfld.long 0x08 16. " [16] ,Data bit 16 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 15. " [15] ,Data bit 15 toggle" "Not toggled,Toggled" bitfld.long 0x08 14. " [14] ,Data bit 14 toggle" "Not toggled,Toggled" bitfld.long 0x08 13. " [13] ,Data bit 13 toggle" "Not toggled,Toggled" bitfld.long 0x08 12. " [12] ,Data bit 12 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 11. " [11] ,Data bit 11 toggle" "Not toggled,Toggled" bitfld.long 0x08 10. " [10] ,Data bit 10 toggle" "Not toggled,Toggled" bitfld.long 0x08 9. " [9] ,Data bit 9 toggle" "Not toggled,Toggled" bitfld.long 0x08 8. " [8] ,Data bit 8 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 7. " [7] ,Data bit 7 toggle" "Not toggled,Toggled" bitfld.long 0x08 6. " [6] ,Data bit 6 toggle" "Not toggled,Toggled" bitfld.long 0x08 5. " [5] ,Data bit 5 toggle" "Not toggled,Toggled" bitfld.long 0x08 4. " [4] ,Data bit 4 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 3. " [3] ,Data bit 3 toggle" "Not toggled,Toggled" bitfld.long 0x08 2. " [2] ,Data bit 2 toggle" "Not toggled,Toggled" bitfld.long 0x08 1. " [1] ,Data bit 1 toggle" "Not toggled,Toggled" bitfld.long 0x08 0. " [0] ,Data bit 0 toggle" "Not toggled,Toggled" width 0x0B tree.end tree "GPIO2" base ad:0x5D0A0000 width 11. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data Register" bitfld.long 0x00 31. " DR[31] ,Data bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,Data bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,Data bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,Data bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,Data bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,Data bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,Data bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,Data bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,Data bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,Data bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,Data bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,Data bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,Data bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,Data bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,Data bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,Data bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,Data bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,Data bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,Data bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,Data bit 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,Data bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,Data bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,Data bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,Data bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,Data bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,Data bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,Data bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,Data bit 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,Data bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,Data bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,Data bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,Data bit 0" "Low,High" line.long 0x04 "GDIR,GPIO Direction Register" bitfld.long 0x04 31. " GDIR[31] ,GPIO direction 31 bit" "Input,Output" bitfld.long 0x04 30. " [30] ,GPIO direction 30 bit" "Input,Output" bitfld.long 0x04 29. " [29] ,GPIO direction 29 bit" "Input,Output" bitfld.long 0x04 28. " [28] ,GPIO direction 28 bit" "Input,Output" newline bitfld.long 0x04 27. " [27] ,GPIO direction 27 bit" "Input,Output" bitfld.long 0x04 26. " [26] ,GPIO direction 26 bit" "Input,Output" bitfld.long 0x04 25. " [25] ,GPIO direction 25 bit" "Input,Output" bitfld.long 0x04 24. " [24] ,GPIO direction 24 bit" "Input,Output" newline bitfld.long 0x04 23. " [23] ,GPIO direction 23 bit" "Input,Output" bitfld.long 0x04 22. " [22] ,GPIO direction 22 bit" "Input,Output" bitfld.long 0x04 21. " [21] ,GPIO direction 21 bit" "Input,Output" bitfld.long 0x04 20. " [20] ,GPIO direction 20 bit" "Input,Output" newline bitfld.long 0x04 19. " [19] ,GPIO direction 19 bit" "Input,Output" bitfld.long 0x04 18. " [18] ,GPIO direction 18 bit" "Input,Output" bitfld.long 0x04 17. " [17] ,GPIO direction 17 bit" "Input,Output" bitfld.long 0x04 16. " [16] ,GPIO direction 16 bit" "Input,Output" newline bitfld.long 0x04 15. " [15] ,GPIO direction 15 bit" "Input,Output" bitfld.long 0x04 14. " [14] ,GPIO direction 14 bit" "Input,Output" bitfld.long 0x04 13. " [13] ,GPIO direction 13 bit" "Input,Output" bitfld.long 0x04 12. " [12] ,GPIO direction 12 bit" "Input,Output" newline bitfld.long 0x04 11. " [11] ,GPIO direction 11 bit" "Input,Output" bitfld.long 0x04 10. " [10] ,GPIO direction 10 bit" "Input,Output" bitfld.long 0x04 9. " [9] ,GPIO direction 9 bit" "Input,Output" bitfld.long 0x04 8. " [8] ,GPIO direction 8 bit" "Input,Output" newline bitfld.long 0x04 7. " [7] ,GPIO direction 7 bit" "Input,Output" bitfld.long 0x04 6. " [6] ,GPIO direction 6 bit" "Input,Output" bitfld.long 0x04 5. " [5] ,GPIO direction 5 bit" "Input,Output" bitfld.long 0x04 4. " [4] ,GPIO direction 4 bit" "Input,Output" newline bitfld.long 0x04 3. " [3] ,GPIO direction 3 bit" "Input,Output" bitfld.long 0x04 2. " [2] ,GPIO direction 2 bit" "Input,Output" bitfld.long 0x04 1. " [1] ,GPIO direction 1 bit" "Input,Output" bitfld.long 0x04 0. " [0] ,GPIO direction 0 bit" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO Pad Status Register" bitfld.long 0x00 31. " PSR[31] ,GPIO pad status bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,GPIO pad status bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,GPIO pad status bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,GPIO pad status bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,GPIO pad status bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,GPIO pad status bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,GPIO pad status bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,GPIO pad status bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,GPIO pad status bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,GPIO pad status bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,GPIO pad status bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,GPIO pad status bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,GPIO pad status bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,GPIO pad status bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,GPIO pad status bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,GPIO pad status bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,GPIO pad status bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,GPIO pad status bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,GPIO pad status bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,GPIO pad status bit 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,GPIO pad status bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,GPIO pad status bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,GPIO pad status bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,GPIO pad status bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,GPIO pad status bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,GPIO pad status bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,GPIO pad status bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,GPIO pad status bit 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,GPIO pad status bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,GPIO pad status bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,GPIO pad status bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,GPIO pad status bit 0" "Low,High" group.long 0x0C++0x13 line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1" bitfld.long 0x00 30.--31. " ICR[15] ,Controls the active condition of the interrupt function for GPIO interrupt 15" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 28.--29. " [14] ,Controls the active condition of the interrupt function for GPIO interrupt 14" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 26.--27. " [13] ,Controls the active condition of the interrupt function for GPIO interrupt 13" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 24.--25. " [12] ,Controls the active condition of the interrupt function for GPIO interrupt 12" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 22.--23. " [11] ,Controls the active condition of the interrupt function for GPIO interrupt 11" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 20.--21. " [10] ,Controls the active condition of the interrupt function for GPIO interrupt 10" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 18.--19. " [9] ,Controls the active condition of the interrupt function for GPIO interrupt 9" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 16.--17. " [8] ,Controls the active condition of the interrupt function for GPIO interrupt 8" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 14.--15. " [7] ,Controls the active condition of the interrupt function for GPIO interrupt 7" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 12.--13. " [6] ,Controls the active condition of the interrupt function for GPIO interrupt 6" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 10.--11. " [5] ,Controls the active condition of the interrupt function for GPIO interrupt 5" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 8.--9. " [4] ,Controls the active condition of the interrupt function for GPIO interrupt 4" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 6.--7. " [3] ,Controls the active condition of the interrupt function for GPIO interrupt 3" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 4.--5. " [2] ,Controls the active condition of the interrupt function for GPIO interrupt 2" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 2.--3. " [1] ,Controls the active condition of the interrupt function for GPIO interrupt 1" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 0.--1. " [0] ,Controls the active condition of the interrupt function for GPIO interrupt 0" "Low-level,High-level,Rising-edge,Falling-edge" line.long 0x04 "ICR2,GPIO Interrupt Configuration Register 2" bitfld.long 0x04 30.--31. " [31] ,Controls the active condition of the interrupt function for GPIO interrupt 31" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 28.--29. " [30] ,Controls the active condition of the interrupt function for GPIO interrupt 30" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 26.--27. " [29] ,Controls the active condition of the interrupt function for GPIO interrupt 29" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 24.--25. " [28] ,Controls the active condition of the interrupt function for GPIO interrupt 28" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 22.--23. " [27] ,Controls the active condition of the interrupt function for GPIO interrupt 27" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 20.--21. " [26] ,Controls the active condition of the interrupt function for GPIO interrupt 26" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 18.--19. " [25] ,Controls the active condition of the interrupt function for GPIO interrupt 25" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 16.--17. " [24] ,Controls the active condition of the interrupt function for GPIO interrupt 24" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 14.--15. " [23] ,Controls the active condition of the interrupt function for GPIO interrupt 23" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 12.--13. " [22] ,Controls the active condition of the interrupt function for GPIO interrupt 22" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 10.--11. " [21] ,Controls the active condition of the interrupt function for GPIO interrupt 21" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 8.--9. " [20] ,Controls the active condition of the interrupt function for GPIO interrupt 20" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 6.--7. " [19] ,Controls the active condition of the interrupt function for GPIO interrupt 19" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 4.--5. " [18] ,Controls the active condition of the interrupt function for GPIO interrupt 18" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 2.--3. " [17] ,Controls the active condition of the interrupt function for GPIO interrupt 17" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 0.--1. " [16] ,Controls the active condition of the interrupt function for GPIO interrupt 16" "Low-level,High-level,Rising-edge,Falling-edge" line.long 0x08 "IMR,GPIO Interrupt Mask Register" bitfld.long 0x08 31. " IMR[31] ,Interrupt 31 mask bit" "Disabled,Enabled" bitfld.long 0x08 30. " [30] ,Interrupt 30 mask bit" "Disabled,Enabled" bitfld.long 0x08 29. " [29] ,Interrupt 29 mask bit" "Disabled,Enabled" bitfld.long 0x08 28. " [28] ,Interrupt 28 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 27. " [27] ,Interrupt 27 mask bit" "Disabled,Enabled" bitfld.long 0x08 26. " [26] ,Interrupt 26 mask bit" "Disabled,Enabled" bitfld.long 0x08 25. " [25] ,Interrupt 25 mask bit" "Disabled,Enabled" bitfld.long 0x08 24. " [24] ,Interrupt 24 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 23. " [23] ,Interrupt 23 mask bit" "Disabled,Enabled" bitfld.long 0x08 22. " [22] ,Interrupt 22 mask bit" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Interrupt 21 mask bit" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Interrupt 20 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 19. " [19] ,Interrupt 19 mask bit" "Disabled,Enabled" bitfld.long 0x08 18. " [18] ,Interrupt 18 mask bit" "Disabled,Enabled" bitfld.long 0x08 17. " [17] ,Interrupt 17 mask bit" "Disabled,Enabled" bitfld.long 0x08 16. " [16] ,Interrupt 16 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 15. " [15] ,Interrupt 15 mask bit" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Interrupt 14 mask bit" "Disabled,Enabled" bitfld.long 0x08 13. " [13] ,Interrupt 13 mask bit" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Interrupt 12 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 11. " [11] ,Interrupt 11 mask bit" "Disabled,Enabled" bitfld.long 0x08 10. " [10] ,Interrupt 10 mask bit" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Interrupt 9 mask bit" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Interrupt 8 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Interrupt 7 mask bit" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Interrupt 6 mask bit" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Interrupt 5 mask bit" "Disabled,Enabled" bitfld.long 0x08 4. " [4] ,Interrupt 4 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 3. " [3] ,Interrupt 3 mask bit" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Interrupt 2 mask bit" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Interrupt 1 mask bit" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Interrupt 0 mask bit" "Disabled,Enabled" line.long 0x0C "ISR,GPIO Interrupt Status Register" eventfld.long 0x0C 31. " ISR[31] ,Interrupt 31 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 30. " [30] ,Interrupt 30 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 29. " [29] ,Interrupt 29 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 28. " [28] ,Interrupt 28 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 27. " [27] ,Interrupt 27 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 26. " [26] ,Interrupt 26 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 25. " [25] ,Interrupt 25 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 24. " [24] ,Interrupt 24 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 23. " [23] ,Interrupt 23 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 22. " [22] ,Interrupt 22 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 21. " [21] ,Interrupt 21 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 20. " [20] ,Interrupt 20 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 19. " [19] ,Interrupt 19 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 18. " [18] ,Interrupt 18 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 17. " [17] ,Interrupt 17 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 16. " [16] ,Interrupt 16 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 15. " [15] ,Interrupt 15 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 14. " [14] ,Interrupt 14 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 13. " [13] ,Interrupt 13 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 12. " [12] ,Interrupt 12 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 11. " [11] ,Interrupt 11 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 10. " [10] ,Interrupt 10 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 9. " [9] ,Interrupt 9 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 8. " [8] ,Interrupt 8 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 7. " [7] ,Interrupt 7 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 6. " [6] ,Interrupt 6 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 5. " [5] ,Interrupt 5 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 4. " [4] ,Interrupt 4 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 3. " [3] ,Interrupt 3 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 2. " [2] ,Interrupt 2 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 1. " [1] ,Interrupt 1 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 0. " [0] ,Interrupt 0 status bit" "No interrupt,Interrupt" line.long 0x10 "EDGE_SEL,GPIO Edge Select Register" bitfld.long 0x10 31. " GPIO_EDGE_SEL[31] ,Edge select bit 31" "31 setting,Any edge" bitfld.long 0x10 30. " [30] ,Edge select bit 30" "30 setting,Any edge" bitfld.long 0x10 29. " [29] ,Edge select bit 29" "29 setting,Any edge" bitfld.long 0x10 28. " [28] ,Edge select bit 28" "28 setting,Any edge" newline bitfld.long 0x10 27. " [27] ,Edge select bit 27" "27 setting,Any edge" bitfld.long 0x10 26. " [26] ,Edge select bit 26" "26 setting,Any edge" bitfld.long 0x10 25. " [25] ,Edge select bit 25" "25 setting,Any edge" bitfld.long 0x10 24. " [24] ,Edge select bit 24" "24 setting,Any edge" newline bitfld.long 0x10 23. " [23] ,Edge select bit 23" "23 setting,Any edge" bitfld.long 0x10 22. " [22] ,Edge select bit 22" "22 setting,Any edge" bitfld.long 0x10 21. " [21] ,Edge select bit 21" "21 setting,Any edge" bitfld.long 0x10 20. " [20] ,Edge select bit 20" "20 setting,Any edge" newline bitfld.long 0x10 19. " [19] ,Edge select bit 19" "19 setting,Any edge" bitfld.long 0x10 18. " [18] ,Edge select bit 18" "18 setting,Any edge" bitfld.long 0x10 17. " [17] ,Edge select bit 17" "17 setting,Any edge" bitfld.long 0x10 16. " [16] ,Edge select bit 16" "16 setting,Any edge" newline bitfld.long 0x10 15. " [15] ,Edge select bit 15" "15 setting,Any edge" bitfld.long 0x10 14. " [14] ,Edge select bit 14" "14 setting,Any edge" bitfld.long 0x10 13. " [13] ,Edge select bit 13" "13 setting,Any edge" bitfld.long 0x10 12. " [12] ,Edge select bit 12" "12 setting,Any edge" newline bitfld.long 0x10 11. " [11] ,Edge select bit 11" "11 setting,Any edge" bitfld.long 0x10 10. " [10] ,Edge select bit 10" "10 setting,Any edge" bitfld.long 0x10 9. " [9] ,Edge select bit 9" "9 setting,Any edge" bitfld.long 0x10 8. " [8] ,Edge select bit 8" "8 setting,Any edge" newline bitfld.long 0x10 7. " [7] ,Edge select bit 7" "7 setting,Any edge" bitfld.long 0x10 6. " [6] ,Edge select bit 6" "6 setting,Any edge" bitfld.long 0x10 5. " [5] ,Edge select bit 5" "5 setting,Any edge" bitfld.long 0x10 4. " [4] ,Edge select bit 4" "4 setting,Any edge" newline bitfld.long 0x10 3. " [3] ,Edge select bit 3" "3 setting,Any edge" bitfld.long 0x10 2. " [2] ,Edge select bit 2" "2 setting,Any edge" bitfld.long 0x10 1. " [1] ,Edge select bit 1" "1 setting,Any edge" bitfld.long 0x10 0. " [0] ,Edge select bit 0" "0 setting,Any edge" wgroup.long 0x84++0x0B line.long 0x00 "DR_SET,GPIO Data Register SET Register" bitfld.long 0x00 31. " DR_SET[31] ,Data bit 31 set" "Not set,Set" bitfld.long 0x00 30. " [30] ,Data bit 30 set" "Not set,Set" bitfld.long 0x00 29. " [29] ,Data bit 29 set" "Not set,Set" bitfld.long 0x00 28. " [28] ,Data bit 28 set" "Not set,Set" newline bitfld.long 0x00 27. " [27] ,Data bit 27 set" "Not set,Set" bitfld.long 0x00 26. " [26] ,Data bit 26 set" "Not set,Set" bitfld.long 0x00 25. " [25] ,Data bit 25 set" "Not set,Set" bitfld.long 0x00 24. " [24] ,Data bit 24 set" "Not set,Set" newline bitfld.long 0x00 23. " [23] ,Data bit 23 set" "Not set,Set" bitfld.long 0x00 22. " [22] ,Data bit 22 set" "Not set,Set" bitfld.long 0x00 21. " [21] ,Data bit 21 set" "Not set,Set" bitfld.long 0x00 20. " [20] ,Data bit 20 set" "Not set,Set" newline bitfld.long 0x00 19. " [19] ,Data bit 19 set" "Not set,Set" bitfld.long 0x00 18. " [18] ,Data bit 18 set" "Not set,Set" bitfld.long 0x00 17. " [17] ,Data bit 17 set" "Not set,Set" bitfld.long 0x00 16. " [16] ,Data bit 16 set" "Not set,Set" newline bitfld.long 0x00 15. " [15] ,Data bit 15 set" "Not set,Set" bitfld.long 0x00 14. " [14] ,Data bit 14 set" "Not set,Set" bitfld.long 0x00 13. " [13] ,Data bit 13 set" "Not set,Set" bitfld.long 0x00 12. " [12] ,Data bit 12 set" "Not set,Set" newline bitfld.long 0x00 11. " [11] ,Data bit 11 set" "Not set,Set" bitfld.long 0x00 10. " [10] ,Data bit 10 set" "Not set,Set" bitfld.long 0x00 9. " [9] ,Data bit 9 set" "Not set,Set" bitfld.long 0x00 8. " [8] ,Data bit 8 set" "Not set,Set" newline bitfld.long 0x00 7. " [7] ,Data bit 7 set" "Not set,Set" bitfld.long 0x00 6. " [6] ,Data bit 6 set" "Not set,Set" bitfld.long 0x00 5. " [5] ,Data bit 5 set" "Not set,Set" bitfld.long 0x00 4. " [4] ,Data bit 4 set" "Not set,Set" newline bitfld.long 0x00 3. " [3] ,Data bit 3 set" "Not set,Set" bitfld.long 0x00 2. " [2] ,Data bit 2 set" "Not set,Set" bitfld.long 0x00 1. " [1] ,Data bit 1 set" "Not set,Set" bitfld.long 0x00 0. " [0] ,Data bit 0 set" "Not set,Set" line.long 0x04 "DR_CLEAR,GPIO Data Register CLEAR Register" bitfld.long 0x04 31. " DR_CLEAR[31] ,Data bit 31 clear" "No effect,Clear" bitfld.long 0x04 30. " [30] ,Data bit 30 clear" "No effect,Clear" bitfld.long 0x04 29. " [29] ,Data bit 29 clear" "No effect,Clear" bitfld.long 0x04 28. " [28] ,Data bit 28 clear" "No effect,Clear" newline bitfld.long 0x04 27. " [27] ,Data bit 27 clear" "No effect,Clear" bitfld.long 0x04 26. " [26] ,Data bit 26 clear" "No effect,Clear" bitfld.long 0x04 25. " [25] ,Data bit 25 clear" "No effect,Clear" bitfld.long 0x04 24. " [24] ,Data bit 24 clear" "No effect,Clear" newline bitfld.long 0x04 23. " [23] ,Data bit 23 clear" "No effect,Clear" bitfld.long 0x04 22. " [22] ,Data bit 22 clear" "No effect,Clear" bitfld.long 0x04 21. " [21] ,Data bit 21 clear" "No effect,Clear" bitfld.long 0x04 20. " [20] ,Data bit 20 clear" "No effect,Clear" newline bitfld.long 0x04 19. " [19] ,Data bit 19 clear" "No effect,Clear" bitfld.long 0x04 18. " [18] ,Data bit 18 clear" "No effect,Clear" bitfld.long 0x04 17. " [17] ,Data bit 17 clear" "No effect,Clear" bitfld.long 0x04 16. " [16] ,Data bit 16 clear" "No effect,Clear" newline bitfld.long 0x04 15. " [15] ,Data bit 15 clear" "No effect,Clear" bitfld.long 0x04 14. " [14] ,Data bit 14 clear" "No effect,Clear" bitfld.long 0x04 13. " [13] ,Data bit 13 clear" "No effect,Clear" bitfld.long 0x04 12. " [12] ,Data bit 12 clear" "No effect,Clear" newline bitfld.long 0x04 11. " [11] ,Data bit 11 clear" "No effect,Clear" bitfld.long 0x04 10. " [10] ,Data bit 10 clear" "No effect,Clear" bitfld.long 0x04 9. " [9] ,Data bit 9 clear" "No effect,Clear" bitfld.long 0x04 8. " [8] ,Data bit 8 clear" "No effect,Clear" newline bitfld.long 0x04 7. " [7] ,Data bit 7 clear" "No effect,Clear" bitfld.long 0x04 6. " [6] ,Data bit 6 clear" "No effect,Clear" bitfld.long 0x04 5. " [5] ,Data bit 5 clear" "No effect,Clear" bitfld.long 0x04 4. " [4] ,Data bit 4 clear" "No effect,Clear" newline bitfld.long 0x04 3. " [3] ,Data bit 3 clear" "No effect,Clear" bitfld.long 0x04 2. " [2] ,Data bit 2 clear" "No effect,Clear" bitfld.long 0x04 1. " [1] ,Data bit 1 clear" "No effect,Clear" bitfld.long 0x04 0. " [0] ,Data bit 0 clear" "No effect,Clear" line.long 0x08 "DR_TOGGLE,GPIO Data Register TOGGLE Register" bitfld.long 0x08 31. " DR_TOGGLE[31] ,Data bit 31 toggle" "Not toggled,Toggled" bitfld.long 0x08 30. " [30] ,Data bit 30 toggle" "No effect,Clear" bitfld.long 0x08 29. " [29] ,Data bit 29 toggle" "Not toggled,Toggled" bitfld.long 0x08 28. " [28] ,Data bit 28 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 27. " [27] ,Data bit 27 toggle" "Not toggled,Toggled" bitfld.long 0x08 26. " [26] ,Data bit 26 toggle" "Not toggled,Toggled" bitfld.long 0x08 25. " [25] ,Data bit 25 toggle" "Not toggled,Toggled" bitfld.long 0x08 24. " [24] ,Data bit 24 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 23. " [23] ,Data bit 23 toggle" "Not toggled,Toggled" bitfld.long 0x08 22. " [22] ,Data bit 22 toggle" "Not toggled,Toggled" bitfld.long 0x08 21. " [21] ,Data bit 21 toggle" "Not toggled,Toggled" bitfld.long 0x08 20. " [20] ,Data bit 20 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 19. " [19] ,Data bit 19 toggle" "Not toggled,Toggled" bitfld.long 0x08 18. " [18] ,Data bit 18 toggle" "Not toggled,Toggled" bitfld.long 0x08 17. " [17] ,Data bit 17 toggle" "Not toggled,Toggled" bitfld.long 0x08 16. " [16] ,Data bit 16 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 15. " [15] ,Data bit 15 toggle" "Not toggled,Toggled" bitfld.long 0x08 14. " [14] ,Data bit 14 toggle" "Not toggled,Toggled" bitfld.long 0x08 13. " [13] ,Data bit 13 toggle" "Not toggled,Toggled" bitfld.long 0x08 12. " [12] ,Data bit 12 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 11. " [11] ,Data bit 11 toggle" "Not toggled,Toggled" bitfld.long 0x08 10. " [10] ,Data bit 10 toggle" "Not toggled,Toggled" bitfld.long 0x08 9. " [9] ,Data bit 9 toggle" "Not toggled,Toggled" bitfld.long 0x08 8. " [8] ,Data bit 8 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 7. " [7] ,Data bit 7 toggle" "Not toggled,Toggled" bitfld.long 0x08 6. " [6] ,Data bit 6 toggle" "Not toggled,Toggled" bitfld.long 0x08 5. " [5] ,Data bit 5 toggle" "Not toggled,Toggled" bitfld.long 0x08 4. " [4] ,Data bit 4 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 3. " [3] ,Data bit 3 toggle" "Not toggled,Toggled" bitfld.long 0x08 2. " [2] ,Data bit 2 toggle" "Not toggled,Toggled" bitfld.long 0x08 1. " [1] ,Data bit 1 toggle" "Not toggled,Toggled" bitfld.long 0x08 0. " [0] ,Data bit 0 toggle" "Not toggled,Toggled" width 0x0B tree.end tree "GPIO3" base ad:0x5D0B0000 width 11. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data Register" bitfld.long 0x00 31. " DR[31] ,Data bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,Data bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,Data bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,Data bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,Data bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,Data bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,Data bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,Data bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,Data bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,Data bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,Data bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,Data bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,Data bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,Data bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,Data bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,Data bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,Data bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,Data bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,Data bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,Data bit 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,Data bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,Data bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,Data bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,Data bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,Data bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,Data bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,Data bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,Data bit 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,Data bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,Data bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,Data bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,Data bit 0" "Low,High" line.long 0x04 "GDIR,GPIO Direction Register" bitfld.long 0x04 31. " GDIR[31] ,GPIO direction 31 bit" "Input,Output" bitfld.long 0x04 30. " [30] ,GPIO direction 30 bit" "Input,Output" bitfld.long 0x04 29. " [29] ,GPIO direction 29 bit" "Input,Output" bitfld.long 0x04 28. " [28] ,GPIO direction 28 bit" "Input,Output" newline bitfld.long 0x04 27. " [27] ,GPIO direction 27 bit" "Input,Output" bitfld.long 0x04 26. " [26] ,GPIO direction 26 bit" "Input,Output" bitfld.long 0x04 25. " [25] ,GPIO direction 25 bit" "Input,Output" bitfld.long 0x04 24. " [24] ,GPIO direction 24 bit" "Input,Output" newline bitfld.long 0x04 23. " [23] ,GPIO direction 23 bit" "Input,Output" bitfld.long 0x04 22. " [22] ,GPIO direction 22 bit" "Input,Output" bitfld.long 0x04 21. " [21] ,GPIO direction 21 bit" "Input,Output" bitfld.long 0x04 20. " [20] ,GPIO direction 20 bit" "Input,Output" newline bitfld.long 0x04 19. " [19] ,GPIO direction 19 bit" "Input,Output" bitfld.long 0x04 18. " [18] ,GPIO direction 18 bit" "Input,Output" bitfld.long 0x04 17. " [17] ,GPIO direction 17 bit" "Input,Output" bitfld.long 0x04 16. " [16] ,GPIO direction 16 bit" "Input,Output" newline bitfld.long 0x04 15. " [15] ,GPIO direction 15 bit" "Input,Output" bitfld.long 0x04 14. " [14] ,GPIO direction 14 bit" "Input,Output" bitfld.long 0x04 13. " [13] ,GPIO direction 13 bit" "Input,Output" bitfld.long 0x04 12. " [12] ,GPIO direction 12 bit" "Input,Output" newline bitfld.long 0x04 11. " [11] ,GPIO direction 11 bit" "Input,Output" bitfld.long 0x04 10. " [10] ,GPIO direction 10 bit" "Input,Output" bitfld.long 0x04 9. " [9] ,GPIO direction 9 bit" "Input,Output" bitfld.long 0x04 8. " [8] ,GPIO direction 8 bit" "Input,Output" newline bitfld.long 0x04 7. " [7] ,GPIO direction 7 bit" "Input,Output" bitfld.long 0x04 6. " [6] ,GPIO direction 6 bit" "Input,Output" bitfld.long 0x04 5. " [5] ,GPIO direction 5 bit" "Input,Output" bitfld.long 0x04 4. " [4] ,GPIO direction 4 bit" "Input,Output" newline bitfld.long 0x04 3. " [3] ,GPIO direction 3 bit" "Input,Output" bitfld.long 0x04 2. " [2] ,GPIO direction 2 bit" "Input,Output" bitfld.long 0x04 1. " [1] ,GPIO direction 1 bit" "Input,Output" bitfld.long 0x04 0. " [0] ,GPIO direction 0 bit" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO Pad Status Register" bitfld.long 0x00 31. " PSR[31] ,GPIO pad status bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,GPIO pad status bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,GPIO pad status bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,GPIO pad status bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,GPIO pad status bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,GPIO pad status bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,GPIO pad status bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,GPIO pad status bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,GPIO pad status bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,GPIO pad status bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,GPIO pad status bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,GPIO pad status bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,GPIO pad status bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,GPIO pad status bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,GPIO pad status bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,GPIO pad status bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,GPIO pad status bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,GPIO pad status bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,GPIO pad status bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,GPIO pad status bit 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,GPIO pad status bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,GPIO pad status bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,GPIO pad status bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,GPIO pad status bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,GPIO pad status bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,GPIO pad status bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,GPIO pad status bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,GPIO pad status bit 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,GPIO pad status bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,GPIO pad status bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,GPIO pad status bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,GPIO pad status bit 0" "Low,High" group.long 0x0C++0x13 line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1" bitfld.long 0x00 30.--31. " ICR[15] ,Controls the active condition of the interrupt function for GPIO interrupt 15" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 28.--29. " [14] ,Controls the active condition of the interrupt function for GPIO interrupt 14" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 26.--27. " [13] ,Controls the active condition of the interrupt function for GPIO interrupt 13" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 24.--25. " [12] ,Controls the active condition of the interrupt function for GPIO interrupt 12" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 22.--23. " [11] ,Controls the active condition of the interrupt function for GPIO interrupt 11" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 20.--21. " [10] ,Controls the active condition of the interrupt function for GPIO interrupt 10" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 18.--19. " [9] ,Controls the active condition of the interrupt function for GPIO interrupt 9" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 16.--17. " [8] ,Controls the active condition of the interrupt function for GPIO interrupt 8" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 14.--15. " [7] ,Controls the active condition of the interrupt function for GPIO interrupt 7" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 12.--13. " [6] ,Controls the active condition of the interrupt function for GPIO interrupt 6" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 10.--11. " [5] ,Controls the active condition of the interrupt function for GPIO interrupt 5" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 8.--9. " [4] ,Controls the active condition of the interrupt function for GPIO interrupt 4" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 6.--7. " [3] ,Controls the active condition of the interrupt function for GPIO interrupt 3" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 4.--5. " [2] ,Controls the active condition of the interrupt function for GPIO interrupt 2" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 2.--3. " [1] ,Controls the active condition of the interrupt function for GPIO interrupt 1" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 0.--1. " [0] ,Controls the active condition of the interrupt function for GPIO interrupt 0" "Low-level,High-level,Rising-edge,Falling-edge" line.long 0x04 "ICR2,GPIO Interrupt Configuration Register 2" bitfld.long 0x04 30.--31. " [31] ,Controls the active condition of the interrupt function for GPIO interrupt 31" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 28.--29. " [30] ,Controls the active condition of the interrupt function for GPIO interrupt 30" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 26.--27. " [29] ,Controls the active condition of the interrupt function for GPIO interrupt 29" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 24.--25. " [28] ,Controls the active condition of the interrupt function for GPIO interrupt 28" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 22.--23. " [27] ,Controls the active condition of the interrupt function for GPIO interrupt 27" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 20.--21. " [26] ,Controls the active condition of the interrupt function for GPIO interrupt 26" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 18.--19. " [25] ,Controls the active condition of the interrupt function for GPIO interrupt 25" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 16.--17. " [24] ,Controls the active condition of the interrupt function for GPIO interrupt 24" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 14.--15. " [23] ,Controls the active condition of the interrupt function for GPIO interrupt 23" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 12.--13. " [22] ,Controls the active condition of the interrupt function for GPIO interrupt 22" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 10.--11. " [21] ,Controls the active condition of the interrupt function for GPIO interrupt 21" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 8.--9. " [20] ,Controls the active condition of the interrupt function for GPIO interrupt 20" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 6.--7. " [19] ,Controls the active condition of the interrupt function for GPIO interrupt 19" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 4.--5. " [18] ,Controls the active condition of the interrupt function for GPIO interrupt 18" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 2.--3. " [17] ,Controls the active condition of the interrupt function for GPIO interrupt 17" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 0.--1. " [16] ,Controls the active condition of the interrupt function for GPIO interrupt 16" "Low-level,High-level,Rising-edge,Falling-edge" line.long 0x08 "IMR,GPIO Interrupt Mask Register" bitfld.long 0x08 31. " IMR[31] ,Interrupt 31 mask bit" "Disabled,Enabled" bitfld.long 0x08 30. " [30] ,Interrupt 30 mask bit" "Disabled,Enabled" bitfld.long 0x08 29. " [29] ,Interrupt 29 mask bit" "Disabled,Enabled" bitfld.long 0x08 28. " [28] ,Interrupt 28 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 27. " [27] ,Interrupt 27 mask bit" "Disabled,Enabled" bitfld.long 0x08 26. " [26] ,Interrupt 26 mask bit" "Disabled,Enabled" bitfld.long 0x08 25. " [25] ,Interrupt 25 mask bit" "Disabled,Enabled" bitfld.long 0x08 24. " [24] ,Interrupt 24 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 23. " [23] ,Interrupt 23 mask bit" "Disabled,Enabled" bitfld.long 0x08 22. " [22] ,Interrupt 22 mask bit" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Interrupt 21 mask bit" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Interrupt 20 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 19. " [19] ,Interrupt 19 mask bit" "Disabled,Enabled" bitfld.long 0x08 18. " [18] ,Interrupt 18 mask bit" "Disabled,Enabled" bitfld.long 0x08 17. " [17] ,Interrupt 17 mask bit" "Disabled,Enabled" bitfld.long 0x08 16. " [16] ,Interrupt 16 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 15. " [15] ,Interrupt 15 mask bit" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Interrupt 14 mask bit" "Disabled,Enabled" bitfld.long 0x08 13. " [13] ,Interrupt 13 mask bit" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Interrupt 12 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 11. " [11] ,Interrupt 11 mask bit" "Disabled,Enabled" bitfld.long 0x08 10. " [10] ,Interrupt 10 mask bit" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Interrupt 9 mask bit" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Interrupt 8 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Interrupt 7 mask bit" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Interrupt 6 mask bit" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Interrupt 5 mask bit" "Disabled,Enabled" bitfld.long 0x08 4. " [4] ,Interrupt 4 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 3. " [3] ,Interrupt 3 mask bit" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Interrupt 2 mask bit" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Interrupt 1 mask bit" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Interrupt 0 mask bit" "Disabled,Enabled" line.long 0x0C "ISR,GPIO Interrupt Status Register" eventfld.long 0x0C 31. " ISR[31] ,Interrupt 31 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 30. " [30] ,Interrupt 30 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 29. " [29] ,Interrupt 29 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 28. " [28] ,Interrupt 28 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 27. " [27] ,Interrupt 27 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 26. " [26] ,Interrupt 26 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 25. " [25] ,Interrupt 25 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 24. " [24] ,Interrupt 24 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 23. " [23] ,Interrupt 23 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 22. " [22] ,Interrupt 22 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 21. " [21] ,Interrupt 21 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 20. " [20] ,Interrupt 20 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 19. " [19] ,Interrupt 19 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 18. " [18] ,Interrupt 18 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 17. " [17] ,Interrupt 17 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 16. " [16] ,Interrupt 16 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 15. " [15] ,Interrupt 15 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 14. " [14] ,Interrupt 14 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 13. " [13] ,Interrupt 13 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 12. " [12] ,Interrupt 12 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 11. " [11] ,Interrupt 11 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 10. " [10] ,Interrupt 10 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 9. " [9] ,Interrupt 9 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 8. " [8] ,Interrupt 8 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 7. " [7] ,Interrupt 7 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 6. " [6] ,Interrupt 6 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 5. " [5] ,Interrupt 5 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 4. " [4] ,Interrupt 4 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 3. " [3] ,Interrupt 3 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 2. " [2] ,Interrupt 2 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 1. " [1] ,Interrupt 1 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 0. " [0] ,Interrupt 0 status bit" "No interrupt,Interrupt" line.long 0x10 "EDGE_SEL,GPIO Edge Select Register" bitfld.long 0x10 31. " GPIO_EDGE_SEL[31] ,Edge select bit 31" "31 setting,Any edge" bitfld.long 0x10 30. " [30] ,Edge select bit 30" "30 setting,Any edge" bitfld.long 0x10 29. " [29] ,Edge select bit 29" "29 setting,Any edge" bitfld.long 0x10 28. " [28] ,Edge select bit 28" "28 setting,Any edge" newline bitfld.long 0x10 27. " [27] ,Edge select bit 27" "27 setting,Any edge" bitfld.long 0x10 26. " [26] ,Edge select bit 26" "26 setting,Any edge" bitfld.long 0x10 25. " [25] ,Edge select bit 25" "25 setting,Any edge" bitfld.long 0x10 24. " [24] ,Edge select bit 24" "24 setting,Any edge" newline bitfld.long 0x10 23. " [23] ,Edge select bit 23" "23 setting,Any edge" bitfld.long 0x10 22. " [22] ,Edge select bit 22" "22 setting,Any edge" bitfld.long 0x10 21. " [21] ,Edge select bit 21" "21 setting,Any edge" bitfld.long 0x10 20. " [20] ,Edge select bit 20" "20 setting,Any edge" newline bitfld.long 0x10 19. " [19] ,Edge select bit 19" "19 setting,Any edge" bitfld.long 0x10 18. " [18] ,Edge select bit 18" "18 setting,Any edge" bitfld.long 0x10 17. " [17] ,Edge select bit 17" "17 setting,Any edge" bitfld.long 0x10 16. " [16] ,Edge select bit 16" "16 setting,Any edge" newline bitfld.long 0x10 15. " [15] ,Edge select bit 15" "15 setting,Any edge" bitfld.long 0x10 14. " [14] ,Edge select bit 14" "14 setting,Any edge" bitfld.long 0x10 13. " [13] ,Edge select bit 13" "13 setting,Any edge" bitfld.long 0x10 12. " [12] ,Edge select bit 12" "12 setting,Any edge" newline bitfld.long 0x10 11. " [11] ,Edge select bit 11" "11 setting,Any edge" bitfld.long 0x10 10. " [10] ,Edge select bit 10" "10 setting,Any edge" bitfld.long 0x10 9. " [9] ,Edge select bit 9" "9 setting,Any edge" bitfld.long 0x10 8. " [8] ,Edge select bit 8" "8 setting,Any edge" newline bitfld.long 0x10 7. " [7] ,Edge select bit 7" "7 setting,Any edge" bitfld.long 0x10 6. " [6] ,Edge select bit 6" "6 setting,Any edge" bitfld.long 0x10 5. " [5] ,Edge select bit 5" "5 setting,Any edge" bitfld.long 0x10 4. " [4] ,Edge select bit 4" "4 setting,Any edge" newline bitfld.long 0x10 3. " [3] ,Edge select bit 3" "3 setting,Any edge" bitfld.long 0x10 2. " [2] ,Edge select bit 2" "2 setting,Any edge" bitfld.long 0x10 1. " [1] ,Edge select bit 1" "1 setting,Any edge" bitfld.long 0x10 0. " [0] ,Edge select bit 0" "0 setting,Any edge" wgroup.long 0x84++0x0B line.long 0x00 "DR_SET,GPIO Data Register SET Register" bitfld.long 0x00 31. " DR_SET[31] ,Data bit 31 set" "Not set,Set" bitfld.long 0x00 30. " [30] ,Data bit 30 set" "Not set,Set" bitfld.long 0x00 29. " [29] ,Data bit 29 set" "Not set,Set" bitfld.long 0x00 28. " [28] ,Data bit 28 set" "Not set,Set" newline bitfld.long 0x00 27. " [27] ,Data bit 27 set" "Not set,Set" bitfld.long 0x00 26. " [26] ,Data bit 26 set" "Not set,Set" bitfld.long 0x00 25. " [25] ,Data bit 25 set" "Not set,Set" bitfld.long 0x00 24. " [24] ,Data bit 24 set" "Not set,Set" newline bitfld.long 0x00 23. " [23] ,Data bit 23 set" "Not set,Set" bitfld.long 0x00 22. " [22] ,Data bit 22 set" "Not set,Set" bitfld.long 0x00 21. " [21] ,Data bit 21 set" "Not set,Set" bitfld.long 0x00 20. " [20] ,Data bit 20 set" "Not set,Set" newline bitfld.long 0x00 19. " [19] ,Data bit 19 set" "Not set,Set" bitfld.long 0x00 18. " [18] ,Data bit 18 set" "Not set,Set" bitfld.long 0x00 17. " [17] ,Data bit 17 set" "Not set,Set" bitfld.long 0x00 16. " [16] ,Data bit 16 set" "Not set,Set" newline bitfld.long 0x00 15. " [15] ,Data bit 15 set" "Not set,Set" bitfld.long 0x00 14. " [14] ,Data bit 14 set" "Not set,Set" bitfld.long 0x00 13. " [13] ,Data bit 13 set" "Not set,Set" bitfld.long 0x00 12. " [12] ,Data bit 12 set" "Not set,Set" newline bitfld.long 0x00 11. " [11] ,Data bit 11 set" "Not set,Set" bitfld.long 0x00 10. " [10] ,Data bit 10 set" "Not set,Set" bitfld.long 0x00 9. " [9] ,Data bit 9 set" "Not set,Set" bitfld.long 0x00 8. " [8] ,Data bit 8 set" "Not set,Set" newline bitfld.long 0x00 7. " [7] ,Data bit 7 set" "Not set,Set" bitfld.long 0x00 6. " [6] ,Data bit 6 set" "Not set,Set" bitfld.long 0x00 5. " [5] ,Data bit 5 set" "Not set,Set" bitfld.long 0x00 4. " [4] ,Data bit 4 set" "Not set,Set" newline bitfld.long 0x00 3. " [3] ,Data bit 3 set" "Not set,Set" bitfld.long 0x00 2. " [2] ,Data bit 2 set" "Not set,Set" bitfld.long 0x00 1. " [1] ,Data bit 1 set" "Not set,Set" bitfld.long 0x00 0. " [0] ,Data bit 0 set" "Not set,Set" line.long 0x04 "DR_CLEAR,GPIO Data Register CLEAR Register" bitfld.long 0x04 31. " DR_CLEAR[31] ,Data bit 31 clear" "No effect,Clear" bitfld.long 0x04 30. " [30] ,Data bit 30 clear" "No effect,Clear" bitfld.long 0x04 29. " [29] ,Data bit 29 clear" "No effect,Clear" bitfld.long 0x04 28. " [28] ,Data bit 28 clear" "No effect,Clear" newline bitfld.long 0x04 27. " [27] ,Data bit 27 clear" "No effect,Clear" bitfld.long 0x04 26. " [26] ,Data bit 26 clear" "No effect,Clear" bitfld.long 0x04 25. " [25] ,Data bit 25 clear" "No effect,Clear" bitfld.long 0x04 24. " [24] ,Data bit 24 clear" "No effect,Clear" newline bitfld.long 0x04 23. " [23] ,Data bit 23 clear" "No effect,Clear" bitfld.long 0x04 22. " [22] ,Data bit 22 clear" "No effect,Clear" bitfld.long 0x04 21. " [21] ,Data bit 21 clear" "No effect,Clear" bitfld.long 0x04 20. " [20] ,Data bit 20 clear" "No effect,Clear" newline bitfld.long 0x04 19. " [19] ,Data bit 19 clear" "No effect,Clear" bitfld.long 0x04 18. " [18] ,Data bit 18 clear" "No effect,Clear" bitfld.long 0x04 17. " [17] ,Data bit 17 clear" "No effect,Clear" bitfld.long 0x04 16. " [16] ,Data bit 16 clear" "No effect,Clear" newline bitfld.long 0x04 15. " [15] ,Data bit 15 clear" "No effect,Clear" bitfld.long 0x04 14. " [14] ,Data bit 14 clear" "No effect,Clear" bitfld.long 0x04 13. " [13] ,Data bit 13 clear" "No effect,Clear" bitfld.long 0x04 12. " [12] ,Data bit 12 clear" "No effect,Clear" newline bitfld.long 0x04 11. " [11] ,Data bit 11 clear" "No effect,Clear" bitfld.long 0x04 10. " [10] ,Data bit 10 clear" "No effect,Clear" bitfld.long 0x04 9. " [9] ,Data bit 9 clear" "No effect,Clear" bitfld.long 0x04 8. " [8] ,Data bit 8 clear" "No effect,Clear" newline bitfld.long 0x04 7. " [7] ,Data bit 7 clear" "No effect,Clear" bitfld.long 0x04 6. " [6] ,Data bit 6 clear" "No effect,Clear" bitfld.long 0x04 5. " [5] ,Data bit 5 clear" "No effect,Clear" bitfld.long 0x04 4. " [4] ,Data bit 4 clear" "No effect,Clear" newline bitfld.long 0x04 3. " [3] ,Data bit 3 clear" "No effect,Clear" bitfld.long 0x04 2. " [2] ,Data bit 2 clear" "No effect,Clear" bitfld.long 0x04 1. " [1] ,Data bit 1 clear" "No effect,Clear" bitfld.long 0x04 0. " [0] ,Data bit 0 clear" "No effect,Clear" line.long 0x08 "DR_TOGGLE,GPIO Data Register TOGGLE Register" bitfld.long 0x08 31. " DR_TOGGLE[31] ,Data bit 31 toggle" "Not toggled,Toggled" bitfld.long 0x08 30. " [30] ,Data bit 30 toggle" "No effect,Clear" bitfld.long 0x08 29. " [29] ,Data bit 29 toggle" "Not toggled,Toggled" bitfld.long 0x08 28. " [28] ,Data bit 28 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 27. " [27] ,Data bit 27 toggle" "Not toggled,Toggled" bitfld.long 0x08 26. " [26] ,Data bit 26 toggle" "Not toggled,Toggled" bitfld.long 0x08 25. " [25] ,Data bit 25 toggle" "Not toggled,Toggled" bitfld.long 0x08 24. " [24] ,Data bit 24 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 23. " [23] ,Data bit 23 toggle" "Not toggled,Toggled" bitfld.long 0x08 22. " [22] ,Data bit 22 toggle" "Not toggled,Toggled" bitfld.long 0x08 21. " [21] ,Data bit 21 toggle" "Not toggled,Toggled" bitfld.long 0x08 20. " [20] ,Data bit 20 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 19. " [19] ,Data bit 19 toggle" "Not toggled,Toggled" bitfld.long 0x08 18. " [18] ,Data bit 18 toggle" "Not toggled,Toggled" bitfld.long 0x08 17. " [17] ,Data bit 17 toggle" "Not toggled,Toggled" bitfld.long 0x08 16. " [16] ,Data bit 16 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 15. " [15] ,Data bit 15 toggle" "Not toggled,Toggled" bitfld.long 0x08 14. " [14] ,Data bit 14 toggle" "Not toggled,Toggled" bitfld.long 0x08 13. " [13] ,Data bit 13 toggle" "Not toggled,Toggled" bitfld.long 0x08 12. " [12] ,Data bit 12 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 11. " [11] ,Data bit 11 toggle" "Not toggled,Toggled" bitfld.long 0x08 10. " [10] ,Data bit 10 toggle" "Not toggled,Toggled" bitfld.long 0x08 9. " [9] ,Data bit 9 toggle" "Not toggled,Toggled" bitfld.long 0x08 8. " [8] ,Data bit 8 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 7. " [7] ,Data bit 7 toggle" "Not toggled,Toggled" bitfld.long 0x08 6. " [6] ,Data bit 6 toggle" "Not toggled,Toggled" bitfld.long 0x08 5. " [5] ,Data bit 5 toggle" "Not toggled,Toggled" bitfld.long 0x08 4. " [4] ,Data bit 4 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 3. " [3] ,Data bit 3 toggle" "Not toggled,Toggled" bitfld.long 0x08 2. " [2] ,Data bit 2 toggle" "Not toggled,Toggled" bitfld.long 0x08 1. " [1] ,Data bit 1 toggle" "Not toggled,Toggled" bitfld.long 0x08 0. " [0] ,Data bit 0 toggle" "Not toggled,Toggled" width 0x0B tree.end tree "GPIO4" base ad:0x5D0C0000 width 11. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data Register" bitfld.long 0x00 31. " DR[31] ,Data bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,Data bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,Data bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,Data bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,Data bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,Data bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,Data bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,Data bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,Data bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,Data bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,Data bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,Data bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,Data bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,Data bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,Data bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,Data bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,Data bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,Data bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,Data bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,Data bit 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,Data bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,Data bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,Data bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,Data bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,Data bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,Data bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,Data bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,Data bit 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,Data bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,Data bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,Data bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,Data bit 0" "Low,High" line.long 0x04 "GDIR,GPIO Direction Register" bitfld.long 0x04 31. " GDIR[31] ,GPIO direction 31 bit" "Input,Output" bitfld.long 0x04 30. " [30] ,GPIO direction 30 bit" "Input,Output" bitfld.long 0x04 29. " [29] ,GPIO direction 29 bit" "Input,Output" bitfld.long 0x04 28. " [28] ,GPIO direction 28 bit" "Input,Output" newline bitfld.long 0x04 27. " [27] ,GPIO direction 27 bit" "Input,Output" bitfld.long 0x04 26. " [26] ,GPIO direction 26 bit" "Input,Output" bitfld.long 0x04 25. " [25] ,GPIO direction 25 bit" "Input,Output" bitfld.long 0x04 24. " [24] ,GPIO direction 24 bit" "Input,Output" newline bitfld.long 0x04 23. " [23] ,GPIO direction 23 bit" "Input,Output" bitfld.long 0x04 22. " [22] ,GPIO direction 22 bit" "Input,Output" bitfld.long 0x04 21. " [21] ,GPIO direction 21 bit" "Input,Output" bitfld.long 0x04 20. " [20] ,GPIO direction 20 bit" "Input,Output" newline bitfld.long 0x04 19. " [19] ,GPIO direction 19 bit" "Input,Output" bitfld.long 0x04 18. " [18] ,GPIO direction 18 bit" "Input,Output" bitfld.long 0x04 17. " [17] ,GPIO direction 17 bit" "Input,Output" bitfld.long 0x04 16. " [16] ,GPIO direction 16 bit" "Input,Output" newline bitfld.long 0x04 15. " [15] ,GPIO direction 15 bit" "Input,Output" bitfld.long 0x04 14. " [14] ,GPIO direction 14 bit" "Input,Output" bitfld.long 0x04 13. " [13] ,GPIO direction 13 bit" "Input,Output" bitfld.long 0x04 12. " [12] ,GPIO direction 12 bit" "Input,Output" newline bitfld.long 0x04 11. " [11] ,GPIO direction 11 bit" "Input,Output" bitfld.long 0x04 10. " [10] ,GPIO direction 10 bit" "Input,Output" bitfld.long 0x04 9. " [9] ,GPIO direction 9 bit" "Input,Output" bitfld.long 0x04 8. " [8] ,GPIO direction 8 bit" "Input,Output" newline bitfld.long 0x04 7. " [7] ,GPIO direction 7 bit" "Input,Output" bitfld.long 0x04 6. " [6] ,GPIO direction 6 bit" "Input,Output" bitfld.long 0x04 5. " [5] ,GPIO direction 5 bit" "Input,Output" bitfld.long 0x04 4. " [4] ,GPIO direction 4 bit" "Input,Output" newline bitfld.long 0x04 3. " [3] ,GPIO direction 3 bit" "Input,Output" bitfld.long 0x04 2. " [2] ,GPIO direction 2 bit" "Input,Output" bitfld.long 0x04 1. " [1] ,GPIO direction 1 bit" "Input,Output" bitfld.long 0x04 0. " [0] ,GPIO direction 0 bit" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO Pad Status Register" bitfld.long 0x00 31. " PSR[31] ,GPIO pad status bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,GPIO pad status bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,GPIO pad status bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,GPIO pad status bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,GPIO pad status bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,GPIO pad status bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,GPIO pad status bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,GPIO pad status bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,GPIO pad status bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,GPIO pad status bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,GPIO pad status bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,GPIO pad status bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,GPIO pad status bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,GPIO pad status bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,GPIO pad status bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,GPIO pad status bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,GPIO pad status bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,GPIO pad status bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,GPIO pad status bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,GPIO pad status bit 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,GPIO pad status bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,GPIO pad status bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,GPIO pad status bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,GPIO pad status bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,GPIO pad status bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,GPIO pad status bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,GPIO pad status bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,GPIO pad status bit 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,GPIO pad status bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,GPIO pad status bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,GPIO pad status bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,GPIO pad status bit 0" "Low,High" group.long 0x0C++0x13 line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1" bitfld.long 0x00 30.--31. " ICR[15] ,Controls the active condition of the interrupt function for GPIO interrupt 15" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 28.--29. " [14] ,Controls the active condition of the interrupt function for GPIO interrupt 14" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 26.--27. " [13] ,Controls the active condition of the interrupt function for GPIO interrupt 13" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 24.--25. " [12] ,Controls the active condition of the interrupt function for GPIO interrupt 12" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 22.--23. " [11] ,Controls the active condition of the interrupt function for GPIO interrupt 11" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 20.--21. " [10] ,Controls the active condition of the interrupt function for GPIO interrupt 10" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 18.--19. " [9] ,Controls the active condition of the interrupt function for GPIO interrupt 9" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 16.--17. " [8] ,Controls the active condition of the interrupt function for GPIO interrupt 8" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 14.--15. " [7] ,Controls the active condition of the interrupt function for GPIO interrupt 7" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 12.--13. " [6] ,Controls the active condition of the interrupt function for GPIO interrupt 6" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 10.--11. " [5] ,Controls the active condition of the interrupt function for GPIO interrupt 5" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 8.--9. " [4] ,Controls the active condition of the interrupt function for GPIO interrupt 4" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 6.--7. " [3] ,Controls the active condition of the interrupt function for GPIO interrupt 3" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 4.--5. " [2] ,Controls the active condition of the interrupt function for GPIO interrupt 2" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 2.--3. " [1] ,Controls the active condition of the interrupt function for GPIO interrupt 1" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 0.--1. " [0] ,Controls the active condition of the interrupt function for GPIO interrupt 0" "Low-level,High-level,Rising-edge,Falling-edge" line.long 0x04 "ICR2,GPIO Interrupt Configuration Register 2" bitfld.long 0x04 30.--31. " [31] ,Controls the active condition of the interrupt function for GPIO interrupt 31" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 28.--29. " [30] ,Controls the active condition of the interrupt function for GPIO interrupt 30" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 26.--27. " [29] ,Controls the active condition of the interrupt function for GPIO interrupt 29" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 24.--25. " [28] ,Controls the active condition of the interrupt function for GPIO interrupt 28" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 22.--23. " [27] ,Controls the active condition of the interrupt function for GPIO interrupt 27" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 20.--21. " [26] ,Controls the active condition of the interrupt function for GPIO interrupt 26" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 18.--19. " [25] ,Controls the active condition of the interrupt function for GPIO interrupt 25" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 16.--17. " [24] ,Controls the active condition of the interrupt function for GPIO interrupt 24" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 14.--15. " [23] ,Controls the active condition of the interrupt function for GPIO interrupt 23" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 12.--13. " [22] ,Controls the active condition of the interrupt function for GPIO interrupt 22" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 10.--11. " [21] ,Controls the active condition of the interrupt function for GPIO interrupt 21" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 8.--9. " [20] ,Controls the active condition of the interrupt function for GPIO interrupt 20" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 6.--7. " [19] ,Controls the active condition of the interrupt function for GPIO interrupt 19" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 4.--5. " [18] ,Controls the active condition of the interrupt function for GPIO interrupt 18" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 2.--3. " [17] ,Controls the active condition of the interrupt function for GPIO interrupt 17" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 0.--1. " [16] ,Controls the active condition of the interrupt function for GPIO interrupt 16" "Low-level,High-level,Rising-edge,Falling-edge" line.long 0x08 "IMR,GPIO Interrupt Mask Register" bitfld.long 0x08 31. " IMR[31] ,Interrupt 31 mask bit" "Disabled,Enabled" bitfld.long 0x08 30. " [30] ,Interrupt 30 mask bit" "Disabled,Enabled" bitfld.long 0x08 29. " [29] ,Interrupt 29 mask bit" "Disabled,Enabled" bitfld.long 0x08 28. " [28] ,Interrupt 28 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 27. " [27] ,Interrupt 27 mask bit" "Disabled,Enabled" bitfld.long 0x08 26. " [26] ,Interrupt 26 mask bit" "Disabled,Enabled" bitfld.long 0x08 25. " [25] ,Interrupt 25 mask bit" "Disabled,Enabled" bitfld.long 0x08 24. " [24] ,Interrupt 24 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 23. " [23] ,Interrupt 23 mask bit" "Disabled,Enabled" bitfld.long 0x08 22. " [22] ,Interrupt 22 mask bit" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Interrupt 21 mask bit" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Interrupt 20 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 19. " [19] ,Interrupt 19 mask bit" "Disabled,Enabled" bitfld.long 0x08 18. " [18] ,Interrupt 18 mask bit" "Disabled,Enabled" bitfld.long 0x08 17. " [17] ,Interrupt 17 mask bit" "Disabled,Enabled" bitfld.long 0x08 16. " [16] ,Interrupt 16 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 15. " [15] ,Interrupt 15 mask bit" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Interrupt 14 mask bit" "Disabled,Enabled" bitfld.long 0x08 13. " [13] ,Interrupt 13 mask bit" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Interrupt 12 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 11. " [11] ,Interrupt 11 mask bit" "Disabled,Enabled" bitfld.long 0x08 10. " [10] ,Interrupt 10 mask bit" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Interrupt 9 mask bit" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Interrupt 8 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Interrupt 7 mask bit" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Interrupt 6 mask bit" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Interrupt 5 mask bit" "Disabled,Enabled" bitfld.long 0x08 4. " [4] ,Interrupt 4 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 3. " [3] ,Interrupt 3 mask bit" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Interrupt 2 mask bit" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Interrupt 1 mask bit" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Interrupt 0 mask bit" "Disabled,Enabled" line.long 0x0C "ISR,GPIO Interrupt Status Register" eventfld.long 0x0C 31. " ISR[31] ,Interrupt 31 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 30. " [30] ,Interrupt 30 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 29. " [29] ,Interrupt 29 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 28. " [28] ,Interrupt 28 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 27. " [27] ,Interrupt 27 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 26. " [26] ,Interrupt 26 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 25. " [25] ,Interrupt 25 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 24. " [24] ,Interrupt 24 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 23. " [23] ,Interrupt 23 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 22. " [22] ,Interrupt 22 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 21. " [21] ,Interrupt 21 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 20. " [20] ,Interrupt 20 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 19. " [19] ,Interrupt 19 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 18. " [18] ,Interrupt 18 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 17. " [17] ,Interrupt 17 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 16. " [16] ,Interrupt 16 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 15. " [15] ,Interrupt 15 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 14. " [14] ,Interrupt 14 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 13. " [13] ,Interrupt 13 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 12. " [12] ,Interrupt 12 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 11. " [11] ,Interrupt 11 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 10. " [10] ,Interrupt 10 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 9. " [9] ,Interrupt 9 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 8. " [8] ,Interrupt 8 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 7. " [7] ,Interrupt 7 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 6. " [6] ,Interrupt 6 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 5. " [5] ,Interrupt 5 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 4. " [4] ,Interrupt 4 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 3. " [3] ,Interrupt 3 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 2. " [2] ,Interrupt 2 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 1. " [1] ,Interrupt 1 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 0. " [0] ,Interrupt 0 status bit" "No interrupt,Interrupt" line.long 0x10 "EDGE_SEL,GPIO Edge Select Register" bitfld.long 0x10 31. " GPIO_EDGE_SEL[31] ,Edge select bit 31" "31 setting,Any edge" bitfld.long 0x10 30. " [30] ,Edge select bit 30" "30 setting,Any edge" bitfld.long 0x10 29. " [29] ,Edge select bit 29" "29 setting,Any edge" bitfld.long 0x10 28. " [28] ,Edge select bit 28" "28 setting,Any edge" newline bitfld.long 0x10 27. " [27] ,Edge select bit 27" "27 setting,Any edge" bitfld.long 0x10 26. " [26] ,Edge select bit 26" "26 setting,Any edge" bitfld.long 0x10 25. " [25] ,Edge select bit 25" "25 setting,Any edge" bitfld.long 0x10 24. " [24] ,Edge select bit 24" "24 setting,Any edge" newline bitfld.long 0x10 23. " [23] ,Edge select bit 23" "23 setting,Any edge" bitfld.long 0x10 22. " [22] ,Edge select bit 22" "22 setting,Any edge" bitfld.long 0x10 21. " [21] ,Edge select bit 21" "21 setting,Any edge" bitfld.long 0x10 20. " [20] ,Edge select bit 20" "20 setting,Any edge" newline bitfld.long 0x10 19. " [19] ,Edge select bit 19" "19 setting,Any edge" bitfld.long 0x10 18. " [18] ,Edge select bit 18" "18 setting,Any edge" bitfld.long 0x10 17. " [17] ,Edge select bit 17" "17 setting,Any edge" bitfld.long 0x10 16. " [16] ,Edge select bit 16" "16 setting,Any edge" newline bitfld.long 0x10 15. " [15] ,Edge select bit 15" "15 setting,Any edge" bitfld.long 0x10 14. " [14] ,Edge select bit 14" "14 setting,Any edge" bitfld.long 0x10 13. " [13] ,Edge select bit 13" "13 setting,Any edge" bitfld.long 0x10 12. " [12] ,Edge select bit 12" "12 setting,Any edge" newline bitfld.long 0x10 11. " [11] ,Edge select bit 11" "11 setting,Any edge" bitfld.long 0x10 10. " [10] ,Edge select bit 10" "10 setting,Any edge" bitfld.long 0x10 9. " [9] ,Edge select bit 9" "9 setting,Any edge" bitfld.long 0x10 8. " [8] ,Edge select bit 8" "8 setting,Any edge" newline bitfld.long 0x10 7. " [7] ,Edge select bit 7" "7 setting,Any edge" bitfld.long 0x10 6. " [6] ,Edge select bit 6" "6 setting,Any edge" bitfld.long 0x10 5. " [5] ,Edge select bit 5" "5 setting,Any edge" bitfld.long 0x10 4. " [4] ,Edge select bit 4" "4 setting,Any edge" newline bitfld.long 0x10 3. " [3] ,Edge select bit 3" "3 setting,Any edge" bitfld.long 0x10 2. " [2] ,Edge select bit 2" "2 setting,Any edge" bitfld.long 0x10 1. " [1] ,Edge select bit 1" "1 setting,Any edge" bitfld.long 0x10 0. " [0] ,Edge select bit 0" "0 setting,Any edge" wgroup.long 0x84++0x0B line.long 0x00 "DR_SET,GPIO Data Register SET Register" bitfld.long 0x00 31. " DR_SET[31] ,Data bit 31 set" "Not set,Set" bitfld.long 0x00 30. " [30] ,Data bit 30 set" "Not set,Set" bitfld.long 0x00 29. " [29] ,Data bit 29 set" "Not set,Set" bitfld.long 0x00 28. " [28] ,Data bit 28 set" "Not set,Set" newline bitfld.long 0x00 27. " [27] ,Data bit 27 set" "Not set,Set" bitfld.long 0x00 26. " [26] ,Data bit 26 set" "Not set,Set" bitfld.long 0x00 25. " [25] ,Data bit 25 set" "Not set,Set" bitfld.long 0x00 24. " [24] ,Data bit 24 set" "Not set,Set" newline bitfld.long 0x00 23. " [23] ,Data bit 23 set" "Not set,Set" bitfld.long 0x00 22. " [22] ,Data bit 22 set" "Not set,Set" bitfld.long 0x00 21. " [21] ,Data bit 21 set" "Not set,Set" bitfld.long 0x00 20. " [20] ,Data bit 20 set" "Not set,Set" newline bitfld.long 0x00 19. " [19] ,Data bit 19 set" "Not set,Set" bitfld.long 0x00 18. " [18] ,Data bit 18 set" "Not set,Set" bitfld.long 0x00 17. " [17] ,Data bit 17 set" "Not set,Set" bitfld.long 0x00 16. " [16] ,Data bit 16 set" "Not set,Set" newline bitfld.long 0x00 15. " [15] ,Data bit 15 set" "Not set,Set" bitfld.long 0x00 14. " [14] ,Data bit 14 set" "Not set,Set" bitfld.long 0x00 13. " [13] ,Data bit 13 set" "Not set,Set" bitfld.long 0x00 12. " [12] ,Data bit 12 set" "Not set,Set" newline bitfld.long 0x00 11. " [11] ,Data bit 11 set" "Not set,Set" bitfld.long 0x00 10. " [10] ,Data bit 10 set" "Not set,Set" bitfld.long 0x00 9. " [9] ,Data bit 9 set" "Not set,Set" bitfld.long 0x00 8. " [8] ,Data bit 8 set" "Not set,Set" newline bitfld.long 0x00 7. " [7] ,Data bit 7 set" "Not set,Set" bitfld.long 0x00 6. " [6] ,Data bit 6 set" "Not set,Set" bitfld.long 0x00 5. " [5] ,Data bit 5 set" "Not set,Set" bitfld.long 0x00 4. " [4] ,Data bit 4 set" "Not set,Set" newline bitfld.long 0x00 3. " [3] ,Data bit 3 set" "Not set,Set" bitfld.long 0x00 2. " [2] ,Data bit 2 set" "Not set,Set" bitfld.long 0x00 1. " [1] ,Data bit 1 set" "Not set,Set" bitfld.long 0x00 0. " [0] ,Data bit 0 set" "Not set,Set" line.long 0x04 "DR_CLEAR,GPIO Data Register CLEAR Register" bitfld.long 0x04 31. " DR_CLEAR[31] ,Data bit 31 clear" "No effect,Clear" bitfld.long 0x04 30. " [30] ,Data bit 30 clear" "No effect,Clear" bitfld.long 0x04 29. " [29] ,Data bit 29 clear" "No effect,Clear" bitfld.long 0x04 28. " [28] ,Data bit 28 clear" "No effect,Clear" newline bitfld.long 0x04 27. " [27] ,Data bit 27 clear" "No effect,Clear" bitfld.long 0x04 26. " [26] ,Data bit 26 clear" "No effect,Clear" bitfld.long 0x04 25. " [25] ,Data bit 25 clear" "No effect,Clear" bitfld.long 0x04 24. " [24] ,Data bit 24 clear" "No effect,Clear" newline bitfld.long 0x04 23. " [23] ,Data bit 23 clear" "No effect,Clear" bitfld.long 0x04 22. " [22] ,Data bit 22 clear" "No effect,Clear" bitfld.long 0x04 21. " [21] ,Data bit 21 clear" "No effect,Clear" bitfld.long 0x04 20. " [20] ,Data bit 20 clear" "No effect,Clear" newline bitfld.long 0x04 19. " [19] ,Data bit 19 clear" "No effect,Clear" bitfld.long 0x04 18. " [18] ,Data bit 18 clear" "No effect,Clear" bitfld.long 0x04 17. " [17] ,Data bit 17 clear" "No effect,Clear" bitfld.long 0x04 16. " [16] ,Data bit 16 clear" "No effect,Clear" newline bitfld.long 0x04 15. " [15] ,Data bit 15 clear" "No effect,Clear" bitfld.long 0x04 14. " [14] ,Data bit 14 clear" "No effect,Clear" bitfld.long 0x04 13. " [13] ,Data bit 13 clear" "No effect,Clear" bitfld.long 0x04 12. " [12] ,Data bit 12 clear" "No effect,Clear" newline bitfld.long 0x04 11. " [11] ,Data bit 11 clear" "No effect,Clear" bitfld.long 0x04 10. " [10] ,Data bit 10 clear" "No effect,Clear" bitfld.long 0x04 9. " [9] ,Data bit 9 clear" "No effect,Clear" bitfld.long 0x04 8. " [8] ,Data bit 8 clear" "No effect,Clear" newline bitfld.long 0x04 7. " [7] ,Data bit 7 clear" "No effect,Clear" bitfld.long 0x04 6. " [6] ,Data bit 6 clear" "No effect,Clear" bitfld.long 0x04 5. " [5] ,Data bit 5 clear" "No effect,Clear" bitfld.long 0x04 4. " [4] ,Data bit 4 clear" "No effect,Clear" newline bitfld.long 0x04 3. " [3] ,Data bit 3 clear" "No effect,Clear" bitfld.long 0x04 2. " [2] ,Data bit 2 clear" "No effect,Clear" bitfld.long 0x04 1. " [1] ,Data bit 1 clear" "No effect,Clear" bitfld.long 0x04 0. " [0] ,Data bit 0 clear" "No effect,Clear" line.long 0x08 "DR_TOGGLE,GPIO Data Register TOGGLE Register" bitfld.long 0x08 31. " DR_TOGGLE[31] ,Data bit 31 toggle" "Not toggled,Toggled" bitfld.long 0x08 30. " [30] ,Data bit 30 toggle" "No effect,Clear" bitfld.long 0x08 29. " [29] ,Data bit 29 toggle" "Not toggled,Toggled" bitfld.long 0x08 28. " [28] ,Data bit 28 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 27. " [27] ,Data bit 27 toggle" "Not toggled,Toggled" bitfld.long 0x08 26. " [26] ,Data bit 26 toggle" "Not toggled,Toggled" bitfld.long 0x08 25. " [25] ,Data bit 25 toggle" "Not toggled,Toggled" bitfld.long 0x08 24. " [24] ,Data bit 24 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 23. " [23] ,Data bit 23 toggle" "Not toggled,Toggled" bitfld.long 0x08 22. " [22] ,Data bit 22 toggle" "Not toggled,Toggled" bitfld.long 0x08 21. " [21] ,Data bit 21 toggle" "Not toggled,Toggled" bitfld.long 0x08 20. " [20] ,Data bit 20 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 19. " [19] ,Data bit 19 toggle" "Not toggled,Toggled" bitfld.long 0x08 18. " [18] ,Data bit 18 toggle" "Not toggled,Toggled" bitfld.long 0x08 17. " [17] ,Data bit 17 toggle" "Not toggled,Toggled" bitfld.long 0x08 16. " [16] ,Data bit 16 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 15. " [15] ,Data bit 15 toggle" "Not toggled,Toggled" bitfld.long 0x08 14. " [14] ,Data bit 14 toggle" "Not toggled,Toggled" bitfld.long 0x08 13. " [13] ,Data bit 13 toggle" "Not toggled,Toggled" bitfld.long 0x08 12. " [12] ,Data bit 12 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 11. " [11] ,Data bit 11 toggle" "Not toggled,Toggled" bitfld.long 0x08 10. " [10] ,Data bit 10 toggle" "Not toggled,Toggled" bitfld.long 0x08 9. " [9] ,Data bit 9 toggle" "Not toggled,Toggled" bitfld.long 0x08 8. " [8] ,Data bit 8 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 7. " [7] ,Data bit 7 toggle" "Not toggled,Toggled" bitfld.long 0x08 6. " [6] ,Data bit 6 toggle" "Not toggled,Toggled" bitfld.long 0x08 5. " [5] ,Data bit 5 toggle" "Not toggled,Toggled" bitfld.long 0x08 4. " [4] ,Data bit 4 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 3. " [3] ,Data bit 3 toggle" "Not toggled,Toggled" bitfld.long 0x08 2. " [2] ,Data bit 2 toggle" "Not toggled,Toggled" bitfld.long 0x08 1. " [1] ,Data bit 1 toggle" "Not toggled,Toggled" bitfld.long 0x08 0. " [0] ,Data bit 0 toggle" "Not toggled,Toggled" width 0x0B tree.end tree "GPIO5" base ad:0x5D0D0000 width 11. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data Register" bitfld.long 0x00 31. " DR[31] ,Data bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,Data bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,Data bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,Data bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,Data bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,Data bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,Data bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,Data bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,Data bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,Data bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,Data bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,Data bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,Data bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,Data bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,Data bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,Data bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,Data bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,Data bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,Data bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,Data bit 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,Data bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,Data bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,Data bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,Data bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,Data bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,Data bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,Data bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,Data bit 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,Data bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,Data bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,Data bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,Data bit 0" "Low,High" line.long 0x04 "GDIR,GPIO Direction Register" bitfld.long 0x04 31. " GDIR[31] ,GPIO direction 31 bit" "Input,Output" bitfld.long 0x04 30. " [30] ,GPIO direction 30 bit" "Input,Output" bitfld.long 0x04 29. " [29] ,GPIO direction 29 bit" "Input,Output" bitfld.long 0x04 28. " [28] ,GPIO direction 28 bit" "Input,Output" newline bitfld.long 0x04 27. " [27] ,GPIO direction 27 bit" "Input,Output" bitfld.long 0x04 26. " [26] ,GPIO direction 26 bit" "Input,Output" bitfld.long 0x04 25. " [25] ,GPIO direction 25 bit" "Input,Output" bitfld.long 0x04 24. " [24] ,GPIO direction 24 bit" "Input,Output" newline bitfld.long 0x04 23. " [23] ,GPIO direction 23 bit" "Input,Output" bitfld.long 0x04 22. " [22] ,GPIO direction 22 bit" "Input,Output" bitfld.long 0x04 21. " [21] ,GPIO direction 21 bit" "Input,Output" bitfld.long 0x04 20. " [20] ,GPIO direction 20 bit" "Input,Output" newline bitfld.long 0x04 19. " [19] ,GPIO direction 19 bit" "Input,Output" bitfld.long 0x04 18. " [18] ,GPIO direction 18 bit" "Input,Output" bitfld.long 0x04 17. " [17] ,GPIO direction 17 bit" "Input,Output" bitfld.long 0x04 16. " [16] ,GPIO direction 16 bit" "Input,Output" newline bitfld.long 0x04 15. " [15] ,GPIO direction 15 bit" "Input,Output" bitfld.long 0x04 14. " [14] ,GPIO direction 14 bit" "Input,Output" bitfld.long 0x04 13. " [13] ,GPIO direction 13 bit" "Input,Output" bitfld.long 0x04 12. " [12] ,GPIO direction 12 bit" "Input,Output" newline bitfld.long 0x04 11. " [11] ,GPIO direction 11 bit" "Input,Output" bitfld.long 0x04 10. " [10] ,GPIO direction 10 bit" "Input,Output" bitfld.long 0x04 9. " [9] ,GPIO direction 9 bit" "Input,Output" bitfld.long 0x04 8. " [8] ,GPIO direction 8 bit" "Input,Output" newline bitfld.long 0x04 7. " [7] ,GPIO direction 7 bit" "Input,Output" bitfld.long 0x04 6. " [6] ,GPIO direction 6 bit" "Input,Output" bitfld.long 0x04 5. " [5] ,GPIO direction 5 bit" "Input,Output" bitfld.long 0x04 4. " [4] ,GPIO direction 4 bit" "Input,Output" newline bitfld.long 0x04 3. " [3] ,GPIO direction 3 bit" "Input,Output" bitfld.long 0x04 2. " [2] ,GPIO direction 2 bit" "Input,Output" bitfld.long 0x04 1. " [1] ,GPIO direction 1 bit" "Input,Output" bitfld.long 0x04 0. " [0] ,GPIO direction 0 bit" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO Pad Status Register" bitfld.long 0x00 31. " PSR[31] ,GPIO pad status bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,GPIO pad status bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,GPIO pad status bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,GPIO pad status bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,GPIO pad status bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,GPIO pad status bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,GPIO pad status bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,GPIO pad status bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,GPIO pad status bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,GPIO pad status bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,GPIO pad status bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,GPIO pad status bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,GPIO pad status bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,GPIO pad status bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,GPIO pad status bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,GPIO pad status bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,GPIO pad status bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,GPIO pad status bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,GPIO pad status bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,GPIO pad status bit 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,GPIO pad status bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,GPIO pad status bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,GPIO pad status bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,GPIO pad status bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,GPIO pad status bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,GPIO pad status bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,GPIO pad status bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,GPIO pad status bit 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,GPIO pad status bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,GPIO pad status bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,GPIO pad status bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,GPIO pad status bit 0" "Low,High" group.long 0x0C++0x13 line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1" bitfld.long 0x00 30.--31. " ICR[15] ,Controls the active condition of the interrupt function for GPIO interrupt 15" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 28.--29. " [14] ,Controls the active condition of the interrupt function for GPIO interrupt 14" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 26.--27. " [13] ,Controls the active condition of the interrupt function for GPIO interrupt 13" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 24.--25. " [12] ,Controls the active condition of the interrupt function for GPIO interrupt 12" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 22.--23. " [11] ,Controls the active condition of the interrupt function for GPIO interrupt 11" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 20.--21. " [10] ,Controls the active condition of the interrupt function for GPIO interrupt 10" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 18.--19. " [9] ,Controls the active condition of the interrupt function for GPIO interrupt 9" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 16.--17. " [8] ,Controls the active condition of the interrupt function for GPIO interrupt 8" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 14.--15. " [7] ,Controls the active condition of the interrupt function for GPIO interrupt 7" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 12.--13. " [6] ,Controls the active condition of the interrupt function for GPIO interrupt 6" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 10.--11. " [5] ,Controls the active condition of the interrupt function for GPIO interrupt 5" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 8.--9. " [4] ,Controls the active condition of the interrupt function for GPIO interrupt 4" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 6.--7. " [3] ,Controls the active condition of the interrupt function for GPIO interrupt 3" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 4.--5. " [2] ,Controls the active condition of the interrupt function for GPIO interrupt 2" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 2.--3. " [1] ,Controls the active condition of the interrupt function for GPIO interrupt 1" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 0.--1. " [0] ,Controls the active condition of the interrupt function for GPIO interrupt 0" "Low-level,High-level,Rising-edge,Falling-edge" line.long 0x04 "ICR2,GPIO Interrupt Configuration Register 2" bitfld.long 0x04 30.--31. " [31] ,Controls the active condition of the interrupt function for GPIO interrupt 31" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 28.--29. " [30] ,Controls the active condition of the interrupt function for GPIO interrupt 30" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 26.--27. " [29] ,Controls the active condition of the interrupt function for GPIO interrupt 29" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 24.--25. " [28] ,Controls the active condition of the interrupt function for GPIO interrupt 28" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 22.--23. " [27] ,Controls the active condition of the interrupt function for GPIO interrupt 27" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 20.--21. " [26] ,Controls the active condition of the interrupt function for GPIO interrupt 26" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 18.--19. " [25] ,Controls the active condition of the interrupt function for GPIO interrupt 25" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 16.--17. " [24] ,Controls the active condition of the interrupt function for GPIO interrupt 24" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 14.--15. " [23] ,Controls the active condition of the interrupt function for GPIO interrupt 23" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 12.--13. " [22] ,Controls the active condition of the interrupt function for GPIO interrupt 22" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 10.--11. " [21] ,Controls the active condition of the interrupt function for GPIO interrupt 21" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 8.--9. " [20] ,Controls the active condition of the interrupt function for GPIO interrupt 20" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 6.--7. " [19] ,Controls the active condition of the interrupt function for GPIO interrupt 19" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 4.--5. " [18] ,Controls the active condition of the interrupt function for GPIO interrupt 18" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 2.--3. " [17] ,Controls the active condition of the interrupt function for GPIO interrupt 17" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 0.--1. " [16] ,Controls the active condition of the interrupt function for GPIO interrupt 16" "Low-level,High-level,Rising-edge,Falling-edge" line.long 0x08 "IMR,GPIO Interrupt Mask Register" bitfld.long 0x08 31. " IMR[31] ,Interrupt 31 mask bit" "Disabled,Enabled" bitfld.long 0x08 30. " [30] ,Interrupt 30 mask bit" "Disabled,Enabled" bitfld.long 0x08 29. " [29] ,Interrupt 29 mask bit" "Disabled,Enabled" bitfld.long 0x08 28. " [28] ,Interrupt 28 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 27. " [27] ,Interrupt 27 mask bit" "Disabled,Enabled" bitfld.long 0x08 26. " [26] ,Interrupt 26 mask bit" "Disabled,Enabled" bitfld.long 0x08 25. " [25] ,Interrupt 25 mask bit" "Disabled,Enabled" bitfld.long 0x08 24. " [24] ,Interrupt 24 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 23. " [23] ,Interrupt 23 mask bit" "Disabled,Enabled" bitfld.long 0x08 22. " [22] ,Interrupt 22 mask bit" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Interrupt 21 mask bit" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Interrupt 20 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 19. " [19] ,Interrupt 19 mask bit" "Disabled,Enabled" bitfld.long 0x08 18. " [18] ,Interrupt 18 mask bit" "Disabled,Enabled" bitfld.long 0x08 17. " [17] ,Interrupt 17 mask bit" "Disabled,Enabled" bitfld.long 0x08 16. " [16] ,Interrupt 16 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 15. " [15] ,Interrupt 15 mask bit" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Interrupt 14 mask bit" "Disabled,Enabled" bitfld.long 0x08 13. " [13] ,Interrupt 13 mask bit" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Interrupt 12 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 11. " [11] ,Interrupt 11 mask bit" "Disabled,Enabled" bitfld.long 0x08 10. " [10] ,Interrupt 10 mask bit" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Interrupt 9 mask bit" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Interrupt 8 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Interrupt 7 mask bit" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Interrupt 6 mask bit" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Interrupt 5 mask bit" "Disabled,Enabled" bitfld.long 0x08 4. " [4] ,Interrupt 4 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 3. " [3] ,Interrupt 3 mask bit" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Interrupt 2 mask bit" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Interrupt 1 mask bit" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Interrupt 0 mask bit" "Disabled,Enabled" line.long 0x0C "ISR,GPIO Interrupt Status Register" eventfld.long 0x0C 31. " ISR[31] ,Interrupt 31 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 30. " [30] ,Interrupt 30 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 29. " [29] ,Interrupt 29 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 28. " [28] ,Interrupt 28 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 27. " [27] ,Interrupt 27 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 26. " [26] ,Interrupt 26 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 25. " [25] ,Interrupt 25 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 24. " [24] ,Interrupt 24 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 23. " [23] ,Interrupt 23 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 22. " [22] ,Interrupt 22 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 21. " [21] ,Interrupt 21 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 20. " [20] ,Interrupt 20 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 19. " [19] ,Interrupt 19 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 18. " [18] ,Interrupt 18 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 17. " [17] ,Interrupt 17 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 16. " [16] ,Interrupt 16 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 15. " [15] ,Interrupt 15 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 14. " [14] ,Interrupt 14 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 13. " [13] ,Interrupt 13 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 12. " [12] ,Interrupt 12 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 11. " [11] ,Interrupt 11 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 10. " [10] ,Interrupt 10 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 9. " [9] ,Interrupt 9 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 8. " [8] ,Interrupt 8 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 7. " [7] ,Interrupt 7 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 6. " [6] ,Interrupt 6 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 5. " [5] ,Interrupt 5 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 4. " [4] ,Interrupt 4 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 3. " [3] ,Interrupt 3 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 2. " [2] ,Interrupt 2 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 1. " [1] ,Interrupt 1 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 0. " [0] ,Interrupt 0 status bit" "No interrupt,Interrupt" line.long 0x10 "EDGE_SEL,GPIO Edge Select Register" bitfld.long 0x10 31. " GPIO_EDGE_SEL[31] ,Edge select bit 31" "31 setting,Any edge" bitfld.long 0x10 30. " [30] ,Edge select bit 30" "30 setting,Any edge" bitfld.long 0x10 29. " [29] ,Edge select bit 29" "29 setting,Any edge" bitfld.long 0x10 28. " [28] ,Edge select bit 28" "28 setting,Any edge" newline bitfld.long 0x10 27. " [27] ,Edge select bit 27" "27 setting,Any edge" bitfld.long 0x10 26. " [26] ,Edge select bit 26" "26 setting,Any edge" bitfld.long 0x10 25. " [25] ,Edge select bit 25" "25 setting,Any edge" bitfld.long 0x10 24. " [24] ,Edge select bit 24" "24 setting,Any edge" newline bitfld.long 0x10 23. " [23] ,Edge select bit 23" "23 setting,Any edge" bitfld.long 0x10 22. " [22] ,Edge select bit 22" "22 setting,Any edge" bitfld.long 0x10 21. " [21] ,Edge select bit 21" "21 setting,Any edge" bitfld.long 0x10 20. " [20] ,Edge select bit 20" "20 setting,Any edge" newline bitfld.long 0x10 19. " [19] ,Edge select bit 19" "19 setting,Any edge" bitfld.long 0x10 18. " [18] ,Edge select bit 18" "18 setting,Any edge" bitfld.long 0x10 17. " [17] ,Edge select bit 17" "17 setting,Any edge" bitfld.long 0x10 16. " [16] ,Edge select bit 16" "16 setting,Any edge" newline bitfld.long 0x10 15. " [15] ,Edge select bit 15" "15 setting,Any edge" bitfld.long 0x10 14. " [14] ,Edge select bit 14" "14 setting,Any edge" bitfld.long 0x10 13. " [13] ,Edge select bit 13" "13 setting,Any edge" bitfld.long 0x10 12. " [12] ,Edge select bit 12" "12 setting,Any edge" newline bitfld.long 0x10 11. " [11] ,Edge select bit 11" "11 setting,Any edge" bitfld.long 0x10 10. " [10] ,Edge select bit 10" "10 setting,Any edge" bitfld.long 0x10 9. " [9] ,Edge select bit 9" "9 setting,Any edge" bitfld.long 0x10 8. " [8] ,Edge select bit 8" "8 setting,Any edge" newline bitfld.long 0x10 7. " [7] ,Edge select bit 7" "7 setting,Any edge" bitfld.long 0x10 6. " [6] ,Edge select bit 6" "6 setting,Any edge" bitfld.long 0x10 5. " [5] ,Edge select bit 5" "5 setting,Any edge" bitfld.long 0x10 4. " [4] ,Edge select bit 4" "4 setting,Any edge" newline bitfld.long 0x10 3. " [3] ,Edge select bit 3" "3 setting,Any edge" bitfld.long 0x10 2. " [2] ,Edge select bit 2" "2 setting,Any edge" bitfld.long 0x10 1. " [1] ,Edge select bit 1" "1 setting,Any edge" bitfld.long 0x10 0. " [0] ,Edge select bit 0" "0 setting,Any edge" wgroup.long 0x84++0x0B line.long 0x00 "DR_SET,GPIO Data Register SET Register" bitfld.long 0x00 31. " DR_SET[31] ,Data bit 31 set" "Not set,Set" bitfld.long 0x00 30. " [30] ,Data bit 30 set" "Not set,Set" bitfld.long 0x00 29. " [29] ,Data bit 29 set" "Not set,Set" bitfld.long 0x00 28. " [28] ,Data bit 28 set" "Not set,Set" newline bitfld.long 0x00 27. " [27] ,Data bit 27 set" "Not set,Set" bitfld.long 0x00 26. " [26] ,Data bit 26 set" "Not set,Set" bitfld.long 0x00 25. " [25] ,Data bit 25 set" "Not set,Set" bitfld.long 0x00 24. " [24] ,Data bit 24 set" "Not set,Set" newline bitfld.long 0x00 23. " [23] ,Data bit 23 set" "Not set,Set" bitfld.long 0x00 22. " [22] ,Data bit 22 set" "Not set,Set" bitfld.long 0x00 21. " [21] ,Data bit 21 set" "Not set,Set" bitfld.long 0x00 20. " [20] ,Data bit 20 set" "Not set,Set" newline bitfld.long 0x00 19. " [19] ,Data bit 19 set" "Not set,Set" bitfld.long 0x00 18. " [18] ,Data bit 18 set" "Not set,Set" bitfld.long 0x00 17. " [17] ,Data bit 17 set" "Not set,Set" bitfld.long 0x00 16. " [16] ,Data bit 16 set" "Not set,Set" newline bitfld.long 0x00 15. " [15] ,Data bit 15 set" "Not set,Set" bitfld.long 0x00 14. " [14] ,Data bit 14 set" "Not set,Set" bitfld.long 0x00 13. " [13] ,Data bit 13 set" "Not set,Set" bitfld.long 0x00 12. " [12] ,Data bit 12 set" "Not set,Set" newline bitfld.long 0x00 11. " [11] ,Data bit 11 set" "Not set,Set" bitfld.long 0x00 10. " [10] ,Data bit 10 set" "Not set,Set" bitfld.long 0x00 9. " [9] ,Data bit 9 set" "Not set,Set" bitfld.long 0x00 8. " [8] ,Data bit 8 set" "Not set,Set" newline bitfld.long 0x00 7. " [7] ,Data bit 7 set" "Not set,Set" bitfld.long 0x00 6. " [6] ,Data bit 6 set" "Not set,Set" bitfld.long 0x00 5. " [5] ,Data bit 5 set" "Not set,Set" bitfld.long 0x00 4. " [4] ,Data bit 4 set" "Not set,Set" newline bitfld.long 0x00 3. " [3] ,Data bit 3 set" "Not set,Set" bitfld.long 0x00 2. " [2] ,Data bit 2 set" "Not set,Set" bitfld.long 0x00 1. " [1] ,Data bit 1 set" "Not set,Set" bitfld.long 0x00 0. " [0] ,Data bit 0 set" "Not set,Set" line.long 0x04 "DR_CLEAR,GPIO Data Register CLEAR Register" bitfld.long 0x04 31. " DR_CLEAR[31] ,Data bit 31 clear" "No effect,Clear" bitfld.long 0x04 30. " [30] ,Data bit 30 clear" "No effect,Clear" bitfld.long 0x04 29. " [29] ,Data bit 29 clear" "No effect,Clear" bitfld.long 0x04 28. " [28] ,Data bit 28 clear" "No effect,Clear" newline bitfld.long 0x04 27. " [27] ,Data bit 27 clear" "No effect,Clear" bitfld.long 0x04 26. " [26] ,Data bit 26 clear" "No effect,Clear" bitfld.long 0x04 25. " [25] ,Data bit 25 clear" "No effect,Clear" bitfld.long 0x04 24. " [24] ,Data bit 24 clear" "No effect,Clear" newline bitfld.long 0x04 23. " [23] ,Data bit 23 clear" "No effect,Clear" bitfld.long 0x04 22. " [22] ,Data bit 22 clear" "No effect,Clear" bitfld.long 0x04 21. " [21] ,Data bit 21 clear" "No effect,Clear" bitfld.long 0x04 20. " [20] ,Data bit 20 clear" "No effect,Clear" newline bitfld.long 0x04 19. " [19] ,Data bit 19 clear" "No effect,Clear" bitfld.long 0x04 18. " [18] ,Data bit 18 clear" "No effect,Clear" bitfld.long 0x04 17. " [17] ,Data bit 17 clear" "No effect,Clear" bitfld.long 0x04 16. " [16] ,Data bit 16 clear" "No effect,Clear" newline bitfld.long 0x04 15. " [15] ,Data bit 15 clear" "No effect,Clear" bitfld.long 0x04 14. " [14] ,Data bit 14 clear" "No effect,Clear" bitfld.long 0x04 13. " [13] ,Data bit 13 clear" "No effect,Clear" bitfld.long 0x04 12. " [12] ,Data bit 12 clear" "No effect,Clear" newline bitfld.long 0x04 11. " [11] ,Data bit 11 clear" "No effect,Clear" bitfld.long 0x04 10. " [10] ,Data bit 10 clear" "No effect,Clear" bitfld.long 0x04 9. " [9] ,Data bit 9 clear" "No effect,Clear" bitfld.long 0x04 8. " [8] ,Data bit 8 clear" "No effect,Clear" newline bitfld.long 0x04 7. " [7] ,Data bit 7 clear" "No effect,Clear" bitfld.long 0x04 6. " [6] ,Data bit 6 clear" "No effect,Clear" bitfld.long 0x04 5. " [5] ,Data bit 5 clear" "No effect,Clear" bitfld.long 0x04 4. " [4] ,Data bit 4 clear" "No effect,Clear" newline bitfld.long 0x04 3. " [3] ,Data bit 3 clear" "No effect,Clear" bitfld.long 0x04 2. " [2] ,Data bit 2 clear" "No effect,Clear" bitfld.long 0x04 1. " [1] ,Data bit 1 clear" "No effect,Clear" bitfld.long 0x04 0. " [0] ,Data bit 0 clear" "No effect,Clear" line.long 0x08 "DR_TOGGLE,GPIO Data Register TOGGLE Register" bitfld.long 0x08 31. " DR_TOGGLE[31] ,Data bit 31 toggle" "Not toggled,Toggled" bitfld.long 0x08 30. " [30] ,Data bit 30 toggle" "No effect,Clear" bitfld.long 0x08 29. " [29] ,Data bit 29 toggle" "Not toggled,Toggled" bitfld.long 0x08 28. " [28] ,Data bit 28 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 27. " [27] ,Data bit 27 toggle" "Not toggled,Toggled" bitfld.long 0x08 26. " [26] ,Data bit 26 toggle" "Not toggled,Toggled" bitfld.long 0x08 25. " [25] ,Data bit 25 toggle" "Not toggled,Toggled" bitfld.long 0x08 24. " [24] ,Data bit 24 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 23. " [23] ,Data bit 23 toggle" "Not toggled,Toggled" bitfld.long 0x08 22. " [22] ,Data bit 22 toggle" "Not toggled,Toggled" bitfld.long 0x08 21. " [21] ,Data bit 21 toggle" "Not toggled,Toggled" bitfld.long 0x08 20. " [20] ,Data bit 20 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 19. " [19] ,Data bit 19 toggle" "Not toggled,Toggled" bitfld.long 0x08 18. " [18] ,Data bit 18 toggle" "Not toggled,Toggled" bitfld.long 0x08 17. " [17] ,Data bit 17 toggle" "Not toggled,Toggled" bitfld.long 0x08 16. " [16] ,Data bit 16 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 15. " [15] ,Data bit 15 toggle" "Not toggled,Toggled" bitfld.long 0x08 14. " [14] ,Data bit 14 toggle" "Not toggled,Toggled" bitfld.long 0x08 13. " [13] ,Data bit 13 toggle" "Not toggled,Toggled" bitfld.long 0x08 12. " [12] ,Data bit 12 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 11. " [11] ,Data bit 11 toggle" "Not toggled,Toggled" bitfld.long 0x08 10. " [10] ,Data bit 10 toggle" "Not toggled,Toggled" bitfld.long 0x08 9. " [9] ,Data bit 9 toggle" "Not toggled,Toggled" bitfld.long 0x08 8. " [8] ,Data bit 8 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 7. " [7] ,Data bit 7 toggle" "Not toggled,Toggled" bitfld.long 0x08 6. " [6] ,Data bit 6 toggle" "Not toggled,Toggled" bitfld.long 0x08 5. " [5] ,Data bit 5 toggle" "Not toggled,Toggled" bitfld.long 0x08 4. " [4] ,Data bit 4 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 3. " [3] ,Data bit 3 toggle" "Not toggled,Toggled" bitfld.long 0x08 2. " [2] ,Data bit 2 toggle" "Not toggled,Toggled" bitfld.long 0x08 1. " [1] ,Data bit 1 toggle" "Not toggled,Toggled" bitfld.long 0x08 0. " [0] ,Data bit 0 toggle" "Not toggled,Toggled" width 0x0B tree.end tree "GPIO6" base ad:0x5D0E0000 width 11. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data Register" bitfld.long 0x00 31. " DR[31] ,Data bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,Data bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,Data bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,Data bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,Data bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,Data bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,Data bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,Data bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,Data bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,Data bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,Data bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,Data bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,Data bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,Data bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,Data bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,Data bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,Data bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,Data bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,Data bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,Data bit 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,Data bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,Data bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,Data bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,Data bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,Data bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,Data bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,Data bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,Data bit 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,Data bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,Data bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,Data bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,Data bit 0" "Low,High" line.long 0x04 "GDIR,GPIO Direction Register" bitfld.long 0x04 31. " GDIR[31] ,GPIO direction 31 bit" "Input,Output" bitfld.long 0x04 30. " [30] ,GPIO direction 30 bit" "Input,Output" bitfld.long 0x04 29. " [29] ,GPIO direction 29 bit" "Input,Output" bitfld.long 0x04 28. " [28] ,GPIO direction 28 bit" "Input,Output" newline bitfld.long 0x04 27. " [27] ,GPIO direction 27 bit" "Input,Output" bitfld.long 0x04 26. " [26] ,GPIO direction 26 bit" "Input,Output" bitfld.long 0x04 25. " [25] ,GPIO direction 25 bit" "Input,Output" bitfld.long 0x04 24. " [24] ,GPIO direction 24 bit" "Input,Output" newline bitfld.long 0x04 23. " [23] ,GPIO direction 23 bit" "Input,Output" bitfld.long 0x04 22. " [22] ,GPIO direction 22 bit" "Input,Output" bitfld.long 0x04 21. " [21] ,GPIO direction 21 bit" "Input,Output" bitfld.long 0x04 20. " [20] ,GPIO direction 20 bit" "Input,Output" newline bitfld.long 0x04 19. " [19] ,GPIO direction 19 bit" "Input,Output" bitfld.long 0x04 18. " [18] ,GPIO direction 18 bit" "Input,Output" bitfld.long 0x04 17. " [17] ,GPIO direction 17 bit" "Input,Output" bitfld.long 0x04 16. " [16] ,GPIO direction 16 bit" "Input,Output" newline bitfld.long 0x04 15. " [15] ,GPIO direction 15 bit" "Input,Output" bitfld.long 0x04 14. " [14] ,GPIO direction 14 bit" "Input,Output" bitfld.long 0x04 13. " [13] ,GPIO direction 13 bit" "Input,Output" bitfld.long 0x04 12. " [12] ,GPIO direction 12 bit" "Input,Output" newline bitfld.long 0x04 11. " [11] ,GPIO direction 11 bit" "Input,Output" bitfld.long 0x04 10. " [10] ,GPIO direction 10 bit" "Input,Output" bitfld.long 0x04 9. " [9] ,GPIO direction 9 bit" "Input,Output" bitfld.long 0x04 8. " [8] ,GPIO direction 8 bit" "Input,Output" newline bitfld.long 0x04 7. " [7] ,GPIO direction 7 bit" "Input,Output" bitfld.long 0x04 6. " [6] ,GPIO direction 6 bit" "Input,Output" bitfld.long 0x04 5. " [5] ,GPIO direction 5 bit" "Input,Output" bitfld.long 0x04 4. " [4] ,GPIO direction 4 bit" "Input,Output" newline bitfld.long 0x04 3. " [3] ,GPIO direction 3 bit" "Input,Output" bitfld.long 0x04 2. " [2] ,GPIO direction 2 bit" "Input,Output" bitfld.long 0x04 1. " [1] ,GPIO direction 1 bit" "Input,Output" bitfld.long 0x04 0. " [0] ,GPIO direction 0 bit" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO Pad Status Register" bitfld.long 0x00 31. " PSR[31] ,GPIO pad status bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,GPIO pad status bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,GPIO pad status bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,GPIO pad status bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,GPIO pad status bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,GPIO pad status bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,GPIO pad status bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,GPIO pad status bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,GPIO pad status bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,GPIO pad status bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,GPIO pad status bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,GPIO pad status bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,GPIO pad status bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,GPIO pad status bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,GPIO pad status bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,GPIO pad status bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,GPIO pad status bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,GPIO pad status bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,GPIO pad status bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,GPIO pad status bit 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,GPIO pad status bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,GPIO pad status bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,GPIO pad status bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,GPIO pad status bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,GPIO pad status bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,GPIO pad status bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,GPIO pad status bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,GPIO pad status bit 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,GPIO pad status bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,GPIO pad status bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,GPIO pad status bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,GPIO pad status bit 0" "Low,High" group.long 0x0C++0x13 line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1" bitfld.long 0x00 30.--31. " ICR[15] ,Controls the active condition of the interrupt function for GPIO interrupt 15" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 28.--29. " [14] ,Controls the active condition of the interrupt function for GPIO interrupt 14" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 26.--27. " [13] ,Controls the active condition of the interrupt function for GPIO interrupt 13" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 24.--25. " [12] ,Controls the active condition of the interrupt function for GPIO interrupt 12" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 22.--23. " [11] ,Controls the active condition of the interrupt function for GPIO interrupt 11" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 20.--21. " [10] ,Controls the active condition of the interrupt function for GPIO interrupt 10" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 18.--19. " [9] ,Controls the active condition of the interrupt function for GPIO interrupt 9" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 16.--17. " [8] ,Controls the active condition of the interrupt function for GPIO interrupt 8" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 14.--15. " [7] ,Controls the active condition of the interrupt function for GPIO interrupt 7" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 12.--13. " [6] ,Controls the active condition of the interrupt function for GPIO interrupt 6" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 10.--11. " [5] ,Controls the active condition of the interrupt function for GPIO interrupt 5" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 8.--9. " [4] ,Controls the active condition of the interrupt function for GPIO interrupt 4" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 6.--7. " [3] ,Controls the active condition of the interrupt function for GPIO interrupt 3" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 4.--5. " [2] ,Controls the active condition of the interrupt function for GPIO interrupt 2" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 2.--3. " [1] ,Controls the active condition of the interrupt function for GPIO interrupt 1" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 0.--1. " [0] ,Controls the active condition of the interrupt function for GPIO interrupt 0" "Low-level,High-level,Rising-edge,Falling-edge" line.long 0x04 "ICR2,GPIO Interrupt Configuration Register 2" bitfld.long 0x04 30.--31. " [31] ,Controls the active condition of the interrupt function for GPIO interrupt 31" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 28.--29. " [30] ,Controls the active condition of the interrupt function for GPIO interrupt 30" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 26.--27. " [29] ,Controls the active condition of the interrupt function for GPIO interrupt 29" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 24.--25. " [28] ,Controls the active condition of the interrupt function for GPIO interrupt 28" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 22.--23. " [27] ,Controls the active condition of the interrupt function for GPIO interrupt 27" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 20.--21. " [26] ,Controls the active condition of the interrupt function for GPIO interrupt 26" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 18.--19. " [25] ,Controls the active condition of the interrupt function for GPIO interrupt 25" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 16.--17. " [24] ,Controls the active condition of the interrupt function for GPIO interrupt 24" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 14.--15. " [23] ,Controls the active condition of the interrupt function for GPIO interrupt 23" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 12.--13. " [22] ,Controls the active condition of the interrupt function for GPIO interrupt 22" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 10.--11. " [21] ,Controls the active condition of the interrupt function for GPIO interrupt 21" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 8.--9. " [20] ,Controls the active condition of the interrupt function for GPIO interrupt 20" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 6.--7. " [19] ,Controls the active condition of the interrupt function for GPIO interrupt 19" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 4.--5. " [18] ,Controls the active condition of the interrupt function for GPIO interrupt 18" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 2.--3. " [17] ,Controls the active condition of the interrupt function for GPIO interrupt 17" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 0.--1. " [16] ,Controls the active condition of the interrupt function for GPIO interrupt 16" "Low-level,High-level,Rising-edge,Falling-edge" line.long 0x08 "IMR,GPIO Interrupt Mask Register" bitfld.long 0x08 31. " IMR[31] ,Interrupt 31 mask bit" "Disabled,Enabled" bitfld.long 0x08 30. " [30] ,Interrupt 30 mask bit" "Disabled,Enabled" bitfld.long 0x08 29. " [29] ,Interrupt 29 mask bit" "Disabled,Enabled" bitfld.long 0x08 28. " [28] ,Interrupt 28 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 27. " [27] ,Interrupt 27 mask bit" "Disabled,Enabled" bitfld.long 0x08 26. " [26] ,Interrupt 26 mask bit" "Disabled,Enabled" bitfld.long 0x08 25. " [25] ,Interrupt 25 mask bit" "Disabled,Enabled" bitfld.long 0x08 24. " [24] ,Interrupt 24 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 23. " [23] ,Interrupt 23 mask bit" "Disabled,Enabled" bitfld.long 0x08 22. " [22] ,Interrupt 22 mask bit" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Interrupt 21 mask bit" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Interrupt 20 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 19. " [19] ,Interrupt 19 mask bit" "Disabled,Enabled" bitfld.long 0x08 18. " [18] ,Interrupt 18 mask bit" "Disabled,Enabled" bitfld.long 0x08 17. " [17] ,Interrupt 17 mask bit" "Disabled,Enabled" bitfld.long 0x08 16. " [16] ,Interrupt 16 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 15. " [15] ,Interrupt 15 mask bit" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Interrupt 14 mask bit" "Disabled,Enabled" bitfld.long 0x08 13. " [13] ,Interrupt 13 mask bit" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Interrupt 12 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 11. " [11] ,Interrupt 11 mask bit" "Disabled,Enabled" bitfld.long 0x08 10. " [10] ,Interrupt 10 mask bit" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Interrupt 9 mask bit" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Interrupt 8 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Interrupt 7 mask bit" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Interrupt 6 mask bit" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Interrupt 5 mask bit" "Disabled,Enabled" bitfld.long 0x08 4. " [4] ,Interrupt 4 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 3. " [3] ,Interrupt 3 mask bit" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Interrupt 2 mask bit" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Interrupt 1 mask bit" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Interrupt 0 mask bit" "Disabled,Enabled" line.long 0x0C "ISR,GPIO Interrupt Status Register" eventfld.long 0x0C 31. " ISR[31] ,Interrupt 31 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 30. " [30] ,Interrupt 30 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 29. " [29] ,Interrupt 29 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 28. " [28] ,Interrupt 28 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 27. " [27] ,Interrupt 27 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 26. " [26] ,Interrupt 26 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 25. " [25] ,Interrupt 25 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 24. " [24] ,Interrupt 24 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 23. " [23] ,Interrupt 23 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 22. " [22] ,Interrupt 22 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 21. " [21] ,Interrupt 21 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 20. " [20] ,Interrupt 20 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 19. " [19] ,Interrupt 19 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 18. " [18] ,Interrupt 18 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 17. " [17] ,Interrupt 17 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 16. " [16] ,Interrupt 16 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 15. " [15] ,Interrupt 15 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 14. " [14] ,Interrupt 14 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 13. " [13] ,Interrupt 13 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 12. " [12] ,Interrupt 12 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 11. " [11] ,Interrupt 11 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 10. " [10] ,Interrupt 10 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 9. " [9] ,Interrupt 9 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 8. " [8] ,Interrupt 8 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 7. " [7] ,Interrupt 7 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 6. " [6] ,Interrupt 6 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 5. " [5] ,Interrupt 5 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 4. " [4] ,Interrupt 4 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 3. " [3] ,Interrupt 3 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 2. " [2] ,Interrupt 2 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 1. " [1] ,Interrupt 1 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 0. " [0] ,Interrupt 0 status bit" "No interrupt,Interrupt" line.long 0x10 "EDGE_SEL,GPIO Edge Select Register" bitfld.long 0x10 31. " GPIO_EDGE_SEL[31] ,Edge select bit 31" "31 setting,Any edge" bitfld.long 0x10 30. " [30] ,Edge select bit 30" "30 setting,Any edge" bitfld.long 0x10 29. " [29] ,Edge select bit 29" "29 setting,Any edge" bitfld.long 0x10 28. " [28] ,Edge select bit 28" "28 setting,Any edge" newline bitfld.long 0x10 27. " [27] ,Edge select bit 27" "27 setting,Any edge" bitfld.long 0x10 26. " [26] ,Edge select bit 26" "26 setting,Any edge" bitfld.long 0x10 25. " [25] ,Edge select bit 25" "25 setting,Any edge" bitfld.long 0x10 24. " [24] ,Edge select bit 24" "24 setting,Any edge" newline bitfld.long 0x10 23. " [23] ,Edge select bit 23" "23 setting,Any edge" bitfld.long 0x10 22. " [22] ,Edge select bit 22" "22 setting,Any edge" bitfld.long 0x10 21. " [21] ,Edge select bit 21" "21 setting,Any edge" bitfld.long 0x10 20. " [20] ,Edge select bit 20" "20 setting,Any edge" newline bitfld.long 0x10 19. " [19] ,Edge select bit 19" "19 setting,Any edge" bitfld.long 0x10 18. " [18] ,Edge select bit 18" "18 setting,Any edge" bitfld.long 0x10 17. " [17] ,Edge select bit 17" "17 setting,Any edge" bitfld.long 0x10 16. " [16] ,Edge select bit 16" "16 setting,Any edge" newline bitfld.long 0x10 15. " [15] ,Edge select bit 15" "15 setting,Any edge" bitfld.long 0x10 14. " [14] ,Edge select bit 14" "14 setting,Any edge" bitfld.long 0x10 13. " [13] ,Edge select bit 13" "13 setting,Any edge" bitfld.long 0x10 12. " [12] ,Edge select bit 12" "12 setting,Any edge" newline bitfld.long 0x10 11. " [11] ,Edge select bit 11" "11 setting,Any edge" bitfld.long 0x10 10. " [10] ,Edge select bit 10" "10 setting,Any edge" bitfld.long 0x10 9. " [9] ,Edge select bit 9" "9 setting,Any edge" bitfld.long 0x10 8. " [8] ,Edge select bit 8" "8 setting,Any edge" newline bitfld.long 0x10 7. " [7] ,Edge select bit 7" "7 setting,Any edge" bitfld.long 0x10 6. " [6] ,Edge select bit 6" "6 setting,Any edge" bitfld.long 0x10 5. " [5] ,Edge select bit 5" "5 setting,Any edge" bitfld.long 0x10 4. " [4] ,Edge select bit 4" "4 setting,Any edge" newline bitfld.long 0x10 3. " [3] ,Edge select bit 3" "3 setting,Any edge" bitfld.long 0x10 2. " [2] ,Edge select bit 2" "2 setting,Any edge" bitfld.long 0x10 1. " [1] ,Edge select bit 1" "1 setting,Any edge" bitfld.long 0x10 0. " [0] ,Edge select bit 0" "0 setting,Any edge" wgroup.long 0x84++0x0B line.long 0x00 "DR_SET,GPIO Data Register SET Register" bitfld.long 0x00 31. " DR_SET[31] ,Data bit 31 set" "Not set,Set" bitfld.long 0x00 30. " [30] ,Data bit 30 set" "Not set,Set" bitfld.long 0x00 29. " [29] ,Data bit 29 set" "Not set,Set" bitfld.long 0x00 28. " [28] ,Data bit 28 set" "Not set,Set" newline bitfld.long 0x00 27. " [27] ,Data bit 27 set" "Not set,Set" bitfld.long 0x00 26. " [26] ,Data bit 26 set" "Not set,Set" bitfld.long 0x00 25. " [25] ,Data bit 25 set" "Not set,Set" bitfld.long 0x00 24. " [24] ,Data bit 24 set" "Not set,Set" newline bitfld.long 0x00 23. " [23] ,Data bit 23 set" "Not set,Set" bitfld.long 0x00 22. " [22] ,Data bit 22 set" "Not set,Set" bitfld.long 0x00 21. " [21] ,Data bit 21 set" "Not set,Set" bitfld.long 0x00 20. " [20] ,Data bit 20 set" "Not set,Set" newline bitfld.long 0x00 19. " [19] ,Data bit 19 set" "Not set,Set" bitfld.long 0x00 18. " [18] ,Data bit 18 set" "Not set,Set" bitfld.long 0x00 17. " [17] ,Data bit 17 set" "Not set,Set" bitfld.long 0x00 16. " [16] ,Data bit 16 set" "Not set,Set" newline bitfld.long 0x00 15. " [15] ,Data bit 15 set" "Not set,Set" bitfld.long 0x00 14. " [14] ,Data bit 14 set" "Not set,Set" bitfld.long 0x00 13. " [13] ,Data bit 13 set" "Not set,Set" bitfld.long 0x00 12. " [12] ,Data bit 12 set" "Not set,Set" newline bitfld.long 0x00 11. " [11] ,Data bit 11 set" "Not set,Set" bitfld.long 0x00 10. " [10] ,Data bit 10 set" "Not set,Set" bitfld.long 0x00 9. " [9] ,Data bit 9 set" "Not set,Set" bitfld.long 0x00 8. " [8] ,Data bit 8 set" "Not set,Set" newline bitfld.long 0x00 7. " [7] ,Data bit 7 set" "Not set,Set" bitfld.long 0x00 6. " [6] ,Data bit 6 set" "Not set,Set" bitfld.long 0x00 5. " [5] ,Data bit 5 set" "Not set,Set" bitfld.long 0x00 4. " [4] ,Data bit 4 set" "Not set,Set" newline bitfld.long 0x00 3. " [3] ,Data bit 3 set" "Not set,Set" bitfld.long 0x00 2. " [2] ,Data bit 2 set" "Not set,Set" bitfld.long 0x00 1. " [1] ,Data bit 1 set" "Not set,Set" bitfld.long 0x00 0. " [0] ,Data bit 0 set" "Not set,Set" line.long 0x04 "DR_CLEAR,GPIO Data Register CLEAR Register" bitfld.long 0x04 31. " DR_CLEAR[31] ,Data bit 31 clear" "No effect,Clear" bitfld.long 0x04 30. " [30] ,Data bit 30 clear" "No effect,Clear" bitfld.long 0x04 29. " [29] ,Data bit 29 clear" "No effect,Clear" bitfld.long 0x04 28. " [28] ,Data bit 28 clear" "No effect,Clear" newline bitfld.long 0x04 27. " [27] ,Data bit 27 clear" "No effect,Clear" bitfld.long 0x04 26. " [26] ,Data bit 26 clear" "No effect,Clear" bitfld.long 0x04 25. " [25] ,Data bit 25 clear" "No effect,Clear" bitfld.long 0x04 24. " [24] ,Data bit 24 clear" "No effect,Clear" newline bitfld.long 0x04 23. " [23] ,Data bit 23 clear" "No effect,Clear" bitfld.long 0x04 22. " [22] ,Data bit 22 clear" "No effect,Clear" bitfld.long 0x04 21. " [21] ,Data bit 21 clear" "No effect,Clear" bitfld.long 0x04 20. " [20] ,Data bit 20 clear" "No effect,Clear" newline bitfld.long 0x04 19. " [19] ,Data bit 19 clear" "No effect,Clear" bitfld.long 0x04 18. " [18] ,Data bit 18 clear" "No effect,Clear" bitfld.long 0x04 17. " [17] ,Data bit 17 clear" "No effect,Clear" bitfld.long 0x04 16. " [16] ,Data bit 16 clear" "No effect,Clear" newline bitfld.long 0x04 15. " [15] ,Data bit 15 clear" "No effect,Clear" bitfld.long 0x04 14. " [14] ,Data bit 14 clear" "No effect,Clear" bitfld.long 0x04 13. " [13] ,Data bit 13 clear" "No effect,Clear" bitfld.long 0x04 12. " [12] ,Data bit 12 clear" "No effect,Clear" newline bitfld.long 0x04 11. " [11] ,Data bit 11 clear" "No effect,Clear" bitfld.long 0x04 10. " [10] ,Data bit 10 clear" "No effect,Clear" bitfld.long 0x04 9. " [9] ,Data bit 9 clear" "No effect,Clear" bitfld.long 0x04 8. " [8] ,Data bit 8 clear" "No effect,Clear" newline bitfld.long 0x04 7. " [7] ,Data bit 7 clear" "No effect,Clear" bitfld.long 0x04 6. " [6] ,Data bit 6 clear" "No effect,Clear" bitfld.long 0x04 5. " [5] ,Data bit 5 clear" "No effect,Clear" bitfld.long 0x04 4. " [4] ,Data bit 4 clear" "No effect,Clear" newline bitfld.long 0x04 3. " [3] ,Data bit 3 clear" "No effect,Clear" bitfld.long 0x04 2. " [2] ,Data bit 2 clear" "No effect,Clear" bitfld.long 0x04 1. " [1] ,Data bit 1 clear" "No effect,Clear" bitfld.long 0x04 0. " [0] ,Data bit 0 clear" "No effect,Clear" line.long 0x08 "DR_TOGGLE,GPIO Data Register TOGGLE Register" bitfld.long 0x08 31. " DR_TOGGLE[31] ,Data bit 31 toggle" "Not toggled,Toggled" bitfld.long 0x08 30. " [30] ,Data bit 30 toggle" "No effect,Clear" bitfld.long 0x08 29. " [29] ,Data bit 29 toggle" "Not toggled,Toggled" bitfld.long 0x08 28. " [28] ,Data bit 28 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 27. " [27] ,Data bit 27 toggle" "Not toggled,Toggled" bitfld.long 0x08 26. " [26] ,Data bit 26 toggle" "Not toggled,Toggled" bitfld.long 0x08 25. " [25] ,Data bit 25 toggle" "Not toggled,Toggled" bitfld.long 0x08 24. " [24] ,Data bit 24 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 23. " [23] ,Data bit 23 toggle" "Not toggled,Toggled" bitfld.long 0x08 22. " [22] ,Data bit 22 toggle" "Not toggled,Toggled" bitfld.long 0x08 21. " [21] ,Data bit 21 toggle" "Not toggled,Toggled" bitfld.long 0x08 20. " [20] ,Data bit 20 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 19. " [19] ,Data bit 19 toggle" "Not toggled,Toggled" bitfld.long 0x08 18. " [18] ,Data bit 18 toggle" "Not toggled,Toggled" bitfld.long 0x08 17. " [17] ,Data bit 17 toggle" "Not toggled,Toggled" bitfld.long 0x08 16. " [16] ,Data bit 16 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 15. " [15] ,Data bit 15 toggle" "Not toggled,Toggled" bitfld.long 0x08 14. " [14] ,Data bit 14 toggle" "Not toggled,Toggled" bitfld.long 0x08 13. " [13] ,Data bit 13 toggle" "Not toggled,Toggled" bitfld.long 0x08 12. " [12] ,Data bit 12 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 11. " [11] ,Data bit 11 toggle" "Not toggled,Toggled" bitfld.long 0x08 10. " [10] ,Data bit 10 toggle" "Not toggled,Toggled" bitfld.long 0x08 9. " [9] ,Data bit 9 toggle" "Not toggled,Toggled" bitfld.long 0x08 8. " [8] ,Data bit 8 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 7. " [7] ,Data bit 7 toggle" "Not toggled,Toggled" bitfld.long 0x08 6. " [6] ,Data bit 6 toggle" "Not toggled,Toggled" bitfld.long 0x08 5. " [5] ,Data bit 5 toggle" "Not toggled,Toggled" bitfld.long 0x08 4. " [4] ,Data bit 4 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 3. " [3] ,Data bit 3 toggle" "Not toggled,Toggled" bitfld.long 0x08 2. " [2] ,Data bit 2 toggle" "Not toggled,Toggled" bitfld.long 0x08 1. " [1] ,Data bit 1 toggle" "Not toggled,Toggled" bitfld.long 0x08 0. " [0] ,Data bit 0 toggle" "Not toggled,Toggled" width 0x0B tree.end tree "GPIO7" base ad:0x5D0F0000 width 11. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data Register" bitfld.long 0x00 31. " DR[31] ,Data bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,Data bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,Data bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,Data bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,Data bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,Data bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,Data bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,Data bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,Data bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,Data bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,Data bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,Data bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,Data bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,Data bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,Data bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,Data bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,Data bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,Data bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,Data bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,Data bit 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,Data bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,Data bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,Data bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,Data bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,Data bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,Data bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,Data bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,Data bit 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,Data bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,Data bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,Data bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,Data bit 0" "Low,High" line.long 0x04 "GDIR,GPIO Direction Register" bitfld.long 0x04 31. " GDIR[31] ,GPIO direction 31 bit" "Input,Output" bitfld.long 0x04 30. " [30] ,GPIO direction 30 bit" "Input,Output" bitfld.long 0x04 29. " [29] ,GPIO direction 29 bit" "Input,Output" bitfld.long 0x04 28. " [28] ,GPIO direction 28 bit" "Input,Output" newline bitfld.long 0x04 27. " [27] ,GPIO direction 27 bit" "Input,Output" bitfld.long 0x04 26. " [26] ,GPIO direction 26 bit" "Input,Output" bitfld.long 0x04 25. " [25] ,GPIO direction 25 bit" "Input,Output" bitfld.long 0x04 24. " [24] ,GPIO direction 24 bit" "Input,Output" newline bitfld.long 0x04 23. " [23] ,GPIO direction 23 bit" "Input,Output" bitfld.long 0x04 22. " [22] ,GPIO direction 22 bit" "Input,Output" bitfld.long 0x04 21. " [21] ,GPIO direction 21 bit" "Input,Output" bitfld.long 0x04 20. " [20] ,GPIO direction 20 bit" "Input,Output" newline bitfld.long 0x04 19. " [19] ,GPIO direction 19 bit" "Input,Output" bitfld.long 0x04 18. " [18] ,GPIO direction 18 bit" "Input,Output" bitfld.long 0x04 17. " [17] ,GPIO direction 17 bit" "Input,Output" bitfld.long 0x04 16. " [16] ,GPIO direction 16 bit" "Input,Output" newline bitfld.long 0x04 15. " [15] ,GPIO direction 15 bit" "Input,Output" bitfld.long 0x04 14. " [14] ,GPIO direction 14 bit" "Input,Output" bitfld.long 0x04 13. " [13] ,GPIO direction 13 bit" "Input,Output" bitfld.long 0x04 12. " [12] ,GPIO direction 12 bit" "Input,Output" newline bitfld.long 0x04 11. " [11] ,GPIO direction 11 bit" "Input,Output" bitfld.long 0x04 10. " [10] ,GPIO direction 10 bit" "Input,Output" bitfld.long 0x04 9. " [9] ,GPIO direction 9 bit" "Input,Output" bitfld.long 0x04 8. " [8] ,GPIO direction 8 bit" "Input,Output" newline bitfld.long 0x04 7. " [7] ,GPIO direction 7 bit" "Input,Output" bitfld.long 0x04 6. " [6] ,GPIO direction 6 bit" "Input,Output" bitfld.long 0x04 5. " [5] ,GPIO direction 5 bit" "Input,Output" bitfld.long 0x04 4. " [4] ,GPIO direction 4 bit" "Input,Output" newline bitfld.long 0x04 3. " [3] ,GPIO direction 3 bit" "Input,Output" bitfld.long 0x04 2. " [2] ,GPIO direction 2 bit" "Input,Output" bitfld.long 0x04 1. " [1] ,GPIO direction 1 bit" "Input,Output" bitfld.long 0x04 0. " [0] ,GPIO direction 0 bit" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO Pad Status Register" bitfld.long 0x00 31. " PSR[31] ,GPIO pad status bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,GPIO pad status bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,GPIO pad status bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,GPIO pad status bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,GPIO pad status bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,GPIO pad status bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,GPIO pad status bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,GPIO pad status bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,GPIO pad status bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,GPIO pad status bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,GPIO pad status bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,GPIO pad status bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,GPIO pad status bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,GPIO pad status bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,GPIO pad status bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,GPIO pad status bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,GPIO pad status bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,GPIO pad status bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,GPIO pad status bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,GPIO pad status bit 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,GPIO pad status bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,GPIO pad status bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,GPIO pad status bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,GPIO pad status bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,GPIO pad status bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,GPIO pad status bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,GPIO pad status bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,GPIO pad status bit 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,GPIO pad status bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,GPIO pad status bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,GPIO pad status bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,GPIO pad status bit 0" "Low,High" group.long 0x0C++0x13 line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1" bitfld.long 0x00 30.--31. " ICR[15] ,Controls the active condition of the interrupt function for GPIO interrupt 15" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 28.--29. " [14] ,Controls the active condition of the interrupt function for GPIO interrupt 14" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 26.--27. " [13] ,Controls the active condition of the interrupt function for GPIO interrupt 13" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 24.--25. " [12] ,Controls the active condition of the interrupt function for GPIO interrupt 12" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 22.--23. " [11] ,Controls the active condition of the interrupt function for GPIO interrupt 11" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 20.--21. " [10] ,Controls the active condition of the interrupt function for GPIO interrupt 10" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 18.--19. " [9] ,Controls the active condition of the interrupt function for GPIO interrupt 9" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 16.--17. " [8] ,Controls the active condition of the interrupt function for GPIO interrupt 8" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 14.--15. " [7] ,Controls the active condition of the interrupt function for GPIO interrupt 7" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 12.--13. " [6] ,Controls the active condition of the interrupt function for GPIO interrupt 6" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 10.--11. " [5] ,Controls the active condition of the interrupt function for GPIO interrupt 5" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 8.--9. " [4] ,Controls the active condition of the interrupt function for GPIO interrupt 4" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 6.--7. " [3] ,Controls the active condition of the interrupt function for GPIO interrupt 3" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 4.--5. " [2] ,Controls the active condition of the interrupt function for GPIO interrupt 2" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 2.--3. " [1] ,Controls the active condition of the interrupt function for GPIO interrupt 1" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 0.--1. " [0] ,Controls the active condition of the interrupt function for GPIO interrupt 0" "Low-level,High-level,Rising-edge,Falling-edge" line.long 0x04 "ICR2,GPIO Interrupt Configuration Register 2" bitfld.long 0x04 30.--31. " [31] ,Controls the active condition of the interrupt function for GPIO interrupt 31" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 28.--29. " [30] ,Controls the active condition of the interrupt function for GPIO interrupt 30" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 26.--27. " [29] ,Controls the active condition of the interrupt function for GPIO interrupt 29" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 24.--25. " [28] ,Controls the active condition of the interrupt function for GPIO interrupt 28" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 22.--23. " [27] ,Controls the active condition of the interrupt function for GPIO interrupt 27" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 20.--21. " [26] ,Controls the active condition of the interrupt function for GPIO interrupt 26" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 18.--19. " [25] ,Controls the active condition of the interrupt function for GPIO interrupt 25" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 16.--17. " [24] ,Controls the active condition of the interrupt function for GPIO interrupt 24" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 14.--15. " [23] ,Controls the active condition of the interrupt function for GPIO interrupt 23" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 12.--13. " [22] ,Controls the active condition of the interrupt function for GPIO interrupt 22" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 10.--11. " [21] ,Controls the active condition of the interrupt function for GPIO interrupt 21" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 8.--9. " [20] ,Controls the active condition of the interrupt function for GPIO interrupt 20" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 6.--7. " [19] ,Controls the active condition of the interrupt function for GPIO interrupt 19" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 4.--5. " [18] ,Controls the active condition of the interrupt function for GPIO interrupt 18" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 2.--3. " [17] ,Controls the active condition of the interrupt function for GPIO interrupt 17" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 0.--1. " [16] ,Controls the active condition of the interrupt function for GPIO interrupt 16" "Low-level,High-level,Rising-edge,Falling-edge" line.long 0x08 "IMR,GPIO Interrupt Mask Register" bitfld.long 0x08 31. " IMR[31] ,Interrupt 31 mask bit" "Disabled,Enabled" bitfld.long 0x08 30. " [30] ,Interrupt 30 mask bit" "Disabled,Enabled" bitfld.long 0x08 29. " [29] ,Interrupt 29 mask bit" "Disabled,Enabled" bitfld.long 0x08 28. " [28] ,Interrupt 28 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 27. " [27] ,Interrupt 27 mask bit" "Disabled,Enabled" bitfld.long 0x08 26. " [26] ,Interrupt 26 mask bit" "Disabled,Enabled" bitfld.long 0x08 25. " [25] ,Interrupt 25 mask bit" "Disabled,Enabled" bitfld.long 0x08 24. " [24] ,Interrupt 24 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 23. " [23] ,Interrupt 23 mask bit" "Disabled,Enabled" bitfld.long 0x08 22. " [22] ,Interrupt 22 mask bit" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Interrupt 21 mask bit" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Interrupt 20 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 19. " [19] ,Interrupt 19 mask bit" "Disabled,Enabled" bitfld.long 0x08 18. " [18] ,Interrupt 18 mask bit" "Disabled,Enabled" bitfld.long 0x08 17. " [17] ,Interrupt 17 mask bit" "Disabled,Enabled" bitfld.long 0x08 16. " [16] ,Interrupt 16 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 15. " [15] ,Interrupt 15 mask bit" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Interrupt 14 mask bit" "Disabled,Enabled" bitfld.long 0x08 13. " [13] ,Interrupt 13 mask bit" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Interrupt 12 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 11. " [11] ,Interrupt 11 mask bit" "Disabled,Enabled" bitfld.long 0x08 10. " [10] ,Interrupt 10 mask bit" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Interrupt 9 mask bit" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Interrupt 8 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Interrupt 7 mask bit" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Interrupt 6 mask bit" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Interrupt 5 mask bit" "Disabled,Enabled" bitfld.long 0x08 4. " [4] ,Interrupt 4 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 3. " [3] ,Interrupt 3 mask bit" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Interrupt 2 mask bit" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Interrupt 1 mask bit" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Interrupt 0 mask bit" "Disabled,Enabled" line.long 0x0C "ISR,GPIO Interrupt Status Register" eventfld.long 0x0C 31. " ISR[31] ,Interrupt 31 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 30. " [30] ,Interrupt 30 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 29. " [29] ,Interrupt 29 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 28. " [28] ,Interrupt 28 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 27. " [27] ,Interrupt 27 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 26. " [26] ,Interrupt 26 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 25. " [25] ,Interrupt 25 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 24. " [24] ,Interrupt 24 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 23. " [23] ,Interrupt 23 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 22. " [22] ,Interrupt 22 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 21. " [21] ,Interrupt 21 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 20. " [20] ,Interrupt 20 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 19. " [19] ,Interrupt 19 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 18. " [18] ,Interrupt 18 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 17. " [17] ,Interrupt 17 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 16. " [16] ,Interrupt 16 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 15. " [15] ,Interrupt 15 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 14. " [14] ,Interrupt 14 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 13. " [13] ,Interrupt 13 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 12. " [12] ,Interrupt 12 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 11. " [11] ,Interrupt 11 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 10. " [10] ,Interrupt 10 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 9. " [9] ,Interrupt 9 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 8. " [8] ,Interrupt 8 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 7. " [7] ,Interrupt 7 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 6. " [6] ,Interrupt 6 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 5. " [5] ,Interrupt 5 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 4. " [4] ,Interrupt 4 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 3. " [3] ,Interrupt 3 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 2. " [2] ,Interrupt 2 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 1. " [1] ,Interrupt 1 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 0. " [0] ,Interrupt 0 status bit" "No interrupt,Interrupt" line.long 0x10 "EDGE_SEL,GPIO Edge Select Register" bitfld.long 0x10 31. " GPIO_EDGE_SEL[31] ,Edge select bit 31" "31 setting,Any edge" bitfld.long 0x10 30. " [30] ,Edge select bit 30" "30 setting,Any edge" bitfld.long 0x10 29. " [29] ,Edge select bit 29" "29 setting,Any edge" bitfld.long 0x10 28. " [28] ,Edge select bit 28" "28 setting,Any edge" newline bitfld.long 0x10 27. " [27] ,Edge select bit 27" "27 setting,Any edge" bitfld.long 0x10 26. " [26] ,Edge select bit 26" "26 setting,Any edge" bitfld.long 0x10 25. " [25] ,Edge select bit 25" "25 setting,Any edge" bitfld.long 0x10 24. " [24] ,Edge select bit 24" "24 setting,Any edge" newline bitfld.long 0x10 23. " [23] ,Edge select bit 23" "23 setting,Any edge" bitfld.long 0x10 22. " [22] ,Edge select bit 22" "22 setting,Any edge" bitfld.long 0x10 21. " [21] ,Edge select bit 21" "21 setting,Any edge" bitfld.long 0x10 20. " [20] ,Edge select bit 20" "20 setting,Any edge" newline bitfld.long 0x10 19. " [19] ,Edge select bit 19" "19 setting,Any edge" bitfld.long 0x10 18. " [18] ,Edge select bit 18" "18 setting,Any edge" bitfld.long 0x10 17. " [17] ,Edge select bit 17" "17 setting,Any edge" bitfld.long 0x10 16. " [16] ,Edge select bit 16" "16 setting,Any edge" newline bitfld.long 0x10 15. " [15] ,Edge select bit 15" "15 setting,Any edge" bitfld.long 0x10 14. " [14] ,Edge select bit 14" "14 setting,Any edge" bitfld.long 0x10 13. " [13] ,Edge select bit 13" "13 setting,Any edge" bitfld.long 0x10 12. " [12] ,Edge select bit 12" "12 setting,Any edge" newline bitfld.long 0x10 11. " [11] ,Edge select bit 11" "11 setting,Any edge" bitfld.long 0x10 10. " [10] ,Edge select bit 10" "10 setting,Any edge" bitfld.long 0x10 9. " [9] ,Edge select bit 9" "9 setting,Any edge" bitfld.long 0x10 8. " [8] ,Edge select bit 8" "8 setting,Any edge" newline bitfld.long 0x10 7. " [7] ,Edge select bit 7" "7 setting,Any edge" bitfld.long 0x10 6. " [6] ,Edge select bit 6" "6 setting,Any edge" bitfld.long 0x10 5. " [5] ,Edge select bit 5" "5 setting,Any edge" bitfld.long 0x10 4. " [4] ,Edge select bit 4" "4 setting,Any edge" newline bitfld.long 0x10 3. " [3] ,Edge select bit 3" "3 setting,Any edge" bitfld.long 0x10 2. " [2] ,Edge select bit 2" "2 setting,Any edge" bitfld.long 0x10 1. " [1] ,Edge select bit 1" "1 setting,Any edge" bitfld.long 0x10 0. " [0] ,Edge select bit 0" "0 setting,Any edge" wgroup.long 0x84++0x0B line.long 0x00 "DR_SET,GPIO Data Register SET Register" bitfld.long 0x00 31. " DR_SET[31] ,Data bit 31 set" "Not set,Set" bitfld.long 0x00 30. " [30] ,Data bit 30 set" "Not set,Set" bitfld.long 0x00 29. " [29] ,Data bit 29 set" "Not set,Set" bitfld.long 0x00 28. " [28] ,Data bit 28 set" "Not set,Set" newline bitfld.long 0x00 27. " [27] ,Data bit 27 set" "Not set,Set" bitfld.long 0x00 26. " [26] ,Data bit 26 set" "Not set,Set" bitfld.long 0x00 25. " [25] ,Data bit 25 set" "Not set,Set" bitfld.long 0x00 24. " [24] ,Data bit 24 set" "Not set,Set" newline bitfld.long 0x00 23. " [23] ,Data bit 23 set" "Not set,Set" bitfld.long 0x00 22. " [22] ,Data bit 22 set" "Not set,Set" bitfld.long 0x00 21. " [21] ,Data bit 21 set" "Not set,Set" bitfld.long 0x00 20. " [20] ,Data bit 20 set" "Not set,Set" newline bitfld.long 0x00 19. " [19] ,Data bit 19 set" "Not set,Set" bitfld.long 0x00 18. " [18] ,Data bit 18 set" "Not set,Set" bitfld.long 0x00 17. " [17] ,Data bit 17 set" "Not set,Set" bitfld.long 0x00 16. " [16] ,Data bit 16 set" "Not set,Set" newline bitfld.long 0x00 15. " [15] ,Data bit 15 set" "Not set,Set" bitfld.long 0x00 14. " [14] ,Data bit 14 set" "Not set,Set" bitfld.long 0x00 13. " [13] ,Data bit 13 set" "Not set,Set" bitfld.long 0x00 12. " [12] ,Data bit 12 set" "Not set,Set" newline bitfld.long 0x00 11. " [11] ,Data bit 11 set" "Not set,Set" bitfld.long 0x00 10. " [10] ,Data bit 10 set" "Not set,Set" bitfld.long 0x00 9. " [9] ,Data bit 9 set" "Not set,Set" bitfld.long 0x00 8. " [8] ,Data bit 8 set" "Not set,Set" newline bitfld.long 0x00 7. " [7] ,Data bit 7 set" "Not set,Set" bitfld.long 0x00 6. " [6] ,Data bit 6 set" "Not set,Set" bitfld.long 0x00 5. " [5] ,Data bit 5 set" "Not set,Set" bitfld.long 0x00 4. " [4] ,Data bit 4 set" "Not set,Set" newline bitfld.long 0x00 3. " [3] ,Data bit 3 set" "Not set,Set" bitfld.long 0x00 2. " [2] ,Data bit 2 set" "Not set,Set" bitfld.long 0x00 1. " [1] ,Data bit 1 set" "Not set,Set" bitfld.long 0x00 0. " [0] ,Data bit 0 set" "Not set,Set" line.long 0x04 "DR_CLEAR,GPIO Data Register CLEAR Register" bitfld.long 0x04 31. " DR_CLEAR[31] ,Data bit 31 clear" "No effect,Clear" bitfld.long 0x04 30. " [30] ,Data bit 30 clear" "No effect,Clear" bitfld.long 0x04 29. " [29] ,Data bit 29 clear" "No effect,Clear" bitfld.long 0x04 28. " [28] ,Data bit 28 clear" "No effect,Clear" newline bitfld.long 0x04 27. " [27] ,Data bit 27 clear" "No effect,Clear" bitfld.long 0x04 26. " [26] ,Data bit 26 clear" "No effect,Clear" bitfld.long 0x04 25. " [25] ,Data bit 25 clear" "No effect,Clear" bitfld.long 0x04 24. " [24] ,Data bit 24 clear" "No effect,Clear" newline bitfld.long 0x04 23. " [23] ,Data bit 23 clear" "No effect,Clear" bitfld.long 0x04 22. " [22] ,Data bit 22 clear" "No effect,Clear" bitfld.long 0x04 21. " [21] ,Data bit 21 clear" "No effect,Clear" bitfld.long 0x04 20. " [20] ,Data bit 20 clear" "No effect,Clear" newline bitfld.long 0x04 19. " [19] ,Data bit 19 clear" "No effect,Clear" bitfld.long 0x04 18. " [18] ,Data bit 18 clear" "No effect,Clear" bitfld.long 0x04 17. " [17] ,Data bit 17 clear" "No effect,Clear" bitfld.long 0x04 16. " [16] ,Data bit 16 clear" "No effect,Clear" newline bitfld.long 0x04 15. " [15] ,Data bit 15 clear" "No effect,Clear" bitfld.long 0x04 14. " [14] ,Data bit 14 clear" "No effect,Clear" bitfld.long 0x04 13. " [13] ,Data bit 13 clear" "No effect,Clear" bitfld.long 0x04 12. " [12] ,Data bit 12 clear" "No effect,Clear" newline bitfld.long 0x04 11. " [11] ,Data bit 11 clear" "No effect,Clear" bitfld.long 0x04 10. " [10] ,Data bit 10 clear" "No effect,Clear" bitfld.long 0x04 9. " [9] ,Data bit 9 clear" "No effect,Clear" bitfld.long 0x04 8. " [8] ,Data bit 8 clear" "No effect,Clear" newline bitfld.long 0x04 7. " [7] ,Data bit 7 clear" "No effect,Clear" bitfld.long 0x04 6. " [6] ,Data bit 6 clear" "No effect,Clear" bitfld.long 0x04 5. " [5] ,Data bit 5 clear" "No effect,Clear" bitfld.long 0x04 4. " [4] ,Data bit 4 clear" "No effect,Clear" newline bitfld.long 0x04 3. " [3] ,Data bit 3 clear" "No effect,Clear" bitfld.long 0x04 2. " [2] ,Data bit 2 clear" "No effect,Clear" bitfld.long 0x04 1. " [1] ,Data bit 1 clear" "No effect,Clear" bitfld.long 0x04 0. " [0] ,Data bit 0 clear" "No effect,Clear" line.long 0x08 "DR_TOGGLE,GPIO Data Register TOGGLE Register" bitfld.long 0x08 31. " DR_TOGGLE[31] ,Data bit 31 toggle" "Not toggled,Toggled" bitfld.long 0x08 30. " [30] ,Data bit 30 toggle" "No effect,Clear" bitfld.long 0x08 29. " [29] ,Data bit 29 toggle" "Not toggled,Toggled" bitfld.long 0x08 28. " [28] ,Data bit 28 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 27. " [27] ,Data bit 27 toggle" "Not toggled,Toggled" bitfld.long 0x08 26. " [26] ,Data bit 26 toggle" "Not toggled,Toggled" bitfld.long 0x08 25. " [25] ,Data bit 25 toggle" "Not toggled,Toggled" bitfld.long 0x08 24. " [24] ,Data bit 24 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 23. " [23] ,Data bit 23 toggle" "Not toggled,Toggled" bitfld.long 0x08 22. " [22] ,Data bit 22 toggle" "Not toggled,Toggled" bitfld.long 0x08 21. " [21] ,Data bit 21 toggle" "Not toggled,Toggled" bitfld.long 0x08 20. " [20] ,Data bit 20 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 19. " [19] ,Data bit 19 toggle" "Not toggled,Toggled" bitfld.long 0x08 18. " [18] ,Data bit 18 toggle" "Not toggled,Toggled" bitfld.long 0x08 17. " [17] ,Data bit 17 toggle" "Not toggled,Toggled" bitfld.long 0x08 16. " [16] ,Data bit 16 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 15. " [15] ,Data bit 15 toggle" "Not toggled,Toggled" bitfld.long 0x08 14. " [14] ,Data bit 14 toggle" "Not toggled,Toggled" bitfld.long 0x08 13. " [13] ,Data bit 13 toggle" "Not toggled,Toggled" bitfld.long 0x08 12. " [12] ,Data bit 12 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 11. " [11] ,Data bit 11 toggle" "Not toggled,Toggled" bitfld.long 0x08 10. " [10] ,Data bit 10 toggle" "Not toggled,Toggled" bitfld.long 0x08 9. " [9] ,Data bit 9 toggle" "Not toggled,Toggled" bitfld.long 0x08 8. " [8] ,Data bit 8 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 7. " [7] ,Data bit 7 toggle" "Not toggled,Toggled" bitfld.long 0x08 6. " [6] ,Data bit 6 toggle" "Not toggled,Toggled" bitfld.long 0x08 5. " [5] ,Data bit 5 toggle" "Not toggled,Toggled" bitfld.long 0x08 4. " [4] ,Data bit 4 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 3. " [3] ,Data bit 3 toggle" "Not toggled,Toggled" bitfld.long 0x08 2. " [2] ,Data bit 2 toggle" "Not toggled,Toggled" bitfld.long 0x08 1. " [1] ,Data bit 1 toggle" "Not toggled,Toggled" bitfld.long 0x08 0. " [0] ,Data bit 0 toggle" "Not toggled,Toggled" width 0x0B tree.end tree.end tree "KPP (Keypad Port)" base ad:0x5D1A0000 width 6. group.word 0x00++0x07 line.word 0x00 "KPCR,Control Register" bitfld.word 0x00 15. " KCO_7 ,Keypad column strobe open-drain enable 7" "Totem pole,Open drain" bitfld.word 0x00 14. " [6] ,Keypad column strobe open-drain enable 6" "Totem pole,Open drain" bitfld.word 0x00 13. " [5] ,Keypad column strobe open-drain enable 5" "Totem pole,Open drain" bitfld.word 0x00 12. " [4] ,Keypad column strobe open-drain enable 4" "Totem pole,Open drain" newline bitfld.word 0x00 11. " [3] ,Keypad column strobe open-drain enable 3" "Totem pole,Open drain" bitfld.word 0x00 10. " [2] ,Keypad column strobe open-drain enable 2" "Totem pole,Open drain" bitfld.word 0x00 9. " [1] ,Keypad column strobe open-drain enable 1" "Totem pole,Open drain" bitfld.word 0x00 8. " [0] ,Keypad column strobe open-drain enable 0" "Totem pole,Open drain" newline bitfld.word 0x00 7. " KRE_7 ,Keypad row enable 7" "Not included,Included" bitfld.word 0x00 6. " [6] ,Keypad row enable 6" "Not included,Included" bitfld.word 0x00 5. " [5] ,Keypad row enable 5" "Not included,Included" bitfld.word 0x00 4. " [4] ,Keypad row enable 4" "Not included,Included" newline bitfld.word 0x00 3. " [3] ,Keypad row enable 3" "Not included,Included" bitfld.word 0x00 2. " [2] ,Keypad row enable 2" "Not included,Included" bitfld.word 0x00 1. " [1] ,Keypad row enable 1" "Not included,Included" bitfld.word 0x00 0. " [0] ,Keypad row enable 0" "Not included,Included" line.word 0x02 "KPSR,Status Register" bitfld.word 0x02 9. " KRIE ,Keypad release interrupt enable" "No interrupt,Interrupted" bitfld.word 0x02 8. " KDIE ,Keypad key depress interrupt enable" "No interrupt,Interrupted" bitfld.word 0x02 3. " KRSS ,Key release synchronizer set" "No effect,Release" bitfld.word 0x02 2. " KDSC ,Key depress synchronizer clear" "No effect,Clear" newline eventfld.word 0x02 1. " KPKR ,Keypad key release" "Not released,Released" eventfld.word 0x02 0. " KPKD ,Keypad key depress" "Not pressed,Depressed" line.word 0x04 "KDDR,Data Direction Register" bitfld.word 0x04 15. " KCCD_7 ,Keypad column data direction register 7" "Input,Output" bitfld.word 0x04 14. " [6] ,Keypad column data direction register 6" "Input,Output" bitfld.word 0x04 13. " [5] ,Keypad column data direction register 5" "Input,Output" bitfld.word 0x04 12. " [4] ,Keypad column data direction register 4" "Input,Output" newline bitfld.word 0x04 11. " [3] ,Keypad column data direction register 3" "Input,Output" bitfld.word 0x04 10. " [2] ,Keypad column data direction register 2" "Input,Output" bitfld.word 0x04 9. " [1] ,Keypad column data direction register 1" "Input,Output" bitfld.word 0x04 8. " [0] ,Keypad column data direction register 0" "Input,Output" newline bitfld.word 0x04 7. " KRDD_7 ,Keypad row data direction 7" "Input,Output" bitfld.word 0x04 6. " [6] ,Keypad row data direction 6" "Input,Output" bitfld.word 0x04 5. " [5] ,Keypad row data direction 5" "Input,Output" bitfld.word 0x04 4. " [4] ,Keypad row data direction 4" "Input,Output" newline bitfld.word 0x04 3. " [3] ,Keypad row data direction 3" "Input,Output" bitfld.word 0x04 2. " [2] ,Keypad row data direction 2" "Input,Output" bitfld.word 0x04 1. " [1] ,Keypad row data direction 1" "Input,Output" bitfld.word 0x04 0. " [0] ,Keypad row data direction 0" "Input,Output" line.word 0x06 "KPDR,Data Register" bitfld.word 0x06 15. " KCD_7 ,Keypad column data 7" "Low,High" bitfld.word 0x06 14. " [6] ,Keypad column data 6" "Low,High" bitfld.word 0x06 13. " [5] ,Keypad column data 5" "Low,High" bitfld.word 0x06 12. " [4] ,Keypad column data 4" "Low,High" newline bitfld.word 0x06 11. " [3] ,Keypad column data 3" "Low,High" bitfld.word 0x06 10. " [2] ,Keypad column data 2" "Low,High" bitfld.word 0x06 9. " [1] ,Keypad column data 1" "Low,High" bitfld.word 0x06 8. " [0] ,Keypad column data 0" "Low,High" newline bitfld.word 0x06 7. " KRD_7 ,Keypad row data 7" "Low,High" bitfld.word 0x06 6. " [6] ,Keypad row data 6" "Low,High" bitfld.word 0x06 5. " [5] ,Keypad row data 5" "Low,High" bitfld.word 0x06 4. " [4] ,Keypad row data 4" "Low,High" newline bitfld.word 0x06 3. " [3] ,Keypad row data 3" "Low,High" bitfld.word 0x06 2. " [2] ,Keypad row data 2" "Low,High" bitfld.word 0x06 1. " [1] ,Keypad row data 1" "Low,High" bitfld.word 0x06 0. " [0] ,Keypad row data 0" "Low,High" width 0x0B tree.end tree.open "PWM (Pulse Width Modulation)" tree "PWM0" base ad:0x5D000000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO water mark (FIFO empty flag set threshold)" ">= 1 empty slot,>= 2 empty slots,>= 3 empty slots,>= 4 empty slots" bitfld.long 0x00 25. " STOPEN ,Stop mode enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait mode enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " DBGEN ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte data swap control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word data swap control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM output configuration" "Set=rollover/Cleared=comparison,Set=comparison/Cleared=rollover,Disconnected,Disconnected" newline bitfld.long 0x00 16.--17. " CLKSRC ,Clock source select" "Off,IPG_CLK,IPG_CLK_HIGHFREQ,IPG_CLK_32K" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter clock prescaler value" bitfld.long 0x00 3. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample repeat" "Once,Twice,Four times,Eight times" newline bitfld.long 0x00 0. " EN ,PWM enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO write error status" "No error,Error" eventfld.long 0x04 5. " CMP ,Compare event status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over event status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO empty status" "Not empty,Empty" newline rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO available" "No available,1 word,2 words,3 words,4 words,?..." line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO empty interrupt enable" "Disabled,Enabled" line.long 0x0C "PWMSAR,PWM Sample Register" hexmask.long.word 0x0C 0.--15. 1. " SAMPLE ,Sample value" line.long 0x10 "PWMPR,PWM Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Period value" rgroup.long 0x14++0x03 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" width 0x0B tree.end tree "PWM1" base ad:0x5D010000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO water mark (FIFO empty flag set threshold)" ">= 1 empty slot,>= 2 empty slots,>= 3 empty slots,>= 4 empty slots" bitfld.long 0x00 25. " STOPEN ,Stop mode enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait mode enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " DBGEN ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte data swap control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word data swap control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM output configuration" "Set=rollover/Cleared=comparison,Set=comparison/Cleared=rollover,Disconnected,Disconnected" newline bitfld.long 0x00 16.--17. " CLKSRC ,Clock source select" "Off,IPG_CLK,IPG_CLK_HIGHFREQ,IPG_CLK_32K" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter clock prescaler value" bitfld.long 0x00 3. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample repeat" "Once,Twice,Four times,Eight times" newline bitfld.long 0x00 0. " EN ,PWM enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO write error status" "No error,Error" eventfld.long 0x04 5. " CMP ,Compare event status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over event status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO empty status" "Not empty,Empty" newline rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO available" "No available,1 word,2 words,3 words,4 words,?..." line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO empty interrupt enable" "Disabled,Enabled" line.long 0x0C "PWMSAR,PWM Sample Register" hexmask.long.word 0x0C 0.--15. 1. " SAMPLE ,Sample value" line.long 0x10 "PWMPR,PWM Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Period value" rgroup.long 0x14++0x03 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" width 0x0B tree.end tree "PWM2" base ad:0x5D020000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO water mark (FIFO empty flag set threshold)" ">= 1 empty slot,>= 2 empty slots,>= 3 empty slots,>= 4 empty slots" bitfld.long 0x00 25. " STOPEN ,Stop mode enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait mode enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " DBGEN ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte data swap control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word data swap control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM output configuration" "Set=rollover/Cleared=comparison,Set=comparison/Cleared=rollover,Disconnected,Disconnected" newline bitfld.long 0x00 16.--17. " CLKSRC ,Clock source select" "Off,IPG_CLK,IPG_CLK_HIGHFREQ,IPG_CLK_32K" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter clock prescaler value" bitfld.long 0x00 3. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample repeat" "Once,Twice,Four times,Eight times" newline bitfld.long 0x00 0. " EN ,PWM enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO write error status" "No error,Error" eventfld.long 0x04 5. " CMP ,Compare event status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over event status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO empty status" "Not empty,Empty" newline rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO available" "No available,1 word,2 words,3 words,4 words,?..." line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO empty interrupt enable" "Disabled,Enabled" line.long 0x0C "PWMSAR,PWM Sample Register" hexmask.long.word 0x0C 0.--15. 1. " SAMPLE ,Sample value" line.long 0x10 "PWMPR,PWM Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Period value" rgroup.long 0x14++0x03 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" width 0x0B tree.end tree "PWM3" base ad:0x5D030000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO water mark (FIFO empty flag set threshold)" ">= 1 empty slot,>= 2 empty slots,>= 3 empty slots,>= 4 empty slots" bitfld.long 0x00 25. " STOPEN ,Stop mode enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait mode enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " DBGEN ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte data swap control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word data swap control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM output configuration" "Set=rollover/Cleared=comparison,Set=comparison/Cleared=rollover,Disconnected,Disconnected" newline bitfld.long 0x00 16.--17. " CLKSRC ,Clock source select" "Off,IPG_CLK,IPG_CLK_HIGHFREQ,IPG_CLK_32K" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter clock prescaler value" bitfld.long 0x00 3. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample repeat" "Once,Twice,Four times,Eight times" newline bitfld.long 0x00 0. " EN ,PWM enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO write error status" "No error,Error" eventfld.long 0x04 5. " CMP ,Compare event status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over event status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO empty status" "Not empty,Empty" newline rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO available" "No available,1 word,2 words,3 words,4 words,?..." line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO empty interrupt enable" "Disabled,Enabled" line.long 0x0C "PWMSAR,PWM Sample Register" hexmask.long.word 0x0C 0.--15. 1. " SAMPLE ,Sample value" line.long 0x10 "PWMPR,PWM Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Period value" rgroup.long 0x14++0x03 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" width 0x0B tree.end tree "PWM4" base ad:0x5D040000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO water mark (FIFO empty flag set threshold)" ">= 1 empty slot,>= 2 empty slots,>= 3 empty slots,>= 4 empty slots" bitfld.long 0x00 25. " STOPEN ,Stop mode enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait mode enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " DBGEN ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte data swap control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word data swap control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM output configuration" "Set=rollover/Cleared=comparison,Set=comparison/Cleared=rollover,Disconnected,Disconnected" newline bitfld.long 0x00 16.--17. " CLKSRC ,Clock source select" "Off,IPG_CLK,IPG_CLK_HIGHFREQ,IPG_CLK_32K" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter clock prescaler value" bitfld.long 0x00 3. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample repeat" "Once,Twice,Four times,Eight times" newline bitfld.long 0x00 0. " EN ,PWM enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO write error status" "No error,Error" eventfld.long 0x04 5. " CMP ,Compare event status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over event status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO empty status" "Not empty,Empty" newline rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO available" "No available,1 word,2 words,3 words,4 words,?..." line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO empty interrupt enable" "Disabled,Enabled" line.long 0x0C "PWMSAR,PWM Sample Register" hexmask.long.word 0x0C 0.--15. 1. " SAMPLE ,Sample value" line.long 0x10 "PWMPR,PWM Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Period value" rgroup.long 0x14++0x03 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" width 0x0B tree.end tree "PWM5" base ad:0x5D050000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO water mark (FIFO empty flag set threshold)" ">= 1 empty slot,>= 2 empty slots,>= 3 empty slots,>= 4 empty slots" bitfld.long 0x00 25. " STOPEN ,Stop mode enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait mode enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " DBGEN ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte data swap control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word data swap control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM output configuration" "Set=rollover/Cleared=comparison,Set=comparison/Cleared=rollover,Disconnected,Disconnected" newline bitfld.long 0x00 16.--17. " CLKSRC ,Clock source select" "Off,IPG_CLK,IPG_CLK_HIGHFREQ,IPG_CLK_32K" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter clock prescaler value" bitfld.long 0x00 3. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample repeat" "Once,Twice,Four times,Eight times" newline bitfld.long 0x00 0. " EN ,PWM enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO write error status" "No error,Error" eventfld.long 0x04 5. " CMP ,Compare event status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over event status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO empty status" "Not empty,Empty" newline rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO available" "No available,1 word,2 words,3 words,4 words,?..." line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO empty interrupt enable" "Disabled,Enabled" line.long 0x0C "PWMSAR,PWM Sample Register" hexmask.long.word 0x0C 0.--15. 1. " SAMPLE ,Sample value" line.long 0x10 "PWMPR,PWM Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Period value" rgroup.long 0x14++0x03 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" width 0x0B tree.end tree "PWM6" base ad:0x5D060000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO water mark (FIFO empty flag set threshold)" ">= 1 empty slot,>= 2 empty slots,>= 3 empty slots,>= 4 empty slots" bitfld.long 0x00 25. " STOPEN ,Stop mode enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait mode enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " DBGEN ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte data swap control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word data swap control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM output configuration" "Set=rollover/Cleared=comparison,Set=comparison/Cleared=rollover,Disconnected,Disconnected" newline bitfld.long 0x00 16.--17. " CLKSRC ,Clock source select" "Off,IPG_CLK,IPG_CLK_HIGHFREQ,IPG_CLK_32K" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter clock prescaler value" bitfld.long 0x00 3. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample repeat" "Once,Twice,Four times,Eight times" newline bitfld.long 0x00 0. " EN ,PWM enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO write error status" "No error,Error" eventfld.long 0x04 5. " CMP ,Compare event status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over event status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO empty status" "Not empty,Empty" newline rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO available" "No available,1 word,2 words,3 words,4 words,?..." line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO empty interrupt enable" "Disabled,Enabled" line.long 0x0C "PWMSAR,PWM Sample Register" hexmask.long.word 0x0C 0.--15. 1. " SAMPLE ,Sample value" line.long 0x10 "PWMPR,PWM Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Period value" rgroup.long 0x14++0x03 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" width 0x0B tree.end tree "PWM7" base ad:0x5D070000 width 8. group.long 0x00++0x13 line.long 0x00 "PWMCR,PWM Control Register" bitfld.long 0x00 26.--27. " FWM ,FIFO water mark (FIFO empty flag set threshold)" ">= 1 empty slot,>= 2 empty slots,>= 3 empty slots,>= 4 empty slots" bitfld.long 0x00 25. " STOPEN ,Stop mode enable" "Disabled,Enabled" bitfld.long 0x00 24. " DOZEN ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " WAITEN ,Wait mode enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " DBGEN ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 21. " BCTR ,Byte data swap control" "Not swapped,Swapped" bitfld.long 0x00 20. " HCTR ,Half-word data swap control" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " POUTC ,PWM output configuration" "Set=rollover/Cleared=comparison,Set=comparison/Cleared=rollover,Disconnected,Disconnected" newline bitfld.long 0x00 16.--17. " CLKSRC ,Clock source select" "Off,IPG_CLK,IPG_CLK_HIGHFREQ,IPG_CLK_32K" hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter clock prescaler value" bitfld.long 0x00 3. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 1.--2. " REPEAT ,Sample repeat" "Once,Twice,Four times,Eight times" newline bitfld.long 0x00 0. " EN ,PWM enable" "Disabled,Enabled" line.long 0x04 "PWMSR,PWM Status Register" eventfld.long 0x04 6. " FWE ,FIFO write error status" "No error,Error" eventfld.long 0x04 5. " CMP ,Compare event status" "Not occurred,Occurred" eventfld.long 0x04 4. " ROV ,Roll-over event status" "Not occurred,Occurred" eventfld.long 0x04 3. " FE ,FIFO empty status" "Not empty,Empty" newline rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO available" "No available,1 word,2 words,3 words,4 words,?..." line.long 0x08 "PWMIR,PWM Interrupt Register" bitfld.long 0x08 2. " CIE ,Compare interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " RIE ,Roll-over interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " FIE ,FIFO empty interrupt enable" "Disabled,Enabled" line.long 0x0C "PWMSAR,PWM Sample Register" hexmask.long.word 0x0C 0.--15. 1. " SAMPLE ,Sample value" line.long 0x10 "PWMPR,PWM Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Period value" rgroup.long 0x14++0x03 line.long 0x00 "PWMCNR,PWM Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" width 0x0B tree.end tree.end tree.open "MU (Messaging Unit)" tree "MU0-A" base ad:0x5D1B0000 width 9. if (((per.l(ad:0x5D1B0000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x5D1B0000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x5D1B0000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x5D1B0000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x5D1B0000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x5D1B0000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x5D1B0000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x5D1B0000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree "MU1-A" base ad:0x5D1C0000 width 9. if (((per.l(ad:0x5D1C0000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x5D1C0000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x5D1C0000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x5D1C0000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x5D1C0000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x5D1C0000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x5D1C0000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x5D1C0000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree "MU2-A" base ad:0x5D1D0000 width 9. if (((per.l(ad:0x5D1D0000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x5D1D0000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x5D1D0000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x5D1D0000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x5D1D0000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x5D1D0000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x5D1D0000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x5D1D0000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree "MU3-A" base ad:0x5D1E0000 width 9. if (((per.l(ad:0x5D1E0000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x5D1E0000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x5D1E0000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x5D1E0000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x5D1E0000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x5D1E0000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x5D1E0000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x5D1E0000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree "MU4-A" base ad:0x5D1F0000 width 9. if (((per.l(ad:0x5D1F0000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x5D1F0000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x5D1F0000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x5D1F0000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x5D1F0000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x5D1F0000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x5D1F0000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x5D1F0000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree "MU5-A" base ad:0x5D200000 width 9. if (((per.l(ad:0x5D200000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x5D200000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x5D200000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x5D200000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x5D200000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x5D200000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x5D200000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x5D200000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree "MU6-A" base ad:0x5D210000 width 9. if (((per.l(ad:0x5D210000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x5D210000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x5D210000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x5D210000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x5D210000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x5D210000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x5D210000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x5D210000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree "MU7-A" base ad:0x5D220000 width 9. if (((per.l(ad:0x5D220000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x5D220000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x5D220000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x5D220000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x5D220000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x5D220000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x5D220000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x5D220000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree "MU8-A" base ad:0x5D230000 width 9. if (((per.l(ad:0x5D230000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x5D230000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x5D230000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x5D230000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x5D230000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x5D230000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x5D230000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x5D230000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree "MU9-A" base ad:0x5D240000 width 9. if (((per.l(ad:0x5D240000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x5D240000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x5D240000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x5D240000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x5D240000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x5D240000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x5D240000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x5D240000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree "MU10-A" base ad:0x5D250000 width 9. if (((per.l(ad:0x5D250000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x5D250000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x5D250000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x5D250000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x5D250000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x5D250000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x5D250000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x5D250000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree "MU11-A" base ad:0x5D260000 width 9. if (((per.l(ad:0x5D260000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x5D260000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x5D260000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x5D260000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x5D260000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x5D260000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x5D260000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x5D260000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree "MU12-A" base ad:0x5D270000 width 9. if (((per.l(ad:0x5D270000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x5D270000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x5D270000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x5D270000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x5D270000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x5D270000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x5D270000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x5D270000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree "MU13-A" base ad:0x5D280000 width 9. if (((per.l(ad:0x5D280000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "ATR0,Processor A Transmit Register 0" endif if (((per.l(ad:0x5D280000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "ATR1,Processor A Transmit Register 1" endif if (((per.l(ad:0x5D280000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "ATR2,Processor A Transmit Register 2" endif if (((per.l(ad:0x5D280000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "ATR3,Processor A Transmit Register 3" endif newline if (((per.l(ad:0x5D280000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "ARR0,Processor A Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "ARR0,Processor A Receive Register 0" in newline endif if (((per.l(ad:0x5D280000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "ARR1,Processor A Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "ARR1,Processor A Receive Register 1" in newline endif if (((per.l(ad:0x5D280000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "ARR2,Processor A Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "ARR2,Processor A Receive Register 2" in newline endif if (((per.l(ad:0x5D280000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "ARR3,Processor A Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "ARR3,Processor A Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "ASR,Processor A Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor A general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor A general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor A general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor A general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor A receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor A receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor A receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor A receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor A transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor A transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor A transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor A transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 9. " BRDIP ,Processor B reset de-asserted interrupt pending" "Not pending,Pending" bitfld.long 0x00 8. " FUP ,Processor A flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " BRS ,Processor B-side reset state" "Not reset,Reset" bitfld.long 0x00 4. " EP ,Processor A-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor A-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor A-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor A-side flag 0" "0,1" line.long 0x04 "ACR,Processor A Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor A general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor A general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor A general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor A general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor A receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor A receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor A receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor A receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor A transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor A transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor A transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor A transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor A general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor A general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor A general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor A general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 6. " BRDIE ,Processor B reset de-assertion interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " MUR ,Processor A MU Reset" "Not reset,Reset" bitfld.long 0x04 4. " BHR ,Processor B hardware reset" "Not reset,Reset" newline bitfld.long 0x04 2. " ABF[2] ,Processor A to processor B flag 2" "Not reset,Reset" bitfld.long 0x04 1. " [1] ,Processor A to processor B flag 1" "Not reset,Reset" bitfld.long 0x04 0. " [0] ,Processor A to processor B flag 0" "Not reset,Reset" width 0x0B tree.end tree "MU5-B" base ad:0x5D290000 width 9. if (((per.l(ad:0x5D290000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "BTR0,Processor B Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "BTR0,Processor B Transmit Register 0" endif if (((per.l(ad:0x5D290000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "BTR1,Processor B Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "BTR1,Processor B Transmit Register 1" endif if (((per.l(ad:0x5D290000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "BTR2,Processor B Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "BTR2,Processor B Transmit Register 2" endif if (((per.l(ad:0x5D290000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "BTR3,Processor B Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "BTR3,Processor B Transmit Register 3" endif newline if (((per.l(ad:0x5D290000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "BRR0,Processor B Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "BRR0,Processor B Receive Register 0" in newline endif if (((per.l(ad:0x5D290000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "BRR1,Processor B Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "BRR1,Processor B Receive Register 1" in newline endif if (((per.l(ad:0x5D290000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "BRR2,Processor B Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "BRR2,Processor B Receive Register 2" in newline endif if (((per.l(ad:0x5D290000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "BRR3,Processor B Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "BRR3,Processor B Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "BSR,Processor B Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor B general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor B general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor B general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor B general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor B receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor B receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor B receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor B receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor B transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor B transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor B transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor B transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 8. " FUP ,Processor B flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " ARS ,Processor A reset state" "No reset,Reset" bitfld.long 0x00 4. " EP ,Processor B-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor B-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor B-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor B-side flag 0" "0,1" line.long 0x04 "BCR,Processor B Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor B general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor B general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor B general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor B general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor B receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor B receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor B receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor B receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor B transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor B transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor B transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor B transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor B general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor B general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor B general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor B general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 4. " HRM ,Processor B hardware reset mask" "Not masked,Masked" newline bitfld.long 0x04 2. " BAF[2] ,Processor B to processor A flag 2" "Clear,Set" bitfld.long 0x04 1. " [1] ,Processor B to processor A flag 1" "Clear,Set" bitfld.long 0x04 0. " [0] ,Processor B to processor A flag 0" "Clear,Set" width 0x0B tree.end tree "MU6-B" base ad:0x5D2A0000 width 9. if (((per.l(ad:0x5D2A0000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "BTR0,Processor B Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "BTR0,Processor B Transmit Register 0" endif if (((per.l(ad:0x5D2A0000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "BTR1,Processor B Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "BTR1,Processor B Transmit Register 1" endif if (((per.l(ad:0x5D2A0000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "BTR2,Processor B Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "BTR2,Processor B Transmit Register 2" endif if (((per.l(ad:0x5D2A0000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "BTR3,Processor B Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "BTR3,Processor B Transmit Register 3" endif newline if (((per.l(ad:0x5D2A0000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "BRR0,Processor B Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "BRR0,Processor B Receive Register 0" in newline endif if (((per.l(ad:0x5D2A0000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "BRR1,Processor B Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "BRR1,Processor B Receive Register 1" in newline endif if (((per.l(ad:0x5D2A0000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "BRR2,Processor B Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "BRR2,Processor B Receive Register 2" in newline endif if (((per.l(ad:0x5D2A0000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "BRR3,Processor B Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "BRR3,Processor B Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "BSR,Processor B Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor B general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor B general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor B general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor B general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor B receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor B receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor B receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor B receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor B transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor B transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor B transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor B transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 8. " FUP ,Processor B flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " ARS ,Processor A reset state" "No reset,Reset" bitfld.long 0x00 4. " EP ,Processor B-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor B-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor B-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor B-side flag 0" "0,1" line.long 0x04 "BCR,Processor B Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor B general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor B general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor B general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor B general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor B receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor B receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor B receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor B receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor B transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor B transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor B transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor B transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor B general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor B general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor B general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor B general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 4. " HRM ,Processor B hardware reset mask" "Not masked,Masked" newline bitfld.long 0x04 2. " BAF[2] ,Processor B to processor A flag 2" "Clear,Set" bitfld.long 0x04 1. " [1] ,Processor B to processor A flag 1" "Clear,Set" bitfld.long 0x04 0. " [0] ,Processor B to processor A flag 0" "Clear,Set" width 0x0B tree.end tree "MU7-B" base ad:0x5D2B0000 width 9. if (((per.l(ad:0x5D2B0000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "BTR0,Processor B Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "BTR0,Processor B Transmit Register 0" endif if (((per.l(ad:0x5D2B0000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "BTR1,Processor B Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "BTR1,Processor B Transmit Register 1" endif if (((per.l(ad:0x5D2B0000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "BTR2,Processor B Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "BTR2,Processor B Transmit Register 2" endif if (((per.l(ad:0x5D2B0000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "BTR3,Processor B Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "BTR3,Processor B Transmit Register 3" endif newline if (((per.l(ad:0x5D2B0000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "BRR0,Processor B Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "BRR0,Processor B Receive Register 0" in newline endif if (((per.l(ad:0x5D2B0000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "BRR1,Processor B Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "BRR1,Processor B Receive Register 1" in newline endif if (((per.l(ad:0x5D2B0000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "BRR2,Processor B Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "BRR2,Processor B Receive Register 2" in newline endif if (((per.l(ad:0x5D2B0000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "BRR3,Processor B Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "BRR3,Processor B Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "BSR,Processor B Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor B general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor B general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor B general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor B general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor B receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor B receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor B receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor B receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor B transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor B transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor B transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor B transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 8. " FUP ,Processor B flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " ARS ,Processor A reset state" "No reset,Reset" bitfld.long 0x00 4. " EP ,Processor B-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor B-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor B-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor B-side flag 0" "0,1" line.long 0x04 "BCR,Processor B Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor B general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor B general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor B general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor B general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor B receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor B receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor B receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor B receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor B transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor B transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor B transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor B transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor B general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor B general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor B general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor B general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 4. " HRM ,Processor B hardware reset mask" "Not masked,Masked" newline bitfld.long 0x04 2. " BAF[2] ,Processor B to processor A flag 2" "Clear,Set" bitfld.long 0x04 1. " [1] ,Processor B to processor A flag 1" "Clear,Set" bitfld.long 0x04 0. " [0] ,Processor B to processor A flag 0" "Clear,Set" width 0x0B tree.end tree "MU8-B" base ad:0x5D2C0000 width 9. if (((per.l(ad:0x5D2C0000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "BTR0,Processor B Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "BTR0,Processor B Transmit Register 0" endif if (((per.l(ad:0x5D2C0000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "BTR1,Processor B Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "BTR1,Processor B Transmit Register 1" endif if (((per.l(ad:0x5D2C0000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "BTR2,Processor B Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "BTR2,Processor B Transmit Register 2" endif if (((per.l(ad:0x5D2C0000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "BTR3,Processor B Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "BTR3,Processor B Transmit Register 3" endif newline if (((per.l(ad:0x5D2C0000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "BRR0,Processor B Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "BRR0,Processor B Receive Register 0" in newline endif if (((per.l(ad:0x5D2C0000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "BRR1,Processor B Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "BRR1,Processor B Receive Register 1" in newline endif if (((per.l(ad:0x5D2C0000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "BRR2,Processor B Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "BRR2,Processor B Receive Register 2" in newline endif if (((per.l(ad:0x5D2C0000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "BRR3,Processor B Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "BRR3,Processor B Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "BSR,Processor B Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor B general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor B general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor B general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor B general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor B receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor B receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor B receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor B receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor B transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor B transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor B transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor B transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 8. " FUP ,Processor B flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " ARS ,Processor A reset state" "No reset,Reset" bitfld.long 0x00 4. " EP ,Processor B-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor B-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor B-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor B-side flag 0" "0,1" line.long 0x04 "BCR,Processor B Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor B general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor B general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor B general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor B general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor B receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor B receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor B receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor B receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor B transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor B transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor B transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor B transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor B general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor B general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor B general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor B general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 4. " HRM ,Processor B hardware reset mask" "Not masked,Masked" newline bitfld.long 0x04 2. " BAF[2] ,Processor B to processor A flag 2" "Clear,Set" bitfld.long 0x04 1. " [1] ,Processor B to processor A flag 1" "Clear,Set" bitfld.long 0x04 0. " [0] ,Processor B to processor A flag 0" "Clear,Set" width 0x0B tree.end tree "MU9-B" base ad:0x5D2D0000 width 9. if (((per.l(ad:0x5D2D0000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "BTR0,Processor B Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "BTR0,Processor B Transmit Register 0" endif if (((per.l(ad:0x5D2D0000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "BTR1,Processor B Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "BTR1,Processor B Transmit Register 1" endif if (((per.l(ad:0x5D2D0000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "BTR2,Processor B Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "BTR2,Processor B Transmit Register 2" endif if (((per.l(ad:0x5D2D0000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "BTR3,Processor B Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "BTR3,Processor B Transmit Register 3" endif newline if (((per.l(ad:0x5D2D0000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "BRR0,Processor B Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "BRR0,Processor B Receive Register 0" in newline endif if (((per.l(ad:0x5D2D0000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "BRR1,Processor B Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "BRR1,Processor B Receive Register 1" in newline endif if (((per.l(ad:0x5D2D0000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "BRR2,Processor B Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "BRR2,Processor B Receive Register 2" in newline endif if (((per.l(ad:0x5D2D0000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "BRR3,Processor B Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "BRR3,Processor B Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "BSR,Processor B Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor B general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor B general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor B general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor B general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor B receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor B receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor B receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor B receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor B transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor B transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor B transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor B transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 8. " FUP ,Processor B flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " ARS ,Processor A reset state" "No reset,Reset" bitfld.long 0x00 4. " EP ,Processor B-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor B-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor B-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor B-side flag 0" "0,1" line.long 0x04 "BCR,Processor B Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor B general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor B general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor B general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor B general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor B receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor B receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor B receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor B receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor B transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor B transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor B transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor B transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor B general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor B general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor B general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor B general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 4. " HRM ,Processor B hardware reset mask" "Not masked,Masked" newline bitfld.long 0x04 2. " BAF[2] ,Processor B to processor A flag 2" "Clear,Set" bitfld.long 0x04 1. " [1] ,Processor B to processor A flag 1" "Clear,Set" bitfld.long 0x04 0. " [0] ,Processor B to processor A flag 0" "Clear,Set" width 0x0B tree.end tree "MU10-B" base ad:0x5D2E0000 width 9. if (((per.l(ad:0x5D2E0000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "BTR0,Processor B Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "BTR0,Processor B Transmit Register 0" endif if (((per.l(ad:0x5D2E0000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "BTR1,Processor B Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "BTR1,Processor B Transmit Register 1" endif if (((per.l(ad:0x5D2E0000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "BTR2,Processor B Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "BTR2,Processor B Transmit Register 2" endif if (((per.l(ad:0x5D2E0000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "BTR3,Processor B Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "BTR3,Processor B Transmit Register 3" endif newline if (((per.l(ad:0x5D2E0000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "BRR0,Processor B Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "BRR0,Processor B Receive Register 0" in newline endif if (((per.l(ad:0x5D2E0000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "BRR1,Processor B Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "BRR1,Processor B Receive Register 1" in newline endif if (((per.l(ad:0x5D2E0000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "BRR2,Processor B Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "BRR2,Processor B Receive Register 2" in newline endif if (((per.l(ad:0x5D2E0000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "BRR3,Processor B Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "BRR3,Processor B Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "BSR,Processor B Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor B general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor B general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor B general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor B general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor B receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor B receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor B receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor B receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor B transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor B transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor B transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor B transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 8. " FUP ,Processor B flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " ARS ,Processor A reset state" "No reset,Reset" bitfld.long 0x00 4. " EP ,Processor B-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor B-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor B-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor B-side flag 0" "0,1" line.long 0x04 "BCR,Processor B Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor B general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor B general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor B general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor B general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor B receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor B receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor B receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor B receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor B transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor B transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor B transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor B transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor B general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor B general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor B general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor B general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 4. " HRM ,Processor B hardware reset mask" "Not masked,Masked" newline bitfld.long 0x04 2. " BAF[2] ,Processor B to processor A flag 2" "Clear,Set" bitfld.long 0x04 1. " [1] ,Processor B to processor A flag 1" "Clear,Set" bitfld.long 0x04 0. " [0] ,Processor B to processor A flag 0" "Clear,Set" width 0x0B tree.end tree "MU11-B" base ad:0x5D2F0000 width 9. if (((per.l(ad:0x5D2F0000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "BTR0,Processor B Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "BTR0,Processor B Transmit Register 0" endif if (((per.l(ad:0x5D2F0000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "BTR1,Processor B Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "BTR1,Processor B Transmit Register 1" endif if (((per.l(ad:0x5D2F0000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "BTR2,Processor B Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "BTR2,Processor B Transmit Register 2" endif if (((per.l(ad:0x5D2F0000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "BTR3,Processor B Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "BTR3,Processor B Transmit Register 3" endif newline if (((per.l(ad:0x5D2F0000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "BRR0,Processor B Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "BRR0,Processor B Receive Register 0" in newline endif if (((per.l(ad:0x5D2F0000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "BRR1,Processor B Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "BRR1,Processor B Receive Register 1" in newline endif if (((per.l(ad:0x5D2F0000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "BRR2,Processor B Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "BRR2,Processor B Receive Register 2" in newline endif if (((per.l(ad:0x5D2F0000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "BRR3,Processor B Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "BRR3,Processor B Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "BSR,Processor B Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor B general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor B general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor B general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor B general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor B receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor B receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor B receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor B receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor B transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor B transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor B transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor B transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 8. " FUP ,Processor B flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " ARS ,Processor A reset state" "No reset,Reset" bitfld.long 0x00 4. " EP ,Processor B-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor B-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor B-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor B-side flag 0" "0,1" line.long 0x04 "BCR,Processor B Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor B general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor B general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor B general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor B general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor B receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor B receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor B receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor B receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor B transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor B transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor B transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor B transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor B general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor B general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor B general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor B general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 4. " HRM ,Processor B hardware reset mask" "Not masked,Masked" newline bitfld.long 0x04 2. " BAF[2] ,Processor B to processor A flag 2" "Clear,Set" bitfld.long 0x04 1. " [1] ,Processor B to processor A flag 1" "Clear,Set" bitfld.long 0x04 0. " [0] ,Processor B to processor A flag 0" "Clear,Set" width 0x0B tree.end tree "MU12-B" base ad:0x5D300000 width 9. if (((per.l(ad:0x5D300000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "BTR0,Processor B Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "BTR0,Processor B Transmit Register 0" endif if (((per.l(ad:0x5D300000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "BTR1,Processor B Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "BTR1,Processor B Transmit Register 1" endif if (((per.l(ad:0x5D300000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "BTR2,Processor B Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "BTR2,Processor B Transmit Register 2" endif if (((per.l(ad:0x5D300000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "BTR3,Processor B Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "BTR3,Processor B Transmit Register 3" endif newline if (((per.l(ad:0x5D300000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "BRR0,Processor B Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "BRR0,Processor B Receive Register 0" in newline endif if (((per.l(ad:0x5D300000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "BRR1,Processor B Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "BRR1,Processor B Receive Register 1" in newline endif if (((per.l(ad:0x5D300000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "BRR2,Processor B Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "BRR2,Processor B Receive Register 2" in newline endif if (((per.l(ad:0x5D300000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "BRR3,Processor B Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "BRR3,Processor B Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "BSR,Processor B Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor B general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor B general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor B general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor B general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor B receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor B receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor B receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor B receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor B transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor B transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor B transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor B transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 8. " FUP ,Processor B flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " ARS ,Processor A reset state" "No reset,Reset" bitfld.long 0x00 4. " EP ,Processor B-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor B-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor B-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor B-side flag 0" "0,1" line.long 0x04 "BCR,Processor B Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor B general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor B general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor B general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor B general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor B receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor B receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor B receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor B receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor B transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor B transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor B transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor B transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor B general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor B general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor B general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor B general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 4. " HRM ,Processor B hardware reset mask" "Not masked,Masked" newline bitfld.long 0x04 2. " BAF[2] ,Processor B to processor A flag 2" "Clear,Set" bitfld.long 0x04 1. " [1] ,Processor B to processor A flag 1" "Clear,Set" bitfld.long 0x04 0. " [0] ,Processor B to processor A flag 0" "Clear,Set" width 0x0B tree.end tree "MU13-B" base ad:0x5D310000 width 9. if (((per.l(ad:0x5D310000+0x20))&0x0100000<<0)==0x0100000<<0) group.long 0x0++0x03 line.long 0x00 "BTR0,Processor B Transmit Register 0" else rgroup.long 0x0++0x03 line.long 0x00 "BTR0,Processor B Transmit Register 0" endif if (((per.l(ad:0x5D310000+0x20))&0x0100000<<1)==0x0100000<<1) group.long 0x4++0x03 line.long 0x00 "BTR1,Processor B Transmit Register 1" else rgroup.long 0x4++0x03 line.long 0x00 "BTR1,Processor B Transmit Register 1" endif if (((per.l(ad:0x5D310000+0x20))&0x0100000<<2)==0x0100000<<2) group.long 0x8++0x03 line.long 0x00 "BTR2,Processor B Transmit Register 2" else rgroup.long 0x8++0x03 line.long 0x00 "BTR2,Processor B Transmit Register 2" endif if (((per.l(ad:0x5D310000+0x20))&0x0100000<<3)==0x0100000<<3) group.long 0xC++0x03 line.long 0x00 "BTR3,Processor B Transmit Register 3" else rgroup.long 0xC++0x03 line.long 0x00 "BTR3,Processor B Transmit Register 3" endif newline if (((per.l(ad:0x5D310000+0x20))&0x01000000<<0)==0x01000000<<0) rgroup.long 0x10++0x03 line.long 0x00 "BRR0,Processor B Receive Register 0" else hgroup.long 0x10++0x03 hide.long 0x00 "BRR0,Processor B Receive Register 0" in newline endif if (((per.l(ad:0x5D310000+0x20))&0x01000000<<1)==0x01000000<<1) rgroup.long 0x14++0x03 line.long 0x00 "BRR1,Processor B Receive Register 1" else hgroup.long 0x14++0x03 hide.long 0x00 "BRR1,Processor B Receive Register 1" in newline endif if (((per.l(ad:0x5D310000+0x20))&0x01000000<<2)==0x01000000<<2) rgroup.long 0x18++0x03 line.long 0x00 "BRR2,Processor B Receive Register 2" else hgroup.long 0x18++0x03 hide.long 0x00 "BRR2,Processor B Receive Register 2" in newline endif if (((per.l(ad:0x5D310000+0x20))&0x01000000<<3)==0x01000000<<3) rgroup.long 0x1C++0x03 line.long 0x00 "BRR3,Processor B Receive Register 3" else hgroup.long 0x1C++0x03 hide.long 0x00 "BRR3,Processor B Receive Register 3" in newline endif group.long 0x20++0x07 line.long 0x00 "BSR,Processor B Status Register" bitfld.long 0x00 31. " GIP[3] ,Processor B general interrupt request 3 pending" "Not pending,Pending" bitfld.long 0x00 30. " [2] ,Processor B general interrupt request 2 pending" "Not pending,Pending" bitfld.long 0x00 29. " [1] ,Processor B general interrupt request 1 pending" "Not pending,Pending" bitfld.long 0x00 28. " [0] ,Processor B general interrupt request 0 pending" "Not pending,Pending" newline bitfld.long 0x00 27. " RF[3] ,Processor B receive register 3 full" "Not full,Full" bitfld.long 0x00 26. " [2] ,Processor B receive register 2 full" "Not full,Full" bitfld.long 0x00 25. " [1] ,Processor B receive register 1 full" "Not full,Full" bitfld.long 0x00 24. " [0] ,Processor B receive register 0 full" "Not full,Full" newline bitfld.long 0x00 23. " TE[3] ,Processor B transmit register 3 empty" "Not empty,Empty" bitfld.long 0x00 22. " [2] ,Processor B transmit register 2 empty" "Not empty,Empty" bitfld.long 0x00 21. " [1] ,Processor B transmit register 1 empty" "Not empty,Empty" bitfld.long 0x00 20. " [0] ,Processor B transmit register 0 empty" "Not empty,Empty" newline bitfld.long 0x00 8. " FUP ,Processor B flags update pending" "Not pending,Pending" bitfld.long 0x00 7. " ARS ,Processor A reset state" "No reset,Reset" bitfld.long 0x00 4. " EP ,Processor B-side event pending" "Not pending,Pending" newline bitfld.long 0x00 3. " F[2] ,Processor B-side flag 2" ",1" bitfld.long 0x00 1. " [1] ,Processor B-side flag 1" "0,1" bitfld.long 0x00 0. " [0] ,Processor B-side flag 0" "0,1" line.long 0x04 "BCR,Processor B Control Register" bitfld.long 0x04 31. " GIE[3] ,Processor B general purpose interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 30. " [2] ,Processor B general purpose interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 29. " [1] ,Processor B general purpose interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 28. " [0] ,Processor B general purpose interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 27. " RIE[3] ,Processor B receive interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Processor B receive interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 25. " [1] ,Processor B receive interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Processor B receive interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " TIE[3] ,Processor B transmit interrupt enable 3" "Disabled,Enabled" bitfld.long 0x04 22. " [2] ,Processor B transmit interrupt enable 2" "Disabled,Enabled" bitfld.long 0x04 21. " [1] ,Processor B transmit interrupt enable 1" "Disabled,Enabled" bitfld.long 0x04 20. " [0] ,Processor B transmit interrupt enable 0" "Disabled,Enabled" newline bitfld.long 0x04 19. " GIR[3] ,Processor B general purpose interrupt request 3" "No request,Request" bitfld.long 0x04 18. " [2] ,Processor B general purpose interrupt request 2" "No request,Request" bitfld.long 0x04 17. " [1] ,Processor B general purpose interrupt request 1" "No request,Request" bitfld.long 0x04 16. " [0] ,Processor B general purpose interrupt request 0" "No request,Request" newline bitfld.long 0x04 4. " HRM ,Processor B hardware reset mask" "Not masked,Masked" newline bitfld.long 0x04 2. " BAF[2] ,Processor B to processor A flag 2" "Clear,Set" bitfld.long 0x04 1. " [1] ,Processor B to processor A flag 1" "Clear,Set" bitfld.long 0x04 0. " [0] ,Processor B to processor A flag 0" "Clear,Set" width 0x0B tree.end tree.end tree.end tree.open "HSIO" tree "PCIe (PCI Express)" base ad:0x5F010000 width 43. tree "PF0_TYPE1_HDR" rgroup.long 0x00++0x03 line.long 0x00 "TYPE1_DEV_ID_VEND_ID_REG,PCIE0 Device ID And Vendor ID Register" hexmask.long.word 0x00 16.--31. 1. " DEVID ,Device ID" hexmask.long.word 0x00 0.--15. 1. " VENDID ,Vendor ID" if (((per.l(ad:0x5F010000+0x1BC))&0x01)==0x01) group.long 0x04++0x03 line.long 0x00 "TYPE1_STATUS_COMMAND_REG,Command And Status Register" eventfld.long 0x00 31. " DETECTED_PARITY_ERROR ,Detected parity error" "No error,Error" eventfld.long 0x00 30. " SIGNALED_SYS_ERROR ,Signaled system error" "No error,Error" newline eventfld.long 0x00 29. " RCVD_MASTER_ABORT ,Received master abort" "No abort,Abort" eventfld.long 0x00 28. " RCVD_TARGET_ABORT ,Received target abort" "No abort,Abort" newline eventfld.long 0x00 27. " SIGNALED_TARGET_ABORT ,Signaled target abort" "No abort,Abort" rbitfld.long 0x00 25.--26. " DEV_SEL_TIMING ,Device select timing" "0,?..." newline eventfld.long 0x00 24. " MASTER_DPE ,Master data parity error" "No error,Error" rbitfld.long 0x00 23. " FASTB2B ,Fast back-to-back transactions enable" "Disabled,?..." newline rbitfld.long 0x00 21. " FAST_66MHZ_CAP ,66 MHz capable" "Not capable,Capable" rbitfld.long 0x00 20. " CAP_LIST ,Capabilities list" "0,1" newline rbitfld.long 0x00 19. " INT_STATUS ,Interrupt status" "Disabled,Enabled" bitfld.long 0x00 10. " INT_EN ,Interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " SERREN ,Reporting of non-fatal and fatal errors detected enable" "Disabled,Enabled" rbitfld.long 0x00 7. " IDSEL ,IDSEL stepping/wait cycle control" "0,1" newline bitfld.long 0x00 6. " PERREN ,Parity error enable" "Disabled,Enabled" rbitfld.long 0x00 5. " VGAPS ,VGA palette snoop" "Disabled,Enabled" newline rbitfld.long 0x00 4. " MWI_EN ,Memory write and invalidate enable" "Disabled,Enabled" rbitfld.long 0x00 3. " SCO ,Special cycle enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " BME ,Bus master enable" "Disabled,Enabled" bitfld.long 0x00 1. " MSE ,Memory space enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " IO_EN ,I/O space enable" "Disabled,Enabled" else group.long 0x04++0x03 line.long 0x00 "TYPE1_STATUS_COMMAND_REG,Command And Status Register" eventfld.long 0x00 31. " DETECTED_PARITY_ERROR ,Detected parity error" "No error,Error" eventfld.long 0x00 30. " SIGNALED_SYS_ERROR ,Signaled system error" "No error,Error" newline eventfld.long 0x00 29. " RCVD_MASTER_ABORT ,Received master abort" "No abort,Abort" eventfld.long 0x00 28. " RCVD_TARGET_ABORT ,Received target abort" "No abort,Abort" newline eventfld.long 0x00 27. " SIGNALED_TARGET_ABORT ,Signaled target abort" "No abort,Abort" rbitfld.long 0x00 25.--26. " DEV_SEL_TIMING ,Device select timing" "0,?..." newline eventfld.long 0x00 24. " MASTER_DPE ,Master data parity error" "No error,Error" rbitfld.long 0x00 23. " FASTB2B ,Fast back-to-back transactions enable" "Disabled,?..." newline rbitfld.long 0x00 21. " FAST_66MHZ_CAP ,66 MHz capable" "Not capable,Capable" rbitfld.long 0x00 20. " CAP_LIST ,Capabilities list" "0,1" newline rbitfld.long 0x00 19. " INT_STATUS ,Interrupt status" "Disabled,Enabled" bitfld.long 0x00 10. " INT_EN ,Interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " SERREN ,Reporting of non-fatal and fatal errors detected enable" "Disabled,Enabled" rbitfld.long 0x00 7. " IDSEL ,IDSEL stepping/wait cycle control" "0,1" newline bitfld.long 0x00 6. " PERREN ,Parity error enable" "Disabled,Enabled" rbitfld.long 0x00 5. " VGAPS ,VGA palette snoop" "Disabled,Enabled" newline rbitfld.long 0x00 4. " MWI_EN ,Memory write and invalidate enable" "Disabled,Enabled" rbitfld.long 0x00 3. " SCO ,Special cycle enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " BME ,Bus master enable" "Disabled,Enabled" rbitfld.long 0x00 1. " MSE ,Memory space enable" "Disabled,Enabled" newline rbitfld.long 0x00 0. " IO_EN ,I/O space enable" "Disabled,Enabled" endif rgroup.long 0x08++0x03 line.long 0x00 "CCRID,Class Code And Revision ID Register" hexmask.long.byte 0x00 24.--31. 1. " BASE_CLASS_CODE ,Base class-memory controller" hexmask.long.byte 0x00 16.--23. 1. " SUBCLASS_CODE ,Sub class-other memory controller" newline hexmask.long.byte 0x00 8.--15. 1. " PROGRAM_INTF ,Register level programming interface" hexmask.long.byte 0x00 0.--7. 1. " REV_ID ,Device revision number" group.long 0x0C++0x03 line.long 0x00 "BISTTCLSMLT,BIST Header Type Cache Line Size And Master Latency Timer Register" hexmask.long.byte 0x00 24.--31. 1. " BIST ,Built-in self test" rbitfld.long 0x00 23. " MULTI_FUNC ,MULTI_FUNC" "0,1" newline hexmask.long.byte 0x00 16.--22. 1. " HEADER_TYPE ,Device configuration header type" hexmask.long.byte 0x00 8.--15. 1. " LAT_MASTER_TMR ,Latency master timer" newline hexmask.long.byte 0x00 0.--7. 1. " CACHE_LINE_SIZE ,Device cache line size" group.long 0x18++0x0F line.long 0x00 "SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG,Primary/Secondary/Subordinate Bus Numbers And Latency Timer Register" hexmask.long.byte 0x00 24.--31. 1. " SEC_LAT_TIMER ,Latency timer" hexmask.long.byte 0x00 16.--23. 1. " SUB_BUS ,Subordinate bus number" newline hexmask.long.byte 0x00 8.--15. 1. " SEC_BUS ,Secondary bus number" hexmask.long.byte 0x00 0.--7. 1. " PRIM_BUS ,Primary bus number" line.long 0x04 "SEC_STAT_IO_LIMIT_IO_BASE_REG,Secondary Status And I/O Base And Limit Register" bitfld.long 0x04 31. " SEC_STAT_DPE ,Secondary status data parity error" "Not occurred,Occurred" bitfld.long 0x04 30. " SEC_STAT_RCVD_SYS_ERR ,Secondary status received system error" "Not occurred,Occurred" newline bitfld.long 0x04 29. " SEC_STAT_RCVD_MSTR_ABRT ,Secondary status received master abort" "Not aborted,Aborted" bitfld.long 0x04 28. " SEC_STAT_RCVD_TRGT_ABRT ,Secondary status received target abort" "0,1" newline bitfld.long 0x04 27. " SEC_STAT_SIG_TRGT_ABRT ,Secondary status signaled target abort" "Not aborted,Aborted" bitfld.long 0x04 24. " SEC_STAT_MDPE ,Secondary status signaled target abort" "0,1" newline bitfld.long 0x04 12.--15. " IO_LIMIT ,I/O limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x04 8. " IO_DECODE_BIT8 ,I/O decode bit 8" "0,1" newline bitfld.long 0x04 4.--7. " IO_BASE ,I/O base" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x04 0. " IO_DECODE ,I/O decode" "0,1" line.long 0x08 "MEM_LIMIT_MEM_BASE_REG,Memory Base And Memory Limit Register" hexmask.long.word 0x08 20.--31. 1. " MEM_LIMIT ,Memory limit" hexmask.long.word 0x08 4.--15. 1. " MEM_BASE ,Memory limit" line.long 0x0C "PREF_MEM_LIMIT_MEM_BASE_REG,Prefetchable Memory Base And Limit Register" hexmask.long.word 0x0C 20.--31. 1. " PREF_MEM_LIMIT ,Prefetchable memory limit" rbitfld.long 0x0C 16. " PREF_MEM_LIMIT_DECODE ,Prefetchable memory limit decode" "0,1" newline hexmask.long.word 0x0C 4.--15. 1. " PREF_MEM_BASE ,Prefetchable memory base" rbitfld.long 0x0C 0. " PREF_MEM_DECODE ,Prefetchable memory decode" "0,1" if (((per.l(ad:0x5F010000+0x1BC))&0x01)==0x01) group.long 0x28++0x0B line.long 0x00 "PREF_BASE_UPPER_REG,Prefetchable Base Upper 32 Bits Register" line.long 0x04 "PREF_LIMIT_UPPER_REG,Prefetchable Limit Upper 32 Bits Register" line.long 0x08 "IO_LIMIT_UPPER_IO_BASE_UPPER_REG,I/O Base And Limit Upper 16 Bits Register" hexmask.long.word 0x08 16.--31. 1. " IO_LIMIT_UPPER ,I/O limit upper 16 bits" hexmask.long.word 0x08 0.--15. 1. " IO_BASE_UPPER ,I/O base upper 16 bits" else rgroup.long 0x28++0x0B line.long 0x00 "PREF_BASE_UPPER_REG,Prefetchable Base Upper 32 Bits Register" line.long 0x04 "PREF_LIMIT_UPPER_REG,Prefetchable Limit Upper 32 Bits Register" line.long 0x08 "IO_LIMIT_UPPER_IO_BASE_UPPER_REG,I/O Base And Limit Upper 16 Bits Register" hexmask.long.word 0x08 16.--31. 1. " IO_LIMIT_UPPER ,I/O limit upper 16 bits" hexmask.long.word 0x08 0.--15. 1. " IO_BASE_UPPER ,I/O base upper 16 bits" endif rgroup.long 0x34++0x03 line.long 0x00 "TYPE1_CAP_PTR_REG,Capability Pointer Register" hexmask.long.byte 0x00 0.--7. 0x01 " CAP_PTR ,Capability list pointer" group.long 0x38++0x07 line.long 0x00 "TYPE1_EXP_ROM_BASE_REG,Expansion ROM BAR And Mask Register" hexmask.long.tbyte 0x00 11.--31. 0x08 " EXP_ROM_BASE_ADDR ,Expansion ROM BAR and mask register" rbitfld.long 0x00 0. " ROM_BAR_EN ,ROM BAR enable" "Disabled,Enabled" line.long 0x04 "BRIDGE_CTRL_INT_PIN_INT_LINE_REG,Interrupt Line And Pin And Bridge Control Register" bitfld.long 0x04 22. " SBR ,Secondary bus hot reset" "0,1" rbitfld.long 0x04 21. " MSTR_ABORT_MODE ,Master abort mode" "0,1" newline rbitfld.long 0x04 20. " VGA_16B_DEC ,VGA 16-bit decode" "Disabled,Enabled" rbitfld.long 0x04 19. " VGA_EN ,VGA enable" "Disabled,Enabled" newline bitfld.long 0x04 18. " ISA_EN ,ISA enable" "Disabled,Enabled" bitfld.long 0x04 17. " SERR_EN ,SERR enable" "Disabled,Enabled" newline bitfld.long 0x04 16. " PERE ,PERE" "0,1" hexmask.long.byte 0x04 8.--15. 1. " INT_PIN ,Interrupt A in the interrupt emulation messages" newline hexmask.long.byte 0x04 0.--7. 1. " INT_LINE ,Interrupt line routing information" tree.end tree "PF0_PM_CAP" base ad:0x5F010000+0x40 width 20. rgroup.long 0x00++0x03 line.long 0x00 "CAP_ID_NXT_PTR_REG,Power Management Capabilities Register" bitfld.long 0x00 27.--31. " PME_SUPPORT ,Support PM event generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 26. " D2_SUPPORT ,Support D2 power management state" "Not supported,Supported" newline bitfld.long 0x00 25. " D1_SUPPORT ,Support D1 power management state" "Not supported,Supported" bitfld.long 0x00 22.--24. " AUX_CURR ,Auxiliary current requirements" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 21. " DSI ,Device specific initialization" "Low,High" newline bitfld.long 0x00 20. " PME_IMM_READI_RETURN_DO ,Immediate readiness on return to D0" "Not ready,Ready" bitfld.long 0x00 19. " PME_CLK ,PME clock" "0,1" newline bitfld.long 0x00 16.--18. " PM_SPEC_VER ,PCI power management capability version" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 8.--15. 0x01 " PM_NEXT_PTR ,Next item pointer" newline hexmask.long.byte 0x00 0.--7. 1. " PM_CAP_ID ,Capability ID" group.long 0x04++0x03 line.long 0x00 "PCIEPMCS,PCI Express Power Management Control And Status Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_REG_ADD_INFO ,Data register add info" rbitfld.long 0x00 23. " BUS_PWR_CLK_CON_EN ,Bus power clock control enable" "Disabled,Enabled" newline rbitfld.long 0x00 22. " B2_B3_SUPPORT ,B2 B3 support" "Not supported,Supported" bitfld.long 0x00 15. " PME_STATUS ,PME status" "0,1" newline rbitfld.long 0x00 13.--14. " DATA_SCALE ,Data scale" "0,1,2,3" rbitfld.long 0x00 9.--12. " DATA_SEL ,Data select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8. " PME_EN ,PM_PME message generation enable" "Disabled,Enabled" rbitfld.long 0x00 3. " NO_SOFT_RST ,No soft reset" "Low,High" newline bitfld.long 0x00 0.--1. " POWER_STATE ,Power state" "0,1,2,3" newline tree.end tree "PF0_MSI_CAP" base ad:0x5F010000+0x50 width 30. group.long 0x00++0x0F line.long 0x00 "PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability ID Next Pointer Control Register" rbitfld.long 0x00 24. " PCI_PVM_SUPPORT ,PVM support" "Not supported,Supported" rbitfld.long 0x00 23. " PCI_MSI_64_BIT_ADDR_CAP ,64-bit addressing capable" "Not capable,Capable" newline bitfld.long 0x00 20.--22. " PCI_MSI_MULTIPLE_MSG_EN ,Multiple messages enable" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--19. " PCI_MSI_MULTIPLE_MSG_CAP ,Multiple message capable" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16. " PCI_MSI_EN ,MSI enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--15. 0x01 " PCI_MSI_CAP_NEXT_OFFSET ,Capability next offset" newline hexmask.long.byte 0x00 0.--7. 1. " PCI_MSI_CAP_ID ,Capability ID" line.long 0x04 "MSI_CAP_OFF_04H_REG,MSI Capability ID Next Pointer Control 04H Register" hexmask.long 0x04 2.--31. 0x04 " PCI_MSI_CAP_OFF_04H ,Capability offset" line.long 0x08 "MSI_CAP_OFF_08H_REG,MSI Capability ID Next Pointer Control 08H Register" hexmask.long.word 0x08 16.--31. 0x01 " PCI_MSI_CAP_OFF_0AH ,Capability offset 0AH" hexmask.long.word 0x08 0.--15. 0x01 " PCI_MSI_CAP_OFF_08H ,Capability offset 08H" line.long 0x0C "MSI_CAP_OFF_0CH_REG,MSI Capability ID Next Pointer Control 0CH Register" hexmask.long.word 0x0C 16.--31. 0x01 " PCI_MSI_CAP_OFF_0EH ,Capability offset 0EH" hexmask.long.word 0x0C 0.--15. 0x01 " PCI_MSI_CAP_OFF_0CH ,Capability offset 0CH" tree.end tree "PF0_PCIE_CAP" base ad:0x5F010000+0x70 width 44. rgroup.long 0x00++0x03 line.long 0x00 "PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG,PCI Express Capabilities ID Next Pointer Register" bitfld.long 0x00 25.--29. " PCIE_INT_MSG_NUM ,Interrupt message number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. " PCIE_SLOT_IMP ,Slot implemented" "Low,High" newline bitfld.long 0x00 20.--23. " PCIE_DEV_PORT_TYPE ,Device/port type" "PCI express endpoint,Legacy PCI express endpoint,,,Root port of PCI express root complex,Upstream port of PCI express switch,Downstream port of PCI express switch,PCI express to PCI/PCI-X bridge,PCI/PCI-X to PCI express bridge,Root complex integrated endpoint,Root complex event collector,?..." bitfld.long 0x00 16.--19. " PCIE_CAP_REG ,Capability version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 0x01 " PCIE_CAP_NEXT_PTR ,Next item pointer" hexmask.long.byte 0x00 0.--7. 1. " PCIE_CAP_ID ,Capability ID" newline width 36. rgroup.long 0x04++0x03 line.long 0x00 "DEVICE_CAPABILITIES_REG,Device Capabilities Register" bitfld.long 0x00 15. " PCIE_CAP_ROLE_BASED_ERR_REPORT ,Role based error reporting" "No error,Error" bitfld.long 0x00 5. " PCIE_CAP_EXT_TAG_SUPP ,Extended tag field support" "5 bit,8 bit" newline bitfld.long 0x00 3.--4. " PCIE_CAP_PHANTOM_FUNC_SUPP ,Phantom functions support" "No bits,The most significant bit,The two most significant bits,All 3 bits" bitfld.long 0x00 0.--2. " PCIE_CAP_MAX_PAYLOAD_SIZE ,Max payload size in bytes" "128,256,512,1024,2048,4096,?..." group.long 0x08++0x0B line.long 0x00 "DEVICE_CONTROL_DEVICE_STATUS,Device Control And Status Register" rbitfld.long 0x00 21. " PCIE_CAP_TRANS_PEND ,Transactions pending" "Completed,Uncompleted" rbitfld.long 0x00 20. " PCIE_CAP_AUX_POWER_DET ,AUX power detected" "Not detected,Detected" newline bitfld.long 0x00 19. " PCIE_CAP_UNSUPP_REQ_DET ,Unsupported request detected" "Not detected,Detected" bitfld.long 0x00 18. " PCIE_CAP_FATAL_ERR_DET ,Fatal error detected" "Not detected,Detected" newline bitfld.long 0x00 17. " PCIE_CAP_NON_FATAL_ERR_DET ,Non-fatal error detected" "Not detected,Detected" bitfld.long 0x00 16. " PCIE_CAP_CORR_ERR_DET ,Correctable error detected" "Not detected,Detected" newline bitfld.long 0x00 15. " PCIE_CAP_INIT_FLR ,Initiate function level reset" "Disabled,Enabled" bitfld.long 0x00 12.--14. " PCIE_CAP_MAX_READ_REQ_SIZE ,Maximum read request size in bytes" "128,256,512,1024,2048,4096,?..." newline bitfld.long 0x00 11. " PCIE_CAP_EN_NO_SNOOP ,Enable no snoop" "Disabled,Enabled" bitfld.long 0x00 10. " PCIE_CAP_AUX_POWER_PM_EN ,Auxiliary power PM enable" "Disabled,Enabled" newline rbitfld.long 0x00 9. " PCIE_CAP_PHANTOM_FUNC_EN ,Phantom functions support" "Not supported,Supported" rbitfld.long 0x00 8. " PCIE_CAP_EXT_TAG_EN ,Extended tag field support" "Not supported,Supported" newline bitfld.long 0x00 5.--7. " PCIE_CAP_MAX_PAYLOAD_SIZE_CS ,Maximum payload size supported in bytes" "128,256,512,1024,2048,4096,?..." bitfld.long 0x00 4. " PCIE_CAP_EN_REL_ORDER ,Enable relaxed ordering" "Disabled,Enabled" newline bitfld.long 0x00 3. " PCIE_CAP_UNSUPPORT_REQ_REP_EN ,Unsupported request reporting enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCIE_CAP_FATAL_ERR_REPORT_EN ,Fatal error detected" "Not detected,Detected" newline bitfld.long 0x00 1. " PCIE_CAP_NON_FATAL_ERR_REPORT_EN ,Non-fatal error detected" "Not detected,Detected" bitfld.long 0x00 0. " PCIE_CAP_CORR_ERR_REPORT_EN ,Correctable error detected" "Not detected,Detected" line.long 0x04 "LINK_CAPABILITIES_REG,Link Capabilities Register" hexmask.long.byte 0x04 24.--31. 1. " PCIE_CAP_PORT_NUM ,Port number" rbitfld.long 0x04 22. " PCIE_CAP_ASPM_OPT_COMPL ,ASPM optionality compliance" "Not compliant,Compliant" newline rbitfld.long 0x04 21. " PCIE_CAP_LINK_BW_NOT_CAP ,Link bandwidth notification capable" "Not capable,Capable" rbitfld.long 0x04 20. " PCIE_CAP_DLL_ACTIVE_REP_CAP ,Data link layer link active reporting capable" "Not capable,Capable" newline rbitfld.long 0x04 19. " PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP ,Surprise down error reporting capable" "Not capable,Capable" rbitfld.long 0x04 18. " PCIE_CAP_CLK_POWER_MAN ,Clock power management" "0,1" newline bitfld.long 0x04 15.--17. " PCIE_CAP_L1_EXIT_LAT ,L1 exit latency" "<1us,<1us:2us),<2us:4us),<4us:8us),<8us:16us),<16us:32us),<32us:64us),64us<" bitfld.long 0x04 12.--14. " PCIE_CAP_L0S_EXIT_LAT ,L0s exit latency" "<64ns,<64ns:128ns),<128ns:256ns),<256ns:512ns),<512ns:1us),<1us:2us),<2us:4us),4us<" newline rbitfld.long 0x04 10.--11. " PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPP ,Active state link PM support" "No support,L0s,L1,L0s and L1" rbitfld.long 0x04 4.--9. " PCIE_CAP_MAX_LINK_WIDTH ,Maximum link width supported by the port" ",x1,x2,,x4,,,,x8,,,,x12,,,,x16,,,,,,,,,,,,,,,,x32,?..." newline bitfld.long 0x04 0.--3. " PCIE_CAP_MAX_LINK_SPEED ,Maximum link speed" ",0,1,2,3,4,5,6,?..." line.long 0x08 "LINK_CONTROL_LINK_STATUS_REG,Link Control And Status Register" bitfld.long 0x08 31. " PCIE_CAP_LINK_AUTO_BW_STAT ,Link autonomous bandwidth status" "0,1" bitfld.long 0x08 30. " PCIE_CAP_LINK_BW_MAN_STATUS ,Link bandwidth management status" "0,1" newline rbitfld.long 0x08 29. " PCIE_CAP_DLL_ACTIVE ,DLL active" "0,1" rbitfld.long 0x08 28. " PCIE_CAP_SLOT_CLK_CONFIG ,Slot clock configuration" "0,1" newline rbitfld.long 0x08 27. " PCIE_CAP_LINK_TRAIN ,Link training" "0,1" rbitfld.long 0x08 20.--25. " PCIE_CAP_NEGO_LINK_WIDTH ,Negotiated link width" ",x1,x2,,x4,,,,x8,,,,x12,,,,x16,,,,,,,,,,,,,,,,x32,?..." newline rbitfld.long 0x08 16.--19. " PCIE_CAP_LINK_SPEED ,Link speed" ",1,2,3,4,5,6,?..." rbitfld.long 0x08 14.--15. " PCIE_CAP_DRS_SIGNALING_CONTROL ,DRS signaling control" "0,1,2,3" newline bitfld.long 0x08 11. " PCIE_CAP_LINK_AUTO_BW_INT_EN ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" bitfld.long 0x08 10. " PCIE_CAP_LINK_BW_MAN_INT_EN ,Link bandwidth management interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 9. " PCIE_CAP_HW_AUTO_WIDTH_DIS ,Hardware autonomous width disable" "No,Yes" newline bitfld.long 0x08 8. " PCIE_CAP_EN_CLK_POWER_MAN ,Enable clock power management" "Disabled,Enabled" bitfld.long 0x08 7. " PCIE_CAP_EXTENDED_SYNCH ,Extended sync" "0,1" newline bitfld.long 0x08 6. " PCIE_CAP_COMMON_CLK_CONFIG ,Common clock configuration" "0,1" bitfld.long 0x08 5. " PCIE_CAP_RETRAIN_LINK ,Retrain link" "0,1" newline bitfld.long 0x08 4. " PCIE_CAP_LINK_DIS ,Link disable" "No,Yes" rbitfld.long 0x08 3. " PCIE_CAP_RCB ,Read completion boundary in byte" "64,128" newline bitfld.long 0x08 0.--1. " PCIE_CAP_ACTIVE_STATE_LINK_PM_CTRL ,Active state link PM control" "Disabled,L0s,L1,L0s and L1" rgroup.long 0x14++0x03 line.long 0x00 "SLOT_CAPABILITIES_REG,Slot Capabilities Register" hexmask.long.word 0x00 19.--31. 1. " PCIE_CAP_PHY_SLOT_NUM ,PHY slot number" bitfld.long 0x00 18. " PCIE_CAP_NO_CMD_CPL_SUPP ,No command completion support" "Not supported,Supported" newline bitfld.long 0x00 17. " PCIE_CAP_ELECTROMECH_INTERLOCK ,Electromechanical interlock present" "0,1" bitfld.long 0x00 15.--16. " PCIE_CAP_SLOT_POWER_LIMIT_SCALE ,Slot power limit scale" "1.0x,0.1x,0.01x,0.001x" newline hexmask.long.word 0x00 7.--14. 1. " PCIE_CAP_SLOT_POWER_LIMIT_VAL ,Slot power limit value" bitfld.long 0x00 6. " PCIE_CAP_HOT_PLUG_CAPABLE ,Hot plug capable" "0,1" newline bitfld.long 0x00 5. " PCIE_CAP_HOT_PLUG_SURPRISE ,Hot plug surprise" "0,1" bitfld.long 0x00 4. " PCIE_CAP_POWER_IND ,Power indicator" "0,1" newline bitfld.long 0x00 3. " PCIE_CAP_ATT_IND ,Attention indicator" "0,1" bitfld.long 0x00 2. " PCIE_CAP_MRL_SENSOR ,MRL sensor" "0,1" newline bitfld.long 0x00 1. " PCIE_CAP_POWER_CONTROLLER ,Power controller" "0,1" bitfld.long 0x00 0. " PCIE_CAP_ATT_IND_BUTTON ,Attention indicator button" "0,1" group.long 0x18++0x0B line.long 0x00 "SLOT_CONTROL_SLOT_STATUS,Slot Control And Status Register" bitfld.long 0x00 24. " PCIE_CAP_DLL_STATE_CHANGED ,DLL state changed" "Not changed,Changed" rbitfld.long 0x00 23. " PCIE_CAP_ELECTROMECH_INTERLOCK_STAT ,Electromechanical interlock status" "0,1" newline rbitfld.long 0x00 22. " PCIE_CAP_PRESENCE_DET_STATE ,Presence detect state" "Not detected,Detected" rbitfld.long 0x00 21. " PCIE_CAP_MRL_SENSOR_STATE ,MRL sensor state" "0,1" newline bitfld.long 0x00 20. " PCIE_CAP_CMD_CPLD ,Command CPLD" "Disengaged,Engaged" bitfld.long 0x00 19. " PCIE_CAP_PRESENCE_DET_CHANGED ,Presence detect changed" "Slot empty,Card present" newline bitfld.long 0x00 18. " PCIE_CAP_MRL_SENSOR_CHANGED ,MRL sensor changed" "Closed,Open" bitfld.long 0x00 17. " PCIE_CAP_POWER_FAULT_DET ,Power fault detect" "Not detected,Detected" newline bitfld.long 0x00 16. " PCIE_CAP_ATT_BUTTON_PRESSED ,Attention button pressed" "Not pressed,Pressed" bitfld.long 0x00 12. " PCIE_CAP_DLL_STATE_CHANGED_EN ,Data link layer state changed enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL ,Electromechanical interlock control" "0,1" bitfld.long 0x00 10. " PCIE_CAP_POWER_CONTROLLER_CTRL ,Power controller control" "On,Off" newline bitfld.long 0x00 8.--9. " PCIE_CAP_POWER_IND_CTRL ,Power indicator control" ",On,Blink,Off" bitfld.long 0x00 6.--7. " PCIE_CAP_ATT_IND_CTRL ,Attention indicator control" ",On,Blink,Off" newline bitfld.long 0x00 5. " PCIE_CAP_HOT_PLUG_INT_EN ,Hot plug indicator enable" "Disabled,Enabled" bitfld.long 0x00 4. " PCIE_CAP_CMD_CPL_INT_EN ,Command CPL indicator enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PCIE_CAP_PRESENCE_DET_CHANGE_EN ,Presence detect changed enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCIE_CAP_SENSOR_CHANGED_EN ,Sensor changed enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " PCIE_CAP_POWER_FAULT_DET_EN ,Power fault detect enable" "Disabled,Enabled" bitfld.long 0x00 0. " PCIE_CAP_ATT_BUTTON_PRESSED_EN ,Attention button pressed enable" "Disabled,Enabled" line.long 0x04 "ROOT_CONTROL_ROOT_CAPABILITIES_REG,Root Control And Capabilities Register" rbitfld.long 0x04 16. " PCIE_CAP_CRS_SW_VISIB ,CRS software visibility capable" "0,1" rbitfld.long 0x04 4. " PCIE_CAP_CRS_SW_VISIB_EN ,Configuration request retry status (CRS) software visibility enable" "Disabled,Enabled" newline bitfld.long 0x04 3. " PCIE_CAP_PME_INT_EN ,PME interrupt enable" "Disabled,Enabled" bitfld.long 0x04 2. " PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN ,System error on fatal error enable" "Disabled,Enabled" newline bitfld.long 0x04 1. " PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN ,System error on non-fatal error enable" "Disabled,Enabled" bitfld.long 0x04 0. " PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN ,System error on correctable error enable" "Disabled,Enabled" line.long 0x08 "ROOT_STATUS_REG,Root Status Register" rbitfld.long 0x08 17. " PCIE_CAP_PME_PEND ,PME pending" "Not pending,Pending" bitfld.long 0x08 16. " PCIE_CAP_PME_STATUS ,PME status" "0,1" newline hexmask.long.word 0x08 0.--15. 1. " PCIE_CAP_PME_REQ_ID ,PME request ID" rgroup.long 0x24++0x03 line.long 0x00 "DEVICE_CAPABILITIES2_REG,Device Capabilities 2 Register" bitfld.long 0x00 18.--19. " PCIE_CAP_OBFF_SUPP ,Optimized buffer flush/fill supported" "Not Supported,Message signaling,WAKE# signaling,Both" bitfld.long 0x00 14.--15. " PCIE_CAP2_LN_SYS_CLS ,LN system CLS" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PCIE_CAP_TPH_CMPLT_SUPP ,PPH completer supported" "None,TPH,,TPH and extended TPH" bitfld.long 0x00 11. " PCIE_CAP_LTR_SUPP ,PLTR mechanism supported" "0,1" newline bitfld.long 0x00 10. " PCIE_CAP_NO_RO_EN_PR2PR_PAR ,No relaxed ordering enabled PR-PR passing" "0,1" bitfld.long 0x00 9. " PCIE_CAP_128_CAS_CPL_SUPP ,128 atomic CAS support" "Not supported,Supported" newline bitfld.long 0x00 8. " PCIE_CAP_64_ATOMIC_CPL_SUPP ,64 atomic support" "Not supported,Supported" bitfld.long 0x00 7. " PCIE_CAP_32_ATOMIC_CPL_SUPP ,32 atomic support" "Not supported,Supported" newline bitfld.long 0x00 6. " PCIE_CAP_ATOMIC_ROUTING_SUPP ,Atomic routing support" "Not supported,Supported" bitfld.long 0x00 5. " PCIE_CAP_ARI_FORWARD_SUPP ,ARI forward support" "Not supported,Supported" newline bitfld.long 0x00 4. " PCIE_CAP_CPL_TIMEOUT_DIS_SUPP ,CPL timeout disable support" "Not supported,Supported" bitfld.long 0x00 0.--3. " PCIE_CAP_CPL_TIMEOUT_RANGE ,CPL timeout range" ",A,B,A and B,,,B and C,A and B and C,,,,,,,B and C and D,A and B and C and D" group.long 0x28++0x03 line.long 0x00 "DEVICE_CONTROL2_DEVICE_STATUS2_REG,Device Control 2 And Status 2 Register" bitfld.long 0x00 9. " PCIE_CAP_IDO_CPL_EN ,IDO completion enable" "Disabled,Enabled" bitfld.long 0x00 8. " PCIE_CAP_IDO_REQ_EN ,IDO request enable" "Disabled,Enabled" newline rbitfld.long 0x00 5. " PCIE_CAP_ARI_FORWARD_SUPP_CS ,ARI forwarding enable" "Disabled,Enabled" bitfld.long 0x00 4. " PCIE_CAP_CPL_TIMEOUT_DIS ,CPL timeout disable" "No,Yes" newline bitfld.long 0x00 0.--3. " PCIE_CAP_CPL_TIMEOUT_VAL ,CPL timeout value" "<50us:50ms>,<50us:100us>,<1ms:10ms>,,,<16ms:55ms>,<65ms:210ms>,,,<260ms:900ms>,<1s:3.5s>,,,<4s:13s>,<17s:64s>,?..." rgroup.long 0x2C++0x03 line.long 0x00 "LINK_CAPABILITIES2_REG,Link Capabilities 2 Register" bitfld.long 0x00 31. " DRS_SUPPORTED ,DRS supported" "Not supported,Supported" bitfld.long 0x00 8. " PCIE_CAP_CROSS_LINK_SUPP ,Cross link support" "Not supported,Supported" newline hexmask.long.byte 0x00 1.--7. 1. " PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR ,Supported link speed vector" group.long 0x30++0x03 line.long 0x00 "LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 And Status 2 Register" rbitfld.long 0x00 31. " DRS_MESSAGE_RECEIVED ,DRS message received" "0,1" rbitfld.long 0x00 28.--30. " DOWNSTREAM_COMPO_PRESENCE ,Downstream component presence" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 21. " PCIE_CAP_LINK_EQ_REQ ,Link equalization request 8.0GT/s" "0,1" rbitfld.long 0x00 20. " PCIE_CAP_EQ_CPL_P3 ,Equalization 8.0GT/s phase 3 successful" "Unsuccessful,Successful" newline rbitfld.long 0x00 19. " PCIE_CAP_EQ_CPL_P2 ,Equalization 8.0GT/s phase 2 successful" "Unsuccessful,Successful" rbitfld.long 0x00 18. " PCIE_CAP_EQ_CPL_P1 ,Equalization 8.0GT/s phase 1 successful." "Unsuccessful,Successful" newline rbitfld.long 0x00 17. " PCIE_CAP_EQ_PCL ,Equalization 8.0GT/s complete" "Not completed,Completed" rbitfld.long 0x00 16. " PCIE_CAP_CURR_DEEMPHASIS ,Current de-emphasis level" "-6 dB,-3.5 dB" newline bitfld.long 0x00 12.--15. " PCIE_CAP_COMP_PRESET ,Compliance preset" "-6 dB,-3.5 dB,?..." bitfld.long 0x00 11. " PCIE_CAP_COMP_SOS ,Compliance SOS" "0,1" newline bitfld.long 0x00 10. " PCIE_CAP_ENTER_MODIFIED_COMP ,Enter modified compliance" "0,1" bitfld.long 0x00 7.--9. " PCIE_CAP_TX_MARGIN ,Controls transmit margin for debug or compliance" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 6. " PCIE_CAP_SEL_DEEMPHASIS ,Select de-emphasis" "-6 dB,-3.5 dB" bitfld.long 0x00 5. " PCIE_CAP_HW_AUTO_SPEED_DIS ,Hardware autonomous speed disable" "No,Yes" newline bitfld.long 0x00 4. " PCIE_CAP_ENTER_COMP ,Enter compliance mode" "0,1" bitfld.long 0x00 0.--3. " PCIE_CAP_TARGET_LINK_SPEED ,Target link speed" ",1,2,3,4,5,6,?..." tree.end tree "PF0_AER_CAP" base ad:0x5F010000+0x100 width 23. rgroup.long 0x00++0x03 line.long 0x00 "AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header Register" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_OFFSET ,Next offset" bitfld.long 0x00 16.--19. " CAP_VER ,Capability version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--15. 1. " CAP_ID ,Capability ID" group.long 0x04++0x17 line.long 0x00 "UNCORR_ERR_STATUS_OFF,Uncorrectable Error Status Register" bitfld.long 0x00 25. " TLP_PRFX_BLOCKED_ERR_STAT ,TLP_PRFX blocked error status" "No error,Error" bitfld.long 0x00 22. " INT_ERR_STAT ,Internal error status" "No error,Error" newline bitfld.long 0x00 20. " UNSUPP_REQ_ERR_STAT ,Unsupported request status" "No error,Error" bitfld.long 0x00 19. " ECRC_ERR_STAT ,ECRC error status" "No error,Error" newline bitfld.long 0x00 18. " MALF_TLP_ERR_STAT ,Malformed TLP error status" "No error,Error" bitfld.long 0x00 17. " REC_OVRFL_ERR_STAT ,Rec overflow error status" "No error,Error" newline bitfld.long 0x00 16. " UNEXP_CMPLT_ERR_STAT ,Unexpected completion error status" "No error,Error" bitfld.long 0x00 15. " CMPLT_ABORT_ERR_STAT ,Completer abort error status" "No error,Error" newline bitfld.long 0x00 14. " CMPLT_TIMEOUT_ERR_STAT ,Completion timeout error status" "No error,Error" bitfld.long 0x00 13. " FC_PROT_ERR_STAT ,FC protocol error status" "No error,Error" newline bitfld.long 0x00 12. " POIS_TLP_ERR_STAT ,Poisoned TLP error status" "No error,Error" bitfld.long 0x00 5. " SUR_DWN_ERR_STAT ,SUR down error status" "No error,Error" newline bitfld.long 0x00 4. " DL_PROT_ERR_STAT ,Data link protocol error status" "No error,Error" line.long 0x04 "UNCORR_ERR_MASK_OFF,Uncorrectable Error Mask Register" rbitfld.long 0x04 25. " TLP_PRFX_BLOCKED_ERR_MASK ,TLP prefix blocked error mask" "Not masked,Masked" rbitfld.long 0x04 24. " ATOMIC_EGRESS_BLOCKED_ERR_MASK ,ATOMIC_EGRESS blocked error mask" "Not masked,Masked" newline bitfld.long 0x04 22. " INTERNAL_ERR_MASK ,Internal error mask" "Not masked,Masked" bitfld.long 0x04 20. " UNSUPP_REQ_ERR_MASK ,Unsupported request error mask" "Not masked,Masked" newline bitfld.long 0x04 19. " ECRC_ERR_MASK ,ECRC error mask" "Not masked,Masked" bitfld.long 0x04 18. " MALF_TLP_ERR_MASK ,Malformed TLP mask" "Not masked,Masked" newline bitfld.long 0x04 17. " REC_OVRF_ERR_MASK ,Rec overflow error mask" "Not masked,Masked" bitfld.long 0x04 16. " UNEXP_CMPLT_ERR_MASK ,Unexpected completion mask" "Not masked,Masked" newline bitfld.long 0x04 15. " CMPLT_ABORT_ERR_MASK ,Completer abort mask" "Not masked,Masked" bitfld.long 0x04 14. " CMPLT_TIMEOUT_ERR_MASK ,Completion timeout mask" "Not masked,Masked" newline bitfld.long 0x04 13. " FC_PROT_ERR_MASK ,FC protocol error mask" "Not masked,Masked" bitfld.long 0x04 12. " POIS_TLP_ERR_ERR_MASK ,Poisoned TLP error mask" "Not masked,Masked" newline rbitfld.long 0x04 5. " SUR_DWN_ERR_MASK ,SUR_DWN error mask" "Not masked,Masked" bitfld.long 0x04 4. " DL_PROT_ERR_MASK ,Data link protocol error mask" "Not masked,Masked" line.long 0x08 "UNCORR_ERR_SEV_OFF,Uncorrectable Error Severity Register" rbitfld.long 0x08 25. " TLP_PRFX_BLOCKED_ERR_SEV ,TLP prefix blocked error severity" "Not occurred,Occurred" rbitfld.long 0x08 24. " ATOMIC_EGRESS_BLOCKED_ERR_SEV ,ATOMIC_EGRESS blocked error severity" "Not occurred,Occurred" newline bitfld.long 0x08 22. " INT_ERR_SEV ,Internal error severity" "Not occurred,Occurred" bitfld.long 0x08 20. " UNSUPP_REQ_ERR_SEV ,Unsupported request error severity" "Not occurred,Occurred" newline bitfld.long 0x08 19. " ECRC_ERR_SEV ,ECRC error severity" "Not occurred,Occurred" bitfld.long 0x08 18. " MALF_TLP_ERR_SEV ,Malformed TLP severity" "Not occurred,Occurred" newline bitfld.long 0x08 17. " REC_OVRF_ERR_SEV ,Rec overflow error severity" "Not occurred,Occurred" bitfld.long 0x08 16. " UNEXP_CMPLT_ERR_SEV ,Unexpected completion severity" "Not occurred,Occurred" newline bitfld.long 0x08 15. " CMPLT_ABORT_ERR_SEV ,Completer abort severity" "Not occurred,Occurred" bitfld.long 0x08 14. " CMPLT_TIMEOUT_ERR_SEV ,Completion timeout severity" "Not occurred,Occurred" newline bitfld.long 0x08 13. " FC_PROT_ERR_SEV ,FC protocol error severity" "Not occurred,Occurred" bitfld.long 0x08 12. " POIS_TLP_ERR_ERR_SEV ,Poisoned TLP error severity" "Not occurred,Occurred" newline rbitfld.long 0x08 5. " SUR_DWN_ERR_SEV ,SUR_DWN error severity" "Not occurred,Occurred" bitfld.long 0x08 4. " DL_PROT_ERR_SEV ,Data link protocol error severity" "Not occurred,Occurred" line.long 0x0C "CORR_ERR_STATUS_OFF,Correctable Error Status Register" bitfld.long 0x0C 15. " HEADER_LOG_OVERFLOW_STATUS ,Header log overflow error status" "Not occurred,Occurred" bitfld.long 0x0C 14. " CORRECTED_INT_ERR_STAT ,Corrected internal error status" "Not occurred,Occurred" newline bitfld.long 0x0C 13. " ADV_NON_FATAL_ERR_STAT ,Advisory non-fatal error status" "Not occurred,Occurred" bitfld.long 0x0C 12. " RPL_TIMER_TIMEOUT_STAT ,Replay timer timeout status" "Not occurred,Occurred" newline bitfld.long 0x0C 8. " RPL_NO_ROLLOVER_STAT ,Replay number rollover status" "Not occurred,Occurred" bitfld.long 0x0C 7. " BAD_DLLP_STAT ,Bad DLLP status" "Not occurred,Occurred" newline bitfld.long 0x0C 6. " BAD_TLP_STAT ,Bad TLP status" "Not occurred,Occurred" bitfld.long 0x0C 0. " RX_ERR_STAT ,Receiver error status" "Not occurred,Occurred" line.long 0x10 "CORR_ERR_MASK_OFF,Correctable Error Mask Register" bitfld.long 0x10 15. " HEADER_LOG_OVERFLOW_MASK ,Header log overflow error mask" "Not occurred,Occurred" bitfld.long 0x10 14. " CORRECTED_INT_ERR_MASK ,Corrected internal error mask" "Not masked,Masked" newline bitfld.long 0x10 13. " ADV_NON_FATAL_ERR_MASK ,Advisory non-fatal error mask" "Not masked,Masked" bitfld.long 0x10 12. " RPL_TIMER_TIMEOUT_MASK ,Replay timer timeout mask" "Not masked,Masked" newline bitfld.long 0x10 8. " RPL_NO_ROLLOVER_MASK ,Replay number rollover mask" "Not masked,Masked" bitfld.long 0x10 7. " BAD_DLLP_MASK ,Bad DLLP mask" "Not masked,Masked" newline bitfld.long 0x10 6. " BAD_TLP_MASK ,Bad TLP mask" "Not masked,Masked" bitfld.long 0x10 0. " RX_ERR_MASK ,Receiver error mask" "Not masked,Masked" line.long 0x14 "ADV_ERR_CAP_CTRL_OFF,Advanced Error Capabilities And Control Register" rbitfld.long 0x14 10. " MULTIPLE_HEADER_EN ,Multiple header recording enable" "Disabled,Enabled" rbitfld.long 0x14 9. " MULTIPLE_HEADER_CAP ,Multiple header recording capable" "0,1" newline bitfld.long 0x14 8. " ECRC_CHECK_EN ,ECRC check enable" "Disabled,Enabled" rbitfld.long 0x14 7. " ECRC_CHECK_CAP ,ECRC check capable" "0,1" newline bitfld.long 0x14 6. " ECRC_GEN_EN ,ECRC generation enable" "Disabled,Enabled" newline rbitfld.long 0x14 5. " ECRC_GEN_CAP ,ECRC generation capable" "0,1" rbitfld.long 0x14 0.--4. " FIRST_ERR_PTR ,First error pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x1C++0x0F line.long 0x00 "HDR_LOG_0_OFF,Header Log Register 0" hexmask.long.byte 0x00 24.--31. 1. " FIRST_DWORD_FOURTH_BYTE ,Byte 3 of header log register of first 32 bit data word" hexmask.long.byte 0x00 16.--23. 1. " FIRST_DWORD_THIRD_BYTE ,Byte 2 of header log register of first 32 bit data word" newline hexmask.long.byte 0x00 8.--15. 1. " FIRST_DWORD_SECOND_BYTE ,Byte 1 of header log register of first 32 bit data word" hexmask.long.byte 0x00 0.--7. 1. " FIRST_DWORD_FIRST_BYTE_BYTE ,Byte 0 of header log register of first 32 bit data word" line.long 0x04 "HDR_LOG_1_OFF,Header Log Register 1" hexmask.long.byte 0x04 24.--31. 1. " SECOND_DWORD_FOURTH_BYTE ,Byte 3 of header log register of second 32 bit data word" hexmask.long.byte 0x04 16.--23. 1. " SECOND_DWORD_THIRD_BYTE ,Byte 2 of header log register of second 32 bit data word" newline hexmask.long.byte 0x04 8.--15. 1. " SECOND_DWORD_SECOND_BYTE ,Byte 1 of header log register of second 32 bit data word" hexmask.long.byte 0x04 0.--7. 1. " SECOND_DWORD_FIRST_BYTE ,Byte 0 of header log register of second 32 bit data word" line.long 0x08 "HDR_LOG_2_OFF,Header Log Register 2" hexmask.long.byte 0x08 24.--31. 1. " THIRD_DWORD_FOURTH_BYTE ,Byte 3 of header log register of third 32 bit data word" hexmask.long.byte 0x08 16.--23. 1. " THIRD_DWORD_THIRD_BYTE ,Byte 2 of header log register of third 32 bit data word" newline hexmask.long.byte 0x08 8.--15. 1. " THIRD_DWORD_SECOND_BYTE ,Byte 1 of header log register of third 32 bit data word" hexmask.long.byte 0x08 0.--7. 1. " THIRD_DWORD_FIRST_BYTE ,Byte 0 of header log register of third 32 bit data word" line.long 0x0C "HDR_LOG_3_OFF,Header Log Register 3" hexmask.long.byte 0x0C 24.--31. 1. " FOURTH_DWORD_FOURTH_BYTE ,Byte 3 of header log register of fourth 32 bit data word" hexmask.long.byte 0x0C 16.--23. 1. " FOURTH_DWORD_THIRD_BYTE ,Byte 2 of header log register of fourth 32 bit data word" newline hexmask.long.byte 0x0C 8.--15. 1. " FOURTH_DWORD_SECOND_BYTE ,Byte 1 of header log register of fourth 32 bit data word" hexmask.long.byte 0x0C 0.--7. 1. " FOURTH_DWORD_FIRST_BYTE ,Byte 0 of header log register of fourth 32 bit data word" group.long 0x2C++0x07 line.long 0x00 "ROOT_ERR_CMD_OFF,Root Error Command Register" bitfld.long 0x00 2. " FATAL_ERR_REP_EN ,Fatal error reporting enable" "Disabled,Enabled" bitfld.long 0x00 1. " NON_FATAL_ERR_REP_EN ,Non-fatal error reporting enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " CORR_ERR_REP_EN ,Correctable error reporting enable" "Disabled,Enabled" line.long 0x04 "ROOT_ERR_STATUS_OFF,Root Error Status Register" bitfld.long 0x04 27.--31. " ADV_ERR_INT_MSG_NUM ,Advanced error interrupt message number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 6. " FATAL_ERR_MSG_RX ,Fatal error messages received" "Not received,Received" newline bitfld.long 0x04 5. " NON_FATAL_ERR_MSG_RX ,Non-fatal error messages received" "Not received,Received" bitfld.long 0x04 4. " FIRST_UNCORR_FATAL ,First uncorrectable fatal" "Not received,Received" newline bitfld.long 0x04 3. " MUL_ERR_FATAL_NON_FATAL_RX ,Multiple err_fatal/nonfatal received" "Not received,Received" bitfld.long 0x04 2. " ERR_FATAL_NON_FATAL_RX ,Err_fatal/nonfatal received" "Not received,Received" newline bitfld.long 0x04 1. " MUL_ERR_COR_RX ,Multiple err_cor received" "Not received,Received" bitfld.long 0x04 0. " ERR_COR_RX ,Err_cor received" "Not received,Received" rgroup.long 0x34++0x13 line.long 0x00 "ERR_SRC_ID_OFF,Error Source Identification Register" hexmask.long.word 0x00 16.--31. 1. " ERR_FATAL_NON_FATAL_SRC_ID ,Err_fatal/nonfatal source identification" hexmask.long.word 0x00 0.--15. 1. " ERR_COR_SRC_ID ,Err_cor source identification" line.long 0x04 "TLP_PREFIX_LOG_1_OFF,TLP Prefix Log Register 1" hexmask.long.byte 0x04 24.--31. 1. " CFG_TLP_PFX_LOG_1_FOURTH_BYTE ,Byte 3 of error TLP prefix log 1" hexmask.long.byte 0x04 16.--23. 1. " CFG_TLP_PFX_LOG_1_THIRD_BYTE ,Byte 2 of error TLP prefix log 1" newline hexmask.long.byte 0x04 8.--15. 1. " CFG_TLP_PFX_LOG_1_SECOND_BYTE ,Byte 1 of error TLP prefix log 1" hexmask.long.byte 0x04 0.--7. 1. " CFG_TLP_PFX_LOG_1_FIRST_BYTE ,Byte 0 of error TLP prefix log 1" line.long 0x08 "TLP_PREFIX_LOG_2_OFF,TLP Prefix Log Register 2" hexmask.long.byte 0x08 24.--31. 1. " CFG_TLP_PFX_LOG_2_FOURTH_BYTE ,Byte 3 of error TLP prefix log 2" hexmask.long.byte 0x08 16.--23. 1. " CFG_TLP_PFX_LOG_2_THIRD_BYTE ,Byte 2 of error TLP prefix log 2" newline hexmask.long.byte 0x08 8.--15. 1. " CFG_TLP_PFX_LOG_2_SECOND_BYTE ,Byte 1 of error TLP prefix log 2" hexmask.long.byte 0x08 0.--7. 1. " CFG_TLP_PFX_LOG_2_FIRST_BYTE ,Byte 0 of error TLP prefix log 2" line.long 0x0C "TLP_PREFIX_LOG_3_OFF,TLP Prefix Log Register 3" hexmask.long.byte 0x0C 24.--31. 1. " CFG_TLP_PFX_LOG_3_FOURTH_BYTE ,Byte 3 of error TLP prefix log 3" hexmask.long.byte 0x0C 16.--23. 1. " CFG_TLP_PFX_LOG_3_THIRD_BYTE ,Byte 2 of error TLP prefix log 3" newline hexmask.long.byte 0x0C 8.--15. 1. " CFG_TLP_PFX_LOG_3_SECOND_BYTE ,Byte 1 of error TLP prefix log 3" hexmask.long.byte 0x0C 0.--7. 1. " CFG_TLP_PFX_LOG_3_FIRST_BYTE ,Byte 0 of error TLP prefix log 3" line.long 0x10 "TLP_PREFIX_LOG_4_OFF,TLP Prefix Log Register 4" hexmask.long.byte 0x10 24.--31. 1. " CFG_TLP_PFX_LOG_4_FOURTH_BYTE ,Byte 3 of error TLP prefix log 4" hexmask.long.byte 0x10 16.--23. 1. " CFG_TLP_PFX_LOG_4_THIRD_BYTE ,Byte 2 of error TLP prefix log 4" newline hexmask.long.byte 0x10 8.--15. 1. " CFG_TLP_PFX_LOG_4_SECOND_BYTE ,Byte 1 of error TLP prefix log 4" hexmask.long.byte 0x10 0.--7. 1. " CFG_TLP_PFX_LOG_4_FIRST_BYTE ,Byte 0 of error TLP prefix log 4" newline tree.end tree "PF0_SPCIE_CAP" base ad:0x5F010000+0x148 width 23. rgroup.long 0x00++0x03 line.long 0x00 "SPCIE_CAP_HEADER_REG,SPCIE Capability Header" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_OFFSET ,Next offset" bitfld.long 0x00 16.--19. " CAP_VER ,Capability version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--15. 1. " EX_CAP_ID ,Extended capability ID" group.long 0x04++0x07 line.long 0x00 "LINK_CONTROL3_REG,Link Control 3 Register" bitfld.long 0x00 1. " EQ_REQ_INT_EN ,Link equalization request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PERFORM_EQ ,Perform equalization" "0,1" line.long 0x04 "LANE_ERR_STATUS_REG,Lane Error Status Register" bitfld.long 0x04 1. " LANE_ERR_STAT[1] ,Lane 1 error status" "No error,Error" bitfld.long 0x04 0. " [0] ,Lane 0 error status" "No error,Error" rgroup.long 0x0C++0x03 line.long 0x00 "SPCIE_CAP_OFF_0CH_REG,Lane Equalization Control Register For Lanes 1 And 0" bitfld.long 0x00 28.--30. " USP_RX_PRESET_HINT1 ,Upstream port 8.0 GT/s receiver preset hint" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--27. " USP_TX_PRESET1 ,Upstream port 8.0 GT/s transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--22. " DSP_RX_PRESET_HINT1 ,Downstream port 8.0 GT/s receiver preset hint" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " DSP_TX_PRESET1 ,Downstream port 8.0 GT/s transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--14. " USP_RX_PRESET_HINT0 ,Upstream port 8.0 GT/s receiver preset hint" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--11. " USP_TX_PRESET0 ,Upstream port 8.0 GT/s transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--6. " DSP_RX_PRESET_HINT0 ,Downstream port 8.0 GT/s receiver preset hint" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--3. " DSP_TX_PRESET0 ,Downstream port 8.0 GT/s transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "PF0_L1SUB_CAP" base ad:0x5F010000+0x168 width 22. rgroup.long 0x00++0x03 line.long 0x00 "L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_OFFSET ,Next offset" bitfld.long 0x00 16.--19. " CAP_VER ,Capability version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--15. 1. " EX_CAP_ID ,Extended capability ID" group.long 0x04++0x0B line.long 0x00 "L1SUB_CAPABILITY_REG,L1 Substates Capability Register" bitfld.long 0x00 19.--23. " PWR_ON_VAL_SUPP ,Port T power on value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--17. " PWR_ON_SCALE_SUPP ,Power on scale support" "0,1,2,3" newline hexmask.long.byte 0x00 8.--15. 1. " COMM_MODE_SUPP ,Common mode support" bitfld.long 0x00 4. " L1_PMSUB_SUPP ,L1_PMSUB support" "Not supported,Supported" newline bitfld.long 0x00 3. " L1_1_ASPM_SUPP ,L1_1_ASPM support" "Not supported,Supported" bitfld.long 0x00 2. " L1_2_ASPM_SUPP ,L1_2_ASPM support" "Not supported,Supported" newline bitfld.long 0x00 1. " L1_1_PCIPM_SUPP ,L1_1_PCIPM support" "Not supported,Supported" bitfld.long 0x00 0. " L1_2_PCIPM_SUPP ,L1_2_PCIPM support" "Not supported,Supported" line.long 0x04 "L1SUB_CONTROL1_REG,L1 Substates Control 1 Register" bitfld.long 0x04 29.--31. " L1_2_TH_SCA ,LTR L12 threshold scale" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 16.--25. 1. " L1_2_TH_VAL ,LTR L12 threshold value" newline hexmask.long.byte 0x04 8.--15. 1. " T_COMMON_MODE ,Common mode restore time" bitfld.long 0x04 3. " L1_1_ASPM_EN ,L1_1_ASPM enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " L1_2_ASPM_EN ,L1_2_ASPM enable" "Disabled,Enabled" bitfld.long 0x04 1. " L1_1_PCIPM_EN ,L1_1_PCIPM enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " L1_2_PCIPM_EN ,L1_2_PCIPM enable" "Disabled,Enabled" line.long 0x08 "L1SUB_CONTROL2_REG,L1 Substates Control 2 Register" bitfld.long 0x08 3.--7. " T_POWER_ON_VAL ,T power on value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 0.--1. " T_POWER_ON_SCALE ,T power on scale" "0,1,2,3" newline tree.end tree "PF0_PORT_LOGIC" base ad:0x5F010000+0x700 width 39. group.long 0x00++0x27 line.long 0x00 "ACK_LATENCY_TIMER_OFF,Ack Latency Timer And Replay Timer Register" hexmask.long.word 0x00 16.--31. 1. " REPLAY_TIME_LIMIT ,Replay timer limit" hexmask.long.word 0x00 0.--15. 1. " ROUND_TRIP_LAT_TIME_LIMIT ,Ack latency timer limit" line.long 0x04 "VENDOR_SPEC_DLLP_OFF,Vendor Specific DLLP Register" line.long 0x08 "PORT_FORCE_OFF,Port Force Link Register" hexmask.long.byte 0x08 24.--31. 1. " CPL_SENT_COUNT ,Low power entrance count" bitfld.long 0x08 16.--21. " LINK_STATE ,Forced LTSSM state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 15. " FORCE_EN ,Force link enable" "Disabled,Enabled" bitfld.long 0x08 8.--11. " FORCED_LTSSM ,Forced link command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x08 0.--7. 1. " LINK_NUM ,Link number" line.long 0x0C "ACK_F_ASPM_CTRL_OFF,Ack Frequency And L0-L1 ASPM Control Register" bitfld.long 0x0C 30. " ENTER_ASPM ,ASPM L1 entry control" "Not entered,Entered" bitfld.long 0x0C 27.--29. " L1_ENTRANCE_LAT ,L1 entrance latency" "1 us,2 us,4 us,8 us,16 us,32 us,64 us,64 us" newline bitfld.long 0x0C 24.--26. " L0S_ENTRANCE_LAT ,L0s entrance latency" "1 us,2 us,3 us,4 us,5 us,6 us,7 us,7 us" hexmask.long.byte 0x0C 16.--23. 1. " COMMON_CLK_N_FTS ,Common clock N_FTS" newline hexmask.long.byte 0x0C 8.--15. 1. " ACK_N_FTS ,Number of fast training sequence" hexmask.long.byte 0x0C 0.--7. 1. " ACK_FREQ ,Ack frequency" line.long 0x10 "PORT_LINK_CTRL_OFF,Port Link Control Register" bitfld.long 0x10 16.--21. " LINK_CAPABLE ,Link mode enable" ",x1,,x2,,,,x4,,,,,,,,x8,,,,,,,,,,,,,,,,x16,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,x32" bitfld.long 0x10 7. " FAST_LINK_MODE ,Fast link mode" "0,1" newline bitfld.long 0x10 5. " DLL_LINK_EN ,DLL link enable" "Disabled,Enabled" bitfld.long 0x10 3. " RST_ASSERT ,Reset assert" "No reset,Reset" newline bitfld.long 0x10 2. " LP_EN ,Loopback enable" "No reset,Reset" bitfld.long 0x10 1. " SCRAMBLE_DIS ,Scramble disable" "No,Yes" newline bitfld.long 0x10 0. " VENDOR_SPEC_DLLP_REQ ,Vendor specific DLLP request" "Not requested,Requested" line.long 0x14 "LANE_SKEW_OFF,Lane Skew Register" bitfld.long 0x14 31. " DIS_LANE_TO_LANE_DESKEW ,Disable lane-to-lane deskew" "No,Yes" bitfld.long 0x14 25. " ACK_NAK_DIS ,Ack/nak disable" "No,Yes" newline bitfld.long 0x14 24. " FLOW_CTRL_DIS ,Flow control disable" "No,Yes" hexmask.long.tbyte 0x14 0.--23. 1. " INSERT_LANE_SKEW ,Insert lane skew for transmit" line.long 0x18 "TIMER_CTRL_MAX_FUNC_NUM_OFF,Timer Control And Max Function Number Register" bitfld.long 0x18 29.--30. " FAST_LINK_SCALING_FACTOR ,Fast link timer scaling factor" "1024,256,64,16" bitfld.long 0x18 19.--23. " TIMER_MOD_ACK_NAK ,Ack latency timer modifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x18 14.--18. " TIMER_MOD_REPLAY_TIMER ,Replay timer limit modifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x18 0.--7. 1. " MAX_FUNC_NUM ,Maximum function number" line.long 0x1C "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer Register And Filter Mask 1 Register" bitfld.long 0x1C 31. " CX_FLT_MASK_RC_CFG_DISCARD ,RC CFG discard mask" "Not masked,Masked" bitfld.long 0x1C 30. " CX_FLT_MASK_RC_IO_DISCARD ,RC IO discard mask" "Not masked,Masked" newline bitfld.long 0x1C 29. " CX_FLT_MASK_MSG_DROP ,Drop MSG TLP mask" "Not masked,Masked" bitfld.long 0x1C 28. " CX_FLT_MASK_CPL_ECRC_DISCARD ,Mask discarding completions with ECRC errors" "Not masked,Masked" newline bitfld.long 0x1C 27. " CX_FLT_MASK_ECRC_DISCARD ,Mask discarding TLPs with ECRC errors" "Not masked,Masked" bitfld.long 0x1C 26. " CX_FLT_MASK_CPL_LEN_MATCH ,Mask length match for completions" "Not masked,Masked" newline bitfld.long 0x1C 25. " CX_FLT_MASK_CPL_ATTR_MATCH ,Mask attribute match for completions" "Not masked,Masked" bitfld.long 0x1C 24. " CX_FLT_MASK_CPL_TC_MATCH ,Mask traffic class match for completions" "Not masked,Masked" newline bitfld.long 0x1C 23. " CX_FLT_MASK_CPL_FUNC_MATCH ,Mask function match for completions" "Not masked,Masked" bitfld.long 0x1C 22. " CX_FLT_MASK_CPL_REQID_MATCH ,Mask req ID match for completions" "Not masked,Masked" newline bitfld.long 0x1C 21. " CX_FLT_MASK_CPL_TAGERR_MATCH ,Mask tag error rules for completions" "Not masked,Masked" bitfld.long 0x1C 20. " CX_FLT_MASK_LOCKED_RD_AS_UR ,Mask treating locked read TLPs as UR for EP" "Not masked,Masked" newline bitfld.long 0x1C 19. " CX_FLT_MASK_CFG_TYPE1_RE_AS_UR ,Mask treating CFG type1 TLPs as UR for EP" "Not masked,Masked" bitfld.long 0x1C 18. " CX_FLT_MASK_UR_OUTSIDE_BAR ,Mask treating out-of-bar TLPs as UR" "Not masked,Masked" newline bitfld.long 0x1C 17. " CX_FLT_MASK_UR_POIS ,Mask treating poisoned TLPs as UR" "Not masked,Masked" bitfld.long 0x1C 16. " CX_FLT_MASK_UR_FUNC_MISMATCH ,Mask treating function mismatched TLPs as UR" "Not masked,Masked" newline hexmask.long.word 0x1C 0.--10. 1. " SKP_INT_VAL ,SKP interval value" line.long 0x20 "FILTER_MASK_2_OFF,Filter Mask 2 Register" bitfld.long 0x20 6. " CX_FLT_UNMASK_TD ,CX_FLT_UNMASK_TD" "0,1" bitfld.long 0x20 5. " CX_FLT_UNMASK_UR_POIS_TRGT0 ,CX_FLT_UNMASK_UR_POIS_TRGT0" "0,1" newline bitfld.long 0x20 4. " CX_FLT_MASK_LN_VENMSG1_DROP ,CX_FLT_MASK_LN_VENMSG1_DROP" "0,1" bitfld.long 0x20 3. " CX_FLT_MASK_HANDLE_FLUSH ,Core filter enable" "Disabled,Enabled" newline bitfld.long 0x20 2. " CX_FLT_MASK_DABORT_4UCPL ,DLLP abort for unexpected completion enable" "Disabled,Enabled" bitfld.long 0x20 1. " CX_FLT_MASK_VENMSG1_DROP ,Vendor MSG type 1 dropped silently" "Not dropped,Dropped" newline bitfld.long 0x20 0. " CX_FLT_MASK_VENMSG0_DROP ,Vendor MSG type 0 dropped with UR error reporting" "Not dropped,Dropped" line.long 0x24 "AMBAMODNPSC,AMBA Multiple Outbound Decomposed NP SubRequests Control Register" bitfld.long 0x24 0. " OB_RD_SPLIT_BURST_EN ,Enable AMBA multiple outbound decomposed NP subrequests" "Disabled,Enabled" rgroup.long 0x28++0x13 line.long 0x00 "PL_DEBUG0_OFF,Debug Register 0" line.long 0x04 "PL_DEBUG1_OFF,Debug Register 1" line.long 0x08 "TX_P_FC_CREDIT_STATUS_OFF,Transmit Posted FC Credit Status" hexmask.long.byte 0x08 12.--19. 1. " TX_P_HEADER_FC_CREDIT ,Transmit posted header FC credits" hexmask.long.word 0x08 0.--11. 1. " TX_P_DATA_FC_CREDIT ,Transmit posted data FC credits" line.long 0x0C "TX_NP_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status Register" hexmask.long.byte 0x0C 12.--19. 1. " TX_NP_HEADER_FC_CREDIT ,Transmit non-posted header FC credits" hexmask.long.word 0x0C 0.--11. 1. " TX_NP_DATA_FC_CREDIT ,Transmit non-posted data FC credits" line.long 0x10 "TX_CPL_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status Register" hexmask.long.byte 0x10 12.--19. 1. " TX_CPL_HEADER_FC_CREDIT ,Transmit completion header FC credits" hexmask.long.word 0x10 0.--11. 1. " TX_CPL_DATA_FC_CREDIT ,Transmit completion data FC credits" group.long 0x3C++0x03 line.long 0x00 "QUEUE_STATUS_OFF,Queue Status Register" bitfld.long 0x00 31. " TIMER_MOD_FLOW_CTRL_EN ,FC latency timer override enable" "Disabled,Enabled" hexmask.long.word 0x00 16.--28. 1. " TIMER_MOD_FLOW_CTRL ,FC latency timer override value" newline rbitfld.long 0x00 2. " RX_QUEUE_NON_EMPTY ,Received queue not empty" "Not received,Received" rbitfld.long 0x00 1. " TX_RETRY_BUF_NE ,Transmit retry buffer not empty" "Not received,Received" newline rbitfld.long 0x00 0. " RX_TLP_FC_CRED_NON_RET ,Received TLP FC credits not returned" "Not received,Received" rgroup.long 0x40++0x07 line.long 0x00 "VC_TX_ARBI_1_OFF,VC Transmit Arbitration Register 1" hexmask.long.byte 0x00 24.--31. 1. " WRR_WEIGHT_VC_3 ,WRR weight for VC3" hexmask.long.byte 0x00 16.--23. 1. " WRR_WEIGHT_VC_2 ,WRR weight for VC2" newline hexmask.long.byte 0x00 8.--15. 1. " WRR_WEIGHT_VC_1 ,WRR weight for VC1" hexmask.long.byte 0x00 0.--7. 1. " WRR_WEIGHT_VC_0 ,WRR weight for VC0" line.long 0x04 "VC_TX_ARBI_2_OFF,VC Transmit Arbitration Register 2" hexmask.long.byte 0x04 24.--31. 1. " WRR_WEIGHT_VC_7 ,WRR weight for VC7" hexmask.long.byte 0x04 16.--23. 1. " WRR_WEIGHT_VC_6 ,WRR weight for VC6" newline hexmask.long.byte 0x04 8.--15. 1. " WRR_WEIGHT_VC_5 ,WRR weight for VC5" hexmask.long.byte 0x04 0.--7. 1. " WRR_WEIGHT_VC_4 ,WRR weight for VC4" group.long 0x48++0x0B line.long 0x00 "VC0_P_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Posted Receive Queue Control" bitfld.long 0x00 31. " VC_ORDERING_RX_Q ,VC ordering for receive queues" "Strict,Round-robin" bitfld.long 0x00 30. " TLP_TYPE_ORDERING_VC0 ,TLP type ordering for VC0" "Strict,PCIe" newline hexmask.long.byte 0x00 12.--19. 1. " VC0_P_HEADER_CRED ,VC0 posted header credits" hexmask.long.word 0x00 0.--11. 1. " VC0_P_DATA_CRED ,VC0 posted data credits" line.long 0x04 "VC0_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Non-Posted Receive Queue Control" hexmask.long.byte 0x04 12.--19. 1. " VC0_NP_HEADER_CRED ,VC0 non-posted header credits" hexmask.long.word 0x04 0.--11. 1. " VC0_NP_DATA_CRED ,VC0 non-posted data credits" line.long 0x08 "VC0_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Completion Receive Queue Control" hexmask.long.byte 0x08 12.--19. 1. " VC0_CPL_HEADER_CRED ,VC0 completion header credits" hexmask.long.word 0x08 0.--11. 1. " VC0_CPL_DATA_CRED ,VC0 completion data credits" group.long 0x10C++0x03 line.long 0x00 "GEN2_CTRL_OFF,Link Width And Speed Change Control Register" bitfld.long 0x00 21. " GEN1_EI_INFER ,Electrical idle inference mode at Gen1 rate" "RxElecIdle,RxValid" bitfld.long 0x00 20. " SEL_DEEMPHASIS ,Select de-emphasis" "-6 dB,-3.5 dB" newline bitfld.long 0x00 19. " CONFIG_TX_COMP_RX ,Config TX compliance receive bit" "0,1" bitfld.long 0x00 18. " CONFIG_PHY_TX_CHANGE ,Config PHY TX swing" "Full,Low" newline bitfld.long 0x00 17. " DIRECT_SPEED_CHANGE ,Directed speed change" "0,1" bitfld.long 0x00 16. " AUTO_LANE_FLIP_CTRL_EN ,Enable auto flipping of the lanes" "Disabled,Enabled" newline bitfld.long 0x00 13.--15. " PRE_DET_LANE ,Predetermined lane for auto flip" "PHY L0,PHY L1,PHY L3,PHY L7,PHY L15,?..." bitfld.long 0x00 8.--12. " NUM_OF_LANES ,Predetermined number of lanes" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.byte 0x00 0.--7. 1. " FAST_TRAIN_SEQ ,Number of fast training sequences" rgroup.long 0x110++0x03 line.long 0x00 "PHY_STATUS_OFF,PHY Status Register" group.long 0x114++0x03 line.long 0x00 "PHY_CONTROL_OFF,PHY Control Register" group.long 0x120++0x07 line.long 0x00 "MSI_CTRL_ADDR_OFF,Integrated MSI Reception Module (iMRM) Address Register" line.long 0x04 "MSI_CTRL_UPPER_ADDR_OFF,Integrated MSI Reception Module Upper Address Register" group.long 0x128++0x0B line.long 0x00 "MSI_CTRL_INT_0_EN_OFF,Integrated MSI Reception Module Interrupt0 Enable Register" line.long 0x04 "MSI_CTRL_INT_0_MASK_OFF,Integrated MSI Reception Module Interrupt0 Mask Register" line.long 0x08 "MSI_CTRL_INT_0_STATUS_OFF,Integrated MSI Reception Module Interrupt0 Status Register" group.long 0x134++0x0B line.long 0x00 "MSI_CTRL_INT_1_EN_OFF,Integrated MSI Reception Module Interrupt1 Enable Register" line.long 0x04 "MSI_CTRL_INT_1_MASK_OFF,Integrated MSI Reception Module Interrupt1 Mask Register" line.long 0x08 "MSI_CTRL_INT_1_STATUS_OFF,Integrated MSI Reception Module Interrupt1 Status Register" group.long 0x140++0x0B line.long 0x00 "MSI_CTRL_INT_2_EN_OFF,Integrated MSI Reception Module Interrupt2 Enable Register" line.long 0x04 "MSI_CTRL_INT_2_MASK_OFF,Integrated MSI Reception Module Interrupt2 Mask Register" line.long 0x08 "MSI_CTRL_INT_2_STATUS_OFF,Integrated MSI Reception Module Interrupt2 Status Register" group.long 0x14C++0x0B line.long 0x00 "MSI_CTRL_INT_3_EN_OFF,Integrated MSI Reception Module Interrupt3 Enable Register" line.long 0x04 "MSI_CTRL_INT_3_MASK_OFF,Integrated MSI Reception Module Interrupt3 Mask Register" line.long 0x08 "MSI_CTRL_INT_3_STATUS_OFF,Integrated MSI Reception Module Interrupt3 Status Register" group.long 0x158++0x0B line.long 0x00 "MSI_CTRL_INT_4_EN_OFF,Integrated MSI Reception Module Interrupt4 Enable Register" line.long 0x04 "MSI_CTRL_INT_4_MASK_OFF,Integrated MSI Reception Module Interrupt4 Mask Register" line.long 0x08 "MSI_CTRL_INT_4_STATUS_OFF,Integrated MSI Reception Module Interrupt4 Status Register" group.long 0x164++0x0B line.long 0x00 "MSI_CTRL_INT_5_EN_OFF,Integrated MSI Reception Module Interrupt5 Enable Register" line.long 0x04 "MSI_CTRL_INT_5_MASK_OFF,Integrated MSI Reception Module Interrupt5 Mask Register" line.long 0x08 "MSI_CTRL_INT_5_STATUS_OFF,Integrated MSI Reception Module Interrupt5 Status Register" group.long 0x170++0x0B line.long 0x00 "MSI_CTRL_INT_6_EN_OFF,Integrated MSI Reception Module Interrupt6 Enable Register" line.long 0x04 "MSI_CTRL_INT_6_MASK_OFF,Integrated MSI Reception Module Interrupt6 Mask Register" line.long 0x08 "MSI_CTRL_INT_6_STATUS_OFF,Integrated MSI Reception Module Interrupt6 Status Register" group.long 0x17C++0x0B line.long 0x00 "MSI_CTRL_INT_7_EN_OFF,Integrated MSI Reception Module Interrupt7 Enable Register" line.long 0x04 "MSI_CTRL_INT_7_MASK_OFF,Integrated MSI Reception Module Interrupt7 Mask Register" line.long 0x08 "MSI_CTRL_INT_7_STATUS_OFF,Integrated MSI Reception Module Interrupt7 Status Register" group.long 0x188++0x07 line.long 0x00 "MSI_GPIO_IO_OFF,Integrated MSI Reception Module General Purpose IO Register" line.long 0x04 "GEN3_RELATED_OFF,Gen3 Control Register" bitfld.long 0x04 23. " GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE ,EQ invalid request and RxEqEval different time assertion disable" "No,Yes" bitfld.long 0x04 18. " GEN3_DC_BALANCE_DIS ,DC balance disable" "No,Yes" newline bitfld.long 0x04 17. " GEN3_DLLP_XMT_DEL_DIS ,DLLP transmission delay disable" "No,Yes" bitfld.long 0x04 16. " GEN3_EQUALIZ_DIS ,Equalization disable" "No,Yes" newline bitfld.long 0x04 13. " RXEQ_RGRDLESS_RXTS ,RxEqEval asserts regardless of TS" "1us,500ns" bitfld.long 0x04 12. " RXEQ_PH01_EN ,RX equalization phase 0/phase 1 hold enable" "Disabled,Enabled" newline bitfld.long 0x04 11. " EQ_REDO ,Equalization redo disable" "No,Yes" bitfld.long 0x04 10. " EQ_EIEOS_CNT ,Equalization EIEOS count reset disable" "No,Yes" newline bitfld.long 0x04 9. " EQ_PHASE_2_3 ,Equalization phase 2 and phase 3 disable" "No,Yes" bitfld.long 0x04 8. " DIS_SCRMB_GEN_3 ,Disable scrambler for gen3 and gen4 data rate" "No,Yes" newline bitfld.long 0x04 0. " GEN3_ZRXDC_NONCOMPL ,Gen3 receiver impedance ZRX-DC not compliant" "Compliant,Not compliant" group.long 0x1A8++0x03 line.long 0x00 "GEN3_EQ_CONTROL_OFF,Gen3 EQ Control Register" bitfld.long 0x00 26. " GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP ,Request core to send back-to-back EIEOS in recovery" "0,1" bitfld.long 0x00 24. " GEN3_EQ_FOM_INC_INIT_EVAL ,Include initial FOM" "Not included,Included" newline hexmask.long.word 0x00 8.--23. 1. " GEN3_EQ_PSET_REQ_VEC ,Preset request vector" bitfld.long 0x00 5. " GEN3_EQ_EVAL_2MS_DIS ,Phase2_3 2 ms timeout disable" "No,Yes" newline bitfld.long 0x00 4. " GEN3_EQ_PHASE23_EXIT_MODE ,Behavior after 24 ms timeout" "Rec.Speed,Rec.Equaliz.RcvrLock" bitfld.long 0x00 0.--3. " GEN3_EQ_FB_MODE ,Feedback mode" "Dir change,Fig of merit,?..." group.long 0x1B4++0x03 line.long 0x00 "ORDER_RULE_CTRL_OFF,Order Rule Control Register" hexmask.long.byte 0x00 8.--15. 1. " CPL_PASS_P ,Completion passing posted ordering rule control" hexmask.long.byte 0x00 0.--7. 1. " NP_PASS_P ,Non-posted passing posted ordering rule control" group.long 0x1B8++0x23 line.long 0x00 "PIPE_LOOPBACK_CONTROL_OFF,PIPE Loopback Control Register" bitfld.long 0x00 31. " PIPE_LP ,PIPE loopback enable" "Disabled,Enabled" line.long 0x04 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register" bitfld.long 0x04 0. " DBI_RO_WR_EN ,Write to RO registers using DBI enable" "Disabled,Enabled" line.long 0x08 "MULTI_LANE_CONTROL_OFF,UpConfigure Multi-lane Control Register" bitfld.long 0x08 7. " UPCONFIGURE_SUPPORT ,Upconfigure support" "0,1" bitfld.long 0x08 6. " DIRECT_LINK_WIDTH_CHANGE ,Directed link width change" "0,1" newline bitfld.long 0x08 0.--5. " TARGET_LINK_WIDTH ,Target link width" "No start,x1,x2,,x4,,,,x8,,,,,,,,x16,,,,,,,,,,,,,,,,x32,?..." line.long 0x0C "PHY_INTEROP_CTRL_OFF,PHY Interoperability Control Register" bitfld.long 0x0C 9. " L1_NOWAIT_P1 ,L1 entry control bit" "No wait,Wait" bitfld.long 0x0C 8. " L1SUB_EXIT_MODE ,L1 exit control using phy_mac_pclkack_n" "Exit,Wait" newline bitfld.long 0x0C 6. " RXSTANDBY_CONTROL[6] ,RxStandby/RxStandbyStatus handshake enable" "Disabled,Enabled" bitfld.long 0x0C 5. " [5] ,EI Infer in L0" "0,1" newline bitfld.long 0x0C 4. " [4] ,RxL0s.Idle" "0,1" bitfld.long 0x0C 3. " [3] ,PowerDown=P1orP2" "0,1" newline bitfld.long 0x0C 2. " [2] ,Inactive lane for upconfigure/downconfigure" "0,1" bitfld.long 0x0C 1. " [1] ,Rate change" "0,1" newline bitfld.long 0x0C 0. " [0] ,RX EIOS and subsequent T TX-IDLE-MIN" "0,1" line.long 0x10 "TRGT_CPL_LUT_DELETE_ENTRY_OFF,TRGT_CPL_LUT Delete Entry Control Register" bitfld.long 0x10 31. " DELETE_EN ,This is a one shot bit" "Not triggered,Triggered" hexmask.long 0x10 0.--30. 1. " LOOK_UP_ID ,This number selects one entry to delete of the TRGT_CPL_LUT" line.long 0x14 "LINK_FLUSH_CONTROL_OFF,Link Reset Request Flush Control Register" bitfld.long 0x14 0. " AUTO_FLUSH_EN ,Enables automatic flushing" "Disabled,Enabled" line.long 0x18 "AMBA_ERROR_RESPONSE_DEFAULT_OFF,AXI Bridge Slave Error Response Register" bitfld.long 0x18 15. " UR ,Unsupported request" "DECERR,SLVERR" bitfld.long 0x18 13. " CA ,Completer abort" "DECERR,SLVERR" newline bitfld.long 0x18 10. " CT ,Complete timeout" "DECERR,SLVERR" bitfld.long 0x18 2. " AMBA_ERROR_RESPONSE_VENDORID ,Vendor ID non-existent slave error response mapping" "0,1" newline bitfld.long 0x18 0. " AMBA_ERROR_RESPONSE_GLOBAL ,Global slave error response mapping" "0,1" line.long 0x1C "AMBA_LINK_TIMEOUT_OFF,Link Down AXI Bridge Slave Timeout Register" bitfld.long 0x1C 8. " LINK_TIMEOUT_EN_DFL ,Disable flush" "No,Yes" hexmask.long.byte 0x1C 0.--7. 1. " LINK_TIMEOUT_PER_DFL ,Timeout value (ms)" line.long 0x20 "AMBA_ORDERING_CTRL_OFF,AMBA Ordering Control" bitfld.long 0x20 3.--4. " AX_MSTR_ORDR_P_EVENT_SEL ,AXI master posted ordering event selector" "B'last,AW'last,W'last,?..." bitfld.long 0x20 2. " AX_IB_CPL_PASS_P ,AXI inbound CPL must not pass P rule disable" "No,Yes" newline bitfld.long 0x20 1. " AX_SNP_EN ,Disable flush" "No,Yes" bitfld.long 0x20 0. " AX_MSTR_NP_PASS_P ,AXI Master NP pass P enable" "Disabled,Enabled" group.long 0x1E0++0x0B line.long 0x00 "COHERENCY_CONTROL_1_OFF,ACE Cache Coherency Control Register 1" hexmask.long 0x00 2.--31. 0x04 " CFG_MEMTYPE_BD_L_ADDR ,Boundary lower address for memory type" bitfld.long 0x00 0. " CFG_MEMTYPE_VAL ,Memory type for the lower and upper parts of the address space select" "L:Periph UP:Mem,L:Mem UP:Periph" line.long 0x04 "COHERENCY_CONTROL_2_OFF,ACE Cache Coherency Control Register 2" line.long 0x08 "COHERENCY_CONTROL_3_OFF,ACE Cache Coherency Control Register 3" bitfld.long 0x08 27.--30. " CFG_MSTR_AWCACHE_VAL ,Master write CACHE signal value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 19.--22. " CFG_MSTR_ARCACHE_VAL ,Master read CACHE signal value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 11.--14. " CFG_MSTR_AWCACHE_MODE ,Master write CACHE signal behavior" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 3.--6. " CFG_MSTR_ARCACHE_MODE ,Master read CACHE signal behavior" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1F0++0x07 line.long 0x00 "AXI_MSTR_MSG_ADDR_LOW_OFF,Lower 20 Bits Of The Programmable AXI Address Where Messages Coming From Wire Are Mapped To" hexmask.long.tbyte 0x00 12.--31. 0x10 " CFG_AXIMSTR_MSG_ADDR_LOW ,Lower 20 bits of the programmable AXI address for Messages" line.long 0x04 "AXI_MSTR_MSG_ADDR_HIGH_OFF,Upper 32 Bits Of The Programmable AXI Address Where Messages Coming From Wire Are Mapped To" group.long 0x200++0x1F line.long 0x00 "IATU_VIEWPORT_OFF,IATU Index Register" bitfld.long 0x00 31. " REGION_DIR ,Region direction" "Outbound,Inbound" bitfld.long 0x00 0.--2. " REGION_INDEX ,Region index" "0,1,2,3,4,5,6,7" line.long 0x04 "IATU_REGION_CTRL_1_OFF_OUTBOUND_0,IATU Region Control 1 Register" bitfld.long 0x04 20.--22. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--17. " AT ,AT" "0,1,2,3" newline bitfld.long 0x04 13. " INCREASE_REGION_SIZE ,Increase the maximum ATU region size" "0,1" bitfld.long 0x04 11. " IDO ,IDO" "0,1" newline bitfld.long 0x04 9.--10. " ATTR ,ATTR" "0,1,2,3" bitfld.long 0x04 8. " TD ,TD" "0,1" newline bitfld.long 0x04 5.--7. " TC ,TC" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--4. " TYPE ,Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "IATU_REGION_CTRL_2_OFF_OUTBOUND_0,IATU Region Control 2 Register" bitfld.long 0x08 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x08 29. " INVERT_MODE ,Invert mode" "Not inverted,Inverted" newline bitfld.long 0x08 28. " CFG_SHIFT_MODE ,CFG shift mode" "0,1" bitfld.long 0x08 27. " DMA_BYPASS ,DMA bypass mode" "0,1" newline bitfld.long 0x08 23. " HEADER_SUBSTITUTE_EN ,Header substitute enable" "Disabled,Enabled" bitfld.long 0x08 22. " INHIBIT_PAYLOAD ,Inhibit TLP payload data for TLP's in matched region" "Disabled,Enabled" newline bitfld.long 0x08 20. " SNP ,Serialize non-posted requests" "0,1" bitfld.long 0x08 19. " FUNC_BYPASS ,Function number translation bypass" "0,1" newline bitfld.long 0x08 16. " TAG_SUBSTITUTE_EN ,TAG substitute enable" "Disabled,Enabled" hexmask.long.byte 0x08 8.--15. 1. " TAG ,TAG" newline hexmask.long.byte 0x08 0.--7. 1. " MSG_CODE ,Message code" line.long 0x0C "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,IATU Lower Base Address Register" hexmask.long.tbyte 0x0C 12.--31. 0x10 " LWR_BASE_RW ,Upper bits of base" hexmask.long.word 0x0C 0.--11. 0x01 " LWR_BASE_HW ,Lower bits of base" line.long 0x10 "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,IATU Upper Base Address Register" line.long 0x14 "IATU_LIMIT_ADDR_OFF_OUTBOUND_0,IATU Limit Address Register" hexmask.long.tbyte 0x14 12.--31. 0x10 " LIMIT_ADDR_RW ,Upper bits of limit address" hexmask.long.word 0x14 0.--11. 0x01 " LIMIT_ADDR_HW ,Lower bits of limit address" line.long 0x18 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,IATU Lower Target Address Register" line.long 0x1C "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,IATU Upper Target Address Register" group.long 0x270++0x03 line.long 0x00 "DMA_CTRL_DATA_ARB_PRIOR_OFF,DMA Arbitration Scheme For TRGT1 Interface" bitfld.long 0x00 9.--11. " RDBUFF_TRGT_WEIGHT ,DMA read channel MWr requests" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " RD_CTRL_TRGT_WEIGHT ,DMA read channel MRd requests" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--5. " WR_CTRL_TRGT_WEIGHT ,DMA write channel MRd requests" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " RTRGT1_WEIGHT ,Non-DMA RX requests" "0,1,2,3,4,5,6,7" rgroup.long 0x278++0x03 line.long 0x00 "DMA_CTRL_OFF,DMA Number Of Channels Register" bitfld.long 0x00 16.--19. " NUM_DMA_RD_CHAN ,Number of read channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " NUM_DMA_WR_CHAN ,Number of write channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x27C++0x07 line.long 0x00 "DMA_WRITE_ENGINE_EN_OFF,DMA Write Engine Enable Register" bitfld.long 0x00 0. " DMA_WRITE_ENGINE ,DMA write engine enable" "Disabled,Enabled" line.long 0x04 "DMA_WRITE_DOORBELL_OFF,DMA Write Doorbell Register" bitfld.long 0x04 31. " WR_STOP ,Stop" "Not stopped,Stopped" bitfld.long 0x04 0.--2. " WR_DOORBELL_NUM ,Doorbell number" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" group.long 0x288++0x07 line.long 0x00 "DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Write Engine Channel Arbitration Weight Low Register" bitfld.long 0x00 15.--19. " WRITE_CHANNEL3_WEIGHT ,Channel 3 weight" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 10.--14. " WRITE_CHANNEL2_WEIGHT ,Channel 2 weight" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 5.--9. " WRITE_CHANNEL1_WEIGHT ,Channel 1 weight" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 0.--4. " WRITE_CHANNEL0_WEIGHT ,Channel 0 weight" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" line.long 0x04 "DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Write Engine Channel Arbitration Weight High Register" bitfld.long 0x04 15.--19. " WRITE_CHANNEL7_WEIGHT ,Channel 7 weight" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 10.--14. " WRITE_CHANNEL6_WEIGHT ,Channel 6 weight" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x04 5.--9. " WRITE_CHANNEL5_WEIGHT ,Channel 5 weight" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 0.--4. " WRITE_CHANNEL4_WEIGHT ,Channel 4 weight" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" group.long 0x29C++0x07 line.long 0x00 "DMA_READ_ENGINE_EN_OFF,DMA Read Engine Enable Register" bitfld.long 0x00 0. " DMA_READ_ENGINE ,DMA read engine enable" "Disabled,Enabled" line.long 0x04 "DMA_READ_DOORBELL_OFF,DMA Read Doorbell Register" bitfld.long 0x04 31. " RD_STOP ,Stop" "Not stopped,Stopped" bitfld.long 0x04 0.--2. " WR_DOORBELL_NUM ,Doorbell number" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" group.long 0x2A8++0x07 line.long 0x00 "DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Read Engine Channel Arbitration Weight Low Register" bitfld.long 0x00 15.--19. " READ_CHANNEL3_WEIGHT ,Channel 3 weight" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 10.--14. " READ_CHANNEL2_WEIGHT ,Channel 2 weight" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 5.--9. " READ_CHANNEL1_WEIGHT ,Channel 1 weight" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 0.--4. " READ_CHANNEL0_WEIGHT ,Channel 0 weight" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" line.long 0x04 "DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Read Engine Channel Arbitration Weight High Register" bitfld.long 0x04 15.--19. " READ_CHANNEL7_WEIGHT ,Channel 7 weight" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 10.--14. " READ_CHANNEL6_WEIGHT ,Channel 6 weight" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x04 5.--9. " READ_CHANNEL5_WEIGHT ,Channel 5 weight" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x04 0.--4. " READ_CHANNEL4_WEIGHT ,Channel 4 weight" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" group.long 0x2BC++0x03 line.long 0x00 "DMA_WRITE_INT_STATUS_OFF,DMA Write Interrupt Status Register" bitfld.long 0x00 23. " WR_ABORT_INT_STATUS[7] ,Abort interrupt status for channel 7" "Not aborted,Aborted" bitfld.long 0x00 22. " [6] ,Abort interrupt status for channel 6" "Not aborted,Aborted" newline bitfld.long 0x00 21. " [5] ,Abort interrupt status for channel 5" "Not aborted,Aborted" bitfld.long 0x00 20. " [4] ,Abort interrupt status for channel 4" "Not aborted,Aborted" newline bitfld.long 0x00 19. " [3] ,Abort interrupt status for channel 3" "Not aborted,Aborted" bitfld.long 0x00 18. " [2] ,Abort interrupt status for channel 2" "Not aborted,Aborted" newline bitfld.long 0x00 17. " [1] ,Abort interrupt status for channel 1" "Not aborted,Aborted" bitfld.long 0x00 16. " [0] ,Abort interrupt status for channel 0" "Not aborted,Aborted" newline bitfld.long 0x00 7. " WR_DONE_INT_STATUS[7] ,Done interrupt status for channel 7" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,Done interrupt status for channel 6" "Not masked,Masked" newline bitfld.long 0x00 5. " [5] ,Done interrupt status for channel 5" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,Done interrupt status for channel 4" "Not masked,Masked" newline bitfld.long 0x00 3. " [3] ,Done interrupt status for channel 3" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,Done interrupt status for channel 2" "Not masked,Masked" newline bitfld.long 0x00 1. " [1] ,Done interrupt status for channel 1" "Not masked,Masked" bitfld.long 0x00 0. " [0] ,Done interrupt status for channel 0" "Not masked,Masked" group.long 0x2C4++0x07 line.long 0x00 "DMA_WRITE_INT_MASK_OFF,DMA Write Interrupt Mask Register" bitfld.long 0x00 16. " WR_ABORT_INT_MASK ,Abort interrupt mask for channel 0" "Not aborted,Aborted" bitfld.long 0x00 0. " WR_DONE_INT_MASK ,Done interrupt mask for channel 0" "Not done,Done" line.long 0x04 "DMA_WRITE_INT_CLEAR_OFF,DMA Write Interrupt Clear Register" bitfld.long 0x04 23. " WR_ABORT_INT_CLEAR[7] ,Abort interrupt clear for channel 7" "Not aborted,Aborted" bitfld.long 0x04 22. " [6] ,Abort interrupt clear for channel 6" "Not aborted,Aborted" newline bitfld.long 0x04 21. " [5] ,Abort interrupt clear for channel 5" "Not aborted,Aborted" bitfld.long 0x04 20. " [4] ,Abort interrupt clear for channel 4" "Not aborted,Aborted" newline bitfld.long 0x04 19. " [3] ,Abort interrupt clear for channel 3" "Not aborted,Aborted" bitfld.long 0x04 18. " [2] ,Abort interrupt clear for channel 2" "Not aborted,Aborted" newline bitfld.long 0x04 17. " [1] ,Abort interrupt clear for channel 1" "Not aborted,Aborted" bitfld.long 0x04 16. " [0] ,Abort interrupt clear for channel 0" "Not aborted,Aborted" newline bitfld.long 0x04 7. " WR_DONE_INT_CLEAR[7] ,Done interrupt clear for channel 7" "Not done,Done" bitfld.long 0x04 6. " [6] ,Done interrupt clear for channel 6" "Not done,Done" newline bitfld.long 0x04 5. " [5] ,Done interrupt clear for channel 5" "Not done,Done" bitfld.long 0x04 4. " [4] ,Done interrupt clear for channel 4" "Not done,Done" newline bitfld.long 0x04 3. " [3] ,Done interrupt clear for channel 3" "Not done,Done" bitfld.long 0x04 2. " [2] ,Done interrupt clear for channel 2" "Not done,Done" newline bitfld.long 0x04 1. " [1] ,Done interrupt clear for channel 1" "Not done,Done" bitfld.long 0x04 0. " [0] ,Done interrupt clear for channel 0" "Not done,Done" rgroup.long 0x2CC++0x03 line.long 0x00 "DMA_WRITE_ERR_STATUS_OFF,DMA Write Error Status Register" bitfld.long 0x00 23. " LINKLIST_ELEMENT_FETCH_ERR_DETECT[7] ,Linked list element fetch error detected for channel 7" "Not occurred,Occurred" bitfld.long 0x00 22. " [6] ,Linked list element fetch error detected for channel 6" "Not occurred,Occurred" newline bitfld.long 0x00 21. " [5] ,Linked list element fetch error detected for channel 5" "Not occurred,Occurred" bitfld.long 0x00 20. " [4] ,Linked list element fetch error detected for channel 4" "Not occurred,Occurred" newline bitfld.long 0x00 19. " [3] ,Linked list element fetch error detected for channel 3" "Not occurred,Occurred" bitfld.long 0x00 18. " [2] ,Linked list element fetch error detected for channel 2" "Not occurred,Occurred" newline bitfld.long 0x00 17. " [1] ,Linked list element fetch error detected for channel 1" "Not occurred,Occurred" bitfld.long 0x00 16. " [0] ,Linked list element fetch error detected for channel 0" "Not occurred,Occurred" newline bitfld.long 0x00 7. " APP_READ_ERR_DETECT[7] ,Application read error detected for channel 7" "Not occurred,Occurred" bitfld.long 0x00 6. " [6] ,Application read error detected for channel 6" "Not occurred,Occurred" newline bitfld.long 0x00 5. " [5] ,Application read error detected for channel 5" "Not occurred,Occurred" bitfld.long 0x00 4. " [4] ,Application read error detected for channel 4" "Not occurred,Occurred" newline bitfld.long 0x00 3. " [3] ,Application read error detected for channel 3" "Not occurred,Occurred" bitfld.long 0x00 2. " [2] ,Application read error detected for channel 2" "Not occurred,Occurred" newline bitfld.long 0x00 1. " [1] ,Application read error detected for channel 1" "Not occurred,Occurred" bitfld.long 0x00 0. " [0] ,Application read error detected for channel 0" "Not occurred,Occurred" group.long 0x2D0++0x1F line.long 0x00 "DMA_WRITE_DONE_IMWR_LOW_OFF,DMA Write Done IMWr Address Low Register" line.long 0x04 "DMA_WRITE_DONE_IMWR_HIGH_OFF,DMA Write Done IMWr Interrupt Address High Register" line.long 0x08 "DMA_WRITE_ABORT_IMWR_LOW_OFF,DMA Write Abort IMWr Address Low Register" line.long 0x0C "DMA_WRITE_ABORT_IMWR_HIGH_OFF,DMA Write Abort IMWr Address High Register" line.long 0x10 "DMA_WRITE_CH01_IMWR_DATA_OFF,DMA Write Channel 1 And 0 IMWr Data Register" hexmask.long.word 0x10 16.--31. 1. " WR_CHANNEL_1_DATA ,Write channel 1 data" hexmask.long.word 0x10 0.--15. 1. " WR_CHANNEL_0_DATA ,Write channel 0 data" line.long 0x14 "DMA_WRITE_CH23_IMWR_DATA_OFF,DMA Write Channel 3 And 2 IMWr Data Register" hexmask.long.word 0x14 16.--31. 1. " WR_CHANNEL_3_DATA ,Write channel 3 data" hexmask.long.word 0x14 0.--15. 1. " WR_CHANNEL_2_DATA ,Write channel 2 data" line.long 0x18 "DMA_WRITE_CH45_IMWR_DATA_OFF,DMA Write Channel 5 And 4 IMWr Data Register" hexmask.long.word 0x18 16.--31. 1. " WR_CHANNEL_5_DATA ,Write channel 5 data" hexmask.long.word 0x18 0.--15. 1. " WR_CHANNEL_4_DATA ,Write channel 4 data" line.long 0x1C "DMA_WRITE_CH67_IMWR_DATA_OFF,DMA Write Channel 7 And 6 IMWr Data Register" hexmask.long.word 0x1C 16.--31. 1. " WR_CHANNEL_7_DATA ,Write channel 7 data" hexmask.long.word 0x1C 0.--15. 1. " WR_CHANNEL_6_DATA ,Write channel 6 data" if (((per.l(ad:0x5F010000+0x370+0x700))&0x200)==0x200) group.long 0x300++0x03 line.long 0x00 "DMA_WRITE_LINKED_LIST_ERR_EN_OFF,DMA Write Linked List Error Enable Register" bitfld.long 0x00 16. " WR_CHANNEL_LLLAIE ,Write channel LL local abort interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " WR_CHANNEL_LLRAIE ,Write channel LL remote abort interrupt enable" "Disabled,Enabled" else hgroup.long 0x300++0x03 hide.long 0x00 "DMA_WRITE_LINKED_LIST_ERR_EN_OFF,DMA Write Linked List Error Enable Register" endif group.long 0x310++0x03 line.long 0x00 "DMA_READ_INT_STATUS_OFF,DMA Read Interrupt Status Register" bitfld.long 0x00 23. " RD_ABORT_INT_STATUS[7] ,Abort interrupt status for channel 7" "Not aborted,Aborted" bitfld.long 0x00 22. " [6] ,Abort interrupt status for channel 6" "Not aborted,Aborted" newline bitfld.long 0x00 21. " [5] ,Abort interrupt status for channel 5" "Not aborted,Aborted" bitfld.long 0x00 20. " [4] ,Abort interrupt status for channel 4" "Not aborted,Aborted" newline bitfld.long 0x00 19. " [3] ,Abort interrupt status for channel 3" "Not aborted,Aborted" bitfld.long 0x00 18. " [2] ,Abort interrupt status for channel 2" "Not aborted,Aborted" newline bitfld.long 0x00 17. " [1] ,Abort interrupt status for channel 1" "Not aborted,Aborted" bitfld.long 0x00 16. " [0] ,Abort interrupt status for channel 0" "Not aborted,Aborted" newline bitfld.long 0x00 7. " RD_DONE_INT_STATUS[7] ,Done interrupt status for channel 7" "Not done,Done" bitfld.long 0x00 6. " [6] ,Done interrupt status for channel 6" "Not done,Done" newline bitfld.long 0x00 5. " [5] ,Done interrupt status for channel 5" "Not done,Done" bitfld.long 0x00 4. " [4] ,Done interrupt status for channel 4" "Not done,Done" newline bitfld.long 0x00 3. " [3] ,Done interrupt status for channel 3" "Not done,Done" bitfld.long 0x00 2. " [2] ,Done interrupt status for channel 2" "Not done,Done" newline bitfld.long 0x00 1. " [1] ,Done interrupt status for channel 1" "Not done,Done" bitfld.long 0x00 0. " [0] ,Done interrupt status for channel 0" "Not done,Done" group.long 0x318++0x03 line.long 0x00 "DMA_READ_INT_MASK_OFF,DMA Read Interrupt Mask Register" bitfld.long 0x00 16. " RD_ABORT_INT_MASK ,Abort interrupt mask" "Not aborted,Aborted" bitfld.long 0x00 0. " RD_DONE_INT_MASK ,Done interrupt mask" "Not done,Done" wgroup.long 0x31C++0x03 line.long 0x00 "DMA_READ_INT_CLEAR_OFF,DMA Read Interrupt Clear Register" bitfld.long 0x00 23. " RD_ABORT_INT_CLEAR[7] ,Abort interrupt clear for channel 7" "Not aborted,Aborted" bitfld.long 0x00 22. " [6] ,Abort interrupt clear for channel 6" "Not aborted,Aborted" newline bitfld.long 0x00 21. " [5] ,Abort interrupt clear for channel 5" "Not aborted,Aborted" bitfld.long 0x00 20. " [4] ,Abort interrupt clear for channel 4" "Not aborted,Aborted" newline bitfld.long 0x00 19. " [3] ,Abort interrupt clear for channel 3" "Not aborted,Aborted" bitfld.long 0x00 18. " [2] ,Abort interrupt clear for channel 2" "Not aborted,Aborted" newline bitfld.long 0x00 17. " [1] ,Abort interrupt clear for channel 1" "Not aborted,Aborted" bitfld.long 0x00 16. " [0] ,Abort interrupt clear for channel 0" "Not aborted,Aborted" newline bitfld.long 0x00 7. " RD_DONE_INT_CLEAR[7] ,Done interrupt clear for channel 7" "Not done,Done" bitfld.long 0x00 6. " [6] ,Done interrupt clear for channel 6" "Not done,Done" newline bitfld.long 0x00 5. " [5] ,Done interrupt clear for channel 5" "Not done,Done" bitfld.long 0x00 4. " [4] ,Done interrupt clear for channel 4" "Not done,Done" newline bitfld.long 0x00 3. " [3] ,Done interrupt clear for channel 3" "Not done,Done" bitfld.long 0x00 2. " [2] ,Done interrupt clear for channel 2" "Not done,Done" newline bitfld.long 0x00 1. " [1] ,Done interrupt clear for channel 1" "Not done,Done" bitfld.long 0x00 0. " [0] ,Done interrupt clear for channel 0" "Not done,Done" rgroup.long 0x324++0x07 line.long 0x00 "DMA_READ_ERR_STATUS_LOW_OFF,DMA Read Error Status Low Register" bitfld.long 0x00 23. " LINK_LIST_ELEMENT_FETCH_ERR_DETECT[7] ,Linked list element fetch error detected for channel 7" "Not detected,Detected" bitfld.long 0x00 22. " [6] ,Linked list element fetch error detected for channel 6" "Not detected,Detected" newline bitfld.long 0x00 21. " [5] ,Linked list element fetch error detected for channel 5" "Not detected,Detected" bitfld.long 0x00 20. " [4] ,Linked list element fetch error detected for channel 4" "Not detected,Detected" newline bitfld.long 0x00 19. " [3] ,Linked list element fetch error detected for channel 3" "Not detected,Detected" bitfld.long 0x00 18. " [2] ,Linked list element fetch error detected for channel 2" "Not detected,Detected" newline bitfld.long 0x00 17. " [1] ,Linked list element fetch error detected for channel 1" "Not detected,Detected" bitfld.long 0x00 16. " [0] ,Linked list element fetch error detected for channel 0" "Not detected,Detected" newline bitfld.long 0x00 7. " APP_WR_ERR_DETECT[7] ,Application write error detected for channel 7" "Not detected,Detected" bitfld.long 0x00 6. " [6] ,Application write error detected for channel 6" "Not detected,Detected" newline bitfld.long 0x00 5. " [5] ,Application write error detected for channel 5" "Not detected,Detected" bitfld.long 0x00 4. " [4] ,Application write error detected for channel 4" "Not detected,Detected" newline bitfld.long 0x00 3. " [3] ,Application write error detected for channel 3" "Not detected,Detected" bitfld.long 0x00 2. " [2] ,Application write error detected for channel 2" "Not detected,Detected" newline bitfld.long 0x00 1. " [1] ,Application write error detected for channel 1" "Not detected,Detected" bitfld.long 0x00 0. " [0] ,Application write error detected for channel 0" "Not detected,Detected" line.long 0x04 "DMA_READ_ERR_STATUS_HIGH_OFF,DMA Read Error Status High Register" bitfld.long 0x04 31. " DATA_POISIONING[7] ,Data poisoning for channel 7" "Disabled,Enabled" bitfld.long 0x04 30. " [6] ,Data poisoning for channel 6" "Disabled,Enabled" newline bitfld.long 0x04 29. " [5] ,Data poisoning for channel 5" "Disabled,Enabled" bitfld.long 0x04 28. " [4] ,Data poisoning for channel 4" "Disabled,Enabled" newline bitfld.long 0x04 27. " [3] ,Data poisoning for channel 3" "Disabled,Enabled" bitfld.long 0x04 26. " [2] ,Data poisoning for channel 2" "Disabled,Enabled" newline bitfld.long 0x04 25. " [1] ,Data poisoning for channel 1" "Disabled,Enabled" bitfld.long 0x04 24. " [0] ,Data poisoning for channel 0" "Disabled,Enabled" newline bitfld.long 0x04 23. " CPL_TIMEOUT[7] ,Completion time out for channel 7" "Disabled,Enabled" bitfld.long 0x04 22. " [6] ,Completion time out for channel 6" "Disabled,Enabled" newline bitfld.long 0x04 21. " [5] ,Completion time out for channel 5" "Disabled,Enabled" bitfld.long 0x04 20. " [4] ,Completion time out for channel 4" "Disabled,Enabled" newline bitfld.long 0x04 19. " [3] ,Completion time out for channel 3" "Disabled,Enabled" bitfld.long 0x04 18. " [2] ,Completion time out for channel 2" "Disabled,Enabled" newline bitfld.long 0x04 17. " [1] ,Completion time out for channel 1" "Disabled,Enabled" bitfld.long 0x04 16. " [0] ,Completion time out for channel 0" "Disabled,Enabled" newline bitfld.long 0x04 15. " CPL_ABORT[7] ,Completer abort for channel 7" "Not Received,Received" bitfld.long 0x04 14. " [6] ,Completer abort for channel 6" "Not Received,Received" newline bitfld.long 0x04 13. " [5] ,Completer abort for channel 5" "Not Received,Received" bitfld.long 0x04 12. " [4] ,Completer abort for channel 4" "Not Received,Received" newline bitfld.long 0x04 11. " [3] ,Completer abort for channel 3" "Not Received,Received" bitfld.long 0x04 10. " [2] ,Completer abort for channel 2" "Not Received,Received" newline bitfld.long 0x04 9. " [1] ,Completer abort for channel 1" "Not Received,Received" bitfld.long 0x04 8. " [0] ,Completer abort for channel 0" "Not Received,Received" newline bitfld.long 0x04 7. " UNSUPPORTED_REQ[7] ,Unsupported request for channel 7" "Not Received,Received" bitfld.long 0x04 6. " [6] ,Unsupported request for channel 6" "Not Received,Received" newline bitfld.long 0x04 5. " [5] ,Unsupported request for channel 5" "Not Received,Received" bitfld.long 0x04 4. " [4] ,Unsupported request for channel 4" "Not Received,Received" newline bitfld.long 0x04 3. " [3] ,Unsupported request for channel 3" "Not Received,Received" bitfld.long 0x04 2. " [2] ,Unsupported request for channel 2" "Not Received,Received" newline bitfld.long 0x04 1. " [1] ,Unsupported request for channel 1" "Not Received,Received" bitfld.long 0x04 0. " [0] ,Unsupported request for channel 0" "Not Received,Received" if (((per.l(ad:0x5F010000+0x370+0x700))&0x200)==0x200) group.long 0x334++0x03 line.long 0x00 "DMA_READ_LINKED_LIST_ERR_EN_OFF,DMA Read Linked List Error Enable Register" bitfld.long 0x00 16. " RD_CHANNEL_LLLAIE ,Read channel LL local abort interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " RD_CHANNEL_LLRAIE ,Read channel LL remote abort interrupt enable" "Disabled,Enabled" else hgroup.long 0x334++0x03 hide.long 0x00 "DMA_READ_LINKED_LIST_ERR_EN_OFF,DMA Read Linked List Error Enable Register" endif group.long 0x33C++0x1F line.long 0x00 "DMA_READ_DONE_IMWR_LOW_OFF,DMA Read Done IMWr Address Low Register" line.long 0x04 "DMA_READ_DONE_IMWR_HIGH_OFF,DMA Read Done IMWr Address High Register" line.long 0x08 "DMA_READ_ABORT_IMWR_LOW_OFF,DMA Read Abort IMWr Address Low Register" line.long 0x0C "DMA_READ_ABORT_IMWR_HIGH_OFF,DMA Read Abort IMWr Address High Register" line.long 0x10 "DMA_READ_CH01_IMWR_DATA_OFF,DMA Read Channel 1 And 0 IMWr Data Register" hexmask.long.word 0x10 16.--31. 1. " RD_CHANNEL_1_DATA ,Read channel 1 data" hexmask.long.word 0x10 0.--15. 1. " RD_CHANNEL_0_DATA ,Read channel 0 data" line.long 0x14 "DMA_READ_CH23_IMWR_DATA_OFF,DMA Read Channel 3 And 2 IMWr Data Register" hexmask.long.word 0x14 16.--31. 1. " RD_CHANNEL_3_DATA ,Read channel 3 data" hexmask.long.word 0x14 0.--15. 1. " RD_CHANNEL_2_DATA ,Read channel 2 data" line.long 0x18 "DMA_READ_CH45_IMWR_DATA_OFF,DMA Read Channel 5 And 4 IMWr Data Register" hexmask.long.word 0x18 16.--31. 1. " RD_CHANNEL_5_DATA ,Read channel 5 data" hexmask.long.word 0x18 0.--15. 1. " RD_CHANNEL_4_DATA ,Read channel 4 data" line.long 0x1C "DMA_READ_CH67_IMWR_DATA_OFF,DMA Read Channel 7 And 6 IMWr Data Register" hexmask.long.word 0x1C 16.--31. 1. " RD_CHANNEL_7_DATA ,Read channel 7 data" hexmask.long.word 0x1C 0.--15. 1. " RD_CHANNEL_6_DATA ,Read channel 6 data" group.long 0x36C++0x03 line.long 0x00 "DMA_VIEWPORT_SEL_OFF,DMA Channel Context Index Register" bitfld.long 0x00 31. " CHANNEL_DIR ,Channel direction" "Write,Read" bitfld.long 0x00 0.--2. " CHANNEL_NUM ,Channel index" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7" if (((per.l(ad:0x5F010000+0x370+0x700))&0x200)==0x200) group.long 0x370++0x03 line.long 0x00 "DMA_CH_CONTROL1_OFF_WRCH_0,DMA Write Channel Control 1 Register" bitfld.long 0x00 30.--31. " DMA_AT ,Address translation TLP header bit" "0,1,2,3" bitfld.long 0x00 27.--29. " DMA_TC ,Traffic class TLP header bit" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 25. " DMA_RO ,Relaxed ordering TLP header bit" "0,1" bitfld.long 0x00 24. " DMA_NS_SRC ,Source no snoop TLP header bit" "0,1" newline bitfld.long 0x00 23. " DMA_NS_DST ,Destination no snoop TLP header bit" "0,1" bitfld.long 0x00 12.--16. " DMA_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 9. " LLE ,Linked list enable" "Disabled,Enabled" bitfld.long 0x00 8. " CCS ,Consumer cycle state" "0,1" newline bitfld.long 0x00 5.--6. " CS ,Channel status" ",Running,Halted,Stopped" bitfld.long 0x00 4. " RIE ,Remote interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " LIE ,Local interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " LLP ,Load link pointer" "0,1" newline bitfld.long 0x00 1. " TCB ,Toggle cycle bit" "0,1" bitfld.long 0x00 0. " CB ,Cycle bit" "0,1" else group.long 0x370++0x03 line.long 0x00 "DMA_CH_CONTROL1_OFF_WRCH_0,DMA Write Channel Control 1 Register" bitfld.long 0x00 30.--31. " DMA_AT ,Address translation TLP header bit" "0,1,2,3" bitfld.long 0x00 27.--29. " DMA_TC ,Traffic class TLP header bit" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 25. " DMA_RO ,Relaxed ordering TLP header bit" "0,1" bitfld.long 0x00 24. " DMA_NS_SRC ,Source no snoop TLP header bit" "0,1" newline bitfld.long 0x00 23. " DMA_NS_DST ,Destination no snoop TLP header bit" "0,1" bitfld.long 0x00 12.--16. " DMA_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 9. " LLE ,Linked list enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " CS ,Channel status" ",Running,Halted,Stopped" newline bitfld.long 0x00 4. " RIE ,Remote interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " LIE ,Local interrupt enable" "Disabled,Enabled" endif group.long 0x378++0x1B line.long 0x00 "DMA_TRANSFER_SIZE_OFF_WRCH_0,DMA Write Transfer Size Register" line.long 0x04 "DMA_SAR_LOW_OFF_WRCH_0,DMA Write SAR Low Register" line.long 0x08 "DMA_SAR_HIGH_OFF_WRCH_0,DMA Write SAR High Register" line.long 0x0C "DMA_DAR_LOW_OFF_WRCH_0,DMA Write DAR Low Register" line.long 0x10 "DMA_DAR_HIGH_OFF_WRCH_0,DMA Write DAR High Register" line.long 0x14 "DMA_LLP_LOW_OFF_WRCH_0,DMA Write Linked List Pointer Low Register" line.long 0x18 "DMA_LLP_HIGH_OFF_WRCH_0,DMA Write Linked List Pointer High Register" group.long 0x440++0x07 line.long 0x00 "AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control Register" hexmask.long.word 0x00 0.--9. 1. " AUX_CLK_FREQ ,The aux_clk frequency in MHz" line.long 0x04 "L1_SUBSTATES_OFF,L1 Substates Timing Register" bitfld.long 0x04 6.--7. " L1SUB_T_PCLKACK ,Max delay" "0,1,2,3" bitfld.long 0x04 2.--5. " L1SUB_T_L1_2 ,Duration (in 1us units) of L1.2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--1. " L1SUB_T_POWER_OFF ,Duration (in 1us units) of L1.2.Entry" "0,1,2,3" tree.end width 0x0B tree.end tree "PCIe_PHY (PCI Express PHY)" base ad:0x5F1A0000 width 8. group.byte 0x00++0x2F line.byte 0x00 "REG00,Control Register 0" bitfld.byte 0x00 7. " AUTO_SHIFT ,Auto shift" "0,1" bitfld.byte 0x00 6. " FORCE_RX_DETECT ,Forces the result of PCIe receiver detect operation to be always detected" "Not forced,Forced" bitfld.byte 0x00 4.--5. " CDR_REFERENCE ,Defines the CDR reference PLL mode" "0,1,2,3" bitfld.byte 0x00 2. " CDR_PLL_DELTA ,Cdr pll delta" "0,1" newline bitfld.byte 0x00 1. " SIGNAL_DETECT_THRESHOLD ,Signal_detect_threshold" "0,1" bitfld.byte 0x00 0. " TX_SELECT_RX_FEEDBACK ,Directly drives the aTxSelRxfb input of the serdes" "0,1" line.byte 0x01 "REG01,Clock Count For Error Counter Decrement" line.byte 0x02 "REG02,Error Counter Threshold - RX Idle Detect Max Latency" bitfld.byte 0x02 4.--7. " RXIDLE_MAX ,Number of clock cycles required before the aTranDet output of the PMA macro and report either electrical idle or valid input data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x02 0.--3. " ERRCNT_THR ,Error counter threshold value after which the CDR PLL switch back to frequency lock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x03 "REG03,RX Impedance Ratio" line.byte 0x04 "REG04,TxPLL F Setting And PCLK Ratio" bitfld.byte 0x04 4.--5. " TX_DIV_MODE0 ,Ratio between PCLK and aTxClk" "/1,/2,,/4" bitfld.byte 0x04 3. " TXF[3] ,Defines the aTxF[3] settings of the PMA macro" "0,1" bitfld.byte 0x04 2. " [2] ,Defines the aTxF[2] settings of the PMA macro" "0,1" bitfld.byte 0x04 1. " [1] ,Defines the aTxF[1] settings of the PMA macro" "0,1" newline bitfld.byte 0x04 0. " [0] ,Defines the aTxF[0] settings of the PMA macro" "0,1" line.byte 0x05 "REG05,TX PLL M And N Settings" bitfld.byte 0x05 7. " CNT250NS_MAX_BIT8 ,This bit is concatenated to register reg08 as MSB bit to define the 250ns base time" "0,1" bitfld.byte 0x05 6. " TXM[1] ,Defines the aTxM[1] setting of the PMA macro" "0,1" bitfld.byte 0x05 5. " [0] ,Defines the aTxM[0] setting of the PMA macro" "0,1" bitfld.byte 0x05 3. " TXN[3] ,Defines the aTxN[3] settings of the PMA macro" "0,1" newline bitfld.byte 0x05 2. " [2] ,Defines the aTxN[2] settings of the PMA macro" "0,1" bitfld.byte 0x05 1. " [1] ,Defines the aTxN[1] settings of the PMA macro" "0,1" bitfld.byte 0x05 0. " [0] ,Defines the aTxN[0] settings of the PMA macro" "0,1" line.byte 0x06 "REG06,RxPLL F Setting And PCLK Ratio" bitfld.byte 0x06 4.--5. " RX_DIV_MODE0 ,Ratio between internal RXCLK and aRxClk" "/1,/2,,/4" bitfld.byte 0x06 3. " RXF[3] ,Defines the aRxF[3] settings of the PMA macro" "0,1" bitfld.byte 0x06 2. " [2] ,Defines the aRxN[2] settings of the PMA macro" "0,1" bitfld.byte 0x06 1. " [1] ,Defines the aRxN[1] settings of the PMA macro" "0,1" newline bitfld.byte 0x06 0. " [0] ,Defines the aRxN[0] settings of the PMA macro" "0,1" line.byte 0x07 "REG07,RX PLL M And N Settings" bitfld.byte 0x07 6. " RXM[1] ,Defines the aRxM[1] setting of the PMA macro" "0,1" bitfld.byte 0x07 5. " [0] ,Defines the aRxM[0] setting of the PMA macro" "0,1" bitfld.byte 0x07 4. " RXN[4] ,Defines the aRxN[4] setting of the PMA macro" "0,1" bitfld.byte 0x07 3. " [3] ,Defines the aRxN[3] setting of the PMA macro" "0,1" newline bitfld.byte 0x07 2. " [2] ,Defines the aRxN[2] setting of the PMA macro" "0,1" bitfld.byte 0x07 1. " [1] ,Defines the aRxN[1] setting of the PMA macro" "0,1" bitfld.byte 0x07 0. " [0] ,Defines the aRxN[0] setting of the PMA macro" "0,1" line.byte 0x08 "REG08,250ns Timer Base Count" line.byte 0x09 "REG09,TX Impedance Ratio" line.byte 0x0A "REG10,TX Post-Cursor Ratio" line.byte 0x0B "REG11,TX Pre-Cursor Ratio" line.byte 0x0C "REG12,End Of Calibration Counter" line.byte 0x0D "REG13,Calibration Stability Counter" bitfld.byte 0x0D 5.--7. " CALIB_SETTLE_MAX ,Number of clock cycles where the aZCompOp signal is checked for stability during TX RX and RX Equalization calibration" "0,1,2,3,4,5,6,7" bitfld.byte 0x0D 0.--4. " CALIB_STABLE_MAX ,Number of clock cycles where the aZCompOp signal is checked for stability during TX RX and RX Equalizer calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x0E "REG14,Power Down Feature" bitfld.byte 0x0E 6.--7. " RXIDLE_MSB ,MSB bits of the activity detector logic enabling to specify that no activity has been detected during up to 61 aTxClkp clock cycles" "0,1,2,3" bitfld.byte 0x0E 3.--5. " FORCE_SIGNAL ,Force signal" "0,1,2,3,4,5,6,7" bitfld.byte 0x0E 0.--2. " FORCE_IDLE ,Force idle" "0,1,2,3,4,5,6,7" line.byte 0x0F "REG15,RX Offset Counter" bitfld.byte 0x0F 5.--7. " RXOFF_SETTLE_MAX ,Calibration for aRxDp/aRxDm/aRxEs/aRxT and Schmitt trigger" "0,1,2,3,4,5,6,7" bitfld.byte 0x0F 0.--4. " RXOFF_STABLE_MAX ,Number of clock cycles where the aRxDpNullDat signal is checked for stability" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x10 "REG16,TxPLL F Setting And PCLK Ratio In PCIe 5Gbps Speed" bitfld.byte 0x10 4.--5. " TX_DIV_MODE1 ,Ratio between PCLK and aTxClk." "/1,/2,,/4" bitfld.byte 0x10 3. " TXF[3] ,Defines the aTxF[3] settings of the PMA macro" "0,1" bitfld.byte 0x10 2. " [2] ,Defines the aTxN[2] settings of the PMA macro" "0,1" bitfld.byte 0x10 1. " [1] ,Defines the aTxN[1] settings of the PMA macro" "0,1" newline bitfld.byte 0x10 0. " [0] ,Defines the aTxN[0] settings of the PMA macro" "0,1" line.byte 0x11 "REG17,TX PLL M And N Settings In PCIe 5Gbps Speed" bitfld.byte 0x11 6. " TXM[1] ,Defines the aTxM[1] setting of the PMA macro" "0,1" bitfld.byte 0x11 5. " [0] ,Defines the aTxM[0] setting of the PMA macro" "0,1" bitfld.byte 0x11 4. " TXN[4] ,Defines the aTxN[4] setting of the PMA macro" "0,1" bitfld.byte 0x11 3. " [3] ,Defines the aTxN[3] setting of the PMA macro" "0,1" newline bitfld.byte 0x11 2. " [2] ,Defines the aTxN[2] setting of the PMA macro" "0,1" bitfld.byte 0x11 1. " [1] ,Defines the aTxN[1] setting of the PMA macro" "0,1" bitfld.byte 0x11 0. " [0] ,Defines the aTxN[0] setting of the PMA macro" "0,1" line.byte 0x12 "REG18,CDRPLL F Setting And PCLK Ratio In PCIe 5Gbps Speed" bitfld.byte 0x12 4.--5. " RX_DIV_MODE1 ,Ratio between internal RXCLK and aRxClk" "/1,/2,,/4" bitfld.byte 0x12 3. " RXF[3] ,Defines the aRxF[3] settings of the PMA macro" "0,1" bitfld.byte 0x12 2. " [2] ,Defines the aRxN[2] settings of the PMA macro" "0,1" bitfld.byte 0x12 1. " [1] ,Defines the aRxN[1] settings of the PMA macro" "0,1" newline bitfld.byte 0x12 0. " [0] ,Defines the aRxN[0] settings of the PMA macro" "0,1" line.byte 0x13 "REG19,CDRPLL M And N Settings In PCIe 5Gbps Speed" bitfld.byte 0x13 6. " RXM[1] ,Defines the aRxM[1] setting of the PMA macro" "0,1" bitfld.byte 0x13 5. " [0] ,Defines the aRxM[0] setting of the PMA macro" "0,1" bitfld.byte 0x13 4. " RXN[4] ,Defines the aRxN[4] setting of the PMA macro" "0,1" bitfld.byte 0x13 3. " [3] ,Defines the aRxN[3] setting of the PMA macro" "0,1" newline bitfld.byte 0x13 2. " [2] ,Defines the aRxN[2] setting of the PMA macro" "0,1" bitfld.byte 0x13 1. " [1] ,Defines the aRxN[1] setting of the PMA macro" "0,1" bitfld.byte 0x13 0. " [0] ,Defines the aRxN[0] setting of the PMA macro" "0,1" line.byte 0x14 "REG20,TX Post-cursor Ratio With TxDeemp=0 Full Swing" line.byte 0x15 "REG21,TX Pre-cursor Ratio With TxDeemp=0 Full Swing" line.byte 0x16 "REG22,TX Post-cursor Ratio With TxDeemp=1 Full Swing" line.byte 0x17 "REG23,TX Pre-cursor Ratio With TxDeemp=1 Full Swing" line.byte 0x18 "REG24,TX Amplitude Ratio TxMargin=0 Full Swing" line.byte 0x19 "REG25,TX Amplitude Ratio TxMargin=1 Full Swing" line.byte 0x1A "REG26,TX Amplitude Ratio TxMargin=2 Full Swing" line.byte 0x1B "REG27,TX Amplitude Ratio TxMargin=3 Full Swing" line.byte 0x1C "REG28,TX Amplitude Ratio TxMargin=4 Full Swing" line.byte 0x1D "REG29,TX Amplitude Ratio TxMargin=5 Full Swing" line.byte 0x1E "REG30,TX Amplitude Ratio TxMargin=6 Full Swing" line.byte 0x1F "REG31,TX Amplitude Ratio TxMargin=7 Full Swing" line.byte 0x20 "REG32,Auxiliary Clock For 1us Base Time" line.byte 0x21 "REG33,CDRPLLL Frequency Comparator Counter" line.byte 0x22 "REG34,CDRPLLL Frequency Comparator Maximum Difference" line.byte 0x23 "REG35,EI4 Mode Register" bitfld.byte 0x23 7. " EL4 ,Electrical Idle mode or Electrical Idle IV select" "Electrical Idle,Electrical Idle IV" bitfld.byte 0x23 2. " RSTCDR_IDL ,When set to 1 the CDR PLL is reset each time that the error gathering function reports an error and direct back the CDR to frequency lock mode" "0,1" bitfld.byte 0x23 1. " RSTCDR_FRQ ,When set to 1 the CDR PLL is reset each time that the frequency comparator trigger an error and direct back the CDR to frequency lock mode" "0,1" bitfld.byte 0x23 0. " RSTCDR_ERR ,When set to 1 the CDR PLL is reset each time that Electrical Idle is detected on RX" "0,1" line.byte 0x24 "REG36,TX Post-Cursor Ratio With TxDeemp=0 Half Swing" line.byte 0x25 "REG37,TX Pre-Cursor Ratio With TxDeemp=0 Half Swing" line.byte 0x26 "REG38,TX Post-Cursor Ratio With TxDeemp=1 Half Swing" line.byte 0x27 "REG39,TX Pre-Cursor Ratio With TxDeemp=1 Half Swing" line.byte 0x28 "REG40,TX Amplitude Ratio TxMargin=0 Half Swing" line.byte 0x29 "REG41,TX Amplitude Ratio TxMargin=1 Half Swing" line.byte 0x2A "REG42,TX Amplitude Ratio TxMargin=2 Half Swing" line.byte 0x2B "REG43,TX Amplitude Ratio TxMargin=3 Half Swing" line.byte 0x2C "REG44,TX Amplitude Ratio TxMargin=4 Half Swing" line.byte 0x2D "REG45,TX Amplitude Ratio TxMargin=5 Half Swing" line.byte 0x2E "REG46,TX Amplitude Ratio TxMargin=6 Half Swing" line.byte 0x2F "REG47,TX Amplitude Ratio TxMargin=7 Half Swing" rgroup.byte 0x30++0x02 line.byte 0x00 "REG48,PMA Status" bitfld.byte 0x00 7. " PMA_RDY ,Defines whether PMA has completed its internal calibration sequence after power-up and PHY reset deassertion" "Not ready,Ready" bitfld.byte 0x00 5. " ARXCTLE_ERR ,Defines whether RX CTLE calibration has reached a min or max value" "No error,Error" bitfld.byte 0x00 4. " ASCH_ERR ,Defines whether Schmitt Offset calibration has reached a min or max value" "No error,Error" bitfld.byte 0x00 3. " ARXES_ERR ,Defines whether RX Offset Error Sampler calibration has reached a min/max value" "No error,Error" newline bitfld.byte 0x00 2. " ARXDM_ERR ,Defines whether RX Offset Dm calibration has reached a min/max value" "No error,Error" bitfld.byte 0x00 1. " ARXDP_ERR ,Defines whether RX Offset Dp calibration has reached a min/max value" "No error,Error" bitfld.byte 0x00 0. " ARXT_ERR ,Defines whether RX Offset T calibration has reached a min/max value" "No error,Error" line.byte 0x01 "REG49,TX Sweep Center" bitfld.byte 0x01 7. " TX_VAL ,Defines whether PMA has completed the TX impedance calibration signaling that TX_SWEEP_CENTER_RESULT is valid" "Not valid,Valid" hexmask.byte 0x01 0.--6. 1. " TX_SWEEP_CENTER_RESULT ,Result of TX impedance calibration" line.byte 0x02 "REG50,RX Sweep Center" bitfld.byte 0x02 7. " RX_VAL ,Defines whether PMA has completed the RX impedance calibration signaling that RX_SWEEP_CENTER_RESULT is valid" "Not valid,Valid" hexmask.byte 0x02 0.--6. 1. " RX_SWEEP_CENTER_RESULT ,Result of RX impedance calibration" rgroup.byte 0x34++0x00 line.byte 0x00 "REG52,Receiver Shift Loader Parameter 0" hexmask.byte 0x00 0.--6. 1. " ATXDRR_SEL0 ,Debug purpose" group.byte 0x35++0x00 line.byte 0x00 "REG53,EOMx Update Cnt Value" hexmask.byte 0x00 0.--6. 1. " EOMX_UPDATE_CNT_VALUE ,Number of cycles that the eom controller must hold the state of the current code" rgroup.byte 0x36++0x01 line.byte 0x00 "REG54,Transmitter P Shift Loader Parameter 0-0" line.byte 0x01 "REG55,Transmitter P Shift Loader Parameter 0-1" group.byte 0x38++0x00 line.byte 0x00 "REG56,Transmitter P Shift Loader Parameter 0-2" bitfld.byte 0x00 5.--7. " EOM_DONE_CNT_VALUE_A ,Number of cycles that we must wait before we can sample the mismatch or match count" "0,1,2,3,4,5,6,7" rbitfld.byte 0x00 0.--4. " ATXDRP_DYN_3 ,ATXDRP_DYN defines the Transmitted P parameter sent to the PHY for driving differential data on the transmit driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.byte 0x39++0x01 line.byte 0x00 "REG57,Transmitter A Shift Loader Parameter 0-0" line.byte 0x01 "REG58,Transmitter A Shift Loader Parameter 0-1" group.byte 0x3B++0x00 line.byte 0x00 "REG59,Transmitter A Shift Loader Parameter 0-2" bitfld.byte 0x00 5.--7. " EOM_DONE_CNT_VALUE_B ,Number of cycles that we must wait before we can sample the mismatch or match count" "0,1,2,3,4,5,6,7" rbitfld.byte 0x00 0.--4. " ATXDRA_DYN_3 ,Transmitted A parameter sent to the PHY for driving differential data on the transmit driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.byte 0x3C++0x14 line.byte 0x00 "REG60,Transmitter T Shift Loader Parameter 0-0" line.byte 0x01 "REG61,Transmitter T Shift Loader Parameter 0-1" line.byte 0x02 "REG62,Transmitter T Shift Loader Parameter 0-2" bitfld.byte 0x02 0.--4. " ATXDRT_DYN_3 ,Transmitted T parameter sent to the PHY for driving differential data on the transmit driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x03 "REG63,Transmitter P Shift Loader Parameter 1-0" line.byte 0x04 "REG64,Transmitter P Shift Loader Parameter 1-1" line.byte 0x05 "REG65,Transmitter P Shift Loader Parameter 1-2" bitfld.byte 0x05 0.--4. " ATXDRP_EI1_3 ,Transmitted A parameter sent to the PHY for being in electrical idle I on the transmit driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x06 "REG66,Transmitter A Shift Loader Parameter 1-0" line.byte 0x07 "REG67,Transmitter A Shift Loader Parameter 1-1" line.byte 0x08 "REG68,Transmitter A Shift Loader Parameter 1-2" bitfld.byte 0x08 0.--4. " ATXDRA_EI1_3 ,Transmitted A parameter sent to the PHY for being in electrical idle I on the transmit driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x09 "REG69,Transmitter T Shift Loader Parameter 1-0" line.byte 0x0A "REG70,Transmitter T Shift Loader Parameter 1-1" line.byte 0x0B "REG71,Transmitter T Shift Loader Parameter 1-2" bitfld.byte 0x0B 0.--4. " ATXDRT_EI1_3 ,Transmitted T parameter sent to the PHY for being in electrical idle I on the transmit driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x0C "REG72,Transmitter P Shift Loader Parameter 2-0" line.byte 0x0D "REG73,Transmitter P Shift Loader Parameter 2-1" line.byte 0x0E "REG74,Transmitter P Shift Loader Parameter 2-2" bitfld.byte 0x0E 0.--4. " ATXDRP_EI2_3 ,Transmitted A parameter sent to the PHY for being in electrical idle II on the transmit driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x0F "REG75,Transmitter A Shift Loader Parameter 2-0" line.byte 0x10 "REG76,Transmitter A Shift Loader Parameter 2-1" line.byte 0x11 "REG77,Transmitter A Shift Loader Parameter 2-2" bitfld.byte 0x11 0.--4. " ATXDRA_EI2_3 ,Transmitted A parameter sent to the PHY for being in electrical idle II on the transmit driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x12 "REG78,Transmitter T Shift Loader Parameter 2-0" line.byte 0x13 "REG79,Transmitter T Shift Loader Parameter 2-1" line.byte 0x14 "REG80,Transmitter T Shift Loader Parameter 2-2" bitfld.byte 0x14 0.--4. " ATXDRT_EI2_3 ,Transmitted T parameter sent to the PHY for being in electrical idle II on the transmit driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x51++0x03 line.byte 0x00 "REG81,Override Calibration Register" bitfld.byte 0x00 7. " OVER_CTLE ,Override the CTLE calibration result with the content of reg140 register content" "0,1" bitfld.byte 0x00 5.--6. " OVER_RXES ,Override the RxEs calibration result with the content of reg135 register content" "0,1,2,3" bitfld.byte 0x00 2.--4. " OVER_RXDM ,Override the RxDm calibration result with the content of reg134 register content" "0,1,2,3,4,5,6,7" bitfld.byte 0x00 0.--1. " OVER_SCH ,Override the Schmitt trigger calibration result with the content of reg99 register content" "0,1,2,3" line.byte 0x01 "REG82,Force Receiver Shift Loader Parameter 0" line.byte 0x02 "REG83,Force Receiver Shift Loader Parameter 1" line.byte 0x03 "REG84,Force Receiver Shift Loader Parameter 2" bitfld.byte 0x03 0.--4. " FORCE_ATXDRR_3 ,Defines the RX Impedance and RX equalization fields used when the override RX settings register is set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.byte 0x55++0x0B line.byte 0x00 "REG85,Force Transmitter P Shift Loader Parameter 0" line.byte 0x01 "REG86,Force Transmitter P Shift Loader Parameter 1" line.byte 0x02 "REG87,Force Transmitter P Shift Loader Parameter 2" bitfld.byte 0x02 0.--4. " FORCE_ATXDRR_3 ,Transmitted P parameter sent to the PHY for driving differential data on the transmit driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x03 "REG88,Force Transmitter A Shift Loader Parameter 0" line.byte 0x04 "REG89,Force Transmitter A Shift Loader Parameter 1" line.byte 0x05 "REG90,Force Transmitter A Shift Loader Parameter 2" bitfld.byte 0x05 0.--4. " FORCE_ATXDRA_3 ,Transmitted A parameter sent to the PHY for driving differential data on the transmit driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x06 "REG91,Force Transmitter T Shift Loader Parameter 0" line.byte 0x07 "REG92,Force Transmitter T Shift Loader Parameter 1" line.byte 0x08 "REG93,Force Transmitter T Shift Loader Parameter 2" bitfld.byte 0x08 0.--4. " FORCE_ATXDRT_3 ,Transmitted T parameter sent to the PHY for driving differential data on the transmit driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x09 "REG94,RxDP Offset Calibration Result" bitfld.byte 0x09 7. " CALIB_ERR[1] ,Negative overflow of calibration result" "Not occurred,Occurred" bitfld.byte 0x09 6. " CALIB_ERR[0] ,Positive overflow of calibration result" "Not occurred,Occurred" bitfld.byte 0x09 5. " ARXDPDIR ,Sign of voltage applied to aRxD settings for RX offset calibration" "0,1" bitfld.byte 0x09 0.--4. " ARXDPNULL ,Voltage applied to aRxD settings for RX offset calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x0A "REG95,RxT Offset Calibration Result" bitfld.byte 0x0A 7. " CALIB_ERR[1] ,Negative overflow of calibration result" "Not occurred,Occurred" bitfld.byte 0x0A 6. " CALIB_ERR[0] ,Positive overflow of calibration result" "Not occurred,Occurred" bitfld.byte 0x0A 5. " ARXDPDIR ,Sign of voltage applied to aRxT settings for RX offset calibration" "0,1" bitfld.byte 0x0A 0.--4. " ARXDPNULL ,Voltage applied to aRxD settings for RX offset calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x0B "REG96,Schmitt Trigger Calibration Result" bitfld.byte 0x0B 6.--7. " ASCH_ERR ,ASCH_ERR" "0,1,2,3" bitfld.byte 0x0B 4. " ASCHDIR ,Sign of voltage applied for Schmitt trigger offset calibration" "0,1" bitfld.byte 0x0B 0.--3. " ASCHDIR ,Voltage applied for Schmitt trigger offset calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x61++0x03 line.byte 0x00 "REG97,Force RxDP Offset Calibration Result" bitfld.byte 0x00 5. " F_ARXDPDIR ,Force the sign of the voltage to apply to aRxDp settings for RX offset calibration" "0,1" bitfld.byte 0x00 0.--4. " F_ARXDPNULL ,Force the voltage to apply to aRxDp settings for RX offset calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x01 "REG98,Force RxT Offset Calibration Result" bitfld.byte 0x01 5. " F_ARXTDIR ,Force the sign of the voltage to apply to aRxT settings for RX offset calibration" "0,1" bitfld.byte 0x01 0.--4. " F_ARXTNULL ,Force the voltage to apply to aRxT settings for RX offset calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x02 "REG99,Force Schmitt Trigger Calibration Result" bitfld.byte 0x02 5. " F_ASCHCAL ,Force calibration mode of the Schmitt trigger offset by software control" "0,1" bitfld.byte 0x02 4. " F_ASCHDIR ,Force the sign of the voltage to apply for Schmitt trigger offset calibration" "0,1" bitfld.byte 0x02 0.--3. " F_ASCHNULL ,Force the voltage to apply for Schmitt trigger offset calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x03 "REG100,PRBS Control Register" bitfld.byte 0x03 6. " PRBS_CHK ,When set this signal starts the PRBS pattern checker" "0,1" bitfld.byte 0x03 4.--5. " ACTAG_REG ,Contains the ACJTAG register of the PHY which is loaded when the update of the PMA settings is required" "0,1,2,3" bitfld.byte 0x03 2.--3. " PRBS_TYP ,Defines the type of PRBS pattern which is applied" "PRBS7,PRBS11,PRBS23,PRBS31" bitfld.byte 0x03 1. " LPBK_EN ,When set the PMA is put in Near-End Loopback" "0,1" newline bitfld.byte 0x03 0. " PRBS_GEN ,When set this signal starts the PRBS pattern transmission" "0,1" rgroup.byte 0x65++0x00 line.byte 0x00 "REG101,PRBS Error Counter Register" group.byte 0x66++0x17 line.byte 0x00 "REG102,PHY Reset Override Register" bitfld.byte 0x00 7. " RXHF_CLKDN ,RX PLL VCO settings by applying a static zero to PMA aRxHfClkDnb signal disable" "No,Yes" bitfld.byte 0x00 6. " TXHF_CLKDN ,TX PLL VCO by applying a static zero to PMA aTxHfClkDnb signal disable" "No,Yes" bitfld.byte 0x00 5. " RXPLLRST ,Reset the RX PLL settings by applying a static zero to PMA aCdrPllRstb signal" "No reset,Reset" bitfld.byte 0x00 4. " TXPLLRST ,TX PLL settings by applying a static zero to PMA aTxPllRstb signal initialization" "Not initialized,Initialized" newline bitfld.byte 0x00 3. " RXPLL_INIT ,RX PLL settings by applying a static one to PMA aRxPllDivInit signal initialization" "Not initialized,Initialized" bitfld.byte 0x00 2. " TXPLL_INIT ,TX PLL settings by applying a static one to PMA aTxPllDivInit signal initialization" "Not initialized,Initialized" bitfld.byte 0x00 1. " RX_HIZ ,Forces the RX driver to hiZ applying a static one to PMA aForceRxHiZ signal" "Not forced,Forced" bitfld.byte 0x00 0. " TX_HIZ ,Forces the TX driver to hiZ applying a static one to PMA aForceTxHiZ signal" "Not forced,Forced" line.byte 0x01 "REG103,PHY Power Override Register" bitfld.byte 0x01 0. " RX_PWRDN ,RX PMA logic to be in power-down mode force" "Not forced,Forced" line.byte 0x02 "REG104,Custom Pattern Byte 0" line.byte 0x03 "REG105,Custom Pattern Byte 1" line.byte 0x04 "REG106,Custom Pattern Byte 2" line.byte 0x05 "REG107,Custom Pattern Byte 3" line.byte 0x06 "REG108,Custom Pattern Byte 4" line.byte 0x07 "REG109,Custom Pattern Byte 5" line.byte 0x08 "REG110,Custom Pattern Byte 6" line.byte 0x09 "REG111,Custom Pattern Byte 7" line.byte 0x0A "REG112,Custom Pattern Byte 8" line.byte 0x0B "REG113,Custom Pattern Byte 9" line.byte 0x0C "REG114,Custom Pattern Control" bitfld.byte 0x0C 6. " CUST_AUTO ,Cust Auto" "0,1" bitfld.byte 0x0C 5. " CUST_SKIP ,RX word alignment manual mode" "0,1" bitfld.byte 0x0C 4. " CUST_CHK ,Enable error counter" "Disabled,Enabled" bitfld.byte 0x0C 1.--3. " CUST_TYP ,Defines whether the custom pattern generated on the link is generated by the custom pattern register or by one of the hard-coded pattern" "0,1,2,3,4,5,6,7" newline bitfld.byte 0x0C 0. " CUST_SEL ,When set this signal replaces the PRBS data transmitted on the link by the custom pattern" "0,1" line.byte 0x0D "REG115,Custom Pattern Status Register" bitfld.byte 0x0D 5.--7. " CUST_STATE ,Reports the current state of the custom pattern word alignment state machine" "0,1,2,3,4,5,6,7" bitfld.byte 0x0D 4. " CUST_SYNC ,Reports that the custom pattern is word aligned" "0,1" bitfld.byte 0x0D 0.--3. " CUST_ERROR ,Number of error detected by the logic when the custom word aligner is in sync" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x0E "REG116,PCS Loopback Control" bitfld.byte 0x0E 6. " RX_POLINV ,Inverts the polarity of data on the received data" "0,1" bitfld.byte 0x0E 5. " TX_POLINV ,Inverts the polarity of data on the transmitted data" "0,1" bitfld.byte 0x0E 4. " EFF_LPBK ,Activates the far-end loopback through PCIe elastic buffer fifo assuming 0ppm between recovered clock and transmit clock" "0,1" rbitfld.byte 0x0E 3. " MESO_SYNC ,Reports whether mesochronous clock alignment state machine has completed its process having thus aligned CDR receive clock to transmit clock" "0,1" newline bitfld.byte 0x0E 2. " MESO_LPBK ,Reports whether mesochronous clock alignment state machine has completed its process having thus aligned CDR receive clock to Transmit clock" "0,1" bitfld.byte 0x0E 1. " PAR_LPBK ,Enables the parallel loopback mode which forces the transmitted PIPE 10-bit encoded data to be loopbacked to the receiver PIPE RX interface" "Disabled,Enabled" bitfld.byte 0x0E 0. " PLESIO_LPBK ,Enables the plesiochronous loopback mode which forces the PCS to loopback data from RX back to TX after the PCIe elastic buffer function" "Disabled,Enabled" line.byte 0x0F "REG117,Gen1 Transmit PLL Current Charge Pump" bitfld.byte 0x0F 0.--2. " ATXICP_RATE0 ,Defines the TX PLL charge pump current when the PMA is running in PCIe Gen1 speed or in any other protocol" "0,1,2,3,4,5,6,7" line.byte 0x10 "REG118,Gen1 Receive PLL Current Charge Pump" bitfld.byte 0x10 4.--6. " ARXCDRICP_RATE0 ,Defines the RX PLL charge pump current when the PMA is CDR locked and running in PCIe Gen1 speed or in any other protocol" "0,1,2,3,4,5,6,7" bitfld.byte 0x10 0.--2. " ARXICP_RATE0 ,Defines the RX PLL charge pump current when the PMA is frequency locked and running in PCIe Gen1 speed or in any other protocol." "0,1,2,3,4,5,6,7" line.byte 0x11 "REG119,Gen2 Transmit PLL Current Charge Pump" bitfld.byte 0x11 0.--2. " ATXICP_RATE1 ,Defines the TX PLL charge pump current when the PMA is running in PCIe Gen1 speed or in any other protocol" "0,1,2,3,4,5,6,7" line.byte 0x12 "REG120,Gen2 Receive PLL Current Charge Pump" bitfld.byte 0x12 4.--6. " ARXCDRICP_RATE1 ,Defines the RX PLL charge pump current when the PMA is CDR locked and running in PCIe Gen1 speed or in any other protocol" "0,1,2,3,4,5,6,7" bitfld.byte 0x12 0.--2. " ARXICP_RATE1 ,Defines the RX PLL charge pump current when the PMA is frequency locked and running in PCIe Gen1 speed or in any other protocol." "0,1,2,3,4,5,6,7" line.byte 0x13 "REG121,CDR PLL Manual Control" bitfld.byte 0x13 2. " FINE_GRAIN ,Force the CDR PLL state machine when used in PCS-driven mode to fine grain state" "Not forced,Forced" bitfld.byte 0x13 1. " COARSE_GRAIN ,Force the CDR PLL state machine when used in PCS-driven mode to coarse grain state" "Not forced,Forced" bitfld.byte 0x13 0. " FREQ_LOCK ,Force the CDR PLL state machine when used in PCS-driven mode to frequency lock state" "Not forced,Forced" line.byte 0x14 "REG122,Gen3 Transmit PLL Current Charge Pump" bitfld.byte 0x14 4.--7. " CTLEBIAS ,Defines the Bias of the PMA hard-macro CTLE block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x14 0.--2. " ATXICP_RATE2 ,Defines the TX PLL charge pump current when the PMA is running in PCIe Gen2 speed or in any other protocol" "0,1,2,3,4,5,6,7" line.byte 0x15 "REG123,Gen3 Receive PLL Current Charge Pump" bitfld.byte 0x15 4.--6. " ARXCDRICP_RATE2 ,Defines the RX PLL charge pump current when the PMA is CDR locked and running in PCIe Gen3 speed or in any other protocol" "0,1,2,3,4,5,6,7" bitfld.byte 0x15 0.--2. " ARXICP_RATE2 ,Defines the RX PLL charge pump current when the PMA is frequency locked and running in PCIe Gen3 speed" "0,1,2,3,4,5,6,7" line.byte 0x16 "REG124,CTLE Gain Override And Bypass Control" bitfld.byte 0x16 5. " ES_PWRDN ,Enables to power down the Error Sampler" "Disabled,Enabled" bitfld.byte 0x16 4. " DFE_PWRDN ,Enables to power down the DFE" "Disabled,Enabled" bitfld.byte 0x16 2. " OVR_HINT3DB ,Enables to override the RX Preset Hint given by the MAC layer which controls the aRxCTLEgain3db pin of the PMA" "Disabled,Enabled" bitfld.byte 0x16 1. " OVR_GAIN3DB ,Defines the value on the aRxCTLEgain3db pin of the PMA when the ovr_hint register is set" "Disabled,Enabled" newline bitfld.byte 0x16 0. " CTLEBYPASS ,Defines the aRxCTLEbypass pin of the PMA" "Disabled,Enabled" line.byte 0x17 "REG125,PMA RsvCtl" rgroup.byte 0x7E++0x01 line.byte 0x00 "REG126,PMA RsvCtl" bitfld.byte 0x00 6. " PCIE2_MODE[2] ,PCIe gen3 mode of the TX PLL based on the current speed mode" "0,1" bitfld.byte 0x00 5. " [1] ,PCIe gen2 mode of the TX PLL based on the current speed mode" "0,1" bitfld.byte 0x00 4. " [0] ,PCIe gen1 mode of the TX PLL based on the current speed mode" "0,1" bitfld.byte 0x00 3. " ARXRSVSTS[3] ,Enables to read back the aRxRsvSts[3] output pins of the PMA" "Disabled,Enabled" newline bitfld.byte 0x00 2. " [2] ,Enables to read back the aRxRsvSts[2] output pins of the PMA" "Disabled,Enabled" bitfld.byte 0x00 1. " [1] ,Enables to read back the aRxRsvSts[1] output pins of the PMA" "Disabled,Enabled" bitfld.byte 0x00 0. " [0] ,Enables to read back the aRxRsvSts[0] output pins of the PMA" "Disabled,Enabled" line.byte 0x01 "REG127,PMA Test_out" bitfld.byte 0x01 7. " ASCHMITTOUT ,ASCHMITTOUT" "0,1" bitfld.byte 0x01 6. " AFARENDRXABSENT ,AFARENDRXABSENT" "0,1" bitfld.byte 0x01 5. " ARXCLKSTATBLE ,ARXCLKSTATBLE" "0,1" bitfld.byte 0x01 4. " ATXCLKSTABLE ,ATXCLKSTABLE" "0,1" newline bitfld.byte 0x01 3. " ACDRDIAGOUT ,ACDRDIAGOUT" "0,1" bitfld.byte 0x01 2. " ATRANDET ,ATRANDET" "0,1" bitfld.byte 0x01 1. " ACDRPLLRST ,ACDRPLLRST" "0,1" bitfld.byte 0x01 0. " ATXPLLRST ,ATXPLLRST" "0,1" wgroup.byte 0x80++0x00 line.byte 0x00 "REG128,Update Settings Command Register" rgroup.byte 0x84++0x01 line.byte 0x00 "REG132,RxDM Offset Calibration Result" bitfld.byte 0x00 7. " CALIB_ERR[1] ,Negative overflow of calibration result" "Not occurred,Occurred" bitfld.byte 0x00 6. " CALIB_ERR[0] ,Positive overflow of calibration result" "Not occurred,Occurred" bitfld.byte 0x00 5. " ARXDMDIR ,Sign of voltage applied to aRxDm settings for RX offset calibration" "0,1" bitfld.byte 0x00 0.--4. " ARXDMNULL ,Voltage applied to aRxDm settings for RX offset calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x01 "REG133,RxEs Offset Calibration Result" bitfld.byte 0x01 7. " CALIB_ERR[1] ,Negative overflow of calibration result" "Not occurred,Occurred" bitfld.byte 0x01 6. " CALIB_ERR[0] ,Positive overflow of calibration result" "Not occurred,Occurred" bitfld.byte 0x01 5. " ARXESDIR ,Sign of voltage applied to aRxEs settings for RX offset calibration" "0,1" bitfld.byte 0x01 0.--4. " ARXESNULL ,Voltage applied to aRxEs settings for RX offset calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x86++0x02 line.byte 0x00 "REG134,Force RxDM Offset Calibration Result" bitfld.byte 0x00 5. " F_ARXDMDIR ,Force the sign of the voltage to apply to aRxDm settings for RX offset calibration" "0,1" bitfld.byte 0x00 0.--4. " F_ARXDMNULL ,Force the voltage to apply to aRxDm settings for RX offset calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x01 "REG135,Force RxEs Offset Calibration Result" bitfld.byte 0x01 5. " F_ARXESDIR ,Force the sign of the voltage to apply to aRxEs settings for RX offset calibration" "0,1" bitfld.byte 0x01 0.--4. " F_ARXESNULL ,Force the voltage to apply to aRxEs settings for RX offset calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x02 "REG136,RSA/CTLE Calibration Override Control" bitfld.byte 0x02 6. " ARXEOM_PWRDN ,Power down the eom rsa" "0,1" bitfld.byte 0x02 5. " ARXDMPWRDN ,Power down the dm rsa" "0,1" bitfld.byte 0x02 4. " ARXDPPWRDN ,Power down the dp rsa" "0,1" bitfld.byte 0x02 2. " ARXOVR_OUT ,Control of the RSA/CTLE calibration through register space" "0,1" newline bitfld.byte 0x02 1. " ARXSEL_OUT ,Value applied to the aRxSel pin of the PMA when ARXOVR_OUT register is set" "0,1" bitfld.byte 0x02 0. " ARXCAL_OUT ,Value applied to the aRxCal pin of the PMA when ARXOVR_OUT register is set" "0,1" rgroup.byte 0x89++0x00 line.byte 0x00 "REG137,RSA Output Signals" bitfld.byte 0x00 4. " ASCH_OUT ,Aschnullout output of the PMA" "0,1" bitfld.byte 0x00 3. " ARXT_OUT ,Arxtnullout output of the PMA" "0,1" bitfld.byte 0x00 2. " ARXES_OUT ,Arxesnullout output of the PMA" "0,1" bitfld.byte 0x00 1. " ARXDM_OUT ,Arxdmnullout output of the PMA" "0,1" newline bitfld.byte 0x00 0. " ARXDP_OUT ,Arxdpnullout output of the PMA" "0,1" group.byte 0x8A++0x02 line.byte 0x00 "REG138,DFE Bias Control" bitfld.byte 0x00 0.--3. " DFE_BIAS ,Controls the Bias applied to the DFE circuit of the PMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x01 "REG139,RSA Ctat And Ptat Control" bitfld.byte 0x01 4.--7. " ARXRSAPTAT ,Control aRxRSAptat input pins of the PMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x01 0.--3. " ARXRSACTAT ,Control aRxRSActat input pins of the PMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x02 "REG140,Force CTLE Offset Calibration Settings" bitfld.byte 0x02 5. " F_ARXCTLEDIR ,Force the sign of the voltage to apply to CTLE settings for RX offset calibration" "0,1" bitfld.byte 0x02 0.--4. " F_ARXCTLENULL ,Force the voltage to apply to CTLE settings for RX offset calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.byte 0x8D++0x00 line.byte 0x00 "REG141,CTLE Offset Calibration Result" bitfld.byte 0x00 6.--7. " ARXCTLE_ERR ,ARXCTLE_ERR" "0,1,2,3" bitfld.byte 0x00 4. " ARXCTLEDIR ,Sign of voltage applied to CTLE settings for RX offset calibration" "0,1" bitfld.byte 0x00 0.--3. " ARXCTLENULL ,Voltage applied to CTLE settings for RX offset calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x90++0x0C line.byte 0x00 "REG144,Error Scale 1" bitfld.byte 0x00 4.--7. " RL2 ,Non-transition sample weighting factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " RL1 ,Transition sample weighting factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x01 "REG145,Error Scale 2" bitfld.byte 0x01 4.--7. " RL3 ,Extended non-transition (>2) sample weighting factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x02 "REG146,L1 Low Power PLL Lock Time" bitfld.byte 0x02 3.--7. " I1_EXIT_PLL_LOCK_TIME ,Minimum time to reset the TX and RX PLL when entering L1 substate or L1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.byte 0x02 0.--2. " I1_ENTER_PLL_RESET_TIME ,Minimum time to reset the TX and RX PLL when entering L1 substate or L1" "0,1,2,3,4,5,6,7" line.byte 0x03 "REG147,Aux Idle Max" line.byte 0x04 "REG148,Elastic Buffer Gen1/2 10b: Almost Empty Threshold" bitfld.byte 0x04 0.--5. " ALMOST_EMPTY_10B ,From this value the elastic buffer starts to add SKPOS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x05 "REG149,Elastic Buffer Gen1/2 10b: Middle Value Threshold" bitfld.byte 0x05 0.--5. " MID_VALU_10B ,From this value the elastic buffer starts to read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x06 "REG150,Elastic Buffer Gen1/2 10b: Almost Full Threshold" bitfld.byte 0x06 0.--5. " ALMOST_FULL_10B ,From this value the elastic buffer starts to add SKPOS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x07 "REG151,Elastic Buffer Gen1/2 20b: Almost Empty Threshold" bitfld.byte 0x07 0.--5. " ALMOST_EMPTY__20B ,From this value the elastic buffer starts to add SKPOS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x08 "REG152,Elastic Buffer Gen1/2 20b: Middle Value Threshold" bitfld.byte 0x08 0.--5. " MID_VALU_20B ,From this value the elastic buffer starts to read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x09 "REG153,Elastic Buffer Gen1/2 20b: Almost Full Threshold" bitfld.byte 0x09 0.--5. " ALMOST_FULL_20B ,From this value the elastic buffer starts to add SKPOS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x0A "REG154,Elastic Buffer Gen3: Almost Empty Threshold" bitfld.byte 0x0A 0.--5. " ALMOST_EMPTY__GEN3 ,From this value the elastic buffer starts to add SKPOS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x0B "REG155,Elastic Buffer Gen3: Middle Value Threshold" bitfld.byte 0x0B 0.--5. " MID_VALU_GEN3 ,From this value the elastic buffer starts to read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x0C "REG156,Elastic Buffer Gen3: Almost Full Threshold" bitfld.byte 0x0C 0.--5. " ALMOST_FULL_GEN3 ,From this value the elastic buffer starts to add SKPOS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x9E++0x00 line.byte 0x00 "REG158,RxEOM Offset Calibration Result" bitfld.byte 0x00 7. " CALIB_ERR[1] ,Negative overflow of calibration result" "Not occurred,Occurred" bitfld.byte 0x00 6. " CALIB_ERR[0] ,Positive overflow of calibration result" "Not occurred,Occurred" bitfld.byte 0x00 5. " ARXEOMDIR ,Sign of voltage applied to aRxEOM settings for RX offset calibration" "0,1" bitfld.byte 0x00 0.--4. " ARXEOMNULL ,Voltage applied to aRxEOM settings for RX offset calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x9F++0x04 line.byte 0x00 "REG159,Force RxEOM Offset Calibration Settings" bitfld.byte 0x00 5. " F_ARXCEOMDIR ,Force the sign of the voltage to apply to aRxEOM settings for RX offset calibration" "Not forced,Forced" bitfld.byte 0x00 0.--4. " F_ARXEOMNULL ,Force the sign of the voltage to apply to aRxEOM settings for RX offset calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x01 "REG160,EOM X And Direction Control" bitfld.byte 0x01 7. " EOM1DIR ,Select the EOM direction 1 (previous bit) for collecting samples" "0,1" bitfld.byte 0x01 6. " EOM0DIR ,Select the EOM direction 1 (current bit) for collecting samples" "0,1" bitfld.byte 0x01 0.--5. " EOMX ,Control the EOM X (time) offset applied to the RSA sampler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x02 "REG161,EOM Y Control" line.byte 0x03 "REG162,EOM Time MSB Control" line.byte 0x04 "REG163,EOM Time LSB Control" if (((per.l(ad:0x5F1A0000+0xA4))&0xC0)==0x00) group.byte 0xA4++0x00 line.byte 0x00 "REG164,EOM Execution Control" bitfld.byte 0x00 6.--7. " EOMMODE ,Type of eye monitoring to perform" "0,1,2,3" bitfld.byte 0x00 5. " EOMRDSEL ,Secondary results from the EOM computation in EOMMode==00b or 11b" "0,1" bitfld.byte 0x00 4. " EOMDIVDIS ,Disable the execution of the division operation allowing to read back directly the number of error samples gathered and the number of valid samples gathered" "No,Yes" bitfld.byte 0x00 3. " EOMCTRL0_LOW ,Override bit for controlling the reset into the PMA EOM unit" "Not overridden,Overridden" newline bitfld.byte 0x00 0. " EOMSTART ,EOM accumulation logic start executing the accumulation sequence for a time specified in EOM_Time" "Not started,Started" else group.byte 0xA4++0x00 line.byte 0x00 "REG164,EOM Execution Control" bitfld.byte 0x00 6.--7. " EOMMODE ,Type of eye monitoring to perform" "0,1,2,3" bitfld.byte 0x00 5. " EOMRDSEL ,Secondary results from the EOM computation in EOMMode==00b or 11b" "0,1" textfld " " bitfld.byte 0x00 3. " EOMCTRL0_LOW ,Override bit for controlling the reset into the PMA EOM unit" "Not overridden,Overridden" newline bitfld.byte 0x00 0. " EOMSTART ,EOM accumulation logic start executing the accumulation sequence for a time specified in EOM_Time" "Not started,Started" endif group.byte 0xA5++0x02 line.byte 0x00 "REG165,EOM Result 0" line.byte 0x01 "REG166,EOM Result 1" line.byte 0x02 "REG167,EOM Result 2" group.byte 0xAF++0x08 line.byte 0x00 "REG175,Max RSA Calibration Wait Count" line.byte 0x01 "REG176,TX PLL F Settings And PCLK Ratio" bitfld.byte 0x01 4.--5. " TX_DIV_MODE2 ,Ratio between PCLK and aTxClk" "0,1,2,3" bitfld.byte 0x01 3. " TXF[3] ,Defines the aTxF[3] settings of the PMA macro" "0,1" bitfld.byte 0x01 2. " [2] ,Defines the aTxF[2] settings of the PMA macro" "0,1" bitfld.byte 0x01 1. " [1] ,Defines the aTxF[1] settings of the PMA macro" "0,1" newline bitfld.byte 0x01 0. " [0] ,Defines the aTxF[0] settings of the PMA macro" "0,1" line.byte 0x02 "REG177,TX PLL M And N Settings" bitfld.byte 0x02 6. " TXM[1] ,Defines the aTxM[1] settings of the PMA macro" "0,1" bitfld.byte 0x02 5. " [0] ,Defines the aTxM[0] settings of the PMA macro" "0,1" bitfld.byte 0x02 4. " TXN[4] ,Defines the aTxN[4] settings of the PMA macro" "0,1" bitfld.byte 0x02 3. " [3] ,Defines the aTxN[3] settings of the PMA macro" "0,1" newline bitfld.byte 0x02 2. " [2] ,Defines the aTxN[2] settings of the PMA macro" "0,1" bitfld.byte 0x02 1. " [1] ,Defines the aTxN[1] settings of the PMA macro" "0,1" bitfld.byte 0x02 0. " [0] ,Defines the aTxN[0] settings of the PMA macro" "0,1" line.byte 0x03 "REG178,CDR PLL F Settings And PCLK Ratio" bitfld.byte 0x03 4.--5. " RX_DIV_MODE2 ,Ratio between aRxClkp and internal rx_clk which clocks the RX PCS PCIe logic" "0,1,2,3" bitfld.byte 0x03 3. " RXF[3] ,Defines the aRxF[3] settings of the PMA macro" "0,1" bitfld.byte 0x03 2. " [2] ,Defines the aRxF[2] settings of the PMA macro" "0,1" bitfld.byte 0x03 1. " [1] ,Defines the aRxF[1] settings of the PMA macro" "0,1" newline bitfld.byte 0x03 0. " [0] ,Defines the aRxF[0] settings of the PMA macro" "0,1" line.byte 0x04 "REG179,CDR PLL M And N Settings" bitfld.byte 0x04 6. " RXM[1] ,Defines the aRxM[1] settings of the PMA macro" "0,1" bitfld.byte 0x04 5. " [0] ,Defines the aRxM[0] settings of the PMA macro" "0,1" bitfld.byte 0x04 4. " RXN[4] ,Defines the aRxN[4] settings of the PMA macro" "0,1" bitfld.byte 0x04 3. " [3] ,Defines the aRxN[3] settings of the PMA macro" "0,1" newline bitfld.byte 0x04 2. " [2] ,Defines the aRxN[2] settings of the PMA macro" "0,1" bitfld.byte 0x04 1. " [1] ,Defines the aRxN[1] settings of the PMA macro" "0,1" bitfld.byte 0x04 0. " [0] ,Defines the aRxN[0] settings of the PMA macro" "0,1" line.byte 0x05 "REG180,RX Equalization Low Frequency LF" bitfld.byte 0x05 0.--5. " LF ,PCI-Express Low-Frequency LF used during RX equalization training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x06 "REG181,A2 Gain During CTLE Calibration" bitfld.byte 0x06 6. " 3DB_CALIB ,CTLE 3dB gain applied during CTLE calibration phase" "0,1" bitfld.byte 0x06 0.--5. " A2GAIN_CALIB ,A2 Gain applied during CTLE calibration phase" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x07 "REG182,Activity Detector Timeout 0 in Gen3" line.byte 0x08 "REG183,Activity Detector Timeout 1 in Gen3" group.byte 0xB8++0x00 line.byte 0x00 "REG184,Preset0 Post-Cursor And Pre-Cursor Settings" bitfld.byte 0x00 4.--7. " PRESET0_POSTCURSOR ,PCI-Express C-1 setting corresponding to Preset Index 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PRESET0_PRECURSOR ,PCI-Express C+1 setting corresponding to Preset Index 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xB9++0x00 line.byte 0x00 "REG185,Preset1 Post-Cursor And Pre-Cursor Settings" bitfld.byte 0x00 4.--7. " PRESET1_POSTCURSOR ,PCI-Express C-1 setting corresponding to Preset Index 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PRESET1_PRECURSOR ,PCI-Express C+1 setting corresponding to Preset Index 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xBA++0x00 line.byte 0x00 "REG186,Preset2 Post-Cursor And Pre-Cursor Settings" bitfld.byte 0x00 4.--7. " PRESET2_POSTCURSOR ,PCI-Express C-1 setting corresponding to Preset Index 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PRESET2_PRECURSOR ,PCI-Express C+1 setting corresponding to Preset Index 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xBB++0x00 line.byte 0x00 "REG187,Preset3 Post-Cursor And Pre-Cursor Settings" bitfld.byte 0x00 4.--7. " PRESET3_POSTCURSOR ,PCI-Express C-1 setting corresponding to Preset Index 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PRESET3_PRECURSOR ,PCI-Express C+1 setting corresponding to Preset Index 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xBC++0x00 line.byte 0x00 "REG188,Preset4 Post-Cursor And Pre-Cursor Settings" bitfld.byte 0x00 4.--7. " PRESET4_POSTCURSOR ,PCI-Express C-1 setting corresponding to Preset Index 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PRESET4_PRECURSOR ,PCI-Express C+1 setting corresponding to Preset Index 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xBD++0x00 line.byte 0x00 "REG189,Preset5 Post-Cursor And Pre-Cursor Settings" bitfld.byte 0x00 4.--7. " PRESET5_POSTCURSOR ,PCI-Express C-1 setting corresponding to Preset Index 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PRESET5_PRECURSOR ,PCI-Express C+1 setting corresponding to Preset Index 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xBE++0x00 line.byte 0x00 "REG190,Preset6 Post-Cursor And Pre-Cursor Settings" bitfld.byte 0x00 4.--7. " PRESET6_POSTCURSOR ,PCI-Express C-1 setting corresponding to Preset Index 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PRESET6_PRECURSOR ,PCI-Express C+1 setting corresponding to Preset Index 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xBF++0x00 line.byte 0x00 "REG191,Preset7 Post-Cursor And Pre-Cursor Settings" bitfld.byte 0x00 4.--7. " PRESET7_POSTCURSOR ,PCI-Express C-1 setting corresponding to Preset Index 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PRESET7_PRECURSOR ,PCI-Express C+1 setting corresponding to Preset Index 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xC0++0x00 line.byte 0x00 "REG192,Preset8 Post-Cursor And Pre-Cursor Settings" bitfld.byte 0x00 4.--7. " PRESET8_POSTCURSOR ,PCI-Express C-1 setting corresponding to Preset Index 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PRESET8_PRECURSOR ,PCI-Express C+1 setting corresponding to Preset Index 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xC1++0x00 line.byte 0x00 "REG193,Preset9 Post-Cursor And Pre-Cursor Settings" bitfld.byte 0x00 4.--7. " PRESET9_POSTCURSOR ,PCI-Express C-1 setting corresponding to Preset Index 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PRESET9_PRECURSOR ,PCI-Express C+1 setting corresponding to Preset Index 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xC3++0x04 line.byte 0x00 "REG195,RX Equalization Init Preset Count" bitfld.byte 0x00 0.--3. " PRESET_COUNT_INI ,Defines the initial preset count value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x01 "REG196,CDR PLL Coarse Grain Phase-Lock Timer Before RX Equalization" line.byte 0x02 "REG197,CDR PLL Coarse Grain Phase-Lock Timer After RX Equalization" line.byte 0x03 "REG198,CDR PLL Fine Grain Phase-Lock Timer Before RX Equalization" line.byte 0x04 "REG199,CDR PLL Fine Grain Phase-Lock Timer After RX Equalization" group.byte 0xC8++0x00 line.byte 0x00 "REG200,RX Preset Hint 0 Mapping To A0 A2 Gain And CTLEgain3db" bitfld.byte 0x00 6. " HINT0_3DB ,Mapping of the RX preset hint index 0 given by the MAC layer to the PMA aRxCTLEGain3db initial gain quantity" "0,1" bitfld.byte 0x00 3.--5. " HINT0_A0GAIN ,Mapping of the RX preset hint index 0 given by the MAC layer to the PMA A0 initial gain quantity (8*Y[2:0]+4)" "0,1,2,3,4,5,6,7" bitfld.byte 0x00 0.--2. " HINT0_A2GAIN ,Mapping of the RX preset hint index 0 given by the MAC layer to the PMA A2 initial gain quantity (8*Y[2:0]+4)" "0,1,2,3,4,5,6,7" group.byte 0xC9++0x00 line.byte 0x00 "REG201,RX Preset Hint 1 Mapping To A0 A2 Gain And CTLEgain3db" bitfld.byte 0x00 6. " HINT0_3DB ,Mapping of the RX preset hint index 1 given by the MAC layer to the PMA aRxCTLEGain3db initial gain quantity" "0,1" bitfld.byte 0x00 3.--5. " HINT0_A0GAIN ,Mapping of the RX preset hint index 1 given by the MAC layer to the PMA A0 initial gain quantity (8*Y[2:0]+4)" "0,1,2,3,4,5,6,7" bitfld.byte 0x00 0.--2. " HINT0_A2GAIN ,Mapping of the RX preset hint index 1 given by the MAC layer to the PMA A2 initial gain quantity (8*Y[2:0]+4)" "0,1,2,3,4,5,6,7" group.byte 0xCA++0x00 line.byte 0x00 "REG202,RX Preset Hint 2 Mapping To A0 A2 Gain And CTLEgain3db" bitfld.byte 0x00 6. " HINT0_3DB ,Mapping of the RX preset hint index 2 given by the MAC layer to the PMA aRxCTLEGain3db initial gain quantity" "0,1" bitfld.byte 0x00 3.--5. " HINT0_A0GAIN ,Mapping of the RX preset hint index 2 given by the MAC layer to the PMA A0 initial gain quantity (8*Y[2:0]+4)" "0,1,2,3,4,5,6,7" bitfld.byte 0x00 0.--2. " HINT0_A2GAIN ,Mapping of the RX preset hint index 2 given by the MAC layer to the PMA A2 initial gain quantity (8*Y[2:0]+4)" "0,1,2,3,4,5,6,7" group.byte 0xCB++0x00 line.byte 0x00 "REG203,RX Preset Hint 3 Mapping To A0 A2 Gain And CTLEgain3db" bitfld.byte 0x00 6. " HINT0_3DB ,Mapping of the RX preset hint index 3 given by the MAC layer to the PMA aRxCTLEGain3db initial gain quantity" "0,1" bitfld.byte 0x00 3.--5. " HINT0_A0GAIN ,Mapping of the RX preset hint index 3 given by the MAC layer to the PMA A0 initial gain quantity (8*Y[2:0]+4)" "0,1,2,3,4,5,6,7" bitfld.byte 0x00 0.--2. " HINT0_A2GAIN ,Mapping of the RX preset hint index 3 given by the MAC layer to the PMA A2 initial gain quantity (8*Y[2:0]+4)" "0,1,2,3,4,5,6,7" group.byte 0xCC++0x00 line.byte 0x00 "REG204,RX Preset Hint 4 Mapping To A0 A2 Gain And CTLEgain3db" bitfld.byte 0x00 6. " HINT0_3DB ,Mapping of the RX preset hint index 4 given by the MAC layer to the PMA aRxCTLEGain3db initial gain quantity" "0,1" bitfld.byte 0x00 3.--5. " HINT0_A0GAIN ,Mapping of the RX preset hint index 4 given by the MAC layer to the PMA A0 initial gain quantity (8*Y[2:0]+4)" "0,1,2,3,4,5,6,7" bitfld.byte 0x00 0.--2. " HINT0_A2GAIN ,Mapping of the RX preset hint index 4 given by the MAC layer to the PMA A2 initial gain quantity (8*Y[2:0]+4)" "0,1,2,3,4,5,6,7" group.byte 0xCD++0x00 line.byte 0x00 "REG205,RX Preset Hint 5 Mapping To A0 A2 Gain And CTLEgain3db" bitfld.byte 0x00 6. " HINT0_3DB ,Mapping of the RX preset hint index 5 given by the MAC layer to the PMA aRxCTLEGain3db initial gain quantity" "0,1" bitfld.byte 0x00 3.--5. " HINT0_A0GAIN ,Mapping of the RX preset hint index 5 given by the MAC layer to the PMA A0 initial gain quantity (8*Y[2:0]+4)" "0,1,2,3,4,5,6,7" bitfld.byte 0x00 0.--2. " HINT0_A2GAIN ,Mapping of the RX preset hint index 5 given by the MAC layer to the PMA A2 initial gain quantity (8*Y[2:0]+4)" "0,1,2,3,4,5,6,7" group.byte 0xCE++0x00 line.byte 0x00 "REG206,RX Preset Hint 6 Mapping To A0 A2 Gain And CTLEgain3db" bitfld.byte 0x00 6. " HINT0_3DB ,Mapping of the RX preset hint index 6 given by the MAC layer to the PMA aRxCTLEGain3db initial gain quantity" "0,1" bitfld.byte 0x00 3.--5. " HINT0_A0GAIN ,Mapping of the RX preset hint index 6 given by the MAC layer to the PMA A0 initial gain quantity (8*Y[2:0]+4)" "0,1,2,3,4,5,6,7" bitfld.byte 0x00 0.--2. " HINT0_A2GAIN ,Mapping of the RX preset hint index 6 given by the MAC layer to the PMA A2 initial gain quantity (8*Y[2:0]+4)" "0,1,2,3,4,5,6,7" group.byte 0xCF++0x00 line.byte 0x00 "REG207,RX Preset Hint 7 Mapping To A0 A2 Gain And CTLEgain3db" bitfld.byte 0x00 6. " HINT0_3DB ,Mapping of the RX preset hint index 7 given by the MAC layer to the PMA aRxCTLEGain3db initial gain quantity" "0,1" bitfld.byte 0x00 3.--5. " HINT0_A0GAIN ,Mapping of the RX preset hint index 7 given by the MAC layer to the PMA A0 initial gain quantity (8*Y[2:0]+4)" "0,1,2,3,4,5,6,7" bitfld.byte 0x00 0.--2. " HINT0_A2GAIN ,Mapping of the RX preset hint index 7 given by the MAC layer to the PMA A2 initial gain quantity (8*Y[2:0]+4)" "0,1,2,3,4,5,6,7" group.byte 0xD0++0x0E line.byte 0x00 "REG208,Pre-Equalization A2 And A1 Gain" bitfld.byte 0x00 3.--5. " PRE_A1COEF ,The coefficient gain for A1 gain used in the Preliminary Phase of RX Equalization" "0,1,2,3,4,5,6,7" bitfld.byte 0x00 0.--2. " PRE_A2COEF ,The coefficient gain for A2 gain used in the Preliminary Phase of RX Equalization" "0,1,2,3,4,5,6,7" line.byte 0x01 "REG209,Pre-Equalization A0 Gain And Iteration Count" bitfld.byte 0x01 7. " GEN3_ENA ,Enables the adaptive equalization to run in preliminary phase of RX Equalization when the link is running in gen3 speed mode" "Disabled,Enabled" bitfld.byte 0x01 6. " GEN12_ENA ,Enables the adaptive equalization to run in preliminary phase of RX Equalization when the link is running in gen1 or gen2 speed mode" "Disabled,Enabled" bitfld.byte 0x01 3.--5. " PRE_ITERCNT ,Number of iteration to gather samples in each direction of evaluation used in the Preliminary Phase of RX Equalization" "0,1,2,3,4,5,6,7" bitfld.byte 0x01 0.--2. " PRE_A0COEF ,Coefficient gain for A0 gain used in the Preliminary Phase of RX Equalization" "0,1,2,3,4,5,6,7" line.byte 0x02 "REG210,Post-Equalization A2 And A1 Gain" bitfld.byte 0x02 3.--5. " POST_A1COEF ,Coefficient gain for A1 gain used in the Post Phase of RX Equalization" "0,1,2,3,4,5,6,7" bitfld.byte 0x02 0.--2. " POST_A2COEF ,Coefficient gain for A2 gain used in the Post Phase of RX Equalization" "0,1,2,3,4,5,6,7" line.byte 0x03 "REG211,Post-Equalization A0 Gain And Iteration Count" bitfld.byte 0x03 7. " GEN3_ENA ,Enables the adaptive equalization to run in post phase of RX Equalization when the link is running in gen3 speed mode" "Disabled,Enabled" bitfld.byte 0x03 6. " GEN12_ENA ,Enables the adaptive equalization to run in post phase of RX Equalization when the link is running in gen1 or gen2 speed mode" "Disabled,Enabled" bitfld.byte 0x03 3.--5. " POST_ITERCNT ,Number of iteration to gather samples in each direction of evaluation used in the Post Phase of RX Equalization" "0,1,2,3,4,5,6,7" bitfld.byte 0x03 0.--2. " POST_A0COEF ,Coefficient gain for A0 gain used in the Post Phase of RX Equalization" "0,1,2,3,4,5,6,7" line.byte 0x04 "REG212,Equalization Training A2 And A1 Gain" bitfld.byte 0x04 3.--5. " TRNG_A1COEF ,Coefficient gain for A1 gain used in the training Phase of RX Equalization" "0,1,2,3,4,5,6,7" bitfld.byte 0x04 0.--2. " TRNG_A2COEF ,Coefficient gain for A2 gain used in the training Phase of RX Equalization" "0,1,2,3,4,5,6,7" line.byte 0x05 "REG213,Equalization Training A0 Gain And Iteration Count" bitfld.byte 0x05 7. " GEN3_ENA ,Enables the adaptive equalization to run in training phase of RX Equalization when the link is running in gen3 speed mode" "Disabled,Enabled" bitfld.byte 0x05 6. " GEN12_ENA ,Enables the adaptive equalization to run in training phase of RX Equalization when the link is running in gen1 or gen2 speed mode" "Disabled,Enabled" bitfld.byte 0x05 3.--5. " TRNG_ITERCNT ,Number of iteration to gather samples in each direction of evaluation used in the training Phase of RX Equalization" "0,1,2,3,4,5,6,7" bitfld.byte 0x05 0.--2. " TRNG_A0COEF ,Coefficient gain for A0 gain used in the training Phase of RX Equalization" "0,1,2,3,4,5,6,7" line.byte 0x06 "REG214,RX Equalization Discard Timer" bitfld.byte 0x06 4.--6. " A_CHNGD_MAX ,Number of clock where the sample fifo need to be flushed after applying any change to the A2/A1/A0 gain" "0,1,2,3,4,5,6,7" bitfld.byte 0x06 0.--2. " CTLE_SETTLE ,Number of clock where the sample fifo need to be flushed after a direction a0dir/a1dir modification" "0,1,2,3,4,5,6,7" line.byte 0x07 "REG215,FOM Control Register 0" bitfld.byte 0x07 7. " FOM_HIRES ,When set the FOM is computed with 16x more samples than usual allowing for more precise FOM result" "0,1" bitfld.byte 0x07 4.--6. " PRE_FOM_AVG ,Encoding of the number of cycles where the tracking is performed for computing a more precise FOM result" "0,1,2,3,4,5,6,7" bitfld.byte 0x07 0.--3. " FOM_THR ,Threshold value for considering a A0 gain evaluation as PASS or FAIL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x08 "REG216,FOM Control Register 1" bitfld.byte 0x08 7. " PRE_FOM ,Defines whether to perform a 4-corner fom evaluation (when clear) or a fast FOM evaluation (when set) during initial lock" "4-corner,FOM" bitfld.byte 0x08 6. " CUR_FOM ,Defines whether to perform a 4-corner fom evaluation (when clear) or a fast FOM evaluation (when set) during the RX Equalization Training" "4-corner,FOM" bitfld.byte 0x08 3.--5. " CUR_FOM_AVG ,Contains an encoding of the number of cycles where the tracking is performed for computing a more precise FOM result" "0,1,2,3,4,5,6,7" bitfld.byte 0x08 0.--2. " FOM_ITERCNT ,Contains the number of iteration to perform during FOM processing for each direction" "0,1,2,3,4,5,6,7" line.byte 0x09 "REG217,Adaptive Equalization Enable Register" bitfld.byte 0x09 7. " BYP_AVG ,When this bit is set the sample gathering averaging function with Min/Max multiplication/division is bypassed" "Not bypassed,Bypassed" bitfld.byte 0x09 4.--6. " RXEQ_ALGO ,Defines which Equalization algorithm to apply in each data rate" "0,1,2,3,4,5,6,7" bitfld.byte 0x09 3. " MODE_BFF ,When this bit is set the adaptive equalization restart from the A2/A1/A0 gain settings corresponding to the best FOM found during Equalization training on exit from Electrical Idle" "0,1" bitfld.byte 0x09 0.--2. " RXEQ_ENABLE ,Enables to perform adaptive equalization in each data rate" "0,1,2,3,4,5,6,7" line.byte 0x0A "REG218,Adaptive Equalization Alert Register" bitfld.byte 0x0A 5.--7. " ALERT_ENABLE ,Enables the alert mechanism to signal loss of lock of the CDR PLL" "0,1,2,3,4,5,6,7" bitfld.byte 0x0A 0.--4. " MAX_VAR ,Maximum variation allowed for A0/A1/A2 gain to move in a period of 4 us" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x0B "REG219,Maximum Number Of Evaluation" line.byte 0x0C "REG220,Force Direction Result" bitfld.byte 0x0C 0.--5. " FORCE_DIR_RSLT ,Direction result which need to be reported to the MAC in 'manual equalization mode'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x0D "REG221,Force FOM Result" line.byte 0x0E "REG222,Maximum Number Of Evaluation In Pre-training" rgroup.byte 0xDF++0x10 line.byte 0x00 "REG223,Maximum Number Of Evaluation In Training" line.byte 0x01 "REG224,Direction Result" bitfld.byte 0x01 0.--1. " DIR_RSLT ,DIR which has been computed by the logic" "0,1,2,3" line.byte 0x02 "REG225,FOM Result" line.byte 0x03 "REG226,RX Equalization Current Number Of Evaluation" bitfld.byte 0x03 0.--3. " RXEQ_FSM ,Current state of the RX Equalization FSM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x04 "REG227,RX Equalization Current Number Of Evaluation" bitfld.byte 0x04 7. " EVAL_SEEN ,Reports that the PHY has seen at least one RX Equalization command from the MAC layer" "0,1" hexmask.byte 0x04 0.--6. 1. " EVAL_COUNT ,Number of times that the MAC has required an evaluation of RX Equalization" line.byte 0x05 "REG228,RX Equalization A0 Gain" bitfld.byte 0x05 0.--5. " A0GAIN ,Current setting applied to the A0 gain setting of the PMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x06 "REG229,RX Equalization A1 Gain" bitfld.byte 0x06 0.--5. " A1GAIN ,Current setting applied to the A1 gain setting of the PMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x07 "REG230,RX Equalization A2 Gain" bitfld.byte 0x07 0.--5. " A2GAIN ,Current setting applied to the A2 gain setting of the PMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x08 "REG231,Best FOM Found RX Equalization A0 Gain" bitfld.byte 0x08 0.--5. " BFF_A0GAIN ,A0 gain corresponding to the Best FOM found" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x09 "REG232,FOM Result A0DIR=0 / A1DIR=0" line.byte 0x0A "REG233,FOM Result A0DIR=1 / A1DIR=0" line.byte 0x0B "REG234,FOM Result A0DIR=0 / A1DIR=1" line.byte 0x0C "REG235,FOM Result A0DIR=1 / A1DIR=1" line.byte 0x0D "REG236,Best FOM Found RX Equalization A1 Gain" bitfld.byte 0x0D 0.--5. " BFF_A1GAIN ,A1 gain corresponding to the Best FOM found" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x0E "REG237,Best FOM Found RX Equalization A2 Gain" bitfld.byte 0x0E 0.--5. " BFF_A2GAIN ,A2 gain corresponding to the Best FOM found" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x0F "REG238,MAC Signal Snooping" bitfld.byte 0x0F 1.--3. " PRESETHINT ,The pipe_rxpresethint[3:0] signal status from the PIPE interface" "0,1,2,3,4,5,6,7" line.byte 0x10 "REG239,MAC Event Status" bitfld.byte 0x10 5. " INVALREQ ,Reports the pipe_invalidrequest signal status from the PIPE interface" "0,1" bitfld.byte 0x10 4. " GEN3_ENTRY ,Reports the rate has been modified to gen3 data rate" "0,1" bitfld.byte 0x10 3. " GEN2_ENTRY ,Reports the rate has been modified to gen2 data rate" "0,1" bitfld.byte 0x10 2. " GEN1_ENTRY ,Reports the rate has been modified to gen1 data rate" "0,1" newline bitfld.byte 0x10 1. " RXEQ_START ,Reports the event that pipe_rxeqeval signal has been asserted on the PIPE interface" "0,1" bitfld.byte 0x10 0. " RXEQ_STOP ,Reports the event that pipe_rxeqeval signal has been deasserted on the PIPE interface" "0,1" group.byte 0xF0++0x06 line.byte 0x00 "REG240,Force A0 Gain" bitfld.byte 0x00 7. " A0_FORCE ,Override the default behavior and force A0 to A0_init[5:0] value" "Not overridden,Overridden" bitfld.byte 0x00 6. " A0_FREEZE ,Overrides the default behavior and freeze A0 to its current value" "Not overridden,Overridden" bitfld.byte 0x00 0.--5. " A0_INIT ,Defines the initial value of A0 or the loaded value of A0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x01 "REG241,Force A0 Gain" bitfld.byte 0x01 7. " A1_FORCE ,Override the default behavior and force A1 to A1_init[5:0] value" "Not overridden,Overridden" bitfld.byte 0x01 6. " A1_FREEZE ,Overrides the default behavior and freeze A1 to its current value" "Not overridden,Overridden" bitfld.byte 0x01 0.--5. " A1_INIT ,Value of A1 or the loaded value of A1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x02 "REG242,Force A0 Gain" bitfld.byte 0x02 7. " A2_FORCE ,Override the default behavior and force A12 to A2_init[5:0] value" "Not overridden,Overridden" bitfld.byte 0x02 6. " A2_FREEZE ,Overrides the default behavior and freeze A2 to its current value" "Not overridden,Overridden" bitfld.byte 0x02 0.--5. " A2_INIT ,Value of A2 or the loaded value of A2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x03 "REG243,RX Equalization Training Override" bitfld.byte 0x03 7. " RXEQ_MANUAL ,Configures the RX Equalization in manual mode" "0,1" bitfld.byte 0x03 6. " OVR_CDR ,Forces the CDR PLL to perform a reset sequence" "No reset,Reset" bitfld.byte 0x03 5. " OVR_DIR ,Overrides the DIR result by the force_dir_rslt[7:0] register value in reg220" "Not overridden,Overridden" bitfld.byte 0x03 4. " OVR_FOM ,Overrides the FOM result by the force_fom_rslt[7:0] register value in reg221" "Not overridden,Overridden" newline bitfld.byte 0x03 0.--3. " RXEQ_STATE ,State of the RX Equalization state machine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x04 "REG244,FOM Compare Register" line.byte 0x05 "REG245,FOM Compare Result" rbitfld.byte 0x05 0. " FOM_PASS ,Comparison result for FOM comparison" "0,1" line.byte 0x06 "REG246,RX Equalization A0DIR/A1DIR Override And Alternate Direction Modes" bitfld.byte 0x06 5. " MIX_DIR ,When set the direction result is initially provided by the DSP gathered data samples and later on by the default direction algorithm" "0,1" bitfld.byte 0x06 4. " DSP_DIR ,When set the direction result is provided by the analysis of the gathered data done by the DSP to determine if additional post-cursor or pre-cursor are required" "0,1" bitfld.byte 0x06 2. " ADIR_OVR ,Enables to override the DSP control of the PMA hard macro A0DIR and A1DIR input" "Disabled,Enabled" bitfld.byte 0x06 1. " A1DIR_VAL ,Value applied on PMA hard macro A1DIR input when ADIR_OVR==1" "0,1" newline bitfld.byte 0x06 0. " A0DIR_VAL ,Value applied on PMA hard macro A0DIR input when ADIR_OVR==1" "0,1" rgroup.byte 0xF7++0x01 line.byte 0x00 "REG247,RX Equalization Farthest Gathered Samples" bitfld.byte 0x00 7. " OLD14 ,Old14" "0,1" bitfld.byte 0x00 6. " OLD13 ,Old13" "0,1" bitfld.byte 0x00 5. " OLD12 ,Old12" "0,1" bitfld.byte 0x00 4. " OLD11 ,Old11" "0,1" newline bitfld.byte 0x00 3. " NEW4 ,New4" "0,1" bitfld.byte 0x00 2. " NEW3 ,New3" "0,1" bitfld.byte 0x00 1. " NEW2 ,New2" "0,1" bitfld.byte 0x00 0. " NEW1 ,New1" "0,1" line.byte 0x01 "REG248,RX Equalization Gathered Samples" bitfld.byte 0x01 7. " ERR19 ,Err19" "0,1" bitfld.byte 0x01 6. " ERR18 ,Err18" "0,1" bitfld.byte 0x01 5. " NEW0 ,New0" "0,1" bitfld.byte 0x01 4. " OLD19 ,Old19" "0,1" newline bitfld.byte 0x01 3. " OLD18 ,Old18" "0,1" bitfld.byte 0x01 2. " OLD17 ,Old17" "0,1" bitfld.byte 0x01 1. " OLD16 ,Old16" "0,1" bitfld.byte 0x01 0. " OLD15 ,Old15" "0,1" group.byte 0xF9++0x06 line.byte 0x00 "REG249,DSP Direction LUT Post_cursor Sign 0" line.byte 0x01 "REG250,DSP Direction LUT Post_cursor Sign 1" line.byte 0x02 "REG251,DSP Direction LUT Post-cursor Amplitude 0" line.byte 0x03 "REG252,DSP Direction LUT Post-cursor Amplitude 1" line.byte 0x04 "REG253,DSP Direction LUT Pre-cursor Sign" line.byte 0x05 "REG254,DSP Direction LUT Pre-cursor Amplitude" line.byte 0x06 "REG255,Timer Gain1 And DSP Direction Timer" bitfld.byte 0x06 6.--7. " DIR_PRE_GAIN ,Gain applied to Pre-cursor samples for the DSP-based direction algorithm" "0,1,2,3" bitfld.byte 0x06 4.--5. " DIR_PST_GAIN ,Gain applied to Post-cursor samples for the DSP-based direction algorithm" "0,1,2,3" bitfld.byte 0x06 0.--3. " GAIN_TIMER1 ,Timer value used during Equalization Training phase" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "GPIO (General Purpose Input/Output)" base ad:0x5F170000 width 11. group.long 0x00++0x07 line.long 0x00 "DR,GPIO Data Register" bitfld.long 0x00 31. " DR[31] ,Data bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,Data bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,Data bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,Data bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,Data bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,Data bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,Data bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,Data bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,Data bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,Data bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,Data bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,Data bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,Data bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,Data bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,Data bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,Data bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,Data bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,Data bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,Data bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,Data bit 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,Data bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,Data bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,Data bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,Data bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,Data bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,Data bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,Data bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,Data bit 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,Data bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,Data bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,Data bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,Data bit 0" "Low,High" line.long 0x04 "GDIR,GPIO Direction Register" bitfld.long 0x04 31. " GDIR[31] ,GPIO direction 31 bit" "Input,Output" bitfld.long 0x04 30. " [30] ,GPIO direction 30 bit" "Input,Output" bitfld.long 0x04 29. " [29] ,GPIO direction 29 bit" "Input,Output" bitfld.long 0x04 28. " [28] ,GPIO direction 28 bit" "Input,Output" newline bitfld.long 0x04 27. " [27] ,GPIO direction 27 bit" "Input,Output" bitfld.long 0x04 26. " [26] ,GPIO direction 26 bit" "Input,Output" bitfld.long 0x04 25. " [25] ,GPIO direction 25 bit" "Input,Output" bitfld.long 0x04 24. " [24] ,GPIO direction 24 bit" "Input,Output" newline bitfld.long 0x04 23. " [23] ,GPIO direction 23 bit" "Input,Output" bitfld.long 0x04 22. " [22] ,GPIO direction 22 bit" "Input,Output" bitfld.long 0x04 21. " [21] ,GPIO direction 21 bit" "Input,Output" bitfld.long 0x04 20. " [20] ,GPIO direction 20 bit" "Input,Output" newline bitfld.long 0x04 19. " [19] ,GPIO direction 19 bit" "Input,Output" bitfld.long 0x04 18. " [18] ,GPIO direction 18 bit" "Input,Output" bitfld.long 0x04 17. " [17] ,GPIO direction 17 bit" "Input,Output" bitfld.long 0x04 16. " [16] ,GPIO direction 16 bit" "Input,Output" newline bitfld.long 0x04 15. " [15] ,GPIO direction 15 bit" "Input,Output" bitfld.long 0x04 14. " [14] ,GPIO direction 14 bit" "Input,Output" bitfld.long 0x04 13. " [13] ,GPIO direction 13 bit" "Input,Output" bitfld.long 0x04 12. " [12] ,GPIO direction 12 bit" "Input,Output" newline bitfld.long 0x04 11. " [11] ,GPIO direction 11 bit" "Input,Output" bitfld.long 0x04 10. " [10] ,GPIO direction 10 bit" "Input,Output" bitfld.long 0x04 9. " [9] ,GPIO direction 9 bit" "Input,Output" bitfld.long 0x04 8. " [8] ,GPIO direction 8 bit" "Input,Output" newline bitfld.long 0x04 7. " [7] ,GPIO direction 7 bit" "Input,Output" bitfld.long 0x04 6. " [6] ,GPIO direction 6 bit" "Input,Output" bitfld.long 0x04 5. " [5] ,GPIO direction 5 bit" "Input,Output" bitfld.long 0x04 4. " [4] ,GPIO direction 4 bit" "Input,Output" newline bitfld.long 0x04 3. " [3] ,GPIO direction 3 bit" "Input,Output" bitfld.long 0x04 2. " [2] ,GPIO direction 2 bit" "Input,Output" bitfld.long 0x04 1. " [1] ,GPIO direction 1 bit" "Input,Output" bitfld.long 0x04 0. " [0] ,GPIO direction 0 bit" "Input,Output" rgroup.long 0x08++0x03 line.long 0x00 "PSR,GPIO Pad Status Register" bitfld.long 0x00 31. " PSR[31] ,GPIO pad status bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,GPIO pad status bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,GPIO pad status bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,GPIO pad status bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,GPIO pad status bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,GPIO pad status bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,GPIO pad status bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,GPIO pad status bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,GPIO pad status bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,GPIO pad status bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,GPIO pad status bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,GPIO pad status bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,GPIO pad status bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,GPIO pad status bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,GPIO pad status bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,GPIO pad status bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,GPIO pad status bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,GPIO pad status bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,GPIO pad status bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,GPIO pad status bit 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,GPIO pad status bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,GPIO pad status bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,GPIO pad status bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,GPIO pad status bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,GPIO pad status bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,GPIO pad status bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,GPIO pad status bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,GPIO pad status bit 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,GPIO pad status bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,GPIO pad status bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,GPIO pad status bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,GPIO pad status bit 0" "Low,High" group.long 0x0C++0x13 line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1" bitfld.long 0x00 30.--31. " ICR[15] ,Controls the active condition of the interrupt function for GPIO interrupt 15" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 28.--29. " [14] ,Controls the active condition of the interrupt function for GPIO interrupt 14" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 26.--27. " [13] ,Controls the active condition of the interrupt function for GPIO interrupt 13" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 24.--25. " [12] ,Controls the active condition of the interrupt function for GPIO interrupt 12" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 22.--23. " [11] ,Controls the active condition of the interrupt function for GPIO interrupt 11" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 20.--21. " [10] ,Controls the active condition of the interrupt function for GPIO interrupt 10" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 18.--19. " [9] ,Controls the active condition of the interrupt function for GPIO interrupt 9" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 16.--17. " [8] ,Controls the active condition of the interrupt function for GPIO interrupt 8" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 14.--15. " [7] ,Controls the active condition of the interrupt function for GPIO interrupt 7" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 12.--13. " [6] ,Controls the active condition of the interrupt function for GPIO interrupt 6" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 10.--11. " [5] ,Controls the active condition of the interrupt function for GPIO interrupt 5" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 8.--9. " [4] ,Controls the active condition of the interrupt function for GPIO interrupt 4" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x00 6.--7. " [3] ,Controls the active condition of the interrupt function for GPIO interrupt 3" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 4.--5. " [2] ,Controls the active condition of the interrupt function for GPIO interrupt 2" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 2.--3. " [1] ,Controls the active condition of the interrupt function for GPIO interrupt 1" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x00 0.--1. " [0] ,Controls the active condition of the interrupt function for GPIO interrupt 0" "Low-level,High-level,Rising-edge,Falling-edge" line.long 0x04 "ICR2,GPIO Interrupt Configuration Register 2" bitfld.long 0x04 30.--31. " [31] ,Controls the active condition of the interrupt function for GPIO interrupt 31" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 28.--29. " [30] ,Controls the active condition of the interrupt function for GPIO interrupt 30" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 26.--27. " [29] ,Controls the active condition of the interrupt function for GPIO interrupt 29" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 24.--25. " [28] ,Controls the active condition of the interrupt function for GPIO interrupt 28" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 22.--23. " [27] ,Controls the active condition of the interrupt function for GPIO interrupt 27" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 20.--21. " [26] ,Controls the active condition of the interrupt function for GPIO interrupt 26" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 18.--19. " [25] ,Controls the active condition of the interrupt function for GPIO interrupt 25" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 16.--17. " [24] ,Controls the active condition of the interrupt function for GPIO interrupt 24" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 14.--15. " [23] ,Controls the active condition of the interrupt function for GPIO interrupt 23" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 12.--13. " [22] ,Controls the active condition of the interrupt function for GPIO interrupt 22" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 10.--11. " [21] ,Controls the active condition of the interrupt function for GPIO interrupt 21" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 8.--9. " [20] ,Controls the active condition of the interrupt function for GPIO interrupt 20" "Low-level,High-level,Rising-edge,Falling-edge" newline bitfld.long 0x04 6.--7. " [19] ,Controls the active condition of the interrupt function for GPIO interrupt 19" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 4.--5. " [18] ,Controls the active condition of the interrupt function for GPIO interrupt 18" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 2.--3. " [17] ,Controls the active condition of the interrupt function for GPIO interrupt 17" "Low-level,High-level,Rising-edge,Falling-edge" bitfld.long 0x04 0.--1. " [16] ,Controls the active condition of the interrupt function for GPIO interrupt 16" "Low-level,High-level,Rising-edge,Falling-edge" line.long 0x08 "IMR,GPIO Interrupt Mask Register" bitfld.long 0x08 31. " IMR[31] ,Interrupt 31 mask bit" "Disabled,Enabled" bitfld.long 0x08 30. " [30] ,Interrupt 30 mask bit" "Disabled,Enabled" bitfld.long 0x08 29. " [29] ,Interrupt 29 mask bit" "Disabled,Enabled" bitfld.long 0x08 28. " [28] ,Interrupt 28 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 27. " [27] ,Interrupt 27 mask bit" "Disabled,Enabled" bitfld.long 0x08 26. " [26] ,Interrupt 26 mask bit" "Disabled,Enabled" bitfld.long 0x08 25. " [25] ,Interrupt 25 mask bit" "Disabled,Enabled" bitfld.long 0x08 24. " [24] ,Interrupt 24 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 23. " [23] ,Interrupt 23 mask bit" "Disabled,Enabled" bitfld.long 0x08 22. " [22] ,Interrupt 22 mask bit" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Interrupt 21 mask bit" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Interrupt 20 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 19. " [19] ,Interrupt 19 mask bit" "Disabled,Enabled" bitfld.long 0x08 18. " [18] ,Interrupt 18 mask bit" "Disabled,Enabled" bitfld.long 0x08 17. " [17] ,Interrupt 17 mask bit" "Disabled,Enabled" bitfld.long 0x08 16. " [16] ,Interrupt 16 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 15. " [15] ,Interrupt 15 mask bit" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Interrupt 14 mask bit" "Disabled,Enabled" bitfld.long 0x08 13. " [13] ,Interrupt 13 mask bit" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Interrupt 12 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 11. " [11] ,Interrupt 11 mask bit" "Disabled,Enabled" bitfld.long 0x08 10. " [10] ,Interrupt 10 mask bit" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Interrupt 9 mask bit" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Interrupt 8 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Interrupt 7 mask bit" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Interrupt 6 mask bit" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Interrupt 5 mask bit" "Disabled,Enabled" bitfld.long 0x08 4. " [4] ,Interrupt 4 mask bit" "Disabled,Enabled" newline bitfld.long 0x08 3. " [3] ,Interrupt 3 mask bit" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Interrupt 2 mask bit" "Disabled,Enabled" bitfld.long 0x08 1. " [1] ,Interrupt 1 mask bit" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Interrupt 0 mask bit" "Disabled,Enabled" line.long 0x0C "ISR,GPIO Interrupt Status Register" eventfld.long 0x0C 31. " ISR[31] ,Interrupt 31 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 30. " [30] ,Interrupt 30 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 29. " [29] ,Interrupt 29 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 28. " [28] ,Interrupt 28 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 27. " [27] ,Interrupt 27 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 26. " [26] ,Interrupt 26 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 25. " [25] ,Interrupt 25 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 24. " [24] ,Interrupt 24 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 23. " [23] ,Interrupt 23 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 22. " [22] ,Interrupt 22 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 21. " [21] ,Interrupt 21 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 20. " [20] ,Interrupt 20 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 19. " [19] ,Interrupt 19 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 18. " [18] ,Interrupt 18 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 17. " [17] ,Interrupt 17 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 16. " [16] ,Interrupt 16 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 15. " [15] ,Interrupt 15 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 14. " [14] ,Interrupt 14 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 13. " [13] ,Interrupt 13 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 12. " [12] ,Interrupt 12 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 11. " [11] ,Interrupt 11 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 10. " [10] ,Interrupt 10 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 9. " [9] ,Interrupt 9 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 8. " [8] ,Interrupt 8 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 7. " [7] ,Interrupt 7 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 6. " [6] ,Interrupt 6 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 5. " [5] ,Interrupt 5 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 4. " [4] ,Interrupt 4 status bit" "No interrupt,Interrupt" newline eventfld.long 0x0C 3. " [3] ,Interrupt 3 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 2. " [2] ,Interrupt 2 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 1. " [1] ,Interrupt 1 status bit" "No interrupt,Interrupt" eventfld.long 0x0C 0. " [0] ,Interrupt 0 status bit" "No interrupt,Interrupt" line.long 0x10 "EDGE_SEL,GPIO Edge Select Register" bitfld.long 0x10 31. " GPIO_EDGE_SEL[31] ,Edge select bit 31" "31 setting,Any edge" bitfld.long 0x10 30. " [30] ,Edge select bit 30" "30 setting,Any edge" bitfld.long 0x10 29. " [29] ,Edge select bit 29" "29 setting,Any edge" bitfld.long 0x10 28. " [28] ,Edge select bit 28" "28 setting,Any edge" newline bitfld.long 0x10 27. " [27] ,Edge select bit 27" "27 setting,Any edge" bitfld.long 0x10 26. " [26] ,Edge select bit 26" "26 setting,Any edge" bitfld.long 0x10 25. " [25] ,Edge select bit 25" "25 setting,Any edge" bitfld.long 0x10 24. " [24] ,Edge select bit 24" "24 setting,Any edge" newline bitfld.long 0x10 23. " [23] ,Edge select bit 23" "23 setting,Any edge" bitfld.long 0x10 22. " [22] ,Edge select bit 22" "22 setting,Any edge" bitfld.long 0x10 21. " [21] ,Edge select bit 21" "21 setting,Any edge" bitfld.long 0x10 20. " [20] ,Edge select bit 20" "20 setting,Any edge" newline bitfld.long 0x10 19. " [19] ,Edge select bit 19" "19 setting,Any edge" bitfld.long 0x10 18. " [18] ,Edge select bit 18" "18 setting,Any edge" bitfld.long 0x10 17. " [17] ,Edge select bit 17" "17 setting,Any edge" bitfld.long 0x10 16. " [16] ,Edge select bit 16" "16 setting,Any edge" newline bitfld.long 0x10 15. " [15] ,Edge select bit 15" "15 setting,Any edge" bitfld.long 0x10 14. " [14] ,Edge select bit 14" "14 setting,Any edge" bitfld.long 0x10 13. " [13] ,Edge select bit 13" "13 setting,Any edge" bitfld.long 0x10 12. " [12] ,Edge select bit 12" "12 setting,Any edge" newline bitfld.long 0x10 11. " [11] ,Edge select bit 11" "11 setting,Any edge" bitfld.long 0x10 10. " [10] ,Edge select bit 10" "10 setting,Any edge" bitfld.long 0x10 9. " [9] ,Edge select bit 9" "9 setting,Any edge" bitfld.long 0x10 8. " [8] ,Edge select bit 8" "8 setting,Any edge" newline bitfld.long 0x10 7. " [7] ,Edge select bit 7" "7 setting,Any edge" bitfld.long 0x10 6. " [6] ,Edge select bit 6" "6 setting,Any edge" bitfld.long 0x10 5. " [5] ,Edge select bit 5" "5 setting,Any edge" bitfld.long 0x10 4. " [4] ,Edge select bit 4" "4 setting,Any edge" newline bitfld.long 0x10 3. " [3] ,Edge select bit 3" "3 setting,Any edge" bitfld.long 0x10 2. " [2] ,Edge select bit 2" "2 setting,Any edge" bitfld.long 0x10 1. " [1] ,Edge select bit 1" "1 setting,Any edge" bitfld.long 0x10 0. " [0] ,Edge select bit 0" "0 setting,Any edge" wgroup.long 0x84++0x0B line.long 0x00 "DR_SET,GPIO Data Register SET Register" bitfld.long 0x00 31. " DR_SET[31] ,Data bit 31 set" "Not set,Set" bitfld.long 0x00 30. " [30] ,Data bit 30 set" "Not set,Set" bitfld.long 0x00 29. " [29] ,Data bit 29 set" "Not set,Set" bitfld.long 0x00 28. " [28] ,Data bit 28 set" "Not set,Set" newline bitfld.long 0x00 27. " [27] ,Data bit 27 set" "Not set,Set" bitfld.long 0x00 26. " [26] ,Data bit 26 set" "Not set,Set" bitfld.long 0x00 25. " [25] ,Data bit 25 set" "Not set,Set" bitfld.long 0x00 24. " [24] ,Data bit 24 set" "Not set,Set" newline bitfld.long 0x00 23. " [23] ,Data bit 23 set" "Not set,Set" bitfld.long 0x00 22. " [22] ,Data bit 22 set" "Not set,Set" bitfld.long 0x00 21. " [21] ,Data bit 21 set" "Not set,Set" bitfld.long 0x00 20. " [20] ,Data bit 20 set" "Not set,Set" newline bitfld.long 0x00 19. " [19] ,Data bit 19 set" "Not set,Set" bitfld.long 0x00 18. " [18] ,Data bit 18 set" "Not set,Set" bitfld.long 0x00 17. " [17] ,Data bit 17 set" "Not set,Set" bitfld.long 0x00 16. " [16] ,Data bit 16 set" "Not set,Set" newline bitfld.long 0x00 15. " [15] ,Data bit 15 set" "Not set,Set" bitfld.long 0x00 14. " [14] ,Data bit 14 set" "Not set,Set" bitfld.long 0x00 13. " [13] ,Data bit 13 set" "Not set,Set" bitfld.long 0x00 12. " [12] ,Data bit 12 set" "Not set,Set" newline bitfld.long 0x00 11. " [11] ,Data bit 11 set" "Not set,Set" bitfld.long 0x00 10. " [10] ,Data bit 10 set" "Not set,Set" bitfld.long 0x00 9. " [9] ,Data bit 9 set" "Not set,Set" bitfld.long 0x00 8. " [8] ,Data bit 8 set" "Not set,Set" newline bitfld.long 0x00 7. " [7] ,Data bit 7 set" "Not set,Set" bitfld.long 0x00 6. " [6] ,Data bit 6 set" "Not set,Set" bitfld.long 0x00 5. " [5] ,Data bit 5 set" "Not set,Set" bitfld.long 0x00 4. " [4] ,Data bit 4 set" "Not set,Set" newline bitfld.long 0x00 3. " [3] ,Data bit 3 set" "Not set,Set" bitfld.long 0x00 2. " [2] ,Data bit 2 set" "Not set,Set" bitfld.long 0x00 1. " [1] ,Data bit 1 set" "Not set,Set" bitfld.long 0x00 0. " [0] ,Data bit 0 set" "Not set,Set" line.long 0x04 "DR_CLEAR,GPIO Data Register CLEAR Register" bitfld.long 0x04 31. " DR_CLEAR[31] ,Data bit 31 clear" "No effect,Clear" bitfld.long 0x04 30. " [30] ,Data bit 30 clear" "No effect,Clear" bitfld.long 0x04 29. " [29] ,Data bit 29 clear" "No effect,Clear" bitfld.long 0x04 28. " [28] ,Data bit 28 clear" "No effect,Clear" newline bitfld.long 0x04 27. " [27] ,Data bit 27 clear" "No effect,Clear" bitfld.long 0x04 26. " [26] ,Data bit 26 clear" "No effect,Clear" bitfld.long 0x04 25. " [25] ,Data bit 25 clear" "No effect,Clear" bitfld.long 0x04 24. " [24] ,Data bit 24 clear" "No effect,Clear" newline bitfld.long 0x04 23. " [23] ,Data bit 23 clear" "No effect,Clear" bitfld.long 0x04 22. " [22] ,Data bit 22 clear" "No effect,Clear" bitfld.long 0x04 21. " [21] ,Data bit 21 clear" "No effect,Clear" bitfld.long 0x04 20. " [20] ,Data bit 20 clear" "No effect,Clear" newline bitfld.long 0x04 19. " [19] ,Data bit 19 clear" "No effect,Clear" bitfld.long 0x04 18. " [18] ,Data bit 18 clear" "No effect,Clear" bitfld.long 0x04 17. " [17] ,Data bit 17 clear" "No effect,Clear" bitfld.long 0x04 16. " [16] ,Data bit 16 clear" "No effect,Clear" newline bitfld.long 0x04 15. " [15] ,Data bit 15 clear" "No effect,Clear" bitfld.long 0x04 14. " [14] ,Data bit 14 clear" "No effect,Clear" bitfld.long 0x04 13. " [13] ,Data bit 13 clear" "No effect,Clear" bitfld.long 0x04 12. " [12] ,Data bit 12 clear" "No effect,Clear" newline bitfld.long 0x04 11. " [11] ,Data bit 11 clear" "No effect,Clear" bitfld.long 0x04 10. " [10] ,Data bit 10 clear" "No effect,Clear" bitfld.long 0x04 9. " [9] ,Data bit 9 clear" "No effect,Clear" bitfld.long 0x04 8. " [8] ,Data bit 8 clear" "No effect,Clear" newline bitfld.long 0x04 7. " [7] ,Data bit 7 clear" "No effect,Clear" bitfld.long 0x04 6. " [6] ,Data bit 6 clear" "No effect,Clear" bitfld.long 0x04 5. " [5] ,Data bit 5 clear" "No effect,Clear" bitfld.long 0x04 4. " [4] ,Data bit 4 clear" "No effect,Clear" newline bitfld.long 0x04 3. " [3] ,Data bit 3 clear" "No effect,Clear" bitfld.long 0x04 2. " [2] ,Data bit 2 clear" "No effect,Clear" bitfld.long 0x04 1. " [1] ,Data bit 1 clear" "No effect,Clear" bitfld.long 0x04 0. " [0] ,Data bit 0 clear" "No effect,Clear" line.long 0x08 "DR_TOGGLE,GPIO Data Register TOGGLE Register" bitfld.long 0x08 31. " DR_TOGGLE[31] ,Data bit 31 toggle" "Not toggled,Toggled" bitfld.long 0x08 30. " [30] ,Data bit 30 toggle" "No effect,Clear" bitfld.long 0x08 29. " [29] ,Data bit 29 toggle" "Not toggled,Toggled" bitfld.long 0x08 28. " [28] ,Data bit 28 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 27. " [27] ,Data bit 27 toggle" "Not toggled,Toggled" bitfld.long 0x08 26. " [26] ,Data bit 26 toggle" "Not toggled,Toggled" bitfld.long 0x08 25. " [25] ,Data bit 25 toggle" "Not toggled,Toggled" bitfld.long 0x08 24. " [24] ,Data bit 24 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 23. " [23] ,Data bit 23 toggle" "Not toggled,Toggled" bitfld.long 0x08 22. " [22] ,Data bit 22 toggle" "Not toggled,Toggled" bitfld.long 0x08 21. " [21] ,Data bit 21 toggle" "Not toggled,Toggled" bitfld.long 0x08 20. " [20] ,Data bit 20 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 19. " [19] ,Data bit 19 toggle" "Not toggled,Toggled" bitfld.long 0x08 18. " [18] ,Data bit 18 toggle" "Not toggled,Toggled" bitfld.long 0x08 17. " [17] ,Data bit 17 toggle" "Not toggled,Toggled" bitfld.long 0x08 16. " [16] ,Data bit 16 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 15. " [15] ,Data bit 15 toggle" "Not toggled,Toggled" bitfld.long 0x08 14. " [14] ,Data bit 14 toggle" "Not toggled,Toggled" bitfld.long 0x08 13. " [13] ,Data bit 13 toggle" "Not toggled,Toggled" bitfld.long 0x08 12. " [12] ,Data bit 12 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 11. " [11] ,Data bit 11 toggle" "Not toggled,Toggled" bitfld.long 0x08 10. " [10] ,Data bit 10 toggle" "Not toggled,Toggled" bitfld.long 0x08 9. " [9] ,Data bit 9 toggle" "Not toggled,Toggled" bitfld.long 0x08 8. " [8] ,Data bit 8 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 7. " [7] ,Data bit 7 toggle" "Not toggled,Toggled" bitfld.long 0x08 6. " [6] ,Data bit 6 toggle" "Not toggled,Toggled" bitfld.long 0x08 5. " [5] ,Data bit 5 toggle" "Not toggled,Toggled" bitfld.long 0x08 4. " [4] ,Data bit 4 toggle" "Not toggled,Toggled" newline bitfld.long 0x08 3. " [3] ,Data bit 3 toggle" "Not toggled,Toggled" bitfld.long 0x08 2. " [2] ,Data bit 2 toggle" "Not toggled,Toggled" bitfld.long 0x08 1. " [1] ,Data bit 1 toggle" "Not toggled,Toggled" bitfld.long 0x08 0. " [0] ,Data bit 0 toggle" "Not toggled,Toggled" width 0x0B tree.end tree.open "CSR (HSIO Control and Status Registers)" tree "MISC CRR" base ad:0x5F160000 width 12. group.long 0x00++0x03 line.long 0x00 "MISC_CTRL0,Miscellaneous Control Register 0" bitfld.long 0x00 28. " CLKREQN_IN_OVERRIDE_1 ,CLKREQN_IN_OVERRIDE_1" "0,1" bitfld.long 0x00 26. " CLKREQN_IN_1 ,CLKREQN_IN_1" "0,1" bitfld.long 0x00 24. " CLKREQN_OUT_OVERRIDE_1 ,CLKREQN_OUT_OVERRIDE_1" "0,1" bitfld.long 0x00 22. " CLKREQN_OUT_1 ,CLKREQN_OUT_1" "0,1" newline bitfld.long 0x00 12. " PHY_X1_EPCS_SEL ,PHY_X1_EPCS_SEL will be used for ECO for PCIe controller bug fix" "0,1" bitfld.long 0x00 11. " FAST_INIT ,FAST_INIT" "0,1" bitfld.long 0x00 3.--4. " IOB_A_0_M1M0 ,IOB_A_0_M1M0" "0,1,3,4" bitfld.long 0x00 2. " IOB_A_0_TXOE ,IOB_A_0_TXOE" "0,1" newline bitfld.long 0x00 1. " IOB_TXENA ,IOB_TXENA" "0,1" bitfld.long 0x00 0. " IOB_RXENA ,IOB_RXENA" "0,1" hgroup.long 0x04++0x03 hide.long 0x00 "MISC_STTS0,Miscellaneous Status Register 0" width 0x0B tree.end tree "PCIe CRR" base ad:0x5F140000 width 14. group.long 0x00++0x0B line.long 0x00 "PCIEX1_CTRL0,PCIe 1 Control Register 0" bitfld.long 0x00 24.--27. " DEVICE_TYPE ,Device type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " PS_REVISION_ID ,PS_REVISION_ID" hexmask.long.word 0x00 0.--15. 1. " PS_DEVICE_ID ,PS_DEVICE_ID" line.long 0x04 "PCIEX1_CTRL1,PCIe 1 Control Register 1" bitfld.long 0x04 14. " CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN ,CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN" "Disabled,Enabled" bitfld.long 0x04 11. " PS_SAMPLING_VALID ,PS_SAMPLING_VALID" "Not valid,Valid" bitfld.long 0x04 10. " POR_SAMPLING_VALID ,POR_SAMPLING_VALID" "Not valid,Valid" newline bitfld.long 0x04 6.--9. " PS_CFG_PCIE_MAX_LINK_SPEED ,PS_CFG_PCIE_MAX_LINK_SPEED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--5. " PS_CFG_PCIE_MAX_LINK_WIDTH ,PS_CFG_PCIE_MAX_LINK_WIDTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "PCIEX1_CTRL2,PCIe 1 Control Register 2" bitfld.long 0x08 26. " GPR_CRS_CLEAR ,GPR_CRS_CLEAR" "Not cleared,Cleared" bitfld.long 0x08 23. " POWER_UP_RST_N ,POWER_UP_RST_N" "0,1" bitfld.long 0x08 22. " PERST_N ,PERST_N" "0,1" newline bitfld.long 0x08 21. " BUTTON_RST_N ,BUTTON_RST_N" "0,1" bitfld.long 0x08 17.--19. " DIAG_CTRL_BUS ,DIAG_CTRL_BUS" "0,1,2,3,4,5,6,7" bitfld.long 0x08 13.--16. " DIAG_STATUS_BUS_SELECT ,DIAG_STATUS_BUS_SELECT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 11. " APP_XFER_PENDING ,APP_XFER_PENDING" "Not pending,Pending" bitfld.long 0x08 10. " APP_CLK_PM_EN ,APP_CLK_PM_EN" "Disabled,Enabled" bitfld.long 0x08 9. " APPS_PM_XMT_TURNOFF ,APPS_PM_XMT_TURNOFF" "On,Off" newline bitfld.long 0x08 8. " APPS_PM_XMT_PME ,APPS_PM_XMT_PME" "0,1" bitfld.long 0x08 7. " APP_REQ_EXIT_L1 ,APP_REQ_EXIT_L1" "Not exited,Exited" bitfld.long 0x08 6. " APP_REQ_ENTR_L1 ,APP_REQ_ENTR_L1" "Not entered,Entered" newline bitfld.long 0x08 5. " APP_READY_ENTR_L23 ,APP_READY_ENTR_L23" "0,1" bitfld.long 0x08 4. " APP_LTSSM_ENABLE ,APP_LTSSM_ENABLE" "Disabled,Enabled" bitfld.long 0x08 3. " APP_INIT_RST ,APP_INIT_RST" "0,1" newline bitfld.long 0x08 2. " APP_CLK_REQ_N ,APP_CLK_REQ_N" "0,1" bitfld.long 0x08 0.--1. " SYS_INT ,SYS_INT" "0,1,2,3" rgroup.long 0x0C++0x0B line.long 0x00 "PCIEX1_STTS0,PCIe 1 Status Register 0" bitfld.long 0x00 22. " CPL_CRS_RCVD ,CPL_CRS_RCVD" "Not received,Received" bitfld.long 0x00 19. " PM_REQ_CORE_RST ,PM_REQ_CORE_RST" "No reset,Reset" bitfld.long 0x00 18. " DBI_XFER_PENDING ,DBI_XFER_PENDING" "Not pending,Pending" newline bitfld.long 0x00 17. " RADM_XFER_PENDING ,RADM_XFER_PENDING" "Not pending,Pending" bitfld.long 0x00 16. " EDMA_XFER_PENDING ,EDMA_XFER_PENDING" "Not pending,Pending" bitfld.long 0x00 15. " BRDG_SLV_XFER_PENDING ,BRDG_SLV_XFER_PENDING" "Not pending,Pending" newline bitfld.long 0x00 14. " PM_LINKST_L2_EXIT ,PM_LINKST_L2_EXIT" "Not exited,Exited" bitfld.long 0x00 13. " PM_LINKST_IN_L2 ,PM_LINKST_IN_L2" "0,1" bitfld.long 0x00 12. " PM_LINKST_IN_L1 ,PM_LINKST_IN_L1" "0,1" newline bitfld.long 0x00 11. " PM_LINKST_IN_L1SUB ,PM_LINKST_IN_L1SUB" "0,1" bitfld.long 0x00 10. " PM_LINKST_IN_L0S ,PM_LINKST_IN_L0S" "0,1" bitfld.long 0x00 7.--9. " PM_DSTATE ,PM_DSTATE" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 6. " CFG_L1SUB_EN ,CFG_L1SUB_EN" "Disabled,Enabled" bitfld.long 0x00 0.--5. " SMLH_LTSSM_STATE ,SMLH_LTSSM_STATE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "PCIEX1_STTS1,PCIe 1 Status Register 1" hexmask.long.word 0x04 0.--15. 1. " CXPL_DEBUG_INFO_EI ,CXPL_DEBUG_INFO_EI" line.long 0x08 "PCIEX1_STTS2,PCIe 1 Status Register 2" width 0x0B tree.end tree "PHY CRR" base ad:0x5F120000 width 13. group.long 0x00++0x03 line.long 0x00 "PHYX1_CTRL0,PHYX1 Control Register 0" bitfld.long 0x00 25. " PIPE_RSTN_OVERRIDE_0 ,PIPE_RSTN_OVERRIDE_0" "0,1" bitfld.long 0x00 24. " PIPE_RSTN_0 ,PIPE_RSTN_0" "0,1" bitfld.long 0x00 21. " EI4_CHANGE_REQ_0 ,EI4_CHANGE_REQ_0" "0,1" newline bitfld.long 0x00 17.--20. " PHY_MODE ,PHY_MODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10. " AIDDQ_0 ,AIDDQ_0" "0,1" bitfld.long 0x00 0. " APB_RSTN ,APB_RSTN" "0,1" rgroup.long 0x04++0x03 line.long 0x00 "PHYX1_STTS0,PHYX1 Status Register 0" bitfld.long 0x00 18. " EPCS_READY ,EPCS_READY" "Not ready,Ready" bitfld.long 0x00 16. " EI4_CHANGE_ACK ,EI4_CHANGE_ACK" "Not ready,Ready" hexmask.long.byte 0x00 0.--7. 1. " TEST_OUT ,TEST_OUT" width 0x0B tree.end tree.end tree.end newline